// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from esp32p4.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Espressif

//go:build esp && esp32p4

// 32-bit RISC-V MCU
//
//	Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
package esp

import (
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "ESP32-P4"
	CPU          = "RV32IMAFC"
	FPUPresent   = true
	NVICPrioBits = 0
)

// Interrupt numbers.
const (
	// Low-power Watchdog Timer
	IRQ_LP_WDT = 1

	// Low-power Timer
	IRQ_LP_TIMER0 = 2

	// Low-power Timer
	IRQ_LP_TIMER1 = 3

	// PMU Peripheral
	IRQ_PMU0 = 6

	// PMU Peripheral
	IRQ_PMU1 = 7

	// LP_ANA_PERI Peripheral
	IRQ_LP_ANA = 8

	// Low-power Analog to Digital Converter
	IRQ_LP_ADC = 9

	// Low-power General Purpose Input/Output
	IRQ_LP_GPIO = 10

	// Low-power I2C (Inter-Integrated Circuit) Controller 0
	IRQ_LP_I2C0 = 11

	// Low-power I2S (Inter-IC Sound) Controller 0
	IRQ_LP_I2S0 = 12

	// LP_TOUCH Peripheral
	IRQ_LP_TOUCH = 14

	// Low-power Temperature Sensor
	IRQ_LP_TSENS = 15

	// Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller
	IRQ_LP_UART = 16

	// LP_SYS Peripheral
	IRQ_LP_SYS = 19

	// LP_HUK Peripheral
	IRQ_LP_HUK = 20

	// Full-speed USB Serial/JTAG Controller
	IRQ_USB_DEVICE = 22

	// DMA (Direct Memory Access) Controller
	IRQ_DMA = 24

	// SPI (Serial Peripheral Interface) Controller 2
	IRQ_SPI2 = 25

	// SPI (Serial Peripheral Interface) Controller 3
	IRQ_SPI3 = 26

	// I2S (Inter-IC Sound) Controller 0
	IRQ_I2S0 = 27

	// I2S (Inter-IC Sound) Controller 1
	IRQ_I2S1 = 28

	// I2S (Inter-IC Sound) Controller 2
	IRQ_I2S2 = 29

	// Universal Host Controller Interface 0
	IRQ_UHCI0 = 30

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 0
	IRQ_UART0 = 31

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 1
	IRQ_UART1 = 32

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 2
	IRQ_UART2 = 33

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 3
	IRQ_UART3 = 34

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 4
	IRQ_UART4 = 35

	// Motor Control Pulse-Width Modulation 0
	IRQ_PWM0 = 38

	// Motor Control Pulse-Width Modulation 1
	IRQ_PWM1 = 39

	// Two-Wire Automotive Interface
	IRQ_TWAI0 = 40

	// Two-Wire Automotive Interface
	IRQ_TWAI1 = 41

	// Two-Wire Automotive Interface
	IRQ_TWAI2 = 42

	// Remote Control
	IRQ_RMT = 43

	// I2C (Inter-Integrated Circuit) Controller 0
	IRQ_I2C0 = 44

	// I2C (Inter-Integrated Circuit) Controller 1
	IRQ_I2C1 = 45

	// Timer Group 0
	IRQ_TG0_T0 = 46

	// Timer Group 0
	IRQ_TG0_T1 = 47

	// Timer Group 0
	IRQ_TG0_WDT = 48

	// Timer Group 1
	IRQ_TG1_T0 = 49

	// Timer Group 1
	IRQ_TG1_T1 = 50

	// Timer Group 1
	IRQ_TG1_WDT = 51

	// LED Control PWM (Pulse Width Modulation)
	IRQ_LEDC = 52

	// System Timer
	IRQ_SYSTIMER_TARGET0 = 53

	// System Timer
	IRQ_SYSTIMER_TARGET1 = 54

	// System Timer
	IRQ_SYSTIMER_TARGET2 = 55

	// AHB_DMA Peripheral
	IRQ_AHB_PDMA_IN_CH0 = 56

	// AHB_DMA Peripheral
	IRQ_AHB_PDMA_IN_CH1 = 57

	// AHB_DMA Peripheral
	IRQ_AHB_PDMA_IN_CH2 = 58

	// AHB_DMA Peripheral
	IRQ_AHB_PDMA_OUT_CH0 = 59

	// AHB_DMA Peripheral
	IRQ_AHB_PDMA_OUT_CH1 = 60

	// AHB_DMA Peripheral
	IRQ_AHB_PDMA_OUT_CH2 = 61

	// AHB_DMA Peripheral
	IRQ_AXI_PDMA_IN_CH0 = 62

	// AHB_DMA Peripheral
	IRQ_AXI_PDMA_IN_CH1 = 63

	// AHB_DMA Peripheral
	IRQ_AXI_PDMA_IN_CH2 = 64

	// AHB_DMA Peripheral
	IRQ_AXI_PDMA_OUT_CH0 = 65

	// AHB_DMA Peripheral
	IRQ_AXI_PDMA_OUT_CH1 = 66

	// AHB_DMA Peripheral
	IRQ_AXI_PDMA_OUT_CH2 = 67

	// RSA (Rivest Shamir Adleman) Accelerator
	IRQ_RSA = 68

	// AES (Advanced Encryption Standard) Accelerator
	IRQ_AES = 69

	// SHA (Secure Hash Algorithm) Accelerator
	IRQ_SHA = 70

	// ECC (ECC Hardware Accelerator)
	IRQ_ECC = 71

	// General Purpose Input/Output
	IRQ_GPIO_INT0 = 74

	// General Purpose Input/Output
	IRQ_GPIO_INT1 = 75

	// General Purpose Input/Output
	IRQ_GPIO_INT2 = 76

	// General Purpose Input/Output
	IRQ_GPIO_INT3 = 77

	// General Purpose Input/Output
	IRQ_GPIO_PAD_COMP = 78

	// CACHE Peripheral
	IRQ_CACHE = 83

	// MIPI Camera Interface Bridge
	IRQ_CSI_BRIDGE = 85

	// MIPI Camera Interface Bridge
	IRQ_DSI_BRIDGE = 86

	// MIPI Camera Interface Host
	IRQ_CSI = 87

	// MIPI Display Interface Host
	IRQ_DSI = 88

	// JPEG Codec
	IRQ_JPEG = 95

	// PPA Peripheral
	IRQ_PPA = 96

	// ISP Peripheral
	IRQ_ISP = 100

	// I3C Controller (Master)
	IRQ_I3C = 101

	// I3C Controller (Slave)
	IRQ_I3C_SLV = 102

	// High-Power System
	IRQ_HP_SYS = 110

	// Pulse Count Controller
	IRQ_PCNT = 111

	// PAU Peripheral
	IRQ_PAU = 112

	// Parallel IO Controller
	IRQ_PARLIO_RX = 113

	// Parallel IO Controller
	IRQ_PARLIO_TX = 114

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_OUT_CH0 = 115

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_OUT_CH1 = 116

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_OUT_CH2 = 117

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_OUT_CH3 = 118

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_OUT_CH4 = 119

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_IN_CH0 = 120

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_IN_CH1 = 121

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_IN_CH2 = 122

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_IN_CH3 = 123

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_IN_CH4 = 124

	// H264 Encoder (DMA)
	IRQ_H264_DMA2D_IN_CH5 = 125

	// H264 Encoder (Core)
	IRQ_H264_REG = 126

	// Debug Assist
	IRQ_ASSIST_DEBUG = 127

	// Highest interrupt number on this device.
	IRQ_max = 127
)

// Pseudo function call that is replaced by the compiler with the actual
// functions registered through interrupt.New.
//
//go:linkname callHandlers runtime/interrupt.callHandlers
func callHandlers(num int)
func HandleInterrupt(num int) {
	switch num {
	case IRQ_LP_WDT:
		callHandlers(IRQ_LP_WDT)
	case IRQ_LP_TIMER0:
		callHandlers(IRQ_LP_TIMER0)
	case IRQ_LP_TIMER1:
		callHandlers(IRQ_LP_TIMER1)
	case IRQ_PMU0:
		callHandlers(IRQ_PMU0)
	case IRQ_PMU1:
		callHandlers(IRQ_PMU1)
	case IRQ_LP_ANA:
		callHandlers(IRQ_LP_ANA)
	case IRQ_LP_ADC:
		callHandlers(IRQ_LP_ADC)
	case IRQ_LP_GPIO:
		callHandlers(IRQ_LP_GPIO)
	case IRQ_LP_I2C0:
		callHandlers(IRQ_LP_I2C0)
	case IRQ_LP_I2S0:
		callHandlers(IRQ_LP_I2S0)
	case IRQ_LP_TOUCH:
		callHandlers(IRQ_LP_TOUCH)
	case IRQ_LP_TSENS:
		callHandlers(IRQ_LP_TSENS)
	case IRQ_LP_UART:
		callHandlers(IRQ_LP_UART)
	case IRQ_LP_SYS:
		callHandlers(IRQ_LP_SYS)
	case IRQ_LP_HUK:
		callHandlers(IRQ_LP_HUK)
	case IRQ_USB_DEVICE:
		callHandlers(IRQ_USB_DEVICE)
	case IRQ_DMA:
		callHandlers(IRQ_DMA)
	case IRQ_SPI2:
		callHandlers(IRQ_SPI2)
	case IRQ_SPI3:
		callHandlers(IRQ_SPI3)
	case IRQ_I2S0:
		callHandlers(IRQ_I2S0)
	case IRQ_I2S1:
		callHandlers(IRQ_I2S1)
	case IRQ_I2S2:
		callHandlers(IRQ_I2S2)
	case IRQ_UHCI0:
		callHandlers(IRQ_UHCI0)
	case IRQ_UART0:
		callHandlers(IRQ_UART0)
	case IRQ_UART1:
		callHandlers(IRQ_UART1)
	case IRQ_UART2:
		callHandlers(IRQ_UART2)
	case IRQ_UART3:
		callHandlers(IRQ_UART3)
	case IRQ_UART4:
		callHandlers(IRQ_UART4)
	case IRQ_PWM0:
		callHandlers(IRQ_PWM0)
	case IRQ_PWM1:
		callHandlers(IRQ_PWM1)
	case IRQ_TWAI0:
		callHandlers(IRQ_TWAI0)
	case IRQ_TWAI1:
		callHandlers(IRQ_TWAI1)
	case IRQ_TWAI2:
		callHandlers(IRQ_TWAI2)
	case IRQ_RMT:
		callHandlers(IRQ_RMT)
	case IRQ_I2C0:
		callHandlers(IRQ_I2C0)
	case IRQ_I2C1:
		callHandlers(IRQ_I2C1)
	case IRQ_TG0_T0:
		callHandlers(IRQ_TG0_T0)
	case IRQ_TG0_T1:
		callHandlers(IRQ_TG0_T1)
	case IRQ_TG0_WDT:
		callHandlers(IRQ_TG0_WDT)
	case IRQ_TG1_T0:
		callHandlers(IRQ_TG1_T0)
	case IRQ_TG1_T1:
		callHandlers(IRQ_TG1_T1)
	case IRQ_TG1_WDT:
		callHandlers(IRQ_TG1_WDT)
	case IRQ_LEDC:
		callHandlers(IRQ_LEDC)
	case IRQ_SYSTIMER_TARGET0:
		callHandlers(IRQ_SYSTIMER_TARGET0)
	case IRQ_SYSTIMER_TARGET1:
		callHandlers(IRQ_SYSTIMER_TARGET1)
	case IRQ_SYSTIMER_TARGET2:
		callHandlers(IRQ_SYSTIMER_TARGET2)
	case IRQ_AHB_PDMA_IN_CH0:
		callHandlers(IRQ_AHB_PDMA_IN_CH0)
	case IRQ_AHB_PDMA_IN_CH1:
		callHandlers(IRQ_AHB_PDMA_IN_CH1)
	case IRQ_AHB_PDMA_IN_CH2:
		callHandlers(IRQ_AHB_PDMA_IN_CH2)
	case IRQ_AHB_PDMA_OUT_CH0:
		callHandlers(IRQ_AHB_PDMA_OUT_CH0)
	case IRQ_AHB_PDMA_OUT_CH1:
		callHandlers(IRQ_AHB_PDMA_OUT_CH1)
	case IRQ_AHB_PDMA_OUT_CH2:
		callHandlers(IRQ_AHB_PDMA_OUT_CH2)
	case IRQ_AXI_PDMA_IN_CH0:
		callHandlers(IRQ_AXI_PDMA_IN_CH0)
	case IRQ_AXI_PDMA_IN_CH1:
		callHandlers(IRQ_AXI_PDMA_IN_CH1)
	case IRQ_AXI_PDMA_IN_CH2:
		callHandlers(IRQ_AXI_PDMA_IN_CH2)
	case IRQ_AXI_PDMA_OUT_CH0:
		callHandlers(IRQ_AXI_PDMA_OUT_CH0)
	case IRQ_AXI_PDMA_OUT_CH1:
		callHandlers(IRQ_AXI_PDMA_OUT_CH1)
	case IRQ_AXI_PDMA_OUT_CH2:
		callHandlers(IRQ_AXI_PDMA_OUT_CH2)
	case IRQ_RSA:
		callHandlers(IRQ_RSA)
	case IRQ_AES:
		callHandlers(IRQ_AES)
	case IRQ_SHA:
		callHandlers(IRQ_SHA)
	case IRQ_ECC:
		callHandlers(IRQ_ECC)
	case IRQ_GPIO_INT0:
		callHandlers(IRQ_GPIO_INT0)
	case IRQ_GPIO_INT1:
		callHandlers(IRQ_GPIO_INT1)
	case IRQ_GPIO_INT2:
		callHandlers(IRQ_GPIO_INT2)
	case IRQ_GPIO_INT3:
		callHandlers(IRQ_GPIO_INT3)
	case IRQ_GPIO_PAD_COMP:
		callHandlers(IRQ_GPIO_PAD_COMP)
	case IRQ_CACHE:
		callHandlers(IRQ_CACHE)
	case IRQ_CSI_BRIDGE:
		callHandlers(IRQ_CSI_BRIDGE)
	case IRQ_DSI_BRIDGE:
		callHandlers(IRQ_DSI_BRIDGE)
	case IRQ_CSI:
		callHandlers(IRQ_CSI)
	case IRQ_DSI:
		callHandlers(IRQ_DSI)
	case IRQ_JPEG:
		callHandlers(IRQ_JPEG)
	case IRQ_PPA:
		callHandlers(IRQ_PPA)
	case IRQ_ISP:
		callHandlers(IRQ_ISP)
	case IRQ_I3C:
		callHandlers(IRQ_I3C)
	case IRQ_I3C_SLV:
		callHandlers(IRQ_I3C_SLV)
	case IRQ_HP_SYS:
		callHandlers(IRQ_HP_SYS)
	case IRQ_PCNT:
		callHandlers(IRQ_PCNT)
	case IRQ_PAU:
		callHandlers(IRQ_PAU)
	case IRQ_PARLIO_RX:
		callHandlers(IRQ_PARLIO_RX)
	case IRQ_PARLIO_TX:
		callHandlers(IRQ_PARLIO_TX)
	case IRQ_H264_DMA2D_OUT_CH0:
		callHandlers(IRQ_H264_DMA2D_OUT_CH0)
	case IRQ_H264_DMA2D_OUT_CH1:
		callHandlers(IRQ_H264_DMA2D_OUT_CH1)
	case IRQ_H264_DMA2D_OUT_CH2:
		callHandlers(IRQ_H264_DMA2D_OUT_CH2)
	case IRQ_H264_DMA2D_OUT_CH3:
		callHandlers(IRQ_H264_DMA2D_OUT_CH3)
	case IRQ_H264_DMA2D_OUT_CH4:
		callHandlers(IRQ_H264_DMA2D_OUT_CH4)
	case IRQ_H264_DMA2D_IN_CH0:
		callHandlers(IRQ_H264_DMA2D_IN_CH0)
	case IRQ_H264_DMA2D_IN_CH1:
		callHandlers(IRQ_H264_DMA2D_IN_CH1)
	case IRQ_H264_DMA2D_IN_CH2:
		callHandlers(IRQ_H264_DMA2D_IN_CH2)
	case IRQ_H264_DMA2D_IN_CH3:
		callHandlers(IRQ_H264_DMA2D_IN_CH3)
	case IRQ_H264_DMA2D_IN_CH4:
		callHandlers(IRQ_H264_DMA2D_IN_CH4)
	case IRQ_H264_DMA2D_IN_CH5:
		callHandlers(IRQ_H264_DMA2D_IN_CH5)
	case IRQ_H264_REG:
		callHandlers(IRQ_H264_REG)
	case IRQ_ASSIST_DEBUG:
		callHandlers(IRQ_ASSIST_DEBUG)
	}
}

// Peripherals.
var (
	// ADC (Analog to Digital Converter)
	ADC = (*ADC_Type)(unsafe.Pointer(uintptr(0x500de000)))

	// AES (Advanced Encryption Standard) Accelerator
	AES = (*AES_Type)(unsafe.Pointer(uintptr(0x50090000)))

	// AHB_DMA Peripheral
	AHB_DMA = (*AHB_DMA_Type)(unsafe.Pointer(uintptr(0x50085000)))

	// LP_I2C_ANA_MST Peripheral
	LP_I2C_ANA_MST = (*ANA_I2C_MST_Type)(unsafe.Pointer(uintptr(0x50124000)))

	// Debug Assist
	ASSIST_DEBUG = (*ASSIST_DEBUG_Type)(unsafe.Pointer(uintptr(0x3ff06000)))

	// AXI_DMA Peripheral
	AXI_DMA = (*AXI_DMA_Type)(unsafe.Pointer(uintptr(0x5008a000)))

	// BITSCRAMBLER Peripheral
	BITSCRAMBLER = (*BITSCRAMBLER_Type)(unsafe.Pointer(uintptr(0x500a3000)))

	// CACHE Peripheral
	CACHE = (*CACHE_Type)(unsafe.Pointer(uintptr(0x3ff10000)))

	// Interrupt Controller (Core 0)
	INTERRUPT_CORE0 = (*CORE0_Type)(unsafe.Pointer(uintptr(0x500d6000)))

	// Interrupt Controller (Core 1)
	INTERRUPT_CORE1 = (*CORE1_Type)(unsafe.Pointer(uintptr(0x500d6800)))

	// MIPI Camera Interface Bridge
	MIPI_CSI_BRIDGE = (*CSI_BRIG_Type)(unsafe.Pointer(uintptr(0x5009f800)))

	// MIPI Camera Interface Host
	MIPI_CSI_HOST = (*CSI_HOST_Type)(unsafe.Pointer(uintptr(0x5009f000)))

	// DMA (Direct Memory Access) Controller
	DMA = (*DMAC_Type)(unsafe.Pointer(uintptr(0x50081000)))

	// Digital Signature
	DS = (*DS_Type)(unsafe.Pointer(uintptr(0x50094000)))

	// MIPI Camera Interface Bridge
	MIPI_DSI_BRIDGE = (*DSI_BRG_Type)(unsafe.Pointer(uintptr(0x500a0800)))

	// MIPI Display Interface Host
	MIPI_DSI_HOST = (*DSI_HOST_Type)(unsafe.Pointer(uintptr(0x500a0000)))

	// ECC (ECC Hardware Accelerator)
	ECC = (*ECC_Type)(unsafe.Pointer(uintptr(0x50093000)))

	// ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator
	ECDSA = (*ECDSA_Type)(unsafe.Pointer(uintptr(0x50096000)))

	// eFuse Controller
	EFUSE = (*EFUSE_Type)(unsafe.Pointer(uintptr(0x5012d000)))

	// General Purpose Input/Output
	GPIO = (*GPIO_Type)(unsafe.Pointer(uintptr(0x500e0000)))

	// Sigma-Delta Modulation
	GPIO_SD = (*GPIOSD_Type)(unsafe.Pointer(uintptr(0x500e0f00)))

	// H264 Encoder (Core)
	H264 = (*H264_Type)(unsafe.Pointer(uintptr(0x50084000)))

	// H264 Encoder (DMA)
	H264_DMA = (*H264_DMA_Type)(unsafe.Pointer(uintptr(0x500a7000)))

	// HMAC (Hash-based Message Authentication Code) Accelerator
	HMAC = (*HMAC_Type)(unsafe.Pointer(uintptr(0x50095000)))

	// High-Power System
	HP_SYS = (*HP_SYS_Type)(unsafe.Pointer(uintptr(0x500e5000)))

	// HP_SYS_CLKRST Peripheral
	HP_SYS_CLKRST = (*HP_SYS_CLKRST_Type)(unsafe.Pointer(uintptr(0x500e6000)))

	// LP_HUK Peripheral
	LP_HUK = (*HUK_Type)(unsafe.Pointer(uintptr(0x50114000)))

	// I2C (Inter-Integrated Circuit) Controller 0
	I2C0 = (*I2C_Type)(unsafe.Pointer(uintptr(0x500c4000)))

	// I2S (Inter-IC Sound) Controller 0
	I2S0 = (*I2S_Type)(unsafe.Pointer(uintptr(0x500c6000)))

	// I3C Controller (Master)
	I3C_MST = (*I3C_MST_Type)(unsafe.Pointer(uintptr(0x500da000)))

	// I3C_MST_MEM Peripheral
	I3C_MST_MEM = (*I3C_MST_MEM_Type)(unsafe.Pointer(uintptr(0x500da000)))

	// I3C Controller (Slave)
	I3C_SLV = (*I3C_SLV_Type)(unsafe.Pointer(uintptr(0x500db000)))

	// AXI_ICM Peripheral
	AXI_ICM = (*ICM_AXI_Type)(unsafe.Pointer(uintptr(0x500a4000)))

	// Input/Output Multiplexer
	IO_MUX = (*IO_MUX_Type)(unsafe.Pointer(uintptr(0x500e1000)))

	// ISP Peripheral
	ISP = (*ISP_Type)(unsafe.Pointer(uintptr(0x500a1000)))

	// JPEG Codec
	JPEG = (*JPEG_Type)(unsafe.Pointer(uintptr(0x50086000)))

	// Camera/LCD Controller
	LCD_CAM = (*LCDCAM_Type)(unsafe.Pointer(uintptr(0x500dc000)))

	// LED Control PWM (Pulse Width Modulation)
	LEDC = (*LEDC_Type)(unsafe.Pointer(uintptr(0x500d3000)))

	// Low-power Interrupt Controller
	LP_INTR = (*LPINTR_Type)(unsafe.Pointer(uintptr(0x5012c000)))

	// LP_PERI Peripheral
	LP_PERI = (*LPPERI_Type)(unsafe.Pointer(uintptr(0x50120000)))

	// LP_SYS Peripheral
	LP_SYS = (*LPSYSREG_Type)(unsafe.Pointer(uintptr(0x50110000)))

	// LP_ANA_PERI Peripheral
	LP_ANA_PERI = (*LP_ANA_PERI_Type)(unsafe.Pointer(uintptr(0x50113000)))

	// LP_AON_CLKRST Peripheral
	LP_AON_CLKRST = (*LP_AON_CLKRST_Type)(unsafe.Pointer(uintptr(0x50111000)))

	// Low-power General Purpose Input/Output
	LP_GPIO = (*LP_GPIO_Type)(unsafe.Pointer(uintptr(0x5012a000)))

	// Low-power I2C (Inter-Integrated Circuit) Controller 0
	LP_I2C0 = (*LP_I2C_Type)(unsafe.Pointer(uintptr(0x50122000)))

	// Low-power I2S (Inter-IC Sound) Controller 0
	LP_I2S0 = (*LP_I2S_Type)(unsafe.Pointer(uintptr(0x50125000)))

	// Low-power Input/Output Multiplexer
	LP_IO_MUX = (*LP_IOMUX_Type)(unsafe.Pointer(uintptr(0x5012b000)))

	// Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller
	LP_UART = (*LP_UART_Type)(unsafe.Pointer(uintptr(0x50121000)))

	// Motor Control Pulse-Width Modulation 0
	MCPWM0 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x500c0000)))

	// Parallel IO Controller
	PARL_IO = (*PARL_IO_Type)(unsafe.Pointer(uintptr(0x500cf000)))

	// PAU Peripheral
	PAU = (*PAU_Type)(unsafe.Pointer(uintptr(0x60093000)))

	// Pulse Count Controller
	PCNT = (*PCNT_Type)(unsafe.Pointer(uintptr(0x500c9000)))

	// PMU Peripheral
	PMU = (*PMU_Type)(unsafe.Pointer(uintptr(0x50115000)))

	// PPA Peripheral
	PPA = (*PPA_Type)(unsafe.Pointer(uintptr(0x50087000)))

	// PVT Peripheral
	PVT = (*PVT_Type)(unsafe.Pointer(uintptr(0x5009e000)))

	// Remote Control
	RMT = (*RMT_Type)(unsafe.Pointer(uintptr(0x500d4000)))

	// RSA (Rivest Shamir Adleman) Accelerator
	RSA = (*RSA_Type)(unsafe.Pointer(uintptr(0x50092000)))

	// Low-power Analog to Digital Converter
	LP_ADC = (*RTCADC_Type)(unsafe.Pointer(uintptr(0x50127000)))

	// Low-power Timer
	LP_TIMER = (*RTC_TIMER_Type)(unsafe.Pointer(uintptr(0x50112000)))

	// LP_TOUCH Peripheral
	LP_TOUCH = (*RTC_TOUCH_Type)(unsafe.Pointer(uintptr(0x50128000)))

	// Low-power Watchdog Timer
	LP_WDT = (*RTC_WDT_Type)(unsafe.Pointer(uintptr(0x50116000)))

	// SD/MMC Host Controller
	SDHOST = (*SDHOST_Type)(unsafe.Pointer(uintptr(0x50083000)))

	// SHA (Secure Hash Algorithm) Accelerator
	SHA = (*SHA_Type)(unsafe.Pointer(uintptr(0x50091000)))

	// Event Task Matrix
	SOC_ETM = (*SOC_ETM_Type)(unsafe.Pointer(uintptr(0x500d5000)))

	// SPI (Serial Peripheral Interface) Controller 0
	SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x5008c000)))

	// SPI (Serial Peripheral Interface) Controller 1
	SPI1 = (*SPI1_Type)(unsafe.Pointer(uintptr(0x5008d000)))

	// SPI (Serial Peripheral Interface) Controller 2
	SPI2 = (*SPI2_Type)(unsafe.Pointer(uintptr(0x500d0000)))

	// SPI (Serial Peripheral Interface) Controller 3
	SPI3 = (*SPI3_Type)(unsafe.Pointer(uintptr(0x500d1000)))

	// System Timer
	SYSTIMER = (*SYSTIMER_Type)(unsafe.Pointer(uintptr(0x500e2000)))

	// Timer Group 0
	TIMG0 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x500c2000)))

	// TRACE0 Peripheral
	TRACE0 = (*TRACE_Type)(unsafe.Pointer(uintptr(0x3ff04000)))

	// Low-power Temperature Sensor
	LP_TSENS = (*TSENS_Type)(unsafe.Pointer(uintptr(0x5012f000)))

	// Two-Wire Automotive Interface
	TWAI0 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x500d7000)))

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 0
	UART0 = (*UART_Type)(unsafe.Pointer(uintptr(0x500ca000)))

	// Universal Host Controller Interface 0
	UHCI0 = (*UHCI_Type)(unsafe.Pointer(uintptr(0x500df000)))

	// Full-speed USB Serial/JTAG Controller
	USB_DEVICE = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x500d2000)))

	// USB_WRAP Peripheral
	USB_WRAP = (*USB_WRAP_Type)(unsafe.Pointer(uintptr(0x50080000)))

	// I2C (Inter-Integrated Circuit) Controller 1
	I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x500c5000)))

	// I2S (Inter-IC Sound) Controller 1
	I2S1 = (*I2S_Type)(unsafe.Pointer(uintptr(0x500c7000)))

	// I2S (Inter-IC Sound) Controller 2
	I2S2 = (*I2S_Type)(unsafe.Pointer(uintptr(0x500c8000)))

	// Motor Control Pulse-Width Modulation 1
	MCPWM1 = (*MCPWM_Type)(unsafe.Pointer(uintptr(0x500c1000)))

	// Timer Group 1
	TIMG1 = (*TIMG_Type)(unsafe.Pointer(uintptr(0x500c3000)))

	// TRACE1 Peripheral
	TRACE1 = (*TRACE_Type)(unsafe.Pointer(uintptr(0x3ff05000)))

	// Two-Wire Automotive Interface
	TWAI1 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x500d8000)))

	// Two-Wire Automotive Interface
	TWAI2 = (*TWAI_Type)(unsafe.Pointer(uintptr(0x500d9000)))

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 1
	UART1 = (*UART_Type)(unsafe.Pointer(uintptr(0x500cb000)))

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 2
	UART2 = (*UART_Type)(unsafe.Pointer(uintptr(0x500cc000)))

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 3
	UART3 = (*UART_Type)(unsafe.Pointer(uintptr(0x500cd000)))

	// UART (Universal Asynchronous Receiver-Transmitter) Controller 4
	UART4 = (*UART_Type)(unsafe.Pointer(uintptr(0x500ce000)))
)

// ADC (Analog to Digital Converter)
type ADC_Type struct {
	CTRL             volatile.Register32 // 0x0
	CTRL2            volatile.Register32 // 0x4
	FILTER_CTRL1     volatile.Register32 // 0x8
	FSM_WAIT         volatile.Register32 // 0xC
	SAR1_STATUS      volatile.Register32 // 0x10
	SAR2_STATUS      volatile.Register32 // 0x14
	SAR1_PATT_TAB1   volatile.Register32 // 0x18
	SAR1_PATT_TAB2   volatile.Register32 // 0x1C
	SAR1_PATT_TAB3   volatile.Register32 // 0x20
	SAR1_PATT_TAB4   volatile.Register32 // 0x24
	SAR2_PATT_TAB1   volatile.Register32 // 0x28
	SAR2_PATT_TAB2   volatile.Register32 // 0x2C
	SAR2_PATT_TAB3   volatile.Register32 // 0x30
	SAR2_PATT_TAB4   volatile.Register32 // 0x34
	ARB_CTRL         volatile.Register32 // 0x38
	FILTER_CTRL0     volatile.Register32 // 0x3C
	SAR1_DATA_STATUS volatile.Register32 // 0x40
	THRES0_CTRL      volatile.Register32 // 0x44
	THRES1_CTRL      volatile.Register32 // 0x48
	THRES_CTRL       volatile.Register32 // 0x4C
	INT_ENA          volatile.Register32 // 0x50
	INT_RAW          volatile.Register32 // 0x54
	INT_ST           volatile.Register32 // 0x58
	INT_CLR          volatile.Register32 // 0x5C
	DMA_CONF         volatile.Register32 // 0x60
	SAR2_DATA_STATUS volatile.Register32 // 0x64
	CALI             volatile.Register32 // 0x68
	RND_ECO_LOW      volatile.Register32 // 0x6C
	RND_ECO_HIGH     volatile.Register32 // 0x70
	RND_ECO_CS       volatile.Register32 // 0x74
	_                [900]byte
	CTRL_DATE        volatile.Register32 // 0x3FC
}

// ADC.CTRL: Register
func (o *ADC_Type) SetCTRL_START_FORCE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCTRL_START_FORCE() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0x1
}
func (o *ADC_Type) SetCTRL_START(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCTRL_START() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCTRL_WORK_MODE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc)|value<<2)
}
func (o *ADC_Type) GetCTRL_WORK_MODE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc) >> 2
}
func (o *ADC_Type) SetCTRL_SAR_SEL(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCTRL_SAR_SEL() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCTRL_SAR_CLK_GATED(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCTRL_SAR_CLK_GATED() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCTRL_SAR_CLK_DIV(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3fc0)|value<<6)
}
func (o *ADC_Type) GetCTRL_SAR_CLK_DIV() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3fc0) >> 6
}
func (o *ADC_Type) SetCTRL_SAR1_PATT_LEN(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3c000)|value<<14)
}
func (o *ADC_Type) GetCTRL_SAR1_PATT_LEN() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3c000) >> 14
}
func (o *ADC_Type) SetCTRL_SAR2_PATT_LEN(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3c0000)|value<<18)
}
func (o *ADC_Type) GetCTRL_SAR2_PATT_LEN() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3c0000) >> 18
}
func (o *ADC_Type) SetCTRL_SAR1_PATT_P_CLEAR(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Type) GetCTRL_SAR1_PATT_P_CLEAR() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22
}
func (o *ADC_Type) SetCTRL_SAR2_PATT_P_CLEAR(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetCTRL_SAR2_PATT_P_CLEAR() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetCTRL_DATA_SAR_SEL(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetCTRL_DATA_SAR_SEL() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetCTRL_DATA_TO_I2S(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetCTRL_DATA_TO_I2S() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetCTRL_XPD_SAR1_FORCE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc000000)|value<<26)
}
func (o *ADC_Type) GetCTRL_XPD_SAR1_FORCE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc000000) >> 26
}
func (o *ADC_Type) SetCTRL_XPD_SAR2_FORCE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x30000000)|value<<28)
}
func (o *ADC_Type) GetCTRL_XPD_SAR2_FORCE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x30000000) >> 28
}
func (o *ADC_Type) SetCTRL_WAIT_ARB_CYCLE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetCTRL_WAIT_ARB_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0xc0000000) >> 30
}

// ADC.CTRL2: Register
func (o *ADC_Type) SetCTRL2_MEAS_NUM_LIMIT(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCTRL2_MEAS_NUM_LIMIT() uint32 {
	return volatile.LoadUint32(&o.CTRL2.Reg) & 0x1
}
func (o *ADC_Type) SetCTRL2_MAX_MEAS_NUM(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1fe)|value<<1)
}
func (o *ADC_Type) GetCTRL2_MAX_MEAS_NUM() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1fe) >> 1
}
func (o *ADC_Type) SetCTRL2_SAR1_INV(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCTRL2_SAR1_INV() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCTRL2_SAR2_INV(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCTRL2_SAR2_INV() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCTRL2_TIMER_SEL(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetCTRL2_TIMER_SEL() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetCTRL2_TIMER_TARGET(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff000)|value<<12)
}
func (o *ADC_Type) GetCTRL2_TIMER_TARGET() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff000) >> 12
}
func (o *ADC_Type) SetCTRL2_TIMER_EN(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetCTRL2_TIMER_EN() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x1000000) >> 24
}

// ADC.FILTER_CTRL1: Register
func (o *ADC_Type) SetFILTER_CTRL1_FILTER_FACTOR1(value uint32) {
	volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0x1c000000)|value<<26)
}
func (o *ADC_Type) GetFILTER_CTRL1_FILTER_FACTOR1() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0x1c000000) >> 26
}
func (o *ADC_Type) SetFILTER_CTRL1_FILTER_FACTOR0(value uint32) {
	volatile.StoreUint32(&o.FILTER_CTRL1.Reg, volatile.LoadUint32(&o.FILTER_CTRL1.Reg)&^(0xe0000000)|value<<29)
}
func (o *ADC_Type) GetFILTER_CTRL1_FILTER_FACTOR0() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CTRL1.Reg) & 0xe0000000) >> 29
}

// ADC.FSM_WAIT: Register
func (o *ADC_Type) SetFSM_WAIT_XPD_WAIT(value uint32) {
	volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff)|value)
}
func (o *ADC_Type) GetFSM_WAIT_XPD_WAIT() uint32 {
	return volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff
}
func (o *ADC_Type) SetFSM_WAIT_RSTB_WAIT(value uint32) {
	volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff00)|value<<8)
}
func (o *ADC_Type) GetFSM_WAIT_RSTB_WAIT() uint32 {
	return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff00) >> 8
}
func (o *ADC_Type) SetFSM_WAIT_STANDBY_WAIT(value uint32) {
	volatile.StoreUint32(&o.FSM_WAIT.Reg, volatile.LoadUint32(&o.FSM_WAIT.Reg)&^(0xff0000)|value<<16)
}
func (o *ADC_Type) GetFSM_WAIT_STANDBY_WAIT() uint32 {
	return (volatile.LoadUint32(&o.FSM_WAIT.Reg) & 0xff0000) >> 16
}

// ADC.SAR1_STATUS: Register
func (o *ADC_Type) SetSAR1_STATUS(value uint32) {
	volatile.StoreUint32(&o.SAR1_STATUS.Reg, value)
}
func (o *ADC_Type) GetSAR1_STATUS() uint32 {
	return volatile.LoadUint32(&o.SAR1_STATUS.Reg)
}

// ADC.SAR2_STATUS: Register
func (o *ADC_Type) SetSAR2_STATUS(value uint32) {
	volatile.StoreUint32(&o.SAR2_STATUS.Reg, value)
}
func (o *ADC_Type) GetSAR2_STATUS() uint32 {
	return volatile.LoadUint32(&o.SAR2_STATUS.Reg)
}

// ADC.SAR1_PATT_TAB1: Register
func (o *ADC_Type) SetSAR1_PATT_TAB1(value uint32) {
	volatile.StoreUint32(&o.SAR1_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB1.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR1_PATT_TAB1() uint32 {
	return volatile.LoadUint32(&o.SAR1_PATT_TAB1.Reg) & 0xffffff
}

// ADC.SAR1_PATT_TAB2: Register
func (o *ADC_Type) SetSAR1_PATT_TAB2(value uint32) {
	volatile.StoreUint32(&o.SAR1_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB2.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR1_PATT_TAB2() uint32 {
	return volatile.LoadUint32(&o.SAR1_PATT_TAB2.Reg) & 0xffffff
}

// ADC.SAR1_PATT_TAB3: Register
func (o *ADC_Type) SetSAR1_PATT_TAB3(value uint32) {
	volatile.StoreUint32(&o.SAR1_PATT_TAB3.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB3.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR1_PATT_TAB3() uint32 {
	return volatile.LoadUint32(&o.SAR1_PATT_TAB3.Reg) & 0xffffff
}

// ADC.SAR1_PATT_TAB4: Register
func (o *ADC_Type) SetSAR1_PATT_TAB4(value uint32) {
	volatile.StoreUint32(&o.SAR1_PATT_TAB4.Reg, volatile.LoadUint32(&o.SAR1_PATT_TAB4.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR1_PATT_TAB4() uint32 {
	return volatile.LoadUint32(&o.SAR1_PATT_TAB4.Reg) & 0xffffff
}

// ADC.SAR2_PATT_TAB1: Register
func (o *ADC_Type) SetSAR2_PATT_TAB1(value uint32) {
	volatile.StoreUint32(&o.SAR2_PATT_TAB1.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB1.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR2_PATT_TAB1() uint32 {
	return volatile.LoadUint32(&o.SAR2_PATT_TAB1.Reg) & 0xffffff
}

// ADC.SAR2_PATT_TAB2: Register
func (o *ADC_Type) SetSAR2_PATT_TAB2(value uint32) {
	volatile.StoreUint32(&o.SAR2_PATT_TAB2.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB2.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR2_PATT_TAB2() uint32 {
	return volatile.LoadUint32(&o.SAR2_PATT_TAB2.Reg) & 0xffffff
}

// ADC.SAR2_PATT_TAB3: Register
func (o *ADC_Type) SetSAR2_PATT_TAB3(value uint32) {
	volatile.StoreUint32(&o.SAR2_PATT_TAB3.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB3.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR2_PATT_TAB3() uint32 {
	return volatile.LoadUint32(&o.SAR2_PATT_TAB3.Reg) & 0xffffff
}

// ADC.SAR2_PATT_TAB4: Register
func (o *ADC_Type) SetSAR2_PATT_TAB4(value uint32) {
	volatile.StoreUint32(&o.SAR2_PATT_TAB4.Reg, volatile.LoadUint32(&o.SAR2_PATT_TAB4.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetSAR2_PATT_TAB4() uint32 {
	return volatile.LoadUint32(&o.SAR2_PATT_TAB4.Reg) & 0xffffff
}

// ADC.ARB_CTRL: Register
func (o *ADC_Type) SetARB_CTRL_ARB_APB_FORCE(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetARB_CTRL_ARB_APB_FORCE() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetARB_CTRL_ARB_RTC_FORCE(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetARB_CTRL_ARB_RTC_FORCE() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetARB_CTRL_ARB_WIFI_FORCE(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetARB_CTRL_ARB_WIFI_FORCE() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetARB_CTRL_ARB_GRANT_FORCE(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetARB_CTRL_ARB_GRANT_FORCE() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetARB_CTRL_ARB_APB_PRIORITY(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc0)|value<<6)
}
func (o *ADC_Type) GetARB_CTRL_ARB_APB_PRIORITY() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc0) >> 6
}
func (o *ADC_Type) SetARB_CTRL_ARB_RTC_PRIORITY(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x300)|value<<8)
}
func (o *ADC_Type) GetARB_CTRL_ARB_RTC_PRIORITY() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x300) >> 8
}
func (o *ADC_Type) SetARB_CTRL_ARB_WIFI_PRIORITY(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0xc00)|value<<10)
}
func (o *ADC_Type) GetARB_CTRL_ARB_WIFI_PRIORITY() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0xc00) >> 10
}
func (o *ADC_Type) SetARB_CTRL_ARB_FIX_PRIORITY(value uint32) {
	volatile.StoreUint32(&o.ARB_CTRL.Reg, volatile.LoadUint32(&o.ARB_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetARB_CTRL_ARB_FIX_PRIORITY() uint32 {
	return (volatile.LoadUint32(&o.ARB_CTRL.Reg) & 0x1000) >> 12
}

// ADC.FILTER_CTRL0: Register
func (o *ADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL1(value uint32) {
	volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x7c000)|value<<14)
}
func (o *ADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL1() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x7c000) >> 14
}
func (o *ADC_Type) SetFILTER_CTRL0_FILTER_CHANNEL0(value uint32) {
	volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0xf80000)|value<<19)
}
func (o *ADC_Type) GetFILTER_CTRL0_FILTER_CHANNEL0() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0xf80000) >> 19
}
func (o *ADC_Type) SetFILTER_CTRL0_FILTER_RESET(value uint32) {
	volatile.StoreUint32(&o.FILTER_CTRL0.Reg, volatile.LoadUint32(&o.FILTER_CTRL0.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetFILTER_CTRL0_FILTER_RESET() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CTRL0.Reg) & 0x80000000) >> 31
}

// ADC.SAR1_DATA_STATUS: Register
func (o *ADC_Type) SetSAR1_DATA_STATUS_APB_SARADC1_DATA(value uint32) {
	volatile.StoreUint32(&o.SAR1_DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR1_DATA_STATUS.Reg)&^(0x1ffff)|value)
}
func (o *ADC_Type) GetSAR1_DATA_STATUS_APB_SARADC1_DATA() uint32 {
	return volatile.LoadUint32(&o.SAR1_DATA_STATUS.Reg) & 0x1ffff
}

// ADC.THRES0_CTRL: Register
func (o *ADC_Type) SetTHRES0_CTRL_THRES0_CHANNEL(value uint32) {
	volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x1f)|value)
}
func (o *ADC_Type) GetTHRES0_CTRL_THRES0_CHANNEL() uint32 {
	return volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x1f
}
func (o *ADC_Type) SetTHRES0_CTRL_THRES0_HIGH(value uint32) {
	volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x3ffe0)|value<<5)
}
func (o *ADC_Type) GetTHRES0_CTRL_THRES0_HIGH() uint32 {
	return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x3ffe0) >> 5
}
func (o *ADC_Type) SetTHRES0_CTRL_THRES0_LOW(value uint32) {
	volatile.StoreUint32(&o.THRES0_CTRL.Reg, volatile.LoadUint32(&o.THRES0_CTRL.Reg)&^(0x7ffc0000)|value<<18)
}
func (o *ADC_Type) GetTHRES0_CTRL_THRES0_LOW() uint32 {
	return (volatile.LoadUint32(&o.THRES0_CTRL.Reg) & 0x7ffc0000) >> 18
}

// ADC.THRES1_CTRL: Register
func (o *ADC_Type) SetTHRES1_CTRL_THRES1_CHANNEL(value uint32) {
	volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x1f)|value)
}
func (o *ADC_Type) GetTHRES1_CTRL_THRES1_CHANNEL() uint32 {
	return volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x1f
}
func (o *ADC_Type) SetTHRES1_CTRL_THRES1_HIGH(value uint32) {
	volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x3ffe0)|value<<5)
}
func (o *ADC_Type) GetTHRES1_CTRL_THRES1_HIGH() uint32 {
	return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x3ffe0) >> 5
}
func (o *ADC_Type) SetTHRES1_CTRL_THRES1_LOW(value uint32) {
	volatile.StoreUint32(&o.THRES1_CTRL.Reg, volatile.LoadUint32(&o.THRES1_CTRL.Reg)&^(0x7ffc0000)|value<<18)
}
func (o *ADC_Type) GetTHRES1_CTRL_THRES1_LOW() uint32 {
	return (volatile.LoadUint32(&o.THRES1_CTRL.Reg) & 0x7ffc0000) >> 18
}

// ADC.THRES_CTRL: Register
func (o *ADC_Type) SetTHRES_CTRL_THRES_ALL_EN(value uint32) {
	volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetTHRES_CTRL_THRES_ALL_EN() uint32 {
	return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetTHRES_CTRL_THRES3_EN(value uint32) {
	volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetTHRES_CTRL_THRES3_EN() uint32 {
	return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetTHRES_CTRL_THRES2_EN(value uint32) {
	volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetTHRES_CTRL_THRES2_EN() uint32 {
	return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetTHRES_CTRL_THRES1_EN(value uint32) {
	volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetTHRES_CTRL_THRES1_EN() uint32 {
	return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetTHRES_CTRL_THRES0_EN(value uint32) {
	volatile.StoreUint32(&o.THRES_CTRL.Reg, volatile.LoadUint32(&o.THRES_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetTHRES_CTRL_THRES0_EN() uint32 {
	return (volatile.LoadUint32(&o.THRES_CTRL.Reg) & 0x80000000) >> 31
}

// ADC.INT_ENA: Register
func (o *ADC_Type) SetINT_ENA_THRES1_LOW_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetINT_ENA_THRES1_LOW_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetINT_ENA_THRES0_LOW_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetINT_ENA_THRES0_LOW_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetINT_ENA_THRES1_HIGH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetINT_ENA_THRES1_HIGH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetINT_ENA_THRES0_HIGH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetINT_ENA_THRES0_HIGH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetINT_ENA_SAR2_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetINT_ENA_SAR2_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetINT_ENA_SAR1_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetINT_ENA_SAR1_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31
}

// ADC.INT_RAW: Register
func (o *ADC_Type) SetINT_RAW_THRES1_LOW_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetINT_RAW_THRES1_LOW_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetINT_RAW_THRES0_LOW_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetINT_RAW_THRES0_LOW_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetINT_RAW_THRES1_HIGH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetINT_RAW_THRES1_HIGH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetINT_RAW_THRES0_HIGH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetINT_RAW_THRES0_HIGH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetINT_RAW_SAR2_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetINT_RAW_SAR2_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetINT_RAW_SAR1_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetINT_RAW_SAR1_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31
}

// ADC.INT_ST: Register
func (o *ADC_Type) SetINT_ST_THRES1_LOW_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetINT_ST_THRES1_LOW_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetINT_ST_THRES0_LOW_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetINT_ST_THRES0_LOW_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetINT_ST_THRES1_HIGH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetINT_ST_THRES1_HIGH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetINT_ST_THRES0_HIGH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetINT_ST_THRES0_HIGH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetINT_ST_APB_SARADC2_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetINT_ST_APB_SARADC2_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetINT_ST_APB_SARADC1_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetINT_ST_APB_SARADC1_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31
}

// ADC.INT_CLR: Register
func (o *ADC_Type) SetINT_CLR_THRES1_LOW_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetINT_CLR_THRES1_LOW_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetINT_CLR_THRES0_LOW_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetINT_CLR_THRES0_LOW_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetINT_CLR_THRES1_HIGH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetINT_CLR_THRES1_HIGH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetINT_CLR_THRES0_HIGH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetINT_CLR_THRES0_HIGH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetINT_CLR_APB_SARADC2_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetINT_CLR_APB_SARADC2_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetINT_CLR_APB_SARADC1_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetINT_CLR_APB_SARADC1_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31
}

// ADC.DMA_CONF: Register
func (o *ADC_Type) SetDMA_CONF_APB_ADC_EOF_NUM(value uint32) {
	volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetDMA_CONF_APB_ADC_EOF_NUM() uint32 {
	return volatile.LoadUint32(&o.DMA_CONF.Reg) & 0xffff
}
func (o *ADC_Type) SetDMA_CONF_APB_ADC_RESET_FSM(value uint32) {
	volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetDMA_CONF_APB_ADC_RESET_FSM() uint32 {
	return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetDMA_CONF_APB_ADC_TRANS(value uint32) {
	volatile.StoreUint32(&o.DMA_CONF.Reg, volatile.LoadUint32(&o.DMA_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetDMA_CONF_APB_ADC_TRANS() uint32 {
	return (volatile.LoadUint32(&o.DMA_CONF.Reg) & 0x80000000) >> 31
}

// ADC.SAR2_DATA_STATUS: Register
func (o *ADC_Type) SetSAR2_DATA_STATUS_APB_SARADC2_DATA(value uint32) {
	volatile.StoreUint32(&o.SAR2_DATA_STATUS.Reg, volatile.LoadUint32(&o.SAR2_DATA_STATUS.Reg)&^(0x1ffff)|value)
}
func (o *ADC_Type) GetSAR2_DATA_STATUS_APB_SARADC2_DATA() uint32 {
	return volatile.LoadUint32(&o.SAR2_DATA_STATUS.Reg) & 0x1ffff
}

// ADC.CALI: Register
func (o *ADC_Type) SetCALI_CFG(value uint32) {
	volatile.StoreUint32(&o.CALI.Reg, volatile.LoadUint32(&o.CALI.Reg)&^(0x1ffff)|value)
}
func (o *ADC_Type) GetCALI_CFG() uint32 {
	return volatile.LoadUint32(&o.CALI.Reg) & 0x1ffff
}

// ADC.RND_ECO_LOW: Register
func (o *ADC_Type) SetRND_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value)
}
func (o *ADC_Type) GetRND_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_LOW.Reg)
}

// ADC.RND_ECO_HIGH: Register
func (o *ADC_Type) SetRND_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value)
}
func (o *ADC_Type) GetRND_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg)
}

// ADC.RND_ECO_CS: Register
func (o *ADC_Type) SetRND_ECO_CS_RND_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetRND_ECO_CS_RND_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1
}
func (o *ADC_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1
}

// ADC.CTRL_DATE: Register
func (o *ADC_Type) SetCTRL_DATE(value uint32) {
	volatile.StoreUint32(&o.CTRL_DATE.Reg, volatile.LoadUint32(&o.CTRL_DATE.Reg)&^(0x7fffffff)|value)
}
func (o *ADC_Type) GetCTRL_DATE() uint32 {
	return volatile.LoadUint32(&o.CTRL_DATE.Reg) & 0x7fffffff
}
func (o *ADC_Type) SetCTRL_DATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CTRL_DATE.Reg, volatile.LoadUint32(&o.CTRL_DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetCTRL_DATE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CTRL_DATE.Reg) & 0x80000000) >> 31
}

// AES (Advanced Encryption Standard) Accelerator
type AES_Type struct {
	KEY_0             volatile.Register32    // 0x0
	KEY_1             volatile.Register32    // 0x4
	KEY_2             volatile.Register32    // 0x8
	KEY_3             volatile.Register32    // 0xC
	KEY_4             volatile.Register32    // 0x10
	KEY_5             volatile.Register32    // 0x14
	KEY_6             volatile.Register32    // 0x18
	KEY_7             volatile.Register32    // 0x1C
	TEXT_IN_0         volatile.Register32    // 0x20
	TEXT_IN_1         volatile.Register32    // 0x24
	TEXT_IN_2         volatile.Register32    // 0x28
	TEXT_IN_3         volatile.Register32    // 0x2C
	TEXT_OUT_0        volatile.Register32    // 0x30
	TEXT_OUT_1        volatile.Register32    // 0x34
	TEXT_OUT_2        volatile.Register32    // 0x38
	TEXT_OUT_3        volatile.Register32    // 0x3C
	MODE              volatile.Register32    // 0x40
	ENDIAN            volatile.Register32    // 0x44
	TRIGGER           volatile.Register32    // 0x48
	STATE             volatile.Register32    // 0x4C
	IV_MEM            [4]volatile.Register32 // 0x50
	H_MEM             [4]volatile.Register32 // 0x60
	J0_MEM            [4]volatile.Register32 // 0x70
	T0_MEM            [4]volatile.Register32 // 0x80
	DMA_ENABLE        volatile.Register32    // 0x90
	BLOCK_MODE        volatile.Register32    // 0x94
	BLOCK_NUM         volatile.Register32    // 0x98
	INC_SEL           volatile.Register32    // 0x9C
	AAD_BLOCK_NUM     volatile.Register32    // 0xA0
	REMAINDER_BIT_NUM volatile.Register32    // 0xA4
	CONTINUE          volatile.Register32    // 0xA8
	INT_CLEAR         volatile.Register32    // 0xAC
	INT_ENA           volatile.Register32    // 0xB0
	DATE              volatile.Register32    // 0xB4
	DMA_EXIT          volatile.Register32    // 0xB8
}

// AES.KEY_0: Key material key_0 configure register
func (o *AES_Type) SetKEY_0(value uint32) {
	volatile.StoreUint32(&o.KEY_0.Reg, value)
}
func (o *AES_Type) GetKEY_0() uint32 {
	return volatile.LoadUint32(&o.KEY_0.Reg)
}

// AES.KEY_1: Key material key_1 configure register
func (o *AES_Type) SetKEY_1(value uint32) {
	volatile.StoreUint32(&o.KEY_1.Reg, value)
}
func (o *AES_Type) GetKEY_1() uint32 {
	return volatile.LoadUint32(&o.KEY_1.Reg)
}

// AES.KEY_2: Key material key_2 configure register
func (o *AES_Type) SetKEY_2(value uint32) {
	volatile.StoreUint32(&o.KEY_2.Reg, value)
}
func (o *AES_Type) GetKEY_2() uint32 {
	return volatile.LoadUint32(&o.KEY_2.Reg)
}

// AES.KEY_3: Key material key_3 configure register
func (o *AES_Type) SetKEY_3(value uint32) {
	volatile.StoreUint32(&o.KEY_3.Reg, value)
}
func (o *AES_Type) GetKEY_3() uint32 {
	return volatile.LoadUint32(&o.KEY_3.Reg)
}

// AES.KEY_4: Key material key_4 configure register
func (o *AES_Type) SetKEY_4(value uint32) {
	volatile.StoreUint32(&o.KEY_4.Reg, value)
}
func (o *AES_Type) GetKEY_4() uint32 {
	return volatile.LoadUint32(&o.KEY_4.Reg)
}

// AES.KEY_5: Key material key_5 configure register
func (o *AES_Type) SetKEY_5(value uint32) {
	volatile.StoreUint32(&o.KEY_5.Reg, value)
}
func (o *AES_Type) GetKEY_5() uint32 {
	return volatile.LoadUint32(&o.KEY_5.Reg)
}

// AES.KEY_6: Key material key_6 configure register
func (o *AES_Type) SetKEY_6(value uint32) {
	volatile.StoreUint32(&o.KEY_6.Reg, value)
}
func (o *AES_Type) GetKEY_6() uint32 {
	return volatile.LoadUint32(&o.KEY_6.Reg)
}

// AES.KEY_7: Key material key_7 configure register
func (o *AES_Type) SetKEY_7(value uint32) {
	volatile.StoreUint32(&o.KEY_7.Reg, value)
}
func (o *AES_Type) GetKEY_7() uint32 {
	return volatile.LoadUint32(&o.KEY_7.Reg)
}

// AES.TEXT_IN_0: source text material text_in_0 configure register
func (o *AES_Type) SetTEXT_IN_0(value uint32) {
	volatile.StoreUint32(&o.TEXT_IN_0.Reg, value)
}
func (o *AES_Type) GetTEXT_IN_0() uint32 {
	return volatile.LoadUint32(&o.TEXT_IN_0.Reg)
}

// AES.TEXT_IN_1: source text material text_in_1 configure register
func (o *AES_Type) SetTEXT_IN_1(value uint32) {
	volatile.StoreUint32(&o.TEXT_IN_1.Reg, value)
}
func (o *AES_Type) GetTEXT_IN_1() uint32 {
	return volatile.LoadUint32(&o.TEXT_IN_1.Reg)
}

// AES.TEXT_IN_2: source text material text_in_2 configure register
func (o *AES_Type) SetTEXT_IN_2(value uint32) {
	volatile.StoreUint32(&o.TEXT_IN_2.Reg, value)
}
func (o *AES_Type) GetTEXT_IN_2() uint32 {
	return volatile.LoadUint32(&o.TEXT_IN_2.Reg)
}

// AES.TEXT_IN_3: source text material text_in_3 configure register
func (o *AES_Type) SetTEXT_IN_3(value uint32) {
	volatile.StoreUint32(&o.TEXT_IN_3.Reg, value)
}
func (o *AES_Type) GetTEXT_IN_3() uint32 {
	return volatile.LoadUint32(&o.TEXT_IN_3.Reg)
}

// AES.TEXT_OUT_0: result text material text_out_0 configure register
func (o *AES_Type) SetTEXT_OUT_0(value uint32) {
	volatile.StoreUint32(&o.TEXT_OUT_0.Reg, value)
}
func (o *AES_Type) GetTEXT_OUT_0() uint32 {
	return volatile.LoadUint32(&o.TEXT_OUT_0.Reg)
}

// AES.TEXT_OUT_1: result text material text_out_1 configure register
func (o *AES_Type) SetTEXT_OUT_1(value uint32) {
	volatile.StoreUint32(&o.TEXT_OUT_1.Reg, value)
}
func (o *AES_Type) GetTEXT_OUT_1() uint32 {
	return volatile.LoadUint32(&o.TEXT_OUT_1.Reg)
}

// AES.TEXT_OUT_2: result text material text_out_2 configure register
func (o *AES_Type) SetTEXT_OUT_2(value uint32) {
	volatile.StoreUint32(&o.TEXT_OUT_2.Reg, value)
}
func (o *AES_Type) GetTEXT_OUT_2() uint32 {
	return volatile.LoadUint32(&o.TEXT_OUT_2.Reg)
}

// AES.TEXT_OUT_3: result text material text_out_3 configure register
func (o *AES_Type) SetTEXT_OUT_3(value uint32) {
	volatile.StoreUint32(&o.TEXT_OUT_3.Reg, value)
}
func (o *AES_Type) GetTEXT_OUT_3() uint32 {
	return volatile.LoadUint32(&o.TEXT_OUT_3.Reg)
}

// AES.MODE: AES Mode register
func (o *AES_Type) SetMODE(value uint32) {
	volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value)
}
func (o *AES_Type) GetMODE() uint32 {
	return volatile.LoadUint32(&o.MODE.Reg) & 0x7
}

// AES.ENDIAN: AES Endian configure register
func (o *AES_Type) SetENDIAN(value uint32) {
	volatile.StoreUint32(&o.ENDIAN.Reg, volatile.LoadUint32(&o.ENDIAN.Reg)&^(0x3f)|value)
}
func (o *AES_Type) GetENDIAN() uint32 {
	return volatile.LoadUint32(&o.ENDIAN.Reg) & 0x3f
}

// AES.TRIGGER: AES trigger register
func (o *AES_Type) SetTRIGGER(value uint32) {
	volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetTRIGGER() uint32 {
	return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1
}

// AES.STATE: AES state register
func (o *AES_Type) SetSTATE(value uint32) {
	volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value)
}
func (o *AES_Type) GetSTATE() uint32 {
	return volatile.LoadUint32(&o.STATE.Reg) & 0x3
}

// AES.DMA_ENABLE: DMA-AES working mode register
func (o *AES_Type) SetDMA_ENABLE(value uint32) {
	volatile.StoreUint32(&o.DMA_ENABLE.Reg, volatile.LoadUint32(&o.DMA_ENABLE.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetDMA_ENABLE() uint32 {
	return volatile.LoadUint32(&o.DMA_ENABLE.Reg) & 0x1
}

// AES.BLOCK_MODE: AES cipher block mode register
func (o *AES_Type) SetBLOCK_MODE(value uint32) {
	volatile.StoreUint32(&o.BLOCK_MODE.Reg, volatile.LoadUint32(&o.BLOCK_MODE.Reg)&^(0x7)|value)
}
func (o *AES_Type) GetBLOCK_MODE() uint32 {
	return volatile.LoadUint32(&o.BLOCK_MODE.Reg) & 0x7
}

// AES.BLOCK_NUM: AES block number register
func (o *AES_Type) SetBLOCK_NUM(value uint32) {
	volatile.StoreUint32(&o.BLOCK_NUM.Reg, value)
}
func (o *AES_Type) GetBLOCK_NUM() uint32 {
	return volatile.LoadUint32(&o.BLOCK_NUM.Reg)
}

// AES.INC_SEL: Standard incrementing function configure register
func (o *AES_Type) SetINC_SEL(value uint32) {
	volatile.StoreUint32(&o.INC_SEL.Reg, volatile.LoadUint32(&o.INC_SEL.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetINC_SEL() uint32 {
	return volatile.LoadUint32(&o.INC_SEL.Reg) & 0x1
}

// AES.AAD_BLOCK_NUM: Additional Authential Data block number register
func (o *AES_Type) SetAAD_BLOCK_NUM(value uint32) {
	volatile.StoreUint32(&o.AAD_BLOCK_NUM.Reg, value)
}
func (o *AES_Type) GetAAD_BLOCK_NUM() uint32 {
	return volatile.LoadUint32(&o.AAD_BLOCK_NUM.Reg)
}

// AES.REMAINDER_BIT_NUM: AES remainder bit number register
func (o *AES_Type) SetREMAINDER_BIT_NUM(value uint32) {
	volatile.StoreUint32(&o.REMAINDER_BIT_NUM.Reg, volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg)&^(0x7f)|value)
}
func (o *AES_Type) GetREMAINDER_BIT_NUM() uint32 {
	return volatile.LoadUint32(&o.REMAINDER_BIT_NUM.Reg) & 0x7f
}

// AES.CONTINUE: AES continue register
func (o *AES_Type) SetCONTINUE(value uint32) {
	volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetCONTINUE() uint32 {
	return volatile.LoadUint32(&o.CONTINUE.Reg) & 0x1
}

// AES.INT_CLEAR: AES Interrupt clear register
func (o *AES_Type) SetINT_CLEAR(value uint32) {
	volatile.StoreUint32(&o.INT_CLEAR.Reg, volatile.LoadUint32(&o.INT_CLEAR.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetINT_CLEAR() uint32 {
	return volatile.LoadUint32(&o.INT_CLEAR.Reg) & 0x1
}

// AES.INT_ENA: AES Interrupt enable register
func (o *AES_Type) SetINT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetINT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}

// AES.DATE: AES version control register
func (o *AES_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value)
}
func (o *AES_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff
}

// AES.DMA_EXIT: AES-DMA exit config
func (o *AES_Type) SetDMA_EXIT(value uint32) {
	volatile.StoreUint32(&o.DMA_EXIT.Reg, volatile.LoadUint32(&o.DMA_EXIT.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetDMA_EXIT() uint32 {
	return volatile.LoadUint32(&o.DMA_EXIT.Reg) & 0x1
}

// AHB_DMA Peripheral
type AHB_DMA_Type struct {
	IN_INT_RAW_CH0             volatile.Register32 // 0x0
	IN_INT_ST_CH0              volatile.Register32 // 0x4
	IN_INT_ENA_CH0             volatile.Register32 // 0x8
	IN_INT_CLR_CH0             volatile.Register32 // 0xC
	IN_INT_RAW_CH1             volatile.Register32 // 0x10
	IN_INT_ST_CH1              volatile.Register32 // 0x14
	IN_INT_ENA_CH1             volatile.Register32 // 0x18
	IN_INT_CLR_CH1             volatile.Register32 // 0x1C
	IN_INT_RAW_CH2             volatile.Register32 // 0x20
	IN_INT_ST_CH2              volatile.Register32 // 0x24
	IN_INT_ENA_CH2             volatile.Register32 // 0x28
	IN_INT_CLR_CH2             volatile.Register32 // 0x2C
	OUT_INT_RAW_CH0            volatile.Register32 // 0x30
	OUT_INT_ST_CH0             volatile.Register32 // 0x34
	OUT_INT_ENA_CH0            volatile.Register32 // 0x38
	OUT_INT_CLR_CH0            volatile.Register32 // 0x3C
	OUT_INT_RAW_CH1            volatile.Register32 // 0x40
	OUT_INT_ST_CH1             volatile.Register32 // 0x44
	OUT_INT_ENA_CH1            volatile.Register32 // 0x48
	OUT_INT_CLR_CH1            volatile.Register32 // 0x4C
	OUT_INT_RAW_CH2            volatile.Register32 // 0x50
	OUT_INT_ST_CH2             volatile.Register32 // 0x54
	OUT_INT_ENA_CH2            volatile.Register32 // 0x58
	OUT_INT_CLR_CH2            volatile.Register32 // 0x5C
	AHB_TEST                   volatile.Register32 // 0x60
	MISC_CONF                  volatile.Register32 // 0x64
	DATE                       volatile.Register32 // 0x68
	_                          [4]byte
	IN_CONF0_CH0               volatile.Register32 // 0x70
	IN_CONF1_CH0               volatile.Register32 // 0x74
	INFIFO_STATUS_CH0          volatile.Register32 // 0x78
	IN_POP_CH0                 volatile.Register32 // 0x7C
	IN_LINK_CH0                volatile.Register32 // 0x80
	IN_STATE_CH0               volatile.Register32 // 0x84
	IN_SUC_EOF_DES_ADDR_CH0    volatile.Register32 // 0x88
	IN_ERR_EOF_DES_ADDR_CH0    volatile.Register32 // 0x8C
	IN_DSCR_CH0                volatile.Register32 // 0x90
	IN_DSCR_BF0_CH0            volatile.Register32 // 0x94
	IN_DSCR_BF1_CH0            volatile.Register32 // 0x98
	IN_PRI_CH0                 volatile.Register32 // 0x9C
	IN_PERI_SEL_CH0            volatile.Register32 // 0xA0
	_                          [44]byte
	OUT_CONF0_CH0              volatile.Register32 // 0xD0
	OUT_CONF1_CH0              volatile.Register32 // 0xD4
	OUTFIFO_STATUS_CH0         volatile.Register32 // 0xD8
	OUT_PUSH_CH0               volatile.Register32 // 0xDC
	OUT_LINK_CH0               volatile.Register32 // 0xE0
	OUT_STATE_CH0              volatile.Register32 // 0xE4
	OUT_EOF_DES_ADDR_CH0       volatile.Register32 // 0xE8
	OUT_EOF_BFR_DES_ADDR_CH0   volatile.Register32 // 0xEC
	OUT_DSCR_CH0               volatile.Register32 // 0xF0
	OUT_DSCR_BF0_CH0           volatile.Register32 // 0xF4
	OUT_DSCR_BF1_CH0           volatile.Register32 // 0xF8
	OUT_PRI_CH0                volatile.Register32 // 0xFC
	OUT_PERI_SEL_CH0           volatile.Register32 // 0x100
	_                          [44]byte
	IN_CONF0_CH1               volatile.Register32 // 0x130
	IN_CONF1_CH1               volatile.Register32 // 0x134
	INFIFO_STATUS_CH1          volatile.Register32 // 0x138
	IN_POP_CH1                 volatile.Register32 // 0x13C
	IN_LINK_CH1                volatile.Register32 // 0x140
	IN_STATE_CH1               volatile.Register32 // 0x144
	IN_SUC_EOF_DES_ADDR_CH1    volatile.Register32 // 0x148
	IN_ERR_EOF_DES_ADDR_CH1    volatile.Register32 // 0x14C
	IN_DSCR_CH1                volatile.Register32 // 0x150
	IN_DSCR_BF0_CH1            volatile.Register32 // 0x154
	IN_DSCR_BF1_CH1            volatile.Register32 // 0x158
	IN_PRI_CH1                 volatile.Register32 // 0x15C
	IN_PERI_SEL_CH1            volatile.Register32 // 0x160
	_                          [44]byte
	OUT_CONF0_CH0              volatile.Register32 // 0x190
	OUT_CONF1_CH1              volatile.Register32 // 0x194
	OUTFIFO_STATUS_CH1         volatile.Register32 // 0x198
	OUT_PUSH_CH1               volatile.Register32 // 0x19C
	OUT_LINK_CH1               volatile.Register32 // 0x1A0
	OUT_STATE_CH1              volatile.Register32 // 0x1A4
	OUT_EOF_DES_ADDR_CH1       volatile.Register32 // 0x1A8
	OUT_EOF_BFR_DES_ADDR_CH1   volatile.Register32 // 0x1AC
	OUT_DSCR_CH1               volatile.Register32 // 0x1B0
	OUT_DSCR_BF0_CH1           volatile.Register32 // 0x1B4
	OUT_DSCR_BF1_CH1           volatile.Register32 // 0x1B8
	OUT_PRI_CH1                volatile.Register32 // 0x1BC
	OUT_PERI_SEL_CH1           volatile.Register32 // 0x1C0
	_                          [44]byte
	IN_CONF0_CH2               volatile.Register32 // 0x1F0
	IN_CONF1_CH2               volatile.Register32 // 0x1F4
	INFIFO_STATUS_CH2          volatile.Register32 // 0x1F8
	IN_POP_CH2                 volatile.Register32 // 0x1FC
	IN_LINK_CH2                volatile.Register32 // 0x200
	IN_STATE_CH2               volatile.Register32 // 0x204
	IN_SUC_EOF_DES_ADDR_CH2    volatile.Register32 // 0x208
	IN_ERR_EOF_DES_ADDR_CH2    volatile.Register32 // 0x20C
	IN_DSCR_CH2                volatile.Register32 // 0x210
	IN_DSCR_BF0_CH2            volatile.Register32 // 0x214
	IN_DSCR_BF1_CH2            volatile.Register32 // 0x218
	IN_PRI_CH2                 volatile.Register32 // 0x21C
	IN_PERI_SEL_CH2            volatile.Register32 // 0x220
	_                          [44]byte
	OUT_CONF0_CH1              volatile.Register32 // 0x250
	OUT_CONF1_CH2              volatile.Register32 // 0x254
	OUTFIFO_STATUS_CH2         volatile.Register32 // 0x258
	OUT_PUSH_CH2               volatile.Register32 // 0x25C
	OUT_LINK_CH2               volatile.Register32 // 0x260
	OUT_STATE_CH2              volatile.Register32 // 0x264
	OUT_EOF_DES_ADDR_CH2       volatile.Register32 // 0x268
	OUT_EOF_BFR_DES_ADDR_CH2   volatile.Register32 // 0x26C
	OUT_DSCR_CH2               volatile.Register32 // 0x270
	OUT_DSCR_BF0_CH2           volatile.Register32 // 0x274
	OUT_DSCR_BF1_CH2           volatile.Register32 // 0x278
	OUT_PRI_CH2                volatile.Register32 // 0x27C
	OUT_PERI_SEL_CH2           volatile.Register32 // 0x280
	_                          [56]byte
	OUT_CRC_INIT_DATA_CH0      volatile.Register32 // 0x2BC
	TX_CRC_WIDTH_CH0           volatile.Register32 // 0x2C0
	OUT_CRC_CLEAR_CH0          volatile.Register32 // 0x2C4
	OUT_CRC_FINAL_RESULT_CH0   volatile.Register32 // 0x2C8
	TX_CRC_EN_WR_DATA_CH0      volatile.Register32 // 0x2CC
	TX_CRC_EN_ADDR_CH0         volatile.Register32 // 0x2D0
	TX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x2D4
	TX_CRC_DATA_EN_ADDR_CH0    volatile.Register32 // 0x2D8
	TX_CH_ARB_WEIGH_CH0        volatile.Register32 // 0x2DC
	TX_ARB_WEIGH_OPT_DIR_CH0   volatile.Register32 // 0x2E0
	OUT_CRC_INIT_DATA_CH1      volatile.Register32 // 0x2E4
	TX_CRC_WIDTH_CH1           volatile.Register32 // 0x2E8
	OUT_CRC_CLEAR_CH1          volatile.Register32 // 0x2EC
	OUT_CRC_FINAL_RESULT_CH1   volatile.Register32 // 0x2F0
	TX_CRC_EN_WR_DATA_CH1      volatile.Register32 // 0x2F4
	TX_CRC_EN_ADDR_CH1         volatile.Register32 // 0x2F8
	TX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0x2FC
	TX_CRC_DATA_EN_ADDR_CH1    volatile.Register32 // 0x300
	TX_CH_ARB_WEIGH_CH1        volatile.Register32 // 0x304
	TX_ARB_WEIGH_OPT_DIR_CH1   volatile.Register32 // 0x308
	OUT_CRC_INIT_DATA_CH2      volatile.Register32 // 0x30C
	TX_CRC_WIDTH_CH2           volatile.Register32 // 0x310
	OUT_CRC_CLEAR_CH2          volatile.Register32 // 0x314
	OUT_CRC_FINAL_RESULT_CH2   volatile.Register32 // 0x318
	TX_CRC_EN_WR_DATA_CH2      volatile.Register32 // 0x31C
	TX_CRC_EN_ADDR_CH2         volatile.Register32 // 0x320
	TX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x324
	TX_CRC_DATA_EN_ADDR_CH2    volatile.Register32 // 0x328
	TX_CH_ARB_WEIGH_CH2        volatile.Register32 // 0x32C
	TX_ARB_WEIGH_OPT_DIR_CH2   volatile.Register32 // 0x330
	IN_CRC_INIT_DATA_CH0       volatile.Register32 // 0x334
	RX_CRC_WIDTH_CH0           volatile.Register32 // 0x338
	IN_CRC_CLEAR_CH0           volatile.Register32 // 0x33C
	IN_CRC_FINAL_RESULT_CH0    volatile.Register32 // 0x340
	RX_CRC_EN_WR_DATA_CH0      volatile.Register32 // 0x344
	RX_CRC_EN_ADDR_CH0         volatile.Register32 // 0x348
	RX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x34C
	RX_CRC_DATA_EN_ADDR_CH0    volatile.Register32 // 0x350
	RX_CH_ARB_WEIGH_CH0        volatile.Register32 // 0x354
	RX_ARB_WEIGH_OPT_DIR_CH0   volatile.Register32 // 0x358
	IN_CRC_INIT_DATA_CH1       volatile.Register32 // 0x35C
	RX_CRC_WIDTH_CH1           volatile.Register32 // 0x360
	IN_CRC_CLEAR_CH1           volatile.Register32 // 0x364
	IN_CRC_FINAL_RESULT_CH1    volatile.Register32 // 0x368
	RX_CRC_EN_WR_DATA_CH1      volatile.Register32 // 0x36C
	RX_CRC_EN_ADDR_CH1         volatile.Register32 // 0x370
	RX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0x374
	RX_CRC_DATA_EN_ADDR_CH1    volatile.Register32 // 0x378
	RX_CH_ARB_WEIGH_CH1        volatile.Register32 // 0x37C
	RX_ARB_WEIGH_OPT_DIR_CH1   volatile.Register32 // 0x380
	IN_CRC_INIT_DATA_CH2       volatile.Register32 // 0x384
	RX_CRC_WIDTH_CH2           volatile.Register32 // 0x388
	IN_CRC_CLEAR_CH2           volatile.Register32 // 0x38C
	IN_CRC_FINAL_RESULT_CH2    volatile.Register32 // 0x390
	RX_CRC_EN_WR_DATA_CH2      volatile.Register32 // 0x394
	RX_CRC_EN_ADDR_CH2         volatile.Register32 // 0x398
	RX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x39C
	RX_CRC_DATA_EN_ADDR_CH2    volatile.Register32 // 0x3A0
	RX_CH_ARB_WEIGH_CH2        volatile.Register32 // 0x3A4
	RX_ARB_WEIGH_OPT_DIR_CH2   volatile.Register32 // 0x3A8
	IN_LINK_ADDR_CH0           volatile.Register32 // 0x3AC
	IN_LINK_ADDR_CH1           volatile.Register32 // 0x3B0
	IN_LINK_ADDR_CH2           volatile.Register32 // 0x3B4
	OUT_LINK_ADDR_CH0          volatile.Register32 // 0x3B8
	OUT_LINK_ADDR_CH1          volatile.Register32 // 0x3BC
	OUT_LINK_ADDR_CH2          volatile.Register32 // 0x3C0
	INTR_MEM_START_ADDR        volatile.Register32 // 0x3C4
	INTR_MEM_END_ADDR          volatile.Register32 // 0x3C8
	ARB_TIMEOUT_TX             volatile.Register32 // 0x3CC
	ARB_TIMEOUT_RX             volatile.Register32 // 0x3D0
	WEIGHT_EN_TX               volatile.Register32 // 0x3D4
	WEIGHT_EN_RX               volatile.Register32 // 0x3D8
}

// AHB_DMA.IN_INT_RAW_CH0: Raw status interrupt of channel 0
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_ST_CH0: Masked interrupt of channel 0
func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_ENA_CH0: Interrupt enable bits of channel 0
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_CLR_CH0: Interrupt clear bits of channel 0
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_RAW_CH1: Raw status interrupt of channel 0
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_ST_CH1: Masked interrupt of channel 0
func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_ENA_CH1: Interrupt enable bits of channel 0
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_CLR_CH1: Interrupt clear bits of channel 0
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_RAW_CH2: Raw status interrupt of channel 0
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_ST_CH2: Masked interrupt of channel 0
func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_ENA_CH2: Interrupt enable bits of channel 0
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6
}

// AHB_DMA.IN_INT_CLR_CH2: Interrupt clear bits of channel 0
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6
}

// AHB_DMA.OUT_INT_RAW_CH0: Raw status interrupt of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_ST_CH0: Masked interrupt of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_ENA_CH0: Interrupt enable bits of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_CLR_CH0: Interrupt clear bits of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_RAW_CH1: Raw status interrupt of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_ST_CH1: Masked interrupt of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_ENA_CH1: Interrupt enable bits of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_CLR_CH1: Interrupt clear bits of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_RAW_CH2: Raw status interrupt of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_ST_CH2: Masked interrupt of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_ENA_CH2: Interrupt enable bits of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5
}

// AHB_DMA.OUT_INT_CLR_CH2: Interrupt clear bits of channel 0
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5
}

// AHB_DMA.AHB_TEST: reserved
func (o *AHB_DMA_Type) SetAHB_TEST_AHB_TESTMODE(value uint32) {
	volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x7)|value)
}
func (o *AHB_DMA_Type) GetAHB_TEST_AHB_TESTMODE() uint32 {
	return volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x7
}
func (o *AHB_DMA_Type) SetAHB_TEST_AHB_TESTADDR(value uint32) {
	volatile.StoreUint32(&o.AHB_TEST.Reg, volatile.LoadUint32(&o.AHB_TEST.Reg)&^(0x30)|value<<4)
}
func (o *AHB_DMA_Type) GetAHB_TEST_AHB_TESTADDR() uint32 {
	return (volatile.LoadUint32(&o.AHB_TEST.Reg) & 0x30) >> 4
}

// AHB_DMA.MISC_CONF: MISC register
func (o *AHB_DMA_Type) SetMISC_CONF_AHBM_RST_INTER(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetMISC_CONF_AHBM_RST_INTER() uint32 {
	return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 {
	return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetMISC_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetMISC_CONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3
}

// AHB_DMA.DATE: Version control register
func (o *AHB_DMA_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *AHB_DMA_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// AHB_DMA.IN_CONF0_CH0: Configure 0 register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_RST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_RST_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_DATA_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_DATA_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH0_IN_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH0_IN_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x20) >> 5
}

// AHB_DMA.IN_CONF1_CH0: Configure 1 register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12
}

// AHB_DMA.INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27
}

// AHB_DMA.IN_POP_CH0: Pop control register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_POP_CH0_INFIFO_RDATA_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value)
}
func (o *AHB_DMA_Type) GetIN_POP_CH0_INFIFO_RDATA_CH() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff
}
func (o *AHB_DMA_Type) SetIN_POP_CH0_INFIFO_POP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetIN_POP_CH0_INFIFO_POP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12
}

// AHB_DMA.IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_AUTO_RET_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_AUTO_RET_CH() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_STOP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_LINK_CH0_INLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH0_INLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH0.Reg) & 0x10) >> 4
}

// AHB_DMA.IN_STATE_CH0: Receive status of Rx channel 0
func (o *AHB_DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff
}
func (o *AHB_DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18
}
func (o *AHB_DMA_Type) SetIN_STATE_CH0_IN_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH0_IN_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20
}

// AHB_DMA.IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0
func (o *AHB_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg)
}

// AHB_DMA.IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0
func (o *AHB_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg)
}

// AHB_DMA.IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg)
}

// AHB_DMA.IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_BF0_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg)
}

// AHB_DMA.IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_BF1_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg)
}

// AHB_DMA.IN_PRI_CH0: Priority register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_PRI_CH0_RX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetIN_PRI_CH0_RX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf
}

// AHB_DMA.IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0
func (o *AHB_DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value)
}
func (o *AHB_DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f
}

// AHB_DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x40) >> 6
}

// AHB_DMA.OUT_CONF1_CH0: Configure 1 register of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12
}

// AHB_DMA.OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26
}

// AHB_DMA.OUT_PUSH_CH0: Push control register of Rx channel 0
func (o *AHB_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value)
}
func (o *AHB_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff
}
func (o *AHB_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AHB_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9
}

// AHB_DMA.OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_STOP_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH0_OUTLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH0_OUTLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH0.Reg) & 0x8) >> 3
}

// AHB_DMA.OUT_STATE_CH0: Transmit status of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff
}
func (o *AHB_DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18
}
func (o *AHB_DMA_Type) SetOUT_STATE_CH0_OUT_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH0_OUT_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20
}

// AHB_DMA.OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg)
}

// AHB_DMA.OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg)
}

// AHB_DMA.OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg)
}

// AHB_DMA.OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg)
}

// AHB_DMA.OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg)
}

// AHB_DMA.OUT_PRI_CH0: Priority register of Tx channel 0.
func (o *AHB_DMA_Type) SetOUT_PRI_CH0_TX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetOUT_PRI_CH0_TX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf
}

// AHB_DMA.OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value)
}
func (o *AHB_DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f
}

// AHB_DMA.IN_CONF0_CH1: Configure 0 register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_RST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_RST_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_DATA_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_DATA_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH1_IN_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH1_IN_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x20) >> 5
}

// AHB_DMA.IN_CONF1_CH1: Configure 1 register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12
}

// AHB_DMA.INFIFO_STATUS_CH1: Receive FIFO status of Rx channel 0
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc) >> 2
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800000) >> 23
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27
}

// AHB_DMA.IN_POP_CH1: Pop control register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_POP_CH1_INFIFO_RDATA_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value)
}
func (o *AHB_DMA_Type) GetIN_POP_CH1_INFIFO_RDATA_CH() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff
}
func (o *AHB_DMA_Type) SetIN_POP_CH1_INFIFO_POP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetIN_POP_CH1_INFIFO_POP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12
}

// AHB_DMA.IN_LINK_CH1: Link descriptor configure and control register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_AUTO_RET_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_AUTO_RET_CH() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_STOP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_LINK_CH1_INLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH1_INLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH1.Reg) & 0x10) >> 4
}

// AHB_DMA.IN_STATE_CH1: Receive status of Rx channel 0
func (o *AHB_DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff
}
func (o *AHB_DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18
}
func (o *AHB_DMA_Type) SetIN_STATE_CH1_IN_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH1_IN_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20
}

// AHB_DMA.IN_SUC_EOF_DES_ADDR_CH1: Inlink descriptor address when EOF occurs of Rx channel 0
func (o *AHB_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg)
}

// AHB_DMA.IN_ERR_EOF_DES_ADDR_CH1: Inlink descriptor address when errors occur of Rx channel 0
func (o *AHB_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg)
}

// AHB_DMA.IN_DSCR_CH1: Current inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg)
}

// AHB_DMA.IN_DSCR_BF0_CH1: The last inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_BF0_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg)
}

// AHB_DMA.IN_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_BF1_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg)
}

// AHB_DMA.IN_PRI_CH1: Priority register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_PRI_CH1_RX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetIN_PRI_CH1_RX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf
}

// AHB_DMA.IN_PERI_SEL_CH1: Peripheral selection of Rx channel 0
func (o *AHB_DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value)
}
func (o *AHB_DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f
}

// AHB_DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel 1
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_DATA_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x40) >> 6
}

// AHB_DMA.OUT_CONF1_CH1: Configure 1 register of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12
}

// AHB_DMA.OUTFIFO_STATUS_CH1: Transmit FIFO status of Tx channel 0
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xfc) >> 2
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26
}

// AHB_DMA.OUT_PUSH_CH1: Push control register of Rx channel 0
func (o *AHB_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value)
}
func (o *AHB_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff
}
func (o *AHB_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AHB_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9
}

// AHB_DMA.OUT_LINK_CH1: Link descriptor configure and control register of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_STOP_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH1_OUTLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH1_OUTLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH1.Reg) & 0x8) >> 3
}

// AHB_DMA.OUT_STATE_CH1: Transmit status of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff
}
func (o *AHB_DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18
}
func (o *AHB_DMA_Type) SetOUT_STATE_CH1_OUT_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH1_OUT_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20
}

// AHB_DMA.OUT_EOF_DES_ADDR_CH1: Outlink descriptor address when EOF occurs of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg)
}

// AHB_DMA.OUT_EOF_BFR_DES_ADDR_CH1: The last outlink descriptor address when EOF occurs of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg)
}

// AHB_DMA.OUT_DSCR_CH1: Current inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg)
}

// AHB_DMA.OUT_DSCR_BF0_CH1: The last inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg)
}

// AHB_DMA.OUT_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg)
}

// AHB_DMA.OUT_PRI_CH1: Priority register of Tx channel 0.
func (o *AHB_DMA_Type) SetOUT_PRI_CH1_TX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetOUT_PRI_CH1_TX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf
}

// AHB_DMA.OUT_PERI_SEL_CH1: Peripheral selection of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value)
}
func (o *AHB_DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f
}

// AHB_DMA.IN_CONF0_CH2: Configure 0 register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_RST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_RST_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_DATA_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_DATA_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetIN_CONF0_CH2_IN_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetIN_CONF0_CH2_IN_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x20) >> 5
}

// AHB_DMA.IN_CONF1_CH2: Configure 1 register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12
}

// AHB_DMA.INFIFO_STATUS_CH2: Receive FIFO status of Rx channel 0
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc) >> 2
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800000) >> 23
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26
}
func (o *AHB_DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27)
}
func (o *AHB_DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27
}

// AHB_DMA.IN_POP_CH2: Pop control register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_POP_CH2_INFIFO_RDATA_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value)
}
func (o *AHB_DMA_Type) GetIN_POP_CH2_INFIFO_RDATA_CH() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff
}
func (o *AHB_DMA_Type) SetIN_POP_CH2_INFIFO_POP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetIN_POP_CH2_INFIFO_POP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12
}

// AHB_DMA.IN_LINK_CH2: Link descriptor configure and control register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_AUTO_RET_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_AUTO_RET_CH() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_STOP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetIN_LINK_CH2_INLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetIN_LINK_CH2_INLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CH2.Reg) & 0x10) >> 4
}

// AHB_DMA.IN_STATE_CH2: Receive status of Rx channel 0
func (o *AHB_DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff
}
func (o *AHB_DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18
}
func (o *AHB_DMA_Type) SetIN_STATE_CH2_IN_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20)
}
func (o *AHB_DMA_Type) GetIN_STATE_CH2_IN_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20
}

// AHB_DMA.IN_SUC_EOF_DES_ADDR_CH2: Inlink descriptor address when EOF occurs of Rx channel 0
func (o *AHB_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg)
}

// AHB_DMA.IN_ERR_EOF_DES_ADDR_CH2: Inlink descriptor address when errors occur of Rx channel 0
func (o *AHB_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg)
}

// AHB_DMA.IN_DSCR_CH2: Current inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg)
}

// AHB_DMA.IN_DSCR_BF0_CH2: The last inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_BF0_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg)
}

// AHB_DMA.IN_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Rx channel 0
func (o *AHB_DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_DSCR_BF1_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg)
}

// AHB_DMA.IN_PRI_CH2: Priority register of Rx channel 0
func (o *AHB_DMA_Type) SetIN_PRI_CH2_RX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetIN_PRI_CH2_RX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf
}

// AHB_DMA.IN_PERI_SEL_CH2: Peripheral selection of Rx channel 0
func (o *AHB_DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value)
}
func (o *AHB_DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f
}

// AHB_DMA.OUT_CONF0_CH1: Configure 0 register of Tx channel 1
func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_RST_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_RST_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_DATA_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_DATA_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x20) >> 5
}
func (o *AHB_DMA_Type) SetOUT_CONF0_CH1_OUT_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AHB_DMA_Type) GetOUT_CONF0_CH1_OUT_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x40) >> 6
}

// AHB_DMA.OUT_CONF1_CH2: Configure 1 register of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AHB_DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12
}

// AHB_DMA.OUTFIFO_STATUS_CH2: Transmit FIFO status of Tx channel 0
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xfc) >> 2
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25
}
func (o *AHB_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26)
}
func (o *AHB_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26
}

// AHB_DMA.OUT_PUSH_CH2: Push control register of Rx channel 0
func (o *AHB_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value)
}
func (o *AHB_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff
}
func (o *AHB_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AHB_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9
}

// AHB_DMA.OUT_LINK_CH2: Link descriptor configure and control register of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_STOP_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x1
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x2) >> 1
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x4) >> 2
}
func (o *AHB_DMA_Type) SetOUT_LINK_CH2_OUTLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AHB_DMA_Type) GetOUT_LINK_CH2_OUTLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CH2.Reg) & 0x8) >> 3
}

// AHB_DMA.OUT_STATE_CH2: Transmit status of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff
}
func (o *AHB_DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18
}
func (o *AHB_DMA_Type) SetOUT_STATE_CH2_OUT_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20)
}
func (o *AHB_DMA_Type) GetOUT_STATE_CH2_OUT_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20
}

// AHB_DMA.OUT_EOF_DES_ADDR_CH2: Outlink descriptor address when EOF occurs of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg)
}

// AHB_DMA.OUT_EOF_BFR_DES_ADDR_CH2: The last outlink descriptor address when EOF occurs of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg)
}

// AHB_DMA.OUT_DSCR_CH2: Current inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg)
}

// AHB_DMA.OUT_DSCR_BF0_CH2: The last inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg)
}

// AHB_DMA.OUT_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg)
}

// AHB_DMA.OUT_PRI_CH2: Priority register of Tx channel 0.
func (o *AHB_DMA_Type) SetOUT_PRI_CH2_TX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetOUT_PRI_CH2_TX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf
}

// AHB_DMA.OUT_PERI_SEL_CH2: Peripheral selection of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value)
}
func (o *AHB_DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f
}

// AHB_DMA.OUT_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AHB_DMA_Type) SetOUT_CRC_INIT_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_INIT_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg)
}

// AHB_DMA.TX_CRC_WIDTH_CH0: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AHB_DMA_Type) SetTX_CRC_WIDTH_CH0_TX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg)&^(0x3)|value)
}
func (o *AHB_DMA_Type) GetTX_CRC_WIDTH_CH0_TX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg) & 0x3
}
func (o *AHB_DMA_Type) SetTX_CRC_WIDTH_CH0_TX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetTX_CRC_WIDTH_CH0_TX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg) & 0x4) >> 2
}

// AHB_DMA.OUT_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
func (o *AHB_DMA_Type) SetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg) & 0x1
}

// AHB_DMA.OUT_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
func (o *AHB_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg)
}

// AHB_DMA.TX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
func (o *AHB_DMA_Type) SetTX_CRC_EN_WR_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_EN_WR_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg)
}

// AHB_DMA.TX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
func (o *AHB_DMA_Type) SetTX_CRC_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH0.Reg)
}

// AHB_DMA.TX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xff)|value)
}
func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xff
}

// AHB_DMA.TX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg)
}

// AHB_DMA.TX_CH_ARB_WEIGH_CH0: This register is used to config ch0 arbiter weigh
func (o *AHB_DMA_Type) SetTX_CH_ARB_WEIGH_CH0_TX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CH_ARB_WEIGH_CH0.Reg, volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH0.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetTX_CH_ARB_WEIGH_CH0_TX_CH_ARB_WEIGH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH0.Reg) & 0xf
}

// AHB_DMA.TX_ARB_WEIGH_OPT_DIR_CH0: This register is used to config off or on weigh optimization
func (o *AHB_DMA_Type) SetTX_ARB_WEIGH_OPT_DIR_CH0_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH0.Reg, volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetTX_ARB_WEIGH_OPT_DIR_CH0_TX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH0.Reg) & 0x1
}

// AHB_DMA.OUT_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AHB_DMA_Type) SetOUT_CRC_INIT_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_INIT_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg)
}

// AHB_DMA.TX_CRC_WIDTH_CH1: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AHB_DMA_Type) SetTX_CRC_WIDTH_CH1_TX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg)&^(0x3)|value)
}
func (o *AHB_DMA_Type) GetTX_CRC_WIDTH_CH1_TX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg) & 0x3
}
func (o *AHB_DMA_Type) SetTX_CRC_WIDTH_CH1_TX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetTX_CRC_WIDTH_CH1_TX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg) & 0x4) >> 2
}

// AHB_DMA.OUT_CRC_CLEAR_CH1: This register is used to clear ch0 crc result
func (o *AHB_DMA_Type) SetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg) & 0x1
}

// AHB_DMA.OUT_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result
func (o *AHB_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg)
}

// AHB_DMA.TX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit
func (o *AHB_DMA_Type) SetTX_CRC_EN_WR_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_EN_WR_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg)
}

// AHB_DMA.TX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr
func (o *AHB_DMA_Type) SetTX_CRC_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH1.Reg)
}

// AHB_DMA.TX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en
func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xff)|value)
}
func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xff
}

// AHB_DMA.TX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en
func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg)
}

// AHB_DMA.TX_CH_ARB_WEIGH_CH1: This register is used to config ch0 arbiter weigh
func (o *AHB_DMA_Type) SetTX_CH_ARB_WEIGH_CH1_TX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CH_ARB_WEIGH_CH1.Reg, volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH1.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetTX_CH_ARB_WEIGH_CH1_TX_CH_ARB_WEIGH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH1.Reg) & 0xf
}

// AHB_DMA.TX_ARB_WEIGH_OPT_DIR_CH1: This register is used to config off or on weigh optimization
func (o *AHB_DMA_Type) SetTX_ARB_WEIGH_OPT_DIR_CH1_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH1.Reg, volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetTX_ARB_WEIGH_OPT_DIR_CH1_TX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH1.Reg) & 0x1
}

// AHB_DMA.OUT_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AHB_DMA_Type) SetOUT_CRC_INIT_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_INIT_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg)
}

// AHB_DMA.TX_CRC_WIDTH_CH2: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AHB_DMA_Type) SetTX_CRC_WIDTH_CH2_TX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg)&^(0x3)|value)
}
func (o *AHB_DMA_Type) GetTX_CRC_WIDTH_CH2_TX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg) & 0x3
}
func (o *AHB_DMA_Type) SetTX_CRC_WIDTH_CH2_TX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetTX_CRC_WIDTH_CH2_TX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg) & 0x4) >> 2
}

// AHB_DMA.OUT_CRC_CLEAR_CH2: This register is used to clear ch0 crc result
func (o *AHB_DMA_Type) SetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg) & 0x1
}

// AHB_DMA.OUT_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result
func (o *AHB_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg)
}

// AHB_DMA.TX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit
func (o *AHB_DMA_Type) SetTX_CRC_EN_WR_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_EN_WR_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg)
}

// AHB_DMA.TX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr
func (o *AHB_DMA_Type) SetTX_CRC_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH2.Reg)
}

// AHB_DMA.TX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en
func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xff)|value)
}
func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xff
}

// AHB_DMA.TX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en
func (o *AHB_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg)
}

// AHB_DMA.TX_CH_ARB_WEIGH_CH2: This register is used to config ch0 arbiter weigh
func (o *AHB_DMA_Type) SetTX_CH_ARB_WEIGH_CH2_TX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CH_ARB_WEIGH_CH2.Reg, volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH2.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetTX_CH_ARB_WEIGH_CH2_TX_CH_ARB_WEIGH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CH_ARB_WEIGH_CH2.Reg) & 0xf
}

// AHB_DMA.TX_ARB_WEIGH_OPT_DIR_CH2: This register is used to config off or on weigh optimization
func (o *AHB_DMA_Type) SetTX_ARB_WEIGH_OPT_DIR_CH2_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH2.Reg, volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetTX_ARB_WEIGH_OPT_DIR_CH2_TX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return volatile.LoadUint32(&o.TX_ARB_WEIGH_OPT_DIR_CH2.Reg) & 0x1
}

// AHB_DMA.IN_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AHB_DMA_Type) SetIN_CRC_INIT_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_CRC_INIT_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH0.Reg)
}

// AHB_DMA.RX_CRC_WIDTH_CH0: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AHB_DMA_Type) SetRX_CRC_WIDTH_CH0_RX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg)&^(0x3)|value)
}
func (o *AHB_DMA_Type) GetRX_CRC_WIDTH_CH0_RX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg) & 0x3
}
func (o *AHB_DMA_Type) SetRX_CRC_WIDTH_CH0_RX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetRX_CRC_WIDTH_CH0_RX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg) & 0x4) >> 2
}

// AHB_DMA.IN_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
func (o *AHB_DMA_Type) SetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg) & 0x1
}

// AHB_DMA.IN_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
func (o *AHB_DMA_Type) SetIN_CRC_FINAL_RESULT_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_CRC_FINAL_RESULT_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg)
}

// AHB_DMA.RX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
func (o *AHB_DMA_Type) SetRX_CRC_EN_WR_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_EN_WR_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg)
}

// AHB_DMA.RX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
func (o *AHB_DMA_Type) SetRX_CRC_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH0.Reg)
}

// AHB_DMA.RX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xff)|value)
}
func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xff
}

// AHB_DMA.RX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg)
}

// AHB_DMA.RX_CH_ARB_WEIGH_CH0: This register is used to config ch0 arbiter weigh
func (o *AHB_DMA_Type) SetRX_CH_ARB_WEIGH_CH0_RX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CH_ARB_WEIGH_CH0.Reg, volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH0.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetRX_CH_ARB_WEIGH_CH0_RX_CH_ARB_WEIGH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH0.Reg) & 0xf
}

// AHB_DMA.RX_ARB_WEIGH_OPT_DIR_CH0: This register is used to config off or on weigh optimization
func (o *AHB_DMA_Type) SetRX_ARB_WEIGH_OPT_DIR_CH0_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH0.Reg, volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH0.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetRX_ARB_WEIGH_OPT_DIR_CH0_RX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH0.Reg) & 0x1
}

// AHB_DMA.IN_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AHB_DMA_Type) SetIN_CRC_INIT_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_CRC_INIT_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH1.Reg)
}

// AHB_DMA.RX_CRC_WIDTH_CH1: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AHB_DMA_Type) SetRX_CRC_WIDTH_CH1_RX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg)&^(0x3)|value)
}
func (o *AHB_DMA_Type) GetRX_CRC_WIDTH_CH1_RX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg) & 0x3
}
func (o *AHB_DMA_Type) SetRX_CRC_WIDTH_CH1_RX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetRX_CRC_WIDTH_CH1_RX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg) & 0x4) >> 2
}

// AHB_DMA.IN_CRC_CLEAR_CH1: This register is used to clear ch0 crc result
func (o *AHB_DMA_Type) SetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg) & 0x1
}

// AHB_DMA.IN_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result
func (o *AHB_DMA_Type) SetIN_CRC_FINAL_RESULT_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_CRC_FINAL_RESULT_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg)
}

// AHB_DMA.RX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit
func (o *AHB_DMA_Type) SetRX_CRC_EN_WR_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_EN_WR_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg)
}

// AHB_DMA.RX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr
func (o *AHB_DMA_Type) SetRX_CRC_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH1.Reg)
}

// AHB_DMA.RX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en
func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xff)|value)
}
func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xff
}

// AHB_DMA.RX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en
func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg)
}

// AHB_DMA.RX_CH_ARB_WEIGH_CH1: This register is used to config ch0 arbiter weigh
func (o *AHB_DMA_Type) SetRX_CH_ARB_WEIGH_CH1_RX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CH_ARB_WEIGH_CH1.Reg, volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH1.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetRX_CH_ARB_WEIGH_CH1_RX_CH_ARB_WEIGH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH1.Reg) & 0xf
}

// AHB_DMA.RX_ARB_WEIGH_OPT_DIR_CH1: This register is used to config off or on weigh optimization
func (o *AHB_DMA_Type) SetRX_ARB_WEIGH_OPT_DIR_CH1_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH1.Reg, volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH1.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetRX_ARB_WEIGH_OPT_DIR_CH1_RX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH1.Reg) & 0x1
}

// AHB_DMA.IN_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AHB_DMA_Type) SetIN_CRC_INIT_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_CRC_INIT_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH2.Reg)
}

// AHB_DMA.RX_CRC_WIDTH_CH2: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AHB_DMA_Type) SetRX_CRC_WIDTH_CH2_RX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg)&^(0x3)|value)
}
func (o *AHB_DMA_Type) GetRX_CRC_WIDTH_CH2_RX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg) & 0x3
}
func (o *AHB_DMA_Type) SetRX_CRC_WIDTH_CH2_RX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AHB_DMA_Type) GetRX_CRC_WIDTH_CH2_RX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg) & 0x4) >> 2
}

// AHB_DMA.IN_CRC_CLEAR_CH2: This register is used to clear ch0 crc result
func (o *AHB_DMA_Type) SetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg) & 0x1
}

// AHB_DMA.IN_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result
func (o *AHB_DMA_Type) SetIN_CRC_FINAL_RESULT_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_CRC_FINAL_RESULT_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg)
}

// AHB_DMA.RX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit
func (o *AHB_DMA_Type) SetRX_CRC_EN_WR_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_EN_WR_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg)
}

// AHB_DMA.RX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr
func (o *AHB_DMA_Type) SetRX_CRC_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH2.Reg)
}

// AHB_DMA.RX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en
func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xff)|value)
}
func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xff
}

// AHB_DMA.RX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en
func (o *AHB_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg)
}

// AHB_DMA.RX_CH_ARB_WEIGH_CH2: This register is used to config ch0 arbiter weigh
func (o *AHB_DMA_Type) SetRX_CH_ARB_WEIGH_CH2_RX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CH_ARB_WEIGH_CH2.Reg, volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH2.Reg)&^(0xf)|value)
}
func (o *AHB_DMA_Type) GetRX_CH_ARB_WEIGH_CH2_RX_CH_ARB_WEIGH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CH_ARB_WEIGH_CH2.Reg) & 0xf
}

// AHB_DMA.RX_ARB_WEIGH_OPT_DIR_CH2: This register is used to config off or on weigh optimization
func (o *AHB_DMA_Type) SetRX_ARB_WEIGH_OPT_DIR_CH2_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH2.Reg, volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH2.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetRX_ARB_WEIGH_OPT_DIR_CH2_RX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return volatile.LoadUint32(&o.RX_ARB_WEIGH_OPT_DIR_CH2.Reg) & 0x1
}

// AHB_DMA.IN_LINK_ADDR_CH0: Link descriptor configure of Rx channel 0
func (o *AHB_DMA_Type) SetIN_LINK_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_LINK_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH0.Reg)
}

// AHB_DMA.IN_LINK_ADDR_CH1: Link descriptor configure of Rx channel 0
func (o *AHB_DMA_Type) SetIN_LINK_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_LINK_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH1.Reg)
}

// AHB_DMA.IN_LINK_ADDR_CH2: Link descriptor configure of Rx channel 0
func (o *AHB_DMA_Type) SetIN_LINK_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetIN_LINK_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH2.Reg)
}

// AHB_DMA.OUT_LINK_ADDR_CH0: Link descriptor configure of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_LINK_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH0.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_LINK_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH0.Reg)
}

// AHB_DMA.OUT_LINK_ADDR_CH1: Link descriptor configure of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_LINK_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH1.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_LINK_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH1.Reg)
}

// AHB_DMA.OUT_LINK_ADDR_CH2: Link descriptor configure of Tx channel 0
func (o *AHB_DMA_Type) SetOUT_LINK_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH2.Reg, value)
}
func (o *AHB_DMA_Type) GetOUT_LINK_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH2.Reg)
}

// AHB_DMA.INTR_MEM_START_ADDR: The start address of accessible address space.
func (o *AHB_DMA_Type) SetINTR_MEM_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.INTR_MEM_START_ADDR.Reg, value)
}
func (o *AHB_DMA_Type) GetINTR_MEM_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.INTR_MEM_START_ADDR.Reg)
}

// AHB_DMA.INTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error.
func (o *AHB_DMA_Type) SetINTR_MEM_END_ADDR(value uint32) {
	volatile.StoreUint32(&o.INTR_MEM_END_ADDR.Reg, value)
}
func (o *AHB_DMA_Type) GetINTR_MEM_END_ADDR() uint32 {
	return volatile.LoadUint32(&o.INTR_MEM_END_ADDR.Reg)
}

// AHB_DMA.ARB_TIMEOUT_TX: This retister is used to config arbiter time slice for tx dir
func (o *AHB_DMA_Type) SetARB_TIMEOUT_TX(value uint32) {
	volatile.StoreUint32(&o.ARB_TIMEOUT_TX.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT_TX.Reg)&^(0xffff)|value)
}
func (o *AHB_DMA_Type) GetARB_TIMEOUT_TX() uint32 {
	return volatile.LoadUint32(&o.ARB_TIMEOUT_TX.Reg) & 0xffff
}

// AHB_DMA.ARB_TIMEOUT_RX: This retister is used to config arbiter time slice for rx dir
func (o *AHB_DMA_Type) SetARB_TIMEOUT_RX(value uint32) {
	volatile.StoreUint32(&o.ARB_TIMEOUT_RX.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT_RX.Reg)&^(0xffff)|value)
}
func (o *AHB_DMA_Type) GetARB_TIMEOUT_RX() uint32 {
	return volatile.LoadUint32(&o.ARB_TIMEOUT_RX.Reg) & 0xffff
}

// AHB_DMA.WEIGHT_EN_TX: This register is used to config arbiter weigh function to on or off for tx dir
func (o *AHB_DMA_Type) SetWEIGHT_EN_TX(value uint32) {
	volatile.StoreUint32(&o.WEIGHT_EN_TX.Reg, volatile.LoadUint32(&o.WEIGHT_EN_TX.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetWEIGHT_EN_TX() uint32 {
	return volatile.LoadUint32(&o.WEIGHT_EN_TX.Reg) & 0x1
}

// AHB_DMA.WEIGHT_EN_RX: This register is used to config arbiter weigh function to on or off for rx dir
func (o *AHB_DMA_Type) SetWEIGHT_EN_RX(value uint32) {
	volatile.StoreUint32(&o.WEIGHT_EN_RX.Reg, volatile.LoadUint32(&o.WEIGHT_EN_RX.Reg)&^(0x1)|value)
}
func (o *AHB_DMA_Type) GetWEIGHT_EN_RX() uint32 {
	return volatile.LoadUint32(&o.WEIGHT_EN_RX.Reg) & 0x1
}

// LP_I2C_ANA_MST Peripheral
type ANA_I2C_MST_Type struct {
	I2C0_CTRL        volatile.Register32 // 0x0
	I2C1_CTRL        volatile.Register32 // 0x4
	I2C0_CONF        volatile.Register32 // 0x8
	I2C1_CONF        volatile.Register32 // 0xC
	I2C_BURST_CONF   volatile.Register32 // 0x10
	I2C_BURST_STATUS volatile.Register32 // 0x14
	ANA_CONF0        volatile.Register32 // 0x18
	ANA_CONF1        volatile.Register32 // 0x1C
	ANA_CONF2        volatile.Register32 // 0x20
	I2C0_CTRL1       volatile.Register32 // 0x24
	I2C1_CTRL1       volatile.Register32 // 0x28
	HW_I2C_CTRL      volatile.Register32 // 0x2C
	NOUSE            volatile.Register32 // 0x30
	CLK160M          volatile.Register32 // 0x34
	DATE             volatile.Register32 // 0x38
}

// ANA_I2C_MST.I2C0_CTRL: need des
func (o *ANA_I2C_MST_Type) SetI2C0_CTRL(value uint32) {
	volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x1ffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetI2C0_CTRL() uint32 {
	return volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x1ffffff
}
func (o *ANA_I2C_MST_Type) SetI2C0_CTRL_I2C0_BUSY(value uint32) {
	volatile.StoreUint32(&o.I2C0_CTRL.Reg, volatile.LoadUint32(&o.I2C0_CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *ANA_I2C_MST_Type) GetI2C0_CTRL_I2C0_BUSY() uint32 {
	return (volatile.LoadUint32(&o.I2C0_CTRL.Reg) & 0x2000000) >> 25
}

// ANA_I2C_MST.I2C1_CTRL: need des
func (o *ANA_I2C_MST_Type) SetI2C1_CTRL(value uint32) {
	volatile.StoreUint32(&o.I2C1_CTRL.Reg, volatile.LoadUint32(&o.I2C1_CTRL.Reg)&^(0x1ffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetI2C1_CTRL() uint32 {
	return volatile.LoadUint32(&o.I2C1_CTRL.Reg) & 0x1ffffff
}
func (o *ANA_I2C_MST_Type) SetI2C1_CTRL_I2C1_BUSY(value uint32) {
	volatile.StoreUint32(&o.I2C1_CTRL.Reg, volatile.LoadUint32(&o.I2C1_CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *ANA_I2C_MST_Type) GetI2C1_CTRL_I2C1_BUSY() uint32 {
	return (volatile.LoadUint32(&o.I2C1_CTRL.Reg) & 0x2000000) >> 25
}

// ANA_I2C_MST.I2C0_CONF: need des
func (o *ANA_I2C_MST_Type) SetI2C0_CONF(value uint32) {
	volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetI2C0_CONF() uint32 {
	return volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xffffff
}
func (o *ANA_I2C_MST_Type) SetI2C0_CONF_I2C0_STATUS(value uint32) {
	volatile.StoreUint32(&o.I2C0_CONF.Reg, volatile.LoadUint32(&o.I2C0_CONF.Reg)&^(0xff000000)|value<<24)
}
func (o *ANA_I2C_MST_Type) GetI2C0_CONF_I2C0_STATUS() uint32 {
	return (volatile.LoadUint32(&o.I2C0_CONF.Reg) & 0xff000000) >> 24
}

// ANA_I2C_MST.I2C1_CONF: need des
func (o *ANA_I2C_MST_Type) SetI2C1_CONF(value uint32) {
	volatile.StoreUint32(&o.I2C1_CONF.Reg, volatile.LoadUint32(&o.I2C1_CONF.Reg)&^(0xffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetI2C1_CONF() uint32 {
	return volatile.LoadUint32(&o.I2C1_CONF.Reg) & 0xffffff
}
func (o *ANA_I2C_MST_Type) SetI2C1_CONF_I2C1_STATUS(value uint32) {
	volatile.StoreUint32(&o.I2C1_CONF.Reg, volatile.LoadUint32(&o.I2C1_CONF.Reg)&^(0xff000000)|value<<24)
}
func (o *ANA_I2C_MST_Type) GetI2C1_CONF_I2C1_STATUS() uint32 {
	return (volatile.LoadUint32(&o.I2C1_CONF.Reg) & 0xff000000) >> 24
}

// ANA_I2C_MST.I2C_BURST_CONF: need des
func (o *ANA_I2C_MST_Type) SetI2C_BURST_CONF(value uint32) {
	volatile.StoreUint32(&o.I2C_BURST_CONF.Reg, value)
}
func (o *ANA_I2C_MST_Type) GetI2C_BURST_CONF() uint32 {
	return volatile.LoadUint32(&o.I2C_BURST_CONF.Reg)
}

// ANA_I2C_MST.I2C_BURST_STATUS: need des
func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST_BURST_DONE(value uint32) {
	volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0x1)|value)
}
func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST_BURST_DONE() uint32 {
	return volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0x1
}
func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST0_BURST_ERR_FLAG(value uint32) {
	volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST0_BURST_ERR_FLAG() uint32 {
	return (volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0x2) >> 1
}
func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST1_BURST_ERR_FLAG(value uint32) {
	volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST1_BURST_ERR_FLAG() uint32 {
	return (volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0x4) >> 2
}
func (o *ANA_I2C_MST_Type) SetI2C_BURST_STATUS_I2C_MST_BURST_TIMEOUT_CNT(value uint32) {
	volatile.StoreUint32(&o.I2C_BURST_STATUS.Reg, volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg)&^(0xfff00000)|value<<20)
}
func (o *ANA_I2C_MST_Type) GetI2C_BURST_STATUS_I2C_MST_BURST_TIMEOUT_CNT() uint32 {
	return (volatile.LoadUint32(&o.I2C_BURST_STATUS.Reg) & 0xfff00000) >> 20
}

// ANA_I2C_MST.ANA_CONF0: need des
func (o *ANA_I2C_MST_Type) SetANA_CONF0(value uint32) {
	volatile.StoreUint32(&o.ANA_CONF0.Reg, volatile.LoadUint32(&o.ANA_CONF0.Reg)&^(0xffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetANA_CONF0() uint32 {
	return volatile.LoadUint32(&o.ANA_CONF0.Reg) & 0xffffff
}
func (o *ANA_I2C_MST_Type) SetANA_CONF0_ANA_STATUS0(value uint32) {
	volatile.StoreUint32(&o.ANA_CONF0.Reg, volatile.LoadUint32(&o.ANA_CONF0.Reg)&^(0xff000000)|value<<24)
}
func (o *ANA_I2C_MST_Type) GetANA_CONF0_ANA_STATUS0() uint32 {
	return (volatile.LoadUint32(&o.ANA_CONF0.Reg) & 0xff000000) >> 24
}

// ANA_I2C_MST.ANA_CONF1: need des
func (o *ANA_I2C_MST_Type) SetANA_CONF1(value uint32) {
	volatile.StoreUint32(&o.ANA_CONF1.Reg, volatile.LoadUint32(&o.ANA_CONF1.Reg)&^(0xffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetANA_CONF1() uint32 {
	return volatile.LoadUint32(&o.ANA_CONF1.Reg) & 0xffffff
}
func (o *ANA_I2C_MST_Type) SetANA_CONF1_ANA_STATUS1(value uint32) {
	volatile.StoreUint32(&o.ANA_CONF1.Reg, volatile.LoadUint32(&o.ANA_CONF1.Reg)&^(0xff000000)|value<<24)
}
func (o *ANA_I2C_MST_Type) GetANA_CONF1_ANA_STATUS1() uint32 {
	return (volatile.LoadUint32(&o.ANA_CONF1.Reg) & 0xff000000) >> 24
}

// ANA_I2C_MST.ANA_CONF2: need des
func (o *ANA_I2C_MST_Type) SetANA_CONF2(value uint32) {
	volatile.StoreUint32(&o.ANA_CONF2.Reg, volatile.LoadUint32(&o.ANA_CONF2.Reg)&^(0xffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetANA_CONF2() uint32 {
	return volatile.LoadUint32(&o.ANA_CONF2.Reg) & 0xffffff
}
func (o *ANA_I2C_MST_Type) SetANA_CONF2_ANA_STATUS2(value uint32) {
	volatile.StoreUint32(&o.ANA_CONF2.Reg, volatile.LoadUint32(&o.ANA_CONF2.Reg)&^(0xff000000)|value<<24)
}
func (o *ANA_I2C_MST_Type) GetANA_CONF2_ANA_STATUS2() uint32 {
	return (volatile.LoadUint32(&o.ANA_CONF2.Reg) & 0xff000000) >> 24
}

// ANA_I2C_MST.I2C0_CTRL1: need des
func (o *ANA_I2C_MST_Type) SetI2C0_CTRL1_I2C0_SCL_PULSE_DUR(value uint32) {
	volatile.StoreUint32(&o.I2C0_CTRL1.Reg, volatile.LoadUint32(&o.I2C0_CTRL1.Reg)&^(0x3f)|value)
}
func (o *ANA_I2C_MST_Type) GetI2C0_CTRL1_I2C0_SCL_PULSE_DUR() uint32 {
	return volatile.LoadUint32(&o.I2C0_CTRL1.Reg) & 0x3f
}
func (o *ANA_I2C_MST_Type) SetI2C0_CTRL1_I2C0_SDA_SIDE_GUARD(value uint32) {
	volatile.StoreUint32(&o.I2C0_CTRL1.Reg, volatile.LoadUint32(&o.I2C0_CTRL1.Reg)&^(0x7c0)|value<<6)
}
func (o *ANA_I2C_MST_Type) GetI2C0_CTRL1_I2C0_SDA_SIDE_GUARD() uint32 {
	return (volatile.LoadUint32(&o.I2C0_CTRL1.Reg) & 0x7c0) >> 6
}

// ANA_I2C_MST.I2C1_CTRL1: need des
func (o *ANA_I2C_MST_Type) SetI2C1_CTRL1_I2C1_SCL_PULSE_DUR(value uint32) {
	volatile.StoreUint32(&o.I2C1_CTRL1.Reg, volatile.LoadUint32(&o.I2C1_CTRL1.Reg)&^(0x3f)|value)
}
func (o *ANA_I2C_MST_Type) GetI2C1_CTRL1_I2C1_SCL_PULSE_DUR() uint32 {
	return volatile.LoadUint32(&o.I2C1_CTRL1.Reg) & 0x3f
}
func (o *ANA_I2C_MST_Type) SetI2C1_CTRL1_I2C1_SDA_SIDE_GUARD(value uint32) {
	volatile.StoreUint32(&o.I2C1_CTRL1.Reg, volatile.LoadUint32(&o.I2C1_CTRL1.Reg)&^(0x7c0)|value<<6)
}
func (o *ANA_I2C_MST_Type) GetI2C1_CTRL1_I2C1_SDA_SIDE_GUARD() uint32 {
	return (volatile.LoadUint32(&o.I2C1_CTRL1.Reg) & 0x7c0) >> 6
}

// ANA_I2C_MST.HW_I2C_CTRL: need des
func (o *ANA_I2C_MST_Type) SetHW_I2C_CTRL_HW_I2C_SCL_PULSE_DUR(value uint32) {
	volatile.StoreUint32(&o.HW_I2C_CTRL.Reg, volatile.LoadUint32(&o.HW_I2C_CTRL.Reg)&^(0x3f)|value)
}
func (o *ANA_I2C_MST_Type) GetHW_I2C_CTRL_HW_I2C_SCL_PULSE_DUR() uint32 {
	return volatile.LoadUint32(&o.HW_I2C_CTRL.Reg) & 0x3f
}
func (o *ANA_I2C_MST_Type) SetHW_I2C_CTRL_HW_I2C_SDA_SIDE_GUARD(value uint32) {
	volatile.StoreUint32(&o.HW_I2C_CTRL.Reg, volatile.LoadUint32(&o.HW_I2C_CTRL.Reg)&^(0x7c0)|value<<6)
}
func (o *ANA_I2C_MST_Type) GetHW_I2C_CTRL_HW_I2C_SDA_SIDE_GUARD() uint32 {
	return (volatile.LoadUint32(&o.HW_I2C_CTRL.Reg) & 0x7c0) >> 6
}
func (o *ANA_I2C_MST_Type) SetHW_I2C_CTRL_ARBITER_DIS(value uint32) {
	volatile.StoreUint32(&o.HW_I2C_CTRL.Reg, volatile.LoadUint32(&o.HW_I2C_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *ANA_I2C_MST_Type) GetHW_I2C_CTRL_ARBITER_DIS() uint32 {
	return (volatile.LoadUint32(&o.HW_I2C_CTRL.Reg) & 0x800) >> 11
}

// ANA_I2C_MST.NOUSE: need des
func (o *ANA_I2C_MST_Type) SetNOUSE(value uint32) {
	volatile.StoreUint32(&o.NOUSE.Reg, value)
}
func (o *ANA_I2C_MST_Type) GetNOUSE() uint32 {
	return volatile.LoadUint32(&o.NOUSE.Reg)
}

// ANA_I2C_MST.CLK160M: need des
func (o *ANA_I2C_MST_Type) SetCLK160M_CLK_I2C_MST_SEL_160M(value uint32) {
	volatile.StoreUint32(&o.CLK160M.Reg, volatile.LoadUint32(&o.CLK160M.Reg)&^(0x1)|value)
}
func (o *ANA_I2C_MST_Type) GetCLK160M_CLK_I2C_MST_SEL_160M() uint32 {
	return volatile.LoadUint32(&o.CLK160M.Reg) & 0x1
}

// ANA_I2C_MST.DATE: need des
func (o *ANA_I2C_MST_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *ANA_I2C_MST_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}
func (o *ANA_I2C_MST_Type) SetDATE_I2C_MST_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x10000000)|value<<28)
}
func (o *ANA_I2C_MST_Type) GetDATE_I2C_MST_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DATE.Reg) & 0x10000000) >> 28
}

// Debug Assist
type ASSIST_DEBUG_Type struct {
	CORE_0_INTR_ENA                        volatile.Register32 // 0x0
	CORE_0_INTR_RAW                        volatile.Register32 // 0x4
	CORE_0_INTR_RLS                        volatile.Register32 // 0x8
	CORE_0_INTR_CLR                        volatile.Register32 // 0xC
	CORE_0_AREA_DRAM0_0_MIN                volatile.Register32 // 0x10
	CORE_0_AREA_DRAM0_0_MAX                volatile.Register32 // 0x14
	CORE_0_AREA_DRAM0_1_MIN                volatile.Register32 // 0x18
	CORE_0_AREA_DRAM0_1_MAX                volatile.Register32 // 0x1C
	CORE_0_AREA_PIF_0_MIN                  volatile.Register32 // 0x20
	CORE_0_AREA_PIF_0_MAX                  volatile.Register32 // 0x24
	CORE_0_AREA_PIF_1_MIN                  volatile.Register32 // 0x28
	CORE_0_AREA_PIF_1_MAX                  volatile.Register32 // 0x2C
	CORE_0_AREA_PC                         volatile.Register32 // 0x30
	CORE_0_AREA_SP                         volatile.Register32 // 0x34
	CORE_0_SP_MIN                          volatile.Register32 // 0x38
	CORE_0_SP_MAX                          volatile.Register32 // 0x3C
	CORE_0_SP_PC                           volatile.Register32 // 0x40
	CORE_0_RCD_EN                          volatile.Register32 // 0x44
	CORE_0_RCD_PDEBUGPC                    volatile.Register32 // 0x48
	CORE_0_RCD_PDEBUGSP                    volatile.Register32 // 0x4C
	CORE_0_IRAM0_EXCEPTION_MONITOR_0       volatile.Register32 // 0x50
	CORE_0_IRAM0_EXCEPTION_MONITOR_1       volatile.Register32 // 0x54
	CORE_0_DRAM0_EXCEPTION_MONITOR_0       volatile.Register32 // 0x58
	CORE_0_DRAM0_EXCEPTION_MONITOR_1       volatile.Register32 // 0x5C
	CORE_0_DRAM0_EXCEPTION_MONITOR_2       volatile.Register32 // 0x60
	CORE_0_DRAM0_EXCEPTION_MONITOR_3       volatile.Register32 // 0x64
	CORE_0_DRAM0_EXCEPTION_MONITOR_4       volatile.Register32 // 0x68
	CORE_0_DRAM0_EXCEPTION_MONITOR_5       volatile.Register32 // 0x6C
	CORE_0_LASTPC_BEFORE_EXCEPTION         volatile.Register32 // 0x70
	CORE_0_DEBUG_MODE                      volatile.Register32 // 0x74
	_                                      [8]byte
	CORE_1_INTR_ENA                        volatile.Register32 // 0x80
	CORE_1_INTR_RAW                        volatile.Register32 // 0x84
	CORE_1_INTR_RLS                        volatile.Register32 // 0x88
	CORE_1_INTR_CLR                        volatile.Register32 // 0x8C
	CORE_1_AREA_DRAM0_0_MIN                volatile.Register32 // 0x90
	CORE_1_AREA_DRAM0_0_MAX                volatile.Register32 // 0x94
	CORE_1_AREA_DRAM0_1_MIN                volatile.Register32 // 0x98
	CORE_1_AREA_DRAM0_1_MAX                volatile.Register32 // 0x9C
	CORE_1_AREA_PIF_0_MIN                  volatile.Register32 // 0xA0
	CORE_1_AREA_PIF_0_MAX                  volatile.Register32 // 0xA4
	CORE_1_AREA_PIF_1_MIN                  volatile.Register32 // 0xA8
	CORE_1_AREA_PIF_1_MAX                  volatile.Register32 // 0xAC
	CORE_1_AREA_PC                         volatile.Register32 // 0xB0
	CORE_1_AREA_SP                         volatile.Register32 // 0xB4
	CORE_1_SP_MIN                          volatile.Register32 // 0xB8
	CORE_1_SP_MAX                          volatile.Register32 // 0xBC
	CORE_1_SP_PC                           volatile.Register32 // 0xC0
	CORE_1_RCD_EN                          volatile.Register32 // 0xC4
	CORE_1_RCD_PDEBUGPC                    volatile.Register32 // 0xC8
	CORE_1_RCD_PDEBUGSP                    volatile.Register32 // 0xCC
	CORE_1_IRAM0_EXCEPTION_MONITOR_0       volatile.Register32 // 0xD0
	CORE_1_IRAM0_EXCEPTION_MONITOR_1       volatile.Register32 // 0xD4
	CORE_1_DRAM0_EXCEPTION_MONITOR_0       volatile.Register32 // 0xD8
	CORE_1_DRAM0_EXCEPTION_MONITOR_1       volatile.Register32 // 0xDC
	CORE_1_DRAM0_EXCEPTION_MONITOR_2       volatile.Register32 // 0xE0
	CORE_1_DRAM0_EXCEPTION_MONITOR_3       volatile.Register32 // 0xE4
	CORE_1_DRAM0_EXCEPTION_MONITOR_4       volatile.Register32 // 0xE8
	CORE_1_DRAM0_EXCEPTION_MONITOR_5       volatile.Register32 // 0xEC
	CORE_1_LASTPC_BEFORE_EXCEPTION         volatile.Register32 // 0xF0
	CORE_1_DEBUG_MODE                      volatile.Register32 // 0xF4
	_                                      [8]byte
	CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 volatile.Register32 // 0x100
	CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 volatile.Register32 // 0x104
	CLOCK_GATE                             volatile.Register32 // 0x108
	_                                      [752]byte
	DATE                                   volatile.Register32 // 0x3FC
}

// ASSIST_DEBUG.CORE_0_INTR_ENA: core0 monitor enable configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA() uint32 {
	return volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_ENA.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_0_INTR_RAW: core0 monitor interrupt status register
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW() uint32 {
	return volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RAW.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_0_INTR_RLS: core0 monitor interrupt enable register
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_RD_RLS() uint32 {
	return volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_RD_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_RD_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_0_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_RD_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_AREA_PIF_1_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MIN_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MIN_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MAX_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_SP_SPILL_MAX_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_RLS_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_RLS_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_RLS.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_0_INTR_CLR: core0 monitor interrupt clr register
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR() uint32 {
	return volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_0_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_INTR_CLR.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MIN.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_0_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_0_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_0_MAX.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MIN.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_DRAM0_1_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_DRAM0_1_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_DRAM0_1_MAX.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MIN.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_0_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_0_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_PIF_0_MAX.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MIN.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PIF_1_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PIF_1_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_PIF_1_MAX.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_PC: core0 area pc status register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_PC(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_PC.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_PC() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_PC.Reg)
}

// ASSIST_DEBUG.CORE_0_AREA_SP: core0 area sp status register
func (o *ASSIST_DEBUG_Type) SetCORE_0_AREA_SP(value uint32) {
	volatile.StoreUint32(&o.CORE_0_AREA_SP.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_AREA_SP() uint32 {
	return volatile.LoadUint32(&o.CORE_0_AREA_SP.Reg)
}

// ASSIST_DEBUG.CORE_0_SP_MIN: stack min value
func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_0_SP_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_0_SP_MIN.Reg)
}

// ASSIST_DEBUG.CORE_0_SP_MAX: stack max value
func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_0_SP_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_0_SP_MAX.Reg)
}

// ASSIST_DEBUG.CORE_0_SP_PC: stack monitor pc status register
func (o *ASSIST_DEBUG_Type) SetCORE_0_SP_PC(value uint32) {
	volatile.StoreUint32(&o.CORE_0_SP_PC.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_SP_PC() uint32 {
	return volatile.LoadUint32(&o.CORE_0_SP_PC.Reg)
}

// ASSIST_DEBUG.CORE_0_RCD_EN: record enable configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN(value uint32) {
	volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_RECORDEN() uint32 {
	return volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN(value uint32) {
	volatile.StoreUint32(&o.CORE_0_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_RCD_EN.Reg) & 0x2) >> 1
}

// ASSIST_DEBUG.CORE_0_RCD_PDEBUGPC: record status regsiter
func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGPC(value uint32) {
	volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGPC.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGPC() uint32 {
	return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGPC.Reg)
}

// ASSIST_DEBUG.CORE_0_RCD_PDEBUGSP: record status regsiter
func (o *ASSIST_DEBUG_Type) SetCORE_0_RCD_PDEBUGSP(value uint32) {
	volatile.StoreUint32(&o.CORE_0_RCD_PDEBUGSP.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_RCD_PDEBUGSP() uint32 {
	return volatile.LoadUint32(&o.CORE_0_RCD_PDEBUGSP.Reg)
}

// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0
func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0() uint32 {
	return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0(value uint32) {
	volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25
}

// ASSIST_DEBUG.CORE_0_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1
func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1() uint32 {
	return volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1(value uint32) {
	volatile.StoreUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25
}

// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0() uint32 {
	return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1fffe)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1fffe) >> 1
}

// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_ADDR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_ADDR_0() uint32 {
	return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff
}

// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_2(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_2() uint32 {
	return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_2.Reg)
}

// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1() uint32 {
	return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_BYTEEN_1(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1fffe)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_BYTEEN_1() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1fffe) >> 1
}

// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_4: exception monitor status register6
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_ADDR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_ADDR_1() uint32 {
	return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_4.Reg) & 0xffffff
}

// ASSIST_DEBUG.CORE_0_DRAM0_EXCEPTION_MONITOR_5: exception monitor status register7
func (o *ASSIST_DEBUG_Type) SetCORE_0_DRAM0_EXCEPTION_MONITOR_5(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_5.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DRAM0_EXCEPTION_MONITOR_5() uint32 {
	return volatile.LoadUint32(&o.CORE_0_DRAM0_EXCEPTION_MONITOR_5.Reg)
}

// ASSIST_DEBUG.CORE_0_LASTPC_BEFORE_EXCEPTION: cpu status register
func (o *ASSIST_DEBUG_Type) SetCORE_0_LASTPC_BEFORE_EXCEPTION(value uint32) {
	volatile.StoreUint32(&o.CORE_0_LASTPC_BEFORE_EXCEPTION.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_LASTPC_BEFORE_EXCEPTION() uint32 {
	return volatile.LoadUint32(&o.CORE_0_LASTPC_BEFORE_EXCEPTION.Reg)
}

// ASSIST_DEBUG.CORE_0_DEBUG_MODE: cpu status register
func (o *ASSIST_DEBUG_Type) SetCORE_0_DEBUG_MODE(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DEBUG_MODE() uint32 {
	return volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.CORE_0_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.CORE_0_DEBUG_MODE.Reg) & 0x2) >> 1
}

// ASSIST_DEBUG.CORE_1_INTR_ENA: core1 monitor enable configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA() uint32 {
	return volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_ENA.Reg, volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_ENA.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_1_INTR_RAW: core1 monitor interrupt status register
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW() uint32 {
	return volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RAW.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RAW.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_1_INTR_RLS: core1 monitor interrupt enable register
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_RD_RLS() uint32 {
	return volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_RD_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_RD_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_0_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_RD_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_RD_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_WR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_AREA_PIF_1_WR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MIN_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MIN_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MAX_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_SP_SPILL_MAX_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_RLS_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_RLS.Reg, volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_RLS_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_RLS.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_1_INTR_CLR: core1 monitor interrupt clr register
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR() uint32 {
	return volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x2) >> 1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x4)|value<<2)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x4) >> 2
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x8)|value<<3)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x8) >> 3
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x10)|value<<4)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x10) >> 4
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x20)|value<<5)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x20) >> 5
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x40)|value<<6)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x40) >> 6
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x80)|value<<7)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x80) >> 7
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x100)|value<<8)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x100) >> 8
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x200)|value<<9)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x200) >> 9
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x400)|value<<10)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x400) >> 10
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_1_INTR_CLR.Reg, volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg)&^(0x800)|value<<11)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_INTR_CLR.Reg) & 0x800) >> 11
}

// ASSIST_DEBUG.CORE_1_AREA_DRAM0_0_MIN: core1 dram0 region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_0_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_0_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_0_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_0_MIN.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_DRAM0_0_MAX: core1 dram0 region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_0_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_0_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_0_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_0_MAX.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_DRAM0_1_MIN: core1 dram0 region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_1_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_1_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_1_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_1_MIN.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_DRAM0_1_MAX: core1 dram0 region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_DRAM0_1_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_DRAM0_1_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_DRAM0_1_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_DRAM0_1_MAX.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_PIF_0_MIN: core1 PIF region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_0_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_PIF_0_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_0_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_PIF_0_MIN.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_PIF_0_MAX: core1 PIF region0 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_0_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_PIF_0_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_0_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_PIF_0_MAX.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_PIF_1_MIN: core1 PIF region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_1_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_PIF_1_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_1_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_PIF_1_MIN.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_PIF_1_MAX: core1 PIF region1 addr configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PIF_1_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_PIF_1_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PIF_1_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_PIF_1_MAX.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_PC: core1 area pc status register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_PC(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_PC.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_PC() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_PC.Reg)
}

// ASSIST_DEBUG.CORE_1_AREA_SP: core1 area sp status register
func (o *ASSIST_DEBUG_Type) SetCORE_1_AREA_SP(value uint32) {
	volatile.StoreUint32(&o.CORE_1_AREA_SP.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_AREA_SP() uint32 {
	return volatile.LoadUint32(&o.CORE_1_AREA_SP.Reg)
}

// ASSIST_DEBUG.CORE_1_SP_MIN: stack min value
func (o *ASSIST_DEBUG_Type) SetCORE_1_SP_MIN(value uint32) {
	volatile.StoreUint32(&o.CORE_1_SP_MIN.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_SP_MIN() uint32 {
	return volatile.LoadUint32(&o.CORE_1_SP_MIN.Reg)
}

// ASSIST_DEBUG.CORE_1_SP_MAX: stack max value
func (o *ASSIST_DEBUG_Type) SetCORE_1_SP_MAX(value uint32) {
	volatile.StoreUint32(&o.CORE_1_SP_MAX.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_SP_MAX() uint32 {
	return volatile.LoadUint32(&o.CORE_1_SP_MAX.Reg)
}

// ASSIST_DEBUG.CORE_1_SP_PC: stack monitor pc status register
func (o *ASSIST_DEBUG_Type) SetCORE_1_SP_PC(value uint32) {
	volatile.StoreUint32(&o.CORE_1_SP_PC.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_SP_PC() uint32 {
	return volatile.LoadUint32(&o.CORE_1_SP_PC.Reg)
}

// ASSIST_DEBUG.CORE_1_RCD_EN: record enable configuration register
func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_EN_CORE_1_RCD_RECORDEN(value uint32) {
	volatile.StoreUint32(&o.CORE_1_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_EN_CORE_1_RCD_RECORDEN() uint32 {
	return volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_EN_CORE_1_RCD_PDEBUGEN(value uint32) {
	volatile.StoreUint32(&o.CORE_1_RCD_EN.Reg, volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_EN_CORE_1_RCD_PDEBUGEN() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_RCD_EN.Reg) & 0x2) >> 1
}

// ASSIST_DEBUG.CORE_1_RCD_PDEBUGPC: record status regsiter
func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_PDEBUGPC(value uint32) {
	volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGPC.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_PDEBUGPC() uint32 {
	return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGPC.Reg)
}

// ASSIST_DEBUG.CORE_1_RCD_PDEBUGSP: record status regsiter
func (o *ASSIST_DEBUG_Type) SetCORE_1_RCD_PDEBUGSP(value uint32) {
	volatile.StoreUint32(&o.CORE_1_RCD_PDEBUGSP.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_RCD_PDEBUGSP() uint32 {
	return volatile.LoadUint32(&o.CORE_1_RCD_PDEBUGSP.Reg)
}

// ASSIST_DEBUG.CORE_1_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0
func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0() uint32 {
	return volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0xffffff
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1000000)|value<<24)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1000000) >> 24
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0(value uint32) {
	volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x2000000)|value<<25)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_0.Reg) & 0x2000000) >> 25
}

// ASSIST_DEBUG.CORE_1_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1
func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1() uint32 {
	return volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x1000000)|value<<24)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x1000000) >> 24
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1(value uint32) {
	volatile.StoreUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg)&^(0x2000000)|value<<25)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_IRAM0_EXCEPTION_MONITOR_1.Reg) & 0x2000000) >> 25
}

// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0() uint32 {
	return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_BYTEEN_0(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0x1fffe)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_BYTEEN_0() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0x1fffe) >> 1
}

// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_ADDR_0(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_ADDR_0() uint32 {
	return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xffffff
}

// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_2(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_2.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_2() uint32 {
	return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_2.Reg)
}

// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1() uint32 {
	return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_BYTEEN_1(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg)&^(0x1fffe)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_BYTEEN_1() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_3.Reg) & 0x1fffe) >> 1
}

// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_4: exception monitor status register6
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_ADDR_1(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg, volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg)&^(0xffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_ADDR_1() uint32 {
	return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_4.Reg) & 0xffffff
}

// ASSIST_DEBUG.CORE_1_DRAM0_EXCEPTION_MONITOR_5: exception monitor status register7
func (o *ASSIST_DEBUG_Type) SetCORE_1_DRAM0_EXCEPTION_MONITOR_5(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_5.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DRAM0_EXCEPTION_MONITOR_5() uint32 {
	return volatile.LoadUint32(&o.CORE_1_DRAM0_EXCEPTION_MONITOR_5.Reg)
}

// ASSIST_DEBUG.CORE_1_LASTPC_BEFORE_EXCEPTION: cpu status register
func (o *ASSIST_DEBUG_Type) SetCORE_1_LASTPC_BEFORE_EXCEPTION(value uint32) {
	volatile.StoreUint32(&o.CORE_1_LASTPC_BEFORE_EXCEPTION.Reg, value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_LASTPC_BEFORE_EXCEPTION() uint32 {
	return volatile.LoadUint32(&o.CORE_1_LASTPC_BEFORE_EXCEPTION.Reg)
}

// ASSIST_DEBUG.CORE_1_DEBUG_MODE: cpu status register
func (o *ASSIST_DEBUG_Type) SetCORE_1_DEBUG_MODE(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DEBUG_MODE() uint32 {
	return volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg) & 0x1
}
func (o *ASSIST_DEBUG_Type) SetCORE_1_DEBUG_MODE_CORE_1_DEBUG_MODULE_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.CORE_1_DEBUG_MODE.Reg, volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg)&^(0x2)|value<<1)
}
func (o *ASSIST_DEBUG_Type) GetCORE_1_DEBUG_MODE_CORE_1_DEBUG_MODULE_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.CORE_1_DEBUG_MODE.Reg) & 0x2) >> 1
}

// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register6
func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0(value uint32) {
	volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg)&^(0xfffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0() uint32 {
	return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0.Reg) & 0xfffff
}

// ASSIST_DEBUG.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register7
func (o *ASSIST_DEBUG_Type) SetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1(value uint32) {
	volatile.StoreUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg, volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg)&^(0xfffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetCORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1() uint32 {
	return volatile.LoadUint32(&o.CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1.Reg) & 0xfffff
}

// ASSIST_DEBUG.CLOCK_GATE: clock register
func (o *ASSIST_DEBUG_Type) SetCLOCK_GATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *ASSIST_DEBUG_Type) GetCLOCK_GATE_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1
}

// ASSIST_DEBUG.DATE: version register
func (o *ASSIST_DEBUG_Type) SetDATE_ASSIST_DEBUG_DATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *ASSIST_DEBUG_Type) GetDATE_ASSIST_DEBUG_DATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// AXI_DMA Peripheral
type AXI_DMA_Type struct {
	IN_INT_RAW_CH0             volatile.Register32 // 0x0
	IN_INT_ST_CH0              volatile.Register32 // 0x4
	IN_INT_ENA_CH0             volatile.Register32 // 0x8
	IN_INT_CLR_CH0             volatile.Register32 // 0xC
	IN_CONF0_CH0               volatile.Register32 // 0x10
	IN_CONF1_CH0               volatile.Register32 // 0x14
	INFIFO_STATUS_CH0          volatile.Register32 // 0x18
	IN_POP_CH0                 volatile.Register32 // 0x1C
	IN_LINK1_CH0               volatile.Register32 // 0x20
	IN_LINK2_CH0               volatile.Register32 // 0x24
	IN_STATE_CH0               volatile.Register32 // 0x28
	IN_SUC_EOF_DES_ADDR_CH0    volatile.Register32 // 0x2C
	IN_ERR_EOF_DES_ADDR_CH0    volatile.Register32 // 0x30
	IN_DSCR_CH0                volatile.Register32 // 0x34
	IN_DSCR_BF0_CH0            volatile.Register32 // 0x38
	IN_DSCR_BF1_CH0            volatile.Register32 // 0x3C
	IN_PRI_CH0                 volatile.Register32 // 0x40
	IN_PERI_SEL_CH0            volatile.Register32 // 0x44
	IN_CRC_INIT_DATA_CH0       volatile.Register32 // 0x48
	RX_CRC_WIDTH_CH0           volatile.Register32 // 0x4C
	IN_CRC_CLEAR_CH0           volatile.Register32 // 0x50
	IN_CRC_FINAL_RESULT_CH0    volatile.Register32 // 0x54
	RX_CRC_EN_WR_DATA_CH0      volatile.Register32 // 0x58
	RX_CRC_EN_ADDR_CH0         volatile.Register32 // 0x5C
	RX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x60
	RX_CRC_DATA_EN_ADDR_CH0    volatile.Register32 // 0x64
	IN_INT_RAW_CH1             volatile.Register32 // 0x68
	IN_INT_ST_CH1              volatile.Register32 // 0x6C
	IN_INT_ENA_CH1             volatile.Register32 // 0x70
	IN_INT_CLR_CH1             volatile.Register32 // 0x74
	IN_CONF0_CH1               volatile.Register32 // 0x78
	IN_CONF1_CH1               volatile.Register32 // 0x7C
	INFIFO_STATUS_CH1          volatile.Register32 // 0x80
	IN_POP_CH1                 volatile.Register32 // 0x84
	IN_LINK1_CH1               volatile.Register32 // 0x88
	IN_LINK2_CH1               volatile.Register32 // 0x8C
	IN_STATE_CH1               volatile.Register32 // 0x90
	IN_SUC_EOF_DES_ADDR_CH1    volatile.Register32 // 0x94
	IN_ERR_EOF_DES_ADDR_CH1    volatile.Register32 // 0x98
	IN_DSCR_CH1                volatile.Register32 // 0x9C
	IN_DSCR_BF0_CH1            volatile.Register32 // 0xA0
	IN_DSCR_BF1_CH1            volatile.Register32 // 0xA4
	IN_PRI_CH1                 volatile.Register32 // 0xA8
	IN_PERI_SEL_CH1            volatile.Register32 // 0xAC
	IN_CRC_INIT_DATA_CH1       volatile.Register32 // 0xB0
	RX_CRC_WIDTH_CH1           volatile.Register32 // 0xB4
	IN_CRC_CLEAR_CH1           volatile.Register32 // 0xB8
	IN_CRC_FINAL_RESULT_CH1    volatile.Register32 // 0xBC
	RX_CRC_EN_WR_DATA_CH1      volatile.Register32 // 0xC0
	RX_CRC_EN_ADDR_CH1         volatile.Register32 // 0xC4
	RX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0xC8
	RX_CRC_DATA_EN_ADDR_CH1    volatile.Register32 // 0xCC
	IN_INT_RAW_CH2             volatile.Register32 // 0xD0
	IN_INT_ST_CH2              volatile.Register32 // 0xD4
	IN_INT_ENA_CH2             volatile.Register32 // 0xD8
	IN_INT_CLR_CH2             volatile.Register32 // 0xDC
	IN_CONF0_CH2               volatile.Register32 // 0xE0
	IN_CONF1_CH2               volatile.Register32 // 0xE4
	INFIFO_STATUS_CH2          volatile.Register32 // 0xE8
	IN_POP_CH2                 volatile.Register32 // 0xEC
	IN_LINK1_CH2               volatile.Register32 // 0xF0
	IN_LINK2_CH2               volatile.Register32 // 0xF4
	IN_STATE_CH2               volatile.Register32 // 0xF8
	IN_SUC_EOF_DES_ADDR_CH2    volatile.Register32 // 0xFC
	IN_ERR_EOF_DES_ADDR_CH2    volatile.Register32 // 0x100
	IN_DSCR_CH2                volatile.Register32 // 0x104
	IN_DSCR_BF0_CH2            volatile.Register32 // 0x108
	IN_DSCR_BF1_CH2            volatile.Register32 // 0x10C
	IN_PRI_CH2                 volatile.Register32 // 0x110
	IN_PERI_SEL_CH2            volatile.Register32 // 0x114
	IN_CRC_INIT_DATA_CH2       volatile.Register32 // 0x118
	RX_CRC_WIDTH_CH2           volatile.Register32 // 0x11C
	IN_CRC_CLEAR_CH2           volatile.Register32 // 0x120
	IN_CRC_FINAL_RESULT_CH2    volatile.Register32 // 0x124
	RX_CRC_EN_WR_DATA_CH2      volatile.Register32 // 0x128
	RX_CRC_EN_ADDR_CH2         volatile.Register32 // 0x12C
	RX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x130
	RX_CRC_DATA_EN_ADDR_CH2    volatile.Register32 // 0x134
	OUT_INT_RAW_CH0            volatile.Register32 // 0x138
	OUT_INT_ST_CH0             volatile.Register32 // 0x13C
	OUT_INT_ENA_CH0            volatile.Register32 // 0x140
	OUT_INT_CLR_CH0            volatile.Register32 // 0x144
	OUT_CONF0_CH0              volatile.Register32 // 0x148
	OUT_CONF1_CH0              volatile.Register32 // 0x14C
	OUTFIFO_STATUS_CH0         volatile.Register32 // 0x150
	OUT_PUSH_CH0               volatile.Register32 // 0x154
	OUT_LINK1_CH0              volatile.Register32 // 0x158
	OUT_LINK2_CH0              volatile.Register32 // 0x15C
	OUT_STATE_CH0              volatile.Register32 // 0x160
	OUT_EOF_DES_ADDR_CH0       volatile.Register32 // 0x164
	OUT_EOF_BFR_DES_ADDR_CH0   volatile.Register32 // 0x168
	OUT_DSCR_CH0               volatile.Register32 // 0x16C
	OUT_DSCR_BF0_CH0           volatile.Register32 // 0x170
	OUT_DSCR_BF1_CH0           volatile.Register32 // 0x174
	OUT_PRI_CH0                volatile.Register32 // 0x178
	OUT_PERI_SEL_CH0           volatile.Register32 // 0x17C
	OUT_CRC_INIT_DATA_CH0      volatile.Register32 // 0x180
	TX_CRC_WIDTH_CH0           volatile.Register32 // 0x184
	OUT_CRC_CLEAR_CH0          volatile.Register32 // 0x188
	OUT_CRC_FINAL_RESULT_CH0   volatile.Register32 // 0x18C
	TX_CRC_EN_WR_DATA_CH0      volatile.Register32 // 0x190
	TX_CRC_EN_ADDR_CH0         volatile.Register32 // 0x194
	TX_CRC_DATA_EN_WR_DATA_CH0 volatile.Register32 // 0x198
	TX_CRC_DATA_EN_ADDR_CH0    volatile.Register32 // 0x19C
	OUT_INT_RAW_CH1            volatile.Register32 // 0x1A0
	OUT_INT_ST_CH1             volatile.Register32 // 0x1A4
	OUT_INT_ENA_CH1            volatile.Register32 // 0x1A8
	OUT_INT_CLR_CH1            volatile.Register32 // 0x1AC
	OUT_CONF0_CH1              volatile.Register32 // 0x1B0
	OUT_CONF1_CH1              volatile.Register32 // 0x1B4
	OUTFIFO_STATUS_CH1         volatile.Register32 // 0x1B8
	OUT_PUSH_CH1               volatile.Register32 // 0x1BC
	OUT_LINK1_CH1              volatile.Register32 // 0x1C0
	OUT_LINK2_CH1              volatile.Register32 // 0x1C4
	OUT_STATE_CH1              volatile.Register32 // 0x1C8
	OUT_EOF_DES_ADDR_CH1       volatile.Register32 // 0x1CC
	OUT_EOF_BFR_DES_ADDR_CH1   volatile.Register32 // 0x1D0
	OUT_DSCR_CH1               volatile.Register32 // 0x1D4
	OUT_DSCR_BF0_CH1           volatile.Register32 // 0x1D8
	OUT_DSCR_BF1_CH1           volatile.Register32 // 0x1DC
	OUT_PRI_CH1                volatile.Register32 // 0x1E0
	OUT_PERI_SEL_CH1           volatile.Register32 // 0x1E4
	OUT_CRC_INIT_DATA_CH1      volatile.Register32 // 0x1E8
	TX_CRC_WIDTH_CH1           volatile.Register32 // 0x1EC
	OUT_CRC_CLEAR_CH1          volatile.Register32 // 0x1F0
	OUT_CRC_FINAL_RESULT_CH1   volatile.Register32 // 0x1F4
	TX_CRC_EN_WR_DATA_CH1      volatile.Register32 // 0x1F8
	TX_CRC_EN_ADDR_CH1         volatile.Register32 // 0x1FC
	TX_CRC_DATA_EN_WR_DATA_CH1 volatile.Register32 // 0x200
	TX_CRC_DATA_EN_ADDR_CH1    volatile.Register32 // 0x204
	OUT_INT_RAW_CH2            volatile.Register32 // 0x208
	OUT_INT_ST_CH2             volatile.Register32 // 0x20C
	OUT_INT_ENA_CH2            volatile.Register32 // 0x210
	OUT_INT_CLR_CH2            volatile.Register32 // 0x214
	OUT_CONF0_CH2              volatile.Register32 // 0x218
	OUT_CONF1_CH2              volatile.Register32 // 0x21C
	OUTFIFO_STATUS_CH2         volatile.Register32 // 0x220
	OUT_PUSH_CH2               volatile.Register32 // 0x224
	OUT_LINK1_CH2              volatile.Register32 // 0x228
	OUT_LINK2_CH2              volatile.Register32 // 0x22C
	OUT_STATE_CH2              volatile.Register32 // 0x230
	OUT_EOF_DES_ADDR_CH2       volatile.Register32 // 0x234
	OUT_EOF_BFR_DES_ADDR_CH2   volatile.Register32 // 0x238
	OUT_DSCR_CH2               volatile.Register32 // 0x23C
	OUT_DSCR_BF0_CH2           volatile.Register32 // 0x240
	OUT_DSCR_BF1_CH2           volatile.Register32 // 0x244
	OUT_PRI_CH2                volatile.Register32 // 0x248
	OUT_PERI_SEL_CH2           volatile.Register32 // 0x24C
	OUT_CRC_INIT_DATA_CH2      volatile.Register32 // 0x250
	TX_CRC_WIDTH_CH2           volatile.Register32 // 0x254
	OUT_CRC_CLEAR_CH2          volatile.Register32 // 0x258
	OUT_CRC_FINAL_RESULT_CH2   volatile.Register32 // 0x25C
	TX_CRC_EN_WR_DATA_CH2      volatile.Register32 // 0x260
	TX_CRC_EN_ADDR_CH2         volatile.Register32 // 0x264
	TX_CRC_DATA_EN_WR_DATA_CH2 volatile.Register32 // 0x268
	TX_CRC_DATA_EN_ADDR_CH2    volatile.Register32 // 0x26C
	ARB_TIMEOUT                volatile.Register32 // 0x270
	WEIGHT_EN                  volatile.Register32 // 0x274
	IN_MEM_CONF                volatile.Register32 // 0x278
	INTR_MEM_START_ADDR        volatile.Register32 // 0x27C
	INTR_MEM_END_ADDR          volatile.Register32 // 0x280
	EXTR_MEM_START_ADDR        volatile.Register32 // 0x284
	EXTR_MEM_END_ADDR          volatile.Register32 // 0x288
	IN_RESET_AVAIL_CH0         volatile.Register32 // 0x28C
	IN_RESET_AVAIL_CH1         volatile.Register32 // 0x290
	IN_RESET_AVAIL_CH2         volatile.Register32 // 0x294
	OUT_RESET_AVAIL_CH0        volatile.Register32 // 0x298
	OUT_RESET_AVAIL_CH1        volatile.Register32 // 0x29C
	OUT_RESET_AVAIL_CH2        volatile.Register32 // 0x2A0
	_                          [4]byte
	MISC_CONF                  volatile.Register32 // 0x2A8
	RDN_RESULT                 volatile.Register32 // 0x2AC
	RDN_ECO_HIGH               volatile.Register32 // 0x2B0
	RDN_ECO_LOW                volatile.Register32 // 0x2B4
	WRESP_CNT                  volatile.Register32 // 0x2B8
	RRESP_CNT                  volatile.Register32 // 0x2BC
	INFIFO_STATUS1_CH0         volatile.Register32 // 0x2C0
	INFIFO_STATUS1_CH1         volatile.Register32 // 0x2C4
	INFIFO_STATUS1_CH2         volatile.Register32 // 0x2C8
	OUTFIFO_STATUS1_CH0        volatile.Register32 // 0x2CC
	OUTFIFO_STATUS1_CH1        volatile.Register32 // 0x2D0
	OUTFIFO_STATUS1_CH2        volatile.Register32 // 0x2D4
	DATE                       volatile.Register32 // 0x2D8
}

// AXI_DMA.IN_INT_RAW_CH0: Raw status interrupt of channel 0
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L1_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L1_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L1_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L1_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L2_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L2_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L2_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L2_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L3_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L3_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_L3_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_L3_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_ST_CH0: Masked interrupt of channel 0
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L1_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L1_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L1_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L1_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L3_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L3_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH0_INFIFO_L3_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH0_INFIFO_L3_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_ENA_CH0: Interrupt enable bits of channel 0
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L1_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L1_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L1_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L1_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L2_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L2_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L2_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L2_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L3_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L3_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_L3_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_L3_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_CLR_CH0: Interrupt clear bits of channel 0
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L1_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L1_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L1_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L1_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L2_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L2_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L2_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L2_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L3_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L3_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_L3_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_L3_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_CONF0_CH0: Configure 0 register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_RST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_RST_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_MEM_TRANS_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_MEM_TRANS_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_BURST_SIZE_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x70)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_BURST_SIZE_SEL_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x70) >> 4
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_CMD_DISABLE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_CMD_DISABLE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_IN_ECC_AEC_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_IN_ECC_AEC_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x200) >> 9
}

// AXI_DMA.IN_CONF1_CH0: Configure 1 register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_CONF1_CH0_IN_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF1_CH0.Reg, volatile.LoadUint32(&o.IN_CONF1_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetIN_CONF1_CH0_IN_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF1_CH0.Reg) & 0x1000) >> 12
}

// AXI_DMA.INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xfc) >> 2
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L3_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L3_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x400) >> 10
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800)|value<<11)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800) >> 11
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000) >> 12
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L1_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000)|value<<13)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L1_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000) >> 13
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000)|value<<14)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000) >> 14
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000)|value<<15)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000) >> 15
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10000) >> 16
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_L2_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_L2_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x20000) >> 17
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x800000) >> 23
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_5B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_5B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_6B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10000000)|value<<28)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_6B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10000000) >> 28
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_7B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x20000000)|value<<29)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_7B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x20000000) >> 29
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_8B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x40000000)|value<<30)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_REMAIN_UNDER_8B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x40000000) >> 30
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x80000000)|value<<31)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH0_IN_BUF_HUNGRY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x80000000) >> 31
}

// AXI_DMA.IN_POP_CH0: Pop control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_POP_CH0_INFIFO_RDATA_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0xfff)|value)
}
func (o *AXI_DMA_Type) GetIN_POP_CH0_INFIFO_RDATA_CH() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0xfff
}
func (o *AXI_DMA_Type) SetIN_POP_CH0_INFIFO_POP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetIN_POP_CH0_INFIFO_POP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x1000) >> 12
}

// AXI_DMA.IN_LINK1_CH0: Link descriptor configure and control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_AUTO_RET_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_AUTO_RET_CH() uint32 {
	return volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_STOP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH0_INLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH0.Reg, volatile.LoadUint32(&o.IN_LINK1_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH0_INLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH0.Reg) & 0x10) >> 4
}

// AXI_DMA.IN_LINK2_CH0: Link descriptor configure and control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_LINK2_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK2_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_LINK2_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_LINK2_CH0.Reg)
}

// AXI_DMA.IN_STATE_CH0: Receive status of Rx channel 0
func (o *AXI_DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff
}
func (o *AXI_DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18
}
func (o *AXI_DMA_Type) SetIN_STATE_CH0_IN_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH0_IN_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20
}

// AXI_DMA.IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0
func (o *AXI_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg)
}

// AXI_DMA.IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0
func (o *AXI_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg)
}

// AXI_DMA.IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg)
}

// AXI_DMA.IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_BF0_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg)
}

// AXI_DMA.IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_BF1_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg)
}

// AXI_DMA.IN_PRI_CH0: Priority register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_PRI_CH0_RX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH0_RX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf
}
func (o *AXI_DMA_Type) SetIN_PRI_CH0_RX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0xf0)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH0_RX_CH_ARB_WEIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0xf0) >> 4
}
func (o *AXI_DMA_Type) SetIN_PRI_CH0_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH0.Reg, volatile.LoadUint32(&o.IN_PRI_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH0_RX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_PRI_CH0.Reg) & 0x100) >> 8
}

// AXI_DMA.IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0
func (o *AXI_DMA_Type) SetIN_PERI_SEL_CH0_PERI_IN_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetIN_PERI_SEL_CH0_PERI_IN_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PERI_SEL_CH0.Reg) & 0x3f
}

// AXI_DMA.IN_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AXI_DMA_Type) SetIN_CRC_INIT_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_CRC_INIT_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH0.Reg)
}

// AXI_DMA.RX_CRC_WIDTH_CH0: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AXI_DMA_Type) SetRX_CRC_WIDTH_CH0_RX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg)&^(0x3)|value)
}
func (o *AXI_DMA_Type) GetRX_CRC_WIDTH_CH0_RX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg) & 0x3
}
func (o *AXI_DMA_Type) SetRX_CRC_WIDTH_CH0_RX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetRX_CRC_WIDTH_CH0_RX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.RX_CRC_WIDTH_CH0.Reg) & 0x4) >> 2
}

// AXI_DMA.IN_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
func (o *AXI_DMA_Type) SetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_CRC_CLEAR_CH0_IN_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH0.Reg) & 0x1
}

// AXI_DMA.IN_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
func (o *AXI_DMA_Type) SetIN_CRC_FINAL_RESULT_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_CRC_FINAL_RESULT_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH0.Reg)
}

// AXI_DMA.RX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
func (o *AXI_DMA_Type) SetRX_CRC_EN_WR_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_EN_WR_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH0.Reg)
}

// AXI_DMA.RX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
func (o *AXI_DMA_Type) SetRX_CRC_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH0.Reg)
}

// AXI_DMA.RX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xffff)|value)
}
func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH0_RX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xffff
}

// AXI_DMA.RX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH0.Reg)
}

// AXI_DMA.IN_INT_RAW_CH1: Raw status interrupt of channel 0
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L1_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L1_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L1_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L1_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L2_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L2_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L2_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L2_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L3_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L3_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_L3_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_L3_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_ST_CH1: Masked interrupt of channel 0
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L1_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L1_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L1_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L1_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L3_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L3_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH1_INFIFO_L3_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH1_INFIFO_L3_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_ENA_CH1: Interrupt enable bits of channel 0
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L1_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L1_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L1_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L1_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L2_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L2_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L2_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L2_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L3_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L3_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_L3_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_L3_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_CLR_CH1: Interrupt clear bits of channel 0
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L1_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L1_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L1_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L1_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L2_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L2_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L2_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L2_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L3_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L3_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_L3_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_L3_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_CONF0_CH1: Configure 0 register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_RST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_RST_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_MEM_TRANS_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_MEM_TRANS_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_BURST_SIZE_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x70)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_BURST_SIZE_SEL_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x70) >> 4
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_CMD_DISABLE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_CMD_DISABLE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_IN_ECC_AEC_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_IN_ECC_AEC_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x200) >> 9
}

// AXI_DMA.IN_CONF1_CH1: Configure 1 register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_CONF1_CH1_IN_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF1_CH1.Reg, volatile.LoadUint32(&o.IN_CONF1_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetIN_CONF1_CH1_IN_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF1_CH1.Reg) & 0x1000) >> 12
}

// AXI_DMA.INFIFO_STATUS_CH1: Receive FIFO status of Rx channel 0
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xfc) >> 2
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L3_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L3_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x400) >> 10
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800)|value<<11)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800) >> 11
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000) >> 12
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L1_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000)|value<<13)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L1_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000) >> 13
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000)|value<<14)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000) >> 14
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000)|value<<15)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000) >> 15
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10000) >> 16
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_L2_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_L2_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x20000) >> 17
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x800000) >> 23
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_5B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_5B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_6B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10000000)|value<<28)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_6B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10000000) >> 28
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_7B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x20000000)|value<<29)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_7B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x20000000) >> 29
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_8B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x40000000)|value<<30)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_REMAIN_UNDER_8B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x40000000) >> 30
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x80000000)|value<<31)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH1_IN_BUF_HUNGRY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x80000000) >> 31
}

// AXI_DMA.IN_POP_CH1: Pop control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_POP_CH1_INFIFO_RDATA_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0xfff)|value)
}
func (o *AXI_DMA_Type) GetIN_POP_CH1_INFIFO_RDATA_CH() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0xfff
}
func (o *AXI_DMA_Type) SetIN_POP_CH1_INFIFO_POP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetIN_POP_CH1_INFIFO_POP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x1000) >> 12
}

// AXI_DMA.IN_LINK1_CH1: Link descriptor configure and control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_AUTO_RET_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_AUTO_RET_CH() uint32 {
	return volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_STOP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH1_INLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH1.Reg, volatile.LoadUint32(&o.IN_LINK1_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH1_INLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH1.Reg) & 0x10) >> 4
}

// AXI_DMA.IN_LINK2_CH1: Link descriptor configure and control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_LINK2_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK2_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_LINK2_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_LINK2_CH1.Reg)
}

// AXI_DMA.IN_STATE_CH1: Receive status of Rx channel 0
func (o *AXI_DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff
}
func (o *AXI_DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18
}
func (o *AXI_DMA_Type) SetIN_STATE_CH1_IN_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH1_IN_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20
}

// AXI_DMA.IN_SUC_EOF_DES_ADDR_CH1: Inlink descriptor address when EOF occurs of Rx channel 0
func (o *AXI_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg)
}

// AXI_DMA.IN_ERR_EOF_DES_ADDR_CH1: Inlink descriptor address when errors occur of Rx channel 0
func (o *AXI_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg)
}

// AXI_DMA.IN_DSCR_CH1: Current inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg)
}

// AXI_DMA.IN_DSCR_BF0_CH1: The last inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_BF0_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg)
}

// AXI_DMA.IN_DSCR_BF1_CH1: The second-to-last inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_BF1_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg)
}

// AXI_DMA.IN_PRI_CH1: Priority register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_PRI_CH1_RX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH1_RX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf
}
func (o *AXI_DMA_Type) SetIN_PRI_CH1_RX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0xf0)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH1_RX_CH_ARB_WEIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0xf0) >> 4
}
func (o *AXI_DMA_Type) SetIN_PRI_CH1_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH1.Reg, volatile.LoadUint32(&o.IN_PRI_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH1_RX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_PRI_CH1.Reg) & 0x100) >> 8
}

// AXI_DMA.IN_PERI_SEL_CH1: Peripheral selection of Rx channel 0
func (o *AXI_DMA_Type) SetIN_PERI_SEL_CH1_PERI_IN_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetIN_PERI_SEL_CH1_PERI_IN_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PERI_SEL_CH1.Reg) & 0x3f
}

// AXI_DMA.IN_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AXI_DMA_Type) SetIN_CRC_INIT_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_CRC_INIT_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH1.Reg)
}

// AXI_DMA.RX_CRC_WIDTH_CH1: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AXI_DMA_Type) SetRX_CRC_WIDTH_CH1_RX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg)&^(0x3)|value)
}
func (o *AXI_DMA_Type) GetRX_CRC_WIDTH_CH1_RX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg) & 0x3
}
func (o *AXI_DMA_Type) SetRX_CRC_WIDTH_CH1_RX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetRX_CRC_WIDTH_CH1_RX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.RX_CRC_WIDTH_CH1.Reg) & 0x4) >> 2
}

// AXI_DMA.IN_CRC_CLEAR_CH1: This register is used to clear ch0 crc result
func (o *AXI_DMA_Type) SetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_CRC_CLEAR_CH1_IN_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH1.Reg) & 0x1
}

// AXI_DMA.IN_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result
func (o *AXI_DMA_Type) SetIN_CRC_FINAL_RESULT_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_CRC_FINAL_RESULT_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH1.Reg)
}

// AXI_DMA.RX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit
func (o *AXI_DMA_Type) SetRX_CRC_EN_WR_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_EN_WR_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH1.Reg)
}

// AXI_DMA.RX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr
func (o *AXI_DMA_Type) SetRX_CRC_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH1.Reg)
}

// AXI_DMA.RX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en
func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xffff)|value)
}
func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH1_RX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xffff
}

// AXI_DMA.RX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en
func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH1.Reg)
}

// AXI_DMA.IN_INT_RAW_CH2: Raw status interrupt of channel 0
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L1_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L1_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L1_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L1_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L2_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L2_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L2_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L2_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L3_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L3_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_L3_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_L3_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_ST_CH2: Masked interrupt of channel 0
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L1_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L1_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L1_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L1_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L3_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L3_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_ST_CH2_INFIFO_L3_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_ST_CH2_INFIFO_L3_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_ENA_CH2: Interrupt enable bits of channel 0
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L1_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L1_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L1_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L1_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L2_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L2_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L2_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L2_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L3_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L3_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_L3_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_L3_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_INT_CLR_CH2: Interrupt clear bits of channel 0
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L1_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L1_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L1_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L1_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L2_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L2_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L2_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L2_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L3_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L3_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_L3_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_L3_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x400) >> 10
}

// AXI_DMA.IN_CONF0_CH2: Configure 0 register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_RST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_RST_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_LOOP_TEST_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_LOOP_TEST_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_MEM_TRANS_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_MEM_TRANS_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_ETM_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_ETM_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_BURST_SIZE_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x70)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_BURST_SIZE_SEL_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x70) >> 4
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_CMD_DISABLE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_CMD_DISABLE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_IN_ECC_AEC_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_IN_ECC_AEC_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x200) >> 9
}

// AXI_DMA.IN_CONF1_CH2: Configure 1 register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_CONF1_CH2_IN_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CONF1_CH2.Reg, volatile.LoadUint32(&o.IN_CONF1_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetIN_CONF1_CH2_IN_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF1_CH2.Reg) & 0x1000) >> 12
}

// AXI_DMA.INFIFO_STATUS_CH2: Receive FIFO status of Rx channel 0
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xfc) >> 2
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L3_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L3_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x400) >> 10
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800)|value<<11)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800) >> 11
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000) >> 12
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L1_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000)|value<<13)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L1_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000) >> 13
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000)|value<<14)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000) >> 14
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000)|value<<15)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000) >> 15
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10000) >> 16
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_L2_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_L2_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x20000) >> 17
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x800000) >> 23
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_5B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_5B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_6B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10000000)|value<<28)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_6B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10000000) >> 28
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_7B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x20000000)|value<<29)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_7B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x20000000) >> 29
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_8B_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x40000000)|value<<30)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_REMAIN_UNDER_8B_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x40000000) >> 30
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x80000000)|value<<31)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS_CH2_IN_BUF_HUNGRY_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x80000000) >> 31
}

// AXI_DMA.IN_POP_CH2: Pop control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_POP_CH2_INFIFO_RDATA_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0xfff)|value)
}
func (o *AXI_DMA_Type) GetIN_POP_CH2_INFIFO_RDATA_CH() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0xfff
}
func (o *AXI_DMA_Type) SetIN_POP_CH2_INFIFO_POP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetIN_POP_CH2_INFIFO_POP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x1000) >> 12
}

// AXI_DMA.IN_LINK1_CH2: Link descriptor configure and control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_AUTO_RET_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_AUTO_RET_CH() uint32 {
	return volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_STOP_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_LINK1_CH2_INLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.IN_LINK1_CH2.Reg, volatile.LoadUint32(&o.IN_LINK1_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_LINK1_CH2_INLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK1_CH2.Reg) & 0x10) >> 4
}

// AXI_DMA.IN_LINK2_CH2: Link descriptor configure and control register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_LINK2_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK2_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_LINK2_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_LINK2_CH2.Reg)
}

// AXI_DMA.IN_STATE_CH2: Receive status of Rx channel 0
func (o *AXI_DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff
}
func (o *AXI_DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18
}
func (o *AXI_DMA_Type) SetIN_STATE_CH2_IN_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20)
}
func (o *AXI_DMA_Type) GetIN_STATE_CH2_IN_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20
}

// AXI_DMA.IN_SUC_EOF_DES_ADDR_CH2: Inlink descriptor address when EOF occurs of Rx channel 0
func (o *AXI_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg)
}

// AXI_DMA.IN_ERR_EOF_DES_ADDR_CH2: Inlink descriptor address when errors occur of Rx channel 0
func (o *AXI_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg)
}

// AXI_DMA.IN_DSCR_CH2: Current inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg)
}

// AXI_DMA.IN_DSCR_BF0_CH2: The last inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_BF0_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg)
}

// AXI_DMA.IN_DSCR_BF1_CH2: The second-to-last inlink descriptor address of Rx channel 0
func (o *AXI_DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_DSCR_BF1_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg)
}

// AXI_DMA.IN_PRI_CH2: Priority register of Rx channel 0
func (o *AXI_DMA_Type) SetIN_PRI_CH2_RX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH2_RX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf
}
func (o *AXI_DMA_Type) SetIN_PRI_CH2_RX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0xf0)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH2_RX_CH_ARB_WEIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0xf0) >> 4
}
func (o *AXI_DMA_Type) SetIN_PRI_CH2_RX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PRI_CH2.Reg, volatile.LoadUint32(&o.IN_PRI_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetIN_PRI_CH2_RX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return (volatile.LoadUint32(&o.IN_PRI_CH2.Reg) & 0x100) >> 8
}

// AXI_DMA.IN_PERI_SEL_CH2: Peripheral selection of Rx channel 0
func (o *AXI_DMA_Type) SetIN_PERI_SEL_CH2_PERI_IN_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetIN_PERI_SEL_CH2_PERI_IN_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_PERI_SEL_CH2.Reg) & 0x3f
}

// AXI_DMA.IN_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AXI_DMA_Type) SetIN_CRC_INIT_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_INIT_DATA_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_CRC_INIT_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_INIT_DATA_CH2.Reg)
}

// AXI_DMA.RX_CRC_WIDTH_CH2: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AXI_DMA_Type) SetRX_CRC_WIDTH_CH2_RX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg)&^(0x3)|value)
}
func (o *AXI_DMA_Type) GetRX_CRC_WIDTH_CH2_RX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg) & 0x3
}
func (o *AXI_DMA_Type) SetRX_CRC_WIDTH_CH2_RX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetRX_CRC_WIDTH_CH2_RX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.RX_CRC_WIDTH_CH2.Reg) & 0x4) >> 2
}

// AXI_DMA.IN_CRC_CLEAR_CH2: This register is used to clear ch0 crc result
func (o *AXI_DMA_Type) SetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_CRC_CLEAR_CH2_IN_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_CLEAR_CH2.Reg) & 0x1
}

// AXI_DMA.IN_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result
func (o *AXI_DMA_Type) SetIN_CRC_FINAL_RESULT_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetIN_CRC_FINAL_RESULT_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_CRC_FINAL_RESULT_CH2.Reg)
}

// AXI_DMA.RX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit
func (o *AXI_DMA_Type) SetRX_CRC_EN_WR_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_EN_WR_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_WR_DATA_CH2.Reg)
}

// AXI_DMA.RX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr
func (o *AXI_DMA_Type) SetRX_CRC_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_EN_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_EN_ADDR_CH2.Reg)
}

// AXI_DMA.RX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en
func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xffff)|value)
}
func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_WR_DATA_CH2_RX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xffff
}

// AXI_DMA.RX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en
func (o *AXI_DMA_Type) SetRX_CRC_DATA_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetRX_CRC_DATA_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.RX_CRC_DATA_EN_ADDR_CH2.Reg)
}

// AXI_DMA.OUT_INT_RAW_CH0: Raw status interrupt of channel0
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L1_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L1_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L1_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L1_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L2_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L2_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L2_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L2_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L3_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L3_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_L3_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_L3_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_ST_CH0: Masked interrupt of channel0
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L1_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L1_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L1_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L1_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L3_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L3_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_L3_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_L3_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_ENA_CH0: Interrupt enable bits of channel0
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L1_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L1_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L1_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L1_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L2_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L2_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L2_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L2_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L3_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L3_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_L3_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_L3_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_CLR_CH0: Interrupt clear bits of channel0
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L1_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L1_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L1_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L1_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L2_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L2_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L2_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L2_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L3_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L3_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_L3_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_L3_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_CONF0_CH0: Configure 0 register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_LOOP_TEST_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_ETM_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_ETM_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_BURST_SIZE_SEL_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0xe0)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_BURST_SIZE_SEL_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0xe0) >> 5
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUT_ECC_AEC_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUT_ECC_AEC_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x400) >> 10
}

// AXI_DMA.OUT_CONF1_CH0: Configure 1 register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF1_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetOUT_CONF1_CH0_OUT_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF1_CH0.Reg) & 0x1000) >> 12
}

// AXI_DMA.OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel0
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xfc)|value<<2)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xfc) >> 2
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L3_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L3_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x400) >> 10
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800)|value<<11)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800) >> 11
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000) >> 12
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L1_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000)|value<<13)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L1_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000) >> 13
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000)|value<<14)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000) >> 14
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x8000)|value<<15)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x8000) >> 15
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x10000) >> 16
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_L2_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_L2_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x20000) >> 17
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x800000)|value<<23)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x800000) >> 23
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1000000) >> 24
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2000000)|value<<25)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2000000) >> 25
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x4000000)|value<<26)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x4000000) >> 26
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_5B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x8000000)|value<<27)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_5B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x8000000) >> 27
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_6B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x10000000)|value<<28)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_6B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x10000000) >> 28
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_7B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x20000000)|value<<29)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_7B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x20000000) >> 29
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_8B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x40000000)|value<<30)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH0_OUT_REMAIN_UNDER_8B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x40000000) >> 30
}

// AXI_DMA.OUT_PUSH_CH0: Push control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x1ff)|value)
}
func (o *AXI_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x1ff
}
func (o *AXI_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_LINK1_CH0: Link descriptor configure and control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_STOP_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH0_OUTLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH0_OUTLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH0.Reg) & 0x8) >> 3
}

// AXI_DMA.OUT_LINK2_CH0: Link descriptor configure and control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_LINK2_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK2_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_LINK2_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK2_CH0.Reg)
}

// AXI_DMA.OUT_STATE_CH0: Transmit status of Tx channel0
func (o *AXI_DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff
}
func (o *AXI_DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18
}
func (o *AXI_DMA_Type) SetOUT_STATE_CH0_OUT_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x700000)|value<<20)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH0_OUT_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x700000) >> 20
}

// AXI_DMA.OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel0
func (o *AXI_DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg)
}

// AXI_DMA.OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel0
func (o *AXI_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH0.Reg)
}

// AXI_DMA.OUT_DSCR_CH0: Current outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg)
}

// AXI_DMA.OUT_DSCR_BF0_CH0: The last outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg)
}

// AXI_DMA.OUT_DSCR_BF1_CH0: The second-to-last outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg)
}

// AXI_DMA.OUT_PRI_CH0: Priority register of Tx channel0.
func (o *AXI_DMA_Type) SetOUT_PRI_CH0_TX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH0_TX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf
}
func (o *AXI_DMA_Type) SetOUT_PRI_CH0_TX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0xf0)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH0_TX_CH_ARB_WEIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0xf0) >> 4
}
func (o *AXI_DMA_Type) SetOUT_PRI_CH0_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH0.Reg, volatile.LoadUint32(&o.OUT_PRI_CH0.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH0_TX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PRI_CH0.Reg) & 0x100) >> 8
}

// AXI_DMA.OUT_PERI_SEL_CH0: Peripheral selection of Tx channel0
func (o *AXI_DMA_Type) SetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PERI_SEL_CH0.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetOUT_PERI_SEL_CH0_PERI_OUT_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PERI_SEL_CH0.Reg) & 0x3f
}

// AXI_DMA.OUT_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AXI_DMA_Type) SetOUT_CRC_INIT_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_INIT_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH0.Reg)
}

// AXI_DMA.TX_CRC_WIDTH_CH0: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AXI_DMA_Type) SetTX_CRC_WIDTH_CH0_TX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg)&^(0x3)|value)
}
func (o *AXI_DMA_Type) GetTX_CRC_WIDTH_CH0_TX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg) & 0x3
}
func (o *AXI_DMA_Type) SetTX_CRC_WIDTH_CH0_TX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetTX_CRC_WIDTH_CH0_TX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.TX_CRC_WIDTH_CH0.Reg) & 0x4) >> 2
}

// AXI_DMA.OUT_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
func (o *AXI_DMA_Type) SetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH0.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_CLEAR_CH0_OUT_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH0.Reg) & 0x1
}

// AXI_DMA.OUT_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
func (o *AXI_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH0.Reg)
}

// AXI_DMA.TX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
func (o *AXI_DMA_Type) SetTX_CRC_EN_WR_DATA_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_EN_WR_DATA_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH0.Reg)
}

// AXI_DMA.TX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
func (o *AXI_DMA_Type) SetTX_CRC_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH0.Reg)
}

// AXI_DMA.TX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg)&^(0xffff)|value)
}
func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH0_TX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH0.Reg) & 0xffff
}

// AXI_DMA.TX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH0.Reg)
}

// AXI_DMA.OUT_INT_RAW_CH1: Raw status interrupt of channel0
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L1_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L1_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L1_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L1_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L2_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L2_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L2_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L2_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L3_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L3_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_L3_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_L3_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_ST_CH1: Masked interrupt of channel0
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L1_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L1_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L1_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L1_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L3_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L3_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_L3_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_L3_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_ENA_CH1: Interrupt enable bits of channel0
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L1_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L1_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L1_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L1_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L2_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L2_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L2_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L2_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L3_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L3_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_L3_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_L3_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_CLR_CH1: Interrupt clear bits of channel0
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L1_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L1_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L1_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L1_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L2_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L2_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L2_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L2_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L3_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L3_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_L3_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_L3_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_CONF0_CH1: Configure 0 register of Tx channel1
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_RST_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_RST_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_LOOP_TEST_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_LOOP_TEST_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_ETM_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_ETM_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_BURST_SIZE_SEL_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0xe0)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_BURST_SIZE_SEL_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0xe0) >> 5
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUT_ECC_AEC_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUT_ECC_AEC_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x400) >> 10
}

// AXI_DMA.OUT_CONF1_CH1: Configure 1 register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF1_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetOUT_CONF1_CH1_OUT_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF1_CH1.Reg) & 0x1000) >> 12
}

// AXI_DMA.OUTFIFO_STATUS_CH1: Transmit FIFO status of Tx channel0
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xfc)|value<<2)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xfc) >> 2
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L3_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L3_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x400) >> 10
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800)|value<<11)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800) >> 11
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000) >> 12
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L1_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000)|value<<13)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L1_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000) >> 13
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000)|value<<14)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000) >> 14
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x8000)|value<<15)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x8000) >> 15
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x10000) >> 16
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_L2_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_L2_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x20000) >> 17
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x800000)|value<<23)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x800000) >> 23
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1000000) >> 24
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2000000)|value<<25)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2000000) >> 25
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x4000000)|value<<26)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x4000000) >> 26
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_5B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x8000000)|value<<27)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_5B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x8000000) >> 27
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_6B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x10000000)|value<<28)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_6B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x10000000) >> 28
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_7B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x20000000)|value<<29)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_7B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x20000000) >> 29
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_8B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x40000000)|value<<30)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH1_OUT_REMAIN_UNDER_8B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x40000000) >> 30
}

// AXI_DMA.OUT_PUSH_CH1: Push control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x1ff)|value)
}
func (o *AXI_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x1ff
}
func (o *AXI_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_LINK1_CH1: Link descriptor configure and control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_STOP_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH1_OUTLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH1_OUTLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH1.Reg) & 0x8) >> 3
}

// AXI_DMA.OUT_LINK2_CH1: Link descriptor configure and control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_LINK2_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK2_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_LINK2_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK2_CH1.Reg)
}

// AXI_DMA.OUT_STATE_CH1: Transmit status of Tx channel0
func (o *AXI_DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff
}
func (o *AXI_DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18
}
func (o *AXI_DMA_Type) SetOUT_STATE_CH1_OUT_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x700000)|value<<20)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH1_OUT_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x700000) >> 20
}

// AXI_DMA.OUT_EOF_DES_ADDR_CH1: Outlink descriptor address when EOF occurs of Tx channel0
func (o *AXI_DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg)
}

// AXI_DMA.OUT_EOF_BFR_DES_ADDR_CH1: The last outlink descriptor address when EOF occurs of Tx channel0
func (o *AXI_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH1.Reg)
}

// AXI_DMA.OUT_DSCR_CH1: Current outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg)
}

// AXI_DMA.OUT_DSCR_BF0_CH1: The last outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg)
}

// AXI_DMA.OUT_DSCR_BF1_CH1: The second-to-last outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg)
}

// AXI_DMA.OUT_PRI_CH1: Priority register of Tx channel0.
func (o *AXI_DMA_Type) SetOUT_PRI_CH1_TX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH1_TX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf
}
func (o *AXI_DMA_Type) SetOUT_PRI_CH1_TX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0xf0)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH1_TX_CH_ARB_WEIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0xf0) >> 4
}
func (o *AXI_DMA_Type) SetOUT_PRI_CH1_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH1.Reg, volatile.LoadUint32(&o.OUT_PRI_CH1.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH1_TX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PRI_CH1.Reg) & 0x100) >> 8
}

// AXI_DMA.OUT_PERI_SEL_CH1: Peripheral selection of Tx channel0
func (o *AXI_DMA_Type) SetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PERI_SEL_CH1.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetOUT_PERI_SEL_CH1_PERI_OUT_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PERI_SEL_CH1.Reg) & 0x3f
}

// AXI_DMA.OUT_CRC_INIT_DATA_CH1: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AXI_DMA_Type) SetOUT_CRC_INIT_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_INIT_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH1.Reg)
}

// AXI_DMA.TX_CRC_WIDTH_CH1: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AXI_DMA_Type) SetTX_CRC_WIDTH_CH1_TX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg)&^(0x3)|value)
}
func (o *AXI_DMA_Type) GetTX_CRC_WIDTH_CH1_TX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg) & 0x3
}
func (o *AXI_DMA_Type) SetTX_CRC_WIDTH_CH1_TX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetTX_CRC_WIDTH_CH1_TX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.TX_CRC_WIDTH_CH1.Reg) & 0x4) >> 2
}

// AXI_DMA.OUT_CRC_CLEAR_CH1: This register is used to clear ch0 crc result
func (o *AXI_DMA_Type) SetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH1.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_CLEAR_CH1_OUT_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH1.Reg) & 0x1
}

// AXI_DMA.OUT_CRC_FINAL_RESULT_CH1: This register is used to store ch0 crc result
func (o *AXI_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH1.Reg)
}

// AXI_DMA.TX_CRC_EN_WR_DATA_CH1: This resister is used to config ch0 crc en for every bit
func (o *AXI_DMA_Type) SetTX_CRC_EN_WR_DATA_CH1(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_EN_WR_DATA_CH1() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH1.Reg)
}

// AXI_DMA.TX_CRC_EN_ADDR_CH1: This register is used to config ch0 crc en addr
func (o *AXI_DMA_Type) SetTX_CRC_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH1.Reg)
}

// AXI_DMA.TX_CRC_DATA_EN_WR_DATA_CH1: This register is used to config crc data_8bit en
func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg)&^(0xffff)|value)
}
func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH1_TX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH1.Reg) & 0xffff
}

// AXI_DMA.TX_CRC_DATA_EN_ADDR_CH1: This register is used to config addr of crc data_8bit en
func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH1.Reg)
}

// AXI_DMA.OUT_INT_RAW_CH2: Raw status interrupt of channel0
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE_CH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L1_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L1_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L1_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L1_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L2_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L2_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L2_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L2_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L3_OVF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L3_OVF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_L3_UDF_CH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_L3_UDF_CH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_ST_CH2: Masked interrupt of channel0
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE_CH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L1_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L1_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L1_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L1_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L3_OVF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L3_OVF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_L3_UDF_CH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_L3_UDF_CH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_ENA_CH2: Interrupt enable bits of channel0
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE_CH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L1_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L1_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L1_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L1_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L2_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L2_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L2_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L2_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L3_OVF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L3_OVF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_L3_UDF_CH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_L3_UDF_CH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_INT_CLR_CH2: Interrupt clear bits of channel0
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE_CH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L1_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L1_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L1_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L1_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L2_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x40)|value<<6)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L2_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x40) >> 6
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L2_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x80)|value<<7)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L2_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x80) >> 7
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L3_OVF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L3_OVF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_L3_UDF_CH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_L3_UDF_CH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_CONF0_CH2: Configure 0 register of Tx channel2
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_RST_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_RST_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_LOOP_TEST_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_LOOP_TEST_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_ETM_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_ETM_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_BURST_SIZE_SEL_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0xe0)|value<<5)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_BURST_SIZE_SEL_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0xe0) >> 5
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUT_ECC_AEC_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUT_ECC_AEC_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x400) >> 10
}

// AXI_DMA.OUT_CONF1_CH2: Configure 1 register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF1_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetOUT_CONF1_CH2_OUT_CHECK_OWNER_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF1_CH2.Reg) & 0x1000) >> 12
}

// AXI_DMA.OUTFIFO_STATUS_CH2: Transmit FIFO status of Tx channel0
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_FULL_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xfc)|value<<2)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xfc) >> 2
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x100) >> 8
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L3_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L3_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x200) >> 9
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x400)|value<<10)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x400) >> 10
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800)|value<<11)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800) >> 11
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000) >> 12
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L1_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000)|value<<13)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L1_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000) >> 13
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_FULL_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000)|value<<14)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_FULL_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000) >> 14
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_EMPTY_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x8000)|value<<15)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_EMPTY_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x8000) >> 15
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_UDF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_UDF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x10000) >> 16
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_L2_OVF_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_L2_OVF_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x20000) >> 17
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x800000)|value<<23)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_1B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x800000) >> 23
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_2B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1000000) >> 24
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2000000)|value<<25)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_3B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2000000) >> 25
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x4000000)|value<<26)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_4B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x4000000) >> 26
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_5B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x8000000)|value<<27)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_5B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x8000000) >> 27
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_6B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x10000000)|value<<28)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_6B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x10000000) >> 28
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_7B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x20000000)|value<<29)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_7B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x20000000) >> 29
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_8B_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x40000000)|value<<30)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS_CH2_OUT_REMAIN_UNDER_8B_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x40000000) >> 30
}

// AXI_DMA.OUT_PUSH_CH2: Push control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x1ff)|value)
}
func (o *AXI_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x1ff
}
func (o *AXI_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x200)|value<<9)
}
func (o *AXI_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x200) >> 9
}

// AXI_DMA.OUT_LINK1_CH2: Link descriptor configure and control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_STOP_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_STOP_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_START_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_START_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_RESTART_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_RESTART_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetOUT_LINK1_CH2_OUTLINK_PARK_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK1_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetOUT_LINK1_CH2_OUTLINK_PARK_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK1_CH2.Reg) & 0x8) >> 3
}

// AXI_DMA.OUT_LINK2_CH2: Link descriptor configure and control register of Tx channel0
func (o *AXI_DMA_Type) SetOUT_LINK2_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK2_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_LINK2_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK2_CH2.Reg)
}

// AXI_DMA.OUT_STATE_CH2: Transmit status of Tx channel0
func (o *AXI_DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff
}
func (o *AXI_DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18
}
func (o *AXI_DMA_Type) SetOUT_STATE_CH2_OUT_STATE_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x700000)|value<<20)
}
func (o *AXI_DMA_Type) GetOUT_STATE_CH2_OUT_STATE_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x700000) >> 20
}

// AXI_DMA.OUT_EOF_DES_ADDR_CH2: Outlink descriptor address when EOF occurs of Tx channel0
func (o *AXI_DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg)
}

// AXI_DMA.OUT_EOF_BFR_DES_ADDR_CH2: The last outlink descriptor address when EOF occurs of Tx channel0
func (o *AXI_DMA_Type) SetOUT_EOF_BFR_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_EOF_BFR_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_BFR_DES_ADDR_CH2.Reg)
}

// AXI_DMA.OUT_DSCR_CH2: Current outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg)
}

// AXI_DMA.OUT_DSCR_BF0_CH2: The last outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg)
}

// AXI_DMA.OUT_DSCR_BF1_CH2: The second-to-last outlink descriptor address of Tx channel0
func (o *AXI_DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg)
}

// AXI_DMA.OUT_PRI_CH2: Priority register of Tx channel0.
func (o *AXI_DMA_Type) SetOUT_PRI_CH2_TX_PRI_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH2_TX_PRI_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf
}
func (o *AXI_DMA_Type) SetOUT_PRI_CH2_TX_CH_ARB_WEIGH_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0xf0)|value<<4)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH2_TX_CH_ARB_WEIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0xf0) >> 4
}
func (o *AXI_DMA_Type) SetOUT_PRI_CH2_TX_ARB_WEIGH_OPT_DIR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PRI_CH2.Reg, volatile.LoadUint32(&o.OUT_PRI_CH2.Reg)&^(0x100)|value<<8)
}
func (o *AXI_DMA_Type) GetOUT_PRI_CH2_TX_ARB_WEIGH_OPT_DIR_CH() uint32 {
	return (volatile.LoadUint32(&o.OUT_PRI_CH2.Reg) & 0x100) >> 8
}

// AXI_DMA.OUT_PERI_SEL_CH2: Peripheral selection of Tx channel0
func (o *AXI_DMA_Type) SetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_PERI_SEL_CH2.Reg, volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetOUT_PERI_SEL_CH2_PERI_OUT_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_PERI_SEL_CH2.Reg) & 0x3f
}

// AXI_DMA.OUT_CRC_INIT_DATA_CH2: This register is used to config ch0 crc initial data(max 32 bit)
func (o *AXI_DMA_Type) SetOUT_CRC_INIT_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_INIT_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_INIT_DATA_CH2.Reg)
}

// AXI_DMA.TX_CRC_WIDTH_CH2: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
func (o *AXI_DMA_Type) SetTX_CRC_WIDTH_CH2_TX_CRC_WIDTH_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg)&^(0x3)|value)
}
func (o *AXI_DMA_Type) GetTX_CRC_WIDTH_CH2_TX_CRC_WIDTH_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg) & 0x3
}
func (o *AXI_DMA_Type) SetTX_CRC_WIDTH_CH2_TX_CRC_LAUTCH_FLGA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_WIDTH_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetTX_CRC_WIDTH_CH2_TX_CRC_LAUTCH_FLGA_CH() uint32 {
	return (volatile.LoadUint32(&o.TX_CRC_WIDTH_CH2.Reg) & 0x4) >> 2
}

// AXI_DMA.OUT_CRC_CLEAR_CH2: This register is used to clear ch0 crc result
func (o *AXI_DMA_Type) SetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_CLEAR_CH2.Reg, volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_CLEAR_CH2_OUT_CRC_CLEAR_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_CLEAR_CH2.Reg) & 0x1
}

// AXI_DMA.OUT_CRC_FINAL_RESULT_CH2: This register is used to store ch0 crc result
func (o *AXI_DMA_Type) SetOUT_CRC_FINAL_RESULT_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetOUT_CRC_FINAL_RESULT_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_CRC_FINAL_RESULT_CH2.Reg)
}

// AXI_DMA.TX_CRC_EN_WR_DATA_CH2: This resister is used to config ch0 crc en for every bit
func (o *AXI_DMA_Type) SetTX_CRC_EN_WR_DATA_CH2(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_EN_WR_DATA_CH2() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_WR_DATA_CH2.Reg)
}

// AXI_DMA.TX_CRC_EN_ADDR_CH2: This register is used to config ch0 crc en addr
func (o *AXI_DMA_Type) SetTX_CRC_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_EN_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_EN_ADDR_CH2.Reg)
}

// AXI_DMA.TX_CRC_DATA_EN_WR_DATA_CH2: This register is used to config crc data_8bit en
func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg, volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg)&^(0xffff)|value)
}
func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_WR_DATA_CH2_TX_CRC_DATA_EN_WR_DATA_CH() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_WR_DATA_CH2.Reg) & 0xffff
}

// AXI_DMA.TX_CRC_DATA_EN_ADDR_CH2: This register is used to config addr of crc data_8bit en
func (o *AXI_DMA_Type) SetTX_CRC_DATA_EN_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg, value)
}
func (o *AXI_DMA_Type) GetTX_CRC_DATA_EN_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.TX_CRC_DATA_EN_ADDR_CH2.Reg)
}

// AXI_DMA.ARB_TIMEOUT: This retister is used to config arbiter time slice
func (o *AXI_DMA_Type) SetARB_TIMEOUT_TX(value uint32) {
	volatile.StoreUint32(&o.ARB_TIMEOUT.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT.Reg)&^(0xffff)|value)
}
func (o *AXI_DMA_Type) GetARB_TIMEOUT_TX() uint32 {
	return volatile.LoadUint32(&o.ARB_TIMEOUT.Reg) & 0xffff
}
func (o *AXI_DMA_Type) SetARB_TIMEOUT_RX(value uint32) {
	volatile.StoreUint32(&o.ARB_TIMEOUT.Reg, volatile.LoadUint32(&o.ARB_TIMEOUT.Reg)&^(0xffff0000)|value<<16)
}
func (o *AXI_DMA_Type) GetARB_TIMEOUT_RX() uint32 {
	return (volatile.LoadUint32(&o.ARB_TIMEOUT.Reg) & 0xffff0000) >> 16
}

// AXI_DMA.WEIGHT_EN: This register is used to config arbiter weight function to on or off
func (o *AXI_DMA_Type) SetWEIGHT_EN_TX(value uint32) {
	volatile.StoreUint32(&o.WEIGHT_EN.Reg, volatile.LoadUint32(&o.WEIGHT_EN.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetWEIGHT_EN_TX() uint32 {
	return volatile.LoadUint32(&o.WEIGHT_EN.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetWEIGHT_EN_RX(value uint32) {
	volatile.StoreUint32(&o.WEIGHT_EN.Reg, volatile.LoadUint32(&o.WEIGHT_EN.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetWEIGHT_EN_RX() uint32 {
	return (volatile.LoadUint32(&o.WEIGHT_EN.Reg) & 0x2) >> 1
}

// AXI_DMA.IN_MEM_CONF: Mem power configure register of Rx channel
func (o *AXI_DMA_Type) SetIN_MEM_CONF_IN_MEM_CLK_FORCE_EN(value uint32) {
	volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_MEM_CONF_IN_MEM_CLK_FORCE_EN() uint32 {
	return volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetIN_MEM_CONF_IN_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetIN_MEM_CONF_IN_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetIN_MEM_CONF_IN_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x4)|value<<2)
}
func (o *AXI_DMA_Type) GetIN_MEM_CONF_IN_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x4) >> 2
}
func (o *AXI_DMA_Type) SetIN_MEM_CONF_OUT_MEM_CLK_FORCE_EN(value uint32) {
	volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetIN_MEM_CONF_OUT_MEM_CLK_FORCE_EN() uint32 {
	return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetIN_MEM_CONF_OUT_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetIN_MEM_CONF_OUT_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x10) >> 4
}
func (o *AXI_DMA_Type) SetIN_MEM_CONF_OUT_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.IN_MEM_CONF.Reg, volatile.LoadUint32(&o.IN_MEM_CONF.Reg)&^(0x20)|value<<5)
}
func (o *AXI_DMA_Type) GetIN_MEM_CONF_OUT_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.IN_MEM_CONF.Reg) & 0x20) >> 5
}

// AXI_DMA.INTR_MEM_START_ADDR: The start address of accessible address space.
func (o *AXI_DMA_Type) SetINTR_MEM_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.INTR_MEM_START_ADDR.Reg, value)
}
func (o *AXI_DMA_Type) GetINTR_MEM_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.INTR_MEM_START_ADDR.Reg)
}

// AXI_DMA.INTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error.
func (o *AXI_DMA_Type) SetINTR_MEM_END_ADDR(value uint32) {
	volatile.StoreUint32(&o.INTR_MEM_END_ADDR.Reg, value)
}
func (o *AXI_DMA_Type) GetINTR_MEM_END_ADDR() uint32 {
	return volatile.LoadUint32(&o.INTR_MEM_END_ADDR.Reg)
}

// AXI_DMA.EXTR_MEM_START_ADDR: The start address of accessible address space.
func (o *AXI_DMA_Type) SetEXTR_MEM_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.EXTR_MEM_START_ADDR.Reg, value)
}
func (o *AXI_DMA_Type) GetEXTR_MEM_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.EXTR_MEM_START_ADDR.Reg)
}

// AXI_DMA.EXTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error.
func (o *AXI_DMA_Type) SetEXTR_MEM_END_ADDR(value uint32) {
	volatile.StoreUint32(&o.EXTR_MEM_END_ADDR.Reg, value)
}
func (o *AXI_DMA_Type) GetEXTR_MEM_END_ADDR() uint32 {
	return volatile.LoadUint32(&o.EXTR_MEM_END_ADDR.Reg)
}

// AXI_DMA.IN_RESET_AVAIL_CH0: The rx channel 0 reset valid_flag register.
func (o *AXI_DMA_Type) SetIN_RESET_AVAIL_CH0_IN_RESET_AVAIL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_RESET_AVAIL_CH0.Reg, volatile.LoadUint32(&o.IN_RESET_AVAIL_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_RESET_AVAIL_CH0_IN_RESET_AVAIL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_RESET_AVAIL_CH0.Reg) & 0x1
}

// AXI_DMA.IN_RESET_AVAIL_CH1: The rx channel 0 reset valid_flag register.
func (o *AXI_DMA_Type) SetIN_RESET_AVAIL_CH1_IN_RESET_AVAIL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_RESET_AVAIL_CH1.Reg, volatile.LoadUint32(&o.IN_RESET_AVAIL_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_RESET_AVAIL_CH1_IN_RESET_AVAIL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_RESET_AVAIL_CH1.Reg) & 0x1
}

// AXI_DMA.IN_RESET_AVAIL_CH2: The rx channel 0 reset valid_flag register.
func (o *AXI_DMA_Type) SetIN_RESET_AVAIL_CH2_IN_RESET_AVAIL_CH(value uint32) {
	volatile.StoreUint32(&o.IN_RESET_AVAIL_CH2.Reg, volatile.LoadUint32(&o.IN_RESET_AVAIL_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetIN_RESET_AVAIL_CH2_IN_RESET_AVAIL_CH() uint32 {
	return volatile.LoadUint32(&o.IN_RESET_AVAIL_CH2.Reg) & 0x1
}

// AXI_DMA.OUT_RESET_AVAIL_CH0: The tx channel 0 reset valid_flag register.
func (o *AXI_DMA_Type) SetOUT_RESET_AVAIL_CH0_OUT_RESET_AVAIL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_RESET_AVAIL_CH0.Reg, volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH0.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_RESET_AVAIL_CH0_OUT_RESET_AVAIL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH0.Reg) & 0x1
}

// AXI_DMA.OUT_RESET_AVAIL_CH1: The tx channel 0 reset valid_flag register.
func (o *AXI_DMA_Type) SetOUT_RESET_AVAIL_CH1_OUT_RESET_AVAIL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_RESET_AVAIL_CH1.Reg, volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH1.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_RESET_AVAIL_CH1_OUT_RESET_AVAIL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH1.Reg) & 0x1
}

// AXI_DMA.OUT_RESET_AVAIL_CH2: The tx channel 0 reset valid_flag register.
func (o *AXI_DMA_Type) SetOUT_RESET_AVAIL_CH2_OUT_RESET_AVAIL_CH(value uint32) {
	volatile.StoreUint32(&o.OUT_RESET_AVAIL_CH2.Reg, volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH2.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetOUT_RESET_AVAIL_CH2_OUT_RESET_AVAIL_CH() uint32 {
	return volatile.LoadUint32(&o.OUT_RESET_AVAIL_CH2.Reg) & 0x1
}

// AXI_DMA.MISC_CONF: MISC register
func (o *AXI_DMA_Type) SetMISC_CONF_AXIM_RST_WR_INTER(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetMISC_CONF_AXIM_RST_WR_INTER() uint32 {
	return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetMISC_CONF_AXIM_RST_RD_INTER(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetMISC_CONF_AXIM_RST_RD_INTER() uint32 {
	return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x2) >> 1
}
func (o *AXI_DMA_Type) SetMISC_CONF_ARB_PRI_DIS(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x8)|value<<3)
}
func (o *AXI_DMA_Type) GetMISC_CONF_ARB_PRI_DIS() uint32 {
	return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x8) >> 3
}
func (o *AXI_DMA_Type) SetMISC_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x10)|value<<4)
}
func (o *AXI_DMA_Type) GetMISC_CONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x10) >> 4
}

// AXI_DMA.RDN_RESULT: reserved
func (o *AXI_DMA_Type) SetRDN_RESULT_RDN_ENA(value uint32) {
	volatile.StoreUint32(&o.RDN_RESULT.Reg, volatile.LoadUint32(&o.RDN_RESULT.Reg)&^(0x1)|value)
}
func (o *AXI_DMA_Type) GetRDN_RESULT_RDN_ENA() uint32 {
	return volatile.LoadUint32(&o.RDN_RESULT.Reg) & 0x1
}
func (o *AXI_DMA_Type) SetRDN_RESULT(value uint32) {
	volatile.StoreUint32(&o.RDN_RESULT.Reg, volatile.LoadUint32(&o.RDN_RESULT.Reg)&^(0x2)|value<<1)
}
func (o *AXI_DMA_Type) GetRDN_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RDN_RESULT.Reg) & 0x2) >> 1
}

// AXI_DMA.RDN_ECO_HIGH: reserved
func (o *AXI_DMA_Type) SetRDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value)
}
func (o *AXI_DMA_Type) GetRDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg)
}

// AXI_DMA.RDN_ECO_LOW: reserved
func (o *AXI_DMA_Type) SetRDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value)
}
func (o *AXI_DMA_Type) GetRDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg)
}

// AXI_DMA.WRESP_CNT: AXI wr responce cnt register.
func (o *AXI_DMA_Type) SetWRESP_CNT(value uint32) {
	volatile.StoreUint32(&o.WRESP_CNT.Reg, volatile.LoadUint32(&o.WRESP_CNT.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetWRESP_CNT() uint32 {
	return volatile.LoadUint32(&o.WRESP_CNT.Reg) & 0xf
}

// AXI_DMA.RRESP_CNT: AXI wr responce cnt register.
func (o *AXI_DMA_Type) SetRRESP_CNT(value uint32) {
	volatile.StoreUint32(&o.RRESP_CNT.Reg, volatile.LoadUint32(&o.RRESP_CNT.Reg)&^(0xf)|value)
}
func (o *AXI_DMA_Type) GetRRESP_CNT() uint32 {
	return volatile.LoadUint32(&o.RRESP_CNT.Reg) & 0xf
}

// AXI_DMA.INFIFO_STATUS1_CH0: Receive FIFO status of Rx channel 0
func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH0_L1INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH0_L1INFIFO_CNT_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg) & 0x3f
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH0_L2INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg)&^(0x3c0)|value<<6)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH0_L2INFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS1_CH0.Reg) & 0x3c0) >> 6
}

// AXI_DMA.INFIFO_STATUS1_CH1: Receive FIFO status of Rx channel 0
func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH1_L1INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH1_L1INFIFO_CNT_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg) & 0x3f
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH1_L2INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg)&^(0x3c0)|value<<6)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH1_L2INFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS1_CH1.Reg) & 0x3c0) >> 6
}

// AXI_DMA.INFIFO_STATUS1_CH2: Receive FIFO status of Rx channel 0
func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH2_L1INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH2_L1INFIFO_CNT_CH() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg) & 0x3f
}
func (o *AXI_DMA_Type) SetINFIFO_STATUS1_CH2_L2INFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg)&^(0x3c0)|value<<6)
}
func (o *AXI_DMA_Type) GetINFIFO_STATUS1_CH2_L2INFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS1_CH2.Reg) & 0x3c0) >> 6
}

// AXI_DMA.OUTFIFO_STATUS1_CH0: Receive FIFO status of Tx channel 0
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH0_L1OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH0_L1OUTFIFO_CNT_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg) & 0x3f
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH0_L2OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg)&^(0x3c0)|value<<6)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH0_L2OUTFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH0.Reg) & 0x3c0) >> 6
}

// AXI_DMA.OUTFIFO_STATUS1_CH1: Receive FIFO status of Tx channel 0
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH1_L1OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH1_L1OUTFIFO_CNT_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg) & 0x3f
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH1_L2OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg)&^(0x3c0)|value<<6)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH1_L2OUTFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH1.Reg) & 0x3c0) >> 6
}

// AXI_DMA.OUTFIFO_STATUS1_CH2: Receive FIFO status of Tx channel 0
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH2_L1OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg)&^(0x3f)|value)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH2_L1OUTFIFO_CNT_CH() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg) & 0x3f
}
func (o *AXI_DMA_Type) SetOUTFIFO_STATUS1_CH2_L2OUTFIFO_CNT_CH(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS1_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg)&^(0x3c0)|value<<6)
}
func (o *AXI_DMA_Type) GetOUTFIFO_STATUS1_CH2_L2OUTFIFO_CNT_CH() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS1_CH2.Reg) & 0x3c0) >> 6
}

// AXI_DMA.DATE: Version control register
func (o *AXI_DMA_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *AXI_DMA_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// BITSCRAMBLER Peripheral
type BITSCRAMBLER_Type struct {
	TX_INST_CFG0    volatile.Register32 // 0x0
	TX_INST_CFG1    volatile.Register32 // 0x4
	RX_INST_CFG0    volatile.Register32 // 0x8
	RX_INST_CFG1    volatile.Register32 // 0xC
	TX_LUT_CFG0     volatile.Register32 // 0x10
	TX_LUT_CFG1     volatile.Register32 // 0x14
	RX_LUT_CFG0     volatile.Register32 // 0x18
	RX_LUT_CFG1     volatile.Register32 // 0x1C
	TX_TAILING_BITS volatile.Register32 // 0x20
	RX_TAILING_BITS volatile.Register32 // 0x24
	TX_CTRL         volatile.Register32 // 0x28
	RX_CTRL         volatile.Register32 // 0x2C
	TX_STATE        volatile.Register32 // 0x30
	RX_STATE        volatile.Register32 // 0x34
	_               [192]byte
	SYS             volatile.Register32 // 0xF8
	VERSION         volatile.Register32 // 0xFC
}

// BITSCRAMBLER.TX_INST_CFG0: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetTX_INST_CFG0_TX_INST_IDX(value uint32) {
	volatile.StoreUint32(&o.TX_INST_CFG0.Reg, volatile.LoadUint32(&o.TX_INST_CFG0.Reg)&^(0x7)|value)
}
func (o *BITSCRAMBLER_Type) GetTX_INST_CFG0_TX_INST_IDX() uint32 {
	return volatile.LoadUint32(&o.TX_INST_CFG0.Reg) & 0x7
}
func (o *BITSCRAMBLER_Type) SetTX_INST_CFG0_TX_INST_POS(value uint32) {
	volatile.StoreUint32(&o.TX_INST_CFG0.Reg, volatile.LoadUint32(&o.TX_INST_CFG0.Reg)&^(0x78)|value<<3)
}
func (o *BITSCRAMBLER_Type) GetTX_INST_CFG0_TX_INST_POS() uint32 {
	return (volatile.LoadUint32(&o.TX_INST_CFG0.Reg) & 0x78) >> 3
}

// BITSCRAMBLER.TX_INST_CFG1: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetTX_INST_CFG1(value uint32) {
	volatile.StoreUint32(&o.TX_INST_CFG1.Reg, value)
}
func (o *BITSCRAMBLER_Type) GetTX_INST_CFG1() uint32 {
	return volatile.LoadUint32(&o.TX_INST_CFG1.Reg)
}

// BITSCRAMBLER.RX_INST_CFG0: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetRX_INST_CFG0_RX_INST_IDX(value uint32) {
	volatile.StoreUint32(&o.RX_INST_CFG0.Reg, volatile.LoadUint32(&o.RX_INST_CFG0.Reg)&^(0x7)|value)
}
func (o *BITSCRAMBLER_Type) GetRX_INST_CFG0_RX_INST_IDX() uint32 {
	return volatile.LoadUint32(&o.RX_INST_CFG0.Reg) & 0x7
}
func (o *BITSCRAMBLER_Type) SetRX_INST_CFG0_RX_INST_POS(value uint32) {
	volatile.StoreUint32(&o.RX_INST_CFG0.Reg, volatile.LoadUint32(&o.RX_INST_CFG0.Reg)&^(0x78)|value<<3)
}
func (o *BITSCRAMBLER_Type) GetRX_INST_CFG0_RX_INST_POS() uint32 {
	return (volatile.LoadUint32(&o.RX_INST_CFG0.Reg) & 0x78) >> 3
}

// BITSCRAMBLER.RX_INST_CFG1: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetRX_INST_CFG1(value uint32) {
	volatile.StoreUint32(&o.RX_INST_CFG1.Reg, value)
}
func (o *BITSCRAMBLER_Type) GetRX_INST_CFG1() uint32 {
	return volatile.LoadUint32(&o.RX_INST_CFG1.Reg)
}

// BITSCRAMBLER.TX_LUT_CFG0: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetTX_LUT_CFG0_TX_LUT_IDX(value uint32) {
	volatile.StoreUint32(&o.TX_LUT_CFG0.Reg, volatile.LoadUint32(&o.TX_LUT_CFG0.Reg)&^(0x7ff)|value)
}
func (o *BITSCRAMBLER_Type) GetTX_LUT_CFG0_TX_LUT_IDX() uint32 {
	return volatile.LoadUint32(&o.TX_LUT_CFG0.Reg) & 0x7ff
}
func (o *BITSCRAMBLER_Type) SetTX_LUT_CFG0_TX_LUT_MODE(value uint32) {
	volatile.StoreUint32(&o.TX_LUT_CFG0.Reg, volatile.LoadUint32(&o.TX_LUT_CFG0.Reg)&^(0x1800)|value<<11)
}
func (o *BITSCRAMBLER_Type) GetTX_LUT_CFG0_TX_LUT_MODE() uint32 {
	return (volatile.LoadUint32(&o.TX_LUT_CFG0.Reg) & 0x1800) >> 11
}

// BITSCRAMBLER.TX_LUT_CFG1: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetTX_LUT_CFG1(value uint32) {
	volatile.StoreUint32(&o.TX_LUT_CFG1.Reg, value)
}
func (o *BITSCRAMBLER_Type) GetTX_LUT_CFG1() uint32 {
	return volatile.LoadUint32(&o.TX_LUT_CFG1.Reg)
}

// BITSCRAMBLER.RX_LUT_CFG0: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetRX_LUT_CFG0_RX_LUT_IDX(value uint32) {
	volatile.StoreUint32(&o.RX_LUT_CFG0.Reg, volatile.LoadUint32(&o.RX_LUT_CFG0.Reg)&^(0x7ff)|value)
}
func (o *BITSCRAMBLER_Type) GetRX_LUT_CFG0_RX_LUT_IDX() uint32 {
	return volatile.LoadUint32(&o.RX_LUT_CFG0.Reg) & 0x7ff
}
func (o *BITSCRAMBLER_Type) SetRX_LUT_CFG0_RX_LUT_MODE(value uint32) {
	volatile.StoreUint32(&o.RX_LUT_CFG0.Reg, volatile.LoadUint32(&o.RX_LUT_CFG0.Reg)&^(0x1800)|value<<11)
}
func (o *BITSCRAMBLER_Type) GetRX_LUT_CFG0_RX_LUT_MODE() uint32 {
	return (volatile.LoadUint32(&o.RX_LUT_CFG0.Reg) & 0x1800) >> 11
}

// BITSCRAMBLER.RX_LUT_CFG1: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetRX_LUT_CFG1(value uint32) {
	volatile.StoreUint32(&o.RX_LUT_CFG1.Reg, value)
}
func (o *BITSCRAMBLER_Type) GetRX_LUT_CFG1() uint32 {
	return volatile.LoadUint32(&o.RX_LUT_CFG1.Reg)
}

// BITSCRAMBLER.TX_TAILING_BITS: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetTX_TAILING_BITS(value uint32) {
	volatile.StoreUint32(&o.TX_TAILING_BITS.Reg, volatile.LoadUint32(&o.TX_TAILING_BITS.Reg)&^(0xffff)|value)
}
func (o *BITSCRAMBLER_Type) GetTX_TAILING_BITS() uint32 {
	return volatile.LoadUint32(&o.TX_TAILING_BITS.Reg) & 0xffff
}

// BITSCRAMBLER.RX_TAILING_BITS: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetRX_TAILING_BITS(value uint32) {
	volatile.StoreUint32(&o.RX_TAILING_BITS.Reg, volatile.LoadUint32(&o.RX_TAILING_BITS.Reg)&^(0xffff)|value)
}
func (o *BITSCRAMBLER_Type) GetRX_TAILING_BITS() uint32 {
	return volatile.LoadUint32(&o.RX_TAILING_BITS.Reg) & 0xffff
}

// BITSCRAMBLER.TX_CTRL: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_ENA(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x1)|value)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_ENA() uint32 {
	return volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x1
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_PAUSE(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x2) >> 1
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_HALT(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_HALT() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x4) >> 2
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_EOF_MODE(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_EOF_MODE() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x8) >> 3
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_COND_MODE(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_COND_MODE() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x10) >> 4
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_FETCH_MODE(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_FETCH_MODE() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x20) >> 5
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_HALT_MODE(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_HALT_MODE() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x40) >> 6
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_RD_DUMMY(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_RD_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x80) >> 7
}
func (o *BITSCRAMBLER_Type) SetTX_CTRL_TX_FIFO_RST(value uint32) {
	volatile.StoreUint32(&o.TX_CTRL.Reg, volatile.LoadUint32(&o.TX_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *BITSCRAMBLER_Type) GetTX_CTRL_TX_FIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.TX_CTRL.Reg) & 0x100) >> 8
}

// BITSCRAMBLER.RX_CTRL: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_ENA(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x1)|value)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_ENA() uint32 {
	return volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x1
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_PAUSE(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x2) >> 1
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_HALT(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_HALT() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x4) >> 2
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_EOF_MODE(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_EOF_MODE() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x8) >> 3
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_COND_MODE(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_COND_MODE() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x10) >> 4
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_FETCH_MODE(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_FETCH_MODE() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x20) >> 5
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_HALT_MODE(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_HALT_MODE() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x40) >> 6
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_RD_DUMMY(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_RD_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x80) >> 7
}
func (o *BITSCRAMBLER_Type) SetRX_CTRL_RX_FIFO_RST(value uint32) {
	volatile.StoreUint32(&o.RX_CTRL.Reg, volatile.LoadUint32(&o.RX_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *BITSCRAMBLER_Type) GetRX_CTRL_RX_FIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.RX_CTRL.Reg) & 0x100) >> 8
}

// BITSCRAMBLER.TX_STATE: Status registers
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_IDLE(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x1)|value)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_IDLE() uint32 {
	return volatile.LoadUint32(&o.TX_STATE.Reg) & 0x1
}
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_RUN(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x2)|value<<1)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_RUN() uint32 {
	return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x2) >> 1
}
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_WAIT(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x4)|value<<2)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_WAIT() uint32 {
	return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x4) >> 2
}
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_IN_PAUSE(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x8)|value<<3)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_IN_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x8) >> 3
}
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_FIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x10)|value<<4)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_FIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x10) >> 4
}
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_EOF_GET_CNT(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_EOF_GET_CNT() uint32 {
	return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x3fff0000) >> 16
}
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_EOF_OVERLOAD(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x40000000)|value<<30)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_EOF_OVERLOAD() uint32 {
	return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x40000000) >> 30
}
func (o *BITSCRAMBLER_Type) SetTX_STATE_TX_EOF_TRACE_CLR(value uint32) {
	volatile.StoreUint32(&o.TX_STATE.Reg, volatile.LoadUint32(&o.TX_STATE.Reg)&^(0x80000000)|value<<31)
}
func (o *BITSCRAMBLER_Type) GetTX_STATE_TX_EOF_TRACE_CLR() uint32 {
	return (volatile.LoadUint32(&o.TX_STATE.Reg) & 0x80000000) >> 31
}

// BITSCRAMBLER.RX_STATE: Status registers
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_IDLE(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x1)|value)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_IDLE() uint32 {
	return volatile.LoadUint32(&o.RX_STATE.Reg) & 0x1
}
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_RUN(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x2)|value<<1)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_RUN() uint32 {
	return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x2) >> 1
}
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_WAIT(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x4)|value<<2)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_WAIT() uint32 {
	return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x4) >> 2
}
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_IN_PAUSE(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x8)|value<<3)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_IN_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x8) >> 3
}
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_FIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x10)|value<<4)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_FIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x10) >> 4
}
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_EOF_GET_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_EOF_GET_CNT() uint32 {
	return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x3fff0000) >> 16
}
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_EOF_OVERLOAD(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x40000000)|value<<30)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_EOF_OVERLOAD() uint32 {
	return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x40000000) >> 30
}
func (o *BITSCRAMBLER_Type) SetRX_STATE_RX_EOF_TRACE_CLR(value uint32) {
	volatile.StoreUint32(&o.RX_STATE.Reg, volatile.LoadUint32(&o.RX_STATE.Reg)&^(0x80000000)|value<<31)
}
func (o *BITSCRAMBLER_Type) GetRX_STATE_RX_EOF_TRACE_CLR() uint32 {
	return (volatile.LoadUint32(&o.RX_STATE.Reg) & 0x80000000) >> 31
}

// BITSCRAMBLER.SYS: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetSYS_LOOP_MODE(value uint32) {
	volatile.StoreUint32(&o.SYS.Reg, volatile.LoadUint32(&o.SYS.Reg)&^(0x1)|value)
}
func (o *BITSCRAMBLER_Type) GetSYS_LOOP_MODE() uint32 {
	return volatile.LoadUint32(&o.SYS.Reg) & 0x1
}
func (o *BITSCRAMBLER_Type) SetSYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SYS.Reg, volatile.LoadUint32(&o.SYS.Reg)&^(0x80000000)|value<<31)
}
func (o *BITSCRAMBLER_Type) GetSYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SYS.Reg) & 0x80000000) >> 31
}

// BITSCRAMBLER.VERSION: Control and configuration registers
func (o *BITSCRAMBLER_Type) SetVERSION_BITSCRAMBLER_VER(value uint32) {
	volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value)
}
func (o *BITSCRAMBLER_Type) GetVERSION_BITSCRAMBLER_VER() uint32 {
	return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff
}

// CACHE Peripheral
type CACHE_Type struct {
	L1_ICACHE_CTRL                  volatile.Register32 // 0x0
	L1_DCACHE_CTRL                  volatile.Register32 // 0x4
	L1_BYPASS_CACHE_CONF            volatile.Register32 // 0x8
	L1_CACHE_ATOMIC_CONF            volatile.Register32 // 0xC
	L1_ICACHE_CACHESIZE_CONF        volatile.Register32 // 0x10
	L1_ICACHE_BLOCKSIZE_CONF        volatile.Register32 // 0x14
	L1_DCACHE_CACHESIZE_CONF        volatile.Register32 // 0x18
	L1_DCACHE_BLOCKSIZE_CONF        volatile.Register32 // 0x1C
	L1_CACHE_WRAP_AROUND_CTRL       volatile.Register32 // 0x20
	L1_CACHE_TAG_MEM_POWER_CTRL     volatile.Register32 // 0x24
	L1_CACHE_DATA_MEM_POWER_CTRL    volatile.Register32 // 0x28
	L1_CACHE_FREEZE_CTRL            volatile.Register32 // 0x2C
	L1_CACHE_DATA_MEM_ACS_CONF      volatile.Register32 // 0x30
	L1_CACHE_TAG_MEM_ACS_CONF       volatile.Register32 // 0x34
	L1_ICACHE0_PRELOCK_CONF         volatile.Register32 // 0x38
	L1_ICACHE0_PRELOCK_SCT0_ADDR    volatile.Register32 // 0x3C
	L1_ICACHE0_PRELOCK_SCT1_ADDR    volatile.Register32 // 0x40
	L1_ICACHE0_PRELOCK_SCT_SIZE     volatile.Register32 // 0x44
	L1_ICACHE1_PRELOCK_CONF         volatile.Register32 // 0x48
	L1_ICACHE1_PRELOCK_SCT0_ADDR    volatile.Register32 // 0x4C
	L1_ICACHE1_PRELOCK_SCT1_ADDR    volatile.Register32 // 0x50
	L1_ICACHE1_PRELOCK_SCT_SIZE     volatile.Register32 // 0x54
	L1_ICACHE2_PRELOCK_CONF         volatile.Register32 // 0x58
	L1_ICACHE2_PRELOCK_SCT0_ADDR    volatile.Register32 // 0x5C
	L1_ICACHE2_PRELOCK_SCT1_ADDR    volatile.Register32 // 0x60
	L1_ICACHE2_PRELOCK_SCT_SIZE     volatile.Register32 // 0x64
	L1_ICACHE3_PRELOCK_CONF         volatile.Register32 // 0x68
	L1_ICACHE3_PRELOCK_SCT0_ADDR    volatile.Register32 // 0x6C
	L1_ICACHE3_PRELOCK_SCT1_ADDR    volatile.Register32 // 0x70
	L1_ICACHE3_PRELOCK_SCT_SIZE     volatile.Register32 // 0x74
	L1_DCACHE_PRELOCK_CONF          volatile.Register32 // 0x78
	L1_DCACHE_PRELOCK_SCT0_ADDR     volatile.Register32 // 0x7C
	L1_DCACHE_PRELOCK_SCT1_ADDR     volatile.Register32 // 0x80
	L1_DCACHE_PRELOCK_SCT_SIZE      volatile.Register32 // 0x84
	LOCK_CTRL                       volatile.Register32 // 0x88
	LOCK_MAP                        volatile.Register32 // 0x8C
	LOCK_ADDR                       volatile.Register32 // 0x90
	LOCK_SIZE                       volatile.Register32 // 0x94
	SYNC_CTRL                       volatile.Register32 // 0x98
	SYNC_MAP                        volatile.Register32 // 0x9C
	SYNC_ADDR                       volatile.Register32 // 0xA0
	SYNC_SIZE                       volatile.Register32 // 0xA4
	L1_ICACHE0_PRELOAD_CTRL         volatile.Register32 // 0xA8
	L1_ICACHE0_PRELOAD_ADDR         volatile.Register32 // 0xAC
	L1_ICACHE0_PRELOAD_SIZE         volatile.Register32 // 0xB0
	L1_ICACHE1_PRELOAD_CTRL         volatile.Register32 // 0xB4
	L1_ICACHE1_PRELOAD_ADDR         volatile.Register32 // 0xB8
	L1_ICACHE1_PRELOAD_SIZE         volatile.Register32 // 0xBC
	L1_ICACHE2_PRELOAD_CTRL         volatile.Register32 // 0xC0
	L1_ICACHE2_PRELOAD_ADDR         volatile.Register32 // 0xC4
	L1_ICACHE2_PRELOAD_SIZE         volatile.Register32 // 0xC8
	L1_ICACHE3_PRELOAD_CTRL         volatile.Register32 // 0xCC
	L1_ICACHE3_PRELOAD_ADDR         volatile.Register32 // 0xD0
	L1_ICACHE3_PRELOAD_SIZE         volatile.Register32 // 0xD4
	L1_DCACHE_PRELOAD_CTRL          volatile.Register32 // 0xD8
	L1_DCACHE_PRELOAD_ADDR          volatile.Register32 // 0xDC
	L1_DCACHE_PRELOAD_SIZE          volatile.Register32 // 0xE0
	L1_ICACHE0_AUTOLOAD_CTRL        volatile.Register32 // 0xE4
	L1_ICACHE0_AUTOLOAD_SCT0_ADDR   volatile.Register32 // 0xE8
	L1_ICACHE0_AUTOLOAD_SCT0_SIZE   volatile.Register32 // 0xEC
	L1_ICACHE0_AUTOLOAD_SCT1_ADDR   volatile.Register32 // 0xF0
	L1_ICACHE0_AUTOLOAD_SCT1_SIZE   volatile.Register32 // 0xF4
	L1_ICACHE1_AUTOLOAD_CTRL        volatile.Register32 // 0xF8
	L1_ICACHE1_AUTOLOAD_SCT0_ADDR   volatile.Register32 // 0xFC
	L1_ICACHE1_AUTOLOAD_SCT0_SIZE   volatile.Register32 // 0x100
	L1_ICACHE1_AUTOLOAD_SCT1_ADDR   volatile.Register32 // 0x104
	L1_ICACHE1_AUTOLOAD_SCT1_SIZE   volatile.Register32 // 0x108
	L1_ICACHE2_AUTOLOAD_CTRL        volatile.Register32 // 0x10C
	L1_ICACHE2_AUTOLOAD_SCT0_ADDR   volatile.Register32 // 0x110
	L1_ICACHE2_AUTOLOAD_SCT0_SIZE   volatile.Register32 // 0x114
	L1_ICACHE2_AUTOLOAD_SCT1_ADDR   volatile.Register32 // 0x118
	L1_ICACHE2_AUTOLOAD_SCT1_SIZE   volatile.Register32 // 0x11C
	L1_ICACHE3_AUTOLOAD_CTRL        volatile.Register32 // 0x120
	L1_ICACHE3_AUTOLOAD_SCT0_ADDR   volatile.Register32 // 0x124
	L1_ICACHE3_AUTOLOAD_SCT0_SIZE   volatile.Register32 // 0x128
	L1_ICACHE3_AUTOLOAD_SCT1_ADDR   volatile.Register32 // 0x12C
	L1_ICACHE3_AUTOLOAD_SCT1_SIZE   volatile.Register32 // 0x130
	L1_DCACHE_AUTOLOAD_CTRL         volatile.Register32 // 0x134
	L1_DCACHE_AUTOLOAD_SCT0_ADDR    volatile.Register32 // 0x138
	L1_DCACHE_AUTOLOAD_SCT0_SIZE    volatile.Register32 // 0x13C
	L1_DCACHE_AUTOLOAD_SCT1_ADDR    volatile.Register32 // 0x140
	L1_DCACHE_AUTOLOAD_SCT1_SIZE    volatile.Register32 // 0x144
	L1_DCACHE_AUTOLOAD_SCT2_ADDR    volatile.Register32 // 0x148
	L1_DCACHE_AUTOLOAD_SCT2_SIZE    volatile.Register32 // 0x14C
	L1_DCACHE_AUTOLOAD_SCT3_ADDR    volatile.Register32 // 0x150
	L1_DCACHE_AUTOLOAD_SCT3_SIZE    volatile.Register32 // 0x154
	L1_CACHE_ACS_CNT_INT_ENA        volatile.Register32 // 0x158
	L1_CACHE_ACS_CNT_INT_CLR        volatile.Register32 // 0x15C
	L1_CACHE_ACS_CNT_INT_RAW        volatile.Register32 // 0x160
	L1_CACHE_ACS_CNT_INT_ST         volatile.Register32 // 0x164
	L1_CACHE_ACS_FAIL_CTRL          volatile.Register32 // 0x168
	L1_CACHE_ACS_FAIL_INT_ENA       volatile.Register32 // 0x16C
	L1_CACHE_ACS_FAIL_INT_CLR       volatile.Register32 // 0x170
	L1_CACHE_ACS_FAIL_INT_RAW       volatile.Register32 // 0x174
	L1_CACHE_ACS_FAIL_INT_ST        volatile.Register32 // 0x178
	L1_CACHE_ACS_CNT_CTRL           volatile.Register32 // 0x17C
	L1_IBUS0_ACS_HIT_CNT            volatile.Register32 // 0x180
	L1_IBUS0_ACS_MISS_CNT           volatile.Register32 // 0x184
	L1_IBUS0_ACS_CONFLICT_CNT       volatile.Register32 // 0x188
	L1_IBUS0_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x18C
	L1_IBUS1_ACS_HIT_CNT            volatile.Register32 // 0x190
	L1_IBUS1_ACS_MISS_CNT           volatile.Register32 // 0x194
	L1_IBUS1_ACS_CONFLICT_CNT       volatile.Register32 // 0x198
	L1_IBUS1_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x19C
	L1_IBUS2_ACS_HIT_CNT            volatile.Register32 // 0x1A0
	L1_IBUS2_ACS_MISS_CNT           volatile.Register32 // 0x1A4
	L1_IBUS2_ACS_CONFLICT_CNT       volatile.Register32 // 0x1A8
	L1_IBUS2_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x1AC
	L1_IBUS3_ACS_HIT_CNT            volatile.Register32 // 0x1B0
	L1_IBUS3_ACS_MISS_CNT           volatile.Register32 // 0x1B4
	L1_IBUS3_ACS_CONFLICT_CNT       volatile.Register32 // 0x1B8
	L1_IBUS3_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x1BC
	L1_DBUS0_ACS_HIT_CNT            volatile.Register32 // 0x1C0
	L1_DBUS0_ACS_MISS_CNT           volatile.Register32 // 0x1C4
	L1_DBUS0_ACS_CONFLICT_CNT       volatile.Register32 // 0x1C8
	L1_DBUS0_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x1CC
	L1_DBUS0_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x1D0
	L1_DBUS1_ACS_HIT_CNT            volatile.Register32 // 0x1D4
	L1_DBUS1_ACS_MISS_CNT           volatile.Register32 // 0x1D8
	L1_DBUS1_ACS_CONFLICT_CNT       volatile.Register32 // 0x1DC
	L1_DBUS1_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x1E0
	L1_DBUS1_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x1E4
	L1_DBUS2_ACS_HIT_CNT            volatile.Register32 // 0x1E8
	L1_DBUS2_ACS_MISS_CNT           volatile.Register32 // 0x1EC
	L1_DBUS2_ACS_CONFLICT_CNT       volatile.Register32 // 0x1F0
	L1_DBUS2_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x1F4
	L1_DBUS2_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x1F8
	L1_DBUS3_ACS_HIT_CNT            volatile.Register32 // 0x1FC
	L1_DBUS3_ACS_MISS_CNT           volatile.Register32 // 0x200
	L1_DBUS3_ACS_CONFLICT_CNT       volatile.Register32 // 0x204
	L1_DBUS3_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x208
	L1_DBUS3_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x20C
	L1_ICACHE0_ACS_FAIL_ID_ATTR     volatile.Register32 // 0x210
	L1_ICACHE0_ACS_FAIL_ADDR        volatile.Register32 // 0x214
	L1_ICACHE1_ACS_FAIL_ID_ATTR     volatile.Register32 // 0x218
	L1_ICACHE1_ACS_FAIL_ADDR        volatile.Register32 // 0x21C
	L1_ICACHE2_ACS_FAIL_ID_ATTR     volatile.Register32 // 0x220
	L1_ICACHE2_ACS_FAIL_ADDR        volatile.Register32 // 0x224
	L1_ICACHE3_ACS_FAIL_ID_ATTR     volatile.Register32 // 0x228
	L1_ICACHE3_ACS_FAIL_ADDR        volatile.Register32 // 0x22C
	L1_DCACHE_ACS_FAIL_ID_ATTR      volatile.Register32 // 0x230
	L1_DCACHE_ACS_FAIL_ADDR         volatile.Register32 // 0x234
	SYNC_L1_CACHE_PRELOAD_INT_ENA   volatile.Register32 // 0x238
	SYNC_L1_CACHE_PRELOAD_INT_CLR   volatile.Register32 // 0x23C
	SYNC_L1_CACHE_PRELOAD_INT_RAW   volatile.Register32 // 0x240
	SYNC_L1_CACHE_PRELOAD_INT_ST    volatile.Register32 // 0x244
	SYNC_L1_CACHE_PRELOAD_EXCEPTION volatile.Register32 // 0x248
	L1_CACHE_SYNC_RST_CTRL          volatile.Register32 // 0x24C
	L1_CACHE_PRELOAD_RST_CTRL       volatile.Register32 // 0x250
	L1_CACHE_AUTOLOAD_BUF_CLR_CTRL  volatile.Register32 // 0x254
	L1_UNALLOCATE_BUFFER_CLEAR      volatile.Register32 // 0x258
	L1_CACHE_OBJECT_CTRL            volatile.Register32 // 0x25C
	L1_CACHE_WAY_OBJECT             volatile.Register32 // 0x260
	L1_CACHE_VADDR                  volatile.Register32 // 0x264
	L1_CACHE_DEBUG_BUS              volatile.Register32 // 0x268
	LEVEL_SPLIT0                    volatile.Register32 // 0x26C
	L2_CACHE_CTRL                   volatile.Register32 // 0x270
	L2_BYPASS_CACHE_CONF            volatile.Register32 // 0x274
	L2_CACHE_CACHESIZE_CONF         volatile.Register32 // 0x278
	L2_CACHE_BLOCKSIZE_CONF         volatile.Register32 // 0x27C
	L2_CACHE_WRAP_AROUND_CTRL       volatile.Register32 // 0x280
	L2_CACHE_TAG_MEM_POWER_CTRL     volatile.Register32 // 0x284
	L2_CACHE_DATA_MEM_POWER_CTRL    volatile.Register32 // 0x288
	L2_CACHE_FREEZE_CTRL            volatile.Register32 // 0x28C
	L2_CACHE_DATA_MEM_ACS_CONF      volatile.Register32 // 0x290
	L2_CACHE_TAG_MEM_ACS_CONF       volatile.Register32 // 0x294
	L2_CACHE_PRELOCK_CONF           volatile.Register32 // 0x298
	L2_CACHE_PRELOCK_SCT0_ADDR      volatile.Register32 // 0x29C
	L2_CACHE_PRELOCK_SCT1_ADDR      volatile.Register32 // 0x2A0
	L2_CACHE_PRELOCK_SCT_SIZE       volatile.Register32 // 0x2A4
	L2_CACHE_PRELOAD_CTRL           volatile.Register32 // 0x2A8
	L2_CACHE_PRELOAD_ADDR           volatile.Register32 // 0x2AC
	L2_CACHE_PRELOAD_SIZE           volatile.Register32 // 0x2B0
	L2_CACHE_AUTOLOAD_CTRL          volatile.Register32 // 0x2B4
	L2_CACHE_AUTOLOAD_SCT0_ADDR     volatile.Register32 // 0x2B8
	L2_CACHE_AUTOLOAD_SCT0_SIZE     volatile.Register32 // 0x2BC
	L2_CACHE_AUTOLOAD_SCT1_ADDR     volatile.Register32 // 0x2C0
	L2_CACHE_AUTOLOAD_SCT1_SIZE     volatile.Register32 // 0x2C4
	L2_CACHE_AUTOLOAD_SCT2_ADDR     volatile.Register32 // 0x2C8
	L2_CACHE_AUTOLOAD_SCT2_SIZE     volatile.Register32 // 0x2CC
	L2_CACHE_AUTOLOAD_SCT3_ADDR     volatile.Register32 // 0x2D0
	L2_CACHE_AUTOLOAD_SCT3_SIZE     volatile.Register32 // 0x2D4
	L2_CACHE_ACS_CNT_INT_ENA        volatile.Register32 // 0x2D8
	L2_CACHE_ACS_CNT_INT_CLR        volatile.Register32 // 0x2DC
	L2_CACHE_ACS_CNT_INT_RAW        volatile.Register32 // 0x2E0
	L2_CACHE_ACS_CNT_INT_ST         volatile.Register32 // 0x2E4
	L2_CACHE_ACS_FAIL_CTRL          volatile.Register32 // 0x2E8
	L2_CACHE_ACS_FAIL_INT_ENA       volatile.Register32 // 0x2EC
	L2_CACHE_ACS_FAIL_INT_CLR       volatile.Register32 // 0x2F0
	L2_CACHE_ACS_FAIL_INT_RAW       volatile.Register32 // 0x2F4
	L2_CACHE_ACS_FAIL_INT_ST        volatile.Register32 // 0x2F8
	L2_CACHE_ACS_CNT_CTRL           volatile.Register32 // 0x2FC
	L2_IBUS0_ACS_HIT_CNT            volatile.Register32 // 0x300
	L2_IBUS0_ACS_MISS_CNT           volatile.Register32 // 0x304
	L2_IBUS0_ACS_CONFLICT_CNT       volatile.Register32 // 0x308
	L2_IBUS0_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x30C
	L2_IBUS1_ACS_HIT_CNT            volatile.Register32 // 0x310
	L2_IBUS1_ACS_MISS_CNT           volatile.Register32 // 0x314
	L2_IBUS1_ACS_CONFLICT_CNT       volatile.Register32 // 0x318
	L2_IBUS1_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x31C
	L2_IBUS2_ACS_HIT_CNT            volatile.Register32 // 0x320
	L2_IBUS2_ACS_MISS_CNT           volatile.Register32 // 0x324
	L2_IBUS2_ACS_CONFLICT_CNT       volatile.Register32 // 0x328
	L2_IBUS2_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x32C
	L2_IBUS3_ACS_HIT_CNT            volatile.Register32 // 0x330
	L2_IBUS3_ACS_MISS_CNT           volatile.Register32 // 0x334
	L2_IBUS3_ACS_CONFLICT_CNT       volatile.Register32 // 0x338
	L2_IBUS3_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x33C
	L2_DBUS0_ACS_HIT_CNT            volatile.Register32 // 0x340
	L2_DBUS0_ACS_MISS_CNT           volatile.Register32 // 0x344
	L2_DBUS0_ACS_CONFLICT_CNT       volatile.Register32 // 0x348
	L2_DBUS0_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x34C
	L2_DBUS0_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x350
	L2_DBUS1_ACS_HIT_CNT            volatile.Register32 // 0x354
	L2_DBUS1_ACS_MISS_CNT           volatile.Register32 // 0x358
	L2_DBUS1_ACS_CONFLICT_CNT       volatile.Register32 // 0x35C
	L2_DBUS1_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x360
	L2_DBUS1_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x364
	L2_DBUS2_ACS_HIT_CNT            volatile.Register32 // 0x368
	L2_DBUS2_ACS_MISS_CNT           volatile.Register32 // 0x36C
	L2_DBUS2_ACS_CONFLICT_CNT       volatile.Register32 // 0x370
	L2_DBUS2_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x374
	L2_DBUS2_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x378
	L2_DBUS3_ACS_HIT_CNT            volatile.Register32 // 0x37C
	L2_DBUS3_ACS_MISS_CNT           volatile.Register32 // 0x380
	L2_DBUS3_ACS_CONFLICT_CNT       volatile.Register32 // 0x384
	L2_DBUS3_ACS_NXTLVL_RD_CNT      volatile.Register32 // 0x388
	L2_DBUS3_ACS_NXTLVL_WR_CNT      volatile.Register32 // 0x38C
	L2_CACHE_ACS_FAIL_ID_ATTR       volatile.Register32 // 0x390
	L2_CACHE_ACS_FAIL_ADDR          volatile.Register32 // 0x394
	L2_CACHE_SYNC_PRELOAD_INT_ENA   volatile.Register32 // 0x398
	L2_CACHE_SYNC_PRELOAD_INT_CLR   volatile.Register32 // 0x39C
	L2_CACHE_SYNC_PRELOAD_INT_RAW   volatile.Register32 // 0x3A0
	L2_CACHE_SYNC_PRELOAD_INT_ST    volatile.Register32 // 0x3A4
	L2_CACHE_SYNC_PRELOAD_EXCEPTION volatile.Register32 // 0x3A8
	L2_CACHE_SYNC_RST_CTRL          volatile.Register32 // 0x3AC
	L2_CACHE_PRELOAD_RST_CTRL       volatile.Register32 // 0x3B0
	L2_CACHE_AUTOLOAD_BUF_CLR_CTRL  volatile.Register32 // 0x3B4
	L2_UNALLOCATE_BUFFER_CLEAR      volatile.Register32 // 0x3B8
	L2_CACHE_ACCESS_ATTR_CTRL       volatile.Register32 // 0x3BC
	L2_CACHE_OBJECT_CTRL            volatile.Register32 // 0x3C0
	L2_CACHE_WAY_OBJECT             volatile.Register32 // 0x3C4
	L2_CACHE_VADDR                  volatile.Register32 // 0x3C8
	L2_CACHE_DEBUG_BUS              volatile.Register32 // 0x3CC
	LEVEL_SPLIT1                    volatile.Register32 // 0x3D0
	CLOCK_GATE                      volatile.Register32 // 0x3D4
	REDUNDANCY_SIG0                 volatile.Register32 // 0x3D8
	REDUNDANCY_SIG1                 volatile.Register32 // 0x3DC
	REDUNDANCY_SIG2                 volatile.Register32 // 0x3E0
	REDUNDANCY_SIG3                 volatile.Register32 // 0x3E4
	REDUNDANCY_SIG4                 volatile.Register32 // 0x3E8
	_                               [16]byte
	DATE                            volatile.Register32 // 0x3FC
}

// CACHE.L1_ICACHE_CTRL: L1 instruction Cache(L1-ICache) control register
func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *CACHE_Type) GetL1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CTRL.Reg) & 0xff00) >> 8
}

// CACHE.L1_DCACHE_CTRL: L1 data Cache(L1-DCache) control register
func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS0(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS0() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS1(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS1() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS2(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS2() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS3(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS3() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DMA(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_SHUT_DMA() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_DCACHE_CTRL_L1_DCACHE_UNDEF_OP(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *CACHE_Type) GetL1_DCACHE_CTRL_L1_DCACHE_UNDEF_OP() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CTRL.Reg) & 0xff00) >> 8
}

// CACHE.L1_BYPASS_CACHE_CONF: Bypass Cache configure register
func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN(value uint32) {
	volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN() uint32 {
	return volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN(value uint32) {
	volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN(value uint32) {
	volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN(value uint32) {
	volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN(value uint32) {
	volatile.StoreUint32(&o.L1_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_BYPASS_CACHE_CONF.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_ATOMIC_CONF: L1 Cache atomic feature configure register
func (o *CACHE_Type) SetL1_CACHE_ATOMIC_CONF_L1_DCACHE_ATOMIC_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ATOMIC_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_ATOMIC_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ATOMIC_CONF_L1_DCACHE_ATOMIC_EN() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ATOMIC_CONF.Reg) & 0x1
}

// CACHE.L1_ICACHE_CACHESIZE_CONF: L1 instruction Cache CacheSize mode configure register
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12
}

// CACHE.L1_ICACHE_BLOCKSIZE_CONF: L1 instruction Cache BlockSize mode configure register
func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5
}

// CACHE.L1_DCACHE_CACHESIZE_CONF: L1 data Cache CacheSize mode configure register
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_2K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_2K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_4K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_4K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_8K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_8K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_16K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_16K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_32K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_32K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_64K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_64K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_128K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_128K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1024K(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1024K() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12
}

// CACHE.L1_DCACHE_BLOCKSIZE_CONF: L1 data Cache BlockSize mode configure register
func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_8(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_8() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_16(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_16() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_32(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_32() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_64(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_64() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_128(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_128() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_256(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_256() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5
}

// CACHE.L1_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register
func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_WRAP_AROUND_CTRL_L1_DCACHE_WRAP(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_WRAP_AROUND_CTRL_L1_DCACHE_WRAP() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_WRAP_AROUND_CTRL.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x10000) >> 16
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x20000) >> 17
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x40000) >> 18
}

// CACHE.L1_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x10000) >> 16
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x20000) >> 17
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x40000) >> 18
}

// CACHE.L1_CACHE_FREEZE_CTRL: Cache Freeze control register
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x10000) >> 16
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x20000) >> 17
}
func (o *CACHE_Type) SetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *CACHE_Type) GetL1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_FREEZE_CTRL.Reg) & 0x40000) >> 18
}

// CACHE.L1_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x10000)|value<<16)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x10000) >> 16
}
func (o *CACHE_Type) SetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x20000)|value<<17)
}
func (o *CACHE_Type) GetL1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x20000) >> 17
}

// CACHE.L1_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x10000)|value<<16)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x10000) >> 16
}
func (o *CACHE_Type) SetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x20000)|value<<17)
}
func (o *CACHE_Type) GetL1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x20000) >> 17
}

// CACHE.L1_ICACHE0_PRELOCK_CONF: L1 instruction Cache 0 prelock configure register
func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg)&^(0x3c)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_CONF.Reg) & 0x3c) >> 2
}

// CACHE.L1_ICACHE0_PRELOCK_SCT0_ADDR: L1 instruction Cache 0 prelock section0 address configure register
func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE0_PRELOCK_SCT1_ADDR: L1 instruction Cache 0 prelock section1 address configure register
func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE0_PRELOCK_SCT_SIZE: L1 instruction Cache 0 prelock section size configure register
func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg) & 0x3fff
}
func (o *CACHE_Type) SetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16
}

// CACHE.L1_ICACHE1_PRELOCK_CONF: L1 instruction Cache 1 prelock configure register
func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg)&^(0x3c)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_CONF.Reg) & 0x3c) >> 2
}

// CACHE.L1_ICACHE1_PRELOCK_SCT0_ADDR: L1 instruction Cache 1 prelock section0 address configure register
func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE1_PRELOCK_SCT1_ADDR: L1 instruction Cache 1 prelock section1 address configure register
func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE1_PRELOCK_SCT_SIZE: L1 instruction Cache 1 prelock section size configure register
func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg) & 0x3fff
}
func (o *CACHE_Type) SetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16
}

// CACHE.L1_ICACHE2_PRELOCK_CONF: L1 instruction Cache 2 prelock configure register
func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg)&^(0x3c)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_CONF.Reg) & 0x3c) >> 2
}

// CACHE.L1_ICACHE2_PRELOCK_SCT0_ADDR: L1 instruction Cache 2 prelock section0 address configure register
func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE2_PRELOCK_SCT1_ADDR: L1 instruction Cache 2 prelock section1 address configure register
func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE2_PRELOCK_SCT_SIZE: L1 instruction Cache 2 prelock section size configure register
func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg) & 0x3fff
}
func (o *CACHE_Type) SetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16
}

// CACHE.L1_ICACHE3_PRELOCK_CONF: L1 instruction Cache 3 prelock configure register
func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg)&^(0x3c)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_CONF.Reg) & 0x3c) >> 2
}

// CACHE.L1_ICACHE3_PRELOCK_SCT0_ADDR: L1 instruction Cache 3 prelock section0 address configure register
func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE3_PRELOCK_SCT1_ADDR: L1 instruction Cache 3 prelock section1 address configure register
func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE3_PRELOCK_SCT_SIZE: L1 instruction Cache 3 prelock section size configure register
func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg) & 0x3fff
}
func (o *CACHE_Type) SetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16
}

// CACHE.L1_DCACHE_PRELOCK_CONF: L1 data Cache prelock configure register
func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT0_EN(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT0_EN() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT1_EN(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT1_EN() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg)&^(0x3c)|value<<2)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_CONF.Reg) & 0x3c) >> 2
}

// CACHE.L1_DCACHE_PRELOCK_SCT0_ADDR: L1 data Cache prelock section0 address configure register
func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT0_ADDR.Reg)
}

// CACHE.L1_DCACHE_PRELOCK_SCT1_ADDR: L1 data Cache prelock section1 address configure register
func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT1_ADDR.Reg)
}

// CACHE.L1_DCACHE_PRELOCK_SCT_SIZE: L1 data Cache prelock section size configure register
func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg) & 0x3fff
}
func (o *CACHE_Type) SetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT1_SIZE() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_PRELOCK_SCT_SIZE.Reg) & 0x3fff0000) >> 16
}

// CACHE.LOCK_CTRL: Lock-class (manual lock) operation control register
func (o *CACHE_Type) SetLOCK_CTRL_LOCK_ENA(value uint32) {
	volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetLOCK_CTRL_LOCK_ENA() uint32 {
	return volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetLOCK_CTRL_UNLOCK_ENA(value uint32) {
	volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetLOCK_CTRL_UNLOCK_ENA() uint32 {
	return (volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetLOCK_CTRL_LOCK_DONE(value uint32) {
	volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetLOCK_CTRL_LOCK_DONE() uint32 {
	return (volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetLOCK_CTRL_LOCK_RGID(value uint32) {
	volatile.StoreUint32(&o.LOCK_CTRL.Reg, volatile.LoadUint32(&o.LOCK_CTRL.Reg)&^(0x78)|value<<3)
}
func (o *CACHE_Type) GetLOCK_CTRL_LOCK_RGID() uint32 {
	return (volatile.LoadUint32(&o.LOCK_CTRL.Reg) & 0x78) >> 3
}

// CACHE.LOCK_MAP: Lock (manual lock) map configure register
func (o *CACHE_Type) SetLOCK_MAP(value uint32) {
	volatile.StoreUint32(&o.LOCK_MAP.Reg, volatile.LoadUint32(&o.LOCK_MAP.Reg)&^(0x3f)|value)
}
func (o *CACHE_Type) GetLOCK_MAP() uint32 {
	return volatile.LoadUint32(&o.LOCK_MAP.Reg) & 0x3f
}

// CACHE.LOCK_ADDR: Lock (manual lock) address configure register
func (o *CACHE_Type) SetLOCK_ADDR(value uint32) {
	volatile.StoreUint32(&o.LOCK_ADDR.Reg, value)
}
func (o *CACHE_Type) GetLOCK_ADDR() uint32 {
	return volatile.LoadUint32(&o.LOCK_ADDR.Reg)
}

// CACHE.LOCK_SIZE: Lock (manual lock) size configure register
func (o *CACHE_Type) SetLOCK_SIZE(value uint32) {
	volatile.StoreUint32(&o.LOCK_SIZE.Reg, volatile.LoadUint32(&o.LOCK_SIZE.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetLOCK_SIZE() uint32 {
	return volatile.LoadUint32(&o.LOCK_SIZE.Reg) & 0xffff
}

// CACHE.SYNC_CTRL: Sync-class operation control register
func (o *CACHE_Type) SetSYNC_CTRL_INVALIDATE_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetSYNC_CTRL_INVALIDATE_ENA() uint32 {
	return volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetSYNC_CTRL_CLEAN_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetSYNC_CTRL_CLEAN_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetSYNC_CTRL_WRITEBACK_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetSYNC_CTRL_WRITEBACK_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetSYNC_CTRL_WRITEBACK_INVALIDATE_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetSYNC_CTRL_WRITEBACK_INVALIDATE_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetSYNC_CTRL_SYNC_DONE(value uint32) {
	volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetSYNC_CTRL_SYNC_DONE() uint32 {
	return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetSYNC_CTRL_SYNC_RGID(value uint32) {
	volatile.StoreUint32(&o.SYNC_CTRL.Reg, volatile.LoadUint32(&o.SYNC_CTRL.Reg)&^(0x1e0)|value<<5)
}
func (o *CACHE_Type) GetSYNC_CTRL_SYNC_RGID() uint32 {
	return (volatile.LoadUint32(&o.SYNC_CTRL.Reg) & 0x1e0) >> 5
}

// CACHE.SYNC_MAP: Sync map configure register
func (o *CACHE_Type) SetSYNC_MAP(value uint32) {
	volatile.StoreUint32(&o.SYNC_MAP.Reg, volatile.LoadUint32(&o.SYNC_MAP.Reg)&^(0x3f)|value)
}
func (o *CACHE_Type) GetSYNC_MAP() uint32 {
	return volatile.LoadUint32(&o.SYNC_MAP.Reg) & 0x3f
}

// CACHE.SYNC_ADDR: Sync address configure register
func (o *CACHE_Type) SetSYNC_ADDR(value uint32) {
	volatile.StoreUint32(&o.SYNC_ADDR.Reg, value)
}
func (o *CACHE_Type) GetSYNC_ADDR() uint32 {
	return volatile.LoadUint32(&o.SYNC_ADDR.Reg)
}

// CACHE.SYNC_SIZE: Sync size configure register
func (o *CACHE_Type) SetSYNC_SIZE(value uint32) {
	volatile.StoreUint32(&o.SYNC_SIZE.Reg, volatile.LoadUint32(&o.SYNC_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetSYNC_SIZE() uint32 {
	return volatile.LoadUint32(&o.SYNC_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE0_PRELOAD_CTRL: L1 instruction Cache 0 preload-operation control register
func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg)&^(0x78)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_CTRL.Reg) & 0x78) >> 3
}

// CACHE.L1_ICACHE0_PRELOAD_ADDR: L1 instruction Cache 0 preload address configure register
func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_ADDR.Reg)
}

// CACHE.L1_ICACHE0_PRELOAD_SIZE: L1 instruction Cache 0 preload size configure register
func (o *CACHE_Type) SetL1_ICACHE0_PRELOAD_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_PRELOAD_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_PRELOAD_SIZE.Reg) & 0x3fff
}

// CACHE.L1_ICACHE1_PRELOAD_CTRL: L1 instruction Cache 1 preload-operation control register
func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg)&^(0x78)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_CTRL.Reg) & 0x78) >> 3
}

// CACHE.L1_ICACHE1_PRELOAD_ADDR: L1 instruction Cache 1 preload address configure register
func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_ADDR.Reg)
}

// CACHE.L1_ICACHE1_PRELOAD_SIZE: L1 instruction Cache 1 preload size configure register
func (o *CACHE_Type) SetL1_ICACHE1_PRELOAD_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_PRELOAD_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_PRELOAD_SIZE.Reg) & 0x3fff
}

// CACHE.L1_ICACHE2_PRELOAD_CTRL: L1 instruction Cache 2 preload-operation control register
func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg)&^(0x78)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_CTRL.Reg) & 0x78) >> 3
}

// CACHE.L1_ICACHE2_PRELOAD_ADDR: L1 instruction Cache 2 preload address configure register
func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_ADDR.Reg)
}

// CACHE.L1_ICACHE2_PRELOAD_SIZE: L1 instruction Cache 2 preload size configure register
func (o *CACHE_Type) SetL1_ICACHE2_PRELOAD_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_PRELOAD_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_PRELOAD_SIZE.Reg) & 0x3fff
}

// CACHE.L1_ICACHE3_PRELOAD_CTRL: L1 instruction Cache 3 preload-operation control register
func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg)&^(0x78)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_CTRL.Reg) & 0x78) >> 3
}

// CACHE.L1_ICACHE3_PRELOAD_ADDR: L1 instruction Cache 3 preload address configure register
func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_ADDR.Reg)
}

// CACHE.L1_ICACHE3_PRELOAD_SIZE: L1 instruction Cache 3 preload size configure register
func (o *CACHE_Type) SetL1_ICACHE3_PRELOAD_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_PRELOAD_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_PRELOAD_SIZE.Reg) & 0x3fff
}

// CACHE.L1_DCACHE_PRELOAD_CTRL: L1 data Cache preload-operation control register
func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg)&^(0x78)|value<<3)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_CTRL.Reg) & 0x78) >> 3
}

// CACHE.L1_DCACHE_PRELOAD_ADDR: L1 data Cache preload address configure register
func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_ADDR.Reg)
}

// CACHE.L1_DCACHE_PRELOAD_SIZE: L1 data Cache preload size configure register
func (o *CACHE_Type) SetL1_DCACHE_PRELOAD_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg)&^(0x3fff)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_PRELOAD_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_PRELOAD_SIZE.Reg) & 0x3fff
}

// CACHE.L1_ICACHE0_AUTOLOAD_CTRL: L1 instruction Cache 0 autoload-operation control register
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x18) >> 3
}
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10
}

// CACHE.L1_ICACHE0_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 0 autoload section 0 address configure register
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE0_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 0 autoload section 0 size configure register
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE0_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 0 autoload section 1 address configure register
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE0_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 0 autoload section 1 size configure register
func (o *CACHE_Type) SetL1_ICACHE0_AUTOLOAD_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_AUTOLOAD_SCT1_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE1_AUTOLOAD_CTRL: L1 instruction Cache 1 autoload-operation control register
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x18) >> 3
}
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10
}

// CACHE.L1_ICACHE1_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 1 autoload section 0 address configure register
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE1_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 1 autoload section 0 size configure register
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE1_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 1 autoload section 1 address configure register
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE1_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 1 autoload section 1 size configure register
func (o *CACHE_Type) SetL1_ICACHE1_AUTOLOAD_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_AUTOLOAD_SCT1_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE2_AUTOLOAD_CTRL: L1 instruction Cache 2 autoload-operation control register
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x18) >> 3
}
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10
}

// CACHE.L1_ICACHE2_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 2 autoload section 0 address configure register
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE2_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 2 autoload section 0 size configure register
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE2_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 2 autoload section 1 address configure register
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE2_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 2 autoload section 1 size configure register
func (o *CACHE_Type) SetL1_ICACHE2_AUTOLOAD_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_AUTOLOAD_SCT1_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE3_AUTOLOAD_CTRL: L1 instruction Cache 3 autoload-operation control register
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x18) >> 3
}
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg)&^(0x3c00)|value<<10)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_CTRL.Reg) & 0x3c00) >> 10
}

// CACHE.L1_ICACHE3_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 3 autoload section 0 address configure register
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_ADDR.Reg)
}

// CACHE.L1_ICACHE3_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 3 autoload section 0 size configure register
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_ICACHE3_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 3 autoload section 1 address configure register
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_ADDR.Reg)
}

// CACHE.L1_ICACHE3_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 3 autoload section 1 size configure register
func (o *CACHE_Type) SetL1_ICACHE3_AUTOLOAD_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_AUTOLOAD_SCT1_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_DCACHE_AUTOLOAD_CTRL: L1 data Cache autoload-operation control register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_TRIGGER_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_TRIGGER_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x18) >> 3
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT0_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT0_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT1_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT1_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT2_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT2_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT3_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT3_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg)&^(0xf000)|value<<12)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_CTRL.Reg) & 0xf000) >> 12
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT0_ADDR: L1 data Cache autoload section 0 address configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_ADDR.Reg)
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT0_SIZE: L1 data Cache autoload section 0 size configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT1_ADDR: L1 data Cache autoload section 1 address configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_ADDR.Reg)
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT1_SIZE: L1 data Cache autoload section 1 size configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT1_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT2_ADDR: L1 data Cache autoload section 2 address configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT2_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT2_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_ADDR.Reg)
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT2_SIZE: L1 data Cache autoload section 2 size configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT2_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT2_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT2_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT3_ADDR: L1 data Cache autoload section 1 address configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT3_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT3_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_ADDR.Reg)
}

// CACHE.L1_DCACHE_AUTOLOAD_SCT3_SIZE: L1 data Cache autoload section 1 size configure register
func (o *CACHE_Type) SetL1_DCACHE_AUTOLOAD_SCT3_SIZE(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_SIZE.Reg, volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_AUTOLOAD_SCT3_SIZE() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_AUTOLOAD_SCT3_SIZE.Reg) & 0xfffffff
}

// CACHE.L1_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS0_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS0_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS1_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS1_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ENA.Reg) & 0x80) >> 7
}

// CACHE.L1_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS0_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS0_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS1_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS1_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_CLR.Reg) & 0x80) >> 7
}

// CACHE.L1_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS0_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS0_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS1_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS1_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_RAW.Reg) & 0x80) >> 7
}

// CACHE.L1_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS0_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS0_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS1_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS1_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_INT_ST.Reg) & 0x80) >> 7
}

// CACHE.L1_CACHE_ACS_FAIL_CTRL: Cache Access Fail Configuration register
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE0_ACS_FAIL_CHECK_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE0_ACS_FAIL_CHECK_MODE() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE1_ACS_FAIL_CHECK_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE1_ACS_FAIL_CHECK_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE2_ACS_FAIL_CHECK_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE2_ACS_FAIL_CHECK_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE3_ACS_FAIL_CHECK_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_ICACHE3_ACS_FAIL_CHECK_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_CTRL_L1_DCACHE_ACS_FAIL_CHECK_MODE(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_CTRL_L1_DCACHE_ACS_FAIL_CHECK_MODE() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_CTRL.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ENA_L1_DCACHE_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ENA_L1_DCACHE_FAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_CLR_L1_DCACHE_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_CLR_L1_DCACHE_FAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_RAW_L1_DCACHE_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_RAW_L1_DCACHE_FAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_FAIL_INT_ST_L1_DCACHE_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_FAIL_INT_ST_L1_DCACHE_FAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_FAIL_INT_ST.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x10000) >> 16
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x20000) >> 17
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x40000) >> 18
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x80000)|value<<19)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x80000) >> 19
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x100000) >> 20
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x200000) >> 21
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x400000) >> 22
}
func (o *CACHE_Type) SetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *CACHE_Type) GetL1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_ACS_CNT_CTRL.Reg) & 0x800000) >> 23
}

// CACHE.L1_IBUS0_ACS_HIT_CNT: L1-ICache bus0 Hit-Access Counter register
func (o *CACHE_Type) SetL1_IBUS0_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS0_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS0_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS0_ACS_HIT_CNT.Reg)
}

// CACHE.L1_IBUS0_ACS_MISS_CNT: L1-ICache bus0 Miss-Access Counter register
func (o *CACHE_Type) SetL1_IBUS0_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS0_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS0_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS0_ACS_MISS_CNT.Reg)
}

// CACHE.L1_IBUS0_ACS_CONFLICT_CNT: L1-ICache bus0 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_IBUS0_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS0_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS0_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS0_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_IBUS0_ACS_NXTLVL_RD_CNT: L1-ICache bus0 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_IBUS0_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS0_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS0_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS0_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_IBUS1_ACS_HIT_CNT: L1-ICache bus1 Hit-Access Counter register
func (o *CACHE_Type) SetL1_IBUS1_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS1_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS1_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS1_ACS_HIT_CNT.Reg)
}

// CACHE.L1_IBUS1_ACS_MISS_CNT: L1-ICache bus1 Miss-Access Counter register
func (o *CACHE_Type) SetL1_IBUS1_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS1_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS1_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS1_ACS_MISS_CNT.Reg)
}

// CACHE.L1_IBUS1_ACS_CONFLICT_CNT: L1-ICache bus1 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_IBUS1_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS1_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS1_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS1_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_IBUS1_ACS_NXTLVL_RD_CNT: L1-ICache bus1 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_IBUS1_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS1_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS1_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS1_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_IBUS2_ACS_HIT_CNT: L1-ICache bus2 Hit-Access Counter register
func (o *CACHE_Type) SetL1_IBUS2_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS2_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS2_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS2_ACS_HIT_CNT.Reg)
}

// CACHE.L1_IBUS2_ACS_MISS_CNT: L1-ICache bus2 Miss-Access Counter register
func (o *CACHE_Type) SetL1_IBUS2_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS2_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS2_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS2_ACS_MISS_CNT.Reg)
}

// CACHE.L1_IBUS2_ACS_CONFLICT_CNT: L1-ICache bus2 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_IBUS2_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS2_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS2_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS2_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_IBUS2_ACS_NXTLVL_RD_CNT: L1-ICache bus2 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_IBUS2_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS2_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS2_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS2_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_IBUS3_ACS_HIT_CNT: L1-ICache bus3 Hit-Access Counter register
func (o *CACHE_Type) SetL1_IBUS3_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS3_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS3_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS3_ACS_HIT_CNT.Reg)
}

// CACHE.L1_IBUS3_ACS_MISS_CNT: L1-ICache bus3 Miss-Access Counter register
func (o *CACHE_Type) SetL1_IBUS3_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS3_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS3_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS3_ACS_MISS_CNT.Reg)
}

// CACHE.L1_IBUS3_ACS_CONFLICT_CNT: L1-ICache bus3 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_IBUS3_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS3_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS3_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS3_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_IBUS3_ACS_NXTLVL_RD_CNT: L1-ICache bus3 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_IBUS3_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_IBUS3_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_IBUS3_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_IBUS3_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_DBUS0_ACS_HIT_CNT: L1-DCache bus0 Hit-Access Counter register
func (o *CACHE_Type) SetL1_DBUS0_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS0_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS0_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS0_ACS_HIT_CNT.Reg)
}

// CACHE.L1_DBUS0_ACS_MISS_CNT: L1-DCache bus0 Miss-Access Counter register
func (o *CACHE_Type) SetL1_DBUS0_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS0_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS0_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS0_ACS_MISS_CNT.Reg)
}

// CACHE.L1_DBUS0_ACS_CONFLICT_CNT: L1-DCache bus0 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_DBUS0_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS0_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS0_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS0_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_DBUS0_ACS_NXTLVL_RD_CNT: L1-DCache bus0 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_DBUS0_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS0_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS0_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS0_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_DBUS0_ACS_NXTLVL_WR_CNT: L1-DCache bus0 WB-Access Counter register
func (o *CACHE_Type) SetL1_DBUS0_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS0_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS0_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS0_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L1_DBUS1_ACS_HIT_CNT: L1-DCache bus1 Hit-Access Counter register
func (o *CACHE_Type) SetL1_DBUS1_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS1_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS1_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS1_ACS_HIT_CNT.Reg)
}

// CACHE.L1_DBUS1_ACS_MISS_CNT: L1-DCache bus1 Miss-Access Counter register
func (o *CACHE_Type) SetL1_DBUS1_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS1_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS1_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS1_ACS_MISS_CNT.Reg)
}

// CACHE.L1_DBUS1_ACS_CONFLICT_CNT: L1-DCache bus1 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_DBUS1_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS1_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS1_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS1_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_DBUS1_ACS_NXTLVL_RD_CNT: L1-DCache bus1 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_DBUS1_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS1_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS1_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS1_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_DBUS1_ACS_NXTLVL_WR_CNT: L1-DCache bus1 WB-Access Counter register
func (o *CACHE_Type) SetL1_DBUS1_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS1_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS1_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS1_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L1_DBUS2_ACS_HIT_CNT: L1-DCache bus2 Hit-Access Counter register
func (o *CACHE_Type) SetL1_DBUS2_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS2_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS2_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS2_ACS_HIT_CNT.Reg)
}

// CACHE.L1_DBUS2_ACS_MISS_CNT: L1-DCache bus2 Miss-Access Counter register
func (o *CACHE_Type) SetL1_DBUS2_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS2_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS2_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS2_ACS_MISS_CNT.Reg)
}

// CACHE.L1_DBUS2_ACS_CONFLICT_CNT: L1-DCache bus2 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_DBUS2_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS2_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS2_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS2_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_DBUS2_ACS_NXTLVL_RD_CNT: L1-DCache bus2 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_DBUS2_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS2_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS2_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS2_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_DBUS2_ACS_NXTLVL_WR_CNT: L1-DCache bus2 WB-Access Counter register
func (o *CACHE_Type) SetL1_DBUS2_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS2_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS2_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS2_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L1_DBUS3_ACS_HIT_CNT: L1-DCache bus3 Hit-Access Counter register
func (o *CACHE_Type) SetL1_DBUS3_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS3_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS3_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS3_ACS_HIT_CNT.Reg)
}

// CACHE.L1_DBUS3_ACS_MISS_CNT: L1-DCache bus3 Miss-Access Counter register
func (o *CACHE_Type) SetL1_DBUS3_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS3_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS3_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS3_ACS_MISS_CNT.Reg)
}

// CACHE.L1_DBUS3_ACS_CONFLICT_CNT: L1-DCache bus3 Conflict-Access Counter register
func (o *CACHE_Type) SetL1_DBUS3_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS3_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS3_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS3_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L1_DBUS3_ACS_NXTLVL_RD_CNT: L1-DCache bus3 Next-Level-Access Counter register
func (o *CACHE_Type) SetL1_DBUS3_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS3_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS3_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS3_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L1_DBUS3_ACS_NXTLVL_WR_CNT: L1-DCache bus3 WB-Access Counter register
func (o *CACHE_Type) SetL1_DBUS3_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L1_DBUS3_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL1_DBUS3_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L1_DBUS3_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L1_ICACHE0_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
func (o *CACHE_Type) SetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg) & 0xffff
}
func (o *CACHE_Type) SetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16
}

// CACHE.L1_ICACHE0_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
func (o *CACHE_Type) SetL1_ICACHE0_ACS_FAIL_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE0_ACS_FAIL_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE0_ACS_FAIL_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE0_ACS_FAIL_ADDR.Reg)
}

// CACHE.L1_ICACHE1_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
func (o *CACHE_Type) SetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg) & 0xffff
}
func (o *CACHE_Type) SetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16
}

// CACHE.L1_ICACHE1_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
func (o *CACHE_Type) SetL1_ICACHE1_ACS_FAIL_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE1_ACS_FAIL_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE1_ACS_FAIL_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE1_ACS_FAIL_ADDR.Reg)
}

// CACHE.L1_ICACHE2_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
func (o *CACHE_Type) SetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg) & 0xffff
}
func (o *CACHE_Type) SetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16
}

// CACHE.L1_ICACHE2_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
func (o *CACHE_Type) SetL1_ICACHE2_ACS_FAIL_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE2_ACS_FAIL_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE2_ACS_FAIL_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE2_ACS_FAIL_ADDR.Reg)
}

// CACHE.L1_ICACHE3_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
func (o *CACHE_Type) SetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg) & 0xffff
}
func (o *CACHE_Type) SetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR() uint32 {
	return (volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16
}

// CACHE.L1_ICACHE3_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
func (o *CACHE_Type) SetL1_ICACHE3_ACS_FAIL_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_ICACHE3_ACS_FAIL_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_ICACHE3_ACS_FAIL_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_ICACHE3_ACS_FAIL_ADDR.Reg)
}

// CACHE.L1_DCACHE_ACS_FAIL_ID_ATTR: L1-DCache Access Fail ID/attribution information register
func (o *CACHE_Type) SetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ID(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ID() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff
}
func (o *CACHE_Type) SetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ATTR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CACHE_Type) GetL1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ATTR() uint32 {
	return (volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16
}

// CACHE.L1_DCACHE_ACS_FAIL_ADDR: L1-DCache Access Fail Address information register
func (o *CACHE_Type) SetL1_DCACHE_ACS_FAIL_ADDR(value uint32) {
	volatile.StoreUint32(&o.L1_DCACHE_ACS_FAIL_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_DCACHE_ACS_FAIL_ADDR() uint32 {
	return volatile.LoadUint32(&o.L1_DCACHE_ACS_FAIL_ADDR.Reg)
}

// CACHE.SYNC_L1_CACHE_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ENA.Reg) & 0x2000) >> 13
}

// CACHE.SYNC_L1_CACHE_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_CLR.Reg) & 0x2000) >> 13
}

// CACHE.SYNC_L1_CACHE_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_RAW.Reg) & 0x2000) >> 13
}

// CACHE.SYNC_L1_CACHE_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_INT_ST.Reg) & 0x2000) >> 13
}

// CACHE.SYNC_L1_CACHE_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x3)|value)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE() uint32 {
	return volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x3
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0xc)|value<<2)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0xc) >> 2
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x30)|value<<4)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x30) >> 4
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0xc0)|value<<6)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0xc0) >> 6
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_DCACHE_PLD_ERR_CODE(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x300)|value<<8)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_DCACHE_PLD_ERR_CODE() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x300) >> 8
}
func (o *CACHE_Type) SetSYNC_L1_CACHE_PRELOAD_EXCEPTION_SYNC_ERR_CODE(value uint32) {
	volatile.StoreUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg)&^(0x3000)|value<<12)
}
func (o *CACHE_Type) GetSYNC_L1_CACHE_PRELOAD_EXCEPTION_SYNC_ERR_CODE() uint32 {
	return (volatile.LoadUint32(&o.SYNC_L1_CACHE_PRELOAD_EXCEPTION.Reg) & 0x3000) >> 12
}

// CACHE.L1_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register
func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_SYNC_RST_CTRL_L1_DCACHE_SYNC_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_SYNC_RST_CTRL_L1_DCACHE_SYNC_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_SYNC_RST_CTRL.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register
func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_PRELOAD_RST_CTRL_L1_DCACHE_PLD_RST(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_PRELOAD_RST_CTRL_L1_DCACHE_PLD_RST() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_PRELOAD_RST_CTRL.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register
func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_DCACHE_ALD_BUF_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_DCACHE_ALD_BUF_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x10) >> 4
}

// CACHE.L1_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers
func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR() uint32 {
	return volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_UNALLOCATE_BUFFER_CLEAR_L1_DCACHE_UNALLOC_CLR(value uint32) {
	volatile.StoreUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_UNALLOCATE_BUFFER_CLEAR_L1_DCACHE_UNALLOC_CLR() uint32 {
	return (volatile.LoadUint32(&o.L1_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x10) >> 4
}

// CACHE.L1_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_DCACHE_TAG_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_DCACHE_TAG_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL1_CACHE_OBJECT_CTRL_L1_DCACHE_MEM_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL1_CACHE_OBJECT_CTRL_L1_DCACHE_MEM_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L1_CACHE_OBJECT_CTRL.Reg) & 0x400) >> 10
}

// CACHE.L1_CACHE_WAY_OBJECT: Cache Tag and Data memory way register
func (o *CACHE_Type) SetL1_CACHE_WAY_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_WAY_OBJECT.Reg, volatile.LoadUint32(&o.L1_CACHE_WAY_OBJECT.Reg)&^(0x7)|value)
}
func (o *CACHE_Type) GetL1_CACHE_WAY_OBJECT() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_WAY_OBJECT.Reg) & 0x7
}

// CACHE.L1_CACHE_VADDR: Cache Vaddr register
func (o *CACHE_Type) SetL1_CACHE_VADDR(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_VADDR.Reg, value)
}
func (o *CACHE_Type) GetL1_CACHE_VADDR() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_VADDR.Reg)
}

// CACHE.L1_CACHE_DEBUG_BUS: Cache Tag/data memory content register
func (o *CACHE_Type) SetL1_CACHE_DEBUG_BUS(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_DEBUG_BUS.Reg, value)
}
func (o *CACHE_Type) GetL1_CACHE_DEBUG_BUS() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_DEBUG_BUS.Reg)
}

// CACHE.LEVEL_SPLIT0: USED TO SPLIT L1 CACHE AND L2 CACHE
func (o *CACHE_Type) SetLEVEL_SPLIT0(value uint32) {
	volatile.StoreUint32(&o.LEVEL_SPLIT0.Reg, value)
}
func (o *CACHE_Type) GetLEVEL_SPLIT0() uint32 {
	return volatile.LoadUint32(&o.LEVEL_SPLIT0.Reg)
}

// CACHE.L2_CACHE_CTRL: L2 Cache(L2-Cache) control register
func (o *CACHE_Type) SetL2_CACHE_CTRL_L2_CACHE_SHUT_DMA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL2_CACHE_CTRL_L2_CACHE_SHUT_DMA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL2_CACHE_CTRL_L2_CACHE_UNDEF_OP(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_CTRL_L2_CACHE_UNDEF_OP() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CTRL.Reg) & 0xff00) >> 8
}

// CACHE.L2_BYPASS_CACHE_CONF: Bypass Cache configure register
func (o *CACHE_Type) SetL2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN(value uint32) {
	volatile.StoreUint32(&o.L2_BYPASS_CACHE_CONF.Reg, volatile.LoadUint32(&o.L2_BYPASS_CACHE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_BYPASS_CACHE_CONF.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_CACHESIZE_CONF: L2 Cache CacheSize mode configure register
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x40)|value<<6)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x40) >> 6
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x80)|value<<7)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x80) >> 7
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_CACHESIZE_CONF.Reg) & 0x1000) >> 12
}

// CACHE.L2_CACHE_BLOCKSIZE_CONF: L2 Cache BlockSize mode configure register
func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x8) >> 3
}
func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x10) >> 4
}
func (o *CACHE_Type) SetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_BLOCKSIZE_CONF.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register
func (o *CACHE_Type) SetL2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_WRAP_AROUND_CTRL.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register
func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x100000) >> 20
}
func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x200000) >> 21
}
func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_POWER_CTRL.Reg) & 0x400000) >> 22
}

// CACHE.L2_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register
func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x100000) >> 20
}
func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x200000) >> 21
}
func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_POWER_CTRL.Reg) & 0x400000) >> 22
}

// CACHE.L2_CACHE_FREEZE_CTRL: Cache Freeze control register
func (o *CACHE_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *CACHE_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x100000) >> 20
}
func (o *CACHE_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *CACHE_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x200000) >> 21
}
func (o *CACHE_Type) SetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_FREEZE_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *CACHE_Type) GetL2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_FREEZE_CTRL.Reg) & 0x400000) >> 22
}

// CACHE.L2_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register
func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x100000) >> 20
}
func (o *CACHE_Type) SetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *CACHE_Type) GetL2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_DATA_MEM_ACS_CONF.Reg) & 0x200000) >> 21
}

// CACHE.L2_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register
func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x100000) >> 20
}
func (o *CACHE_Type) SetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *CACHE_Type) GetL2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_TAG_MEM_ACS_CONF.Reg) & 0x200000) >> 21
}

// CACHE.L2_CACHE_PRELOCK_CONF: L2 Cache prelock configure register
func (o *CACHE_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x1
}
func (o *CACHE_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOCK_CONF.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg)&^(0x3c)|value<<2)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_CONF.Reg) & 0x3c) >> 2
}

// CACHE.L2_CACHE_PRELOCK_SCT0_ADDR: L2 Cache prelock section0 address configure register
func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT0_ADDR.Reg)
}

// CACHE.L2_CACHE_PRELOCK_SCT1_ADDR: L2 Cache prelock section1 address configure register
func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT1_ADDR.Reg)
}

// CACHE.L2_CACHE_PRELOCK_SCT_SIZE: L2 Cache prelock section size configure register
func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff
}
func (o *CACHE_Type) SetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg)&^(0xffff0000)|value<<16)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_PRELOCK_SCT_SIZE.Reg) & 0xffff0000) >> 16
}

// CACHE.L2_CACHE_PRELOAD_CTRL: L2 Cache preload-operation control register
func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg)&^(0x78)|value<<3)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_CTRL.Reg) & 0x78) >> 3
}

// CACHE.L2_CACHE_PRELOAD_ADDR: L2 Cache preload address configure register
func (o *CACHE_Type) SetL2_CACHE_PRELOAD_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOAD_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOAD_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_ADDR.Reg)
}

// CACHE.L2_CACHE_PRELOAD_SIZE: L2 Cache preload size configure register
func (o *CACHE_Type) SetL2_CACHE_PRELOAD_SIZE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOAD_SIZE() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PRELOAD_SIZE.Reg) & 0xffff
}

// CACHE.L2_CACHE_AUTOLOAD_CTRL: L2 Cache autoload-operation control register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x18)|value<<3)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x18) >> 3
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg)&^(0xf000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_CTRL.Reg) & 0xf000) >> 12
}

// CACHE.L2_CACHE_AUTOLOAD_SCT0_ADDR: L2 Cache autoload section 0 address configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT0_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT0_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT0_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_ADDR.Reg)
}

// CACHE.L2_CACHE_AUTOLOAD_SCT0_SIZE: L2 Cache autoload section 0 size configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT0_SIZE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT0_SIZE() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT0_SIZE.Reg) & 0xfffffff
}

// CACHE.L2_CACHE_AUTOLOAD_SCT1_ADDR: L2 Cache autoload section 1 address configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT1_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT1_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT1_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_ADDR.Reg)
}

// CACHE.L2_CACHE_AUTOLOAD_SCT1_SIZE: L2 Cache autoload section 1 size configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT1_SIZE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT1_SIZE() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT1_SIZE.Reg) & 0xfffffff
}

// CACHE.L2_CACHE_AUTOLOAD_SCT2_ADDR: L2 Cache autoload section 2 address configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT2_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT2_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT2_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_ADDR.Reg)
}

// CACHE.L2_CACHE_AUTOLOAD_SCT2_SIZE: L2 Cache autoload section 2 size configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT2_SIZE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT2_SIZE() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT2_SIZE.Reg) & 0xfffffff
}

// CACHE.L2_CACHE_AUTOLOAD_SCT3_ADDR: L2 Cache autoload section 3 address configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT3_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT3_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT3_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_ADDR.Reg)
}

// CACHE.L2_CACHE_AUTOLOAD_SCT3_SIZE: L2 Cache autoload section 3 size configure register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_SCT3_SIZE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_SCT3_SIZE() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_SCT3_SIZE.Reg) & 0xfffffff
}

// CACHE.L2_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ENA.Reg) & 0x8000) >> 15
}

// CACHE.L2_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_CLR.Reg) & 0x8000) >> 15
}

// CACHE.L2_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_RAW.Reg) & 0x8000) >> 15
}

// CACHE.L2_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_INT_ST.Reg) & 0x8000) >> 15
}

// CACHE.L2_CACHE_ACS_FAIL_CTRL: Cache Access Fail Configuration register
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_CTRL_L2_CACHE_ACS_FAIL_CHECK_MODE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_CTRL_L2_CACHE_ACS_FAIL_CHECK_MODE() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_CTRL.Reg) & 0x1
}

// CACHE.L2_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ENA.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_CLR.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_RAW.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_INT_ST.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x100) >> 8
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x200) >> 9
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x400) >> 10
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x800) >> 11
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x1000) >> 12
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x2000) >> 13
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x4000) >> 14
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x8000) >> 15
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x1000000) >> 24
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x2000000) >> 25
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x4000000)|value<<26)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x4000000) >> 26
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x8000000)|value<<27)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x8000000) >> 27
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x10000000) >> 28
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x20000000) >> 29
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x40000000) >> 30
}
func (o *CACHE_Type) SetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_CNT_CTRL.Reg) & 0x80000000) >> 31
}

// CACHE.L2_IBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register
func (o *CACHE_Type) SetL2_IBUS0_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS0_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS0_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS0_ACS_HIT_CNT.Reg)
}

// CACHE.L2_IBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register
func (o *CACHE_Type) SetL2_IBUS0_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS0_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS0_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS0_ACS_MISS_CNT.Reg)
}

// CACHE.L2_IBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_IBUS0_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS0_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS0_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS0_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_IBUS0_ACS_NXTLVL_RD_CNT: L2-Cache bus0 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_IBUS0_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS0_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS0_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS0_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_IBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register
func (o *CACHE_Type) SetL2_IBUS1_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS1_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS1_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS1_ACS_HIT_CNT.Reg)
}

// CACHE.L2_IBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register
func (o *CACHE_Type) SetL2_IBUS1_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS1_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS1_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS1_ACS_MISS_CNT.Reg)
}

// CACHE.L2_IBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_IBUS1_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS1_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS1_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS1_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_IBUS1_ACS_NXTLVL_RD_CNT: L2-Cache bus1 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_IBUS1_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS1_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS1_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS1_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_IBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register
func (o *CACHE_Type) SetL2_IBUS2_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS2_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS2_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS2_ACS_HIT_CNT.Reg)
}

// CACHE.L2_IBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register
func (o *CACHE_Type) SetL2_IBUS2_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS2_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS2_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS2_ACS_MISS_CNT.Reg)
}

// CACHE.L2_IBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_IBUS2_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS2_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS2_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS2_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_IBUS2_ACS_NXTLVL_RD_CNT: L2-Cache bus2 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_IBUS2_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS2_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS2_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS2_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_IBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register
func (o *CACHE_Type) SetL2_IBUS3_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS3_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS3_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS3_ACS_HIT_CNT.Reg)
}

// CACHE.L2_IBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register
func (o *CACHE_Type) SetL2_IBUS3_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS3_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS3_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS3_ACS_MISS_CNT.Reg)
}

// CACHE.L2_IBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_IBUS3_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS3_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS3_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS3_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_IBUS3_ACS_NXTLVL_RD_CNT: L2-Cache bus3 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_IBUS3_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_IBUS3_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_IBUS3_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_IBUS3_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_DBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register
func (o *CACHE_Type) SetL2_DBUS0_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS0_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS0_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS0_ACS_HIT_CNT.Reg)
}

// CACHE.L2_DBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register
func (o *CACHE_Type) SetL2_DBUS0_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS0_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS0_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS0_ACS_MISS_CNT.Reg)
}

// CACHE.L2_DBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_DBUS0_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS0_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS0_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS0_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_DBUS0_ACS_NXTLVL_RD_CNT: L2-Cache bus0 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_DBUS0_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS0_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS0_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS0_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_DBUS0_ACS_NXTLVL_WR_CNT: L2-Cache bus0 WB-Access Counter register
func (o *CACHE_Type) SetL2_DBUS0_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS0_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS0_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS0_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L2_DBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register
func (o *CACHE_Type) SetL2_DBUS1_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS1_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS1_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS1_ACS_HIT_CNT.Reg)
}

// CACHE.L2_DBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register
func (o *CACHE_Type) SetL2_DBUS1_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS1_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS1_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS1_ACS_MISS_CNT.Reg)
}

// CACHE.L2_DBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_DBUS1_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS1_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS1_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS1_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_DBUS1_ACS_NXTLVL_RD_CNT: L2-Cache bus1 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_DBUS1_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS1_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS1_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS1_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_DBUS1_ACS_NXTLVL_WR_CNT: L2-Cache bus1 WB-Access Counter register
func (o *CACHE_Type) SetL2_DBUS1_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS1_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS1_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS1_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L2_DBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register
func (o *CACHE_Type) SetL2_DBUS2_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS2_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS2_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS2_ACS_HIT_CNT.Reg)
}

// CACHE.L2_DBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register
func (o *CACHE_Type) SetL2_DBUS2_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS2_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS2_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS2_ACS_MISS_CNT.Reg)
}

// CACHE.L2_DBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_DBUS2_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS2_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS2_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS2_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_DBUS2_ACS_NXTLVL_RD_CNT: L2-Cache bus2 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_DBUS2_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS2_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS2_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS2_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_DBUS2_ACS_NXTLVL_WR_CNT: L2-Cache bus2 WB-Access Counter register
func (o *CACHE_Type) SetL2_DBUS2_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS2_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS2_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS2_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L2_DBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register
func (o *CACHE_Type) SetL2_DBUS3_ACS_HIT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS3_ACS_HIT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS3_ACS_HIT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS3_ACS_HIT_CNT.Reg)
}

// CACHE.L2_DBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register
func (o *CACHE_Type) SetL2_DBUS3_ACS_MISS_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS3_ACS_MISS_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS3_ACS_MISS_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS3_ACS_MISS_CNT.Reg)
}

// CACHE.L2_DBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register
func (o *CACHE_Type) SetL2_DBUS3_ACS_CONFLICT_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS3_ACS_CONFLICT_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS3_ACS_CONFLICT_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS3_ACS_CONFLICT_CNT.Reg)
}

// CACHE.L2_DBUS3_ACS_NXTLVL_RD_CNT: L2-Cache bus3 Next-Level-Access Counter register
func (o *CACHE_Type) SetL2_DBUS3_ACS_NXTLVL_RD_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS3_ACS_NXTLVL_RD_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS3_ACS_NXTLVL_RD_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS3_ACS_NXTLVL_RD_CNT.Reg)
}

// CACHE.L2_DBUS3_ACS_NXTLVL_WR_CNT: L2-Cache bus3 WB-Access Counter register
func (o *CACHE_Type) SetL2_DBUS3_ACS_NXTLVL_WR_CNT(value uint32) {
	volatile.StoreUint32(&o.L2_DBUS3_ACS_NXTLVL_WR_CNT.Reg, value)
}
func (o *CACHE_Type) GetL2_DBUS3_ACS_NXTLVL_WR_CNT() uint32 {
	return volatile.LoadUint32(&o.L2_DBUS3_ACS_NXTLVL_WR_CNT.Reg)
}

// CACHE.L2_CACHE_ACS_FAIL_ID_ATTR: L2-Cache Access Fail ID/attribution information register
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff)|value)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff
}
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg, volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ID_ATTR.Reg) & 0xffff0000) >> 16
}

// CACHE.L2_CACHE_ACS_FAIL_ADDR: L2-Cache Access Fail Address information register
func (o *CACHE_Type) SetL2_CACHE_ACS_FAIL_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACS_FAIL_ADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_ACS_FAIL_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_ACS_FAIL_ADDR.Reg)
}

// CACHE.L2_CACHE_SYNC_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ENA.Reg) & 0x1000) >> 12
}

// CACHE.L2_CACHE_SYNC_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_CLR.Reg) & 0x1000) >> 12
}

// CACHE.L2_CACHE_SYNC_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_RAW.Reg) & 0x1000) >> 12
}

// CACHE.L2_CACHE_SYNC_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_INT_ST.Reg) & 0x1000) >> 12
}

// CACHE.L2_CACHE_SYNC_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register
func (o *CACHE_Type) SetL2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg)&^(0xc00)|value<<10)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_PRELOAD_EXCEPTION.Reg) & 0xc00) >> 10
}

// CACHE.L2_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register
func (o *CACHE_Type) SetL2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_SYNC_RST_CTRL.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register
func (o *CACHE_Type) SetL2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_PRELOAD_RST_CTRL.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register
func (o *CACHE_Type) SetL2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_AUTOLOAD_BUF_CLR_CTRL.Reg) & 0x20) >> 5
}

// CACHE.L2_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers
func (o *CACHE_Type) SetL2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg, volatile.LoadUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_UNALLOCATE_BUFFER_CLEAR.Reg) & 0x20) >> 5
}

// CACHE.L2_CACHE_ACCESS_ATTR_CTRL: L2 cache access attribute control register
func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x1
}
func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x2) >> 1
}
func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x4) >> 2
}
func (o *CACHE_Type) SetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *CACHE_Type) GetL2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_ACCESS_ATTR_CTRL.Reg) & 0x8) >> 3
}

// CACHE.L2_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register
func (o *CACHE_Type) SetL2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *CACHE_Type) GetL2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg) & 0x20) >> 5
}
func (o *CACHE_Type) SetL2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_OBJECT_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *CACHE_Type) GetL2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT() uint32 {
	return (volatile.LoadUint32(&o.L2_CACHE_OBJECT_CTRL.Reg) & 0x800) >> 11
}

// CACHE.L2_CACHE_WAY_OBJECT: Cache Tag and Data memory way register
func (o *CACHE_Type) SetL2_CACHE_WAY_OBJECT(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_WAY_OBJECT.Reg, volatile.LoadUint32(&o.L2_CACHE_WAY_OBJECT.Reg)&^(0x7)|value)
}
func (o *CACHE_Type) GetL2_CACHE_WAY_OBJECT() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_WAY_OBJECT.Reg) & 0x7
}

// CACHE.L2_CACHE_VADDR: Cache Vaddr register
func (o *CACHE_Type) SetL2_CACHE_VADDR(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_VADDR.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_VADDR() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_VADDR.Reg)
}

// CACHE.L2_CACHE_DEBUG_BUS: Cache Tag/data memory content register
func (o *CACHE_Type) SetL2_CACHE_DEBUG_BUS(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_DEBUG_BUS.Reg, value)
}
func (o *CACHE_Type) GetL2_CACHE_DEBUG_BUS() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_DEBUG_BUS.Reg)
}

// CACHE.LEVEL_SPLIT1: USED TO SPLIT L1 CACHE AND L2 CACHE
func (o *CACHE_Type) SetLEVEL_SPLIT1(value uint32) {
	volatile.StoreUint32(&o.LEVEL_SPLIT1.Reg, value)
}
func (o *CACHE_Type) GetLEVEL_SPLIT1() uint32 {
	return volatile.LoadUint32(&o.LEVEL_SPLIT1.Reg)
}

// CACHE.CLOCK_GATE: Clock gate control register
func (o *CACHE_Type) SetCLOCK_GATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetCLOCK_GATE_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1
}

// CACHE.REDUNDANCY_SIG0: Cache redundancy signal 0 register
func (o *CACHE_Type) SetREDUNDANCY_SIG0(value uint32) {
	volatile.StoreUint32(&o.REDUNDANCY_SIG0.Reg, value)
}
func (o *CACHE_Type) GetREDUNDANCY_SIG0() uint32 {
	return volatile.LoadUint32(&o.REDUNDANCY_SIG0.Reg)
}

// CACHE.REDUNDANCY_SIG1: Cache redundancy signal 1 register
func (o *CACHE_Type) SetREDUNDANCY_SIG1(value uint32) {
	volatile.StoreUint32(&o.REDUNDANCY_SIG1.Reg, value)
}
func (o *CACHE_Type) GetREDUNDANCY_SIG1() uint32 {
	return volatile.LoadUint32(&o.REDUNDANCY_SIG1.Reg)
}

// CACHE.REDUNDANCY_SIG2: Cache redundancy signal 2 register
func (o *CACHE_Type) SetREDUNDANCY_SIG2(value uint32) {
	volatile.StoreUint32(&o.REDUNDANCY_SIG2.Reg, value)
}
func (o *CACHE_Type) GetREDUNDANCY_SIG2() uint32 {
	return volatile.LoadUint32(&o.REDUNDANCY_SIG2.Reg)
}

// CACHE.REDUNDANCY_SIG3: Cache redundancy signal 3 register
func (o *CACHE_Type) SetREDUNDANCY_SIG3(value uint32) {
	volatile.StoreUint32(&o.REDUNDANCY_SIG3.Reg, value)
}
func (o *CACHE_Type) GetREDUNDANCY_SIG3() uint32 {
	return volatile.LoadUint32(&o.REDUNDANCY_SIG3.Reg)
}

// CACHE.REDUNDANCY_SIG4: Cache redundancy signal 0 register
func (o *CACHE_Type) SetREDUNDANCY_SIG4_REDCY_SIG4(value uint32) {
	volatile.StoreUint32(&o.REDUNDANCY_SIG4.Reg, volatile.LoadUint32(&o.REDUNDANCY_SIG4.Reg)&^(0xf)|value)
}
func (o *CACHE_Type) GetREDUNDANCY_SIG4_REDCY_SIG4() uint32 {
	return volatile.LoadUint32(&o.REDUNDANCY_SIG4.Reg) & 0xf
}

// CACHE.DATE: Version control register
func (o *CACHE_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *CACHE_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// Interrupt Controller (Core 0)
type CORE0_Type struct {
	LP_RTC_INT_MAP                  volatile.Register32 // 0x0
	LP_WDT_INT_MAP                  volatile.Register32 // 0x4
	LP_TIMER_REG_0_INT_MAP          volatile.Register32 // 0x8
	LP_TIMER_REG_1_INT_MAP          volatile.Register32 // 0xC
	MB_HP_INT_MAP                   volatile.Register32 // 0x10
	MB_LP_INT_MAP                   volatile.Register32 // 0x14
	PMU_REG_0_INT_MAP               volatile.Register32 // 0x18
	PMU_REG_1_INT_MAP               volatile.Register32 // 0x1C
	LP_ANAPERI_INT_MAP              volatile.Register32 // 0x20
	LP_ADC_INT_MAP                  volatile.Register32 // 0x24
	LP_GPIO_INT_MAP                 volatile.Register32 // 0x28
	LP_I2C_INT_MAP                  volatile.Register32 // 0x2C
	LP_I2S_INT_MAP                  volatile.Register32 // 0x30
	LP_SPI_INT_MAP                  volatile.Register32 // 0x34
	LP_TOUCH_INT_MAP                volatile.Register32 // 0x38
	LP_TSENS_INT_MAP                volatile.Register32 // 0x3C
	LP_UART_INT_MAP                 volatile.Register32 // 0x40
	LP_EFUSE_INT_MAP                volatile.Register32 // 0x44
	LP_SW_INT_MAP                   volatile.Register32 // 0x48
	LP_SYSREG_INT_MAP               volatile.Register32 // 0x4C
	LP_HUK_INT_MAP                  volatile.Register32 // 0x50
	SYS_ICM_INT_MAP                 volatile.Register32 // 0x54
	USB_DEVICE_INT_MAP              volatile.Register32 // 0x58
	SDIO_HOST_INT_MAP               volatile.Register32 // 0x5C
	GDMA_INT_MAP                    volatile.Register32 // 0x60
	SPI2_INT_MAP                    volatile.Register32 // 0x64
	SPI3_INT_MAP                    volatile.Register32 // 0x68
	I2S0_INT_MAP                    volatile.Register32 // 0x6C
	I2S1_INT_MAP                    volatile.Register32 // 0x70
	I2S2_INT_MAP                    volatile.Register32 // 0x74
	UHCI0_INT_MAP                   volatile.Register32 // 0x78
	UART0_INT_MAP                   volatile.Register32 // 0x7C
	UART1_INT_MAP                   volatile.Register32 // 0x80
	UART2_INT_MAP                   volatile.Register32 // 0x84
	UART3_INT_MAP                   volatile.Register32 // 0x88
	UART4_INT_MAP                   volatile.Register32 // 0x8C
	LCD_CAM_INT_MAP                 volatile.Register32 // 0x90
	ADC_INT_MAP                     volatile.Register32 // 0x94
	PWM0_INT_MAP                    volatile.Register32 // 0x98
	PWM1_INT_MAP                    volatile.Register32 // 0x9C
	CAN0_INT_MAP                    volatile.Register32 // 0xA0
	CAN1_INT_MAP                    volatile.Register32 // 0xA4
	CAN2_INT_MAP                    volatile.Register32 // 0xA8
	RMT_INT_MAP                     volatile.Register32 // 0xAC
	I2C0_INT_MAP                    volatile.Register32 // 0xB0
	I2C1_INT_MAP                    volatile.Register32 // 0xB4
	TIMERGRP0_T0_INT_MAP            volatile.Register32 // 0xB8
	TIMERGRP0_T1_INT_MAP            volatile.Register32 // 0xBC
	TIMERGRP0_WDT_INT_MAP           volatile.Register32 // 0xC0
	TIMERGRP1_T0_INT_MAP            volatile.Register32 // 0xC4
	TIMERGRP1_T1_INT_MAP            volatile.Register32 // 0xC8
	TIMERGRP1_WDT_INT_MAP           volatile.Register32 // 0xCC
	LEDC_INT_MAP                    volatile.Register32 // 0xD0
	SYSTIMER_TARGET0_INT_MAP        volatile.Register32 // 0xD4
	SYSTIMER_TARGET1_INT_MAP        volatile.Register32 // 0xD8
	SYSTIMER_TARGET2_INT_MAP        volatile.Register32 // 0xDC
	AHB_PDMA_IN_CH0_INT_MAP         volatile.Register32 // 0xE0
	AHB_PDMA_IN_CH1_INT_MAP         volatile.Register32 // 0xE4
	AHB_PDMA_IN_CH2_INT_MAP         volatile.Register32 // 0xE8
	AHB_PDMA_OUT_CH0_INT_MAP        volatile.Register32 // 0xEC
	AHB_PDMA_OUT_CH1_INT_MAP        volatile.Register32 // 0xF0
	AHB_PDMA_OUT_CH2_INT_MAP        volatile.Register32 // 0xF4
	AXI_PDMA_IN_CH0_INT_MAP         volatile.Register32 // 0xF8
	AXI_PDMA_IN_CH1_INT_MAP         volatile.Register32 // 0xFC
	AXI_PDMA_IN_CH2_INT_MAP         volatile.Register32 // 0x100
	AXI_PDMA_OUT_CH0_INT_MAP        volatile.Register32 // 0x104
	AXI_PDMA_OUT_CH1_INT_MAP        volatile.Register32 // 0x108
	AXI_PDMA_OUT_CH2_INT_MAP        volatile.Register32 // 0x10C
	RSA_INT_MAP                     volatile.Register32 // 0x110
	AES_INT_MAP                     volatile.Register32 // 0x114
	SHA_INT_MAP                     volatile.Register32 // 0x118
	ECC_INT_MAP                     volatile.Register32 // 0x11C
	ECDSA_INT_MAP                   volatile.Register32 // 0x120
	KM_INT_MAP                      volatile.Register32 // 0x124
	GPIO_INT0_MAP                   volatile.Register32 // 0x128
	GPIO_INT1_MAP                   volatile.Register32 // 0x12C
	GPIO_INT2_MAP                   volatile.Register32 // 0x130
	GPIO_INT3_MAP                   volatile.Register32 // 0x134
	GPIO_PAD_COMP_INT_MAP           volatile.Register32 // 0x138
	CPU_INT_FROM_CPU_0_MAP          volatile.Register32 // 0x13C
	CPU_INT_FROM_CPU_1_MAP          volatile.Register32 // 0x140
	CPU_INT_FROM_CPU_2_MAP          volatile.Register32 // 0x144
	CPU_INT_FROM_CPU_3_MAP          volatile.Register32 // 0x148
	CACHE_INT_MAP                   volatile.Register32 // 0x14C
	FLASH_MSPI_INT_MAP              volatile.Register32 // 0x150
	CSI_BRIDGE_INT_MAP              volatile.Register32 // 0x154
	DSI_BRIDGE_INT_MAP              volatile.Register32 // 0x158
	CSI_INT_MAP                     volatile.Register32 // 0x15C
	DSI_INT_MAP                     volatile.Register32 // 0x160
	GMII_PHY_INT_MAP                volatile.Register32 // 0x164
	LPI_INT_MAP                     volatile.Register32 // 0x168
	PMT_INT_MAP                     volatile.Register32 // 0x16C
	SBD_INT_MAP                     volatile.Register32 // 0x170
	USB_OTG_INT_MAP                 volatile.Register32 // 0x174
	USB_OTG_ENDP_MULTI_PROC_INT_MAP volatile.Register32 // 0x178
	JPEG_INT_MAP                    volatile.Register32 // 0x17C
	PPA_INT_MAP                     volatile.Register32 // 0x180
	CORE0_TRACE_INT_MAP             volatile.Register32 // 0x184
	CORE1_TRACE_INT_MAP             volatile.Register32 // 0x188
	HP_CORE_CTRL_INT_MAP            volatile.Register32 // 0x18C
	ISP_INT_MAP                     volatile.Register32 // 0x190
	I3C_MST_INT_MAP                 volatile.Register32 // 0x194
	I3C_SLV_INT_MAP                 volatile.Register32 // 0x198
	USB_OTG11_INT_MAP               volatile.Register32 // 0x19C
	DMA2D_IN_CH0_INT_MAP            volatile.Register32 // 0x1A0
	DMA2D_IN_CH1_INT_MAP            volatile.Register32 // 0x1A4
	DMA2D_OUT_CH0_INT_MAP           volatile.Register32 // 0x1A8
	DMA2D_OUT_CH1_INT_MAP           volatile.Register32 // 0x1AC
	DMA2D_OUT_CH2_INT_MAP           volatile.Register32 // 0x1B0
	PSRAM_MSPI_INT_MAP              volatile.Register32 // 0x1B4
	HP_SYSREG_INT_MAP               volatile.Register32 // 0x1B8
	PCNT_INT_MAP                    volatile.Register32 // 0x1BC
	HP_PAU_INT_MAP                  volatile.Register32 // 0x1C0
	HP_PARLIO_RX_INT_MAP            volatile.Register32 // 0x1C4
	HP_PARLIO_TX_INT_MAP            volatile.Register32 // 0x1C8
	H264_DMA2D_OUT_CH0_INT_MAP      volatile.Register32 // 0x1CC
	H264_DMA2D_OUT_CH1_INT_MAP      volatile.Register32 // 0x1D0
	H264_DMA2D_OUT_CH2_INT_MAP      volatile.Register32 // 0x1D4
	H264_DMA2D_OUT_CH3_INT_MAP      volatile.Register32 // 0x1D8
	H264_DMA2D_OUT_CH4_INT_MAP      volatile.Register32 // 0x1DC
	H264_DMA2D_IN_CH0_INT_MAP       volatile.Register32 // 0x1E0
	H264_DMA2D_IN_CH1_INT_MAP       volatile.Register32 // 0x1E4
	H264_DMA2D_IN_CH2_INT_MAP       volatile.Register32 // 0x1E8
	H264_DMA2D_IN_CH3_INT_MAP       volatile.Register32 // 0x1EC
	H264_DMA2D_IN_CH4_INT_MAP       volatile.Register32 // 0x1F0
	H264_DMA2D_IN_CH5_INT_MAP       volatile.Register32 // 0x1F4
	H264_REG_INT_MAP                volatile.Register32 // 0x1F8
	ASSIST_DEBUG_INT_MAP            volatile.Register32 // 0x1FC
	INTR_STATUS_REG_0               volatile.Register32 // 0x200
	INTR_STATUS_REG_1               volatile.Register32 // 0x204
	INTR_STATUS_REG_2               volatile.Register32 // 0x208
	INTR_STATUS_REG_3               volatile.Register32 // 0x20C
	CLOCK_GATE                      volatile.Register32 // 0x210
	_                               [488]byte
	INTERRUPT_REG_DATE              volatile.Register32 // 0x3FC
}

// CORE0.LP_RTC_INT_MAP: NA
func (o *CORE0_Type) SetLP_RTC_INT_MAP_CORE0_LP_RTC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_RTC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_RTC_INT_MAP_CORE0_LP_RTC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_WDT_INT_MAP: NA
func (o *CORE0_Type) SetLP_WDT_INT_MAP_CORE0_LP_WDT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_WDT_INT_MAP_CORE0_LP_WDT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_TIMER_REG_0_INT_MAP: NA
func (o *CORE0_Type) SetLP_TIMER_REG_0_INT_MAP_CORE0_LP_TIMER_REG_0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_TIMER_REG_0_INT_MAP_CORE0_LP_TIMER_REG_0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_TIMER_REG_1_INT_MAP: NA
func (o *CORE0_Type) SetLP_TIMER_REG_1_INT_MAP_CORE0_LP_TIMER_REG_1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_TIMER_REG_1_INT_MAP_CORE0_LP_TIMER_REG_1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg) & 0x3f
}

// CORE0.MB_HP_INT_MAP: NA
func (o *CORE0_Type) SetMB_HP_INT_MAP_CORE0_MB_HP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.MB_HP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetMB_HP_INT_MAP_CORE0_MB_HP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg) & 0x3f
}

// CORE0.MB_LP_INT_MAP: NA
func (o *CORE0_Type) SetMB_LP_INT_MAP_CORE0_MB_LP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.MB_LP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetMB_LP_INT_MAP_CORE0_MB_LP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg) & 0x3f
}

// CORE0.PMU_REG_0_INT_MAP: NA
func (o *CORE0_Type) SetPMU_REG_0_INT_MAP_CORE0_PMU_REG_0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PMU_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPMU_REG_0_INT_MAP_CORE0_PMU_REG_0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg) & 0x3f
}

// CORE0.PMU_REG_1_INT_MAP: NA
func (o *CORE0_Type) SetPMU_REG_1_INT_MAP_CORE0_PMU_REG_1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PMU_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPMU_REG_1_INT_MAP_CORE0_PMU_REG_1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_ANAPERI_INT_MAP: NA
func (o *CORE0_Type) SetLP_ANAPERI_INT_MAP_CORE0_LP_ANAPERI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_ANAPERI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_ANAPERI_INT_MAP_CORE0_LP_ANAPERI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_ADC_INT_MAP: NA
func (o *CORE0_Type) SetLP_ADC_INT_MAP_CORE0_LP_ADC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_ADC_INT_MAP_CORE0_LP_ADC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_GPIO_INT_MAP: NA
func (o *CORE0_Type) SetLP_GPIO_INT_MAP_CORE0_LP_GPIO_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_GPIO_INT_MAP.Reg, volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_GPIO_INT_MAP_CORE0_LP_GPIO_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_I2C_INT_MAP: NA
func (o *CORE0_Type) SetLP_I2C_INT_MAP_CORE0_LP_I2C_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_I2C_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_I2C_INT_MAP_CORE0_LP_I2C_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_I2S_INT_MAP: NA
func (o *CORE0_Type) SetLP_I2S_INT_MAP_CORE0_LP_I2S_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_I2S_INT_MAP_CORE0_LP_I2S_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_SPI_INT_MAP: NA
func (o *CORE0_Type) SetLP_SPI_INT_MAP_CORE0_LP_SPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_SPI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_SPI_INT_MAP_CORE0_LP_SPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_TOUCH_INT_MAP: NA
func (o *CORE0_Type) SetLP_TOUCH_INT_MAP_CORE0_LP_TOUCH_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TOUCH_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_TOUCH_INT_MAP_CORE0_LP_TOUCH_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_TSENS_INT_MAP: NA
func (o *CORE0_Type) SetLP_TSENS_INT_MAP_CORE0_LP_TSENS_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TSENS_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_TSENS_INT_MAP_CORE0_LP_TSENS_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_UART_INT_MAP: NA
func (o *CORE0_Type) SetLP_UART_INT_MAP_CORE0_LP_UART_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_UART_INT_MAP.Reg, volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_UART_INT_MAP_CORE0_LP_UART_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_EFUSE_INT_MAP: NA
func (o *CORE0_Type) SetLP_EFUSE_INT_MAP_CORE0_LP_EFUSE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_EFUSE_INT_MAP_CORE0_LP_EFUSE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_SW_INT_MAP: NA
func (o *CORE0_Type) SetLP_SW_INT_MAP_CORE0_LP_SW_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_SW_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_SW_INT_MAP_CORE0_LP_SW_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_SYSREG_INT_MAP: NA
func (o *CORE0_Type) SetLP_SYSREG_INT_MAP_CORE0_LP_SYSREG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_SYSREG_INT_MAP_CORE0_LP_SYSREG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg) & 0x3f
}

// CORE0.LP_HUK_INT_MAP: NA
func (o *CORE0_Type) SetLP_HUK_INT_MAP_CORE0_LP_HUK_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_HUK_INT_MAP.Reg, volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLP_HUK_INT_MAP_CORE0_LP_HUK_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg) & 0x3f
}

// CORE0.SYS_ICM_INT_MAP: NA
func (o *CORE0_Type) SetSYS_ICM_INT_MAP_CORE0_SYS_ICM_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYS_ICM_INT_MAP.Reg, volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSYS_ICM_INT_MAP_CORE0_SYS_ICM_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg) & 0x3f
}

// CORE0.USB_DEVICE_INT_MAP: NA
func (o *CORE0_Type) SetUSB_DEVICE_INT_MAP_CORE0_USB_DEVICE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_DEVICE_INT_MAP.Reg, volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUSB_DEVICE_INT_MAP_CORE0_USB_DEVICE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg) & 0x3f
}

// CORE0.SDIO_HOST_INT_MAP: NA
func (o *CORE0_Type) SetSDIO_HOST_INT_MAP_CORE0_SDIO_HOST_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SDIO_HOST_INT_MAP.Reg, volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSDIO_HOST_INT_MAP_CORE0_SDIO_HOST_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg) & 0x3f
}

// CORE0.GDMA_INT_MAP: NA
func (o *CORE0_Type) SetGDMA_INT_MAP_CORE0_GDMA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.GDMA_INT_MAP.Reg, volatile.LoadUint32(&o.GDMA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetGDMA_INT_MAP_CORE0_GDMA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.GDMA_INT_MAP.Reg) & 0x3f
}

// CORE0.SPI2_INT_MAP: NA
func (o *CORE0_Type) SetSPI2_INT_MAP_CORE0_SPI2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SPI2_INT_MAP.Reg, volatile.LoadUint32(&o.SPI2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSPI2_INT_MAP_CORE0_SPI2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SPI2_INT_MAP.Reg) & 0x3f
}

// CORE0.SPI3_INT_MAP: NA
func (o *CORE0_Type) SetSPI3_INT_MAP_CORE0_SPI3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SPI3_INT_MAP.Reg, volatile.LoadUint32(&o.SPI3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSPI3_INT_MAP_CORE0_SPI3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SPI3_INT_MAP.Reg) & 0x3f
}

// CORE0.I2S0_INT_MAP: NA
func (o *CORE0_Type) SetI2S0_INT_MAP_CORE0_I2S0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.I2S0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetI2S0_INT_MAP_CORE0_I2S0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2S0_INT_MAP.Reg) & 0x3f
}

// CORE0.I2S1_INT_MAP: NA
func (o *CORE0_Type) SetI2S1_INT_MAP_CORE0_I2S1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.I2S1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetI2S1_INT_MAP_CORE0_I2S1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2S1_INT_MAP.Reg) & 0x3f
}

// CORE0.I2S2_INT_MAP: NA
func (o *CORE0_Type) SetI2S2_INT_MAP_CORE0_I2S2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2S2_INT_MAP.Reg, volatile.LoadUint32(&o.I2S2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetI2S2_INT_MAP_CORE0_I2S2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2S2_INT_MAP.Reg) & 0x3f
}

// CORE0.UHCI0_INT_MAP: NA
func (o *CORE0_Type) SetUHCI0_INT_MAP_CORE0_UHCI0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UHCI0_INT_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUHCI0_INT_MAP_CORE0_UHCI0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg) & 0x3f
}

// CORE0.UART0_INT_MAP: NA
func (o *CORE0_Type) SetUART0_INT_MAP_CORE0_UART0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART0_INT_MAP.Reg, volatile.LoadUint32(&o.UART0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUART0_INT_MAP_CORE0_UART0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART0_INT_MAP.Reg) & 0x3f
}

// CORE0.UART1_INT_MAP: NA
func (o *CORE0_Type) SetUART1_INT_MAP_CORE0_UART1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART1_INT_MAP.Reg, volatile.LoadUint32(&o.UART1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUART1_INT_MAP_CORE0_UART1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART1_INT_MAP.Reg) & 0x3f
}

// CORE0.UART2_INT_MAP: NA
func (o *CORE0_Type) SetUART2_INT_MAP_CORE0_UART2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART2_INT_MAP.Reg, volatile.LoadUint32(&o.UART2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUART2_INT_MAP_CORE0_UART2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART2_INT_MAP.Reg) & 0x3f
}

// CORE0.UART3_INT_MAP: NA
func (o *CORE0_Type) SetUART3_INT_MAP_CORE0_UART3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART3_INT_MAP.Reg, volatile.LoadUint32(&o.UART3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUART3_INT_MAP_CORE0_UART3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART3_INT_MAP.Reg) & 0x3f
}

// CORE0.UART4_INT_MAP: NA
func (o *CORE0_Type) SetUART4_INT_MAP_CORE0_UART4_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART4_INT_MAP.Reg, volatile.LoadUint32(&o.UART4_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUART4_INT_MAP_CORE0_UART4_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART4_INT_MAP.Reg) & 0x3f
}

// CORE0.LCD_CAM_INT_MAP: NA
func (o *CORE0_Type) SetLCD_CAM_INT_MAP_CORE0_LCD_CAM_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LCD_CAM_INT_MAP.Reg, volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLCD_CAM_INT_MAP_CORE0_LCD_CAM_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg) & 0x3f
}

// CORE0.ADC_INT_MAP: NA
func (o *CORE0_Type) SetADC_INT_MAP_CORE0_ADC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ADC_INT_MAP.Reg, volatile.LoadUint32(&o.ADC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetADC_INT_MAP_CORE0_ADC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ADC_INT_MAP.Reg) & 0x3f
}

// CORE0.PWM0_INT_MAP: NA
func (o *CORE0_Type) SetPWM0_INT_MAP_CORE0_PWM0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PWM0_INT_MAP.Reg, volatile.LoadUint32(&o.PWM0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPWM0_INT_MAP_CORE0_PWM0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PWM0_INT_MAP.Reg) & 0x3f
}

// CORE0.PWM1_INT_MAP: NA
func (o *CORE0_Type) SetPWM1_INT_MAP_CORE0_PWM1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PWM1_INT_MAP.Reg, volatile.LoadUint32(&o.PWM1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPWM1_INT_MAP_CORE0_PWM1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PWM1_INT_MAP.Reg) & 0x3f
}

// CORE0.CAN0_INT_MAP: NA
func (o *CORE0_Type) SetCAN0_INT_MAP_CORE0_CAN0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CAN0_INT_MAP.Reg, volatile.LoadUint32(&o.CAN0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCAN0_INT_MAP_CORE0_CAN0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CAN0_INT_MAP.Reg) & 0x3f
}

// CORE0.CAN1_INT_MAP: NA
func (o *CORE0_Type) SetCAN1_INT_MAP_CORE0_CAN1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CAN1_INT_MAP.Reg, volatile.LoadUint32(&o.CAN1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCAN1_INT_MAP_CORE0_CAN1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CAN1_INT_MAP.Reg) & 0x3f
}

// CORE0.CAN2_INT_MAP: NA
func (o *CORE0_Type) SetCAN2_INT_MAP_CORE0_CAN2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CAN2_INT_MAP.Reg, volatile.LoadUint32(&o.CAN2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCAN2_INT_MAP_CORE0_CAN2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CAN2_INT_MAP.Reg) & 0x3f
}

// CORE0.RMT_INT_MAP: NA
func (o *CORE0_Type) SetRMT_INT_MAP_CORE0_RMT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.RMT_INT_MAP.Reg, volatile.LoadUint32(&o.RMT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetRMT_INT_MAP_CORE0_RMT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.RMT_INT_MAP.Reg) & 0x3f
}

// CORE0.I2C0_INT_MAP: NA
func (o *CORE0_Type) SetI2C0_INT_MAP_CORE0_I2C0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2C0_INT_MAP.Reg, volatile.LoadUint32(&o.I2C0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetI2C0_INT_MAP_CORE0_I2C0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2C0_INT_MAP.Reg) & 0x3f
}

// CORE0.I2C1_INT_MAP: NA
func (o *CORE0_Type) SetI2C1_INT_MAP_CORE0_I2C1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2C1_INT_MAP.Reg, volatile.LoadUint32(&o.I2C1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetI2C1_INT_MAP_CORE0_I2C1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2C1_INT_MAP.Reg) & 0x3f
}

// CORE0.TIMERGRP0_T0_INT_MAP: NA
func (o *CORE0_Type) SetTIMERGRP0_T0_INT_MAP_CORE0_TIMERGRP0_T0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP0_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetTIMERGRP0_T0_INT_MAP_CORE0_TIMERGRP0_T0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg) & 0x3f
}

// CORE0.TIMERGRP0_T1_INT_MAP: NA
func (o *CORE0_Type) SetTIMERGRP0_T1_INT_MAP_CORE0_TIMERGRP0_T1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP0_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetTIMERGRP0_T1_INT_MAP_CORE0_TIMERGRP0_T1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg) & 0x3f
}

// CORE0.TIMERGRP0_WDT_INT_MAP: NA
func (o *CORE0_Type) SetTIMERGRP0_WDT_INT_MAP_CORE0_TIMERGRP0_WDT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetTIMERGRP0_WDT_INT_MAP_CORE0_TIMERGRP0_WDT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg) & 0x3f
}

// CORE0.TIMERGRP1_T0_INT_MAP: NA
func (o *CORE0_Type) SetTIMERGRP1_T0_INT_MAP_CORE0_TIMERGRP1_T0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP1_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetTIMERGRP1_T0_INT_MAP_CORE0_TIMERGRP1_T0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg) & 0x3f
}

// CORE0.TIMERGRP1_T1_INT_MAP: NA
func (o *CORE0_Type) SetTIMERGRP1_T1_INT_MAP_CORE0_TIMERGRP1_T1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP1_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetTIMERGRP1_T1_INT_MAP_CORE0_TIMERGRP1_T1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg) & 0x3f
}

// CORE0.TIMERGRP1_WDT_INT_MAP: NA
func (o *CORE0_Type) SetTIMERGRP1_WDT_INT_MAP_CORE0_TIMERGRP1_WDT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetTIMERGRP1_WDT_INT_MAP_CORE0_TIMERGRP1_WDT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg) & 0x3f
}

// CORE0.LEDC_INT_MAP: NA
func (o *CORE0_Type) SetLEDC_INT_MAP_CORE0_LEDC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLEDC_INT_MAP_CORE0_LEDC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x3f
}

// CORE0.SYSTIMER_TARGET0_INT_MAP: NA
func (o *CORE0_Type) SetSYSTIMER_TARGET0_INT_MAP_CORE0_SYSTIMER_TARGET0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSYSTIMER_TARGET0_INT_MAP_CORE0_SYSTIMER_TARGET0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x3f
}

// CORE0.SYSTIMER_TARGET1_INT_MAP: NA
func (o *CORE0_Type) SetSYSTIMER_TARGET1_INT_MAP_CORE0_SYSTIMER_TARGET1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSYSTIMER_TARGET1_INT_MAP_CORE0_SYSTIMER_TARGET1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x3f
}

// CORE0.SYSTIMER_TARGET2_INT_MAP: NA
func (o *CORE0_Type) SetSYSTIMER_TARGET2_INT_MAP_CORE0_SYSTIMER_TARGET2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSYSTIMER_TARGET2_INT_MAP_CORE0_SYSTIMER_TARGET2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x3f
}

// CORE0.AHB_PDMA_IN_CH0_INT_MAP: NA
func (o *CORE0_Type) SetAHB_PDMA_IN_CH0_INT_MAP_CORE0_AHB_PDMA_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAHB_PDMA_IN_CH0_INT_MAP_CORE0_AHB_PDMA_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.AHB_PDMA_IN_CH1_INT_MAP: NA
func (o *CORE0_Type) SetAHB_PDMA_IN_CH1_INT_MAP_CORE0_AHB_PDMA_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAHB_PDMA_IN_CH1_INT_MAP_CORE0_AHB_PDMA_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.AHB_PDMA_IN_CH2_INT_MAP: NA
func (o *CORE0_Type) SetAHB_PDMA_IN_CH2_INT_MAP_CORE0_AHB_PDMA_IN_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAHB_PDMA_IN_CH2_INT_MAP_CORE0_AHB_PDMA_IN_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f
}

// CORE0.AHB_PDMA_OUT_CH0_INT_MAP: NA
func (o *CORE0_Type) SetAHB_PDMA_OUT_CH0_INT_MAP_CORE0_AHB_PDMA_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAHB_PDMA_OUT_CH0_INT_MAP_CORE0_AHB_PDMA_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.AHB_PDMA_OUT_CH1_INT_MAP: NA
func (o *CORE0_Type) SetAHB_PDMA_OUT_CH1_INT_MAP_CORE0_AHB_PDMA_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAHB_PDMA_OUT_CH1_INT_MAP_CORE0_AHB_PDMA_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.AHB_PDMA_OUT_CH2_INT_MAP: NA
func (o *CORE0_Type) SetAHB_PDMA_OUT_CH2_INT_MAP_CORE0_AHB_PDMA_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAHB_PDMA_OUT_CH2_INT_MAP_CORE0_AHB_PDMA_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE0.AXI_PDMA_IN_CH0_INT_MAP: NA
func (o *CORE0_Type) SetAXI_PDMA_IN_CH0_INT_MAP_CORE0_AXI_PDMA_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAXI_PDMA_IN_CH0_INT_MAP_CORE0_AXI_PDMA_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.AXI_PDMA_IN_CH1_INT_MAP: NA
func (o *CORE0_Type) SetAXI_PDMA_IN_CH1_INT_MAP_CORE0_AXI_PDMA_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAXI_PDMA_IN_CH1_INT_MAP_CORE0_AXI_PDMA_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.AXI_PDMA_IN_CH2_INT_MAP: NA
func (o *CORE0_Type) SetAXI_PDMA_IN_CH2_INT_MAP_CORE0_AXI_PDMA_IN_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAXI_PDMA_IN_CH2_INT_MAP_CORE0_AXI_PDMA_IN_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f
}

// CORE0.AXI_PDMA_OUT_CH0_INT_MAP: NA
func (o *CORE0_Type) SetAXI_PDMA_OUT_CH0_INT_MAP_CORE0_AXI_PDMA_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAXI_PDMA_OUT_CH0_INT_MAP_CORE0_AXI_PDMA_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.AXI_PDMA_OUT_CH1_INT_MAP: NA
func (o *CORE0_Type) SetAXI_PDMA_OUT_CH1_INT_MAP_CORE0_AXI_PDMA_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAXI_PDMA_OUT_CH1_INT_MAP_CORE0_AXI_PDMA_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.AXI_PDMA_OUT_CH2_INT_MAP: NA
func (o *CORE0_Type) SetAXI_PDMA_OUT_CH2_INT_MAP_CORE0_AXI_PDMA_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAXI_PDMA_OUT_CH2_INT_MAP_CORE0_AXI_PDMA_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE0.RSA_INT_MAP: NA
func (o *CORE0_Type) SetRSA_INT_MAP_CORE0_RSA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.RSA_INT_MAP.Reg, volatile.LoadUint32(&o.RSA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetRSA_INT_MAP_CORE0_RSA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.RSA_INT_MAP.Reg) & 0x3f
}

// CORE0.AES_INT_MAP: NA
func (o *CORE0_Type) SetAES_INT_MAP_CORE0_AES_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AES_INT_MAP.Reg, volatile.LoadUint32(&o.AES_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetAES_INT_MAP_CORE0_AES_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AES_INT_MAP.Reg) & 0x3f
}

// CORE0.SHA_INT_MAP: NA
func (o *CORE0_Type) SetSHA_INT_MAP_CORE0_SHA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSHA_INT_MAP_CORE0_SHA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x3f
}

// CORE0.ECC_INT_MAP: NA
func (o *CORE0_Type) SetECC_INT_MAP_CORE0_ECC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ECC_INT_MAP.Reg, volatile.LoadUint32(&o.ECC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetECC_INT_MAP_CORE0_ECC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ECC_INT_MAP.Reg) & 0x3f
}

// CORE0.ECDSA_INT_MAP: NA
func (o *CORE0_Type) SetECDSA_INT_MAP_CORE0_ECDSA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ECDSA_INT_MAP.Reg, volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetECDSA_INT_MAP_CORE0_ECDSA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg) & 0x3f
}

// CORE0.KM_INT_MAP: NA
func (o *CORE0_Type) SetKM_INT_MAP_CORE0_KM_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.KM_INT_MAP.Reg, volatile.LoadUint32(&o.KM_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetKM_INT_MAP_CORE0_KM_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.KM_INT_MAP.Reg) & 0x3f
}

// CORE0.GPIO_INT0_MAP: NA
func (o *CORE0_Type) SetGPIO_INT0_MAP_CORE0_GPIO_INT0_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT0_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetGPIO_INT0_MAP_CORE0_GPIO_INT0_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg) & 0x3f
}

// CORE0.GPIO_INT1_MAP: NA
func (o *CORE0_Type) SetGPIO_INT1_MAP_CORE0_GPIO_INT1_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT1_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetGPIO_INT1_MAP_CORE0_GPIO_INT1_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg) & 0x3f
}

// CORE0.GPIO_INT2_MAP: NA
func (o *CORE0_Type) SetGPIO_INT2_MAP_CORE0_GPIO_INT2_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT2_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetGPIO_INT2_MAP_CORE0_GPIO_INT2_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg) & 0x3f
}

// CORE0.GPIO_INT3_MAP: NA
func (o *CORE0_Type) SetGPIO_INT3_MAP_CORE0_GPIO_INT3_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT3_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetGPIO_INT3_MAP_CORE0_GPIO_INT3_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg) & 0x3f
}

// CORE0.GPIO_PAD_COMP_INT_MAP: NA
func (o *CORE0_Type) SetGPIO_PAD_COMP_INT_MAP_CORE0_GPIO_PAD_COMP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg, volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetGPIO_PAD_COMP_INT_MAP_CORE0_GPIO_PAD_COMP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg) & 0x3f
}

// CORE0.CPU_INT_FROM_CPU_0_MAP: NA
func (o *CORE0_Type) SetCPU_INT_FROM_CPU_0_MAP_CORE0_CPU_INT_FROM_CPU_0_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCPU_INT_FROM_CPU_0_MAP_CORE0_CPU_INT_FROM_CPU_0_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg) & 0x3f
}

// CORE0.CPU_INT_FROM_CPU_1_MAP: NA
func (o *CORE0_Type) SetCPU_INT_FROM_CPU_1_MAP_CORE0_CPU_INT_FROM_CPU_1_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCPU_INT_FROM_CPU_1_MAP_CORE0_CPU_INT_FROM_CPU_1_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg) & 0x3f
}

// CORE0.CPU_INT_FROM_CPU_2_MAP: NA
func (o *CORE0_Type) SetCPU_INT_FROM_CPU_2_MAP_CORE0_CPU_INT_FROM_CPU_2_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCPU_INT_FROM_CPU_2_MAP_CORE0_CPU_INT_FROM_CPU_2_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg) & 0x3f
}

// CORE0.CPU_INT_FROM_CPU_3_MAP: NA
func (o *CORE0_Type) SetCPU_INT_FROM_CPU_3_MAP_CORE0_CPU_INT_FROM_CPU_3_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCPU_INT_FROM_CPU_3_MAP_CORE0_CPU_INT_FROM_CPU_3_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg) & 0x3f
}

// CORE0.CACHE_INT_MAP: NA
func (o *CORE0_Type) SetCACHE_INT_MAP_CORE0_CACHE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CACHE_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCACHE_INT_MAP_CORE0_CACHE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CACHE_INT_MAP.Reg) & 0x3f
}

// CORE0.FLASH_MSPI_INT_MAP: NA
func (o *CORE0_Type) SetFLASH_MSPI_INT_MAP_CORE0_FLASH_MSPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.FLASH_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetFLASH_MSPI_INT_MAP_CORE0_FLASH_MSPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg) & 0x3f
}

// CORE0.CSI_BRIDGE_INT_MAP: NA
func (o *CORE0_Type) SetCSI_BRIDGE_INT_MAP_CORE0_CSI_BRIDGE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCSI_BRIDGE_INT_MAP_CORE0_CSI_BRIDGE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg) & 0x3f
}

// CORE0.DSI_BRIDGE_INT_MAP: NA
func (o *CORE0_Type) SetDSI_BRIDGE_INT_MAP_CORE0_DSI_BRIDGE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetDSI_BRIDGE_INT_MAP_CORE0_DSI_BRIDGE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg) & 0x3f
}

// CORE0.CSI_INT_MAP: NA
func (o *CORE0_Type) SetCSI_INT_MAP_CORE0_CSI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CSI_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCSI_INT_MAP_CORE0_CSI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CSI_INT_MAP.Reg) & 0x3f
}

// CORE0.DSI_INT_MAP: NA
func (o *CORE0_Type) SetDSI_INT_MAP_CORE0_DSI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DSI_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetDSI_INT_MAP_CORE0_DSI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DSI_INT_MAP.Reg) & 0x3f
}

// CORE0.GMII_PHY_INT_MAP: NA
func (o *CORE0_Type) SetGMII_PHY_INT_MAP_CORE0_GMII_PHY_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.GMII_PHY_INT_MAP.Reg, volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetGMII_PHY_INT_MAP_CORE0_GMII_PHY_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg) & 0x3f
}

// CORE0.LPI_INT_MAP: NA
func (o *CORE0_Type) SetLPI_INT_MAP_CORE0_LPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LPI_INT_MAP.Reg, volatile.LoadUint32(&o.LPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetLPI_INT_MAP_CORE0_LPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LPI_INT_MAP.Reg) & 0x3f
}

// CORE0.PMT_INT_MAP: NA
func (o *CORE0_Type) SetPMT_INT_MAP_CORE0_PMT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PMT_INT_MAP.Reg, volatile.LoadUint32(&o.PMT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPMT_INT_MAP_CORE0_PMT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PMT_INT_MAP.Reg) & 0x3f
}

// CORE0.SBD_INT_MAP: NA
func (o *CORE0_Type) SetSBD_INT_MAP_CORE0_SBD_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SBD_INT_MAP.Reg, volatile.LoadUint32(&o.SBD_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetSBD_INT_MAP_CORE0_SBD_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SBD_INT_MAP.Reg) & 0x3f
}

// CORE0.USB_OTG_INT_MAP: NA
func (o *CORE0_Type) SetUSB_OTG_INT_MAP_CORE0_USB_OTG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_OTG_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUSB_OTG_INT_MAP_CORE0_USB_OTG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg) & 0x3f
}

// CORE0.USB_OTG_ENDP_MULTI_PROC_INT_MAP: NA
func (o *CORE0_Type) SetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg) & 0x3f
}

// CORE0.JPEG_INT_MAP: NA
func (o *CORE0_Type) SetJPEG_INT_MAP_CORE0_JPEG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.JPEG_INT_MAP.Reg, volatile.LoadUint32(&o.JPEG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetJPEG_INT_MAP_CORE0_JPEG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.JPEG_INT_MAP.Reg) & 0x3f
}

// CORE0.PPA_INT_MAP: NA
func (o *CORE0_Type) SetPPA_INT_MAP_CORE0_PPA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PPA_INT_MAP.Reg, volatile.LoadUint32(&o.PPA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPPA_INT_MAP_CORE0_PPA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PPA_INT_MAP.Reg) & 0x3f
}

// CORE0.CORE0_TRACE_INT_MAP: NA
func (o *CORE0_Type) SetCORE0_TRACE_INT_MAP_CORE0_CORE0_TRACE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CORE0_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCORE0_TRACE_INT_MAP_CORE0_CORE0_TRACE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg) & 0x3f
}

// CORE0.CORE1_TRACE_INT_MAP: NA
func (o *CORE0_Type) SetCORE1_TRACE_INT_MAP_CORE0_CORE1_TRACE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CORE1_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetCORE1_TRACE_INT_MAP_CORE0_CORE1_TRACE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg) & 0x3f
}

// CORE0.HP_CORE_CTRL_INT_MAP: NA
func (o *CORE0_Type) SetHP_CORE_CTRL_INT_MAP_CORE0_HP_CORE_CTRL_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_CORE_CTRL_INT_MAP.Reg, volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetHP_CORE_CTRL_INT_MAP_CORE0_HP_CORE_CTRL_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg) & 0x3f
}

// CORE0.ISP_INT_MAP: NA
func (o *CORE0_Type) SetISP_INT_MAP_CORE0_ISP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ISP_INT_MAP.Reg, volatile.LoadUint32(&o.ISP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetISP_INT_MAP_CORE0_ISP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ISP_INT_MAP.Reg) & 0x3f
}

// CORE0.I3C_MST_INT_MAP: NA
func (o *CORE0_Type) SetI3C_MST_INT_MAP_CORE0_I3C_MST_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I3C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetI3C_MST_INT_MAP_CORE0_I3C_MST_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg) & 0x3f
}

// CORE0.I3C_SLV_INT_MAP: NA
func (o *CORE0_Type) SetI3C_SLV_INT_MAP_CORE0_I3C_SLV_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I3C_SLV_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetI3C_SLV_INT_MAP_CORE0_I3C_SLV_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg) & 0x3f
}

// CORE0.USB_OTG11_INT_MAP: NA
func (o *CORE0_Type) SetUSB_OTG11_INT_MAP_CORE0_USB_OTG11_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_OTG11_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetUSB_OTG11_INT_MAP_CORE0_USB_OTG11_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg) & 0x3f
}

// CORE0.DMA2D_IN_CH0_INT_MAP: NA
func (o *CORE0_Type) SetDMA2D_IN_CH0_INT_MAP_CORE0_DMA2D_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetDMA2D_IN_CH0_INT_MAP_CORE0_DMA2D_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.DMA2D_IN_CH1_INT_MAP: NA
func (o *CORE0_Type) SetDMA2D_IN_CH1_INT_MAP_CORE0_DMA2D_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetDMA2D_IN_CH1_INT_MAP_CORE0_DMA2D_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.DMA2D_OUT_CH0_INT_MAP: NA
func (o *CORE0_Type) SetDMA2D_OUT_CH0_INT_MAP_CORE0_DMA2D_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetDMA2D_OUT_CH0_INT_MAP_CORE0_DMA2D_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.DMA2D_OUT_CH1_INT_MAP: NA
func (o *CORE0_Type) SetDMA2D_OUT_CH1_INT_MAP_CORE0_DMA2D_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetDMA2D_OUT_CH1_INT_MAP_CORE0_DMA2D_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.DMA2D_OUT_CH2_INT_MAP: NA
func (o *CORE0_Type) SetDMA2D_OUT_CH2_INT_MAP_CORE0_DMA2D_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetDMA2D_OUT_CH2_INT_MAP_CORE0_DMA2D_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE0.PSRAM_MSPI_INT_MAP: NA
func (o *CORE0_Type) SetPSRAM_MSPI_INT_MAP_CORE0_PSRAM_MSPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PSRAM_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPSRAM_MSPI_INT_MAP_CORE0_PSRAM_MSPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg) & 0x3f
}

// CORE0.HP_SYSREG_INT_MAP: NA
func (o *CORE0_Type) SetHP_SYSREG_INT_MAP_CORE0_HP_SYSREG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetHP_SYSREG_INT_MAP_CORE0_HP_SYSREG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg) & 0x3f
}

// CORE0.PCNT_INT_MAP: NA
func (o *CORE0_Type) SetPCNT_INT_MAP_CORE0_PCNT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PCNT_INT_MAP.Reg, volatile.LoadUint32(&o.PCNT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetPCNT_INT_MAP_CORE0_PCNT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PCNT_INT_MAP.Reg) & 0x3f
}

// CORE0.HP_PAU_INT_MAP: NA
func (o *CORE0_Type) SetHP_PAU_INT_MAP_CORE0_HP_PAU_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_PAU_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetHP_PAU_INT_MAP_CORE0_HP_PAU_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg) & 0x3f
}

// CORE0.HP_PARLIO_RX_INT_MAP: NA
func (o *CORE0_Type) SetHP_PARLIO_RX_INT_MAP_CORE0_HP_PARLIO_RX_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_PARLIO_RX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetHP_PARLIO_RX_INT_MAP_CORE0_HP_PARLIO_RX_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg) & 0x3f
}

// CORE0.HP_PARLIO_TX_INT_MAP: NA
func (o *CORE0_Type) SetHP_PARLIO_TX_INT_MAP_CORE0_HP_PARLIO_TX_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_PARLIO_TX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetHP_PARLIO_TX_INT_MAP_CORE0_HP_PARLIO_TX_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_OUT_CH0_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_OUT_CH0_INT_MAP_CORE0_H264_DMA2D_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_OUT_CH0_INT_MAP_CORE0_H264_DMA2D_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_OUT_CH1_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_OUT_CH1_INT_MAP_CORE0_H264_DMA2D_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_OUT_CH1_INT_MAP_CORE0_H264_DMA2D_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_OUT_CH2_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_OUT_CH2_INT_MAP_CORE0_H264_DMA2D_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_OUT_CH2_INT_MAP_CORE0_H264_DMA2D_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_OUT_CH3_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_OUT_CH3_INT_MAP_CORE0_H264_DMA2D_OUT_CH3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_OUT_CH3_INT_MAP_CORE0_H264_DMA2D_OUT_CH3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_OUT_CH4_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_OUT_CH4_INT_MAP_CORE0_H264_DMA2D_OUT_CH4_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_OUT_CH4_INT_MAP_CORE0_H264_DMA2D_OUT_CH4_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_IN_CH0_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_IN_CH0_INT_MAP_CORE0_H264_DMA2D_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_IN_CH0_INT_MAP_CORE0_H264_DMA2D_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_IN_CH1_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_IN_CH1_INT_MAP_CORE0_H264_DMA2D_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_IN_CH1_INT_MAP_CORE0_H264_DMA2D_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_IN_CH2_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_IN_CH2_INT_MAP_CORE0_H264_DMA2D_IN_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_IN_CH2_INT_MAP_CORE0_H264_DMA2D_IN_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_IN_CH3_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_IN_CH3_INT_MAP_CORE0_H264_DMA2D_IN_CH3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_IN_CH3_INT_MAP_CORE0_H264_DMA2D_IN_CH3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_IN_CH4_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_IN_CH4_INT_MAP_CORE0_H264_DMA2D_IN_CH4_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_IN_CH4_INT_MAP_CORE0_H264_DMA2D_IN_CH4_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_DMA2D_IN_CH5_INT_MAP: NA
func (o *CORE0_Type) SetH264_DMA2D_IN_CH5_INT_MAP_CORE0_H264_DMA2D_IN_CH5_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_DMA2D_IN_CH5_INT_MAP_CORE0_H264_DMA2D_IN_CH5_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg) & 0x3f
}

// CORE0.H264_REG_INT_MAP: NA
func (o *CORE0_Type) SetH264_REG_INT_MAP_CORE0_H264_REG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_REG_INT_MAP.Reg, volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetH264_REG_INT_MAP_CORE0_H264_REG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg) & 0x3f
}

// CORE0.ASSIST_DEBUG_INT_MAP: NA
func (o *CORE0_Type) SetASSIST_DEBUG_INT_MAP_CORE0_ASSIST_DEBUG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ASSIST_DEBUG_INT_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE0_Type) GetASSIST_DEBUG_INT_MAP_CORE0_ASSIST_DEBUG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg) & 0x3f
}

// CORE0.INTR_STATUS_REG_0: NA
func (o *CORE0_Type) SetINTR_STATUS_REG_0(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value)
}
func (o *CORE0_Type) GetINTR_STATUS_REG_0() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg)
}

// CORE0.INTR_STATUS_REG_1: NA
func (o *CORE0_Type) SetINTR_STATUS_REG_1(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value)
}
func (o *CORE0_Type) GetINTR_STATUS_REG_1() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg)
}

// CORE0.INTR_STATUS_REG_2: NA
func (o *CORE0_Type) SetINTR_STATUS_REG_2(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_2.Reg, value)
}
func (o *CORE0_Type) GetINTR_STATUS_REG_2() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_2.Reg)
}

// CORE0.INTR_STATUS_REG_3: NA
func (o *CORE0_Type) SetINTR_STATUS_REG_3(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_3.Reg, value)
}
func (o *CORE0_Type) GetINTR_STATUS_REG_3() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_3.Reg)
}

// CORE0.CLOCK_GATE: NA
func (o *CORE0_Type) SetCLOCK_GATE_CORE0_REG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *CORE0_Type) GetCLOCK_GATE_CORE0_REG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1
}

// CORE0.INTERRUPT_REG_DATE: NA
func (o *CORE0_Type) SetINTERRUPT_REG_DATE_CORE0_INTERRUPT_REG_DATE(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value)
}
func (o *CORE0_Type) GetINTERRUPT_REG_DATE_CORE0_INTERRUPT_REG_DATE() uint32 {
	return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff
}

// Interrupt Controller (Core 1)
type CORE1_Type struct {
	LP_RTC_INT_MAP                  volatile.Register32 // 0x0
	LP_WDT_INT_MAP                  volatile.Register32 // 0x4
	LP_TIMER_REG_0_INT_MAP          volatile.Register32 // 0x8
	LP_TIMER_REG_1_INT_MAP          volatile.Register32 // 0xC
	MB_HP_INT_MAP                   volatile.Register32 // 0x10
	MB_LP_INT_MAP                   volatile.Register32 // 0x14
	PMU_REG_0_INT_MAP               volatile.Register32 // 0x18
	PMU_REG_1_INT_MAP               volatile.Register32 // 0x1C
	LP_ANAPERI_INT_MAP              volatile.Register32 // 0x20
	LP_ADC_INT_MAP                  volatile.Register32 // 0x24
	LP_GPIO_INT_MAP                 volatile.Register32 // 0x28
	LP_I2C_INT_MAP                  volatile.Register32 // 0x2C
	LP_I2S_INT_MAP                  volatile.Register32 // 0x30
	LP_SPI_INT_MAP                  volatile.Register32 // 0x34
	LP_TOUCH_INT_MAP                volatile.Register32 // 0x38
	LP_TSENS_INT_MAP                volatile.Register32 // 0x3C
	LP_UART_INT_MAP                 volatile.Register32 // 0x40
	LP_EFUSE_INT_MAP                volatile.Register32 // 0x44
	LP_SW_INT_MAP                   volatile.Register32 // 0x48
	LP_SYSREG_INT_MAP               volatile.Register32 // 0x4C
	LP_HUK_INT_MAP                  volatile.Register32 // 0x50
	SYS_ICM_INT_MAP                 volatile.Register32 // 0x54
	USB_DEVICE_INT_MAP              volatile.Register32 // 0x58
	SDIO_HOST_INT_MAP               volatile.Register32 // 0x5C
	GDMA_INT_MAP                    volatile.Register32 // 0x60
	SPI2_INT_MAP                    volatile.Register32 // 0x64
	SPI3_INT_MAP                    volatile.Register32 // 0x68
	I2S0_INT_MAP                    volatile.Register32 // 0x6C
	I2S1_INT_MAP                    volatile.Register32 // 0x70
	I2S2_INT_MAP                    volatile.Register32 // 0x74
	UHCI0_INT_MAP                   volatile.Register32 // 0x78
	UART0_INT_MAP                   volatile.Register32 // 0x7C
	UART1_INT_MAP                   volatile.Register32 // 0x80
	UART2_INT_MAP                   volatile.Register32 // 0x84
	UART3_INT_MAP                   volatile.Register32 // 0x88
	UART4_INT_MAP                   volatile.Register32 // 0x8C
	LCD_CAM_INT_MAP                 volatile.Register32 // 0x90
	ADC_INT_MAP                     volatile.Register32 // 0x94
	PWM0_INT_MAP                    volatile.Register32 // 0x98
	PWM1_INT_MAP                    volatile.Register32 // 0x9C
	CAN0_INT_MAP                    volatile.Register32 // 0xA0
	CAN1_INT_MAP                    volatile.Register32 // 0xA4
	CAN2_INT_MAP                    volatile.Register32 // 0xA8
	RMT_INT_MAP                     volatile.Register32 // 0xAC
	I2C0_INT_MAP                    volatile.Register32 // 0xB0
	I2C1_INT_MAP                    volatile.Register32 // 0xB4
	TIMERGRP0_T0_INT_MAP            volatile.Register32 // 0xB8
	TIMERGRP0_T1_INT_MAP            volatile.Register32 // 0xBC
	TIMERGRP0_WDT_INT_MAP           volatile.Register32 // 0xC0
	TIMERGRP1_T0_INT_MAP            volatile.Register32 // 0xC4
	TIMERGRP1_T1_INT_MAP            volatile.Register32 // 0xC8
	TIMERGRP1_WDT_INT_MAP           volatile.Register32 // 0xCC
	LEDC_INT_MAP                    volatile.Register32 // 0xD0
	SYSTIMER_TARGET0_INT_MAP        volatile.Register32 // 0xD4
	SYSTIMER_TARGET1_INT_MAP        volatile.Register32 // 0xD8
	SYSTIMER_TARGET2_INT_MAP        volatile.Register32 // 0xDC
	AHB_PDMA_IN_CH0_INT_MAP         volatile.Register32 // 0xE0
	AHB_PDMA_IN_CH1_INT_MAP         volatile.Register32 // 0xE4
	AHB_PDMA_IN_CH2_INT_MAP         volatile.Register32 // 0xE8
	AHB_PDMA_OUT_CH0_INT_MAP        volatile.Register32 // 0xEC
	AHB_PDMA_OUT_CH1_INT_MAP        volatile.Register32 // 0xF0
	AHB_PDMA_OUT_CH2_INT_MAP        volatile.Register32 // 0xF4
	AXI_PDMA_IN_CH0_INT_MAP         volatile.Register32 // 0xF8
	AXI_PDMA_IN_CH1_INT_MAP         volatile.Register32 // 0xFC
	AXI_PDMA_IN_CH2_INT_MAP         volatile.Register32 // 0x100
	AXI_PDMA_OUT_CH0_INT_MAP        volatile.Register32 // 0x104
	AXI_PDMA_OUT_CH1_INT_MAP        volatile.Register32 // 0x108
	AXI_PDMA_OUT_CH2_INT_MAP        volatile.Register32 // 0x10C
	RSA_INT_MAP                     volatile.Register32 // 0x110
	AES_INT_MAP                     volatile.Register32 // 0x114
	SHA_INT_MAP                     volatile.Register32 // 0x118
	ECC_INT_MAP                     volatile.Register32 // 0x11C
	ECDSA_INT_MAP                   volatile.Register32 // 0x120
	KM_INT_MAP                      volatile.Register32 // 0x124
	GPIO_INT0_MAP                   volatile.Register32 // 0x128
	GPIO_INT1_MAP                   volatile.Register32 // 0x12C
	GPIO_INT2_MAP                   volatile.Register32 // 0x130
	GPIO_INT3_MAP                   volatile.Register32 // 0x134
	GPIO_PAD_COMP_INT_MAP           volatile.Register32 // 0x138
	CPU_INT_FROM_CPU_0_MAP          volatile.Register32 // 0x13C
	CPU_INT_FROM_CPU_1_MAP          volatile.Register32 // 0x140
	CPU_INT_FROM_CPU_2_MAP          volatile.Register32 // 0x144
	CPU_INT_FROM_CPU_3_MAP          volatile.Register32 // 0x148
	CACHE_INT_MAP                   volatile.Register32 // 0x14C
	FLASH_MSPI_INT_MAP              volatile.Register32 // 0x150
	CSI_BRIDGE_INT_MAP              volatile.Register32 // 0x154
	DSI_BRIDGE_INT_MAP              volatile.Register32 // 0x158
	CSI_INT_MAP                     volatile.Register32 // 0x15C
	DSI_INT_MAP                     volatile.Register32 // 0x160
	GMII_PHY_INT_MAP                volatile.Register32 // 0x164
	LPI_INT_MAP                     volatile.Register32 // 0x168
	PMT_INT_MAP                     volatile.Register32 // 0x16C
	SBD_INT_MAP                     volatile.Register32 // 0x170
	USB_OTG_INT_MAP                 volatile.Register32 // 0x174
	USB_OTG_ENDP_MULTI_PROC_INT_MAP volatile.Register32 // 0x178
	JPEG_INT_MAP                    volatile.Register32 // 0x17C
	PPA_INT_MAP                     volatile.Register32 // 0x180
	CORE0_TRACE_INT_MAP             volatile.Register32 // 0x184
	CORE1_TRACE_INT_MAP             volatile.Register32 // 0x188
	HP_CORE_CTRL_INT_MAP            volatile.Register32 // 0x18C
	ISP_INT_MAP                     volatile.Register32 // 0x190
	I3C_MST_INT_MAP                 volatile.Register32 // 0x194
	I3C_SLV_INT_MAP                 volatile.Register32 // 0x198
	USB_OTG11_INT_MAP               volatile.Register32 // 0x19C
	DMA2D_IN_CH0_INT_MAP            volatile.Register32 // 0x1A0
	DMA2D_IN_CH1_INT_MAP            volatile.Register32 // 0x1A4
	DMA2D_OUT_CH0_INT_MAP           volatile.Register32 // 0x1A8
	DMA2D_OUT_CH1_INT_MAP           volatile.Register32 // 0x1AC
	DMA2D_OUT_CH2_INT_MAP           volatile.Register32 // 0x1B0
	PSRAM_MSPI_INT_MAP              volatile.Register32 // 0x1B4
	HP_SYSREG_INT_MAP               volatile.Register32 // 0x1B8
	PCNT_INT_MAP                    volatile.Register32 // 0x1BC
	HP_PAU_INT_MAP                  volatile.Register32 // 0x1C0
	HP_PARLIO_RX_INT_MAP            volatile.Register32 // 0x1C4
	HP_PARLIO_TX_INT_MAP            volatile.Register32 // 0x1C8
	H264_DMA2D_OUT_CH0_INT_MAP      volatile.Register32 // 0x1CC
	H264_DMA2D_OUT_CH1_INT_MAP      volatile.Register32 // 0x1D0
	H264_DMA2D_OUT_CH2_INT_MAP      volatile.Register32 // 0x1D4
	H264_DMA2D_OUT_CH3_INT_MAP      volatile.Register32 // 0x1D8
	H264_DMA2D_OUT_CH4_INT_MAP      volatile.Register32 // 0x1DC
	H264_DMA2D_IN_CH0_INT_MAP       volatile.Register32 // 0x1E0
	H264_DMA2D_IN_CH1_INT_MAP       volatile.Register32 // 0x1E4
	H264_DMA2D_IN_CH2_INT_MAP       volatile.Register32 // 0x1E8
	H264_DMA2D_IN_CH3_INT_MAP       volatile.Register32 // 0x1EC
	H264_DMA2D_IN_CH4_INT_MAP       volatile.Register32 // 0x1F0
	H264_DMA2D_IN_CH5_INT_MAP       volatile.Register32 // 0x1F4
	H264_REG_INT_MAP                volatile.Register32 // 0x1F8
	ASSIST_DEBUG_INT_MAP            volatile.Register32 // 0x1FC
	INTR_STATUS_REG_0               volatile.Register32 // 0x200
	INTR_STATUS_REG_1               volatile.Register32 // 0x204
	INTR_STATUS_REG_2               volatile.Register32 // 0x208
	INTR_STATUS_REG_3               volatile.Register32 // 0x20C
	CLOCK_GATE                      volatile.Register32 // 0x210
	_                               [488]byte
	INTERRUPT_REG_DATE              volatile.Register32 // 0x3FC
}

// CORE1.LP_RTC_INT_MAP: NA
func (o *CORE1_Type) SetLP_RTC_INT_MAP_CORE1_LP_RTC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_RTC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_RTC_INT_MAP_CORE1_LP_RTC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_RTC_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_WDT_INT_MAP: NA
func (o *CORE1_Type) SetLP_WDT_INT_MAP_CORE1_LP_WDT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_WDT_INT_MAP_CORE1_LP_WDT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_WDT_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_TIMER_REG_0_INT_MAP: NA
func (o *CORE1_Type) SetLP_TIMER_REG_0_INT_MAP_CORE1_LP_TIMER_REG_0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_TIMER_REG_0_INT_MAP_CORE1_LP_TIMER_REG_0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TIMER_REG_0_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_TIMER_REG_1_INT_MAP: NA
func (o *CORE1_Type) SetLP_TIMER_REG_1_INT_MAP_CORE1_LP_TIMER_REG_1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_TIMER_REG_1_INT_MAP_CORE1_LP_TIMER_REG_1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TIMER_REG_1_INT_MAP.Reg) & 0x3f
}

// CORE1.MB_HP_INT_MAP: NA
func (o *CORE1_Type) SetMB_HP_INT_MAP_CORE1_MB_HP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.MB_HP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetMB_HP_INT_MAP_CORE1_MB_HP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.MB_HP_INT_MAP.Reg) & 0x3f
}

// CORE1.MB_LP_INT_MAP: NA
func (o *CORE1_Type) SetMB_LP_INT_MAP_CORE1_MB_LP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.MB_LP_INT_MAP.Reg, volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetMB_LP_INT_MAP_CORE1_MB_LP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.MB_LP_INT_MAP.Reg) & 0x3f
}

// CORE1.PMU_REG_0_INT_MAP: NA
func (o *CORE1_Type) SetPMU_REG_0_INT_MAP_CORE1_PMU_REG_0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PMU_REG_0_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPMU_REG_0_INT_MAP_CORE1_PMU_REG_0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PMU_REG_0_INT_MAP.Reg) & 0x3f
}

// CORE1.PMU_REG_1_INT_MAP: NA
func (o *CORE1_Type) SetPMU_REG_1_INT_MAP_CORE1_PMU_REG_1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PMU_REG_1_INT_MAP.Reg, volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPMU_REG_1_INT_MAP_CORE1_PMU_REG_1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PMU_REG_1_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_ANAPERI_INT_MAP: NA
func (o *CORE1_Type) SetLP_ANAPERI_INT_MAP_CORE1_LP_ANAPERI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_ANAPERI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_ANAPERI_INT_MAP_CORE1_LP_ANAPERI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_ANAPERI_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_ADC_INT_MAP: NA
func (o *CORE1_Type) SetLP_ADC_INT_MAP_CORE1_LP_ADC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_ADC_INT_MAP.Reg, volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_ADC_INT_MAP_CORE1_LP_ADC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_ADC_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_GPIO_INT_MAP: NA
func (o *CORE1_Type) SetLP_GPIO_INT_MAP_CORE1_LP_GPIO_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_GPIO_INT_MAP.Reg, volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_GPIO_INT_MAP_CORE1_LP_GPIO_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_GPIO_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_I2C_INT_MAP: NA
func (o *CORE1_Type) SetLP_I2C_INT_MAP_CORE1_LP_I2C_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_I2C_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_I2C_INT_MAP_CORE1_LP_I2C_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_I2C_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_I2S_INT_MAP: NA
func (o *CORE1_Type) SetLP_I2S_INT_MAP_CORE1_LP_I2S_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_INT_MAP.Reg, volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_I2S_INT_MAP_CORE1_LP_I2S_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_I2S_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_SPI_INT_MAP: NA
func (o *CORE1_Type) SetLP_SPI_INT_MAP_CORE1_LP_SPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_SPI_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_SPI_INT_MAP_CORE1_LP_SPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_SPI_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_TOUCH_INT_MAP: NA
func (o *CORE1_Type) SetLP_TOUCH_INT_MAP_CORE1_LP_TOUCH_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TOUCH_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_TOUCH_INT_MAP_CORE1_LP_TOUCH_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TOUCH_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_TSENS_INT_MAP: NA
func (o *CORE1_Type) SetLP_TSENS_INT_MAP_CORE1_LP_TSENS_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_TSENS_INT_MAP.Reg, volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_TSENS_INT_MAP_CORE1_LP_TSENS_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_TSENS_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_UART_INT_MAP: NA
func (o *CORE1_Type) SetLP_UART_INT_MAP_CORE1_LP_UART_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_UART_INT_MAP.Reg, volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_UART_INT_MAP_CORE1_LP_UART_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_UART_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_EFUSE_INT_MAP: NA
func (o *CORE1_Type) SetLP_EFUSE_INT_MAP_CORE1_LP_EFUSE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_EFUSE_INT_MAP.Reg, volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_EFUSE_INT_MAP_CORE1_LP_EFUSE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_EFUSE_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_SW_INT_MAP: NA
func (o *CORE1_Type) SetLP_SW_INT_MAP_CORE1_LP_SW_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_SW_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_SW_INT_MAP_CORE1_LP_SW_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_SW_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_SYSREG_INT_MAP: NA
func (o *CORE1_Type) SetLP_SYSREG_INT_MAP_CORE1_LP_SYSREG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_SYSREG_INT_MAP_CORE1_LP_SYSREG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_SYSREG_INT_MAP.Reg) & 0x3f
}

// CORE1.LP_HUK_INT_MAP: NA
func (o *CORE1_Type) SetLP_HUK_INT_MAP_CORE1_LP_HUK_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_HUK_INT_MAP.Reg, volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLP_HUK_INT_MAP_CORE1_LP_HUK_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LP_HUK_INT_MAP.Reg) & 0x3f
}

// CORE1.SYS_ICM_INT_MAP: NA
func (o *CORE1_Type) SetSYS_ICM_INT_MAP_CORE1_SYS_ICM_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYS_ICM_INT_MAP.Reg, volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSYS_ICM_INT_MAP_CORE1_SYS_ICM_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYS_ICM_INT_MAP.Reg) & 0x3f
}

// CORE1.USB_DEVICE_INT_MAP: NA
func (o *CORE1_Type) SetUSB_DEVICE_INT_MAP_CORE1_USB_DEVICE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_DEVICE_INT_MAP.Reg, volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUSB_DEVICE_INT_MAP_CORE1_USB_DEVICE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_DEVICE_INT_MAP.Reg) & 0x3f
}

// CORE1.SDIO_HOST_INT_MAP: NA
func (o *CORE1_Type) SetSDIO_HOST_INT_MAP_CORE1_SDIO_HOST_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SDIO_HOST_INT_MAP.Reg, volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSDIO_HOST_INT_MAP_CORE1_SDIO_HOST_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SDIO_HOST_INT_MAP.Reg) & 0x3f
}

// CORE1.GDMA_INT_MAP: NA
func (o *CORE1_Type) SetGDMA_INT_MAP_CORE1_GDMA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.GDMA_INT_MAP.Reg, volatile.LoadUint32(&o.GDMA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetGDMA_INT_MAP_CORE1_GDMA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.GDMA_INT_MAP.Reg) & 0x3f
}

// CORE1.SPI2_INT_MAP: NA
func (o *CORE1_Type) SetSPI2_INT_MAP_CORE1_SPI2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SPI2_INT_MAP.Reg, volatile.LoadUint32(&o.SPI2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSPI2_INT_MAP_CORE1_SPI2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SPI2_INT_MAP.Reg) & 0x3f
}

// CORE1.SPI3_INT_MAP: NA
func (o *CORE1_Type) SetSPI3_INT_MAP_CORE1_SPI3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SPI3_INT_MAP.Reg, volatile.LoadUint32(&o.SPI3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSPI3_INT_MAP_CORE1_SPI3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SPI3_INT_MAP.Reg) & 0x3f
}

// CORE1.I2S0_INT_MAP: NA
func (o *CORE1_Type) SetI2S0_INT_MAP_CORE1_I2S0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2S0_INT_MAP.Reg, volatile.LoadUint32(&o.I2S0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetI2S0_INT_MAP_CORE1_I2S0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2S0_INT_MAP.Reg) & 0x3f
}

// CORE1.I2S1_INT_MAP: NA
func (o *CORE1_Type) SetI2S1_INT_MAP_CORE1_I2S1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2S1_INT_MAP.Reg, volatile.LoadUint32(&o.I2S1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetI2S1_INT_MAP_CORE1_I2S1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2S1_INT_MAP.Reg) & 0x3f
}

// CORE1.I2S2_INT_MAP: NA
func (o *CORE1_Type) SetI2S2_INT_MAP_CORE1_I2S2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2S2_INT_MAP.Reg, volatile.LoadUint32(&o.I2S2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetI2S2_INT_MAP_CORE1_I2S2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2S2_INT_MAP.Reg) & 0x3f
}

// CORE1.UHCI0_INT_MAP: NA
func (o *CORE1_Type) SetUHCI0_INT_MAP_CORE1_UHCI0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UHCI0_INT_MAP.Reg, volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUHCI0_INT_MAP_CORE1_UHCI0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UHCI0_INT_MAP.Reg) & 0x3f
}

// CORE1.UART0_INT_MAP: NA
func (o *CORE1_Type) SetUART0_INT_MAP_CORE1_UART0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART0_INT_MAP.Reg, volatile.LoadUint32(&o.UART0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUART0_INT_MAP_CORE1_UART0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART0_INT_MAP.Reg) & 0x3f
}

// CORE1.UART1_INT_MAP: NA
func (o *CORE1_Type) SetUART1_INT_MAP_CORE1_UART1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART1_INT_MAP.Reg, volatile.LoadUint32(&o.UART1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUART1_INT_MAP_CORE1_UART1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART1_INT_MAP.Reg) & 0x3f
}

// CORE1.UART2_INT_MAP: NA
func (o *CORE1_Type) SetUART2_INT_MAP_CORE1_UART2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART2_INT_MAP.Reg, volatile.LoadUint32(&o.UART2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUART2_INT_MAP_CORE1_UART2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART2_INT_MAP.Reg) & 0x3f
}

// CORE1.UART3_INT_MAP: NA
func (o *CORE1_Type) SetUART3_INT_MAP_CORE1_UART3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART3_INT_MAP.Reg, volatile.LoadUint32(&o.UART3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUART3_INT_MAP_CORE1_UART3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART3_INT_MAP.Reg) & 0x3f
}

// CORE1.UART4_INT_MAP: NA
func (o *CORE1_Type) SetUART4_INT_MAP_CORE1_UART4_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.UART4_INT_MAP.Reg, volatile.LoadUint32(&o.UART4_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUART4_INT_MAP_CORE1_UART4_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.UART4_INT_MAP.Reg) & 0x3f
}

// CORE1.LCD_CAM_INT_MAP: NA
func (o *CORE1_Type) SetLCD_CAM_INT_MAP_CORE1_LCD_CAM_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LCD_CAM_INT_MAP.Reg, volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLCD_CAM_INT_MAP_CORE1_LCD_CAM_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LCD_CAM_INT_MAP.Reg) & 0x3f
}

// CORE1.ADC_INT_MAP: NA
func (o *CORE1_Type) SetADC_INT_MAP_CORE1_ADC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ADC_INT_MAP.Reg, volatile.LoadUint32(&o.ADC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetADC_INT_MAP_CORE1_ADC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ADC_INT_MAP.Reg) & 0x3f
}

// CORE1.PWM0_INT_MAP: NA
func (o *CORE1_Type) SetPWM0_INT_MAP_CORE1_PWM0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PWM0_INT_MAP.Reg, volatile.LoadUint32(&o.PWM0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPWM0_INT_MAP_CORE1_PWM0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PWM0_INT_MAP.Reg) & 0x3f
}

// CORE1.PWM1_INT_MAP: NA
func (o *CORE1_Type) SetPWM1_INT_MAP_CORE1_PWM1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PWM1_INT_MAP.Reg, volatile.LoadUint32(&o.PWM1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPWM1_INT_MAP_CORE1_PWM1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PWM1_INT_MAP.Reg) & 0x3f
}

// CORE1.CAN0_INT_MAP: NA
func (o *CORE1_Type) SetCAN0_INT_MAP_CORE1_CAN0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CAN0_INT_MAP.Reg, volatile.LoadUint32(&o.CAN0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCAN0_INT_MAP_CORE1_CAN0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CAN0_INT_MAP.Reg) & 0x3f
}

// CORE1.CAN1_INT_MAP: NA
func (o *CORE1_Type) SetCAN1_INT_MAP_CORE1_CAN1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CAN1_INT_MAP.Reg, volatile.LoadUint32(&o.CAN1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCAN1_INT_MAP_CORE1_CAN1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CAN1_INT_MAP.Reg) & 0x3f
}

// CORE1.CAN2_INT_MAP: NA
func (o *CORE1_Type) SetCAN2_INT_MAP_CORE1_CAN2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CAN2_INT_MAP.Reg, volatile.LoadUint32(&o.CAN2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCAN2_INT_MAP_CORE1_CAN2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CAN2_INT_MAP.Reg) & 0x3f
}

// CORE1.RMT_INT_MAP: NA
func (o *CORE1_Type) SetRMT_INT_MAP_CORE1_RMT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.RMT_INT_MAP.Reg, volatile.LoadUint32(&o.RMT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetRMT_INT_MAP_CORE1_RMT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.RMT_INT_MAP.Reg) & 0x3f
}

// CORE1.I2C0_INT_MAP: NA
func (o *CORE1_Type) SetI2C0_INT_MAP_CORE1_I2C0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2C0_INT_MAP.Reg, volatile.LoadUint32(&o.I2C0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetI2C0_INT_MAP_CORE1_I2C0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2C0_INT_MAP.Reg) & 0x3f
}

// CORE1.I2C1_INT_MAP: NA
func (o *CORE1_Type) SetI2C1_INT_MAP_CORE1_I2C1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I2C1_INT_MAP.Reg, volatile.LoadUint32(&o.I2C1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetI2C1_INT_MAP_CORE1_I2C1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I2C1_INT_MAP.Reg) & 0x3f
}

// CORE1.TIMERGRP0_T0_INT_MAP: NA
func (o *CORE1_Type) SetTIMERGRP0_T0_INT_MAP_CORE1_TIMERGRP0_T0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP0_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetTIMERGRP0_T0_INT_MAP_CORE1_TIMERGRP0_T0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP0_T0_INT_MAP.Reg) & 0x3f
}

// CORE1.TIMERGRP0_T1_INT_MAP: NA
func (o *CORE1_Type) SetTIMERGRP0_T1_INT_MAP_CORE1_TIMERGRP0_T1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP0_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetTIMERGRP0_T1_INT_MAP_CORE1_TIMERGRP0_T1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP0_T1_INT_MAP.Reg) & 0x3f
}

// CORE1.TIMERGRP0_WDT_INT_MAP: NA
func (o *CORE1_Type) SetTIMERGRP0_WDT_INT_MAP_CORE1_TIMERGRP0_WDT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetTIMERGRP0_WDT_INT_MAP_CORE1_TIMERGRP0_WDT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP0_WDT_INT_MAP.Reg) & 0x3f
}

// CORE1.TIMERGRP1_T0_INT_MAP: NA
func (o *CORE1_Type) SetTIMERGRP1_T0_INT_MAP_CORE1_TIMERGRP1_T0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP1_T0_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetTIMERGRP1_T0_INT_MAP_CORE1_TIMERGRP1_T0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP1_T0_INT_MAP.Reg) & 0x3f
}

// CORE1.TIMERGRP1_T1_INT_MAP: NA
func (o *CORE1_Type) SetTIMERGRP1_T1_INT_MAP_CORE1_TIMERGRP1_T1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP1_T1_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetTIMERGRP1_T1_INT_MAP_CORE1_TIMERGRP1_T1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP1_T1_INT_MAP.Reg) & 0x3f
}

// CORE1.TIMERGRP1_WDT_INT_MAP: NA
func (o *CORE1_Type) SetTIMERGRP1_WDT_INT_MAP_CORE1_TIMERGRP1_WDT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg, volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetTIMERGRP1_WDT_INT_MAP_CORE1_TIMERGRP1_WDT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.TIMERGRP1_WDT_INT_MAP.Reg) & 0x3f
}

// CORE1.LEDC_INT_MAP: NA
func (o *CORE1_Type) SetLEDC_INT_MAP_CORE1_LEDC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LEDC_INT_MAP.Reg, volatile.LoadUint32(&o.LEDC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLEDC_INT_MAP_CORE1_LEDC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LEDC_INT_MAP.Reg) & 0x3f
}

// CORE1.SYSTIMER_TARGET0_INT_MAP: NA
func (o *CORE1_Type) SetSYSTIMER_TARGET0_INT_MAP_CORE1_SYSTIMER_TARGET0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSYSTIMER_TARGET0_INT_MAP_CORE1_SYSTIMER_TARGET0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYSTIMER_TARGET0_INT_MAP.Reg) & 0x3f
}

// CORE1.SYSTIMER_TARGET1_INT_MAP: NA
func (o *CORE1_Type) SetSYSTIMER_TARGET1_INT_MAP_CORE1_SYSTIMER_TARGET1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSYSTIMER_TARGET1_INT_MAP_CORE1_SYSTIMER_TARGET1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYSTIMER_TARGET1_INT_MAP.Reg) & 0x3f
}

// CORE1.SYSTIMER_TARGET2_INT_MAP: NA
func (o *CORE1_Type) SetSYSTIMER_TARGET2_INT_MAP_CORE1_SYSTIMER_TARGET2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg, volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSYSTIMER_TARGET2_INT_MAP_CORE1_SYSTIMER_TARGET2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SYSTIMER_TARGET2_INT_MAP.Reg) & 0x3f
}

// CORE1.AHB_PDMA_IN_CH0_INT_MAP: NA
func (o *CORE1_Type) SetAHB_PDMA_IN_CH0_INT_MAP_CORE1_AHB_PDMA_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAHB_PDMA_IN_CH0_INT_MAP_CORE1_AHB_PDMA_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.AHB_PDMA_IN_CH1_INT_MAP: NA
func (o *CORE1_Type) SetAHB_PDMA_IN_CH1_INT_MAP_CORE1_AHB_PDMA_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAHB_PDMA_IN_CH1_INT_MAP_CORE1_AHB_PDMA_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.AHB_PDMA_IN_CH2_INT_MAP: NA
func (o *CORE1_Type) SetAHB_PDMA_IN_CH2_INT_MAP_CORE1_AHB_PDMA_IN_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAHB_PDMA_IN_CH2_INT_MAP_CORE1_AHB_PDMA_IN_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f
}

// CORE1.AHB_PDMA_OUT_CH0_INT_MAP: NA
func (o *CORE1_Type) SetAHB_PDMA_OUT_CH0_INT_MAP_CORE1_AHB_PDMA_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAHB_PDMA_OUT_CH0_INT_MAP_CORE1_AHB_PDMA_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.AHB_PDMA_OUT_CH1_INT_MAP: NA
func (o *CORE1_Type) SetAHB_PDMA_OUT_CH1_INT_MAP_CORE1_AHB_PDMA_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAHB_PDMA_OUT_CH1_INT_MAP_CORE1_AHB_PDMA_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.AHB_PDMA_OUT_CH2_INT_MAP: NA
func (o *CORE1_Type) SetAHB_PDMA_OUT_CH2_INT_MAP_CORE1_AHB_PDMA_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAHB_PDMA_OUT_CH2_INT_MAP_CORE1_AHB_PDMA_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AHB_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE1.AXI_PDMA_IN_CH0_INT_MAP: NA
func (o *CORE1_Type) SetAXI_PDMA_IN_CH0_INT_MAP_CORE1_AXI_PDMA_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAXI_PDMA_IN_CH0_INT_MAP_CORE1_AXI_PDMA_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.AXI_PDMA_IN_CH1_INT_MAP: NA
func (o *CORE1_Type) SetAXI_PDMA_IN_CH1_INT_MAP_CORE1_AXI_PDMA_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAXI_PDMA_IN_CH1_INT_MAP_CORE1_AXI_PDMA_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.AXI_PDMA_IN_CH2_INT_MAP: NA
func (o *CORE1_Type) SetAXI_PDMA_IN_CH2_INT_MAP_CORE1_AXI_PDMA_IN_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAXI_PDMA_IN_CH2_INT_MAP_CORE1_AXI_PDMA_IN_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_IN_CH2_INT_MAP.Reg) & 0x3f
}

// CORE1.AXI_PDMA_OUT_CH0_INT_MAP: NA
func (o *CORE1_Type) SetAXI_PDMA_OUT_CH0_INT_MAP_CORE1_AXI_PDMA_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAXI_PDMA_OUT_CH0_INT_MAP_CORE1_AXI_PDMA_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.AXI_PDMA_OUT_CH1_INT_MAP: NA
func (o *CORE1_Type) SetAXI_PDMA_OUT_CH1_INT_MAP_CORE1_AXI_PDMA_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAXI_PDMA_OUT_CH1_INT_MAP_CORE1_AXI_PDMA_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.AXI_PDMA_OUT_CH2_INT_MAP: NA
func (o *CORE1_Type) SetAXI_PDMA_OUT_CH2_INT_MAP_CORE1_AXI_PDMA_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAXI_PDMA_OUT_CH2_INT_MAP_CORE1_AXI_PDMA_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AXI_PDMA_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE1.RSA_INT_MAP: NA
func (o *CORE1_Type) SetRSA_INT_MAP_CORE1_RSA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.RSA_INT_MAP.Reg, volatile.LoadUint32(&o.RSA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetRSA_INT_MAP_CORE1_RSA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.RSA_INT_MAP.Reg) & 0x3f
}

// CORE1.AES_INT_MAP: NA
func (o *CORE1_Type) SetAES_INT_MAP_CORE1_AES_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.AES_INT_MAP.Reg, volatile.LoadUint32(&o.AES_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetAES_INT_MAP_CORE1_AES_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.AES_INT_MAP.Reg) & 0x3f
}

// CORE1.SHA_INT_MAP: NA
func (o *CORE1_Type) SetSHA_INT_MAP_CORE1_SHA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SHA_INT_MAP.Reg, volatile.LoadUint32(&o.SHA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSHA_INT_MAP_CORE1_SHA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SHA_INT_MAP.Reg) & 0x3f
}

// CORE1.ECC_INT_MAP: NA
func (o *CORE1_Type) SetECC_INT_MAP_CORE1_ECC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ECC_INT_MAP.Reg, volatile.LoadUint32(&o.ECC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetECC_INT_MAP_CORE1_ECC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ECC_INT_MAP.Reg) & 0x3f
}

// CORE1.ECDSA_INT_MAP: NA
func (o *CORE1_Type) SetECDSA_INT_MAP_CORE1_ECDSA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ECDSA_INT_MAP.Reg, volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetECDSA_INT_MAP_CORE1_ECDSA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ECDSA_INT_MAP.Reg) & 0x3f
}

// CORE1.KM_INT_MAP: NA
func (o *CORE1_Type) SetKM_INT_MAP_CORE1_KM_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.KM_INT_MAP.Reg, volatile.LoadUint32(&o.KM_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetKM_INT_MAP_CORE1_KM_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.KM_INT_MAP.Reg) & 0x3f
}

// CORE1.GPIO_INT0_MAP: NA
func (o *CORE1_Type) SetGPIO_INT0_MAP_CORE1_GPIO_INT0_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT0_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetGPIO_INT0_MAP_CORE1_GPIO_INT0_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT0_MAP.Reg) & 0x3f
}

// CORE1.GPIO_INT1_MAP: NA
func (o *CORE1_Type) SetGPIO_INT1_MAP_CORE1_GPIO_INT1_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT1_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetGPIO_INT1_MAP_CORE1_GPIO_INT1_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT1_MAP.Reg) & 0x3f
}

// CORE1.GPIO_INT2_MAP: NA
func (o *CORE1_Type) SetGPIO_INT2_MAP_CORE1_GPIO_INT2_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT2_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetGPIO_INT2_MAP_CORE1_GPIO_INT2_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT2_MAP.Reg) & 0x3f
}

// CORE1.GPIO_INT3_MAP: NA
func (o *CORE1_Type) SetGPIO_INT3_MAP_CORE1_GPIO_INT3_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_INT3_MAP.Reg, volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetGPIO_INT3_MAP_CORE1_GPIO_INT3_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_INT3_MAP.Reg) & 0x3f
}

// CORE1.GPIO_PAD_COMP_INT_MAP: NA
func (o *CORE1_Type) SetGPIO_PAD_COMP_INT_MAP_CORE1_GPIO_PAD_COMP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg, volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetGPIO_PAD_COMP_INT_MAP_CORE1_GPIO_PAD_COMP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.GPIO_PAD_COMP_INT_MAP.Reg) & 0x3f
}

// CORE1.CPU_INT_FROM_CPU_0_MAP: NA
func (o *CORE1_Type) SetCPU_INT_FROM_CPU_0_MAP_CORE1_CPU_INT_FROM_CPU_0_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCPU_INT_FROM_CPU_0_MAP_CORE1_CPU_INT_FROM_CPU_0_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_0_MAP.Reg) & 0x3f
}

// CORE1.CPU_INT_FROM_CPU_1_MAP: NA
func (o *CORE1_Type) SetCPU_INT_FROM_CPU_1_MAP_CORE1_CPU_INT_FROM_CPU_1_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCPU_INT_FROM_CPU_1_MAP_CORE1_CPU_INT_FROM_CPU_1_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_1_MAP.Reg) & 0x3f
}

// CORE1.CPU_INT_FROM_CPU_2_MAP: NA
func (o *CORE1_Type) SetCPU_INT_FROM_CPU_2_MAP_CORE1_CPU_INT_FROM_CPU_2_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCPU_INT_FROM_CPU_2_MAP_CORE1_CPU_INT_FROM_CPU_2_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_2_MAP.Reg) & 0x3f
}

// CORE1.CPU_INT_FROM_CPU_3_MAP: NA
func (o *CORE1_Type) SetCPU_INT_FROM_CPU_3_MAP_CORE1_CPU_INT_FROM_CPU_3_MAP(value uint32) {
	volatile.StoreUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg, volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCPU_INT_FROM_CPU_3_MAP_CORE1_CPU_INT_FROM_CPU_3_MAP() uint32 {
	return volatile.LoadUint32(&o.CPU_INT_FROM_CPU_3_MAP.Reg) & 0x3f
}

// CORE1.CACHE_INT_MAP: NA
func (o *CORE1_Type) SetCACHE_INT_MAP_CORE1_CACHE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CACHE_INT_MAP.Reg, volatile.LoadUint32(&o.CACHE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCACHE_INT_MAP_CORE1_CACHE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CACHE_INT_MAP.Reg) & 0x3f
}

// CORE1.FLASH_MSPI_INT_MAP: NA
func (o *CORE1_Type) SetFLASH_MSPI_INT_MAP_CORE1_FLASH_MSPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.FLASH_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetFLASH_MSPI_INT_MAP_CORE1_FLASH_MSPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.FLASH_MSPI_INT_MAP.Reg) & 0x3f
}

// CORE1.CSI_BRIDGE_INT_MAP: NA
func (o *CORE1_Type) SetCSI_BRIDGE_INT_MAP_CORE1_CSI_BRIDGE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCSI_BRIDGE_INT_MAP_CORE1_CSI_BRIDGE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CSI_BRIDGE_INT_MAP.Reg) & 0x3f
}

// CORE1.DSI_BRIDGE_INT_MAP: NA
func (o *CORE1_Type) SetDSI_BRIDGE_INT_MAP_CORE1_DSI_BRIDGE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DSI_BRIDGE_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetDSI_BRIDGE_INT_MAP_CORE1_DSI_BRIDGE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DSI_BRIDGE_INT_MAP.Reg) & 0x3f
}

// CORE1.CSI_INT_MAP: NA
func (o *CORE1_Type) SetCSI_INT_MAP_CORE1_CSI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CSI_INT_MAP.Reg, volatile.LoadUint32(&o.CSI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCSI_INT_MAP_CORE1_CSI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CSI_INT_MAP.Reg) & 0x3f
}

// CORE1.DSI_INT_MAP: NA
func (o *CORE1_Type) SetDSI_INT_MAP_CORE1_DSI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DSI_INT_MAP.Reg, volatile.LoadUint32(&o.DSI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetDSI_INT_MAP_CORE1_DSI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DSI_INT_MAP.Reg) & 0x3f
}

// CORE1.GMII_PHY_INT_MAP: NA
func (o *CORE1_Type) SetGMII_PHY_INT_MAP_CORE1_GMII_PHY_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.GMII_PHY_INT_MAP.Reg, volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetGMII_PHY_INT_MAP_CORE1_GMII_PHY_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.GMII_PHY_INT_MAP.Reg) & 0x3f
}

// CORE1.LPI_INT_MAP: NA
func (o *CORE1_Type) SetLPI_INT_MAP_CORE1_LPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.LPI_INT_MAP.Reg, volatile.LoadUint32(&o.LPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetLPI_INT_MAP_CORE1_LPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.LPI_INT_MAP.Reg) & 0x3f
}

// CORE1.PMT_INT_MAP: NA
func (o *CORE1_Type) SetPMT_INT_MAP_CORE1_PMT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PMT_INT_MAP.Reg, volatile.LoadUint32(&o.PMT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPMT_INT_MAP_CORE1_PMT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PMT_INT_MAP.Reg) & 0x3f
}

// CORE1.SBD_INT_MAP: NA
func (o *CORE1_Type) SetSBD_INT_MAP_CORE1_SBD_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.SBD_INT_MAP.Reg, volatile.LoadUint32(&o.SBD_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetSBD_INT_MAP_CORE1_SBD_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.SBD_INT_MAP.Reg) & 0x3f
}

// CORE1.USB_OTG_INT_MAP: NA
func (o *CORE1_Type) SetUSB_OTG_INT_MAP_CORE1_USB_OTG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_OTG_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUSB_OTG_INT_MAP_CORE1_USB_OTG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_OTG_INT_MAP.Reg) & 0x3f
}

// CORE1.USB_OTG_ENDP_MULTI_PROC_INT_MAP: NA
func (o *CORE1_Type) SetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUSB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_OTG_ENDP_MULTI_PROC_INT_MAP.Reg) & 0x3f
}

// CORE1.JPEG_INT_MAP: NA
func (o *CORE1_Type) SetJPEG_INT_MAP_CORE1_JPEG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.JPEG_INT_MAP.Reg, volatile.LoadUint32(&o.JPEG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetJPEG_INT_MAP_CORE1_JPEG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.JPEG_INT_MAP.Reg) & 0x3f
}

// CORE1.PPA_INT_MAP: NA
func (o *CORE1_Type) SetPPA_INT_MAP_CORE1_PPA_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PPA_INT_MAP.Reg, volatile.LoadUint32(&o.PPA_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPPA_INT_MAP_CORE1_PPA_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PPA_INT_MAP.Reg) & 0x3f
}

// CORE1.CORE0_TRACE_INT_MAP: NA
func (o *CORE1_Type) SetCORE0_TRACE_INT_MAP_CORE1_CORE0_TRACE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CORE0_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCORE0_TRACE_INT_MAP_CORE1_CORE0_TRACE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CORE0_TRACE_INT_MAP.Reg) & 0x3f
}

// CORE1.CORE1_TRACE_INT_MAP: NA
func (o *CORE1_Type) SetCORE1_TRACE_INT_MAP_CORE1_CORE1_TRACE_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.CORE1_TRACE_INT_MAP.Reg, volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetCORE1_TRACE_INT_MAP_CORE1_CORE1_TRACE_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.CORE1_TRACE_INT_MAP.Reg) & 0x3f
}

// CORE1.HP_CORE_CTRL_INT_MAP: NA
func (o *CORE1_Type) SetHP_CORE_CTRL_INT_MAP_CORE1_HP_CORE_CTRL_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_CORE_CTRL_INT_MAP.Reg, volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetHP_CORE_CTRL_INT_MAP_CORE1_HP_CORE_CTRL_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_CORE_CTRL_INT_MAP.Reg) & 0x3f
}

// CORE1.ISP_INT_MAP: NA
func (o *CORE1_Type) SetISP_INT_MAP_CORE1_ISP_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ISP_INT_MAP.Reg, volatile.LoadUint32(&o.ISP_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetISP_INT_MAP_CORE1_ISP_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ISP_INT_MAP.Reg) & 0x3f
}

// CORE1.I3C_MST_INT_MAP: NA
func (o *CORE1_Type) SetI3C_MST_INT_MAP_CORE1_I3C_MST_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I3C_MST_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetI3C_MST_INT_MAP_CORE1_I3C_MST_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I3C_MST_INT_MAP.Reg) & 0x3f
}

// CORE1.I3C_SLV_INT_MAP: NA
func (o *CORE1_Type) SetI3C_SLV_INT_MAP_CORE1_I3C_SLV_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.I3C_SLV_INT_MAP.Reg, volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetI3C_SLV_INT_MAP_CORE1_I3C_SLV_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.I3C_SLV_INT_MAP.Reg) & 0x3f
}

// CORE1.USB_OTG11_INT_MAP: NA
func (o *CORE1_Type) SetUSB_OTG11_INT_MAP_CORE1_USB_OTG11_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.USB_OTG11_INT_MAP.Reg, volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetUSB_OTG11_INT_MAP_CORE1_USB_OTG11_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.USB_OTG11_INT_MAP.Reg) & 0x3f
}

// CORE1.DMA2D_IN_CH0_INT_MAP: NA
func (o *CORE1_Type) SetDMA2D_IN_CH0_INT_MAP_CORE1_DMA2D_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetDMA2D_IN_CH0_INT_MAP_CORE1_DMA2D_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.DMA2D_IN_CH1_INT_MAP: NA
func (o *CORE1_Type) SetDMA2D_IN_CH1_INT_MAP_CORE1_DMA2D_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetDMA2D_IN_CH1_INT_MAP_CORE1_DMA2D_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.DMA2D_OUT_CH0_INT_MAP: NA
func (o *CORE1_Type) SetDMA2D_OUT_CH0_INT_MAP_CORE1_DMA2D_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetDMA2D_OUT_CH0_INT_MAP_CORE1_DMA2D_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.DMA2D_OUT_CH1_INT_MAP: NA
func (o *CORE1_Type) SetDMA2D_OUT_CH1_INT_MAP_CORE1_DMA2D_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetDMA2D_OUT_CH1_INT_MAP_CORE1_DMA2D_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.DMA2D_OUT_CH2_INT_MAP: NA
func (o *CORE1_Type) SetDMA2D_OUT_CH2_INT_MAP_CORE1_DMA2D_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetDMA2D_OUT_CH2_INT_MAP_CORE1_DMA2D_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE1.PSRAM_MSPI_INT_MAP: NA
func (o *CORE1_Type) SetPSRAM_MSPI_INT_MAP_CORE1_PSRAM_MSPI_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PSRAM_MSPI_INT_MAP.Reg, volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPSRAM_MSPI_INT_MAP_CORE1_PSRAM_MSPI_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PSRAM_MSPI_INT_MAP.Reg) & 0x3f
}

// CORE1.HP_SYSREG_INT_MAP: NA
func (o *CORE1_Type) SetHP_SYSREG_INT_MAP_CORE1_HP_SYSREG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_SYSREG_INT_MAP.Reg, volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetHP_SYSREG_INT_MAP_CORE1_HP_SYSREG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_SYSREG_INT_MAP.Reg) & 0x3f
}

// CORE1.PCNT_INT_MAP: NA
func (o *CORE1_Type) SetPCNT_INT_MAP_CORE1_PCNT_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.PCNT_INT_MAP.Reg, volatile.LoadUint32(&o.PCNT_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetPCNT_INT_MAP_CORE1_PCNT_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.PCNT_INT_MAP.Reg) & 0x3f
}

// CORE1.HP_PAU_INT_MAP: NA
func (o *CORE1_Type) SetHP_PAU_INT_MAP_CORE1_HP_PAU_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_PAU_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetHP_PAU_INT_MAP_CORE1_HP_PAU_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_PAU_INT_MAP.Reg) & 0x3f
}

// CORE1.HP_PARLIO_RX_INT_MAP: NA
func (o *CORE1_Type) SetHP_PARLIO_RX_INT_MAP_CORE1_HP_PARLIO_RX_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_PARLIO_RX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetHP_PARLIO_RX_INT_MAP_CORE1_HP_PARLIO_RX_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_PARLIO_RX_INT_MAP.Reg) & 0x3f
}

// CORE1.HP_PARLIO_TX_INT_MAP: NA
func (o *CORE1_Type) SetHP_PARLIO_TX_INT_MAP_CORE1_HP_PARLIO_TX_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.HP_PARLIO_TX_INT_MAP.Reg, volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetHP_PARLIO_TX_INT_MAP_CORE1_HP_PARLIO_TX_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.HP_PARLIO_TX_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_OUT_CH0_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_OUT_CH0_INT_MAP_CORE1_H264_DMA2D_OUT_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_OUT_CH0_INT_MAP_CORE1_H264_DMA2D_OUT_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_OUT_CH1_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_OUT_CH1_INT_MAP_CORE1_H264_DMA2D_OUT_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_OUT_CH1_INT_MAP_CORE1_H264_DMA2D_OUT_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_OUT_CH2_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_OUT_CH2_INT_MAP_CORE1_H264_DMA2D_OUT_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_OUT_CH2_INT_MAP_CORE1_H264_DMA2D_OUT_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH2_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_OUT_CH3_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_OUT_CH3_INT_MAP_CORE1_H264_DMA2D_OUT_CH3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_OUT_CH3_INT_MAP_CORE1_H264_DMA2D_OUT_CH3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH3_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_OUT_CH4_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_OUT_CH4_INT_MAP_CORE1_H264_DMA2D_OUT_CH4_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_OUT_CH4_INT_MAP_CORE1_H264_DMA2D_OUT_CH4_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_OUT_CH4_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_IN_CH0_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_IN_CH0_INT_MAP_CORE1_H264_DMA2D_IN_CH0_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_IN_CH0_INT_MAP_CORE1_H264_DMA2D_IN_CH0_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH0_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_IN_CH1_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_IN_CH1_INT_MAP_CORE1_H264_DMA2D_IN_CH1_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_IN_CH1_INT_MAP_CORE1_H264_DMA2D_IN_CH1_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH1_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_IN_CH2_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_IN_CH2_INT_MAP_CORE1_H264_DMA2D_IN_CH2_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_IN_CH2_INT_MAP_CORE1_H264_DMA2D_IN_CH2_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH2_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_IN_CH3_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_IN_CH3_INT_MAP_CORE1_H264_DMA2D_IN_CH3_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_IN_CH3_INT_MAP_CORE1_H264_DMA2D_IN_CH3_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH3_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_IN_CH4_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_IN_CH4_INT_MAP_CORE1_H264_DMA2D_IN_CH4_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_IN_CH4_INT_MAP_CORE1_H264_DMA2D_IN_CH4_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH4_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_DMA2D_IN_CH5_INT_MAP: NA
func (o *CORE1_Type) SetH264_DMA2D_IN_CH5_INT_MAP_CORE1_H264_DMA2D_IN_CH5_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg, volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_DMA2D_IN_CH5_INT_MAP_CORE1_H264_DMA2D_IN_CH5_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_DMA2D_IN_CH5_INT_MAP.Reg) & 0x3f
}

// CORE1.H264_REG_INT_MAP: NA
func (o *CORE1_Type) SetH264_REG_INT_MAP_CORE1_H264_REG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.H264_REG_INT_MAP.Reg, volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetH264_REG_INT_MAP_CORE1_H264_REG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.H264_REG_INT_MAP.Reg) & 0x3f
}

// CORE1.ASSIST_DEBUG_INT_MAP: NA
func (o *CORE1_Type) SetASSIST_DEBUG_INT_MAP_CORE1_ASSIST_DEBUG_INT_MAP(value uint32) {
	volatile.StoreUint32(&o.ASSIST_DEBUG_INT_MAP.Reg, volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg)&^(0x3f)|value)
}
func (o *CORE1_Type) GetASSIST_DEBUG_INT_MAP_CORE1_ASSIST_DEBUG_INT_MAP() uint32 {
	return volatile.LoadUint32(&o.ASSIST_DEBUG_INT_MAP.Reg) & 0x3f
}

// CORE1.INTR_STATUS_REG_0: NA
func (o *CORE1_Type) SetINTR_STATUS_REG_0(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_0.Reg, value)
}
func (o *CORE1_Type) GetINTR_STATUS_REG_0() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_0.Reg)
}

// CORE1.INTR_STATUS_REG_1: NA
func (o *CORE1_Type) SetINTR_STATUS_REG_1(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_1.Reg, value)
}
func (o *CORE1_Type) GetINTR_STATUS_REG_1() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_1.Reg)
}

// CORE1.INTR_STATUS_REG_2: NA
func (o *CORE1_Type) SetINTR_STATUS_REG_2(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_2.Reg, value)
}
func (o *CORE1_Type) GetINTR_STATUS_REG_2() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_2.Reg)
}

// CORE1.INTR_STATUS_REG_3: NA
func (o *CORE1_Type) SetINTR_STATUS_REG_3(value uint32) {
	volatile.StoreUint32(&o.INTR_STATUS_REG_3.Reg, value)
}
func (o *CORE1_Type) GetINTR_STATUS_REG_3() uint32 {
	return volatile.LoadUint32(&o.INTR_STATUS_REG_3.Reg)
}

// CORE1.CLOCK_GATE: NA
func (o *CORE1_Type) SetCLOCK_GATE_CORE1_REG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *CORE1_Type) GetCLOCK_GATE_CORE1_REG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1
}

// CORE1.INTERRUPT_REG_DATE: NA
func (o *CORE1_Type) SetINTERRUPT_REG_DATE_CORE1_INTERRUPT_REG_DATE(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_REG_DATE.Reg, volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg)&^(0xfffffff)|value)
}
func (o *CORE1_Type) GetINTERRUPT_REG_DATE_CORE1_INTERRUPT_REG_DATE() uint32 {
	return volatile.LoadUint32(&o.INTERRUPT_REG_DATE.Reg) & 0xfffffff
}

// MIPI Camera Interface Bridge
type CSI_BRIG_Type struct {
	CLK_EN           volatile.Register32 // 0x0
	CSI_EN           volatile.Register32 // 0x4
	DMA_REQ_CFG      volatile.Register32 // 0x8
	BUF_FLOW_CTL     volatile.Register32 // 0xC
	DATA_TYPE_CFG    volatile.Register32 // 0x10
	FRAME_CFG        volatile.Register32 // 0x14
	ENDIAN_MODE      volatile.Register32 // 0x18
	INT_RAW          volatile.Register32 // 0x1C
	INT_CLR          volatile.Register32 // 0x20
	INT_ST           volatile.Register32 // 0x24
	INT_ENA          volatile.Register32 // 0x28
	DMA_REQ_INTERVAL volatile.Register32 // 0x2C
	DMABLK_SIZE      volatile.Register32 // 0x30
	RDN_ECO_CS       volatile.Register32 // 0x34
	RDN_ECO_LOW      volatile.Register32 // 0x38
	RDN_ECO_HIGH     volatile.Register32 // 0x3C
	HOST_CTRL        volatile.Register32 // 0x40
	MEM_CTRL         volatile.Register32 // 0x44
}

// CSI_BRIG.CLK_EN: csi bridge register mapping unit clock gating.
func (o *CSI_BRIG_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetCLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1
}

// CSI_BRIG.CSI_EN: csi bridge enable.
func (o *CSI_BRIG_Type) SetCSI_EN_CSI_BRIG_EN(value uint32) {
	volatile.StoreUint32(&o.CSI_EN.Reg, volatile.LoadUint32(&o.CSI_EN.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetCSI_EN_CSI_BRIG_EN() uint32 {
	return volatile.LoadUint32(&o.CSI_EN.Reg) & 0x1
}

// CSI_BRIG.DMA_REQ_CFG: dma request configuration.
func (o *CSI_BRIG_Type) SetDMA_REQ_CFG_DMA_BURST_LEN(value uint32) {
	volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0xfff)|value)
}
func (o *CSI_BRIG_Type) GetDMA_REQ_CFG_DMA_BURST_LEN() uint32 {
	return volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0xfff
}
func (o *CSI_BRIG_Type) SetDMA_REQ_CFG_DMA_CFG_UPD_BY_BLK(value uint32) {
	volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_BRIG_Type) GetDMA_REQ_CFG_DMA_CFG_UPD_BY_BLK() uint32 {
	return (volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0x1000) >> 12
}
func (o *CSI_BRIG_Type) SetDMA_REQ_CFG_DMA_FORCE_RD_STATUS(value uint32) {
	volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_BRIG_Type) GetDMA_REQ_CFG_DMA_FORCE_RD_STATUS() uint32 {
	return (volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0x10000) >> 16
}

// CSI_BRIG.BUF_FLOW_CTL: csi bridge buffer control.
func (o *CSI_BRIG_Type) SetBUF_FLOW_CTL_CSI_BUF_AFULL_THRD(value uint32) {
	volatile.StoreUint32(&o.BUF_FLOW_CTL.Reg, volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg)&^(0x3fff)|value)
}
func (o *CSI_BRIG_Type) GetBUF_FLOW_CTL_CSI_BUF_AFULL_THRD() uint32 {
	return volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg) & 0x3fff
}
func (o *CSI_BRIG_Type) SetBUF_FLOW_CTL_CSI_BUF_DEPTH(value uint32) {
	volatile.StoreUint32(&o.BUF_FLOW_CTL.Reg, volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg)&^(0x3fff0000)|value<<16)
}
func (o *CSI_BRIG_Type) GetBUF_FLOW_CTL_CSI_BUF_DEPTH() uint32 {
	return (volatile.LoadUint32(&o.BUF_FLOW_CTL.Reg) & 0x3fff0000) >> 16
}

// CSI_BRIG.DATA_TYPE_CFG: pixel data type configuration.
func (o *CSI_BRIG_Type) SetDATA_TYPE_CFG_DATA_TYPE_MIN(value uint32) {
	volatile.StoreUint32(&o.DATA_TYPE_CFG.Reg, volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg)&^(0x3f)|value)
}
func (o *CSI_BRIG_Type) GetDATA_TYPE_CFG_DATA_TYPE_MIN() uint32 {
	return volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg) & 0x3f
}
func (o *CSI_BRIG_Type) SetDATA_TYPE_CFG_DATA_TYPE_MAX(value uint32) {
	volatile.StoreUint32(&o.DATA_TYPE_CFG.Reg, volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg)&^(0x3f00)|value<<8)
}
func (o *CSI_BRIG_Type) GetDATA_TYPE_CFG_DATA_TYPE_MAX() uint32 {
	return (volatile.LoadUint32(&o.DATA_TYPE_CFG.Reg) & 0x3f00) >> 8
}

// CSI_BRIG.FRAME_CFG: frame configuration.
func (o *CSI_BRIG_Type) SetFRAME_CFG_VADR_NUM(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff)|value)
}
func (o *CSI_BRIG_Type) GetFRAME_CFG_VADR_NUM() uint32 {
	return volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff
}
func (o *CSI_BRIG_Type) SetFRAME_CFG_HADR_NUM(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff000)|value<<12)
}
func (o *CSI_BRIG_Type) GetFRAME_CFG_HADR_NUM() uint32 {
	return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff000) >> 12
}
func (o *CSI_BRIG_Type) SetFRAME_CFG_HAS_HSYNC_E(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *CSI_BRIG_Type) GetFRAME_CFG_HAS_HSYNC_E() uint32 {
	return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x1000000) >> 24
}
func (o *CSI_BRIG_Type) SetFRAME_CFG_VADR_NUM_CHECK(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x2000000)|value<<25)
}
func (o *CSI_BRIG_Type) GetFRAME_CFG_VADR_NUM_CHECK() uint32 {
	return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x2000000) >> 25
}

// CSI_BRIG.ENDIAN_MODE: data endianness order configuration.
func (o *CSI_BRIG_Type) SetENDIAN_MODE_BYTE_ENDIAN_ORDER(value uint32) {
	volatile.StoreUint32(&o.ENDIAN_MODE.Reg, volatile.LoadUint32(&o.ENDIAN_MODE.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetENDIAN_MODE_BYTE_ENDIAN_ORDER() uint32 {
	return volatile.LoadUint32(&o.ENDIAN_MODE.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetENDIAN_MODE_BIT_ENDIAN_ORDER(value uint32) {
	volatile.StoreUint32(&o.ENDIAN_MODE.Reg, volatile.LoadUint32(&o.ENDIAN_MODE.Reg)&^(0x2)|value<<1)
}
func (o *CSI_BRIG_Type) GetENDIAN_MODE_BIT_ENDIAN_ORDER() uint32 {
	return (volatile.LoadUint32(&o.ENDIAN_MODE.Reg) & 0x2) >> 1
}

// CSI_BRIG.INT_RAW: csi bridge interrupt raw.
func (o *CSI_BRIG_Type) SetINT_RAW_VADR_NUM_GT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetINT_RAW_VADR_NUM_GT_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetINT_RAW_VADR_NUM_LT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *CSI_BRIG_Type) GetINT_RAW_VADR_NUM_LT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *CSI_BRIG_Type) SetINT_RAW_DISCARD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *CSI_BRIG_Type) GetINT_RAW_DISCARD_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *CSI_BRIG_Type) SetINT_RAW_CSI_BUF_OVERRUN_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *CSI_BRIG_Type) GetINT_RAW_CSI_BUF_OVERRUN_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *CSI_BRIG_Type) SetINT_RAW_CSI_ASYNC_FIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *CSI_BRIG_Type) GetINT_RAW_CSI_ASYNC_FIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *CSI_BRIG_Type) SetINT_RAW_DMA_CFG_HAS_UPDATED_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *CSI_BRIG_Type) GetINT_RAW_DMA_CFG_HAS_UPDATED_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}

// CSI_BRIG.INT_CLR: csi bridge interrupt clr.
func (o *CSI_BRIG_Type) SetINT_CLR_VADR_NUM_GT_REAL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetINT_CLR_VADR_NUM_GT_REAL_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetINT_CLR_VADR_NUM_LT_REAL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *CSI_BRIG_Type) GetINT_CLR_VADR_NUM_LT_REAL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *CSI_BRIG_Type) SetINT_CLR_DISCARD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *CSI_BRIG_Type) GetINT_CLR_DISCARD_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *CSI_BRIG_Type) SetINT_CLR_CSI_BUF_OVERRUN_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *CSI_BRIG_Type) GetINT_CLR_CSI_BUF_OVERRUN_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *CSI_BRIG_Type) SetINT_CLR_CSI_ASYNC_FIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *CSI_BRIG_Type) GetINT_CLR_CSI_ASYNC_FIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *CSI_BRIG_Type) SetINT_CLR_DMA_CFG_HAS_UPDATED_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *CSI_BRIG_Type) GetINT_CLR_DMA_CFG_HAS_UPDATED_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}

// CSI_BRIG.INT_ST: csi bridge interrupt st.
func (o *CSI_BRIG_Type) SetINT_ST_VADR_NUM_GT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetINT_ST_VADR_NUM_GT_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetINT_ST_VADR_NUM_LT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *CSI_BRIG_Type) GetINT_ST_VADR_NUM_LT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *CSI_BRIG_Type) SetINT_ST_DISCARD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *CSI_BRIG_Type) GetINT_ST_DISCARD_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *CSI_BRIG_Type) SetINT_ST_CSI_BUF_OVERRUN_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *CSI_BRIG_Type) GetINT_ST_CSI_BUF_OVERRUN_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *CSI_BRIG_Type) SetINT_ST_CSI_ASYNC_FIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *CSI_BRIG_Type) GetINT_ST_CSI_ASYNC_FIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *CSI_BRIG_Type) SetINT_ST_DMA_CFG_HAS_UPDATED_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *CSI_BRIG_Type) GetINT_ST_DMA_CFG_HAS_UPDATED_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}

// CSI_BRIG.INT_ENA: csi bridge interrupt enable.
func (o *CSI_BRIG_Type) SetINT_ENA_VADR_NUM_GT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetINT_ENA_VADR_NUM_GT_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetINT_ENA_VADR_NUM_LT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *CSI_BRIG_Type) GetINT_ENA_VADR_NUM_LT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *CSI_BRIG_Type) SetINT_ENA_DISCARD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *CSI_BRIG_Type) GetINT_ENA_DISCARD_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *CSI_BRIG_Type) SetINT_ENA_CSI_BUF_OVERRUN_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *CSI_BRIG_Type) GetINT_ENA_CSI_BUF_OVERRUN_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *CSI_BRIG_Type) SetINT_ENA_CSI_ASYNC_FIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *CSI_BRIG_Type) GetINT_ENA_CSI_ASYNC_FIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *CSI_BRIG_Type) SetINT_ENA_DMA_CFG_HAS_UPDATED_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *CSI_BRIG_Type) GetINT_ENA_DMA_CFG_HAS_UPDATED_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}

// CSI_BRIG.DMA_REQ_INTERVAL: DMA interval configuration.
func (o *CSI_BRIG_Type) SetDMA_REQ_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.DMA_REQ_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg)&^(0xffff)|value)
}
func (o *CSI_BRIG_Type) GetDMA_REQ_INTERVAL() uint32 {
	return volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg) & 0xffff
}

// CSI_BRIG.DMABLK_SIZE: DMA block size configuration.
func (o *CSI_BRIG_Type) SetDMABLK_SIZE(value uint32) {
	volatile.StoreUint32(&o.DMABLK_SIZE.Reg, volatile.LoadUint32(&o.DMABLK_SIZE.Reg)&^(0x1fff)|value)
}
func (o *CSI_BRIG_Type) GetDMABLK_SIZE() uint32 {
	return volatile.LoadUint32(&o.DMABLK_SIZE.Reg) & 0x1fff
}

// CSI_BRIG.RDN_ECO_CS: N/A
func (o *CSI_BRIG_Type) SetRDN_ECO_CS_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetRDN_ECO_CS_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetRDN_ECO_CS_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *CSI_BRIG_Type) GetRDN_ECO_CS_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1
}

// CSI_BRIG.RDN_ECO_LOW: N/A
func (o *CSI_BRIG_Type) SetRDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value)
}
func (o *CSI_BRIG_Type) GetRDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg)
}

// CSI_BRIG.RDN_ECO_HIGH: N/A
func (o *CSI_BRIG_Type) SetRDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value)
}
func (o *CSI_BRIG_Type) GetRDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg)
}

// CSI_BRIG.HOST_CTRL: csi host control by csi bridge.
func (o *CSI_BRIG_Type) SetHOST_CTRL_CSI_ENABLECLK(value uint32) {
	volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetHOST_CTRL_CSI_ENABLECLK() uint32 {
	return volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetHOST_CTRL_CSI_CFG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_BRIG_Type) GetHOST_CTRL_CSI_CFG_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x2) >> 1
}
func (o *CSI_BRIG_Type) SetHOST_CTRL_LOOPBK_TEST_EN(value uint32) {
	volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_BRIG_Type) GetHOST_CTRL_LOOPBK_TEST_EN() uint32 {
	return (volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x4) >> 2
}

// CSI_BRIG.MEM_CTRL: csi bridge buffer control.
func (o *CSI_BRIG_Type) SetMEM_CTRL_CSI_BRIDGE_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x1)|value)
}
func (o *CSI_BRIG_Type) GetMEM_CTRL_CSI_BRIDGE_MEM_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x1
}
func (o *CSI_BRIG_Type) SetMEM_CTRL_CSI_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x7ffe)|value<<1)
}
func (o *CSI_BRIG_Type) GetMEM_CTRL_CSI_MEM_AUX_CTRL() uint32 {
	return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x7ffe) >> 1
}

// MIPI Camera Interface Host
type CSI_HOST_Type struct {
	VERSION                     volatile.Register32 // 0x0
	N_LANES                     volatile.Register32 // 0x4
	CSI2_RESETN                 volatile.Register32 // 0x8
	INT_ST_MAIN                 volatile.Register32 // 0xC
	_                           [48]byte
	PHY_SHUTDOWNZ               volatile.Register32 // 0x40
	DPHY_RSTZ                   volatile.Register32 // 0x44
	PHY_RX                      volatile.Register32 // 0x48
	PHY_STOPSTATE               volatile.Register32 // 0x4C
	PHY_TEST_CTRL0              volatile.Register32 // 0x50
	PHY_TEST_CTRL1              volatile.Register32 // 0x54
	_                           [112]byte
	VC_EXTENSION                volatile.Register32 // 0xC8
	PHY_CAL                     volatile.Register32 // 0xCC
	_                           [16]byte
	INT_ST_PHY_FATAL            volatile.Register32 // 0xE0
	INT_MSK_PHY_FATAL           volatile.Register32 // 0xE4
	INT_FORCE_PHY_FATAL         volatile.Register32 // 0xE8
	_                           [4]byte
	INT_ST_PKT_FATAL            volatile.Register32 // 0xF0
	INT_MSK_PKT_FATAL           volatile.Register32 // 0xF4
	INT_FORCE_PKT_FATAL         volatile.Register32 // 0xF8
	_                           [20]byte
	INT_ST_PHY                  volatile.Register32 // 0x110
	INT_MSK_PHY                 volatile.Register32 // 0x114
	INT_FORCE_PHY               volatile.Register32 // 0x118
	_                           [356]byte
	INT_ST_BNDRY_FRAME_FATAL    volatile.Register32 // 0x280
	INT_MSK_BNDRY_FRAME_FATAL   volatile.Register32 // 0x284
	INT_FORCE_BNDRY_FRAME_FATAL volatile.Register32 // 0x288
	_                           [4]byte
	INT_ST_SEQ_FRAME_FATAL      volatile.Register32 // 0x290
	INT_MSK_SEQ_FRAME_FATAL     volatile.Register32 // 0x294
	INT_FORCE_SEQ_FRAME_FATAL   volatile.Register32 // 0x298
	_                           [4]byte
	INT_ST_CRC_FRAME_FATAL      volatile.Register32 // 0x2A0
	INT_MSK_CRC_FRAME_FATAL     volatile.Register32 // 0x2A4
	INT_FORCE_CRC_FRAME_FATAL   volatile.Register32 // 0x2A8
	_                           [4]byte
	INT_ST_PLD_CRC_FATAL        volatile.Register32 // 0x2B0
	INT_MSK_PLD_CRC_FATAL       volatile.Register32 // 0x2B4
	INT_FORCE_PLD_CRC_FATAL     volatile.Register32 // 0x2B8
	_                           [4]byte
	INT_ST_DATA_ID              volatile.Register32 // 0x2C0
	INT_MSK_DATA_ID             volatile.Register32 // 0x2C4
	INT_FORCE_DATA_ID           volatile.Register32 // 0x2C8
	_                           [4]byte
	INT_ST_ECC_CORRECTED        volatile.Register32 // 0x2D0
	INT_MSK_ECC_CORRECTED       volatile.Register32 // 0x2D4
	INT_FORCE_ECC_CORRECTED     volatile.Register32 // 0x2D8
	_                           [36]byte
	SCRAMBLING                  volatile.Register32 // 0x300
	SCRAMBLING_SEED1            volatile.Register32 // 0x304
	SCRAMBLING_SEED2            volatile.Register32 // 0x308
}

// CSI_HOST.VERSION: NA
func (o *CSI_HOST_Type) SetVERSION(value uint32) {
	volatile.StoreUint32(&o.VERSION.Reg, value)
}
func (o *CSI_HOST_Type) GetVERSION() uint32 {
	return volatile.LoadUint32(&o.VERSION.Reg)
}

// CSI_HOST.N_LANES: NA
func (o *CSI_HOST_Type) SetN_LANES(value uint32) {
	volatile.StoreUint32(&o.N_LANES.Reg, volatile.LoadUint32(&o.N_LANES.Reg)&^(0x7)|value)
}
func (o *CSI_HOST_Type) GetN_LANES() uint32 {
	return volatile.LoadUint32(&o.N_LANES.Reg) & 0x7
}

// CSI_HOST.CSI2_RESETN: NA
func (o *CSI_HOST_Type) SetCSI2_RESETN(value uint32) {
	volatile.StoreUint32(&o.CSI2_RESETN.Reg, volatile.LoadUint32(&o.CSI2_RESETN.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetCSI2_RESETN() uint32 {
	return volatile.LoadUint32(&o.CSI2_RESETN.Reg) & 0x1
}

// CSI_HOST.INT_ST_MAIN: NA
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PHY_FATAL(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PHY_FATAL() uint32 {
	return volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PKT_FATAL(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PKT_FATAL() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_BNDRY_FRAME_FATAL(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_BNDRY_FRAME_FATAL() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_SEQ_FRAME_FATAL(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_SEQ_FRAME_FATAL() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_CRC_FRAME_FATAL(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_CRC_FRAME_FATAL() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PLD_CRC_FATAL(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PLD_CRC_FATAL() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_DATA_ID(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_DATA_ID() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_ECC_CORRECTED(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_ECC_CORRECTED() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_ST_MAIN_ST_STATUS_INT_PHY(value uint32) {
	volatile.StoreUint32(&o.INT_ST_MAIN.Reg, volatile.LoadUint32(&o.INT_ST_MAIN.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_HOST_Type) GetINT_ST_MAIN_ST_STATUS_INT_PHY() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_MAIN.Reg) & 0x10000) >> 16
}

// CSI_HOST.PHY_SHUTDOWNZ: NA
func (o *CSI_HOST_Type) SetPHY_SHUTDOWNZ(value uint32) {
	volatile.StoreUint32(&o.PHY_SHUTDOWNZ.Reg, volatile.LoadUint32(&o.PHY_SHUTDOWNZ.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetPHY_SHUTDOWNZ() uint32 {
	return volatile.LoadUint32(&o.PHY_SHUTDOWNZ.Reg) & 0x1
}

// CSI_HOST.DPHY_RSTZ: NA
func (o *CSI_HOST_Type) SetDPHY_RSTZ(value uint32) {
	volatile.StoreUint32(&o.DPHY_RSTZ.Reg, volatile.LoadUint32(&o.DPHY_RSTZ.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetDPHY_RSTZ() uint32 {
	return volatile.LoadUint32(&o.DPHY_RSTZ.Reg) & 0x1
}

// CSI_HOST.PHY_RX: NA
func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXULPSESC_0(value uint32) {
	volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXULPSESC_0() uint32 {
	return volatile.LoadUint32(&o.PHY_RX.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXULPSESC_1(value uint32) {
	volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXULPSESC_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_RX.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXULPSCLKNOT(value uint32) {
	volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXULPSCLKNOT() uint32 {
	return (volatile.LoadUint32(&o.PHY_RX.Reg) & 0x10000) >> 16
}
func (o *CSI_HOST_Type) SetPHY_RX_PHY_RXCLKACTIVEHS(value uint32) {
	volatile.StoreUint32(&o.PHY_RX.Reg, volatile.LoadUint32(&o.PHY_RX.Reg)&^(0x20000)|value<<17)
}
func (o *CSI_HOST_Type) GetPHY_RX_PHY_RXCLKACTIVEHS() uint32 {
	return (volatile.LoadUint32(&o.PHY_RX.Reg) & 0x20000) >> 17
}

// CSI_HOST.PHY_STOPSTATE: NA
func (o *CSI_HOST_Type) SetPHY_STOPSTATE_PHY_STOPSTATEDATA_0(value uint32) {
	volatile.StoreUint32(&o.PHY_STOPSTATE.Reg, volatile.LoadUint32(&o.PHY_STOPSTATE.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetPHY_STOPSTATE_PHY_STOPSTATEDATA_0() uint32 {
	return volatile.LoadUint32(&o.PHY_STOPSTATE.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetPHY_STOPSTATE_PHY_STOPSTATEDATA_1(value uint32) {
	volatile.StoreUint32(&o.PHY_STOPSTATE.Reg, volatile.LoadUint32(&o.PHY_STOPSTATE.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetPHY_STOPSTATE_PHY_STOPSTATEDATA_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_STOPSTATE.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetPHY_STOPSTATE_PHY_STOPSTATECLK(value uint32) {
	volatile.StoreUint32(&o.PHY_STOPSTATE.Reg, volatile.LoadUint32(&o.PHY_STOPSTATE.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_HOST_Type) GetPHY_STOPSTATE_PHY_STOPSTATECLK() uint32 {
	return (volatile.LoadUint32(&o.PHY_STOPSTATE.Reg) & 0x10000) >> 16
}

// CSI_HOST.PHY_TEST_CTRL0: NA
func (o *CSI_HOST_Type) SetPHY_TEST_CTRL0_PHY_TESTCLR(value uint32) {
	volatile.StoreUint32(&o.PHY_TEST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetPHY_TEST_CTRL0_PHY_TESTCLR() uint32 {
	return volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetPHY_TEST_CTRL0_PHY_TESTCLK(value uint32) {
	volatile.StoreUint32(&o.PHY_TEST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetPHY_TEST_CTRL0_PHY_TESTCLK() uint32 {
	return (volatile.LoadUint32(&o.PHY_TEST_CTRL0.Reg) & 0x2) >> 1
}

// CSI_HOST.PHY_TEST_CTRL1: NA
func (o *CSI_HOST_Type) SetPHY_TEST_CTRL1_PHY_TESTDIN(value uint32) {
	volatile.StoreUint32(&o.PHY_TEST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg)&^(0xff)|value)
}
func (o *CSI_HOST_Type) GetPHY_TEST_CTRL1_PHY_TESTDIN() uint32 {
	return volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg) & 0xff
}
func (o *CSI_HOST_Type) SetPHY_TEST_CTRL1_PHY_TESTDOUT(value uint32) {
	volatile.StoreUint32(&o.PHY_TEST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg)&^(0xff00)|value<<8)
}
func (o *CSI_HOST_Type) GetPHY_TEST_CTRL1_PHY_TESTDOUT() uint32 {
	return (volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg) & 0xff00) >> 8
}
func (o *CSI_HOST_Type) SetPHY_TEST_CTRL1_PHY_TESTEN(value uint32) {
	volatile.StoreUint32(&o.PHY_TEST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_HOST_Type) GetPHY_TEST_CTRL1_PHY_TESTEN() uint32 {
	return (volatile.LoadUint32(&o.PHY_TEST_CTRL1.Reg) & 0x10000) >> 16
}

// CSI_HOST.VC_EXTENSION: NA
func (o *CSI_HOST_Type) SetVC_EXTENSION_VCX(value uint32) {
	volatile.StoreUint32(&o.VC_EXTENSION.Reg, volatile.LoadUint32(&o.VC_EXTENSION.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetVC_EXTENSION_VCX() uint32 {
	return volatile.LoadUint32(&o.VC_EXTENSION.Reg) & 0x1
}

// CSI_HOST.PHY_CAL: NA
func (o *CSI_HOST_Type) SetPHY_CAL_RXSKEWCALHS(value uint32) {
	volatile.StoreUint32(&o.PHY_CAL.Reg, volatile.LoadUint32(&o.PHY_CAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetPHY_CAL_RXSKEWCALHS() uint32 {
	return volatile.LoadUint32(&o.PHY_CAL.Reg) & 0x1
}

// CSI_HOST.INT_ST_PHY_FATAL: NA
func (o *CSI_HOST_Type) SetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PHY_FATAL.Reg) & 0x2) >> 1
}

// CSI_HOST.INT_MSK_PHY_FATAL: NA
func (o *CSI_HOST_Type) SetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PHY_FATAL.Reg) & 0x2) >> 1
}

// CSI_HOST.INT_FORCE_PHY_FATAL: NA
func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PHY_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PHY_FATAL.Reg) & 0x2) >> 1
}

// CSI_HOST.INT_ST_PKT_FATAL: NA
func (o *CSI_HOST_Type) SetINT_ST_PKT_FATAL_ST_ERR_ECC_DOUBLE(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_PKT_FATAL_ST_ERR_ECC_DOUBLE() uint32 {
	return volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_PKT_FATAL_ST_SHORTER_PAYLOAD(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_PKT_FATAL_ST_SHORTER_PAYLOAD() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PKT_FATAL.Reg) & 0x2) >> 1
}

// CSI_HOST.INT_MSK_PKT_FATAL: NA
func (o *CSI_HOST_Type) SetINT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_PKT_FATAL_MASK_SHORTER_PAYLOAD(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_PKT_FATAL_MASK_SHORTER_PAYLOAD() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PKT_FATAL.Reg) & 0x2) >> 1
}

// CSI_HOST.INT_FORCE_PKT_FATAL: NA
func (o *CSI_HOST_Type) SetINT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_PKT_FATAL_FORCE_SHORTER_PAYLOAD(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PKT_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PKT_FATAL_FORCE_SHORTER_PAYLOAD() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PKT_FATAL.Reg) & 0x2) >> 1
}

// CSI_HOST.INT_ST_PHY: NA
func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRSOTHS_0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRSOTHS_0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRSOTHS_1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRSOTHS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRESC_0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRESC_0() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x10000) >> 16
}
func (o *CSI_HOST_Type) SetINT_ST_PHY_ST_PHY_ERRESC_1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PHY.Reg, volatile.LoadUint32(&o.INT_ST_PHY.Reg)&^(0x20000)|value<<17)
}
func (o *CSI_HOST_Type) GetINT_ST_PHY_ST_PHY_ERRESC_1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PHY.Reg) & 0x20000) >> 17
}

// CSI_HOST.INT_MSK_PHY: NA
func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRSOTHS_0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRSOTHS_0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRSOTHS_1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRSOTHS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRESC_0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRESC_0() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x10000) >> 16
}
func (o *CSI_HOST_Type) SetINT_MSK_PHY_MASK_PHY_ERRESC_1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PHY.Reg, volatile.LoadUint32(&o.INT_MSK_PHY.Reg)&^(0x20000)|value<<17)
}
func (o *CSI_HOST_Type) GetINT_MSK_PHY_MASK_PHY_ERRESC_1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PHY.Reg) & 0x20000) >> 17
}

// CSI_HOST.INT_FORCE_PHY: NA
func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRESC_0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x10000)|value<<16)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRESC_0() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x10000) >> 16
}
func (o *CSI_HOST_Type) SetINT_FORCE_PHY_FORCE_PHY_ERRESC_1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PHY.Reg, volatile.LoadUint32(&o.INT_FORCE_PHY.Reg)&^(0x20000)|value<<17)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PHY_FORCE_PHY_ERRESC_1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PHY.Reg) & 0x20000) >> 17
}

// CSI_HOST.INT_ST_BNDRY_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_BNDRY_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_MSK_BNDRY_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_BNDRY_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_FORCE_BNDRY_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_BNDRY_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_ST_SEQ_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_SEQ_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_MSK_SEQ_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_SEQ_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_FORCE_SEQ_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_SEQ_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_ST_CRC_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_CRC_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_MSK_CRC_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_CRC_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_FORCE_CRC_FRAME_FATAL: NA
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_CRC_FRAME_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_ST_PLD_CRC_FATAL: NA
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_ST_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_PLD_CRC_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_MSK_PLD_CRC_FATAL: NA
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_PLD_CRC_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_FORCE_PLD_CRC_FATAL: NA
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg, volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_PLD_CRC_FATAL.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_ST_DATA_ID: NA
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_ST_DATA_ID_ST_ERR_ID_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_ST_DATA_ID.Reg, volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_ST_DATA_ID_ST_ERR_ID_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_DATA_ID.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_MSK_DATA_ID: NA
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_MSK_DATA_ID_MASK_ERR_ID_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_DATA_ID.Reg, volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_MSK_DATA_ID_MASK_ERR_ID_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_DATA_ID.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_FORCE_DATA_ID: NA
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_DATA_ID.Reg, volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_FORCE_DATA_ID_FORCE_ERR_ID_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_DATA_ID.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_ST_ECC_CORRECTED: NA
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ECC_CORRECTED.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_MSK_ECC_CORRECTED: NA
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_MSK_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK_ECC_CORRECTED.Reg) & 0x8000) >> 15
}

// CSI_HOST.INT_FORCE_ECC_CORRECTED: NA
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x1
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x2)|value<<1)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x2) >> 1
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x4)|value<<2)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x4) >> 2
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x8)|value<<3)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x8) >> 3
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x10)|value<<4)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x10) >> 4
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC5(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x20)|value<<5)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC5() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x20) >> 5
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC6(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x40)|value<<6)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC6() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x40) >> 6
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC7(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x80)|value<<7)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC7() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x80) >> 7
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC8(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x100)|value<<8)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC8() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x100) >> 8
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC9(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x200)|value<<9)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC9() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x200) >> 9
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC10(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x400)|value<<10)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC10() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x400) >> 10
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC11(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x800)|value<<11)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC11() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x800) >> 11
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC12(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x1000)|value<<12)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC12() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x1000) >> 12
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC13(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x2000)|value<<13)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC13() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x2000) >> 13
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC14(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x4000)|value<<14)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC14() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x4000) >> 14
}
func (o *CSI_HOST_Type) SetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC15(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE_ECC_CORRECTED.Reg, volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg)&^(0x8000)|value<<15)
}
func (o *CSI_HOST_Type) GetINT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC15() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE_ECC_CORRECTED.Reg) & 0x8000) >> 15
}

// CSI_HOST.SCRAMBLING: NA
func (o *CSI_HOST_Type) SetSCRAMBLING_SCRAMBLE_ENABLE(value uint32) {
	volatile.StoreUint32(&o.SCRAMBLING.Reg, volatile.LoadUint32(&o.SCRAMBLING.Reg)&^(0x1)|value)
}
func (o *CSI_HOST_Type) GetSCRAMBLING_SCRAMBLE_ENABLE() uint32 {
	return volatile.LoadUint32(&o.SCRAMBLING.Reg) & 0x1
}

// CSI_HOST.SCRAMBLING_SEED1: NA
func (o *CSI_HOST_Type) SetSCRAMBLING_SEED1_SCRAMBLE_SEED_LANE1(value uint32) {
	volatile.StoreUint32(&o.SCRAMBLING_SEED1.Reg, volatile.LoadUint32(&o.SCRAMBLING_SEED1.Reg)&^(0xffff)|value)
}
func (o *CSI_HOST_Type) GetSCRAMBLING_SEED1_SCRAMBLE_SEED_LANE1() uint32 {
	return volatile.LoadUint32(&o.SCRAMBLING_SEED1.Reg) & 0xffff
}

// CSI_HOST.SCRAMBLING_SEED2: NA
func (o *CSI_HOST_Type) SetSCRAMBLING_SEED2_SCRAMBLE_SEED_LANE2(value uint32) {
	volatile.StoreUint32(&o.SCRAMBLING_SEED2.Reg, volatile.LoadUint32(&o.SCRAMBLING_SEED2.Reg)&^(0xffff)|value)
}
func (o *CSI_HOST_Type) GetSCRAMBLING_SEED2_SCRAMBLE_SEED_LANE2() uint32 {
	return volatile.LoadUint32(&o.SCRAMBLING_SEED2.Reg) & 0xffff
}

// DMA (Direct Memory Access) Controller
type DMAC_Type struct {
	ID0                         volatile.Register32 // 0x0
	_                           [4]byte
	COMPVER0                    volatile.Register32 // 0x8
	_                           [4]byte
	CFG0                        volatile.Register32 // 0x10
	_                           [4]byte
	CHEN0                       volatile.Register32 // 0x18
	CHEN1                       volatile.Register32 // 0x1C
	_                           [16]byte
	INTSTATUS0                  volatile.Register32 // 0x30
	_                           [4]byte
	COMMONREG_INTCLEAR0         volatile.Register32 // 0x38
	_                           [4]byte
	COMMONREG_INTSTATUS_ENABLE0 volatile.Register32 // 0x40
	_                           [4]byte
	COMMONREG_INTSIGNAL_ENABLE0 volatile.Register32 // 0x48
	_                           [4]byte
	COMMONREG_INTSTATUS0        volatile.Register32 // 0x50
	_                           [4]byte
	RESET0                      volatile.Register32 // 0x58
	_                           [4]byte
	LOWPOWER_CFG0               volatile.Register32 // 0x60
	LOWPOWER_CFG1               volatile.Register32 // 0x64
	_                           [152]byte
	CH1_SAR0                    volatile.Register32 // 0x100
	CH1_SAR1                    volatile.Register32 // 0x104
	CH1_DAR0                    volatile.Register32 // 0x108
	CH1_DAR1                    volatile.Register32 // 0x10C
	CH1_BLOCK_TS0               volatile.Register32 // 0x110
	_                           [4]byte
	CH1_CTL0                    volatile.Register32 // 0x118
	CH1_CTL1                    volatile.Register32 // 0x11C
	CH1_CFG0                    volatile.Register32 // 0x120
	CH1_CFG1                    volatile.Register32 // 0x124
	CH1_LLP0                    volatile.Register32 // 0x128
	CH1_LLP1                    volatile.Register32 // 0x12C
	CH1_STATUS0                 volatile.Register32 // 0x130
	CH1_STATUS1                 volatile.Register32 // 0x134
	CH1_SWHSSRC0                volatile.Register32 // 0x138
	_                           [4]byte
	CH1_SWHSDST0                volatile.Register32 // 0x140
	_                           [4]byte
	CH1_BLK_TFR_RESUMEREQ0      volatile.Register32 // 0x148
	_                           [4]byte
	CH1_AXI_ID0                 volatile.Register32 // 0x150
	_                           [4]byte
	CH1_AXI_QOS0                volatile.Register32 // 0x158
	_                           [4]byte
	CH1_SSTAT0                  volatile.Register32 // 0x160
	_                           [4]byte
	CH1_DSTAT0                  volatile.Register32 // 0x168
	_                           [4]byte
	CH1_SSTATAR0                volatile.Register32 // 0x170
	CH1_SSTATAR1                volatile.Register32 // 0x174
	CH1_DSTATAR0                volatile.Register32 // 0x178
	CH1_DSTATAR1                volatile.Register32 // 0x17C
	CH1_INTSTATUS_ENABLE0       volatile.Register32 // 0x180
	CH1_INTSTATUS_ENABLE1       volatile.Register32 // 0x184
	CH1_INTSTATUS0              volatile.Register32 // 0x188
	CH1_INTSTATUS1              volatile.Register32 // 0x18C
	CH1_INTSIGNAL_ENABLE0       volatile.Register32 // 0x190
	CH1_INTSIGNAL_ENABLE1       volatile.Register32 // 0x194
	CH1_INTCLEAR0               volatile.Register32 // 0x198
	CH1_INTCLEAR1               volatile.Register32 // 0x19C
	_                           [96]byte
	CH2_SAR0                    volatile.Register32 // 0x200
	CH2_SAR1                    volatile.Register32 // 0x204
	CH2_DAR0                    volatile.Register32 // 0x208
	CH2_DAR1                    volatile.Register32 // 0x20C
	CH2_BLOCK_TS0               volatile.Register32 // 0x210
	_                           [4]byte
	CH2_CTL0                    volatile.Register32 // 0x218
	CH2_CTL1                    volatile.Register32 // 0x21C
	CH2_CFG0                    volatile.Register32 // 0x220
	CH2_CFG1                    volatile.Register32 // 0x224
	CH2_LLP0                    volatile.Register32 // 0x228
	CH2_LLP1                    volatile.Register32 // 0x22C
	CH2_STATUS0                 volatile.Register32 // 0x230
	CH2_STATUS1                 volatile.Register32 // 0x234
	CH2_SWHSSRC0                volatile.Register32 // 0x238
	_                           [4]byte
	CH2_SWHSDST0                volatile.Register32 // 0x240
	_                           [4]byte
	CH2_BLK_TFR_RESUMEREQ0      volatile.Register32 // 0x248
	_                           [4]byte
	CH2_AXI_ID0                 volatile.Register32 // 0x250
	_                           [4]byte
	CH2_AXI_QOS0                volatile.Register32 // 0x258
	_                           [4]byte
	CH2_SSTAT0                  volatile.Register32 // 0x260
	_                           [4]byte
	CH2_DSTAT0                  volatile.Register32 // 0x268
	_                           [4]byte
	CH2_SSTATAR0                volatile.Register32 // 0x270
	CH2_SSTATAR1                volatile.Register32 // 0x274
	CH2_DSTATAR0                volatile.Register32 // 0x278
	CH2_DSTATAR1                volatile.Register32 // 0x27C
	CH2_INTSTATUS_ENABLE0       volatile.Register32 // 0x280
	CH2_INTSTATUS_ENABLE1       volatile.Register32 // 0x284
	CH2_INTSTATUS0              volatile.Register32 // 0x288
	CH2_INTSTATUS1              volatile.Register32 // 0x28C
	CH2_INTSIGNAL_ENABLE0       volatile.Register32 // 0x290
	CH2_INTSIGNAL_ENABLE1       volatile.Register32 // 0x294
	CH2_INTCLEAR0               volatile.Register32 // 0x298
	CH2_INTCLEAR1               volatile.Register32 // 0x29C
	_                           [96]byte
	CH3_SAR0                    volatile.Register32 // 0x300
	CH3_SAR1                    volatile.Register32 // 0x304
	CH3_DAR0                    volatile.Register32 // 0x308
	CH3_DAR1                    volatile.Register32 // 0x30C
	CH3_BLOCK_TS0               volatile.Register32 // 0x310
	_                           [4]byte
	CH3_CTL0                    volatile.Register32 // 0x318
	CH3_CTL1                    volatile.Register32 // 0x31C
	CH3_CFG0                    volatile.Register32 // 0x320
	CH3_CFG1                    volatile.Register32 // 0x324
	CH3_LLP0                    volatile.Register32 // 0x328
	CH3_LLP1                    volatile.Register32 // 0x32C
	CH3_STATUS0                 volatile.Register32 // 0x330
	CH3_STATUS1                 volatile.Register32 // 0x334
	CH3_SWHSSRC0                volatile.Register32 // 0x338
	_                           [4]byte
	CH3_SWHSDST0                volatile.Register32 // 0x340
	_                           [4]byte
	CH3_BLK_TFR_RESUMEREQ0      volatile.Register32 // 0x348
	_                           [4]byte
	CH3_AXI_ID0                 volatile.Register32 // 0x350
	_                           [4]byte
	CH3_AXI_QOS0                volatile.Register32 // 0x358
	_                           [4]byte
	CH3_SSTAT0                  volatile.Register32 // 0x360
	_                           [4]byte
	CH3_DSTAT0                  volatile.Register32 // 0x368
	_                           [4]byte
	CH3_SSTATAR0                volatile.Register32 // 0x370
	CH3_SSTATAR1                volatile.Register32 // 0x374
	CH3_DSTATAR0                volatile.Register32 // 0x378
	CH3_DSTATAR1                volatile.Register32 // 0x37C
	CH3_INTSTATUS_ENABLE0       volatile.Register32 // 0x380
	CH3_INTSTATUS_ENABLE1       volatile.Register32 // 0x384
	CH3_INTSTATUS0              volatile.Register32 // 0x388
	CH3_INTSTATUS1              volatile.Register32 // 0x38C
	CH3_INTSIGNAL_ENABLE0       volatile.Register32 // 0x390
	CH3_INTSIGNAL_ENABLE1       volatile.Register32 // 0x394
	CH3_INTCLEAR0               volatile.Register32 // 0x398
	CH3_INTCLEAR1               volatile.Register32 // 0x39C
	_                           [96]byte
	CH4_SAR0                    volatile.Register32 // 0x400
	CH4_SAR1                    volatile.Register32 // 0x404
	CH4_DAR0                    volatile.Register32 // 0x408
	CH4_DAR1                    volatile.Register32 // 0x40C
	CH4_BLOCK_TS0               volatile.Register32 // 0x410
	_                           [4]byte
	CH4_CTL0                    volatile.Register32 // 0x418
	CH4_CTL1                    volatile.Register32 // 0x41C
	CH4_CFG0                    volatile.Register32 // 0x420
	CH4_CFG1                    volatile.Register32 // 0x424
	CH4_LLP0                    volatile.Register32 // 0x428
	CH4_LLP1                    volatile.Register32 // 0x42C
	CH4_STATUS0                 volatile.Register32 // 0x430
	CH4_STATUS1                 volatile.Register32 // 0x434
	CH4_SWHSSRC0                volatile.Register32 // 0x438
	_                           [4]byte
	CH4_SWHSDST0                volatile.Register32 // 0x440
	_                           [4]byte
	CH4_BLK_TFR_RESUMEREQ0      volatile.Register32 // 0x448
	_                           [4]byte
	CH4_AXI_ID0                 volatile.Register32 // 0x450
	_                           [4]byte
	CH4_AXI_QOS0                volatile.Register32 // 0x458
	_                           [4]byte
	CH4_SSTAT0                  volatile.Register32 // 0x460
	_                           [4]byte
	CH4_DSTAT0                  volatile.Register32 // 0x468
	_                           [4]byte
	CH4_SSTATAR0                volatile.Register32 // 0x470
	CH4_SSTATAR1                volatile.Register32 // 0x474
	CH4_DSTATAR0                volatile.Register32 // 0x478
	CH4_DSTATAR1                volatile.Register32 // 0x47C
	CH4_INTSTATUS_ENABLE0       volatile.Register32 // 0x480
	CH4_INTSTATUS_ENABLE1       volatile.Register32 // 0x484
	CH4_INTSTATUS0              volatile.Register32 // 0x488
	CH4_INTSTATUS1              volatile.Register32 // 0x48C
	CH4_INTSIGNAL_ENABLE0       volatile.Register32 // 0x490
	CH4_INTSIGNAL_ENABLE1       volatile.Register32 // 0x494
	CH4_INTCLEAR0               volatile.Register32 // 0x498
	CH4_INTCLEAR1               volatile.Register32 // 0x49C
}

// DMAC.ID0: NA
func (o *DMAC_Type) SetID0(value uint32) {
	volatile.StoreUint32(&o.ID0.Reg, value)
}
func (o *DMAC_Type) GetID0() uint32 {
	return volatile.LoadUint32(&o.ID0.Reg)
}

// DMAC.COMPVER0: NA
func (o *DMAC_Type) SetCOMPVER0(value uint32) {
	volatile.StoreUint32(&o.COMPVER0.Reg, value)
}
func (o *DMAC_Type) GetCOMPVER0() uint32 {
	return volatile.LoadUint32(&o.COMPVER0.Reg)
}

// DMAC.CFG0: NA
func (o *DMAC_Type) SetCFG0_DMAC_EN(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCFG0_DMAC_EN() uint32 {
	return volatile.LoadUint32(&o.CFG0.Reg) & 0x1
}
func (o *DMAC_Type) SetCFG0_INT_EN(value uint32) {
	volatile.StoreUint32(&o.CFG0.Reg, volatile.LoadUint32(&o.CFG0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCFG0_INT_EN() uint32 {
	return (volatile.LoadUint32(&o.CFG0.Reg) & 0x2) >> 1
}

// DMAC.CHEN0: NA
func (o *DMAC_Type) SetCHEN0_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCHEN0_CH1_EN() uint32 {
	return volatile.LoadUint32(&o.CHEN0.Reg) & 0x1
}
func (o *DMAC_Type) SetCHEN0_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCHEN0_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCHEN0_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCHEN0_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCHEN0_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCHEN0_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCHEN0_CH1_EN_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCHEN0_CH1_EN_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCHEN0_CH2_EN_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCHEN0_CH2_EN_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCHEN0_CH3_EN_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCHEN0_CH3_EN_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCHEN0_CH4_EN_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCHEN0_CH4_EN_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCHEN0_CH1_SUSP(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCHEN0_CH1_SUSP() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCHEN0_CH2_SUSP(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCHEN0_CH2_SUSP() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCHEN0_CH3_SUSP(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCHEN0_CH3_SUSP() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCHEN0_CH4_SUSP(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCHEN0_CH4_SUSP() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCHEN0_CH1_SUSP_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x1000000)|value<<24)
}
func (o *DMAC_Type) GetCHEN0_CH1_SUSP_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x1000000) >> 24
}
func (o *DMAC_Type) SetCHEN0_CH2_SUSP_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCHEN0_CH2_SUSP_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCHEN0_CH3_SUSP_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x4000000)|value<<26)
}
func (o *DMAC_Type) GetCHEN0_CH3_SUSP_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x4000000) >> 26
}
func (o *DMAC_Type) SetCHEN0_CH4_SUSP_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN0.Reg, volatile.LoadUint32(&o.CHEN0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCHEN0_CH4_SUSP_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN0.Reg) & 0x8000000) >> 27
}

// DMAC.CHEN1: NA
func (o *DMAC_Type) SetCHEN1_CH1_ABORT(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCHEN1_CH1_ABORT() uint32 {
	return volatile.LoadUint32(&o.CHEN1.Reg) & 0x1
}
func (o *DMAC_Type) SetCHEN1_CH2_ABORT(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCHEN1_CH2_ABORT() uint32 {
	return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCHEN1_CH3_ABORT(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCHEN1_CH3_ABORT() uint32 {
	return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCHEN1_CH4_ABORT(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCHEN1_CH4_ABORT() uint32 {
	return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCHEN1_CH1_ABORT_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCHEN1_CH1_ABORT_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCHEN1_CH2_ABORT_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCHEN1_CH2_ABORT_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCHEN1_CH3_ABORT_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCHEN1_CH3_ABORT_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCHEN1_CH4_ABORT_WE(value uint32) {
	volatile.StoreUint32(&o.CHEN1.Reg, volatile.LoadUint32(&o.CHEN1.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCHEN1_CH4_ABORT_WE() uint32 {
	return (volatile.LoadUint32(&o.CHEN1.Reg) & 0x800) >> 11
}

// DMAC.INTSTATUS0: NA
func (o *DMAC_Type) SetINTSTATUS0_CH1_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetINTSTATUS0_CH1_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x1
}
func (o *DMAC_Type) SetINTSTATUS0_CH2_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetINTSTATUS0_CH2_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetINTSTATUS0_CH3_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetINTSTATUS0_CH3_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetINTSTATUS0_CH4_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetINTSTATUS0_CH4_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetINTSTATUS0_COMMONREG_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.INTSTATUS0.Reg, volatile.LoadUint32(&o.INTSTATUS0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetINTSTATUS0_COMMONREG_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.INTSTATUS0.Reg) & 0x10000) >> 16
}

// DMAC.COMMONREG_INTCLEAR0: NA
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x1
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTCLEAR0.Reg, volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCOMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTCLEAR0.Reg) & 0x100000) >> 20
}

// DMAC.COMMONREG_INTSTATUS_ENABLE0: NA
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20
}

// DMAC.COMMONREG_INTSIGNAL_ENABLE0: NA
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCOMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20
}

// DMAC.COMMONREG_INTSTATUS0: NA
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_DEC_ERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x1
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.COMMONREG_INTSTATUS0.Reg, volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCOMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.COMMONREG_INTSTATUS0.Reg) & 0x100000) >> 20
}

// DMAC.RESET0: NA
func (o *DMAC_Type) SetRESET0_DMAC_RST(value uint32) {
	volatile.StoreUint32(&o.RESET0.Reg, volatile.LoadUint32(&o.RESET0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetRESET0_DMAC_RST() uint32 {
	return volatile.LoadUint32(&o.RESET0.Reg) & 0x1
}

// DMAC.LOWPOWER_CFG0: NA
func (o *DMAC_Type) SetLOWPOWER_CFG0_GBL_CSLP_EN(value uint32) {
	volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetLOWPOWER_CFG0_GBL_CSLP_EN() uint32 {
	return volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x1
}
func (o *DMAC_Type) SetLOWPOWER_CFG0_CHNL_CSLP_EN(value uint32) {
	volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetLOWPOWER_CFG0_CHNL_CSLP_EN() uint32 {
	return (volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetLOWPOWER_CFG0_SBIU_CSLP_EN(value uint32) {
	volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetLOWPOWER_CFG0_SBIU_CSLP_EN() uint32 {
	return (volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetLOWPOWER_CFG0_MXIF_CSLP_EN(value uint32) {
	volatile.StoreUint32(&o.LOWPOWER_CFG0.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetLOWPOWER_CFG0_MXIF_CSLP_EN() uint32 {
	return (volatile.LoadUint32(&o.LOWPOWER_CFG0.Reg) & 0x8) >> 3
}

// DMAC.LOWPOWER_CFG1: NA
func (o *DMAC_Type) SetLOWPOWER_CFG1_GLCH_LPDLY(value uint32) {
	volatile.StoreUint32(&o.LOWPOWER_CFG1.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg)&^(0xff)|value)
}
func (o *DMAC_Type) GetLOWPOWER_CFG1_GLCH_LPDLY() uint32 {
	return volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg) & 0xff
}
func (o *DMAC_Type) SetLOWPOWER_CFG1_SBIU_LPDLY(value uint32) {
	volatile.StoreUint32(&o.LOWPOWER_CFG1.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg)&^(0xff00)|value<<8)
}
func (o *DMAC_Type) GetLOWPOWER_CFG1_SBIU_LPDLY() uint32 {
	return (volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg) & 0xff00) >> 8
}
func (o *DMAC_Type) SetLOWPOWER_CFG1_MXIF_LPDLY(value uint32) {
	volatile.StoreUint32(&o.LOWPOWER_CFG1.Reg, volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg)&^(0xff0000)|value<<16)
}
func (o *DMAC_Type) GetLOWPOWER_CFG1_MXIF_LPDLY() uint32 {
	return (volatile.LoadUint32(&o.LOWPOWER_CFG1.Reg) & 0xff0000) >> 16
}

// DMAC.CH1_SAR0: NA
func (o *DMAC_Type) SetCH1_SAR0(value uint32) {
	volatile.StoreUint32(&o.CH1_SAR0.Reg, value)
}
func (o *DMAC_Type) GetCH1_SAR0() uint32 {
	return volatile.LoadUint32(&o.CH1_SAR0.Reg)
}

// DMAC.CH1_SAR1: NA
func (o *DMAC_Type) SetCH1_SAR1(value uint32) {
	volatile.StoreUint32(&o.CH1_SAR1.Reg, value)
}
func (o *DMAC_Type) GetCH1_SAR1() uint32 {
	return volatile.LoadUint32(&o.CH1_SAR1.Reg)
}

// DMAC.CH1_DAR0: NA
func (o *DMAC_Type) SetCH1_DAR0(value uint32) {
	volatile.StoreUint32(&o.CH1_DAR0.Reg, value)
}
func (o *DMAC_Type) GetCH1_DAR0() uint32 {
	return volatile.LoadUint32(&o.CH1_DAR0.Reg)
}

// DMAC.CH1_DAR1: NA
func (o *DMAC_Type) SetCH1_DAR1(value uint32) {
	volatile.StoreUint32(&o.CH1_DAR1.Reg, value)
}
func (o *DMAC_Type) GetCH1_DAR1() uint32 {
	return volatile.LoadUint32(&o.CH1_DAR1.Reg)
}

// DMAC.CH1_BLOCK_TS0: NA
func (o *DMAC_Type) SetCH1_BLOCK_TS0_CH1_BLOCK_TS(value uint32) {
	volatile.StoreUint32(&o.CH1_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH1_BLOCK_TS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH1_BLOCK_TS0_CH1_BLOCK_TS() uint32 {
	return volatile.LoadUint32(&o.CH1_BLOCK_TS0.Reg) & 0x3fffff
}

// DMAC.CH1_CTL0: NA
func (o *DMAC_Type) SetCH1_CTL0_CH1_SMS(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_SMS() uint32 {
	return volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_DMS(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_DMS() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_SINC(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_SINC() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_DINC(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_DINC() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_SRC_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x700)|value<<8)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_SRC_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x700) >> 8
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_DST_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3800)|value<<11)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_DST_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3800) >> 11
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_SRC_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c000)|value<<14)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_SRC_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c000) >> 14
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_DST_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_DST_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_AR_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c00000)|value<<22)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_AR_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c00000) >> 22
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_AW_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x3c000000)|value<<26)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_AW_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x3c000000) >> 26
}
func (o *DMAC_Type) SetCH1_CTL0_CH1_NONPOSTED_LASTWRITE_EN(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL0.Reg, volatile.LoadUint32(&o.CH1_CTL0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH1_CTL0_CH1_NONPOSTED_LASTWRITE_EN() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL0.Reg) & 0x40000000) >> 30
}

// DMAC.CH1_CTL1: NA
func (o *DMAC_Type) SetCH1_CTL1_CH1_AR_PROT(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_AR_PROT() uint32 {
	return volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_AW_PROT(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x38)|value<<3)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_AW_PROT() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x38) >> 3
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_ARLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_ARLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_ARLEN(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x7f80)|value<<7)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_ARLEN() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x7f80) >> 7
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_AWLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_AWLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_AWLEN(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0xff0000)|value<<16)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_AWLEN() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0xff0000) >> 16
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_SRC_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x1000000)|value<<24)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_SRC_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x1000000) >> 24
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_DST_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_DST_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_IOC_BLKTFR(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x4000000)|value<<26)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_IOC_BLKTFR() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x4000000) >> 26
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_SHADOWREG_OR_LLI_LAST(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_SHADOWREG_OR_LLI_LAST() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH1_CTL1_CH1_SHADOWREG_OR_LLI_VALID(value uint32) {
	volatile.StoreUint32(&o.CH1_CTL1.Reg, volatile.LoadUint32(&o.CH1_CTL1.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH1_CTL1_CH1_SHADOWREG_OR_LLI_VALID() uint32 {
	return (volatile.LoadUint32(&o.CH1_CTL1.Reg) & 0x80000000) >> 31
}

// DMAC.CH1_CFG0: NA
func (o *DMAC_Type) SetCH1_CFG0_CH1_SRC_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0x3)|value)
}
func (o *DMAC_Type) GetCH1_CFG0_CH1_SRC_MULTBLK_TYPE() uint32 {
	return volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0x3
}
func (o *DMAC_Type) SetCH1_CFG0_CH1_DST_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0xc)|value<<2)
}
func (o *DMAC_Type) GetCH1_CFG0_CH1_DST_MULTBLK_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0xc) >> 2
}
func (o *DMAC_Type) SetCH1_CFG0_CH1_RD_UID(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH1_CFG0_CH1_RD_UID() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH1_CFG0_CH1_WR_UID(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG0.Reg, volatile.LoadUint32(&o.CH1_CFG0.Reg)&^(0x1e000000)|value<<25)
}
func (o *DMAC_Type) GetCH1_CFG0_CH1_WR_UID() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG0.Reg) & 0x1e000000) >> 25
}

// DMAC.CH1_CFG1: NA
func (o *DMAC_Type) SetCH1_CFG1_CH1_TT_FC(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_TT_FC() uint32 {
	return volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_HS_SEL_SRC(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_HS_SEL_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_HS_SEL_DST(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_HS_SEL_DST() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_SRC_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_SRC_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_DST_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_DST_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x180)|value<<7)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_SRC_PER() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x180) >> 7
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x3000)|value<<12)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x3000) >> 12
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_CH_PRIOR(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0xe0000)|value<<17)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_CH_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0xe0000) >> 17
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_LOCK_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_LOCK_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_LOCK_CH_L(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_LOCK_CH_L() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_SRC_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x7800000)|value<<23)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_SRC_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x7800000) >> 23
}
func (o *DMAC_Type) SetCH1_CFG1_CH1_DST_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH1_CFG1.Reg, volatile.LoadUint32(&o.CH1_CFG1.Reg)&^(0x78000000)|value<<27)
}
func (o *DMAC_Type) GetCH1_CFG1_CH1_DST_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH1_CFG1.Reg) & 0x78000000) >> 27
}

// DMAC.CH1_LLP0: NA
func (o *DMAC_Type) SetCH1_LLP0_CH1_LMS(value uint32) {
	volatile.StoreUint32(&o.CH1_LLP0.Reg, volatile.LoadUint32(&o.CH1_LLP0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_LLP0_CH1_LMS() uint32 {
	return volatile.LoadUint32(&o.CH1_LLP0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_LLP0_CH1_LOC0(value uint32) {
	volatile.StoreUint32(&o.CH1_LLP0.Reg, volatile.LoadUint32(&o.CH1_LLP0.Reg)&^(0xffffffc0)|value<<6)
}
func (o *DMAC_Type) GetCH1_LLP0_CH1_LOC0() uint32 {
	return (volatile.LoadUint32(&o.CH1_LLP0.Reg) & 0xffffffc0) >> 6
}

// DMAC.CH1_LLP1: NA
func (o *DMAC_Type) SetCH1_LLP1(value uint32) {
	volatile.StoreUint32(&o.CH1_LLP1.Reg, value)
}
func (o *DMAC_Type) GetCH1_LLP1() uint32 {
	return volatile.LoadUint32(&o.CH1_LLP1.Reg)
}

// DMAC.CH1_STATUS0: NA
func (o *DMAC_Type) SetCH1_STATUS0_CH1_CMPLTD_BLK_TFR_SIZE(value uint32) {
	volatile.StoreUint32(&o.CH1_STATUS0.Reg, volatile.LoadUint32(&o.CH1_STATUS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH1_STATUS0_CH1_CMPLTD_BLK_TFR_SIZE() uint32 {
	return volatile.LoadUint32(&o.CH1_STATUS0.Reg) & 0x3fffff
}

// DMAC.CH1_STATUS1: NA
func (o *DMAC_Type) SetCH1_STATUS1_CH1_DATA_LEFT_IN_FIFO(value uint32) {
	volatile.StoreUint32(&o.CH1_STATUS1.Reg, volatile.LoadUint32(&o.CH1_STATUS1.Reg)&^(0x7fff)|value)
}
func (o *DMAC_Type) GetCH1_STATUS1_CH1_DATA_LEFT_IN_FIFO() uint32 {
	return volatile.LoadUint32(&o.CH1_STATUS1.Reg) & 0x7fff
}

// DMAC.CH1_SWHSSRC0: NA
func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC() uint32 {
	return volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_REQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_LST_SRC(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_LST_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_SWHSSRC0_CH1_SWHS_LST_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH1_SWHSSRC0_CH1_SWHS_LST_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSSRC0.Reg) & 0x20) >> 5
}

// DMAC.CH1_SWHSDST0: NA
func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_REQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_REQ_DST() uint32 {
	return volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_REQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_REQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_LST_DST(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_LST_DST() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_SWHSDST0_CH1_SWHS_LST_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH1_SWHSDST0.Reg, volatile.LoadUint32(&o.CH1_SWHSDST0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH1_SWHSDST0_CH1_SWHS_LST_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH1_SWHSDST0.Reg) & 0x20) >> 5
}

// DMAC.CH1_BLK_TFR_RESUMEREQ0: NA
func (o *DMAC_Type) SetCH1_BLK_TFR_RESUMEREQ0_CH1_BLK_TFR_RESUMEREQ(value uint32) {
	volatile.StoreUint32(&o.CH1_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH1_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_BLK_TFR_RESUMEREQ0_CH1_BLK_TFR_RESUMEREQ() uint32 {
	return volatile.LoadUint32(&o.CH1_BLK_TFR_RESUMEREQ0.Reg) & 0x1
}

// DMAC.CH1_AXI_ID0: NA
func (o *DMAC_Type) SetCH1_AXI_ID0_CH1_AXI_READ_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH1_AXI_ID0.Reg, volatile.LoadUint32(&o.CH1_AXI_ID0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_AXI_ID0_CH1_AXI_READ_ID_SUFFIX() uint32 {
	return volatile.LoadUint32(&o.CH1_AXI_ID0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_AXI_ID0_CH1_AXI_WRITE_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH1_AXI_ID0.Reg, volatile.LoadUint32(&o.CH1_AXI_ID0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH1_AXI_ID0_CH1_AXI_WRITE_ID_SUFFIX() uint32 {
	return (volatile.LoadUint32(&o.CH1_AXI_ID0.Reg) & 0x10000) >> 16
}

// DMAC.CH1_AXI_QOS0: NA
func (o *DMAC_Type) SetCH1_AXI_QOS0_CH1_AXI_AWQOS(value uint32) {
	volatile.StoreUint32(&o.CH1_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCH1_AXI_QOS0_CH1_AXI_AWQOS() uint32 {
	return volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg) & 0xf
}
func (o *DMAC_Type) SetCH1_AXI_QOS0_CH1_AXI_ARQOS(value uint32) {
	volatile.StoreUint32(&o.CH1_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCH1_AXI_QOS0_CH1_AXI_ARQOS() uint32 {
	return (volatile.LoadUint32(&o.CH1_AXI_QOS0.Reg) & 0xf0) >> 4
}

// DMAC.CH1_SSTAT0: NA
func (o *DMAC_Type) SetCH1_SSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH1_SSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH1_SSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH1_SSTAT0.Reg)
}

// DMAC.CH1_DSTAT0: NA
func (o *DMAC_Type) SetCH1_DSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH1_DSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH1_DSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH1_DSTAT0.Reg)
}

// DMAC.CH1_SSTATAR0: NA
func (o *DMAC_Type) SetCH1_SSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH1_SSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH1_SSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH1_SSTATAR0.Reg)
}

// DMAC.CH1_SSTATAR1: NA
func (o *DMAC_Type) SetCH1_SSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH1_SSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH1_SSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH1_SSTATAR1.Reg)
}

// DMAC.CH1_DSTATAR0: NA
func (o *DMAC_Type) SetCH1_DSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH1_DSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH1_DSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH1_DSTATAR0.Reg)
}

// DMAC.CH1_DSTATAR1: NA
func (o *DMAC_Type) SetCH1_DSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH1_DSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH1_DSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH1_DSTATAR1.Reg)
}

// DMAC.CH1_INTSTATUS_ENABLE0: NA
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH1_INTSTATUS_ENABLE1: NA
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH1_INTSTATUS0: NA
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH1_INTSTATUS0_CH1_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH1_INTSTATUS0_CH1_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS0.Reg) & 0x80000000) >> 31
}

// DMAC.CH1_INTSTATUS1: NA
func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSTATUS1.Reg) & 0x8) >> 3
}

// DMAC.CH1_INTSIGNAL_ENABLE0: NA
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH1_INTSIGNAL_ENABLE1: NA
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH1_INTCLEAR0: NA
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH1_INTCLEAR0_CH1_CLEAR_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH1_INTCLEAR0_CH1_CLEAR_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR0.Reg) & 0x80000000) >> 31
}

// DMAC.CH1_INTCLEAR1: NA
func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH1_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH1_INTCLEAR1.Reg) & 0x8) >> 3
}

// DMAC.CH2_SAR0: NA
func (o *DMAC_Type) SetCH2_SAR0(value uint32) {
	volatile.StoreUint32(&o.CH2_SAR0.Reg, value)
}
func (o *DMAC_Type) GetCH2_SAR0() uint32 {
	return volatile.LoadUint32(&o.CH2_SAR0.Reg)
}

// DMAC.CH2_SAR1: NA
func (o *DMAC_Type) SetCH2_SAR1(value uint32) {
	volatile.StoreUint32(&o.CH2_SAR1.Reg, value)
}
func (o *DMAC_Type) GetCH2_SAR1() uint32 {
	return volatile.LoadUint32(&o.CH2_SAR1.Reg)
}

// DMAC.CH2_DAR0: NA
func (o *DMAC_Type) SetCH2_DAR0(value uint32) {
	volatile.StoreUint32(&o.CH2_DAR0.Reg, value)
}
func (o *DMAC_Type) GetCH2_DAR0() uint32 {
	return volatile.LoadUint32(&o.CH2_DAR0.Reg)
}

// DMAC.CH2_DAR1: NA
func (o *DMAC_Type) SetCH2_DAR1(value uint32) {
	volatile.StoreUint32(&o.CH2_DAR1.Reg, value)
}
func (o *DMAC_Type) GetCH2_DAR1() uint32 {
	return volatile.LoadUint32(&o.CH2_DAR1.Reg)
}

// DMAC.CH2_BLOCK_TS0: NA
func (o *DMAC_Type) SetCH2_BLOCK_TS0_CH2_BLOCK_TS(value uint32) {
	volatile.StoreUint32(&o.CH2_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH2_BLOCK_TS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH2_BLOCK_TS0_CH2_BLOCK_TS() uint32 {
	return volatile.LoadUint32(&o.CH2_BLOCK_TS0.Reg) & 0x3fffff
}

// DMAC.CH2_CTL0: NA
func (o *DMAC_Type) SetCH2_CTL0_CH2_SMS(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_SMS() uint32 {
	return volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_DMS(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_DMS() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_SINC(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_SINC() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_DINC(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_DINC() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_SRC_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x700)|value<<8)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_SRC_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x700) >> 8
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_DST_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3800)|value<<11)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_DST_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3800) >> 11
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_SRC_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c000)|value<<14)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_SRC_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c000) >> 14
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_DST_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_DST_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_AR_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c00000)|value<<22)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_AR_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c00000) >> 22
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_AW_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x3c000000)|value<<26)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_AW_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x3c000000) >> 26
}
func (o *DMAC_Type) SetCH2_CTL0_CH2_NONPOSTED_LASTWRITE_EN(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL0.Reg, volatile.LoadUint32(&o.CH2_CTL0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH2_CTL0_CH2_NONPOSTED_LASTWRITE_EN() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL0.Reg) & 0x40000000) >> 30
}

// DMAC.CH2_CTL1: NA
func (o *DMAC_Type) SetCH2_CTL1_CH2_AR_PROT(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_AR_PROT() uint32 {
	return volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_AW_PROT(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x38)|value<<3)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_AW_PROT() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x38) >> 3
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_ARLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_ARLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_ARLEN(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x7f80)|value<<7)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_ARLEN() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x7f80) >> 7
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_AWLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_AWLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_AWLEN(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0xff0000)|value<<16)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_AWLEN() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0xff0000) >> 16
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_SRC_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x1000000)|value<<24)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_SRC_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x1000000) >> 24
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_DST_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_DST_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_IOC_BLKTFR(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x4000000)|value<<26)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_IOC_BLKTFR() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x4000000) >> 26
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_SHADOWREG_OR_LLI_LAST(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_SHADOWREG_OR_LLI_LAST() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH2_CTL1_CH2_SHADOWREG_OR_LLI_VALID(value uint32) {
	volatile.StoreUint32(&o.CH2_CTL1.Reg, volatile.LoadUint32(&o.CH2_CTL1.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH2_CTL1_CH2_SHADOWREG_OR_LLI_VALID() uint32 {
	return (volatile.LoadUint32(&o.CH2_CTL1.Reg) & 0x80000000) >> 31
}

// DMAC.CH2_CFG0: NA
func (o *DMAC_Type) SetCH2_CFG0_CH2_SRC_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0x3)|value)
}
func (o *DMAC_Type) GetCH2_CFG0_CH2_SRC_MULTBLK_TYPE() uint32 {
	return volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0x3
}
func (o *DMAC_Type) SetCH2_CFG0_CH2_DST_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0xc)|value<<2)
}
func (o *DMAC_Type) GetCH2_CFG0_CH2_DST_MULTBLK_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0xc) >> 2
}
func (o *DMAC_Type) SetCH2_CFG0_CH2_RD_UID(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH2_CFG0_CH2_RD_UID() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH2_CFG0_CH2_WR_UID(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG0.Reg, volatile.LoadUint32(&o.CH2_CFG0.Reg)&^(0x1e000000)|value<<25)
}
func (o *DMAC_Type) GetCH2_CFG0_CH2_WR_UID() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG0.Reg) & 0x1e000000) >> 25
}

// DMAC.CH2_CFG1: NA
func (o *DMAC_Type) SetCH2_CFG1_CH2_TT_FC(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_TT_FC() uint32 {
	return volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_HS_SEL_SRC(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_HS_SEL_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_HS_SEL_DST(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_HS_SEL_DST() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_SRC_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_SRC_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_DST_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_DST_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x180)|value<<7)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_SRC_PER() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x180) >> 7
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x3000)|value<<12)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x3000) >> 12
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_CH_PRIOR(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0xe0000)|value<<17)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_CH_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0xe0000) >> 17
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_LOCK_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_LOCK_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_LOCK_CH_L(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_LOCK_CH_L() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_SRC_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x7800000)|value<<23)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_SRC_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x7800000) >> 23
}
func (o *DMAC_Type) SetCH2_CFG1_CH2_DST_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH2_CFG1.Reg, volatile.LoadUint32(&o.CH2_CFG1.Reg)&^(0x78000000)|value<<27)
}
func (o *DMAC_Type) GetCH2_CFG1_CH2_DST_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH2_CFG1.Reg) & 0x78000000) >> 27
}

// DMAC.CH2_LLP0: NA
func (o *DMAC_Type) SetCH2_LLP0_CH2_LMS(value uint32) {
	volatile.StoreUint32(&o.CH2_LLP0.Reg, volatile.LoadUint32(&o.CH2_LLP0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_LLP0_CH2_LMS() uint32 {
	return volatile.LoadUint32(&o.CH2_LLP0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_LLP0_CH2_LOC0(value uint32) {
	volatile.StoreUint32(&o.CH2_LLP0.Reg, volatile.LoadUint32(&o.CH2_LLP0.Reg)&^(0xffffffc0)|value<<6)
}
func (o *DMAC_Type) GetCH2_LLP0_CH2_LOC0() uint32 {
	return (volatile.LoadUint32(&o.CH2_LLP0.Reg) & 0xffffffc0) >> 6
}

// DMAC.CH2_LLP1: NA
func (o *DMAC_Type) SetCH2_LLP1(value uint32) {
	volatile.StoreUint32(&o.CH2_LLP1.Reg, value)
}
func (o *DMAC_Type) GetCH2_LLP1() uint32 {
	return volatile.LoadUint32(&o.CH2_LLP1.Reg)
}

// DMAC.CH2_STATUS0: NA
func (o *DMAC_Type) SetCH2_STATUS0_CH2_CMPLTD_BLK_TFR_SIZE(value uint32) {
	volatile.StoreUint32(&o.CH2_STATUS0.Reg, volatile.LoadUint32(&o.CH2_STATUS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH2_STATUS0_CH2_CMPLTD_BLK_TFR_SIZE() uint32 {
	return volatile.LoadUint32(&o.CH2_STATUS0.Reg) & 0x3fffff
}

// DMAC.CH2_STATUS1: NA
func (o *DMAC_Type) SetCH2_STATUS1_CH2_DATA_LEFT_IN_FIFO(value uint32) {
	volatile.StoreUint32(&o.CH2_STATUS1.Reg, volatile.LoadUint32(&o.CH2_STATUS1.Reg)&^(0x7fff)|value)
}
func (o *DMAC_Type) GetCH2_STATUS1_CH2_DATA_LEFT_IN_FIFO() uint32 {
	return volatile.LoadUint32(&o.CH2_STATUS1.Reg) & 0x7fff
}

// DMAC.CH2_SWHSSRC0: NA
func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC() uint32 {
	return volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_REQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_LST_SRC(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_LST_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_SWHSSRC0_CH2_SWHS_LST_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH2_SWHSSRC0_CH2_SWHS_LST_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSSRC0.Reg) & 0x20) >> 5
}

// DMAC.CH2_SWHSDST0: NA
func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_REQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_REQ_DST() uint32 {
	return volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_REQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_REQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_LST_DST(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_LST_DST() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_SWHSDST0_CH2_SWHS_LST_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH2_SWHSDST0.Reg, volatile.LoadUint32(&o.CH2_SWHSDST0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH2_SWHSDST0_CH2_SWHS_LST_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH2_SWHSDST0.Reg) & 0x20) >> 5
}

// DMAC.CH2_BLK_TFR_RESUMEREQ0: NA
func (o *DMAC_Type) SetCH2_BLK_TFR_RESUMEREQ0_CH2_BLK_TFR_RESUMEREQ(value uint32) {
	volatile.StoreUint32(&o.CH2_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH2_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_BLK_TFR_RESUMEREQ0_CH2_BLK_TFR_RESUMEREQ() uint32 {
	return volatile.LoadUint32(&o.CH2_BLK_TFR_RESUMEREQ0.Reg) & 0x1
}

// DMAC.CH2_AXI_ID0: NA
func (o *DMAC_Type) SetCH2_AXI_ID0_CH2_AXI_READ_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH2_AXI_ID0.Reg, volatile.LoadUint32(&o.CH2_AXI_ID0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_AXI_ID0_CH2_AXI_READ_ID_SUFFIX() uint32 {
	return volatile.LoadUint32(&o.CH2_AXI_ID0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_AXI_ID0_CH2_AXI_WRITE_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH2_AXI_ID0.Reg, volatile.LoadUint32(&o.CH2_AXI_ID0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH2_AXI_ID0_CH2_AXI_WRITE_ID_SUFFIX() uint32 {
	return (volatile.LoadUint32(&o.CH2_AXI_ID0.Reg) & 0x10000) >> 16
}

// DMAC.CH2_AXI_QOS0: NA
func (o *DMAC_Type) SetCH2_AXI_QOS0_CH2_AXI_AWQOS(value uint32) {
	volatile.StoreUint32(&o.CH2_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCH2_AXI_QOS0_CH2_AXI_AWQOS() uint32 {
	return volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg) & 0xf
}
func (o *DMAC_Type) SetCH2_AXI_QOS0_CH2_AXI_ARQOS(value uint32) {
	volatile.StoreUint32(&o.CH2_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCH2_AXI_QOS0_CH2_AXI_ARQOS() uint32 {
	return (volatile.LoadUint32(&o.CH2_AXI_QOS0.Reg) & 0xf0) >> 4
}

// DMAC.CH2_SSTAT0: NA
func (o *DMAC_Type) SetCH2_SSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH2_SSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH2_SSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH2_SSTAT0.Reg)
}

// DMAC.CH2_DSTAT0: NA
func (o *DMAC_Type) SetCH2_DSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH2_DSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH2_DSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH2_DSTAT0.Reg)
}

// DMAC.CH2_SSTATAR0: NA
func (o *DMAC_Type) SetCH2_SSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH2_SSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH2_SSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH2_SSTATAR0.Reg)
}

// DMAC.CH2_SSTATAR1: NA
func (o *DMAC_Type) SetCH2_SSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH2_SSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH2_SSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH2_SSTATAR1.Reg)
}

// DMAC.CH2_DSTATAR0: NA
func (o *DMAC_Type) SetCH2_DSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH2_DSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH2_DSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH2_DSTATAR0.Reg)
}

// DMAC.CH2_DSTATAR1: NA
func (o *DMAC_Type) SetCH2_DSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH2_DSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH2_DSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH2_DSTATAR1.Reg)
}

// DMAC.CH2_INTSTATUS_ENABLE0: NA
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH2_INTSTATUS_ENABLE1: NA
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH2_INTSTATUS0: NA
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH2_INTSTATUS0_CH2_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH2_INTSTATUS0_CH2_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS0.Reg) & 0x80000000) >> 31
}

// DMAC.CH2_INTSTATUS1: NA
func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSTATUS1.Reg) & 0x8) >> 3
}

// DMAC.CH2_INTSIGNAL_ENABLE0: NA
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH2_INTSIGNAL_ENABLE1: NA
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH2_INTCLEAR0: NA
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH2_INTCLEAR0_CH2_CLEAR_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH2_INTCLEAR0_CH2_CLEAR_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR0.Reg) & 0x80000000) >> 31
}

// DMAC.CH2_INTCLEAR1: NA
func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH2_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH2_INTCLEAR1.Reg) & 0x8) >> 3
}

// DMAC.CH3_SAR0: NA
func (o *DMAC_Type) SetCH3_SAR0(value uint32) {
	volatile.StoreUint32(&o.CH3_SAR0.Reg, value)
}
func (o *DMAC_Type) GetCH3_SAR0() uint32 {
	return volatile.LoadUint32(&o.CH3_SAR0.Reg)
}

// DMAC.CH3_SAR1: NA
func (o *DMAC_Type) SetCH3_SAR1(value uint32) {
	volatile.StoreUint32(&o.CH3_SAR1.Reg, value)
}
func (o *DMAC_Type) GetCH3_SAR1() uint32 {
	return volatile.LoadUint32(&o.CH3_SAR1.Reg)
}

// DMAC.CH3_DAR0: NA
func (o *DMAC_Type) SetCH3_DAR0(value uint32) {
	volatile.StoreUint32(&o.CH3_DAR0.Reg, value)
}
func (o *DMAC_Type) GetCH3_DAR0() uint32 {
	return volatile.LoadUint32(&o.CH3_DAR0.Reg)
}

// DMAC.CH3_DAR1: NA
func (o *DMAC_Type) SetCH3_DAR1(value uint32) {
	volatile.StoreUint32(&o.CH3_DAR1.Reg, value)
}
func (o *DMAC_Type) GetCH3_DAR1() uint32 {
	return volatile.LoadUint32(&o.CH3_DAR1.Reg)
}

// DMAC.CH3_BLOCK_TS0: NA
func (o *DMAC_Type) SetCH3_BLOCK_TS0_CH3_BLOCK_TS(value uint32) {
	volatile.StoreUint32(&o.CH3_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH3_BLOCK_TS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH3_BLOCK_TS0_CH3_BLOCK_TS() uint32 {
	return volatile.LoadUint32(&o.CH3_BLOCK_TS0.Reg) & 0x3fffff
}

// DMAC.CH3_CTL0: NA
func (o *DMAC_Type) SetCH3_CTL0_CH3_SMS(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_SMS() uint32 {
	return volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_DMS(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_DMS() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_SINC(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_SINC() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_DINC(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_DINC() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_SRC_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x700)|value<<8)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_SRC_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x700) >> 8
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_DST_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3800)|value<<11)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_DST_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3800) >> 11
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_SRC_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c000)|value<<14)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_SRC_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c000) >> 14
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_DST_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_DST_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_AR_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c00000)|value<<22)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_AR_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c00000) >> 22
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_AW_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x3c000000)|value<<26)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_AW_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x3c000000) >> 26
}
func (o *DMAC_Type) SetCH3_CTL0_CH3_NONPOSTED_LASTWRITE_EN(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL0.Reg, volatile.LoadUint32(&o.CH3_CTL0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH3_CTL0_CH3_NONPOSTED_LASTWRITE_EN() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL0.Reg) & 0x40000000) >> 30
}

// DMAC.CH3_CTL1: NA
func (o *DMAC_Type) SetCH3_CTL1_CH3_AR_PROT(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_AR_PROT() uint32 {
	return volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_AW_PROT(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x38)|value<<3)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_AW_PROT() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x38) >> 3
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_ARLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_ARLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_ARLEN(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x7f80)|value<<7)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_ARLEN() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x7f80) >> 7
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_AWLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_AWLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_AWLEN(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0xff0000)|value<<16)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_AWLEN() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0xff0000) >> 16
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_SRC_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x1000000)|value<<24)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_SRC_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x1000000) >> 24
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_DST_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_DST_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_IOC_BLKTFR(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x4000000)|value<<26)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_IOC_BLKTFR() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x4000000) >> 26
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_SHADOWREG_OR_LLI_LAST(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_SHADOWREG_OR_LLI_LAST() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH3_CTL1_CH3_SHADOWREG_OR_LLI_VALID(value uint32) {
	volatile.StoreUint32(&o.CH3_CTL1.Reg, volatile.LoadUint32(&o.CH3_CTL1.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH3_CTL1_CH3_SHADOWREG_OR_LLI_VALID() uint32 {
	return (volatile.LoadUint32(&o.CH3_CTL1.Reg) & 0x80000000) >> 31
}

// DMAC.CH3_CFG0: NA
func (o *DMAC_Type) SetCH3_CFG0_CH3_SRC_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0x3)|value)
}
func (o *DMAC_Type) GetCH3_CFG0_CH3_SRC_MULTBLK_TYPE() uint32 {
	return volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0x3
}
func (o *DMAC_Type) SetCH3_CFG0_CH3_DST_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0xc)|value<<2)
}
func (o *DMAC_Type) GetCH3_CFG0_CH3_DST_MULTBLK_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0xc) >> 2
}
func (o *DMAC_Type) SetCH3_CFG0_CH3_RD_UID(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH3_CFG0_CH3_RD_UID() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH3_CFG0_CH3_WR_UID(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG0.Reg, volatile.LoadUint32(&o.CH3_CFG0.Reg)&^(0x1e000000)|value<<25)
}
func (o *DMAC_Type) GetCH3_CFG0_CH3_WR_UID() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG0.Reg) & 0x1e000000) >> 25
}

// DMAC.CH3_CFG1: NA
func (o *DMAC_Type) SetCH3_CFG1_CH3_TT_FC(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_TT_FC() uint32 {
	return volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_HS_SEL_SRC(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_HS_SEL_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_HS_SEL_DST(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_HS_SEL_DST() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_SRC_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_SRC_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_DST_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_DST_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x180)|value<<7)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_SRC_PER() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x180) >> 7
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x3000)|value<<12)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x3000) >> 12
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_CH_PRIOR(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0xe0000)|value<<17)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_CH_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0xe0000) >> 17
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_LOCK_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_LOCK_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_LOCK_CH_L(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_LOCK_CH_L() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_SRC_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x7800000)|value<<23)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_SRC_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x7800000) >> 23
}
func (o *DMAC_Type) SetCH3_CFG1_CH3_DST_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH3_CFG1.Reg, volatile.LoadUint32(&o.CH3_CFG1.Reg)&^(0x78000000)|value<<27)
}
func (o *DMAC_Type) GetCH3_CFG1_CH3_DST_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH3_CFG1.Reg) & 0x78000000) >> 27
}

// DMAC.CH3_LLP0: NA
func (o *DMAC_Type) SetCH3_LLP0_CH3_LMS(value uint32) {
	volatile.StoreUint32(&o.CH3_LLP0.Reg, volatile.LoadUint32(&o.CH3_LLP0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_LLP0_CH3_LMS() uint32 {
	return volatile.LoadUint32(&o.CH3_LLP0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_LLP0_CH3_LOC0(value uint32) {
	volatile.StoreUint32(&o.CH3_LLP0.Reg, volatile.LoadUint32(&o.CH3_LLP0.Reg)&^(0xffffffc0)|value<<6)
}
func (o *DMAC_Type) GetCH3_LLP0_CH3_LOC0() uint32 {
	return (volatile.LoadUint32(&o.CH3_LLP0.Reg) & 0xffffffc0) >> 6
}

// DMAC.CH3_LLP1: NA
func (o *DMAC_Type) SetCH3_LLP1(value uint32) {
	volatile.StoreUint32(&o.CH3_LLP1.Reg, value)
}
func (o *DMAC_Type) GetCH3_LLP1() uint32 {
	return volatile.LoadUint32(&o.CH3_LLP1.Reg)
}

// DMAC.CH3_STATUS0: NA
func (o *DMAC_Type) SetCH3_STATUS0_CH3_CMPLTD_BLK_TFR_SIZE(value uint32) {
	volatile.StoreUint32(&o.CH3_STATUS0.Reg, volatile.LoadUint32(&o.CH3_STATUS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH3_STATUS0_CH3_CMPLTD_BLK_TFR_SIZE() uint32 {
	return volatile.LoadUint32(&o.CH3_STATUS0.Reg) & 0x3fffff
}

// DMAC.CH3_STATUS1: NA
func (o *DMAC_Type) SetCH3_STATUS1_CH3_DATA_LEFT_IN_FIFO(value uint32) {
	volatile.StoreUint32(&o.CH3_STATUS1.Reg, volatile.LoadUint32(&o.CH3_STATUS1.Reg)&^(0x7fff)|value)
}
func (o *DMAC_Type) GetCH3_STATUS1_CH3_DATA_LEFT_IN_FIFO() uint32 {
	return volatile.LoadUint32(&o.CH3_STATUS1.Reg) & 0x7fff
}

// DMAC.CH3_SWHSSRC0: NA
func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC() uint32 {
	return volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_REQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_LST_SRC(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_LST_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_SWHSSRC0_CH3_SWHS_LST_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH3_SWHSSRC0_CH3_SWHS_LST_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSSRC0.Reg) & 0x20) >> 5
}

// DMAC.CH3_SWHSDST0: NA
func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_REQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_REQ_DST() uint32 {
	return volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_REQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_REQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_LST_DST(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_LST_DST() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_SWHSDST0_CH3_SWHS_LST_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH3_SWHSDST0.Reg, volatile.LoadUint32(&o.CH3_SWHSDST0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH3_SWHSDST0_CH3_SWHS_LST_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH3_SWHSDST0.Reg) & 0x20) >> 5
}

// DMAC.CH3_BLK_TFR_RESUMEREQ0: NA
func (o *DMAC_Type) SetCH3_BLK_TFR_RESUMEREQ0_CH3_BLK_TFR_RESUMEREQ(value uint32) {
	volatile.StoreUint32(&o.CH3_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH3_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_BLK_TFR_RESUMEREQ0_CH3_BLK_TFR_RESUMEREQ() uint32 {
	return volatile.LoadUint32(&o.CH3_BLK_TFR_RESUMEREQ0.Reg) & 0x1
}

// DMAC.CH3_AXI_ID0: NA
func (o *DMAC_Type) SetCH3_AXI_ID0_CH3_AXI_READ_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH3_AXI_ID0.Reg, volatile.LoadUint32(&o.CH3_AXI_ID0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_AXI_ID0_CH3_AXI_READ_ID_SUFFIX() uint32 {
	return volatile.LoadUint32(&o.CH3_AXI_ID0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_AXI_ID0_CH3_AXI_WRITE_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH3_AXI_ID0.Reg, volatile.LoadUint32(&o.CH3_AXI_ID0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH3_AXI_ID0_CH3_AXI_WRITE_ID_SUFFIX() uint32 {
	return (volatile.LoadUint32(&o.CH3_AXI_ID0.Reg) & 0x10000) >> 16
}

// DMAC.CH3_AXI_QOS0: NA
func (o *DMAC_Type) SetCH3_AXI_QOS0_CH3_AXI_AWQOS(value uint32) {
	volatile.StoreUint32(&o.CH3_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCH3_AXI_QOS0_CH3_AXI_AWQOS() uint32 {
	return volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg) & 0xf
}
func (o *DMAC_Type) SetCH3_AXI_QOS0_CH3_AXI_ARQOS(value uint32) {
	volatile.StoreUint32(&o.CH3_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCH3_AXI_QOS0_CH3_AXI_ARQOS() uint32 {
	return (volatile.LoadUint32(&o.CH3_AXI_QOS0.Reg) & 0xf0) >> 4
}

// DMAC.CH3_SSTAT0: NA
func (o *DMAC_Type) SetCH3_SSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH3_SSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH3_SSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH3_SSTAT0.Reg)
}

// DMAC.CH3_DSTAT0: NA
func (o *DMAC_Type) SetCH3_DSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH3_DSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH3_DSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH3_DSTAT0.Reg)
}

// DMAC.CH3_SSTATAR0: NA
func (o *DMAC_Type) SetCH3_SSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH3_SSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH3_SSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH3_SSTATAR0.Reg)
}

// DMAC.CH3_SSTATAR1: NA
func (o *DMAC_Type) SetCH3_SSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH3_SSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH3_SSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH3_SSTATAR1.Reg)
}

// DMAC.CH3_DSTATAR0: NA
func (o *DMAC_Type) SetCH3_DSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH3_DSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH3_DSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH3_DSTATAR0.Reg)
}

// DMAC.CH3_DSTATAR1: NA
func (o *DMAC_Type) SetCH3_DSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH3_DSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH3_DSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH3_DSTATAR1.Reg)
}

// DMAC.CH3_INTSTATUS_ENABLE0: NA
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH3_INTSTATUS_ENABLE1: NA
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH3_INTSTATUS0: NA
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH3_INTSTATUS0_CH3_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH3_INTSTATUS0_CH3_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS0.Reg) & 0x80000000) >> 31
}

// DMAC.CH3_INTSTATUS1: NA
func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSTATUS1.Reg) & 0x8) >> 3
}

// DMAC.CH3_INTSIGNAL_ENABLE0: NA
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH3_INTSIGNAL_ENABLE1: NA
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH3_INTCLEAR0: NA
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH3_INTCLEAR0_CH3_CLEAR_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH3_INTCLEAR0_CH3_CLEAR_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR0.Reg) & 0x80000000) >> 31
}

// DMAC.CH3_INTCLEAR1: NA
func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH3_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH3_INTCLEAR1.Reg) & 0x8) >> 3
}

// DMAC.CH4_SAR0: NA
func (o *DMAC_Type) SetCH4_SAR0(value uint32) {
	volatile.StoreUint32(&o.CH4_SAR0.Reg, value)
}
func (o *DMAC_Type) GetCH4_SAR0() uint32 {
	return volatile.LoadUint32(&o.CH4_SAR0.Reg)
}

// DMAC.CH4_SAR1: NA
func (o *DMAC_Type) SetCH4_SAR1(value uint32) {
	volatile.StoreUint32(&o.CH4_SAR1.Reg, value)
}
func (o *DMAC_Type) GetCH4_SAR1() uint32 {
	return volatile.LoadUint32(&o.CH4_SAR1.Reg)
}

// DMAC.CH4_DAR0: NA
func (o *DMAC_Type) SetCH4_DAR0(value uint32) {
	volatile.StoreUint32(&o.CH4_DAR0.Reg, value)
}
func (o *DMAC_Type) GetCH4_DAR0() uint32 {
	return volatile.LoadUint32(&o.CH4_DAR0.Reg)
}

// DMAC.CH4_DAR1: NA
func (o *DMAC_Type) SetCH4_DAR1(value uint32) {
	volatile.StoreUint32(&o.CH4_DAR1.Reg, value)
}
func (o *DMAC_Type) GetCH4_DAR1() uint32 {
	return volatile.LoadUint32(&o.CH4_DAR1.Reg)
}

// DMAC.CH4_BLOCK_TS0: NA
func (o *DMAC_Type) SetCH4_BLOCK_TS0_CH4_BLOCK_TS(value uint32) {
	volatile.StoreUint32(&o.CH4_BLOCK_TS0.Reg, volatile.LoadUint32(&o.CH4_BLOCK_TS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH4_BLOCK_TS0_CH4_BLOCK_TS() uint32 {
	return volatile.LoadUint32(&o.CH4_BLOCK_TS0.Reg) & 0x3fffff
}

// DMAC.CH4_CTL0: NA
func (o *DMAC_Type) SetCH4_CTL0_CH4_SMS(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_SMS() uint32 {
	return volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_DMS(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_DMS() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_SINC(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_SINC() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_DINC(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_DINC() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_SRC_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x700)|value<<8)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_SRC_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x700) >> 8
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_DST_TR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3800)|value<<11)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_DST_TR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3800) >> 11
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_SRC_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c000)|value<<14)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_SRC_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c000) >> 14
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_DST_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_DST_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_AR_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c00000)|value<<22)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_AR_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c00000) >> 22
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_AW_CACHE(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x3c000000)|value<<26)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_AW_CACHE() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x3c000000) >> 26
}
func (o *DMAC_Type) SetCH4_CTL0_CH4_NONPOSTED_LASTWRITE_EN(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL0.Reg, volatile.LoadUint32(&o.CH4_CTL0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH4_CTL0_CH4_NONPOSTED_LASTWRITE_EN() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL0.Reg) & 0x40000000) >> 30
}

// DMAC.CH4_CTL1: NA
func (o *DMAC_Type) SetCH4_CTL1_CH4_AR_PROT(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_AR_PROT() uint32 {
	return volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_AW_PROT(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x38)|value<<3)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_AW_PROT() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x38) >> 3
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_ARLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_ARLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_ARLEN(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x7f80)|value<<7)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_ARLEN() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x7f80) >> 7
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_AWLEN_EN(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x8000)|value<<15)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_AWLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x8000) >> 15
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_AWLEN(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0xff0000)|value<<16)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_AWLEN() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0xff0000) >> 16
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_SRC_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x1000000)|value<<24)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_SRC_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x1000000) >> 24
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_DST_STAT_EN(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_DST_STAT_EN() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_IOC_BLKTFR(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x4000000)|value<<26)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_IOC_BLKTFR() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x4000000) >> 26
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_SHADOWREG_OR_LLI_LAST(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_SHADOWREG_OR_LLI_LAST() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH4_CTL1_CH4_SHADOWREG_OR_LLI_VALID(value uint32) {
	volatile.StoreUint32(&o.CH4_CTL1.Reg, volatile.LoadUint32(&o.CH4_CTL1.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH4_CTL1_CH4_SHADOWREG_OR_LLI_VALID() uint32 {
	return (volatile.LoadUint32(&o.CH4_CTL1.Reg) & 0x80000000) >> 31
}

// DMAC.CH4_CFG0: NA
func (o *DMAC_Type) SetCH4_CFG0_CH4_SRC_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0x3)|value)
}
func (o *DMAC_Type) GetCH4_CFG0_CH4_SRC_MULTBLK_TYPE() uint32 {
	return volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0x3
}
func (o *DMAC_Type) SetCH4_CFG0_CH4_DST_MULTBLK_TYPE(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0xc)|value<<2)
}
func (o *DMAC_Type) GetCH4_CFG0_CH4_DST_MULTBLK_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0xc) >> 2
}
func (o *DMAC_Type) SetCH4_CFG0_CH4_RD_UID(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0x3c0000)|value<<18)
}
func (o *DMAC_Type) GetCH4_CFG0_CH4_RD_UID() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0x3c0000) >> 18
}
func (o *DMAC_Type) SetCH4_CFG0_CH4_WR_UID(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG0.Reg, volatile.LoadUint32(&o.CH4_CFG0.Reg)&^(0x1e000000)|value<<25)
}
func (o *DMAC_Type) GetCH4_CFG0_CH4_WR_UID() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG0.Reg) & 0x1e000000) >> 25
}

// DMAC.CH4_CFG1: NA
func (o *DMAC_Type) SetCH4_CFG1_CH4_TT_FC(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x7)|value)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_TT_FC() uint32 {
	return volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x7
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_HS_SEL_SRC(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_HS_SEL_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_HS_SEL_DST(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_HS_SEL_DST() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_SRC_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_SRC_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_DST_HWHS_POL(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_DST_HWHS_POL() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_SRC_PER(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x180)|value<<7)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_SRC_PER() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x180) >> 7
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_DST_PER(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x3000)|value<<12)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_DST_PER() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x3000) >> 12
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_CH_PRIOR(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0xe0000)|value<<17)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_CH_PRIOR() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0xe0000) >> 17
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_LOCK_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_LOCK_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_LOCK_CH_L(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x600000)|value<<21)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_LOCK_CH_L() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x600000) >> 21
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_SRC_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x7800000)|value<<23)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_SRC_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x7800000) >> 23
}
func (o *DMAC_Type) SetCH4_CFG1_CH4_DST_OSR_LMT(value uint32) {
	volatile.StoreUint32(&o.CH4_CFG1.Reg, volatile.LoadUint32(&o.CH4_CFG1.Reg)&^(0x78000000)|value<<27)
}
func (o *DMAC_Type) GetCH4_CFG1_CH4_DST_OSR_LMT() uint32 {
	return (volatile.LoadUint32(&o.CH4_CFG1.Reg) & 0x78000000) >> 27
}

// DMAC.CH4_LLP0: NA
func (o *DMAC_Type) SetCH4_LLP0_CH4_LMS(value uint32) {
	volatile.StoreUint32(&o.CH4_LLP0.Reg, volatile.LoadUint32(&o.CH4_LLP0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_LLP0_CH4_LMS() uint32 {
	return volatile.LoadUint32(&o.CH4_LLP0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_LLP0_CH4_LOC0(value uint32) {
	volatile.StoreUint32(&o.CH4_LLP0.Reg, volatile.LoadUint32(&o.CH4_LLP0.Reg)&^(0xffffffc0)|value<<6)
}
func (o *DMAC_Type) GetCH4_LLP0_CH4_LOC0() uint32 {
	return (volatile.LoadUint32(&o.CH4_LLP0.Reg) & 0xffffffc0) >> 6
}

// DMAC.CH4_LLP1: NA
func (o *DMAC_Type) SetCH4_LLP1(value uint32) {
	volatile.StoreUint32(&o.CH4_LLP1.Reg, value)
}
func (o *DMAC_Type) GetCH4_LLP1() uint32 {
	return volatile.LoadUint32(&o.CH4_LLP1.Reg)
}

// DMAC.CH4_STATUS0: NA
func (o *DMAC_Type) SetCH4_STATUS0_CH4_CMPLTD_BLK_TFR_SIZE(value uint32) {
	volatile.StoreUint32(&o.CH4_STATUS0.Reg, volatile.LoadUint32(&o.CH4_STATUS0.Reg)&^(0x3fffff)|value)
}
func (o *DMAC_Type) GetCH4_STATUS0_CH4_CMPLTD_BLK_TFR_SIZE() uint32 {
	return volatile.LoadUint32(&o.CH4_STATUS0.Reg) & 0x3fffff
}

// DMAC.CH4_STATUS1: NA
func (o *DMAC_Type) SetCH4_STATUS1_CH4_DATA_LEFT_IN_FIFO(value uint32) {
	volatile.StoreUint32(&o.CH4_STATUS1.Reg, volatile.LoadUint32(&o.CH4_STATUS1.Reg)&^(0x7fff)|value)
}
func (o *DMAC_Type) GetCH4_STATUS1_CH4_DATA_LEFT_IN_FIFO() uint32 {
	return volatile.LoadUint32(&o.CH4_STATUS1.Reg) & 0x7fff
}

// DMAC.CH4_SWHSSRC0: NA
func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC() uint32 {
	return volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_REQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_LST_SRC(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_LST_SRC() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_SWHSSRC0_CH4_SWHS_LST_SRC_WE(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSSRC0.Reg, volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH4_SWHSSRC0_CH4_SWHS_LST_SRC_WE() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSSRC0.Reg) & 0x20) >> 5
}

// DMAC.CH4_SWHSDST0: NA
func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_REQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_REQ_DST() uint32 {
	return volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_REQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_REQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_LST_DST(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_LST_DST() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_SWHSDST0_CH4_SWHS_LST_DST_WE(value uint32) {
	volatile.StoreUint32(&o.CH4_SWHSDST0.Reg, volatile.LoadUint32(&o.CH4_SWHSDST0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH4_SWHSDST0_CH4_SWHS_LST_DST_WE() uint32 {
	return (volatile.LoadUint32(&o.CH4_SWHSDST0.Reg) & 0x20) >> 5
}

// DMAC.CH4_BLK_TFR_RESUMEREQ0: NA
func (o *DMAC_Type) SetCH4_BLK_TFR_RESUMEREQ0_CH4_BLK_TFR_RESUMEREQ(value uint32) {
	volatile.StoreUint32(&o.CH4_BLK_TFR_RESUMEREQ0.Reg, volatile.LoadUint32(&o.CH4_BLK_TFR_RESUMEREQ0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_BLK_TFR_RESUMEREQ0_CH4_BLK_TFR_RESUMEREQ() uint32 {
	return volatile.LoadUint32(&o.CH4_BLK_TFR_RESUMEREQ0.Reg) & 0x1
}

// DMAC.CH4_AXI_ID0: NA
func (o *DMAC_Type) SetCH4_AXI_ID0_CH4_AXI_READ_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH4_AXI_ID0.Reg, volatile.LoadUint32(&o.CH4_AXI_ID0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_AXI_ID0_CH4_AXI_READ_ID_SUFFIX() uint32 {
	return volatile.LoadUint32(&o.CH4_AXI_ID0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_AXI_ID0_CH4_AXI_WRITE_ID_SUFFIX(value uint32) {
	volatile.StoreUint32(&o.CH4_AXI_ID0.Reg, volatile.LoadUint32(&o.CH4_AXI_ID0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH4_AXI_ID0_CH4_AXI_WRITE_ID_SUFFIX() uint32 {
	return (volatile.LoadUint32(&o.CH4_AXI_ID0.Reg) & 0x10000) >> 16
}

// DMAC.CH4_AXI_QOS0: NA
func (o *DMAC_Type) SetCH4_AXI_QOS0_CH4_AXI_AWQOS(value uint32) {
	volatile.StoreUint32(&o.CH4_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg)&^(0xf)|value)
}
func (o *DMAC_Type) GetCH4_AXI_QOS0_CH4_AXI_AWQOS() uint32 {
	return volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg) & 0xf
}
func (o *DMAC_Type) SetCH4_AXI_QOS0_CH4_AXI_ARQOS(value uint32) {
	volatile.StoreUint32(&o.CH4_AXI_QOS0.Reg, volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg)&^(0xf0)|value<<4)
}
func (o *DMAC_Type) GetCH4_AXI_QOS0_CH4_AXI_ARQOS() uint32 {
	return (volatile.LoadUint32(&o.CH4_AXI_QOS0.Reg) & 0xf0) >> 4
}

// DMAC.CH4_SSTAT0: NA
func (o *DMAC_Type) SetCH4_SSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH4_SSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH4_SSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH4_SSTAT0.Reg)
}

// DMAC.CH4_DSTAT0: NA
func (o *DMAC_Type) SetCH4_DSTAT0(value uint32) {
	volatile.StoreUint32(&o.CH4_DSTAT0.Reg, value)
}
func (o *DMAC_Type) GetCH4_DSTAT0() uint32 {
	return volatile.LoadUint32(&o.CH4_DSTAT0.Reg)
}

// DMAC.CH4_SSTATAR0: NA
func (o *DMAC_Type) SetCH4_SSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH4_SSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH4_SSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH4_SSTATAR0.Reg)
}

// DMAC.CH4_SSTATAR1: NA
func (o *DMAC_Type) SetCH4_SSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH4_SSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH4_SSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH4_SSTATAR1.Reg)
}

// DMAC.CH4_DSTATAR0: NA
func (o *DMAC_Type) SetCH4_DSTATAR0(value uint32) {
	volatile.StoreUint32(&o.CH4_DSTATAR0.Reg, value)
}
func (o *DMAC_Type) GetCH4_DSTATAR0() uint32 {
	return volatile.LoadUint32(&o.CH4_DSTATAR0.Reg)
}

// DMAC.CH4_DSTATAR1: NA
func (o *DMAC_Type) SetCH4_DSTATAR1(value uint32) {
	volatile.StoreUint32(&o.CH4_DSTATAR1.Reg, value)
}
func (o *DMAC_Type) GetCH4_DSTATAR1() uint32 {
	return volatile.LoadUint32(&o.CH4_DSTATAR1.Reg)
}

// DMAC.CH4_INTSTATUS_ENABLE0: NA
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH4_INTSTATUS_ENABLE1: NA
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH4_INTSTATUS0: NA
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH4_INTSTATUS0_CH4_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS0.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH4_INTSTATUS0_CH4_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS0.Reg) & 0x80000000) >> 31
}

// DMAC.CH4_INTSTATUS1: NA
func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSTATUS1.Reg, volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSTATUS1.Reg) & 0x8) >> 3
}

// DMAC.CH4_INTSIGNAL_ENABLE0: NA
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE0.Reg) & 0x80000000) >> 31
}

// DMAC.CH4_INTSIGNAL_ENABLE1: NA
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL() uint32 {
	return volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL(value uint32) {
	volatile.StoreUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg, volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTSIGNAL_ENABLE1.Reg) & 0x8) >> 3
}

// DMAC.CH4_INTCLEAR0: NA
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DMA_TFR_DONE_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DMA_TFR_DONE_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x8) >> 3
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DST_TRANSCOMP_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x10)|value<<4)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DST_TRANSCOMP_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x10) >> 4
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SRC_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x20)|value<<5)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SRC_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x20) >> 5
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DST_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x40)|value<<6)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DST_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x40) >> 6
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SRC_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x80)|value<<7)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SRC_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x80) >> 7
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_DST_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_DST_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x100) >> 8
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x200)|value<<9)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x200) >> 9
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x400)|value<<10)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x400) >> 10
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x800)|value<<11)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x800) >> 11
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x1000)|value<<12)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x1000) >> 12
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x2000) >> 13
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x4000)|value<<14)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x4000) >> 14
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x10000) >> 16
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x20000)|value<<17)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x20000) >> 17
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x40000)|value<<18)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x40000) >> 18
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x80000)|value<<19)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x80000) >> 19
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x100000)|value<<20)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x100000) >> 20
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x200000)|value<<21)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x200000) >> 21
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x2000000)|value<<25)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x2000000) >> 25
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x8000000)|value<<27)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x8000000) >> 27
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x10000000)|value<<28)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x10000000) >> 28
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_SUSPENDED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x20000000)|value<<29)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_SUSPENDED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x20000000) >> 29
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_DISABLED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x40000000)|value<<30)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_DISABLED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x40000000) >> 30
}
func (o *DMAC_Type) SetCH4_INTCLEAR0_CH4_CLEAR_CH_ABORTED_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR0.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg)&^(0x80000000)|value<<31)
}
func (o *DMAC_Type) GetCH4_INTCLEAR0_CH4_CLEAR_CH_ABORTED_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR0.Reg) & 0x80000000) >> 31
}

// DMAC.CH4_INTCLEAR1: NA
func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x1)|value)
}
func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT() uint32 {
	return volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x1
}
func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x2)|value<<1)
}
func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x2) >> 1
}
func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x4)|value<<2)
}
func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x4) >> 2
}
func (o *DMAC_Type) SetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT(value uint32) {
	volatile.StoreUint32(&o.CH4_INTCLEAR1.Reg, volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg)&^(0x8)|value<<3)
}
func (o *DMAC_Type) GetCH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT() uint32 {
	return (volatile.LoadUint32(&o.CH4_INTCLEAR1.Reg) & 0x8) >> 3
}

// Digital Signature
type DS_Type struct {
	Y_MEM           [128]volatile.Register32 // 0x0
	M_MEM           [128]volatile.Register32 // 0x200
	RB_MEM          [128]volatile.Register32 // 0x400
	BOX_MEM         [12]volatile.Register32  // 0x600
	IV_MEM          [4]volatile.Register32   // 0x630
	_               [448]byte
	X_MEM           [128]volatile.Register32 // 0x800
	Z_MEM           [128]volatile.Register32 // 0xA00
	_               [512]byte
	SET_START       volatile.Register32 // 0xE00
	SET_CONTINUE    volatile.Register32 // 0xE04
	SET_FINISH      volatile.Register32 // 0xE08
	QUERY_BUSY      volatile.Register32 // 0xE0C
	QUERY_KEY_WRONG volatile.Register32 // 0xE10
	QUERY_CHECK     volatile.Register32 // 0xE14
	_               [8]byte
	DATE            volatile.Register32 // 0xE20
}

// DS.SET_START: DS start control register
func (o *DS_Type) SetSET_START(value uint32) {
	volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value)
}
func (o *DS_Type) GetSET_START() uint32 {
	return volatile.LoadUint32(&o.SET_START.Reg) & 0x1
}

// DS.SET_CONTINUE: DS continue control register
func (o *DS_Type) SetSET_CONTINUE(value uint32) {
	volatile.StoreUint32(&o.SET_CONTINUE.Reg, volatile.LoadUint32(&o.SET_CONTINUE.Reg)&^(0x1)|value)
}
func (o *DS_Type) GetSET_CONTINUE() uint32 {
	return volatile.LoadUint32(&o.SET_CONTINUE.Reg) & 0x1
}

// DS.SET_FINISH: DS finish control register
func (o *DS_Type) SetSET_FINISH(value uint32) {
	volatile.StoreUint32(&o.SET_FINISH.Reg, volatile.LoadUint32(&o.SET_FINISH.Reg)&^(0x1)|value)
}
func (o *DS_Type) GetSET_FINISH() uint32 {
	return volatile.LoadUint32(&o.SET_FINISH.Reg) & 0x1
}

// DS.QUERY_BUSY: DS query busy register
func (o *DS_Type) SetQUERY_BUSY(value uint32) {
	volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value)
}
func (o *DS_Type) GetQUERY_BUSY() uint32 {
	return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1
}

// DS.QUERY_KEY_WRONG: DS query key-wrong counter register
func (o *DS_Type) SetQUERY_KEY_WRONG(value uint32) {
	volatile.StoreUint32(&o.QUERY_KEY_WRONG.Reg, volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg)&^(0xf)|value)
}
func (o *DS_Type) GetQUERY_KEY_WRONG() uint32 {
	return volatile.LoadUint32(&o.QUERY_KEY_WRONG.Reg) & 0xf
}

// DS.QUERY_CHECK: DS query check result register
func (o *DS_Type) SetQUERY_CHECK_MD_ERROR(value uint32) {
	volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x1)|value)
}
func (o *DS_Type) GetQUERY_CHECK_MD_ERROR() uint32 {
	return volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x1
}
func (o *DS_Type) SetQUERY_CHECK_PADDING_BAD(value uint32) {
	volatile.StoreUint32(&o.QUERY_CHECK.Reg, volatile.LoadUint32(&o.QUERY_CHECK.Reg)&^(0x2)|value<<1)
}
func (o *DS_Type) GetQUERY_CHECK_PADDING_BAD() uint32 {
	return (volatile.LoadUint32(&o.QUERY_CHECK.Reg) & 0x2) >> 1
}

// DS.DATE: DS version control register
func (o *DS_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value)
}
func (o *DS_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff
}

// MIPI Camera Interface Bridge
type DSI_BRG_Type struct {
	CLK_EN                    volatile.Register32 // 0x0
	EN                        volatile.Register32 // 0x4
	DMA_REQ_CFG               volatile.Register32 // 0x8
	RAW_NUM_CFG               volatile.Register32 // 0xC
	RAW_BUF_CREDIT_CTL        volatile.Register32 // 0x10
	FIFO_FLOW_STATUS          volatile.Register32 // 0x14
	PIXEL_TYPE                volatile.Register32 // 0x18
	DMA_BLOCK_INTERVAL        volatile.Register32 // 0x1C
	DMA_REQ_INTERVAL          volatile.Register32 // 0x20
	DPI_LCD_CTL               volatile.Register32 // 0x24
	DPI_RSV_DPI_DATA          volatile.Register32 // 0x28
	_                         [4]byte
	DPI_V_CFG0                volatile.Register32 // 0x30
	DPI_V_CFG1                volatile.Register32 // 0x34
	DPI_H_CFG0                volatile.Register32 // 0x38
	DPI_H_CFG1                volatile.Register32 // 0x3C
	DPI_MISC_CONFIG           volatile.Register32 // 0x40
	DPI_CONFIG_UPDATE         volatile.Register32 // 0x44
	_                         [8]byte
	INT_ENA                   volatile.Register32 // 0x50
	INT_CLR                   volatile.Register32 // 0x54
	INT_RAW                   volatile.Register32 // 0x58
	INT_ST                    volatile.Register32 // 0x5C
	HOST_BIST_CTL             volatile.Register32 // 0x60
	HOST_TRIGGER_REV          volatile.Register32 // 0x64
	BLK_RAW_NUM_CFG           volatile.Register32 // 0x68
	DMA_FRAME_INTERVAL        volatile.Register32 // 0x6C
	MEM_AUX_CTRL              volatile.Register32 // 0x70
	RDN_ECO_CS                volatile.Register32 // 0x74
	RDN_ECO_LOW               volatile.Register32 // 0x78
	RDN_ECO_HIGH              volatile.Register32 // 0x7C
	HOST_CTRL                 volatile.Register32 // 0x80
	MEM_CLK_CTRL              volatile.Register32 // 0x84
	DMA_FLOW_CTRL             volatile.Register32 // 0x88
	RAW_BUF_ALMOST_EMPTY_THRD volatile.Register32 // 0x8C
	YUV_CFG                   volatile.Register32 // 0x90
	PHY_LP_LOOPBACK_CTRL      volatile.Register32 // 0x94
	PHY_HS_LOOPBACK_CTRL      volatile.Register32 // 0x98
	PHY_LOOPBACK_CNT          volatile.Register32 // 0x9C
}

// DSI_BRG.CLK_EN: dsi bridge clk control register
func (o *DSI_BRG_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetCLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1
}

// DSI_BRG.EN: dsi bridge en register
func (o *DSI_BRG_Type) SetEN_DSI_EN(value uint32) {
	volatile.StoreUint32(&o.EN.Reg, volatile.LoadUint32(&o.EN.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetEN_DSI_EN() uint32 {
	return volatile.LoadUint32(&o.EN.Reg) & 0x1
}

// DSI_BRG.DMA_REQ_CFG: dsi bridge dma burst len register
func (o *DSI_BRG_Type) SetDMA_REQ_CFG_DMA_BURST_LEN(value uint32) {
	volatile.StoreUint32(&o.DMA_REQ_CFG.Reg, volatile.LoadUint32(&o.DMA_REQ_CFG.Reg)&^(0xfff)|value)
}
func (o *DSI_BRG_Type) GetDMA_REQ_CFG_DMA_BURST_LEN() uint32 {
	return volatile.LoadUint32(&o.DMA_REQ_CFG.Reg) & 0xfff
}

// DSI_BRG.RAW_NUM_CFG: dsi bridge raw number control register
func (o *DSI_BRG_Type) SetRAW_NUM_CFG_RAW_NUM_TOTAL(value uint32) {
	volatile.StoreUint32(&o.RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.RAW_NUM_CFG.Reg)&^(0x3fffff)|value)
}
func (o *DSI_BRG_Type) GetRAW_NUM_CFG_RAW_NUM_TOTAL() uint32 {
	return volatile.LoadUint32(&o.RAW_NUM_CFG.Reg) & 0x3fffff
}
func (o *DSI_BRG_Type) SetRAW_NUM_CFG_UNALIGN_64BIT_EN(value uint32) {
	volatile.StoreUint32(&o.RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.RAW_NUM_CFG.Reg)&^(0x400000)|value<<22)
}
func (o *DSI_BRG_Type) GetRAW_NUM_CFG_UNALIGN_64BIT_EN() uint32 {
	return (volatile.LoadUint32(&o.RAW_NUM_CFG.Reg) & 0x400000) >> 22
}
func (o *DSI_BRG_Type) SetRAW_NUM_CFG_RAW_NUM_TOTAL_SET(value uint32) {
	volatile.StoreUint32(&o.RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.RAW_NUM_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *DSI_BRG_Type) GetRAW_NUM_CFG_RAW_NUM_TOTAL_SET() uint32 {
	return (volatile.LoadUint32(&o.RAW_NUM_CFG.Reg) & 0x80000000) >> 31
}

// DSI_BRG.RAW_BUF_CREDIT_CTL: dsi bridge credit register
func (o *DSI_BRG_Type) SetRAW_BUF_CREDIT_CTL_CREDIT_THRD(value uint32) {
	volatile.StoreUint32(&o.RAW_BUF_CREDIT_CTL.Reg, volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg)&^(0x7fff)|value)
}
func (o *DSI_BRG_Type) GetRAW_BUF_CREDIT_CTL_CREDIT_THRD() uint32 {
	return volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg) & 0x7fff
}
func (o *DSI_BRG_Type) SetRAW_BUF_CREDIT_CTL_CREDIT_BURST_THRD(value uint32) {
	volatile.StoreUint32(&o.RAW_BUF_CREDIT_CTL.Reg, volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg)&^(0x7fff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetRAW_BUF_CREDIT_CTL_CREDIT_BURST_THRD() uint32 {
	return (volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg) & 0x7fff0000) >> 16
}
func (o *DSI_BRG_Type) SetRAW_BUF_CREDIT_CTL_CREDIT_RESET(value uint32) {
	volatile.StoreUint32(&o.RAW_BUF_CREDIT_CTL.Reg, volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg)&^(0x80000000)|value<<31)
}
func (o *DSI_BRG_Type) GetRAW_BUF_CREDIT_CTL_CREDIT_RESET() uint32 {
	return (volatile.LoadUint32(&o.RAW_BUF_CREDIT_CTL.Reg) & 0x80000000) >> 31
}

// DSI_BRG.FIFO_FLOW_STATUS: dsi bridge raw buffer depth register
func (o *DSI_BRG_Type) SetFIFO_FLOW_STATUS_RAW_BUF_DEPTH(value uint32) {
	volatile.StoreUint32(&o.FIFO_FLOW_STATUS.Reg, volatile.LoadUint32(&o.FIFO_FLOW_STATUS.Reg)&^(0x3fff)|value)
}
func (o *DSI_BRG_Type) GetFIFO_FLOW_STATUS_RAW_BUF_DEPTH() uint32 {
	return volatile.LoadUint32(&o.FIFO_FLOW_STATUS.Reg) & 0x3fff
}

// DSI_BRG.PIXEL_TYPE: dsi bridge dpi type control register
func (o *DSI_BRG_Type) SetPIXEL_TYPE_RAW_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIXEL_TYPE.Reg, volatile.LoadUint32(&o.PIXEL_TYPE.Reg)&^(0xf)|value)
}
func (o *DSI_BRG_Type) GetPIXEL_TYPE_RAW_TYPE() uint32 {
	return volatile.LoadUint32(&o.PIXEL_TYPE.Reg) & 0xf
}
func (o *DSI_BRG_Type) SetPIXEL_TYPE_DPI_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIXEL_TYPE.Reg, volatile.LoadUint32(&o.PIXEL_TYPE.Reg)&^(0x30)|value<<4)
}
func (o *DSI_BRG_Type) GetPIXEL_TYPE_DPI_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIXEL_TYPE.Reg) & 0x30) >> 4
}
func (o *DSI_BRG_Type) SetPIXEL_TYPE_DATA_IN_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIXEL_TYPE.Reg, volatile.LoadUint32(&o.PIXEL_TYPE.Reg)&^(0x40)|value<<6)
}
func (o *DSI_BRG_Type) GetPIXEL_TYPE_DATA_IN_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIXEL_TYPE.Reg) & 0x40) >> 6
}

// DSI_BRG.DMA_BLOCK_INTERVAL: dsi bridge dma block interval control register
func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL_DMA_BLOCK_SLOT(value uint32) {
	volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0x3ff)|value)
}
func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL_DMA_BLOCK_SLOT() uint32 {
	return volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0x3ff
}
func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0xffffc00)|value<<10)
}
func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL() uint32 {
	return (volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0xffffc00) >> 10
}
func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL_RAW_NUM_TOTAL_AUTO_RELOAD(value uint32) {
	volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0x10000000)|value<<28)
}
func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL_RAW_NUM_TOTAL_AUTO_RELOAD() uint32 {
	return (volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0x10000000) >> 28
}
func (o *DSI_BRG_Type) SetDMA_BLOCK_INTERVAL_EN(value uint32) {
	volatile.StoreUint32(&o.DMA_BLOCK_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg)&^(0x20000000)|value<<29)
}
func (o *DSI_BRG_Type) GetDMA_BLOCK_INTERVAL_EN() uint32 {
	return (volatile.LoadUint32(&o.DMA_BLOCK_INTERVAL.Reg) & 0x20000000) >> 29
}

// DSI_BRG.DMA_REQ_INTERVAL: dsi bridge dma req interval control register
func (o *DSI_BRG_Type) SetDMA_REQ_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.DMA_REQ_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg)&^(0xffff)|value)
}
func (o *DSI_BRG_Type) GetDMA_REQ_INTERVAL() uint32 {
	return volatile.LoadUint32(&o.DMA_REQ_INTERVAL.Reg) & 0xffff
}

// DSI_BRG.DPI_LCD_CTL: dsi bridge dpi signal control register
func (o *DSI_BRG_Type) SetDPI_LCD_CTL_DPISHUTDN(value uint32) {
	volatile.StoreUint32(&o.DPI_LCD_CTL.Reg, volatile.LoadUint32(&o.DPI_LCD_CTL.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetDPI_LCD_CTL_DPISHUTDN() uint32 {
	return volatile.LoadUint32(&o.DPI_LCD_CTL.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetDPI_LCD_CTL_DPICOLORM(value uint32) {
	volatile.StoreUint32(&o.DPI_LCD_CTL.Reg, volatile.LoadUint32(&o.DPI_LCD_CTL.Reg)&^(0x2)|value<<1)
}
func (o *DSI_BRG_Type) GetDPI_LCD_CTL_DPICOLORM() uint32 {
	return (volatile.LoadUint32(&o.DPI_LCD_CTL.Reg) & 0x2) >> 1
}
func (o *DSI_BRG_Type) SetDPI_LCD_CTL_DPIUPDATECFG(value uint32) {
	volatile.StoreUint32(&o.DPI_LCD_CTL.Reg, volatile.LoadUint32(&o.DPI_LCD_CTL.Reg)&^(0x4)|value<<2)
}
func (o *DSI_BRG_Type) GetDPI_LCD_CTL_DPIUPDATECFG() uint32 {
	return (volatile.LoadUint32(&o.DPI_LCD_CTL.Reg) & 0x4) >> 2
}

// DSI_BRG.DPI_RSV_DPI_DATA: dsi bridge dpi reserved data register
func (o *DSI_BRG_Type) SetDPI_RSV_DPI_DATA_DPI_RSV_DATA(value uint32) {
	volatile.StoreUint32(&o.DPI_RSV_DPI_DATA.Reg, volatile.LoadUint32(&o.DPI_RSV_DPI_DATA.Reg)&^(0x3fffffff)|value)
}
func (o *DSI_BRG_Type) GetDPI_RSV_DPI_DATA_DPI_RSV_DATA() uint32 {
	return volatile.LoadUint32(&o.DPI_RSV_DPI_DATA.Reg) & 0x3fffffff
}

// DSI_BRG.DPI_V_CFG0: dsi bridge dpi v config register 0
func (o *DSI_BRG_Type) SetDPI_V_CFG0_VTOTAL(value uint32) {
	volatile.StoreUint32(&o.DPI_V_CFG0.Reg, volatile.LoadUint32(&o.DPI_V_CFG0.Reg)&^(0xfff)|value)
}
func (o *DSI_BRG_Type) GetDPI_V_CFG0_VTOTAL() uint32 {
	return volatile.LoadUint32(&o.DPI_V_CFG0.Reg) & 0xfff
}
func (o *DSI_BRG_Type) SetDPI_V_CFG0_VDISP(value uint32) {
	volatile.StoreUint32(&o.DPI_V_CFG0.Reg, volatile.LoadUint32(&o.DPI_V_CFG0.Reg)&^(0xfff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetDPI_V_CFG0_VDISP() uint32 {
	return (volatile.LoadUint32(&o.DPI_V_CFG0.Reg) & 0xfff0000) >> 16
}

// DSI_BRG.DPI_V_CFG1: dsi bridge dpi v config register 1
func (o *DSI_BRG_Type) SetDPI_V_CFG1_VBANK(value uint32) {
	volatile.StoreUint32(&o.DPI_V_CFG1.Reg, volatile.LoadUint32(&o.DPI_V_CFG1.Reg)&^(0xfff)|value)
}
func (o *DSI_BRG_Type) GetDPI_V_CFG1_VBANK() uint32 {
	return volatile.LoadUint32(&o.DPI_V_CFG1.Reg) & 0xfff
}
func (o *DSI_BRG_Type) SetDPI_V_CFG1_VSYNC(value uint32) {
	volatile.StoreUint32(&o.DPI_V_CFG1.Reg, volatile.LoadUint32(&o.DPI_V_CFG1.Reg)&^(0xfff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetDPI_V_CFG1_VSYNC() uint32 {
	return (volatile.LoadUint32(&o.DPI_V_CFG1.Reg) & 0xfff0000) >> 16
}

// DSI_BRG.DPI_H_CFG0: dsi bridge dpi h config register 0
func (o *DSI_BRG_Type) SetDPI_H_CFG0_HTOTAL(value uint32) {
	volatile.StoreUint32(&o.DPI_H_CFG0.Reg, volatile.LoadUint32(&o.DPI_H_CFG0.Reg)&^(0xfff)|value)
}
func (o *DSI_BRG_Type) GetDPI_H_CFG0_HTOTAL() uint32 {
	return volatile.LoadUint32(&o.DPI_H_CFG0.Reg) & 0xfff
}
func (o *DSI_BRG_Type) SetDPI_H_CFG0_HDISP(value uint32) {
	volatile.StoreUint32(&o.DPI_H_CFG0.Reg, volatile.LoadUint32(&o.DPI_H_CFG0.Reg)&^(0xfff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetDPI_H_CFG0_HDISP() uint32 {
	return (volatile.LoadUint32(&o.DPI_H_CFG0.Reg) & 0xfff0000) >> 16
}

// DSI_BRG.DPI_H_CFG1: dsi bridge dpi h config register 1
func (o *DSI_BRG_Type) SetDPI_H_CFG1_HBANK(value uint32) {
	volatile.StoreUint32(&o.DPI_H_CFG1.Reg, volatile.LoadUint32(&o.DPI_H_CFG1.Reg)&^(0xfff)|value)
}
func (o *DSI_BRG_Type) GetDPI_H_CFG1_HBANK() uint32 {
	return volatile.LoadUint32(&o.DPI_H_CFG1.Reg) & 0xfff
}
func (o *DSI_BRG_Type) SetDPI_H_CFG1_HSYNC(value uint32) {
	volatile.StoreUint32(&o.DPI_H_CFG1.Reg, volatile.LoadUint32(&o.DPI_H_CFG1.Reg)&^(0xfff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetDPI_H_CFG1_HSYNC() uint32 {
	return (volatile.LoadUint32(&o.DPI_H_CFG1.Reg) & 0xfff0000) >> 16
}

// DSI_BRG.DPI_MISC_CONFIG: dsi_bridge dpi misc config register
func (o *DSI_BRG_Type) SetDPI_MISC_CONFIG_DPI_EN(value uint32) {
	volatile.StoreUint32(&o.DPI_MISC_CONFIG.Reg, volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetDPI_MISC_CONFIG_DPI_EN() uint32 {
	return volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetDPI_MISC_CONFIG_FIFO_UNDERRUN_DISCARD_VCNT(value uint32) {
	volatile.StoreUint32(&o.DPI_MISC_CONFIG.Reg, volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg)&^(0xfff0)|value<<4)
}
func (o *DSI_BRG_Type) GetDPI_MISC_CONFIG_FIFO_UNDERRUN_DISCARD_VCNT() uint32 {
	return (volatile.LoadUint32(&o.DPI_MISC_CONFIG.Reg) & 0xfff0) >> 4
}

// DSI_BRG.DPI_CONFIG_UPDATE: dsi_bridge dpi config update register
func (o *DSI_BRG_Type) SetDPI_CONFIG_UPDATE(value uint32) {
	volatile.StoreUint32(&o.DPI_CONFIG_UPDATE.Reg, volatile.LoadUint32(&o.DPI_CONFIG_UPDATE.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetDPI_CONFIG_UPDATE() uint32 {
	return volatile.LoadUint32(&o.DPI_CONFIG_UPDATE.Reg) & 0x1
}

// DSI_BRG.INT_ENA: dsi_bridge interrupt enable register
func (o *DSI_BRG_Type) SetINT_ENA_UNDERRUN_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetINT_ENA_UNDERRUN_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}

// DSI_BRG.INT_CLR: dsi_bridge interrupt clear register
func (o *DSI_BRG_Type) SetINT_CLR_UNDERRUN_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetINT_CLR_UNDERRUN_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}

// DSI_BRG.INT_RAW: dsi_bridge raw interrupt register
func (o *DSI_BRG_Type) SetINT_RAW_UNDERRUN_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetINT_RAW_UNDERRUN_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}

// DSI_BRG.INT_ST: dsi_bridge masked interrupt register
func (o *DSI_BRG_Type) SetINT_ST_UNDERRUN_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetINT_ST_UNDERRUN_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}

// DSI_BRG.HOST_BIST_CTL: dsi_bridge host bist control register
func (o *DSI_BRG_Type) SetHOST_BIST_CTL_BISTOK(value uint32) {
	volatile.StoreUint32(&o.HOST_BIST_CTL.Reg, volatile.LoadUint32(&o.HOST_BIST_CTL.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetHOST_BIST_CTL_BISTOK() uint32 {
	return volatile.LoadUint32(&o.HOST_BIST_CTL.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetHOST_BIST_CTL_BISTON(value uint32) {
	volatile.StoreUint32(&o.HOST_BIST_CTL.Reg, volatile.LoadUint32(&o.HOST_BIST_CTL.Reg)&^(0x2)|value<<1)
}
func (o *DSI_BRG_Type) GetHOST_BIST_CTL_BISTON() uint32 {
	return (volatile.LoadUint32(&o.HOST_BIST_CTL.Reg) & 0x2) >> 1
}

// DSI_BRG.HOST_TRIGGER_REV: dsi_bridge host trigger reverse control register
func (o *DSI_BRG_Type) SetHOST_TRIGGER_REV_TX_TRIGGER_REV_EN(value uint32) {
	volatile.StoreUint32(&o.HOST_TRIGGER_REV.Reg, volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetHOST_TRIGGER_REV_TX_TRIGGER_REV_EN() uint32 {
	return volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetHOST_TRIGGER_REV_RX_TRIGGER_REV_EN(value uint32) {
	volatile.StoreUint32(&o.HOST_TRIGGER_REV.Reg, volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg)&^(0x2)|value<<1)
}
func (o *DSI_BRG_Type) GetHOST_TRIGGER_REV_RX_TRIGGER_REV_EN() uint32 {
	return (volatile.LoadUint32(&o.HOST_TRIGGER_REV.Reg) & 0x2) >> 1
}

// DSI_BRG.BLK_RAW_NUM_CFG: dsi_bridge block raw number control register
func (o *DSI_BRG_Type) SetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL(value uint32) {
	volatile.StoreUint32(&o.BLK_RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg)&^(0x3fffff)|value)
}
func (o *DSI_BRG_Type) GetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL() uint32 {
	return volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg) & 0x3fffff
}
func (o *DSI_BRG_Type) SetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_SET(value uint32) {
	volatile.StoreUint32(&o.BLK_RAW_NUM_CFG.Reg, volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *DSI_BRG_Type) GetBLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_SET() uint32 {
	return (volatile.LoadUint32(&o.BLK_RAW_NUM_CFG.Reg) & 0x80000000) >> 31
}

// DSI_BRG.DMA_FRAME_INTERVAL: dsi_bridge dam frame interval control register
func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL_DMA_FRAME_SLOT(value uint32) {
	volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0x3ff)|value)
}
func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL_DMA_FRAME_SLOT() uint32 {
	return volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0x3ff
}
func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0xffffc00)|value<<10)
}
func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL() uint32 {
	return (volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0xffffc00) >> 10
}
func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL_DMA_MULTIBLK_EN(value uint32) {
	volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0x10000000)|value<<28)
}
func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL_DMA_MULTIBLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0x10000000) >> 28
}
func (o *DSI_BRG_Type) SetDMA_FRAME_INTERVAL_EN(value uint32) {
	volatile.StoreUint32(&o.DMA_FRAME_INTERVAL.Reg, volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg)&^(0x20000000)|value<<29)
}
func (o *DSI_BRG_Type) GetDMA_FRAME_INTERVAL_EN() uint32 {
	return (volatile.LoadUint32(&o.DMA_FRAME_INTERVAL.Reg) & 0x20000000) >> 29
}

// DSI_BRG.MEM_AUX_CTRL: dsi_bridge mem aux control register
func (o *DSI_BRG_Type) SetMEM_AUX_CTRL_DSI_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL.Reg)&^(0x3fff)|value)
}
func (o *DSI_BRG_Type) GetMEM_AUX_CTRL_DSI_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.MEM_AUX_CTRL.Reg) & 0x3fff
}

// DSI_BRG.RDN_ECO_CS: dsi_bridge rdn eco cs register
func (o *DSI_BRG_Type) SetRDN_ECO_CS_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetRDN_ECO_CS_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetRDN_ECO_CS_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *DSI_BRG_Type) GetRDN_ECO_CS_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1
}

// DSI_BRG.RDN_ECO_LOW: dsi_bridge rdn eco all low register
func (o *DSI_BRG_Type) SetRDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value)
}
func (o *DSI_BRG_Type) GetRDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg)
}

// DSI_BRG.RDN_ECO_HIGH: dsi_bridge rdn eco all high register
func (o *DSI_BRG_Type) SetRDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value)
}
func (o *DSI_BRG_Type) GetRDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg)
}

// DSI_BRG.HOST_CTRL: dsi_bridge host control register
func (o *DSI_BRG_Type) SetHOST_CTRL_DSI_CFG_REF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.HOST_CTRL.Reg, volatile.LoadUint32(&o.HOST_CTRL.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetHOST_CTRL_DSI_CFG_REF_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.HOST_CTRL.Reg) & 0x1
}

// DSI_BRG.MEM_CLK_CTRL: dsi_bridge mem force on control register
func (o *DSI_BRG_Type) SetMEM_CLK_CTRL_DSI_BRIDGE_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.MEM_CLK_CTRL.Reg, volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetMEM_CLK_CTRL_DSI_BRIDGE_MEM_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetMEM_CLK_CTRL_DSI_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.MEM_CLK_CTRL.Reg, volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *DSI_BRG_Type) GetMEM_CLK_CTRL_DSI_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.MEM_CLK_CTRL.Reg) & 0x2) >> 1
}

// DSI_BRG.DMA_FLOW_CTRL: dsi_bridge dma flow controller register
func (o *DSI_BRG_Type) SetDMA_FLOW_CTRL_DSI_DMA_FLOW_CONTROLLER(value uint32) {
	volatile.StoreUint32(&o.DMA_FLOW_CTRL.Reg, volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetDMA_FLOW_CTRL_DSI_DMA_FLOW_CONTROLLER() uint32 {
	return volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetDMA_FLOW_CTRL_DMA_FLOW_MULTIBLK_NUM(value uint32) {
	volatile.StoreUint32(&o.DMA_FLOW_CTRL.Reg, volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg)&^(0xf0)|value<<4)
}
func (o *DSI_BRG_Type) GetDMA_FLOW_CTRL_DMA_FLOW_MULTIBLK_NUM() uint32 {
	return (volatile.LoadUint32(&o.DMA_FLOW_CTRL.Reg) & 0xf0) >> 4
}

// DSI_BRG.RAW_BUF_ALMOST_EMPTY_THRD: dsi_bridge buffer empty threshold register
func (o *DSI_BRG_Type) SetRAW_BUF_ALMOST_EMPTY_THRD_DSI_RAW_BUF_ALMOST_EMPTY_THRD(value uint32) {
	volatile.StoreUint32(&o.RAW_BUF_ALMOST_EMPTY_THRD.Reg, volatile.LoadUint32(&o.RAW_BUF_ALMOST_EMPTY_THRD.Reg)&^(0x7ff)|value)
}
func (o *DSI_BRG_Type) GetRAW_BUF_ALMOST_EMPTY_THRD_DSI_RAW_BUF_ALMOST_EMPTY_THRD() uint32 {
	return volatile.LoadUint32(&o.RAW_BUF_ALMOST_EMPTY_THRD.Reg) & 0x7ff
}

// DSI_BRG.YUV_CFG: dsi_bridge yuv format config register
func (o *DSI_BRG_Type) SetYUV_CFG_PROTOCAL(value uint32) {
	volatile.StoreUint32(&o.YUV_CFG.Reg, volatile.LoadUint32(&o.YUV_CFG.Reg)&^(0x1)|value)
}
func (o *DSI_BRG_Type) GetYUV_CFG_PROTOCAL() uint32 {
	return volatile.LoadUint32(&o.YUV_CFG.Reg) & 0x1
}
func (o *DSI_BRG_Type) SetYUV_CFG_YUV_PIX_ENDIAN(value uint32) {
	volatile.StoreUint32(&o.YUV_CFG.Reg, volatile.LoadUint32(&o.YUV_CFG.Reg)&^(0x2)|value<<1)
}
func (o *DSI_BRG_Type) GetYUV_CFG_YUV_PIX_ENDIAN() uint32 {
	return (volatile.LoadUint32(&o.YUV_CFG.Reg) & 0x2) >> 1
}
func (o *DSI_BRG_Type) SetYUV_CFG_YUV422_FORMAT(value uint32) {
	volatile.StoreUint32(&o.YUV_CFG.Reg, volatile.LoadUint32(&o.YUV_CFG.Reg)&^(0xc)|value<<2)
}
func (o *DSI_BRG_Type) GetYUV_CFG_YUV422_FORMAT() uint32 {
	return (volatile.LoadUint32(&o.YUV_CFG.Reg) & 0xc) >> 2
}

// DSI_BRG.PHY_LP_LOOPBACK_CTRL: dsi phy lp_loopback test ctrl
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_1(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0xff)|value)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_1() uint32 {
	return volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0xff
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_1(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x100) >> 8
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_1(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x200) >> 9
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_1(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x400) >> 10
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_1(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x800) >> 11
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_0(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0xff0000) >> 16
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_0(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x1000000) >> 24
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_0(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x2000000) >> 25
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_0(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x4000000)|value<<26)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x4000000) >> 26
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_0(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x8000000)|value<<27)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x8000000) >> 27
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x10000000) >> 28
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_DONE(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_DONE() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x20000000) >> 29
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_EN(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_EN() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x40000000) >> 30
}
func (o *DSI_BRG_Type) SetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_OK(value uint32) {
	volatile.StoreUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *DSI_BRG_Type) GetPHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_OK() uint32 {
	return (volatile.LoadUint32(&o.PHY_LP_LOOPBACK_CTRL.Reg) & 0x80000000) >> 31
}

// DSI_BRG.PHY_HS_LOOPBACK_CTRL: dsi phy hp_loopback test ctrl
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_1(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0xff)|value)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_1() uint32 {
	return volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0xff
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_1(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x100) >> 8
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_1(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_1() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x200) >> 9
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_0(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0xff0000) >> 16
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_0(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x1000000) >> 24
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_0(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_0() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x2000000) >> 25
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTHSCLK(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x8000000)|value<<27)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTHSCLK() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x8000000) >> 27
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x10000000) >> 28
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_DONE(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_DONE() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x20000000) >> 29
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_EN(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_EN() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x40000000) >> 30
}
func (o *DSI_BRG_Type) SetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_OK(value uint32) {
	volatile.StoreUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg, volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *DSI_BRG_Type) GetPHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_OK() uint32 {
	return (volatile.LoadUint32(&o.PHY_HS_LOOPBACK_CTRL.Reg) & 0x80000000) >> 31
}

// DSI_BRG.PHY_LOOPBACK_CNT: loopback test cnt
func (o *DSI_BRG_Type) SetPHY_LOOPBACK_CNT_PHY_HS_CHECK_CNT_TH(value uint32) {
	volatile.StoreUint32(&o.PHY_LOOPBACK_CNT.Reg, volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg)&^(0xff)|value)
}
func (o *DSI_BRG_Type) GetPHY_LOOPBACK_CNT_PHY_HS_CHECK_CNT_TH() uint32 {
	return volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg) & 0xff
}
func (o *DSI_BRG_Type) SetPHY_LOOPBACK_CNT_PHY_LP_CHECK_CNT_TH(value uint32) {
	volatile.StoreUint32(&o.PHY_LOOPBACK_CNT.Reg, volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg)&^(0xff0000)|value<<16)
}
func (o *DSI_BRG_Type) GetPHY_LOOPBACK_CNT_PHY_LP_CHECK_CNT_TH() uint32 {
	return (volatile.LoadUint32(&o.PHY_LOOPBACK_CNT.Reg) & 0xff0000) >> 16
}

// MIPI Display Interface Host
type DSI_HOST_Type struct {
	VERSION               volatile.Register32 // 0x0
	PWR_UP                volatile.Register32 // 0x4
	CLKMGR_CFG            volatile.Register32 // 0x8
	DPI_VCID              volatile.Register32 // 0xC
	DPI_COLOR_CODING      volatile.Register32 // 0x10
	DPI_CFG_POL           volatile.Register32 // 0x14
	DPI_LP_CMD_TIM        volatile.Register32 // 0x18
	DBI_VCID              volatile.Register32 // 0x1C
	DBI_CFG               volatile.Register32 // 0x20
	DBI_PARTITIONING_EN   volatile.Register32 // 0x24
	DBI_CMDSIZE           volatile.Register32 // 0x28
	PCKHDL_CFG            volatile.Register32 // 0x2C
	GEN_VCID              volatile.Register32 // 0x30
	MODE_CFG              volatile.Register32 // 0x34
	VID_MODE_CFG          volatile.Register32 // 0x38
	VID_PKT_SIZE          volatile.Register32 // 0x3C
	VID_NUM_CHUNKS        volatile.Register32 // 0x40
	VID_NULL_SIZE         volatile.Register32 // 0x44
	VID_HSA_TIME          volatile.Register32 // 0x48
	VID_HBP_TIME          volatile.Register32 // 0x4C
	VID_HLINE_TIME        volatile.Register32 // 0x50
	VID_VSA_LINES         volatile.Register32 // 0x54
	VID_VBP_LINES         volatile.Register32 // 0x58
	VID_VFP_LINES         volatile.Register32 // 0x5C
	VID_VACTIVE_LINES     volatile.Register32 // 0x60
	EDPI_CMD_SIZE         volatile.Register32 // 0x64
	CMD_MODE_CFG          volatile.Register32 // 0x68
	GEN_HDR               volatile.Register32 // 0x6C
	GEN_PLD_DATA          volatile.Register32 // 0x70
	CMD_PKT_STATUS        volatile.Register32 // 0x74
	TO_CNT_CFG            volatile.Register32 // 0x78
	HS_RD_TO_CNT          volatile.Register32 // 0x7C
	LP_RD_TO_CNT          volatile.Register32 // 0x80
	HS_WR_TO_CNT          volatile.Register32 // 0x84
	LP_WR_TO_CNT          volatile.Register32 // 0x88
	BTA_TO_CNT            volatile.Register32 // 0x8C
	SDF_3D                volatile.Register32 // 0x90
	LPCLK_CTRL            volatile.Register32 // 0x94
	PHY_TMR_LPCLK_CFG     volatile.Register32 // 0x98
	PHY_TMR_CFG           volatile.Register32 // 0x9C
	PHY_RSTZ              volatile.Register32 // 0xA0
	PHY_IF_CFG            volatile.Register32 // 0xA4
	PHY_ULPS_CTRL         volatile.Register32 // 0xA8
	PHY_TX_TRIGGERS       volatile.Register32 // 0xAC
	PHY_STATUS            volatile.Register32 // 0xB0
	PHY_TST_CTRL0         volatile.Register32 // 0xB4
	PHY_TST_CTRL1         volatile.Register32 // 0xB8
	INT_ST0               volatile.Register32 // 0xBC
	INT_ST1               volatile.Register32 // 0xC0
	INT_MSK0              volatile.Register32 // 0xC4
	INT_MSK1              volatile.Register32 // 0xC8
	PHY_CAL               volatile.Register32 // 0xCC
	_                     [8]byte
	INT_FORCE0            volatile.Register32 // 0xD8
	INT_FORCE1            volatile.Register32 // 0xDC
	_                     [16]byte
	DSC_PARAMETER         volatile.Register32 // 0xF0
	PHY_TMR_RD_CFG        volatile.Register32 // 0xF4
	_                     [8]byte
	VID_SHADOW_CTRL       volatile.Register32 // 0x100
	_                     [8]byte
	DPI_VCID_ACT          volatile.Register32 // 0x10C
	DPI_COLOR_CODING_ACT  volatile.Register32 // 0x110
	_                     [4]byte
	DPI_LP_CMD_TIM_ACT    volatile.Register32 // 0x118
	EDPI_TE_HW_CFG        volatile.Register32 // 0x11C
	_                     [24]byte
	VID_MODE_CFG_ACT      volatile.Register32 // 0x138
	VID_PKT_SIZE_ACT      volatile.Register32 // 0x13C
	VID_NUM_CHUNKS_ACT    volatile.Register32 // 0x140
	VID_NULL_SIZE_ACT     volatile.Register32 // 0x144
	VID_HSA_TIME_ACT      volatile.Register32 // 0x148
	VID_HBP_TIME_ACT      volatile.Register32 // 0x14C
	VID_HLINE_TIME_ACT    volatile.Register32 // 0x150
	VID_VSA_LINES_ACT     volatile.Register32 // 0x154
	VID_VBP_LINES_ACT     volatile.Register32 // 0x158
	VID_VFP_LINES_ACT     volatile.Register32 // 0x15C
	VID_VACTIVE_LINES_ACT volatile.Register32 // 0x160
	_                     [4]byte
	VID_PKT_STATUS        volatile.Register32 // 0x168
	_                     [36]byte
	SDF_3D_ACT            volatile.Register32 // 0x190
}

// DSI_HOST.VERSION: NA
func (o *DSI_HOST_Type) SetVERSION(value uint32) {
	volatile.StoreUint32(&o.VERSION.Reg, value)
}
func (o *DSI_HOST_Type) GetVERSION() uint32 {
	return volatile.LoadUint32(&o.VERSION.Reg)
}

// DSI_HOST.PWR_UP: NA
func (o *DSI_HOST_Type) SetPWR_UP_SHUTDOWNZ(value uint32) {
	volatile.StoreUint32(&o.PWR_UP.Reg, volatile.LoadUint32(&o.PWR_UP.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetPWR_UP_SHUTDOWNZ() uint32 {
	return volatile.LoadUint32(&o.PWR_UP.Reg) & 0x1
}

// DSI_HOST.CLKMGR_CFG: NA
func (o *DSI_HOST_Type) SetCLKMGR_CFG_TX_ESC_CLK_DIVISION(value uint32) {
	volatile.StoreUint32(&o.CLKMGR_CFG.Reg, volatile.LoadUint32(&o.CLKMGR_CFG.Reg)&^(0xff)|value)
}
func (o *DSI_HOST_Type) GetCLKMGR_CFG_TX_ESC_CLK_DIVISION() uint32 {
	return volatile.LoadUint32(&o.CLKMGR_CFG.Reg) & 0xff
}
func (o *DSI_HOST_Type) SetCLKMGR_CFG_TO_CLK_DIVISION(value uint32) {
	volatile.StoreUint32(&o.CLKMGR_CFG.Reg, volatile.LoadUint32(&o.CLKMGR_CFG.Reg)&^(0xff00)|value<<8)
}
func (o *DSI_HOST_Type) GetCLKMGR_CFG_TO_CLK_DIVISION() uint32 {
	return (volatile.LoadUint32(&o.CLKMGR_CFG.Reg) & 0xff00) >> 8
}

// DSI_HOST.DPI_VCID: NA
func (o *DSI_HOST_Type) SetDPI_VCID(value uint32) {
	volatile.StoreUint32(&o.DPI_VCID.Reg, volatile.LoadUint32(&o.DPI_VCID.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetDPI_VCID() uint32 {
	return volatile.LoadUint32(&o.DPI_VCID.Reg) & 0x3
}

// DSI_HOST.DPI_COLOR_CODING: NA
func (o *DSI_HOST_Type) SetDPI_COLOR_CODING(value uint32) {
	volatile.StoreUint32(&o.DPI_COLOR_CODING.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg)&^(0xf)|value)
}
func (o *DSI_HOST_Type) GetDPI_COLOR_CODING() uint32 {
	return volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg) & 0xf
}
func (o *DSI_HOST_Type) SetDPI_COLOR_CODING_LOOSELY18_EN(value uint32) {
	volatile.StoreUint32(&o.DPI_COLOR_CODING.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetDPI_COLOR_CODING_LOOSELY18_EN() uint32 {
	return (volatile.LoadUint32(&o.DPI_COLOR_CODING.Reg) & 0x100) >> 8
}

// DSI_HOST.DPI_CFG_POL: NA
func (o *DSI_HOST_Type) SetDPI_CFG_POL_DATAEN_ACTIVE_LOW(value uint32) {
	volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetDPI_CFG_POL_DATAEN_ACTIVE_LOW() uint32 {
	return volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetDPI_CFG_POL_VSYNC_ACTIVE_LOW(value uint32) {
	volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetDPI_CFG_POL_VSYNC_ACTIVE_LOW() uint32 {
	return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetDPI_CFG_POL_HSYNC_ACTIVE_LOW(value uint32) {
	volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetDPI_CFG_POL_HSYNC_ACTIVE_LOW() uint32 {
	return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetDPI_CFG_POL_SHUTD_ACTIVE_LOW(value uint32) {
	volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetDPI_CFG_POL_SHUTD_ACTIVE_LOW() uint32 {
	return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetDPI_CFG_POL_COLORM_ACTIVE_LOW(value uint32) {
	volatile.StoreUint32(&o.DPI_CFG_POL.Reg, volatile.LoadUint32(&o.DPI_CFG_POL.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetDPI_CFG_POL_COLORM_ACTIVE_LOW() uint32 {
	return (volatile.LoadUint32(&o.DPI_CFG_POL.Reg) & 0x10) >> 4
}

// DSI_HOST.DPI_LP_CMD_TIM: NA
func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_INVACT_LPCMD_TIME(value uint32) {
	volatile.StoreUint32(&o.DPI_LP_CMD_TIM.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg)&^(0xff)|value)
}
func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_INVACT_LPCMD_TIME() uint32 {
	return volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg) & 0xff
}
func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME(value uint32) {
	volatile.StoreUint32(&o.DPI_LP_CMD_TIM.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg)&^(0xff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME() uint32 {
	return (volatile.LoadUint32(&o.DPI_LP_CMD_TIM.Reg) & 0xff0000) >> 16
}

// DSI_HOST.DBI_VCID: NA
func (o *DSI_HOST_Type) SetDBI_VCID(value uint32) {
	volatile.StoreUint32(&o.DBI_VCID.Reg, volatile.LoadUint32(&o.DBI_VCID.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetDBI_VCID() uint32 {
	return volatile.LoadUint32(&o.DBI_VCID.Reg) & 0x3
}

// DSI_HOST.DBI_CFG: NA
func (o *DSI_HOST_Type) SetDBI_CFG_IN_DBI_CONF(value uint32) {
	volatile.StoreUint32(&o.DBI_CFG.Reg, volatile.LoadUint32(&o.DBI_CFG.Reg)&^(0xf)|value)
}
func (o *DSI_HOST_Type) GetDBI_CFG_IN_DBI_CONF() uint32 {
	return volatile.LoadUint32(&o.DBI_CFG.Reg) & 0xf
}
func (o *DSI_HOST_Type) SetDBI_CFG_OUT_DBI_CONF(value uint32) {
	volatile.StoreUint32(&o.DBI_CFG.Reg, volatile.LoadUint32(&o.DBI_CFG.Reg)&^(0xf00)|value<<8)
}
func (o *DSI_HOST_Type) GetDBI_CFG_OUT_DBI_CONF() uint32 {
	return (volatile.LoadUint32(&o.DBI_CFG.Reg) & 0xf00) >> 8
}
func (o *DSI_HOST_Type) SetDBI_CFG_LUT_SIZE_CONF(value uint32) {
	volatile.StoreUint32(&o.DBI_CFG.Reg, volatile.LoadUint32(&o.DBI_CFG.Reg)&^(0x30000)|value<<16)
}
func (o *DSI_HOST_Type) GetDBI_CFG_LUT_SIZE_CONF() uint32 {
	return (volatile.LoadUint32(&o.DBI_CFG.Reg) & 0x30000) >> 16
}

// DSI_HOST.DBI_PARTITIONING_EN: NA
func (o *DSI_HOST_Type) SetDBI_PARTITIONING_EN_PARTITIONING_EN(value uint32) {
	volatile.StoreUint32(&o.DBI_PARTITIONING_EN.Reg, volatile.LoadUint32(&o.DBI_PARTITIONING_EN.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetDBI_PARTITIONING_EN_PARTITIONING_EN() uint32 {
	return volatile.LoadUint32(&o.DBI_PARTITIONING_EN.Reg) & 0x1
}

// DSI_HOST.DBI_CMDSIZE: NA
func (o *DSI_HOST_Type) SetDBI_CMDSIZE_WR_CMD_SIZE(value uint32) {
	volatile.StoreUint32(&o.DBI_CMDSIZE.Reg, volatile.LoadUint32(&o.DBI_CMDSIZE.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetDBI_CMDSIZE_WR_CMD_SIZE() uint32 {
	return volatile.LoadUint32(&o.DBI_CMDSIZE.Reg) & 0xffff
}
func (o *DSI_HOST_Type) SetDBI_CMDSIZE_ALLOWED_CMD_SIZE(value uint32) {
	volatile.StoreUint32(&o.DBI_CMDSIZE.Reg, volatile.LoadUint32(&o.DBI_CMDSIZE.Reg)&^(0xffff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetDBI_CMDSIZE_ALLOWED_CMD_SIZE() uint32 {
	return (volatile.LoadUint32(&o.DBI_CMDSIZE.Reg) & 0xffff0000) >> 16
}

// DSI_HOST.PCKHDL_CFG: NA
func (o *DSI_HOST_Type) SetPCKHDL_CFG_EOTP_TX_EN(value uint32) {
	volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetPCKHDL_CFG_EOTP_TX_EN() uint32 {
	return volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetPCKHDL_CFG_EOTP_RX_EN(value uint32) {
	volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetPCKHDL_CFG_EOTP_RX_EN() uint32 {
	return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetPCKHDL_CFG_BTA_EN(value uint32) {
	volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetPCKHDL_CFG_BTA_EN() uint32 {
	return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetPCKHDL_CFG_ECC_RX_EN(value uint32) {
	volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetPCKHDL_CFG_ECC_RX_EN() uint32 {
	return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetPCKHDL_CFG_CRC_RX_EN(value uint32) {
	volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetPCKHDL_CFG_CRC_RX_EN() uint32 {
	return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetPCKHDL_CFG_EOTP_TX_LP_EN(value uint32) {
	volatile.StoreUint32(&o.PCKHDL_CFG.Reg, volatile.LoadUint32(&o.PCKHDL_CFG.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetPCKHDL_CFG_EOTP_TX_LP_EN() uint32 {
	return (volatile.LoadUint32(&o.PCKHDL_CFG.Reg) & 0x20) >> 5
}

// DSI_HOST.GEN_VCID: NA
func (o *DSI_HOST_Type) SetGEN_VCID_RX(value uint32) {
	volatile.StoreUint32(&o.GEN_VCID.Reg, volatile.LoadUint32(&o.GEN_VCID.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetGEN_VCID_RX() uint32 {
	return volatile.LoadUint32(&o.GEN_VCID.Reg) & 0x3
}
func (o *DSI_HOST_Type) SetGEN_VCID_TEAR_AUTO(value uint32) {
	volatile.StoreUint32(&o.GEN_VCID.Reg, volatile.LoadUint32(&o.GEN_VCID.Reg)&^(0x300)|value<<8)
}
func (o *DSI_HOST_Type) GetGEN_VCID_TEAR_AUTO() uint32 {
	return (volatile.LoadUint32(&o.GEN_VCID.Reg) & 0x300) >> 8
}
func (o *DSI_HOST_Type) SetGEN_VCID_TX_AUTO(value uint32) {
	volatile.StoreUint32(&o.GEN_VCID.Reg, volatile.LoadUint32(&o.GEN_VCID.Reg)&^(0x30000)|value<<16)
}
func (o *DSI_HOST_Type) GetGEN_VCID_TX_AUTO() uint32 {
	return (volatile.LoadUint32(&o.GEN_VCID.Reg) & 0x30000) >> 16
}

// DSI_HOST.MODE_CFG: NA
func (o *DSI_HOST_Type) SetMODE_CFG_CMD_VIDEO_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE_CFG.Reg, volatile.LoadUint32(&o.MODE_CFG.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetMODE_CFG_CMD_VIDEO_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE_CFG.Reg) & 0x1
}

// DSI_HOST.VID_MODE_CFG: NA
func (o *DSI_HOST_Type) SetVID_MODE_CFG_VID_MODE_TYPE(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_VID_MODE_TYPE() uint32 {
	return volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x3
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VSA_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VSA_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VBP_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VBP_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VFP_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VFP_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_VACT_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_VACT_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_HBP_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_HBP_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_HFP_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_HFP_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x2000) >> 13
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_FRAME_BTA_ACK_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x4000)|value<<14)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_FRAME_BTA_ACK_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x4000) >> 14
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_LP_CMD_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x8000)|value<<15)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_LP_CMD_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x8000) >> 15
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_VPG_EN(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_VPG_EN() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x10000) >> 16
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_VPG_MODE(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x100000)|value<<20)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_VPG_MODE() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x100000) >> 20
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_VPG_ORIENTATION(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG.Reg, volatile.LoadUint32(&o.VID_MODE_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_VPG_ORIENTATION() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG.Reg) & 0x1000000) >> 24
}

// DSI_HOST.VID_PKT_SIZE: NA
func (o *DSI_HOST_Type) SetVID_PKT_SIZE(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_SIZE.Reg, volatile.LoadUint32(&o.VID_PKT_SIZE.Reg)&^(0x3fff)|value)
}
func (o *DSI_HOST_Type) GetVID_PKT_SIZE() uint32 {
	return volatile.LoadUint32(&o.VID_PKT_SIZE.Reg) & 0x3fff
}

// DSI_HOST.VID_NUM_CHUNKS: NA
func (o *DSI_HOST_Type) SetVID_NUM_CHUNKS(value uint32) {
	volatile.StoreUint32(&o.VID_NUM_CHUNKS.Reg, volatile.LoadUint32(&o.VID_NUM_CHUNKS.Reg)&^(0x1fff)|value)
}
func (o *DSI_HOST_Type) GetVID_NUM_CHUNKS() uint32 {
	return volatile.LoadUint32(&o.VID_NUM_CHUNKS.Reg) & 0x1fff
}

// DSI_HOST.VID_NULL_SIZE: NA
func (o *DSI_HOST_Type) SetVID_NULL_SIZE(value uint32) {
	volatile.StoreUint32(&o.VID_NULL_SIZE.Reg, volatile.LoadUint32(&o.VID_NULL_SIZE.Reg)&^(0x1fff)|value)
}
func (o *DSI_HOST_Type) GetVID_NULL_SIZE() uint32 {
	return volatile.LoadUint32(&o.VID_NULL_SIZE.Reg) & 0x1fff
}

// DSI_HOST.VID_HSA_TIME: NA
func (o *DSI_HOST_Type) SetVID_HSA_TIME(value uint32) {
	volatile.StoreUint32(&o.VID_HSA_TIME.Reg, volatile.LoadUint32(&o.VID_HSA_TIME.Reg)&^(0xfff)|value)
}
func (o *DSI_HOST_Type) GetVID_HSA_TIME() uint32 {
	return volatile.LoadUint32(&o.VID_HSA_TIME.Reg) & 0xfff
}

// DSI_HOST.VID_HBP_TIME: NA
func (o *DSI_HOST_Type) SetVID_HBP_TIME(value uint32) {
	volatile.StoreUint32(&o.VID_HBP_TIME.Reg, volatile.LoadUint32(&o.VID_HBP_TIME.Reg)&^(0xfff)|value)
}
func (o *DSI_HOST_Type) GetVID_HBP_TIME() uint32 {
	return volatile.LoadUint32(&o.VID_HBP_TIME.Reg) & 0xfff
}

// DSI_HOST.VID_HLINE_TIME: NA
func (o *DSI_HOST_Type) SetVID_HLINE_TIME(value uint32) {
	volatile.StoreUint32(&o.VID_HLINE_TIME.Reg, volatile.LoadUint32(&o.VID_HLINE_TIME.Reg)&^(0x7fff)|value)
}
func (o *DSI_HOST_Type) GetVID_HLINE_TIME() uint32 {
	return volatile.LoadUint32(&o.VID_HLINE_TIME.Reg) & 0x7fff
}

// DSI_HOST.VID_VSA_LINES: NA
func (o *DSI_HOST_Type) SetVID_VSA_LINES_VSA_LINES(value uint32) {
	volatile.StoreUint32(&o.VID_VSA_LINES.Reg, volatile.LoadUint32(&o.VID_VSA_LINES.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetVID_VSA_LINES_VSA_LINES() uint32 {
	return volatile.LoadUint32(&o.VID_VSA_LINES.Reg) & 0x3ff
}

// DSI_HOST.VID_VBP_LINES: NA
func (o *DSI_HOST_Type) SetVID_VBP_LINES_VBP_LINES(value uint32) {
	volatile.StoreUint32(&o.VID_VBP_LINES.Reg, volatile.LoadUint32(&o.VID_VBP_LINES.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetVID_VBP_LINES_VBP_LINES() uint32 {
	return volatile.LoadUint32(&o.VID_VBP_LINES.Reg) & 0x3ff
}

// DSI_HOST.VID_VFP_LINES: NA
func (o *DSI_HOST_Type) SetVID_VFP_LINES_VFP_LINES(value uint32) {
	volatile.StoreUint32(&o.VID_VFP_LINES.Reg, volatile.LoadUint32(&o.VID_VFP_LINES.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetVID_VFP_LINES_VFP_LINES() uint32 {
	return volatile.LoadUint32(&o.VID_VFP_LINES.Reg) & 0x3ff
}

// DSI_HOST.VID_VACTIVE_LINES: NA
func (o *DSI_HOST_Type) SetVID_VACTIVE_LINES_V_ACTIVE_LINES(value uint32) {
	volatile.StoreUint32(&o.VID_VACTIVE_LINES.Reg, volatile.LoadUint32(&o.VID_VACTIVE_LINES.Reg)&^(0x3fff)|value)
}
func (o *DSI_HOST_Type) GetVID_VACTIVE_LINES_V_ACTIVE_LINES() uint32 {
	return volatile.LoadUint32(&o.VID_VACTIVE_LINES.Reg) & 0x3fff
}

// DSI_HOST.EDPI_CMD_SIZE: NA
func (o *DSI_HOST_Type) SetEDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE(value uint32) {
	volatile.StoreUint32(&o.EDPI_CMD_SIZE.Reg, volatile.LoadUint32(&o.EDPI_CMD_SIZE.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetEDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE() uint32 {
	return volatile.LoadUint32(&o.EDPI_CMD_SIZE.Reg) & 0xffff
}

// DSI_HOST.CMD_MODE_CFG: NA
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_TEAR_FX_EN(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_TEAR_FX_EN() uint32 {
	return volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_ACK_RQST_EN(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_ACK_RQST_EN() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SW_0P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SW_0P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SW_1P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SW_1P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SW_2P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SW_2P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SR_0P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SR_0P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SR_1P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SR_1P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_SR_2P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_SR_2P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x2000) >> 13
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_GEN_LW_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x4000)|value<<14)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_GEN_LW_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x4000) >> 14
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_SW_0P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_SW_0P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x10000) >> 16
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_SW_1P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x20000)|value<<17)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_SW_1P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x20000) >> 17
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_SR_0P_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x40000)|value<<18)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_SR_0P_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x40000) >> 18
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_DCS_LW_TX(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_DCS_LW_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x80000) >> 19
}
func (o *DSI_HOST_Type) SetCMD_MODE_CFG_MAX_RD_PKT_SIZE(value uint32) {
	volatile.StoreUint32(&o.CMD_MODE_CFG.Reg, volatile.LoadUint32(&o.CMD_MODE_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *DSI_HOST_Type) GetCMD_MODE_CFG_MAX_RD_PKT_SIZE() uint32 {
	return (volatile.LoadUint32(&o.CMD_MODE_CFG.Reg) & 0x1000000) >> 24
}

// DSI_HOST.GEN_HDR: NA
func (o *DSI_HOST_Type) SetGEN_HDR_GEN_DT(value uint32) {
	volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0x3f)|value)
}
func (o *DSI_HOST_Type) GetGEN_HDR_GEN_DT() uint32 {
	return volatile.LoadUint32(&o.GEN_HDR.Reg) & 0x3f
}
func (o *DSI_HOST_Type) SetGEN_HDR_GEN_VC(value uint32) {
	volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0xc0)|value<<6)
}
func (o *DSI_HOST_Type) GetGEN_HDR_GEN_VC() uint32 {
	return (volatile.LoadUint32(&o.GEN_HDR.Reg) & 0xc0) >> 6
}
func (o *DSI_HOST_Type) SetGEN_HDR_GEN_WC_LSBYTE(value uint32) {
	volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0xff00)|value<<8)
}
func (o *DSI_HOST_Type) GetGEN_HDR_GEN_WC_LSBYTE() uint32 {
	return (volatile.LoadUint32(&o.GEN_HDR.Reg) & 0xff00) >> 8
}
func (o *DSI_HOST_Type) SetGEN_HDR_GEN_WC_MSBYTE(value uint32) {
	volatile.StoreUint32(&o.GEN_HDR.Reg, volatile.LoadUint32(&o.GEN_HDR.Reg)&^(0xff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetGEN_HDR_GEN_WC_MSBYTE() uint32 {
	return (volatile.LoadUint32(&o.GEN_HDR.Reg) & 0xff0000) >> 16
}

// DSI_HOST.GEN_PLD_DATA: NA
func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B1(value uint32) {
	volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff)|value)
}
func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B1() uint32 {
	return volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff
}
func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B2(value uint32) {
	volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff00)|value<<8)
}
func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B2() uint32 {
	return (volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff00) >> 8
}
func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B3(value uint32) {
	volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B3() uint32 {
	return (volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff0000) >> 16
}
func (o *DSI_HOST_Type) SetGEN_PLD_DATA_GEN_PLD_B4(value uint32) {
	volatile.StoreUint32(&o.GEN_PLD_DATA.Reg, volatile.LoadUint32(&o.GEN_PLD_DATA.Reg)&^(0xff000000)|value<<24)
}
func (o *DSI_HOST_Type) GetGEN_PLD_DATA_GEN_PLD_B4() uint32 {
	return (volatile.LoadUint32(&o.GEN_PLD_DATA.Reg) & 0xff000000) >> 24
}

// DSI_HOST.CMD_PKT_STATUS: NA
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_CMD_EMPTY(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_CMD_EMPTY() uint32 {
	return volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_CMD_FULL(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_CMD_FULL() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_W_EMPTY(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_W_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_W_FULL(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_W_FULL() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_R_EMPTY(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_R_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_PLD_R_FULL(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_PLD_R_FULL() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_RD_CMD_BUSY(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_RD_CMD_BUSY() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x10000) >> 16
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_CMD_FULL(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x20000)|value<<17)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_CMD_FULL() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x20000) >> 17
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x40000)|value<<18)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x40000) >> 18
}
func (o *DSI_HOST_Type) SetCMD_PKT_STATUS_GEN_BUFF_PLD_FULL(value uint32) {
	volatile.StoreUint32(&o.CMD_PKT_STATUS.Reg, volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetCMD_PKT_STATUS_GEN_BUFF_PLD_FULL() uint32 {
	return (volatile.LoadUint32(&o.CMD_PKT_STATUS.Reg) & 0x80000) >> 19
}

// DSI_HOST.TO_CNT_CFG: NA
func (o *DSI_HOST_Type) SetTO_CNT_CFG_LPRX_TO_CNT(value uint32) {
	volatile.StoreUint32(&o.TO_CNT_CFG.Reg, volatile.LoadUint32(&o.TO_CNT_CFG.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetTO_CNT_CFG_LPRX_TO_CNT() uint32 {
	return volatile.LoadUint32(&o.TO_CNT_CFG.Reg) & 0xffff
}
func (o *DSI_HOST_Type) SetTO_CNT_CFG_HSTX_TO_CNT(value uint32) {
	volatile.StoreUint32(&o.TO_CNT_CFG.Reg, volatile.LoadUint32(&o.TO_CNT_CFG.Reg)&^(0xffff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetTO_CNT_CFG_HSTX_TO_CNT() uint32 {
	return (volatile.LoadUint32(&o.TO_CNT_CFG.Reg) & 0xffff0000) >> 16
}

// DSI_HOST.HS_RD_TO_CNT: NA
func (o *DSI_HOST_Type) SetHS_RD_TO_CNT(value uint32) {
	volatile.StoreUint32(&o.HS_RD_TO_CNT.Reg, volatile.LoadUint32(&o.HS_RD_TO_CNT.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetHS_RD_TO_CNT() uint32 {
	return volatile.LoadUint32(&o.HS_RD_TO_CNT.Reg) & 0xffff
}

// DSI_HOST.LP_RD_TO_CNT: NA
func (o *DSI_HOST_Type) SetLP_RD_TO_CNT(value uint32) {
	volatile.StoreUint32(&o.LP_RD_TO_CNT.Reg, volatile.LoadUint32(&o.LP_RD_TO_CNT.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetLP_RD_TO_CNT() uint32 {
	return volatile.LoadUint32(&o.LP_RD_TO_CNT.Reg) & 0xffff
}

// DSI_HOST.HS_WR_TO_CNT: NA
func (o *DSI_HOST_Type) SetHS_WR_TO_CNT(value uint32) {
	volatile.StoreUint32(&o.HS_WR_TO_CNT.Reg, volatile.LoadUint32(&o.HS_WR_TO_CNT.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetHS_WR_TO_CNT() uint32 {
	return volatile.LoadUint32(&o.HS_WR_TO_CNT.Reg) & 0xffff
}

// DSI_HOST.LP_WR_TO_CNT: NA
func (o *DSI_HOST_Type) SetLP_WR_TO_CNT(value uint32) {
	volatile.StoreUint32(&o.LP_WR_TO_CNT.Reg, volatile.LoadUint32(&o.LP_WR_TO_CNT.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetLP_WR_TO_CNT() uint32 {
	return volatile.LoadUint32(&o.LP_WR_TO_CNT.Reg) & 0xffff
}

// DSI_HOST.BTA_TO_CNT: NA
func (o *DSI_HOST_Type) SetBTA_TO_CNT(value uint32) {
	volatile.StoreUint32(&o.BTA_TO_CNT.Reg, volatile.LoadUint32(&o.BTA_TO_CNT.Reg)&^(0xffff)|value)
}
func (o *DSI_HOST_Type) GetBTA_TO_CNT() uint32 {
	return volatile.LoadUint32(&o.BTA_TO_CNT.Reg) & 0xffff
}

// DSI_HOST.SDF_3D: NA
func (o *DSI_HOST_Type) SetSDF_3D_MODE_3D(value uint32) {
	volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetSDF_3D_MODE_3D() uint32 {
	return volatile.LoadUint32(&o.SDF_3D.Reg) & 0x3
}
func (o *DSI_HOST_Type) SetSDF_3D_FORMAT_3D(value uint32) {
	volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0xc)|value<<2)
}
func (o *DSI_HOST_Type) GetSDF_3D_FORMAT_3D() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0xc) >> 2
}
func (o *DSI_HOST_Type) SetSDF_3D_SECOND_VSYNC(value uint32) {
	volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetSDF_3D_SECOND_VSYNC() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetSDF_3D_RIGHT_FIRST(value uint32) {
	volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetSDF_3D_RIGHT_FIRST() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetSDF_3D_SEND_3D_CFG(value uint32) {
	volatile.StoreUint32(&o.SDF_3D.Reg, volatile.LoadUint32(&o.SDF_3D.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetSDF_3D_SEND_3D_CFG() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D.Reg) & 0x10000) >> 16
}

// DSI_HOST.LPCLK_CTRL: NA
func (o *DSI_HOST_Type) SetLPCLK_CTRL_PHY_TXREQUESTCLKHS(value uint32) {
	volatile.StoreUint32(&o.LPCLK_CTRL.Reg, volatile.LoadUint32(&o.LPCLK_CTRL.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetLPCLK_CTRL_PHY_TXREQUESTCLKHS() uint32 {
	return volatile.LoadUint32(&o.LPCLK_CTRL.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetLPCLK_CTRL_AUTO_CLKLANE_CTRL(value uint32) {
	volatile.StoreUint32(&o.LPCLK_CTRL.Reg, volatile.LoadUint32(&o.LPCLK_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetLPCLK_CTRL_AUTO_CLKLANE_CTRL() uint32 {
	return (volatile.LoadUint32(&o.LPCLK_CTRL.Reg) & 0x2) >> 1
}

// DSI_HOST.PHY_TMR_LPCLK_CFG: NA
func (o *DSI_HOST_Type) SetPHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME(value uint32) {
	volatile.StoreUint32(&o.PHY_TMR_LPCLK_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetPHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME() uint32 {
	return volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg) & 0x3ff
}
func (o *DSI_HOST_Type) SetPHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME(value uint32) {
	volatile.StoreUint32(&o.PHY_TMR_LPCLK_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg)&^(0x3ff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetPHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME() uint32 {
	return (volatile.LoadUint32(&o.PHY_TMR_LPCLK_CFG.Reg) & 0x3ff0000) >> 16
}

// DSI_HOST.PHY_TMR_CFG: NA
func (o *DSI_HOST_Type) SetPHY_TMR_CFG_PHY_LP2HS_TIME(value uint32) {
	volatile.StoreUint32(&o.PHY_TMR_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_CFG.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetPHY_TMR_CFG_PHY_LP2HS_TIME() uint32 {
	return volatile.LoadUint32(&o.PHY_TMR_CFG.Reg) & 0x3ff
}
func (o *DSI_HOST_Type) SetPHY_TMR_CFG_PHY_HS2LP_TIME(value uint32) {
	volatile.StoreUint32(&o.PHY_TMR_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_CFG.Reg)&^(0x3ff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetPHY_TMR_CFG_PHY_HS2LP_TIME() uint32 {
	return (volatile.LoadUint32(&o.PHY_TMR_CFG.Reg) & 0x3ff0000) >> 16
}

// DSI_HOST.PHY_RSTZ: NA
func (o *DSI_HOST_Type) SetPHY_RSTZ_PHY_SHUTDOWNZ(value uint32) {
	volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetPHY_RSTZ_PHY_SHUTDOWNZ() uint32 {
	return volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetPHY_RSTZ(value uint32) {
	volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetPHY_RSTZ() uint32 {
	return (volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetPHY_RSTZ_PHY_ENABLECLK(value uint32) {
	volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetPHY_RSTZ_PHY_ENABLECLK() uint32 {
	return (volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetPHY_RSTZ_PHY_FORCEPLL(value uint32) {
	volatile.StoreUint32(&o.PHY_RSTZ.Reg, volatile.LoadUint32(&o.PHY_RSTZ.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetPHY_RSTZ_PHY_FORCEPLL() uint32 {
	return (volatile.LoadUint32(&o.PHY_RSTZ.Reg) & 0x8) >> 3
}

// DSI_HOST.PHY_IF_CFG: NA
func (o *DSI_HOST_Type) SetPHY_IF_CFG_N_LANES(value uint32) {
	volatile.StoreUint32(&o.PHY_IF_CFG.Reg, volatile.LoadUint32(&o.PHY_IF_CFG.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetPHY_IF_CFG_N_LANES() uint32 {
	return volatile.LoadUint32(&o.PHY_IF_CFG.Reg) & 0x3
}
func (o *DSI_HOST_Type) SetPHY_IF_CFG_PHY_STOP_WAIT_TIME(value uint32) {
	volatile.StoreUint32(&o.PHY_IF_CFG.Reg, volatile.LoadUint32(&o.PHY_IF_CFG.Reg)&^(0xff00)|value<<8)
}
func (o *DSI_HOST_Type) GetPHY_IF_CFG_PHY_STOP_WAIT_TIME() uint32 {
	return (volatile.LoadUint32(&o.PHY_IF_CFG.Reg) & 0xff00) >> 8
}

// DSI_HOST.PHY_ULPS_CTRL: NA
func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXREQULPSCLK(value uint32) {
	volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXREQULPSCLK() uint32 {
	return volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXEXITULPSCLK(value uint32) {
	volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXEXITULPSCLK() uint32 {
	return (volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXREQULPSLAN(value uint32) {
	volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXREQULPSLAN() uint32 {
	return (volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetPHY_ULPS_CTRL_PHY_TXEXITULPSLAN(value uint32) {
	volatile.StoreUint32(&o.PHY_ULPS_CTRL.Reg, volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetPHY_ULPS_CTRL_PHY_TXEXITULPSLAN() uint32 {
	return (volatile.LoadUint32(&o.PHY_ULPS_CTRL.Reg) & 0x8) >> 3
}

// DSI_HOST.PHY_TX_TRIGGERS: NA
func (o *DSI_HOST_Type) SetPHY_TX_TRIGGERS(value uint32) {
	volatile.StoreUint32(&o.PHY_TX_TRIGGERS.Reg, volatile.LoadUint32(&o.PHY_TX_TRIGGERS.Reg)&^(0xf)|value)
}
func (o *DSI_HOST_Type) GetPHY_TX_TRIGGERS() uint32 {
	return volatile.LoadUint32(&o.PHY_TX_TRIGGERS.Reg) & 0xf
}

// DSI_HOST.PHY_STATUS: NA
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_LOCK(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_LOCK() uint32 {
	return volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_STOPSTATECLKLANE(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_STOPSTATECLKLANE() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_ULPSACTIVENOTCLK(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_ULPSACTIVENOTCLK() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_STOPSTATE0LANE(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_STOPSTATE0LANE() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_ULPSACTIVENOT0LANE(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_ULPSACTIVENOT0LANE() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_RXULPSESC0LANE(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_RXULPSESC0LANE() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_STOPSTATE1LANE(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_STOPSTATE1LANE() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetPHY_STATUS_PHY_ULPSACTIVENOT1LANE(value uint32) {
	volatile.StoreUint32(&o.PHY_STATUS.Reg, volatile.LoadUint32(&o.PHY_STATUS.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetPHY_STATUS_PHY_ULPSACTIVENOT1LANE() uint32 {
	return (volatile.LoadUint32(&o.PHY_STATUS.Reg) & 0x100) >> 8
}

// DSI_HOST.PHY_TST_CTRL0: NA
func (o *DSI_HOST_Type) SetPHY_TST_CTRL0_PHY_TESTCLR(value uint32) {
	volatile.StoreUint32(&o.PHY_TST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetPHY_TST_CTRL0_PHY_TESTCLR() uint32 {
	return volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetPHY_TST_CTRL0_PHY_TESTCLK(value uint32) {
	volatile.StoreUint32(&o.PHY_TST_CTRL0.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetPHY_TST_CTRL0_PHY_TESTCLK() uint32 {
	return (volatile.LoadUint32(&o.PHY_TST_CTRL0.Reg) & 0x2) >> 1
}

// DSI_HOST.PHY_TST_CTRL1: NA
func (o *DSI_HOST_Type) SetPHY_TST_CTRL1_PHY_TESTDIN(value uint32) {
	volatile.StoreUint32(&o.PHY_TST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg)&^(0xff)|value)
}
func (o *DSI_HOST_Type) GetPHY_TST_CTRL1_PHY_TESTDIN() uint32 {
	return volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg) & 0xff
}
func (o *DSI_HOST_Type) SetPHY_TST_CTRL1_PHT_TESTDOUT(value uint32) {
	volatile.StoreUint32(&o.PHY_TST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg)&^(0xff00)|value<<8)
}
func (o *DSI_HOST_Type) GetPHY_TST_CTRL1_PHT_TESTDOUT() uint32 {
	return (volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg) & 0xff00) >> 8
}
func (o *DSI_HOST_Type) SetPHY_TST_CTRL1_PHY_TESTEN(value uint32) {
	volatile.StoreUint32(&o.PHY_TST_CTRL1.Reg, volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetPHY_TST_CTRL1_PHY_TESTEN() uint32 {
	return (volatile.LoadUint32(&o.PHY_TST_CTRL1.Reg) & 0x10000) >> 16
}

// DSI_HOST.INT_ST0: NA
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_0(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_0() uint32 {
	return volatile.LoadUint32(&o.INT_ST0.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_1(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_2(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_3(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_4(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_5(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_5() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_6(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_6() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_7(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_7() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_8(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_8() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_9(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_9() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_10(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_10() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_11(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_11() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_12(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_12() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_13(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x2000)|value<<13)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_13() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x2000) >> 13
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_14(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x4000)|value<<14)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_14() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x4000) >> 14
}
func (o *DSI_HOST_Type) SetINT_ST0_ACK_WITH_ERR_15(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x8000)|value<<15)
}
func (o *DSI_HOST_Type) GetINT_ST0_ACK_WITH_ERR_15() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x8000) >> 15
}
func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_0(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_0() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x10000) >> 16
}
func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_1(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x20000)|value<<17)
}
func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x20000) >> 17
}
func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_2(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x40000)|value<<18)
}
func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_2() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x40000) >> 18
}
func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_3(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_3() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x80000) >> 19
}
func (o *DSI_HOST_Type) SetINT_ST0_DPHY_ERRORS_4(value uint32) {
	volatile.StoreUint32(&o.INT_ST0.Reg, volatile.LoadUint32(&o.INT_ST0.Reg)&^(0x100000)|value<<20)
}
func (o *DSI_HOST_Type) GetINT_ST0_DPHY_ERRORS_4() uint32 {
	return (volatile.LoadUint32(&o.INT_ST0.Reg) & 0x100000) >> 20
}

// DSI_HOST.INT_ST1: NA
func (o *DSI_HOST_Type) SetINT_ST1_TO_HS_TX(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetINT_ST1_TO_HS_TX() uint32 {
	return volatile.LoadUint32(&o.INT_ST1.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetINT_ST1_TO_LP_RX(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetINT_ST1_TO_LP_RX() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetINT_ST1_ECC_SINGLE_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetINT_ST1_ECC_SINGLE_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetINT_ST1_ECC_MILTI_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetINT_ST1_ECC_MILTI_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetINT_ST1_CRC_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetINT_ST1_CRC_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetINT_ST1_PKT_SIZE_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetINT_ST1_PKT_SIZE_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetINT_ST1_EOPT_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetINT_ST1_EOPT_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetINT_ST1_DPI_PLD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetINT_ST1_DPI_PLD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetINT_ST1_GEN_CMD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetINT_ST1_GEN_CMD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_SEND_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_SEND_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_RD_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_RD_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetINT_ST1_GEN_PLD_RECEV_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetINT_ST1_GEN_PLD_RECEV_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetINT_ST1_DPI_BUFF_PLD_UNDER(value uint32) {
	volatile.StoreUint32(&o.INT_ST1.Reg, volatile.LoadUint32(&o.INT_ST1.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetINT_ST1_DPI_BUFF_PLD_UNDER() uint32 {
	return (volatile.LoadUint32(&o.INT_ST1.Reg) & 0x80000) >> 19
}

// DSI_HOST.INT_MSK0: NA
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_0() uint32 {
	return volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_5(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_5() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_6(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_6() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_7(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_7() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_8(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_8() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_9(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_9() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_10(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_10() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_11(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_11() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_12(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_12() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_13(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x2000)|value<<13)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_13() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x2000) >> 13
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_14(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x4000)|value<<14)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_14() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x4000) >> 14
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_ACK_WITH_ERR_15(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x8000)|value<<15)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_ACK_WITH_ERR_15() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x8000) >> 15
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_0(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_0() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x10000) >> 16
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_1(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x20000)|value<<17)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x20000) >> 17
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_2(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x40000)|value<<18)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_2() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x40000) >> 18
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_3(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_3() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x80000) >> 19
}
func (o *DSI_HOST_Type) SetINT_MSK0_MASK_DPHY_ERRORS_4(value uint32) {
	volatile.StoreUint32(&o.INT_MSK0.Reg, volatile.LoadUint32(&o.INT_MSK0.Reg)&^(0x100000)|value<<20)
}
func (o *DSI_HOST_Type) GetINT_MSK0_MASK_DPHY_ERRORS_4() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK0.Reg) & 0x100000) >> 20
}

// DSI_HOST.INT_MSK1: NA
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_TO_HS_TX(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_TO_HS_TX() uint32 {
	return volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_TO_LP_RX(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_TO_LP_RX() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_ECC_SINGLE_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_ECC_SINGLE_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_ECC_MILTI_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_ECC_MILTI_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_CRC_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_CRC_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_PKT_SIZE_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_PKT_SIZE_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_EOPT_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_EOPT_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_DPI_PLD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_DPI_PLD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_CMD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_CMD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_SEND_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_SEND_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_RD_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_RD_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_GEN_PLD_RECEV_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_GEN_PLD_RECEV_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetINT_MSK1_MASK_DPI_BUFF_PLD_UNDER(value uint32) {
	volatile.StoreUint32(&o.INT_MSK1.Reg, volatile.LoadUint32(&o.INT_MSK1.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetINT_MSK1_MASK_DPI_BUFF_PLD_UNDER() uint32 {
	return (volatile.LoadUint32(&o.INT_MSK1.Reg) & 0x80000) >> 19
}

// DSI_HOST.PHY_CAL: NA
func (o *DSI_HOST_Type) SetPHY_CAL_TXSKEWCALHS(value uint32) {
	volatile.StoreUint32(&o.PHY_CAL.Reg, volatile.LoadUint32(&o.PHY_CAL.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetPHY_CAL_TXSKEWCALHS() uint32 {
	return volatile.LoadUint32(&o.PHY_CAL.Reg) & 0x1
}

// DSI_HOST.INT_FORCE0: NA
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_0() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_5(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_5() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_6(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_6() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_7(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_7() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_8(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_8() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_9(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_9() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_10(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_10() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_11(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_11() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_12(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_12() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_13(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x2000)|value<<13)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_13() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x2000) >> 13
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_14(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x4000)|value<<14)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_14() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x4000) >> 14
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_ACK_WITH_ERR_15(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x8000)|value<<15)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_ACK_WITH_ERR_15() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x8000) >> 15
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_0(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_0() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x10000) >> 16
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_1(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x20000)|value<<17)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_1() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x20000) >> 17
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_2(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x40000)|value<<18)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_2() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x40000) >> 18
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_3(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_3() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x80000) >> 19
}
func (o *DSI_HOST_Type) SetINT_FORCE0_FORCE_DPHY_ERRORS_4(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE0.Reg, volatile.LoadUint32(&o.INT_FORCE0.Reg)&^(0x100000)|value<<20)
}
func (o *DSI_HOST_Type) GetINT_FORCE0_FORCE_DPHY_ERRORS_4() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE0.Reg) & 0x100000) >> 20
}

// DSI_HOST.INT_FORCE1: NA
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_TO_HS_TX(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_TO_HS_TX() uint32 {
	return volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_TO_LP_RX(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_TO_LP_RX() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_ECC_SINGLE_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_ECC_SINGLE_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_ECC_MILTI_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_ECC_MILTI_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_CRC_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_CRC_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_PKT_SIZE_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_PKT_SIZE_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_EOPT_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_EOPT_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_DPI_PLD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_DPI_PLD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_CMD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_CMD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_WR_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_WR_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x200) >> 9
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_SEND_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x400)|value<<10)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_SEND_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x400) >> 10
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_RD_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x800)|value<<11)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_RD_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x800) >> 11
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_GEN_PLD_RECEV_ERR(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x1000)|value<<12)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_GEN_PLD_RECEV_ERR() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x1000) >> 12
}
func (o *DSI_HOST_Type) SetINT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER(value uint32) {
	volatile.StoreUint32(&o.INT_FORCE1.Reg, volatile.LoadUint32(&o.INT_FORCE1.Reg)&^(0x80000)|value<<19)
}
func (o *DSI_HOST_Type) GetINT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER() uint32 {
	return (volatile.LoadUint32(&o.INT_FORCE1.Reg) & 0x80000) >> 19
}

// DSI_HOST.DSC_PARAMETER: NA
func (o *DSI_HOST_Type) SetDSC_PARAMETER_COMPRESSION_MODE(value uint32) {
	volatile.StoreUint32(&o.DSC_PARAMETER.Reg, volatile.LoadUint32(&o.DSC_PARAMETER.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetDSC_PARAMETER_COMPRESSION_MODE() uint32 {
	return volatile.LoadUint32(&o.DSC_PARAMETER.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetDSC_PARAMETER_COMPRESS_ALGO(value uint32) {
	volatile.StoreUint32(&o.DSC_PARAMETER.Reg, volatile.LoadUint32(&o.DSC_PARAMETER.Reg)&^(0x300)|value<<8)
}
func (o *DSI_HOST_Type) GetDSC_PARAMETER_COMPRESS_ALGO() uint32 {
	return (volatile.LoadUint32(&o.DSC_PARAMETER.Reg) & 0x300) >> 8
}
func (o *DSI_HOST_Type) SetDSC_PARAMETER_PPS_SEL(value uint32) {
	volatile.StoreUint32(&o.DSC_PARAMETER.Reg, volatile.LoadUint32(&o.DSC_PARAMETER.Reg)&^(0x30000)|value<<16)
}
func (o *DSI_HOST_Type) GetDSC_PARAMETER_PPS_SEL() uint32 {
	return (volatile.LoadUint32(&o.DSC_PARAMETER.Reg) & 0x30000) >> 16
}

// DSI_HOST.PHY_TMR_RD_CFG: NA
func (o *DSI_HOST_Type) SetPHY_TMR_RD_CFG_MAX_RD_TIME(value uint32) {
	volatile.StoreUint32(&o.PHY_TMR_RD_CFG.Reg, volatile.LoadUint32(&o.PHY_TMR_RD_CFG.Reg)&^(0x7fff)|value)
}
func (o *DSI_HOST_Type) GetPHY_TMR_RD_CFG_MAX_RD_TIME() uint32 {
	return volatile.LoadUint32(&o.PHY_TMR_RD_CFG.Reg) & 0x7fff
}

// DSI_HOST.VID_SHADOW_CTRL: NA
func (o *DSI_HOST_Type) SetVID_SHADOW_CTRL_VID_SHADOW_EN(value uint32) {
	volatile.StoreUint32(&o.VID_SHADOW_CTRL.Reg, volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetVID_SHADOW_CTRL_VID_SHADOW_EN() uint32 {
	return volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetVID_SHADOW_CTRL_VID_SHADOW_REQ(value uint32) {
	volatile.StoreUint32(&o.VID_SHADOW_CTRL.Reg, volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetVID_SHADOW_CTRL_VID_SHADOW_REQ() uint32 {
	return (volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetVID_SHADOW_CTRL_VID_SHADOW_PIN_REQ(value uint32) {
	volatile.StoreUint32(&o.VID_SHADOW_CTRL.Reg, volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetVID_SHADOW_CTRL_VID_SHADOW_PIN_REQ() uint32 {
	return (volatile.LoadUint32(&o.VID_SHADOW_CTRL.Reg) & 0x10000) >> 16
}

// DSI_HOST.DPI_VCID_ACT: NA
func (o *DSI_HOST_Type) SetDPI_VCID_ACT(value uint32) {
	volatile.StoreUint32(&o.DPI_VCID_ACT.Reg, volatile.LoadUint32(&o.DPI_VCID_ACT.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetDPI_VCID_ACT() uint32 {
	return volatile.LoadUint32(&o.DPI_VCID_ACT.Reg) & 0x3
}

// DSI_HOST.DPI_COLOR_CODING_ACT: NA
func (o *DSI_HOST_Type) SetDPI_COLOR_CODING_ACT(value uint32) {
	volatile.StoreUint32(&o.DPI_COLOR_CODING_ACT.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg)&^(0xf)|value)
}
func (o *DSI_HOST_Type) GetDPI_COLOR_CODING_ACT() uint32 {
	return volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg) & 0xf
}
func (o *DSI_HOST_Type) SetDPI_COLOR_CODING_ACT_LOOSELY18_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.DPI_COLOR_CODING_ACT.Reg, volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetDPI_COLOR_CODING_ACT_LOOSELY18_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.DPI_COLOR_CODING_ACT.Reg) & 0x100) >> 8
}

// DSI_HOST.DPI_LP_CMD_TIM_ACT: NA
func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_ACT(value uint32) {
	volatile.StoreUint32(&o.DPI_LP_CMD_TIM_ACT.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg)&^(0xff)|value)
}
func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_ACT() uint32 {
	return volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg) & 0xff
}
func (o *DSI_HOST_Type) SetDPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_ACT(value uint32) {
	volatile.StoreUint32(&o.DPI_LP_CMD_TIM_ACT.Reg, volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg)&^(0xff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetDPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_ACT() uint32 {
	return (volatile.LoadUint32(&o.DPI_LP_CMD_TIM_ACT.Reg) & 0xff0000) >> 16
}

// DSI_HOST.EDPI_TE_HW_CFG: NA
func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_ON(value uint32) {
	volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_ON() uint32 {
	return volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_GEN(value uint32) {
	volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_HW_TEAR_EFFECT_GEN() uint32 {
	return (volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_HW_SET_SCAN_LINE(value uint32) {
	volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_HW_SET_SCAN_LINE() uint32 {
	return (volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetEDPI_TE_HW_CFG_SCAN_LINE_PARAMETER(value uint32) {
	volatile.StoreUint32(&o.EDPI_TE_HW_CFG.Reg, volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg)&^(0xffff0000)|value<<16)
}
func (o *DSI_HOST_Type) GetEDPI_TE_HW_CFG_SCAN_LINE_PARAMETER() uint32 {
	return (volatile.LoadUint32(&o.EDPI_TE_HW_CFG.Reg) & 0xffff0000) >> 16
}

// DSI_HOST.VID_MODE_CFG_ACT: NA
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_VID_MODE_TYPE_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_VID_MODE_TYPE_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x3
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VSA_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VSA_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VBP_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VBP_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VFP_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VFP_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_VACT_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_VACT_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_HBP_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x40)|value<<6)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_HBP_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x40) >> 6
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_HFP_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x80)|value<<7)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_HFP_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x80) >> 7
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x100)|value<<8)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x100) >> 8
}
func (o *DSI_HOST_Type) SetVID_MODE_CFG_ACT_LP_CMD_EN_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_MODE_CFG_ACT.Reg, volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg)&^(0x200)|value<<9)
}
func (o *DSI_HOST_Type) GetVID_MODE_CFG_ACT_LP_CMD_EN_ACT() uint32 {
	return (volatile.LoadUint32(&o.VID_MODE_CFG_ACT.Reg) & 0x200) >> 9
}

// DSI_HOST.VID_PKT_SIZE_ACT: NA
func (o *DSI_HOST_Type) SetVID_PKT_SIZE_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_SIZE_ACT.Reg, volatile.LoadUint32(&o.VID_PKT_SIZE_ACT.Reg)&^(0x3fff)|value)
}
func (o *DSI_HOST_Type) GetVID_PKT_SIZE_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_PKT_SIZE_ACT.Reg) & 0x3fff
}

// DSI_HOST.VID_NUM_CHUNKS_ACT: NA
func (o *DSI_HOST_Type) SetVID_NUM_CHUNKS_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_NUM_CHUNKS_ACT.Reg, volatile.LoadUint32(&o.VID_NUM_CHUNKS_ACT.Reg)&^(0x1fff)|value)
}
func (o *DSI_HOST_Type) GetVID_NUM_CHUNKS_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_NUM_CHUNKS_ACT.Reg) & 0x1fff
}

// DSI_HOST.VID_NULL_SIZE_ACT: NA
func (o *DSI_HOST_Type) SetVID_NULL_SIZE_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_NULL_SIZE_ACT.Reg, volatile.LoadUint32(&o.VID_NULL_SIZE_ACT.Reg)&^(0x1fff)|value)
}
func (o *DSI_HOST_Type) GetVID_NULL_SIZE_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_NULL_SIZE_ACT.Reg) & 0x1fff
}

// DSI_HOST.VID_HSA_TIME_ACT: NA
func (o *DSI_HOST_Type) SetVID_HSA_TIME_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_HSA_TIME_ACT.Reg, volatile.LoadUint32(&o.VID_HSA_TIME_ACT.Reg)&^(0xfff)|value)
}
func (o *DSI_HOST_Type) GetVID_HSA_TIME_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_HSA_TIME_ACT.Reg) & 0xfff
}

// DSI_HOST.VID_HBP_TIME_ACT: NA
func (o *DSI_HOST_Type) SetVID_HBP_TIME_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_HBP_TIME_ACT.Reg, volatile.LoadUint32(&o.VID_HBP_TIME_ACT.Reg)&^(0xfff)|value)
}
func (o *DSI_HOST_Type) GetVID_HBP_TIME_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_HBP_TIME_ACT.Reg) & 0xfff
}

// DSI_HOST.VID_HLINE_TIME_ACT: NA
func (o *DSI_HOST_Type) SetVID_HLINE_TIME_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_HLINE_TIME_ACT.Reg, volatile.LoadUint32(&o.VID_HLINE_TIME_ACT.Reg)&^(0x7fff)|value)
}
func (o *DSI_HOST_Type) GetVID_HLINE_TIME_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_HLINE_TIME_ACT.Reg) & 0x7fff
}

// DSI_HOST.VID_VSA_LINES_ACT: NA
func (o *DSI_HOST_Type) SetVID_VSA_LINES_ACT_VSA_LINES_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_VSA_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VSA_LINES_ACT.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetVID_VSA_LINES_ACT_VSA_LINES_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_VSA_LINES_ACT.Reg) & 0x3ff
}

// DSI_HOST.VID_VBP_LINES_ACT: NA
func (o *DSI_HOST_Type) SetVID_VBP_LINES_ACT_VBP_LINES_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_VBP_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VBP_LINES_ACT.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetVID_VBP_LINES_ACT_VBP_LINES_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_VBP_LINES_ACT.Reg) & 0x3ff
}

// DSI_HOST.VID_VFP_LINES_ACT: NA
func (o *DSI_HOST_Type) SetVID_VFP_LINES_ACT_VFP_LINES_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_VFP_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VFP_LINES_ACT.Reg)&^(0x3ff)|value)
}
func (o *DSI_HOST_Type) GetVID_VFP_LINES_ACT_VFP_LINES_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_VFP_LINES_ACT.Reg) & 0x3ff
}

// DSI_HOST.VID_VACTIVE_LINES_ACT: NA
func (o *DSI_HOST_Type) SetVID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_ACT(value uint32) {
	volatile.StoreUint32(&o.VID_VACTIVE_LINES_ACT.Reg, volatile.LoadUint32(&o.VID_VACTIVE_LINES_ACT.Reg)&^(0x3fff)|value)
}
func (o *DSI_HOST_Type) GetVID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_ACT() uint32 {
	return volatile.LoadUint32(&o.VID_VACTIVE_LINES_ACT.Reg) & 0x3fff
}

// DSI_HOST.VID_PKT_STATUS: NA
func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_CMD_W_EMPTY(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x1)|value)
}
func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_CMD_W_EMPTY() uint32 {
	return volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x1
}
func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_CMD_W_FULL(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_CMD_W_FULL() uint32 {
	return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x2) >> 1
}
func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_PLD_W_EMPTY(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_PLD_W_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x4) >> 2
}
func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_PLD_W_FULL(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_PLD_W_FULL() uint32 {
	return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x8) >> 3
}
func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_BUFF_PLD_EMPTY(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_BUFF_PLD_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x10000) >> 16
}
func (o *DSI_HOST_Type) SetVID_PKT_STATUS_DPI_BUFF_PLD_FULL(value uint32) {
	volatile.StoreUint32(&o.VID_PKT_STATUS.Reg, volatile.LoadUint32(&o.VID_PKT_STATUS.Reg)&^(0x20000)|value<<17)
}
func (o *DSI_HOST_Type) GetVID_PKT_STATUS_DPI_BUFF_PLD_FULL() uint32 {
	return (volatile.LoadUint32(&o.VID_PKT_STATUS.Reg) & 0x20000) >> 17
}

// DSI_HOST.SDF_3D_ACT: NA
func (o *DSI_HOST_Type) SetSDF_3D_ACT_MODE_3D_ACT(value uint32) {
	volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x3)|value)
}
func (o *DSI_HOST_Type) GetSDF_3D_ACT_MODE_3D_ACT() uint32 {
	return volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x3
}
func (o *DSI_HOST_Type) SetSDF_3D_ACT_FORMAT_3D_ACT(value uint32) {
	volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0xc)|value<<2)
}
func (o *DSI_HOST_Type) GetSDF_3D_ACT_FORMAT_3D_ACT() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0xc) >> 2
}
func (o *DSI_HOST_Type) SetSDF_3D_ACT_SECOND_VSYNC_ACT(value uint32) {
	volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x10)|value<<4)
}
func (o *DSI_HOST_Type) GetSDF_3D_ACT_SECOND_VSYNC_ACT() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x10) >> 4
}
func (o *DSI_HOST_Type) SetSDF_3D_ACT_RIGHT_FIRST_ACT(value uint32) {
	volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x20)|value<<5)
}
func (o *DSI_HOST_Type) GetSDF_3D_ACT_RIGHT_FIRST_ACT() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x20) >> 5
}
func (o *DSI_HOST_Type) SetSDF_3D_ACT_SEND_3D_CFG_ACT(value uint32) {
	volatile.StoreUint32(&o.SDF_3D_ACT.Reg, volatile.LoadUint32(&o.SDF_3D_ACT.Reg)&^(0x10000)|value<<16)
}
func (o *DSI_HOST_Type) GetSDF_3D_ACT_SEND_3D_CFG_ACT() uint32 {
	return (volatile.LoadUint32(&o.SDF_3D_ACT.Reg) & 0x10000) >> 16
}

// ECC (ECC Hardware Accelerator)
type ECC_Type struct {
	_            [12]byte
	MULT_INT_RAW volatile.Register32 // 0xC
	MULT_INT_ST  volatile.Register32 // 0x10
	MULT_INT_ENA volatile.Register32 // 0x14
	MULT_INT_CLR volatile.Register32 // 0x18
	MULT_CONF    volatile.Register32 // 0x1C
	_            [220]byte
	MULT_DATE    volatile.Register32    // 0xFC
	K_MEM        [8]volatile.Register32 // 0x100
	PX_MEM       [8]volatile.Register32 // 0x120
	PY_MEM       [8]volatile.Register32 // 0x140
}

// ECC.MULT_INT_RAW: ECC interrupt raw register, valid in level.
func (o *ECC_Type) SetMULT_INT_RAW_CALC_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.MULT_INT_RAW.Reg, volatile.LoadUint32(&o.MULT_INT_RAW.Reg)&^(0x1)|value)
}
func (o *ECC_Type) GetMULT_INT_RAW_CALC_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.MULT_INT_RAW.Reg) & 0x1
}

// ECC.MULT_INT_ST: ECC interrupt status register.
func (o *ECC_Type) SetMULT_INT_ST_CALC_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.MULT_INT_ST.Reg, volatile.LoadUint32(&o.MULT_INT_ST.Reg)&^(0x1)|value)
}
func (o *ECC_Type) GetMULT_INT_ST_CALC_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.MULT_INT_ST.Reg) & 0x1
}

// ECC.MULT_INT_ENA: ECC interrupt enable register.
func (o *ECC_Type) SetMULT_INT_ENA_CALC_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.MULT_INT_ENA.Reg, volatile.LoadUint32(&o.MULT_INT_ENA.Reg)&^(0x1)|value)
}
func (o *ECC_Type) GetMULT_INT_ENA_CALC_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.MULT_INT_ENA.Reg) & 0x1
}

// ECC.MULT_INT_CLR: ECC interrupt clear register.
func (o *ECC_Type) SetMULT_INT_CLR_CALC_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.MULT_INT_CLR.Reg, volatile.LoadUint32(&o.MULT_INT_CLR.Reg)&^(0x1)|value)
}
func (o *ECC_Type) GetMULT_INT_CLR_CALC_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.MULT_INT_CLR.Reg) & 0x1
}

// ECC.MULT_CONF: ECC configure register
func (o *ECC_Type) SetMULT_CONF_START(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x1)|value)
}
func (o *ECC_Type) GetMULT_CONF_START() uint32 {
	return volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x1
}
func (o *ECC_Type) SetMULT_CONF_RESET(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x2)|value<<1)
}
func (o *ECC_Type) GetMULT_CONF_RESET() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x2) >> 1
}
func (o *ECC_Type) SetMULT_CONF_KEY_LENGTH(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x4)|value<<2)
}
func (o *ECC_Type) GetMULT_CONF_KEY_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x4) >> 2
}
func (o *ECC_Type) SetMULT_CONF_MOD_BASE(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x8)|value<<3)
}
func (o *ECC_Type) GetMULT_CONF_MOD_BASE() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x8) >> 3
}
func (o *ECC_Type) SetMULT_CONF_WORK_MODE(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0xf0)|value<<4)
}
func (o *ECC_Type) GetMULT_CONF_WORK_MODE() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0xf0) >> 4
}
func (o *ECC_Type) SetMULT_CONF_SECURITY_MODE(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x100)|value<<8)
}
func (o *ECC_Type) GetMULT_CONF_SECURITY_MODE() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x100) >> 8
}
func (o *ECC_Type) SetMULT_CONF_VERIFICATION_RESULT(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x20000000)|value<<29)
}
func (o *ECC_Type) GetMULT_CONF_VERIFICATION_RESULT() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x20000000) >> 29
}
func (o *ECC_Type) SetMULT_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *ECC_Type) GetMULT_CONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x40000000) >> 30
}
func (o *ECC_Type) SetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.MULT_CONF.Reg, volatile.LoadUint32(&o.MULT_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *ECC_Type) GetMULT_CONF_MEM_CLOCK_GATE_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.MULT_CONF.Reg) & 0x80000000) >> 31
}

// ECC.MULT_DATE: Version control register
func (o *ECC_Type) SetMULT_DATE_DATE(value uint32) {
	volatile.StoreUint32(&o.MULT_DATE.Reg, volatile.LoadUint32(&o.MULT_DATE.Reg)&^(0xfffffff)|value)
}
func (o *ECC_Type) GetMULT_DATE_DATE() uint32 {
	return volatile.LoadUint32(&o.MULT_DATE.Reg) & 0xfffffff
}

// ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator
type ECDSA_Type struct {
	_            [4]byte
	CONF         volatile.Register32 // 0x4
	CLK          volatile.Register32 // 0x8
	INT_RAW      volatile.Register32 // 0xC
	INT_ST       volatile.Register32 // 0x10
	INT_ENA      volatile.Register32 // 0x14
	INT_CLR      volatile.Register32 // 0x18
	START        volatile.Register32 // 0x1C
	STATE        volatile.Register32 // 0x20
	RESULT       volatile.Register32 // 0x24
	_            [212]byte
	DATE         volatile.Register32 // 0xFC
	_            [256]byte
	SHA_MODE     volatile.Register32 // 0x200
	_            [12]byte
	SHA_START    volatile.Register32 // 0x210
	SHA_CONTINUE volatile.Register32 // 0x214
	SHA_BUSY     volatile.Register32 // 0x218
	_            [100]byte
	MESSAGE_MEM  [8]volatile.Register32 // 0x280
	_            [1888]byte
	R_MEM        [8]volatile.Register32 // 0xA00
	S_MEM        [8]volatile.Register32 // 0xA20
	Z_MEM        [8]volatile.Register32 // 0xA40
	QAX_MEM      [8]volatile.Register32 // 0xA60
	QAY_MEM      [8]volatile.Register32 // 0xA80
}

// ECDSA.CONF: ECDSA configure register
func (o *ECDSA_Type) SetCONF_WORK_MODE(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value)
}
func (o *ECDSA_Type) GetCONF_WORK_MODE() uint32 {
	return volatile.LoadUint32(&o.CONF.Reg) & 0x3
}
func (o *ECDSA_Type) SetCONF_ECC_CURVE(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2)
}
func (o *ECDSA_Type) GetCONF_ECC_CURVE() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2
}
func (o *ECDSA_Type) SetCONF_SOFTWARE_SET_K(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3)
}
func (o *ECDSA_Type) GetCONF_SOFTWARE_SET_K() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3
}
func (o *ECDSA_Type) SetCONF_SOFTWARE_SET_Z(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4)
}
func (o *ECDSA_Type) GetCONF_SOFTWARE_SET_Z() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4
}
func (o *ECDSA_Type) SetCONF_DETERMINISTIC_K(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5)
}
func (o *ECDSA_Type) GetCONF_DETERMINISTIC_K() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5
}
func (o *ECDSA_Type) SetCONF_DETERMINISTIC_LOOP(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3fffc0)|value<<6)
}
func (o *ECDSA_Type) GetCONF_DETERMINISTIC_LOOP() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x3fffc0) >> 6
}

// ECDSA.CLK: ECDSA clock gate register
func (o *ECDSA_Type) SetCLK_GATE_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetCLK_GATE_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.CLK.Reg) & 0x1
}

// ECDSA.INT_RAW: ECDSA interrupt raw register, valid in level.
func (o *ECDSA_Type) SetINT_RAW_CALC_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetINT_RAW_CALC_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *ECDSA_Type) SetINT_RAW_SHA_RELEASE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *ECDSA_Type) GetINT_RAW_SHA_RELEASE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}

// ECDSA.INT_ST: ECDSA interrupt status register.
func (o *ECDSA_Type) SetINT_ST_CALC_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetINT_ST_CALC_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *ECDSA_Type) SetINT_ST_SHA_RELEASE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *ECDSA_Type) GetINT_ST_SHA_RELEASE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}

// ECDSA.INT_ENA: ECDSA interrupt enable register.
func (o *ECDSA_Type) SetINT_ENA_CALC_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetINT_ENA_CALC_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *ECDSA_Type) SetINT_ENA_SHA_RELEASE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *ECDSA_Type) GetINT_ENA_SHA_RELEASE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}

// ECDSA.INT_CLR: ECDSA interrupt clear register.
func (o *ECDSA_Type) SetINT_CLR_CALC_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetINT_CLR_CALC_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *ECDSA_Type) SetINT_CLR_SHA_RELEASE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *ECDSA_Type) GetINT_CLR_SHA_RELEASE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}

// ECDSA.START: ECDSA start register
func (o *ECDSA_Type) SetSTART(value uint32) {
	volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetSTART() uint32 {
	return volatile.LoadUint32(&o.START.Reg) & 0x1
}
func (o *ECDSA_Type) SetSTART_LOAD_DONE(value uint32) {
	volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x2)|value<<1)
}
func (o *ECDSA_Type) GetSTART_LOAD_DONE() uint32 {
	return (volatile.LoadUint32(&o.START.Reg) & 0x2) >> 1
}
func (o *ECDSA_Type) SetSTART_GET_DONE(value uint32) {
	volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x4)|value<<2)
}
func (o *ECDSA_Type) GetSTART_GET_DONE() uint32 {
	return (volatile.LoadUint32(&o.START.Reg) & 0x4) >> 2
}

// ECDSA.STATE: ECDSA status register
func (o *ECDSA_Type) SetSTATE_BUSY(value uint32) {
	volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value)
}
func (o *ECDSA_Type) GetSTATE_BUSY() uint32 {
	return volatile.LoadUint32(&o.STATE.Reg) & 0x3
}

// ECDSA.RESULT: ECDSA result register
func (o *ECDSA_Type) SetRESULT_OPERATION_RESULT(value uint32) {
	volatile.StoreUint32(&o.RESULT.Reg, volatile.LoadUint32(&o.RESULT.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetRESULT_OPERATION_RESULT() uint32 {
	return volatile.LoadUint32(&o.RESULT.Reg) & 0x1
}
func (o *ECDSA_Type) SetRESULT_K_VALUE_WARNING(value uint32) {
	volatile.StoreUint32(&o.RESULT.Reg, volatile.LoadUint32(&o.RESULT.Reg)&^(0x2)|value<<1)
}
func (o *ECDSA_Type) GetRESULT_K_VALUE_WARNING() uint32 {
	return (volatile.LoadUint32(&o.RESULT.Reg) & 0x2) >> 1
}

// ECDSA.DATE: Version control register
func (o *ECDSA_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *ECDSA_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// ECDSA.SHA_MODE: ECDSA control SHA register
func (o *ECDSA_Type) SetSHA_MODE(value uint32) {
	volatile.StoreUint32(&o.SHA_MODE.Reg, volatile.LoadUint32(&o.SHA_MODE.Reg)&^(0x7)|value)
}
func (o *ECDSA_Type) GetSHA_MODE() uint32 {
	return volatile.LoadUint32(&o.SHA_MODE.Reg) & 0x7
}

// ECDSA.SHA_START: ECDSA control SHA register
func (o *ECDSA_Type) SetSHA_START(value uint32) {
	volatile.StoreUint32(&o.SHA_START.Reg, volatile.LoadUint32(&o.SHA_START.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetSHA_START() uint32 {
	return volatile.LoadUint32(&o.SHA_START.Reg) & 0x1
}

// ECDSA.SHA_CONTINUE: ECDSA control SHA register
func (o *ECDSA_Type) SetSHA_CONTINUE(value uint32) {
	volatile.StoreUint32(&o.SHA_CONTINUE.Reg, volatile.LoadUint32(&o.SHA_CONTINUE.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetSHA_CONTINUE() uint32 {
	return volatile.LoadUint32(&o.SHA_CONTINUE.Reg) & 0x1
}

// ECDSA.SHA_BUSY: ECDSA status register
func (o *ECDSA_Type) SetSHA_BUSY(value uint32) {
	volatile.StoreUint32(&o.SHA_BUSY.Reg, volatile.LoadUint32(&o.SHA_BUSY.Reg)&^(0x1)|value)
}
func (o *ECDSA_Type) GetSHA_BUSY() uint32 {
	return volatile.LoadUint32(&o.SHA_BUSY.Reg) & 0x1
}

// eFuse Controller
type EFUSE_Type struct {
	PGM_DATA0               volatile.Register32 // 0x0
	PGM_DATA1               volatile.Register32 // 0x4
	PGM_DATA2               volatile.Register32 // 0x8
	PGM_DATA3               volatile.Register32 // 0xC
	PGM_DATA4               volatile.Register32 // 0x10
	PGM_DATA5               volatile.Register32 // 0x14
	PGM_DATA6               volatile.Register32 // 0x18
	PGM_DATA7               volatile.Register32 // 0x1C
	PGM_CHECK_VALUE0        volatile.Register32 // 0x20
	PGM_CHECK_VALUE1        volatile.Register32 // 0x24
	PGM_CHECK_VALUE2        volatile.Register32 // 0x28
	RD_WR_DIS               volatile.Register32 // 0x2C
	RD_REPEAT_DATA0         volatile.Register32 // 0x30
	RD_REPEAT_DATA1         volatile.Register32 // 0x34
	RD_REPEAT_DATA2         volatile.Register32 // 0x38
	RD_REPEAT_DATA3         volatile.Register32 // 0x3C
	RD_REPEAT_DATA4         volatile.Register32 // 0x40
	RD_MAC_SYS_0            volatile.Register32 // 0x44
	RD_MAC_SYS_1            volatile.Register32 // 0x48
	RD_MAC_SYS_2            volatile.Register32 // 0x4C
	RD_MAC_SYS_3            volatile.Register32 // 0x50
	RD_MAC_SYS_4            volatile.Register32 // 0x54
	RD_MAC_SYS_5            volatile.Register32 // 0x58
	RD_SYS_PART1_DATA0      volatile.Register32 // 0x5C
	RD_SYS_PART1_DATA1      volatile.Register32 // 0x60
	RD_SYS_PART1_DATA2      volatile.Register32 // 0x64
	RD_SYS_PART1_DATA3      volatile.Register32 // 0x68
	RD_SYS_PART1_DATA4      volatile.Register32 // 0x6C
	RD_SYS_PART1_DATA5      volatile.Register32 // 0x70
	RD_SYS_PART1_DATA6      volatile.Register32 // 0x74
	RD_SYS_PART1_DATA7      volatile.Register32 // 0x78
	RD_USR_DATA0            volatile.Register32 // 0x7C
	RD_USR_DATA1            volatile.Register32 // 0x80
	RD_USR_DATA2            volatile.Register32 // 0x84
	RD_USR_DATA3            volatile.Register32 // 0x88
	RD_USR_DATA4            volatile.Register32 // 0x8C
	RD_USR_DATA5            volatile.Register32 // 0x90
	RD_USR_DATA6            volatile.Register32 // 0x94
	RD_USR_DATA7            volatile.Register32 // 0x98
	RD_KEY0_DATA0           volatile.Register32 // 0x9C
	RD_KEY0_DATA1           volatile.Register32 // 0xA0
	RD_KEY0_DATA2           volatile.Register32 // 0xA4
	RD_KEY0_DATA3           volatile.Register32 // 0xA8
	RD_KEY0_DATA4           volatile.Register32 // 0xAC
	RD_KEY0_DATA5           volatile.Register32 // 0xB0
	RD_KEY0_DATA6           volatile.Register32 // 0xB4
	RD_KEY0_DATA7           volatile.Register32 // 0xB8
	RD_KEY1_DATA0           volatile.Register32 // 0xBC
	RD_KEY1_DATA1           volatile.Register32 // 0xC0
	RD_KEY1_DATA2           volatile.Register32 // 0xC4
	RD_KEY1_DATA3           volatile.Register32 // 0xC8
	RD_KEY1_DATA4           volatile.Register32 // 0xCC
	RD_KEY1_DATA5           volatile.Register32 // 0xD0
	RD_KEY1_DATA6           volatile.Register32 // 0xD4
	RD_KEY1_DATA7           volatile.Register32 // 0xD8
	RD_KEY2_DATA0           volatile.Register32 // 0xDC
	RD_KEY2_DATA1           volatile.Register32 // 0xE0
	RD_KEY2_DATA2           volatile.Register32 // 0xE4
	RD_KEY2_DATA3           volatile.Register32 // 0xE8
	RD_KEY2_DATA4           volatile.Register32 // 0xEC
	RD_KEY2_DATA5           volatile.Register32 // 0xF0
	RD_KEY2_DATA6           volatile.Register32 // 0xF4
	RD_KEY2_DATA7           volatile.Register32 // 0xF8
	RD_KEY3_DATA0           volatile.Register32 // 0xFC
	RD_KEY3_DATA1           volatile.Register32 // 0x100
	RD_KEY3_DATA2           volatile.Register32 // 0x104
	RD_KEY3_DATA3           volatile.Register32 // 0x108
	RD_KEY3_DATA4           volatile.Register32 // 0x10C
	RD_KEY3_DATA5           volatile.Register32 // 0x110
	RD_KEY3_DATA6           volatile.Register32 // 0x114
	RD_KEY3_DATA7           volatile.Register32 // 0x118
	RD_KEY4_DATA0           volatile.Register32 // 0x11C
	RD_KEY4_DATA1           volatile.Register32 // 0x120
	RD_KEY4_DATA2           volatile.Register32 // 0x124
	RD_KEY4_DATA3           volatile.Register32 // 0x128
	RD_KEY4_DATA4           volatile.Register32 // 0x12C
	RD_KEY4_DATA5           volatile.Register32 // 0x130
	RD_KEY4_DATA6           volatile.Register32 // 0x134
	RD_KEY4_DATA7           volatile.Register32 // 0x138
	RD_KEY5_DATA0           volatile.Register32 // 0x13C
	RD_KEY5_DATA1           volatile.Register32 // 0x140
	RD_KEY5_DATA2           volatile.Register32 // 0x144
	RD_KEY5_DATA3           volatile.Register32 // 0x148
	RD_KEY5_DATA4           volatile.Register32 // 0x14C
	RD_KEY5_DATA5           volatile.Register32 // 0x150
	RD_KEY5_DATA6           volatile.Register32 // 0x154
	RD_KEY5_DATA7           volatile.Register32 // 0x158
	RD_SYS_PART2_DATA0      volatile.Register32 // 0x15C
	RD_SYS_PART2_DATA1      volatile.Register32 // 0x160
	RD_SYS_PART2_DATA2      volatile.Register32 // 0x164
	RD_SYS_PART2_DATA3      volatile.Register32 // 0x168
	RD_SYS_PART2_DATA4      volatile.Register32 // 0x16C
	RD_SYS_PART2_DATA5      volatile.Register32 // 0x170
	RD_SYS_PART2_DATA6      volatile.Register32 // 0x174
	RD_SYS_PART2_DATA7      volatile.Register32 // 0x178
	RD_REPEAT_ERR0          volatile.Register32 // 0x17C
	RD_REPEAT_ERR1          volatile.Register32 // 0x180
	RD_REPEAT_ERR2          volatile.Register32 // 0x184
	RD_REPEAT_ERR3          volatile.Register32 // 0x188
	RD_REPEAT_ERR4          volatile.Register32 // 0x18C
	_                       [48]byte
	RD_RS_ERR0              volatile.Register32 // 0x1C0
	RD_RS_ERR1              volatile.Register32 // 0x1C4
	CLK                     volatile.Register32 // 0x1C8
	CONF                    volatile.Register32 // 0x1CC
	STATUS                  volatile.Register32 // 0x1D0
	CMD                     volatile.Register32 // 0x1D4
	INT_RAW                 volatile.Register32 // 0x1D8
	INT_ST                  volatile.Register32 // 0x1DC
	INT_ENA                 volatile.Register32 // 0x1E0
	INT_CLR                 volatile.Register32 // 0x1E4
	DAC_CONF                volatile.Register32 // 0x1E8
	RD_TIM_CONF             volatile.Register32 // 0x1EC
	WR_TIM_CONF1            volatile.Register32 // 0x1F0
	WR_TIM_CONF2            volatile.Register32 // 0x1F4
	WR_TIM_CONF0_RS_BYPASS  volatile.Register32 // 0x1F8
	DATE                    volatile.Register32 // 0x1FC
	_                       [1536]byte
	APB2OTP_WR_DIS          volatile.Register32 // 0x800
	APB2OTP_BLK0_BACKUP1_W1 volatile.Register32 // 0x804
	APB2OTP_BLK0_BACKUP1_W2 volatile.Register32 // 0x808
	APB2OTP_BLK0_BACKUP1_W3 volatile.Register32 // 0x80C
	APB2OTP_BLK0_BACKUP1_W4 volatile.Register32 // 0x810
	APB2OTP_BLK0_BACKUP1_W5 volatile.Register32 // 0x814
	APB2OTP_BLK0_BACKUP2_W1 volatile.Register32 // 0x818
	APB2OTP_BLK0_BACKUP2_W2 volatile.Register32 // 0x81C
	APB2OTP_BLK0_BACKUP2_W3 volatile.Register32 // 0x820
	APB2OTP_BLK0_BACKUP2_W4 volatile.Register32 // 0x824
	APB2OTP_BLK0_BACKUP2_W5 volatile.Register32 // 0x828
	APB2OTP_BLK0_BACKUP3_W1 volatile.Register32 // 0x82C
	APB2OTP_BLK0_BACKUP3_W2 volatile.Register32 // 0x830
	APB2OTP_BLK0_BACKUP3_W3 volatile.Register32 // 0x834
	APB2OTP_BLK0_BACKUP3_W4 volatile.Register32 // 0x838
	APB2OTP_BLK0_BACKUP3_W5 volatile.Register32 // 0x83C
	APB2OTP_BLK0_BACKUP4_W1 volatile.Register32 // 0x840
	APB2OTP_BLK0_BACKUP4_W2 volatile.Register32 // 0x844
	APB2OTP_BLK0_BACKUP4_W3 volatile.Register32 // 0x848
	APB2OTP_BLK0_BACKUP4_W4 volatile.Register32 // 0x84C
	APB2OTP_BLK0_BACKUP4_W5 volatile.Register32 // 0x850
	APB2OTP_BLK1_W1         volatile.Register32 // 0x854
	APB2OTP_BLK1_W2         volatile.Register32 // 0x858
	APB2OTP_BLK1_W3         volatile.Register32 // 0x85C
	APB2OTP_BLK1_W4         volatile.Register32 // 0x860
	APB2OTP_BLK1_W5         volatile.Register32 // 0x864
	APB2OTP_BLK1_W6         volatile.Register32 // 0x868
	APB2OTP_BLK1_W7         volatile.Register32 // 0x86C
	APB2OTP_BLK1_W8         volatile.Register32 // 0x870
	APB2OTP_BLK1_W9         volatile.Register32 // 0x874
	APB2OTP_BLK2_W1         volatile.Register32 // 0x878
	APB2OTP_BLK2_W2         volatile.Register32 // 0x87C
	APB2OTP_BLK2_W3         volatile.Register32 // 0x880
	APB2OTP_BLK2_W4         volatile.Register32 // 0x884
	APB2OTP_BLK2_W5         volatile.Register32 // 0x888
	APB2OTP_BLK2_W6         volatile.Register32 // 0x88C
	APB2OTP_BLK2_W7         volatile.Register32 // 0x890
	APB2OTP_BLK2_W8         volatile.Register32 // 0x894
	APB2OTP_BLK2_W9         volatile.Register32 // 0x898
	APB2OTP_BLK2_W10        volatile.Register32 // 0x89C
	APB2OTP_BLK2_W11        volatile.Register32 // 0x8A0
	APB2OTP_BLK3_W1         volatile.Register32 // 0x8A4
	APB2OTP_BLK3_W2         volatile.Register32 // 0x8A8
	APB2OTP_BLK3_W3         volatile.Register32 // 0x8AC
	APB2OTP_BLK3_W4         volatile.Register32 // 0x8B0
	APB2OTP_BLK3_W5         volatile.Register32 // 0x8B4
	APB2OTP_BLK3_W6         volatile.Register32 // 0x8B8
	APB2OTP_BLK3_W7         volatile.Register32 // 0x8BC
	APB2OTP_BLK3_W8         volatile.Register32 // 0x8C0
	APB2OTP_BLK3_W9         volatile.Register32 // 0x8C4
	APB2OTP_BLK3_W10        volatile.Register32 // 0x8C8
	APB2OTP_BLK3_W11        volatile.Register32 // 0x8CC
	APB2OTP_BLK4_W1         volatile.Register32 // 0x8D0
	APB2OTP_BLK4_W2         volatile.Register32 // 0x8D4
	APB2OTP_BLK4_W3         volatile.Register32 // 0x8D8
	APB2OTP_BLK4_W4         volatile.Register32 // 0x8DC
	APB2OTP_BLK4_W5         volatile.Register32 // 0x8E0
	APB2OTP_BLK4_W6         volatile.Register32 // 0x8E4
	APB2OTP_BLK4_W7         volatile.Register32 // 0x8E8
	APB2OTP_BLK4_W8         volatile.Register32 // 0x8EC
	APB2OTP_BLK4_W9         volatile.Register32 // 0x8F0
	APB2OTP_BLK4_W10        volatile.Register32 // 0x8F4
	APB2OTP_BLK4_W11        volatile.Register32 // 0x8F8
	APB2OTP_BLK5_W1         volatile.Register32 // 0x8FC
	APB2OTP_BLK5_W2         volatile.Register32 // 0x900
	APB2OTP_BLK5_W3         volatile.Register32 // 0x904
	APB2OTP_BLK5_W4         volatile.Register32 // 0x908
	APB2OTP_BLK5_W5         volatile.Register32 // 0x90C
	APB2OTP_BLK5_W6         volatile.Register32 // 0x910
	APB2OTP_BLK5_W7         volatile.Register32 // 0x914
	APB2OTP_BLK5_W8         volatile.Register32 // 0x918
	APB2OTP_BLK5_W9         volatile.Register32 // 0x91C
	APB2OTP_BLK5_W10        volatile.Register32 // 0x920
	APB2OTP_BLK5_W11        volatile.Register32 // 0x924
	APB2OTP_BLK6_W1         volatile.Register32 // 0x928
	APB2OTP_BLK6_W2         volatile.Register32 // 0x92C
	APB2OTP_BLK6_W3         volatile.Register32 // 0x930
	APB2OTP_BLK6_W4         volatile.Register32 // 0x934
	APB2OTP_BLK6_W5         volatile.Register32 // 0x938
	APB2OTP_BLK6_W6         volatile.Register32 // 0x93C
	APB2OTP_BLK6_W7         volatile.Register32 // 0x940
	APB2OTP_BLK6_W8         volatile.Register32 // 0x944
	APB2OTP_BLK6_W9         volatile.Register32 // 0x948
	APB2OTP_BLK6_W10        volatile.Register32 // 0x94C
	APB2OTP_BLK6_W11        volatile.Register32 // 0x950
	APB2OTP_BLK7_W1         volatile.Register32 // 0x954
	APB2OTP_BLK7_W2         volatile.Register32 // 0x958
	APB2OTP_BLK7_W3         volatile.Register32 // 0x95C
	APB2OTP_BLK7_W4         volatile.Register32 // 0x960
	APB2OTP_BLK7_W5         volatile.Register32 // 0x964
	APB2OTP_BLK7_W6         volatile.Register32 // 0x968
	APB2OTP_BLK7_W7         volatile.Register32 // 0x96C
	APB2OTP_BLK7_W8         volatile.Register32 // 0x970
	APB2OTP_BLK7_W9         volatile.Register32 // 0x974
	APB2OTP_BLK7_W10        volatile.Register32 // 0x978
	APB2OTP_BLK7_W11        volatile.Register32 // 0x97C
	APB2OTP_BLK8_W1         volatile.Register32 // 0x980
	APB2OTP_BLK8_W2         volatile.Register32 // 0x984
	APB2OTP_BLK8_W3         volatile.Register32 // 0x988
	APB2OTP_BLK8_W4         volatile.Register32 // 0x98C
	APB2OTP_BLK8_W5         volatile.Register32 // 0x990
	APB2OTP_BLK8_W6         volatile.Register32 // 0x994
	APB2OTP_BLK8_W7         volatile.Register32 // 0x998
	APB2OTP_BLK8_W8         volatile.Register32 // 0x99C
	APB2OTP_BLK8_W9         volatile.Register32 // 0x9A0
	APB2OTP_BLK8_W10        volatile.Register32 // 0x9A4
	APB2OTP_BLK8_W11        volatile.Register32 // 0x9A8
	APB2OTP_BLK9_W1         volatile.Register32 // 0x9AC
	APB2OTP_BLK9_W2         volatile.Register32 // 0x9B0
	APB2OTP_BLK9_W3         volatile.Register32 // 0x9B4
	APB2OTP_BLK9_W4         volatile.Register32 // 0x9B8
	APB2OTP_BLK9_W5         volatile.Register32 // 0x9BC
	APB2OTP_BLK9_W6         volatile.Register32 // 0x9C0
	APB2OTP_BLK9_W7         volatile.Register32 // 0x9C4
	APB2OTP_BLK9_W8         volatile.Register32 // 0x9C8
	APB2OTP_BLK9_W9         volatile.Register32 // 0x9CC
	APB2OTP_BLK9_W10        volatile.Register32 // 0x9D0
	APB2OTP_BLK9_W11        volatile.Register32 // 0x9D4
	APB2OTP_BLK10_W1        volatile.Register32 // 0x9D8
	APB2OTP_BLK10_W2        volatile.Register32 // 0x9DC
	APB2OTP_BLK10_W3        volatile.Register32 // 0x9E0
	APB2OTP_BLK10_W4        volatile.Register32 // 0x9E4
	APB2OTP_BLK10_W5        volatile.Register32 // 0x9E8
	APB2OTP_BLK10_W6        volatile.Register32 // 0x9EC
	APB2OTP_BLK10_W7        volatile.Register32 // 0x9F0
	APB2OTP_BLK10_W8        volatile.Register32 // 0x9F4
	APB2OTP_BLK10_W9        volatile.Register32 // 0x9F8
	APB2OTP_BLK10_W10       volatile.Register32 // 0x9FC
	APB2OTP_BLK10_W11       volatile.Register32 // 0xA00
	_                       [4]byte
	APB2OTP_EN              volatile.Register32 // 0xA08
}

// EFUSE.PGM_DATA0: Register 0 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA0(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA0() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA0.Reg)
}

// EFUSE.PGM_DATA1: Register 1 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA1(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA1() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA1.Reg)
}

// EFUSE.PGM_DATA2: Register 2 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA2(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA2() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA2.Reg)
}

// EFUSE.PGM_DATA3: Register 3 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA3(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA3() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA3.Reg)
}

// EFUSE.PGM_DATA4: Register 4 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA4(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA4() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA4.Reg)
}

// EFUSE.PGM_DATA5: Register 5 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA5(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA5() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA5.Reg)
}

// EFUSE.PGM_DATA6: Register 6 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA6(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA6() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA6.Reg)
}

// EFUSE.PGM_DATA7: Register 7 that stores data to be programmed.
func (o *EFUSE_Type) SetPGM_DATA7(value uint32) {
	volatile.StoreUint32(&o.PGM_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetPGM_DATA7() uint32 {
	return volatile.LoadUint32(&o.PGM_DATA7.Reg)
}

// EFUSE.PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed.
func (o *EFUSE_Type) SetPGM_CHECK_VALUE0(value uint32) {
	volatile.StoreUint32(&o.PGM_CHECK_VALUE0.Reg, value)
}
func (o *EFUSE_Type) GetPGM_CHECK_VALUE0() uint32 {
	return volatile.LoadUint32(&o.PGM_CHECK_VALUE0.Reg)
}

// EFUSE.PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed.
func (o *EFUSE_Type) SetPGM_CHECK_VALUE1(value uint32) {
	volatile.StoreUint32(&o.PGM_CHECK_VALUE1.Reg, value)
}
func (o *EFUSE_Type) GetPGM_CHECK_VALUE1() uint32 {
	return volatile.LoadUint32(&o.PGM_CHECK_VALUE1.Reg)
}

// EFUSE.PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed.
func (o *EFUSE_Type) SetPGM_CHECK_VALUE2(value uint32) {
	volatile.StoreUint32(&o.PGM_CHECK_VALUE2.Reg, value)
}
func (o *EFUSE_Type) GetPGM_CHECK_VALUE2() uint32 {
	return volatile.LoadUint32(&o.PGM_CHECK_VALUE2.Reg)
}

// EFUSE.RD_WR_DIS: BLOCK0 data register 0.
func (o *EFUSE_Type) SetRD_WR_DIS(value uint32) {
	volatile.StoreUint32(&o.RD_WR_DIS.Reg, value)
}
func (o *EFUSE_Type) GetRD_WR_DIS() uint32 {
	return volatile.LoadUint32(&o.RD_WR_DIS.Reg)
}

// EFUSE.RD_REPEAT_DATA0: BLOCK0 data register 1.
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_RD_DIS(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x7f)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_RD_DIS() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x7f
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DEVICE_EXCHG_PINS(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80)|value<<7)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DEVICE_EXCHG_PINS() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80) >> 7
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_OTG11_EXCHG_PINS(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_OTG11_EXCHG_PINS() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_JTAG(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x200)|value<<9)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_JTAG() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x200) >> 9
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_POWERGLITCH_EN(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x400)|value<<10)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_POWERGLITCH_EN() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x400) >> 10
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x800)|value<<11)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x800) >> 11
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1000)|value<<12)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1000) >> 12
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000)|value<<13)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000) >> 13
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_TWAI(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x4000)|value<<14)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_TWAI() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x4000) >> 14
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_JTAG_SEL_ENABLE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x8000)|value<<15)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_JTAG_SEL_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x8000) >> 15
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_SOFT_DIS_JTAG(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x70000)|value<<16)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_SOFT_DIS_JTAG() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x70000) >> 16
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_PAD_JTAG(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x80000)|value<<19)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_PAD_JTAG() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x80000) >> 19
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x100000)|value<<20)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x100000) >> 20
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_DEVICE_DREFH(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x600000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_DEVICE_DREFH() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x600000) >> 21
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_OTG11_DREFH(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x1800000)|value<<23)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_OTG11_DREFH() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x1800000) >> 23
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_USB_PHY_SEL(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0x2000000)|value<<25)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_USB_PHY_SEL() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0x2000000) >> 25
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA0_KM_HUK_GEN_STATE_LOW(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA0.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg)&^(0xfc000000)|value<<26)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA0_KM_HUK_GEN_STATE_LOW() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA0.Reg) & 0xfc000000) >> 26
}

// EFUSE.RD_REPEAT_DATA1: BLOCK0 data register 2.
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KM_HUK_GEN_STATE_HIGH(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x7)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KM_HUK_GEN_STATE_HIGH() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x7
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KM_RND_SWITCH_CYCLE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x18)|value<<3)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KM_RND_SWITCH_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x18) >> 3
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KM_DEPLOY_ONLY_ONCE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1e0)|value<<5)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KM_DEPLOY_ONLY_ONCE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1e0) >> 5
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_FORCE_USE_KEY_MANAGER_KEY(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1e00)|value<<9)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_FORCE_USE_KEY_MANAGER_KEY() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1e00) >> 9
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_FORCE_DISABLE_SW_INIT_KEY(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x2000)|value<<13)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_FORCE_DISABLE_SW_INIT_KEY() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x2000) >> 13
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_XTS_KEY_LENGTH_256(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x4000)|value<<14)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_XTS_KEY_LENGTH_256() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x4000) >> 14
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_WDT_DELAY_SEL(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x30000)|value<<16)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_WDT_DELAY_SEL() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x30000) >> 16
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x1c0000)|value<<18)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x1c0000) >> 18
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x200000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x200000) >> 21
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x400000)|value<<22)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x400000) >> 22
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0x800000)|value<<23)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0x800000) >> 23
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_0(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf000000)|value<<24)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_0() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf000000) >> 24
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA1_KEY_PURPOSE_1(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA1.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg)&^(0xf0000000)|value<<28)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA1_KEY_PURPOSE_1() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA1.Reg) & 0xf0000000) >> 28
}

// EFUSE.RD_REPEAT_DATA2: BLOCK0 data register 3.
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_2(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_2() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_3(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0)|value<<4)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_3() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0) >> 4
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_4(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf00)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_4() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf00) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_KEY_PURPOSE_5(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf000)|value<<12)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_KEY_PURPOSE_5() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf000) >> 12
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SEC_DPA_LEVEL(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x30000)|value<<16)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SEC_DPA_LEVEL() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x30000) >> 16
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_ECDSA_ENABLE_SOFT_K(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x40000)|value<<18)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_ECDSA_ENABLE_SOFT_K() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x40000) >> 18
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x80000)|value<<19)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_CRYPT_DPA_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x80000) >> 19
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_EN(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x100000)|value<<20)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_EN() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x100000) >> 20
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x200000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x200000) >> 21
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TYPE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x800000)|value<<23)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TYPE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x800000) >> 23
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_PAGE_SIZE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x3000000)|value<<24)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_PAGE_SIZE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x3000000) >> 24
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x4000000)|value<<26)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_ECC_EN() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x4000000) >> 26
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_DIS_USB_OTG_DOWNLOAD_MODE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0x8000000)|value<<27)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_DIS_USB_OTG_DOWNLOAD_MODE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0x8000000) >> 27
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA2_FLASH_TPUW(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA2.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg)&^(0xf0000000)|value<<28)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA2_FLASH_TPUW() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA2.Reg) & 0xf0000000) >> 28
}

// EFUSE.RD_REPEAT_DATA3: BLOCK0 data register 4.
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DOWNLOAD_MODE() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_DIRECT_BOOT(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_DIRECT_BOOT() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2) >> 1
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_ROM_PRINT(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4)|value<<2)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_ROM_PRINT() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4) >> 2
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_LOCK_KM_KEY(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x8)|value<<3)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_LOCK_KM_KEY() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x8) >> 3
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x10)|value<<4)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x10) >> 4
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x20)|value<<5)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x20) >> 5
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_UART_PRINT_CONTROL(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xc0)|value<<6)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_UART_PRINT_CONTROL() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xc0) >> 6
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_FORCE_SEND_RESUME(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x100)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_FORCE_SEND_RESUME() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x100) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_VERSION(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x1fffe00)|value<<9)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_VERSION() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x1fffe00) >> 9
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x2000000)|value<<25)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x2000000) >> 25
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_HYS_EN_PAD(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0x4000000)|value<<26)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_HYS_EN_PAD() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0x4000000) >> 26
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA3_DCDC_VSET(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA3.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg)&^(0xf8000000)|value<<27)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA3_DCDC_VSET() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA3.Reg) & 0xf8000000) >> 27
}

// EFUSE.RD_REPEAT_DATA4: BLOCK0 data register 5.
func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_0(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x3)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_0() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x3
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_1(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xc)|value<<2)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xc) >> 2
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_2(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x30)|value<<4)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_2() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x30) >> 4
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4__0PXA_TIEH_SEL_3(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xc0)|value<<6)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4__0PXA_TIEH_SEL_3() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xc0) >> 6
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4_KM_DISABLE_DEPLOY_MODE(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xf00)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4_KM_DISABLE_DEPLOY_MODE() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xf00) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4_USB_DEVICE_DREFL(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x3000)|value<<12)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4_USB_DEVICE_DREFL() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x3000) >> 12
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4_USB_OTG11_DREFL(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0xc000)|value<<14)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4_USB_OTG11_DREFL() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0xc000) >> 14
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4_HP_PWR_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x40000)|value<<18)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4_HP_PWR_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x40000) >> 18
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4_DCDC_VSET_EN(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x80000)|value<<19)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4_DCDC_VSET_EN() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x80000) >> 19
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4_DIS_WDT(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x100000)|value<<20)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4_DIS_WDT() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x100000) >> 20
}
func (o *EFUSE_Type) SetRD_REPEAT_DATA4_DIS_SWD(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_DATA4.Reg, volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg)&^(0x200000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_DATA4_DIS_SWD() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_DATA4.Reg) & 0x200000) >> 21
}

// EFUSE.RD_MAC_SYS_0: BLOCK1 data register $n.
func (o *EFUSE_Type) SetRD_MAC_SYS_0(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_0.Reg, value)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_0() uint32 {
	return volatile.LoadUint32(&o.RD_MAC_SYS_0.Reg)
}

// EFUSE.RD_MAC_SYS_1: BLOCK1 data register $n.
func (o *EFUSE_Type) SetRD_MAC_SYS_1_MAC_1(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg)&^(0xffff)|value)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_1_MAC_1() uint32 {
	return volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg) & 0xffff
}
func (o *EFUSE_Type) SetRD_MAC_SYS_1_MAC_EXT(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_1.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg)&^(0xffff0000)|value<<16)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_1_MAC_EXT() uint32 {
	return (volatile.LoadUint32(&o.RD_MAC_SYS_1.Reg) & 0xffff0000) >> 16
}

// EFUSE.RD_MAC_SYS_2: BLOCK1 data register $n.
func (o *EFUSE_Type) SetRD_MAC_SYS_2_MAC_RESERVED_1(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg)&^(0x3fff)|value)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_2_MAC_RESERVED_1() uint32 {
	return volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg) & 0x3fff
}
func (o *EFUSE_Type) SetRD_MAC_SYS_2_MAC_RESERVED_0(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_2.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg)&^(0xffffc000)|value<<14)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_2_MAC_RESERVED_0() uint32 {
	return (volatile.LoadUint32(&o.RD_MAC_SYS_2.Reg) & 0xffffc000) >> 14
}

// EFUSE.RD_MAC_SYS_3: BLOCK1 data register $n.
func (o *EFUSE_Type) SetRD_MAC_SYS_3_MAC_RESERVED_2(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg)&^(0x3ffff)|value)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_3_MAC_RESERVED_2() uint32 {
	return volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg) & 0x3ffff
}
func (o *EFUSE_Type) SetRD_MAC_SYS_3_SYS_DATA_PART0_0(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_3.Reg, volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg)&^(0xfffc0000)|value<<18)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_3_SYS_DATA_PART0_0() uint32 {
	return (volatile.LoadUint32(&o.RD_MAC_SYS_3.Reg) & 0xfffc0000) >> 18
}

// EFUSE.RD_MAC_SYS_4: BLOCK1 data register $n.
func (o *EFUSE_Type) SetRD_MAC_SYS_4(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_4.Reg, value)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_4() uint32 {
	return volatile.LoadUint32(&o.RD_MAC_SYS_4.Reg)
}

// EFUSE.RD_MAC_SYS_5: BLOCK1 data register $n.
func (o *EFUSE_Type) SetRD_MAC_SYS_5(value uint32) {
	volatile.StoreUint32(&o.RD_MAC_SYS_5.Reg, value)
}
func (o *EFUSE_Type) GetRD_MAC_SYS_5() uint32 {
	return volatile.LoadUint32(&o.RD_MAC_SYS_5.Reg)
}

// EFUSE.RD_SYS_PART1_DATA0: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA0.Reg)
}

// EFUSE.RD_SYS_PART1_DATA1: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA1.Reg)
}

// EFUSE.RD_SYS_PART1_DATA2: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA2.Reg)
}

// EFUSE.RD_SYS_PART1_DATA3: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA3.Reg)
}

// EFUSE.RD_SYS_PART1_DATA4: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA4.Reg)
}

// EFUSE.RD_SYS_PART1_DATA5: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA5.Reg)
}

// EFUSE.RD_SYS_PART1_DATA6: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA6.Reg)
}

// EFUSE.RD_SYS_PART1_DATA7: Register $n of BLOCK2 (system).
func (o *EFUSE_Type) SetRD_SYS_PART1_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART1_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART1_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART1_DATA7.Reg)
}

// EFUSE.RD_USR_DATA0: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA0.Reg)
}

// EFUSE.RD_USR_DATA1: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA1.Reg)
}

// EFUSE.RD_USR_DATA2: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA2.Reg)
}

// EFUSE.RD_USR_DATA3: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA3.Reg)
}

// EFUSE.RD_USR_DATA4: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA4.Reg)
}

// EFUSE.RD_USR_DATA5: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA5.Reg)
}

// EFUSE.RD_USR_DATA6: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA6.Reg)
}

// EFUSE.RD_USR_DATA7: Register $n of BLOCK3 (user).
func (o *EFUSE_Type) SetRD_USR_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_USR_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_USR_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_USR_DATA7.Reg)
}

// EFUSE.RD_KEY0_DATA0: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA0.Reg)
}

// EFUSE.RD_KEY0_DATA1: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA1.Reg)
}

// EFUSE.RD_KEY0_DATA2: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA2.Reg)
}

// EFUSE.RD_KEY0_DATA3: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA3.Reg)
}

// EFUSE.RD_KEY0_DATA4: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA4.Reg)
}

// EFUSE.RD_KEY0_DATA5: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA5.Reg)
}

// EFUSE.RD_KEY0_DATA6: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA6.Reg)
}

// EFUSE.RD_KEY0_DATA7: Register $n of BLOCK4 (KEY0).
func (o *EFUSE_Type) SetRD_KEY0_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_KEY0_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY0_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_KEY0_DATA7.Reg)
}

// EFUSE.RD_KEY1_DATA0: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA0.Reg)
}

// EFUSE.RD_KEY1_DATA1: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA1.Reg)
}

// EFUSE.RD_KEY1_DATA2: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA2.Reg)
}

// EFUSE.RD_KEY1_DATA3: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA3.Reg)
}

// EFUSE.RD_KEY1_DATA4: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA4.Reg)
}

// EFUSE.RD_KEY1_DATA5: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA5.Reg)
}

// EFUSE.RD_KEY1_DATA6: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA6.Reg)
}

// EFUSE.RD_KEY1_DATA7: Register $n of BLOCK5 (KEY1).
func (o *EFUSE_Type) SetRD_KEY1_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_KEY1_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY1_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_KEY1_DATA7.Reg)
}

// EFUSE.RD_KEY2_DATA0: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA0.Reg)
}

// EFUSE.RD_KEY2_DATA1: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA1.Reg)
}

// EFUSE.RD_KEY2_DATA2: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA2.Reg)
}

// EFUSE.RD_KEY2_DATA3: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA3.Reg)
}

// EFUSE.RD_KEY2_DATA4: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA4.Reg)
}

// EFUSE.RD_KEY2_DATA5: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA5.Reg)
}

// EFUSE.RD_KEY2_DATA6: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA6.Reg)
}

// EFUSE.RD_KEY2_DATA7: Register $n of BLOCK6 (KEY2).
func (o *EFUSE_Type) SetRD_KEY2_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_KEY2_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY2_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_KEY2_DATA7.Reg)
}

// EFUSE.RD_KEY3_DATA0: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA0.Reg)
}

// EFUSE.RD_KEY3_DATA1: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA1.Reg)
}

// EFUSE.RD_KEY3_DATA2: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA2.Reg)
}

// EFUSE.RD_KEY3_DATA3: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA3.Reg)
}

// EFUSE.RD_KEY3_DATA4: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA4.Reg)
}

// EFUSE.RD_KEY3_DATA5: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA5.Reg)
}

// EFUSE.RD_KEY3_DATA6: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA6.Reg)
}

// EFUSE.RD_KEY3_DATA7: Register $n of BLOCK7 (KEY3).
func (o *EFUSE_Type) SetRD_KEY3_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_KEY3_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY3_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_KEY3_DATA7.Reg)
}

// EFUSE.RD_KEY4_DATA0: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA0.Reg)
}

// EFUSE.RD_KEY4_DATA1: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA1.Reg)
}

// EFUSE.RD_KEY4_DATA2: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA2.Reg)
}

// EFUSE.RD_KEY4_DATA3: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA3.Reg)
}

// EFUSE.RD_KEY4_DATA4: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA4.Reg)
}

// EFUSE.RD_KEY4_DATA5: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA5.Reg)
}

// EFUSE.RD_KEY4_DATA6: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA6.Reg)
}

// EFUSE.RD_KEY4_DATA7: Register $n of BLOCK8 (KEY4).
func (o *EFUSE_Type) SetRD_KEY4_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_KEY4_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY4_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_KEY4_DATA7.Reg)
}

// EFUSE.RD_KEY5_DATA0: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA0.Reg)
}

// EFUSE.RD_KEY5_DATA1: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA1.Reg)
}

// EFUSE.RD_KEY5_DATA2: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA2.Reg)
}

// EFUSE.RD_KEY5_DATA3: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA3.Reg)
}

// EFUSE.RD_KEY5_DATA4: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA4.Reg)
}

// EFUSE.RD_KEY5_DATA5: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA5.Reg)
}

// EFUSE.RD_KEY5_DATA6: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA6.Reg)
}

// EFUSE.RD_KEY5_DATA7: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_KEY5_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_KEY5_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_KEY5_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_KEY5_DATA7.Reg)
}

// EFUSE.RD_SYS_PART2_DATA0: Register $n of BLOCK10 (system).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA0(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA0.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA0() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA0.Reg)
}

// EFUSE.RD_SYS_PART2_DATA1: Register $n of BLOCK9 (KEY5).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA1(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA1.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA1() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA1.Reg)
}

// EFUSE.RD_SYS_PART2_DATA2: Register $n of BLOCK10 (system).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA2(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA2.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA2() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA2.Reg)
}

// EFUSE.RD_SYS_PART2_DATA3: Register $n of BLOCK10 (system).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA3(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA3.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA3() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA3.Reg)
}

// EFUSE.RD_SYS_PART2_DATA4: Register $n of BLOCK10 (system).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA4(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA4.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA4() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA4.Reg)
}

// EFUSE.RD_SYS_PART2_DATA5: Register $n of BLOCK10 (system).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA5(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA5.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA5() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA5.Reg)
}

// EFUSE.RD_SYS_PART2_DATA6: Register $n of BLOCK10 (system).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA6(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA6.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA6() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA6.Reg)
}

// EFUSE.RD_SYS_PART2_DATA7: Register $n of BLOCK10 (system).
func (o *EFUSE_Type) SetRD_SYS_PART2_DATA7(value uint32) {
	volatile.StoreUint32(&o.RD_SYS_PART2_DATA7.Reg, value)
}
func (o *EFUSE_Type) GetRD_SYS_PART2_DATA7() uint32 {
	return volatile.LoadUint32(&o.RD_SYS_PART2_DATA7.Reg)
}

// EFUSE.RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0.
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_RD_DIS_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x7f)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_RD_DIS_ERR() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x7f
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_DEVICE_EXCHG_PINS_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80)|value<<7)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_DEVICE_EXCHG_PINS_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80) >> 7
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_OTG11_EXCHG_PINS_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_OTG11_EXCHG_PINS_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x200)|value<<9)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_JTAG_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x200) >> 9
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x400)|value<<10)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_POWERGLITCH_EN_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x400) >> 10
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x800)|value<<11)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x800) >> 11
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1000)|value<<12)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1000) >> 12
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000)|value<<13)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000) >> 13
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_TWAI_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x4000)|value<<14)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_TWAI_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x4000) >> 14
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x8000)|value<<15)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x8000) >> 15
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x70000)|value<<16)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x70000) >> 16
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x80000)|value<<19)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_PAD_JTAG_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x80000) >> 19
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x100000)|value<<20)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x100000) >> 20
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_DEVICE_DREFH_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x600000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_DEVICE_DREFH_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x600000) >> 21
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_OTG11_DREFH_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x1800000)|value<<23)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_OTG11_DREFH_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x1800000) >> 23
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_USB_PHY_SEL_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0x2000000)|value<<25)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_USB_PHY_SEL_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0x2000000) >> 25
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR0_HUK_GEN_STATE_LOW_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR0.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg)&^(0xfc000000)|value<<26)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR0_HUK_GEN_STATE_LOW_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR0.Reg) & 0xfc000000) >> 26
}

// EFUSE.RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0.
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KM_HUK_GEN_STATE_HIGH_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x7)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KM_HUK_GEN_STATE_HIGH_ERR() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x7
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KM_RND_SWITCH_CYCLE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x18)|value<<3)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KM_RND_SWITCH_CYCLE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x18) >> 3
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KM_DEPLOY_ONLY_ONCE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1e0)|value<<5)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KM_DEPLOY_ONLY_ONCE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1e0) >> 5
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_FORCE_USE_KEY_MANAGER_KEY_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1e00)|value<<9)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_FORCE_USE_KEY_MANAGER_KEY_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1e00) >> 9
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_FORCE_DISABLE_SW_INIT_KEY_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x2000)|value<<13)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_FORCE_DISABLE_SW_INIT_KEY_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x2000) >> 13
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_XTS_KEY_LENGTH_256_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x4000)|value<<14)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_XTS_KEY_LENGTH_256_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x4000) >> 14
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x30000)|value<<16)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_WDT_DELAY_SEL_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x30000) >> 16
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x1c0000)|value<<18)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x1c0000) >> 18
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x200000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x200000) >> 21
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x400000)|value<<22)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x400000) >> 22
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0x800000)|value<<23)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0x800000) >> 23
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf000000)|value<<24)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_0_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf000000) >> 24
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR1.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg)&^(0xf0000000)|value<<28)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR1_KEY_PURPOSE_1_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR1.Reg) & 0xf0000000) >> 28
}

// EFUSE.RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0.
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_2_ERR() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0)|value<<4)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_3_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0) >> 4
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf00)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_4_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf00) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf000)|value<<12)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_KEY_PURPOSE_5_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf000) >> 12
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x30000)|value<<16)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x30000) >> 16
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_ECDSA_ENABLE_SOFT_K_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x40000)|value<<18)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_ECDSA_ENABLE_SOFT_K_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x40000) >> 18
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x80000)|value<<19)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x80000) >> 19
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x100000)|value<<20)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_EN_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x100000) >> 20
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x200000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x200000) >> 21
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TYPE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x800000)|value<<23)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TYPE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x800000) >> 23
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_PAGE_SIZE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x3000000)|value<<24)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_PAGE_SIZE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x3000000) >> 24
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_ECC_EN_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x4000000)|value<<26)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_ECC_EN_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x4000000) >> 26
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_DIS_USB_OTG_DOWNLOAD_MODE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0x8000000)|value<<27)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_DIS_USB_OTG_DOWNLOAD_MODE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0x8000000) >> 27
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR2_FLASH_TPUW_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR2.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg)&^(0xf0000000)|value<<28)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR2_FLASH_TPUW_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR2.Reg) & 0xf0000000) >> 28
}

// EFUSE.RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0.
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2) >> 1
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4)|value<<2)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4) >> 2
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_LOCK_KM_KEY_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x8)|value<<3)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_LOCK_KM_KEY_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x8) >> 3
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x10)|value<<4)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x10) >> 4
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x20)|value<<5)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x20) >> 5
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xc0)|value<<6)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xc0) >> 6
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x100)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x100) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_VERSION_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x1fffe00)|value<<9)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_VERSION_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x1fffe00) >> 9
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x2000000)|value<<25)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x2000000) >> 25
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_HYS_EN_PAD_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0x4000000)|value<<26)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_HYS_EN_PAD_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0x4000000) >> 26
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR3_DCDC_VSET_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR3.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg)&^(0xf8000000)|value<<27)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR3_DCDC_VSET_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR3.Reg) & 0xf8000000) >> 27
}

// EFUSE.RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0.
func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_0_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x3)|value)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_0_ERR() uint32 {
	return volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x3
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_1_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xc)|value<<2)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_1_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xc) >> 2
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_2_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x30)|value<<4)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_2_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x30) >> 4
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4__0PXA_TIEH_SEL_3_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xc0)|value<<6)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4__0PXA_TIEH_SEL_3_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xc0) >> 6
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4_KM_DISABLE_DEPLOY_MODE_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xf00)|value<<8)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4_KM_DISABLE_DEPLOY_MODE_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xf00) >> 8
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4_USB_DEVICE_DREFL_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x3000)|value<<12)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4_USB_DEVICE_DREFL_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x3000) >> 12
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4_USB_OTG11_DREFL_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0xc000)|value<<14)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4_USB_OTG11_DREFL_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0xc000) >> 14
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4_HP_PWR_SRC_SEL_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x40000)|value<<18)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4_HP_PWR_SRC_SEL_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x40000) >> 18
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4_DCDC_VSET_EN_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x80000)|value<<19)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4_DCDC_VSET_EN_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x80000) >> 19
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4_DIS_WDT_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x100000)|value<<20)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4_DIS_WDT_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x100000) >> 20
}
func (o *EFUSE_Type) SetRD_REPEAT_ERR4_DIS_SWD_ERR(value uint32) {
	volatile.StoreUint32(&o.RD_REPEAT_ERR4.Reg, volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg)&^(0x200000)|value<<21)
}
func (o *EFUSE_Type) GetRD_REPEAT_ERR4_DIS_SWD_ERR() uint32 {
	return (volatile.LoadUint32(&o.RD_REPEAT_ERR4.Reg) & 0x200000) >> 21
}

// EFUSE.RD_RS_ERR0: Programming error record register 0 of BLOCK1-10.
func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SYS_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7)|value)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SYS_ERR_NUM() uint32 {
	return volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7
}
func (o *EFUSE_Type) SetRD_RS_ERR0_MAC_SYS_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8)|value<<3)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_MAC_SYS_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8) >> 3
}
func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70)|value<<4)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70) >> 4
}
func (o *EFUSE_Type) SetRD_RS_ERR0_SYS_PART1_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80)|value<<7)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_SYS_PART1_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80) >> 7
}
func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700)|value<<8)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700) >> 8
}
func (o *EFUSE_Type) SetRD_RS_ERR0_USR_DATA_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800)|value<<11)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_USR_DATA_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800) >> 11
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000)|value<<12)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000) >> 12
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY0_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000)|value<<15)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY0_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000) >> 15
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000)|value<<16)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000) >> 16
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY1_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000)|value<<19)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY1_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000) >> 19
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x700000)|value<<20)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x700000) >> 20
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY2_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x800000)|value<<23)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY2_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x800000) >> 23
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x7000000)|value<<24)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x7000000) >> 24
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY3_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x8000000)|value<<27)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY3_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x8000000) >> 27
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x70000000)|value<<28)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x70000000) >> 28
}
func (o *EFUSE_Type) SetRD_RS_ERR0_KEY4_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR0.Reg, volatile.LoadUint32(&o.RD_RS_ERR0.Reg)&^(0x80000000)|value<<31)
}
func (o *EFUSE_Type) GetRD_RS_ERR0_KEY4_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR0.Reg) & 0x80000000) >> 31
}

// EFUSE.RD_RS_ERR1: Programming error record register 1 of BLOCK1-10.
func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x7)|value)
}
func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_ERR_NUM() uint32 {
	return volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x7
}
func (o *EFUSE_Type) SetRD_RS_ERR1_KEY5_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x8)|value<<3)
}
func (o *EFUSE_Type) GetRD_RS_ERR1_KEY5_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x8) >> 3
}
func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_ERR_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x70)|value<<4)
}
func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_ERR_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x70) >> 4
}
func (o *EFUSE_Type) SetRD_RS_ERR1_SYS_PART2_FAIL(value uint32) {
	volatile.StoreUint32(&o.RD_RS_ERR1.Reg, volatile.LoadUint32(&o.RD_RS_ERR1.Reg)&^(0x80)|value<<7)
}
func (o *EFUSE_Type) GetRD_RS_ERR1_SYS_PART2_FAIL() uint32 {
	return (volatile.LoadUint32(&o.RD_RS_ERR1.Reg) & 0x80) >> 7
}

// EFUSE.CLK: eFuse clcok configuration register.
func (o *EFUSE_Type) SetCLK_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetCLK_MEM_FORCE_PD() uint32 {
	return volatile.LoadUint32(&o.CLK.Reg) & 0x1
}
func (o *EFUSE_Type) SetCLK_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetCLK_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1
}
func (o *EFUSE_Type) SetCLK_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x4)|value<<2)
}
func (o *EFUSE_Type) GetCLK_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0x4) >> 2
}
func (o *EFUSE_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x10000)|value<<16)
}
func (o *EFUSE_Type) GetCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0x10000) >> 16
}

// EFUSE.CONF: eFuse operation mode configuraiton register
func (o *EFUSE_Type) SetCONF_OP_CODE(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xffff)|value)
}
func (o *EFUSE_Type) GetCONF_OP_CODE() uint32 {
	return volatile.LoadUint32(&o.CONF.Reg) & 0xffff
}
func (o *EFUSE_Type) SetCONF_CFG_ECDSA_BLK(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xf0000)|value<<16)
}
func (o *EFUSE_Type) GetCONF_CFG_ECDSA_BLK() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0xf0000) >> 16
}

// EFUSE.STATUS: eFuse status register.
func (o *EFUSE_Type) SetSTATUS_STATE(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf)|value)
}
func (o *EFUSE_Type) GetSTATUS_STATE() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg) & 0xf
}
func (o *EFUSE_Type) SetSTATUS_OTP_LOAD_SW(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4)
}
func (o *EFUSE_Type) GetSTATUS_OTP_LOAD_SW() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4
}
func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_C_SYNC2(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5)
}
func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_C_SYNC2() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5
}
func (o *EFUSE_Type) SetSTATUS_OTP_STROBE_SW(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6)
}
func (o *EFUSE_Type) GetSTATUS_OTP_STROBE_SW() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6
}
func (o *EFUSE_Type) SetSTATUS_OTP_CSB_SW(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7)
}
func (o *EFUSE_Type) GetSTATUS_OTP_CSB_SW() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7
}
func (o *EFUSE_Type) SetSTATUS_OTP_PGENB_SW(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8)
}
func (o *EFUSE_Type) GetSTATUS_OTP_PGENB_SW() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8
}
func (o *EFUSE_Type) SetSTATUS_OTP_VDDQ_IS_SW(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9)
}
func (o *EFUSE_Type) GetSTATUS_OTP_VDDQ_IS_SW() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9
}
func (o *EFUSE_Type) SetSTATUS_BLK0_VALID_BIT_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xffc00)|value<<10)
}
func (o *EFUSE_Type) GetSTATUS_BLK0_VALID_BIT_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0xffc00) >> 10
}
func (o *EFUSE_Type) SetSTATUS_CUR_ECDSA_BLK(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf00000)|value<<20)
}
func (o *EFUSE_Type) GetSTATUS_CUR_ECDSA_BLK() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf00000) >> 20
}

// EFUSE.CMD: eFuse command register.
func (o *EFUSE_Type) SetCMD_READ_CMD(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetCMD_READ_CMD() uint32 {
	return volatile.LoadUint32(&o.CMD.Reg) & 0x1
}
func (o *EFUSE_Type) SetCMD_PGM_CMD(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetCMD_PGM_CMD() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1
}
func (o *EFUSE_Type) SetCMD_BLK_NUM(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3c)|value<<2)
}
func (o *EFUSE_Type) GetCMD_BLK_NUM() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x3c) >> 2
}

// EFUSE.INT_RAW: eFuse raw interrupt register.
func (o *EFUSE_Type) SetINT_RAW_READ_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetINT_RAW_READ_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *EFUSE_Type) SetINT_RAW_PGM_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetINT_RAW_PGM_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}

// EFUSE.INT_ST: eFuse interrupt status register.
func (o *EFUSE_Type) SetINT_ST_READ_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetINT_ST_READ_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *EFUSE_Type) SetINT_ST_PGM_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetINT_ST_PGM_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}

// EFUSE.INT_ENA: eFuse interrupt enable register.
func (o *EFUSE_Type) SetINT_ENA_READ_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetINT_ENA_READ_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *EFUSE_Type) SetINT_ENA_PGM_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetINT_ENA_PGM_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}

// EFUSE.INT_CLR: eFuse interrupt clear register.
func (o *EFUSE_Type) SetINT_CLR_READ_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetINT_CLR_READ_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *EFUSE_Type) SetINT_CLR_PGM_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *EFUSE_Type) GetINT_CLR_PGM_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}

// EFUSE.DAC_CONF: Controls the eFuse programming voltage.
func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_DIV(value uint32) {
	volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0xff)|value)
}
func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_DIV() uint32 {
	return volatile.LoadUint32(&o.DAC_CONF.Reg) & 0xff
}
func (o *EFUSE_Type) SetDAC_CONF_DAC_CLK_PAD_SEL(value uint32) {
	volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x100)|value<<8)
}
func (o *EFUSE_Type) GetDAC_CONF_DAC_CLK_PAD_SEL() uint32 {
	return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x100) >> 8
}
func (o *EFUSE_Type) SetDAC_CONF_DAC_NUM(value uint32) {
	volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x1fe00)|value<<9)
}
func (o *EFUSE_Type) GetDAC_CONF_DAC_NUM() uint32 {
	return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x1fe00) >> 9
}
func (o *EFUSE_Type) SetDAC_CONF_OE_CLR(value uint32) {
	volatile.StoreUint32(&o.DAC_CONF.Reg, volatile.LoadUint32(&o.DAC_CONF.Reg)&^(0x20000)|value<<17)
}
func (o *EFUSE_Type) GetDAC_CONF_OE_CLR() uint32 {
	return (volatile.LoadUint32(&o.DAC_CONF.Reg) & 0x20000) >> 17
}

// EFUSE.RD_TIM_CONF: Configures read timing parameters.
func (o *EFUSE_Type) SetRD_TIM_CONF_THR_A(value uint32) {
	volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff)|value)
}
func (o *EFUSE_Type) GetRD_TIM_CONF_THR_A() uint32 {
	return volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff
}
func (o *EFUSE_Type) SetRD_TIM_CONF_TRD(value uint32) {
	volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff00)|value<<8)
}
func (o *EFUSE_Type) GetRD_TIM_CONF_TRD() uint32 {
	return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff00) >> 8
}
func (o *EFUSE_Type) SetRD_TIM_CONF_TSUR_A(value uint32) {
	volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff0000)|value<<16)
}
func (o *EFUSE_Type) GetRD_TIM_CONF_TSUR_A() uint32 {
	return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff0000) >> 16
}
func (o *EFUSE_Type) SetRD_TIM_CONF_READ_INIT_NUM(value uint32) {
	volatile.StoreUint32(&o.RD_TIM_CONF.Reg, volatile.LoadUint32(&o.RD_TIM_CONF.Reg)&^(0xff000000)|value<<24)
}
func (o *EFUSE_Type) GetRD_TIM_CONF_READ_INIT_NUM() uint32 {
	return (volatile.LoadUint32(&o.RD_TIM_CONF.Reg) & 0xff000000) >> 24
}

// EFUSE.WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters.
func (o *EFUSE_Type) SetWR_TIM_CONF1_TSUP_A(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff)|value)
}
func (o *EFUSE_Type) GetWR_TIM_CONF1_TSUP_A() uint32 {
	return volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff
}
func (o *EFUSE_Type) SetWR_TIM_CONF1_PWR_ON_NUM(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xffff00)|value<<8)
}
func (o *EFUSE_Type) GetWR_TIM_CONF1_PWR_ON_NUM() uint32 {
	return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xffff00) >> 8
}
func (o *EFUSE_Type) SetWR_TIM_CONF1_THP_A(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF1.Reg, volatile.LoadUint32(&o.WR_TIM_CONF1.Reg)&^(0xff000000)|value<<24)
}
func (o *EFUSE_Type) GetWR_TIM_CONF1_THP_A() uint32 {
	return (volatile.LoadUint32(&o.WR_TIM_CONF1.Reg) & 0xff000000) >> 24
}

// EFUSE.WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters.
func (o *EFUSE_Type) SetWR_TIM_CONF2_PWR_OFF_NUM(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff)|value)
}
func (o *EFUSE_Type) GetWR_TIM_CONF2_PWR_OFF_NUM() uint32 {
	return volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff
}
func (o *EFUSE_Type) SetWR_TIM_CONF2_TPGM(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF2.Reg, volatile.LoadUint32(&o.WR_TIM_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *EFUSE_Type) GetWR_TIM_CONF2_TPGM() uint32 {
	return (volatile.LoadUint32(&o.WR_TIM_CONF2.Reg) & 0xffff0000) >> 16
}

// EFUSE.WR_TIM_CONF0_RS_BYPASS: Configurarion register0 of eFuse programming time parameters and rs bypass operation.
func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION() uint32 {
	return volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1
}
func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0xffe)|value<<1)
}
func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM() uint32 {
	return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0xffe) >> 1
}
func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_UPDATE(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1000)|value<<12)
}
func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1000) >> 12
}
func (o *EFUSE_Type) SetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE(value uint32) {
	volatile.StoreUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg, volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg)&^(0x1fe000)|value<<13)
}
func (o *EFUSE_Type) GetWR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE() uint32 {
	return (volatile.LoadUint32(&o.WR_TIM_CONF0_RS_BYPASS.Reg) & 0x1fe000) >> 13
}

// EFUSE.DATE: eFuse version register.
func (o *EFUSE_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *EFUSE_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// EFUSE.APB2OTP_WR_DIS: eFuse apb2otp block0 data register1.
func (o *EFUSE_Type) SetAPB2OTP_WR_DIS(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_WR_DIS.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_WR_DIS() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_WR_DIS.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP1_W1: eFuse apb2otp block0 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W1.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP1_W2: eFuse apb2otp block0 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W2.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP1_W3: eFuse apb2otp block0 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W3.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP1_W4: eFuse apb2otp block0 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W4.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP1_W5: eFuse apb2otp block0 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP1_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP1_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP1_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP1_W5.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP2_W1: eFuse apb2otp block0 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W1.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP2_W2: eFuse apb2otp block0 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W2.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP2_W3: eFuse apb2otp block0 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W3.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP2_W4: eFuse apb2otp block0 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W4.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP2_W5: eFuse apb2otp block0 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP2_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP2_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP2_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP2_W5.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP3_W1: eFuse apb2otp block0 data register12.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W1.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP3_W2: eFuse apb2otp block0 data register13.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W2.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP3_W3: eFuse apb2otp block0 data register14.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W3.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP3_W4: eFuse apb2otp block0 data register15.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W4.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP3_W5: eFuse apb2otp block0 data register16.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP3_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP3_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP3_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP3_W5.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP4_W1: eFuse apb2otp block0 data register17.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W1.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP4_W2: eFuse apb2otp block0 data register18.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W2.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP4_W3: eFuse apb2otp block0 data register19.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W3.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP4_W4: eFuse apb2otp block0 data register20.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W4.Reg)
}

// EFUSE.APB2OTP_BLK0_BACKUP4_W5: eFuse apb2otp block0 data register21.
func (o *EFUSE_Type) SetAPB2OTP_BLK0_BACKUP4_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK0_BACKUP4_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK0_BACKUP4_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK0_BACKUP4_W5.Reg)
}

// EFUSE.APB2OTP_BLK1_W1: eFuse apb2otp block1 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W1.Reg)
}

// EFUSE.APB2OTP_BLK1_W2: eFuse apb2otp block1 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W2.Reg)
}

// EFUSE.APB2OTP_BLK1_W3: eFuse apb2otp block1 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W3.Reg)
}

// EFUSE.APB2OTP_BLK1_W4: eFuse apb2otp block1 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W4.Reg)
}

// EFUSE.APB2OTP_BLK1_W5: eFuse apb2otp block1 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W5.Reg)
}

// EFUSE.APB2OTP_BLK1_W6: eFuse apb2otp block1 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W6.Reg)
}

// EFUSE.APB2OTP_BLK1_W7: eFuse apb2otp block1 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W7.Reg)
}

// EFUSE.APB2OTP_BLK1_W8: eFuse apb2otp block1 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W8.Reg)
}

// EFUSE.APB2OTP_BLK1_W9: eFuse apb2otp block1 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK1_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK1_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK1_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK1_W9.Reg)
}

// EFUSE.APB2OTP_BLK2_W1: eFuse apb2otp block2 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W1.Reg)
}

// EFUSE.APB2OTP_BLK2_W2: eFuse apb2otp block2 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W2.Reg)
}

// EFUSE.APB2OTP_BLK2_W3: eFuse apb2otp block2 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W3.Reg)
}

// EFUSE.APB2OTP_BLK2_W4: eFuse apb2otp block2 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W4.Reg)
}

// EFUSE.APB2OTP_BLK2_W5: eFuse apb2otp block2 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W5.Reg)
}

// EFUSE.APB2OTP_BLK2_W6: eFuse apb2otp block2 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W6.Reg)
}

// EFUSE.APB2OTP_BLK2_W7: eFuse apb2otp block2 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W7.Reg)
}

// EFUSE.APB2OTP_BLK2_W8: eFuse apb2otp block2 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W8.Reg)
}

// EFUSE.APB2OTP_BLK2_W9: eFuse apb2otp block2 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W9.Reg)
}

// EFUSE.APB2OTP_BLK2_W10: eFuse apb2otp block2 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W10.Reg)
}

// EFUSE.APB2OTP_BLK2_W11: eFuse apb2otp block2 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK2_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK2_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK2_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK2_W11.Reg)
}

// EFUSE.APB2OTP_BLK3_W1: eFuse apb2otp block3 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W1.Reg)
}

// EFUSE.APB2OTP_BLK3_W2: eFuse apb2otp block3 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W2.Reg)
}

// EFUSE.APB2OTP_BLK3_W3: eFuse apb2otp block3 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W3.Reg)
}

// EFUSE.APB2OTP_BLK3_W4: eFuse apb2otp block3 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W4.Reg)
}

// EFUSE.APB2OTP_BLK3_W5: eFuse apb2otp block3 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W5.Reg)
}

// EFUSE.APB2OTP_BLK3_W6: eFuse apb2otp block3 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W6.Reg)
}

// EFUSE.APB2OTP_BLK3_W7: eFuse apb2otp block3 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W7.Reg)
}

// EFUSE.APB2OTP_BLK3_W8: eFuse apb2otp block3 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W8.Reg)
}

// EFUSE.APB2OTP_BLK3_W9: eFuse apb2otp block3 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W9.Reg)
}

// EFUSE.APB2OTP_BLK3_W10: eFuse apb2otp block3 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W10.Reg)
}

// EFUSE.APB2OTP_BLK3_W11: eFuse apb2otp block3 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK3_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK3_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK3_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK3_W11.Reg)
}

// EFUSE.APB2OTP_BLK4_W1: eFuse apb2otp block4 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W1.Reg)
}

// EFUSE.APB2OTP_BLK4_W2: eFuse apb2otp block4 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W2.Reg)
}

// EFUSE.APB2OTP_BLK4_W3: eFuse apb2otp block4 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W3.Reg)
}

// EFUSE.APB2OTP_BLK4_W4: eFuse apb2otp block4 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W4.Reg)
}

// EFUSE.APB2OTP_BLK4_W5: eFuse apb2otp block4 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W5.Reg)
}

// EFUSE.APB2OTP_BLK4_W6: eFuse apb2otp block4 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W6.Reg)
}

// EFUSE.APB2OTP_BLK4_W7: eFuse apb2otp block4 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W7.Reg)
}

// EFUSE.APB2OTP_BLK4_W8: eFuse apb2otp block4 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W8.Reg)
}

// EFUSE.APB2OTP_BLK4_W9: eFuse apb2otp block4 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W9.Reg)
}

// EFUSE.APB2OTP_BLK4_W10: eFuse apb2otp block4 data registe10.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W10.Reg)
}

// EFUSE.APB2OTP_BLK4_W11: eFuse apb2otp block4 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK4_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK4_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK4_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK4_W11.Reg)
}

// EFUSE.APB2OTP_BLK5_W1: eFuse apb2otp block5 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W1.Reg)
}

// EFUSE.APB2OTP_BLK5_W2: eFuse apb2otp block5 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W2.Reg)
}

// EFUSE.APB2OTP_BLK5_W3: eFuse apb2otp block5 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W3.Reg)
}

// EFUSE.APB2OTP_BLK5_W4: eFuse apb2otp block5 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W4.Reg)
}

// EFUSE.APB2OTP_BLK5_W5: eFuse apb2otp block5 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W5.Reg)
}

// EFUSE.APB2OTP_BLK5_W6: eFuse apb2otp block5 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W6.Reg)
}

// EFUSE.APB2OTP_BLK5_W7: eFuse apb2otp block5 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W7.Reg)
}

// EFUSE.APB2OTP_BLK5_W8: eFuse apb2otp block5 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W8.Reg)
}

// EFUSE.APB2OTP_BLK5_W9: eFuse apb2otp block5 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W9.Reg)
}

// EFUSE.APB2OTP_BLK5_W10: eFuse apb2otp block5 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W10.Reg)
}

// EFUSE.APB2OTP_BLK5_W11: eFuse apb2otp block5 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK5_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK5_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK5_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK5_W11.Reg)
}

// EFUSE.APB2OTP_BLK6_W1: eFuse apb2otp block6 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W1.Reg)
}

// EFUSE.APB2OTP_BLK6_W2: eFuse apb2otp block6 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W2.Reg)
}

// EFUSE.APB2OTP_BLK6_W3: eFuse apb2otp block6 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W3.Reg)
}

// EFUSE.APB2OTP_BLK6_W4: eFuse apb2otp block6 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W4.Reg)
}

// EFUSE.APB2OTP_BLK6_W5: eFuse apb2otp block6 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W5.Reg)
}

// EFUSE.APB2OTP_BLK6_W6: eFuse apb2otp block6 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W6.Reg)
}

// EFUSE.APB2OTP_BLK6_W7: eFuse apb2otp block6 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W7.Reg)
}

// EFUSE.APB2OTP_BLK6_W8: eFuse apb2otp block6 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W8.Reg)
}

// EFUSE.APB2OTP_BLK6_W9: eFuse apb2otp block6 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W9.Reg)
}

// EFUSE.APB2OTP_BLK6_W10: eFuse apb2otp block6 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W10.Reg)
}

// EFUSE.APB2OTP_BLK6_W11: eFuse apb2otp block6 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK6_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK6_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK6_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK6_W11.Reg)
}

// EFUSE.APB2OTP_BLK7_W1: eFuse apb2otp block7 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W1.Reg)
}

// EFUSE.APB2OTP_BLK7_W2: eFuse apb2otp block7 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W2.Reg)
}

// EFUSE.APB2OTP_BLK7_W3: eFuse apb2otp block7 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W3.Reg)
}

// EFUSE.APB2OTP_BLK7_W4: eFuse apb2otp block7 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W4.Reg)
}

// EFUSE.APB2OTP_BLK7_W5: eFuse apb2otp block7 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W5.Reg)
}

// EFUSE.APB2OTP_BLK7_W6: eFuse apb2otp block7 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W6.Reg)
}

// EFUSE.APB2OTP_BLK7_W7: eFuse apb2otp block7 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W7.Reg)
}

// EFUSE.APB2OTP_BLK7_W8: eFuse apb2otp block7 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W8.Reg)
}

// EFUSE.APB2OTP_BLK7_W9: eFuse apb2otp block7 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W9.Reg)
}

// EFUSE.APB2OTP_BLK7_W10: eFuse apb2otp block7 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W10.Reg)
}

// EFUSE.APB2OTP_BLK7_W11: eFuse apb2otp block7 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK7_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK7_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK7_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK7_W11.Reg)
}

// EFUSE.APB2OTP_BLK8_W1: eFuse apb2otp block8 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W1.Reg)
}

// EFUSE.APB2OTP_BLK8_W2: eFuse apb2otp block8 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W2.Reg)
}

// EFUSE.APB2OTP_BLK8_W3: eFuse apb2otp block8 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W3.Reg)
}

// EFUSE.APB2OTP_BLK8_W4: eFuse apb2otp block8 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W4.Reg)
}

// EFUSE.APB2OTP_BLK8_W5: eFuse apb2otp block8 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W5.Reg)
}

// EFUSE.APB2OTP_BLK8_W6: eFuse apb2otp block8 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W6.Reg)
}

// EFUSE.APB2OTP_BLK8_W7: eFuse apb2otp block8 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W7.Reg)
}

// EFUSE.APB2OTP_BLK8_W8: eFuse apb2otp block8 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W8.Reg)
}

// EFUSE.APB2OTP_BLK8_W9: eFuse apb2otp block8 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W9.Reg)
}

// EFUSE.APB2OTP_BLK8_W10: eFuse apb2otp block8 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W10.Reg)
}

// EFUSE.APB2OTP_BLK8_W11: eFuse apb2otp block8 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK8_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK8_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK8_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK8_W11.Reg)
}

// EFUSE.APB2OTP_BLK9_W1: eFuse apb2otp block9 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W1.Reg)
}

// EFUSE.APB2OTP_BLK9_W2: eFuse apb2otp block9 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W2.Reg)
}

// EFUSE.APB2OTP_BLK9_W3: eFuse apb2otp block9 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W3.Reg)
}

// EFUSE.APB2OTP_BLK9_W4: eFuse apb2otp block9 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W4.Reg)
}

// EFUSE.APB2OTP_BLK9_W5: eFuse apb2otp block9 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W5.Reg)
}

// EFUSE.APB2OTP_BLK9_W6: eFuse apb2otp block9 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W6.Reg)
}

// EFUSE.APB2OTP_BLK9_W7: eFuse apb2otp block9 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W7.Reg)
}

// EFUSE.APB2OTP_BLK9_W8: eFuse apb2otp block9 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W8.Reg)
}

// EFUSE.APB2OTP_BLK9_W9: eFuse apb2otp block9 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W9.Reg)
}

// EFUSE.APB2OTP_BLK9_W10: eFuse apb2otp block9 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W10.Reg)
}

// EFUSE.APB2OTP_BLK9_W11: eFuse apb2otp block9 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK9_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK9_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK9_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK9_W11.Reg)
}

// EFUSE.APB2OTP_BLK10_W1: eFuse apb2otp block10 data register1.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W1(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W1.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W1() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W1.Reg)
}

// EFUSE.APB2OTP_BLK10_W2: eFuse apb2otp block10 data register2.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W2(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W2.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W2() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W2.Reg)
}

// EFUSE.APB2OTP_BLK10_W3: eFuse apb2otp block10 data register3.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W3(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W3.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W3() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W3.Reg)
}

// EFUSE.APB2OTP_BLK10_W4: eFuse apb2otp block10 data register4.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W4(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W4.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W4() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W4.Reg)
}

// EFUSE.APB2OTP_BLK10_W5: eFuse apb2otp block10 data register5.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W5(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W5.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W5() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W5.Reg)
}

// EFUSE.APB2OTP_BLK10_W6: eFuse apb2otp block10 data register6.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W6(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W6.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W6() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W6.Reg)
}

// EFUSE.APB2OTP_BLK10_W7: eFuse apb2otp block10 data register7.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W7(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W7.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W7() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W7.Reg)
}

// EFUSE.APB2OTP_BLK10_W8: eFuse apb2otp block10 data register8.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W8(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W8.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W8() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W8.Reg)
}

// EFUSE.APB2OTP_BLK10_W9: eFuse apb2otp block10 data register9.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W9(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W9.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W9() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W9.Reg)
}

// EFUSE.APB2OTP_BLK10_W10: eFuse apb2otp block10 data register10.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W10(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W10.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W10() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W10.Reg)
}

// EFUSE.APB2OTP_BLK10_W11: eFuse apb2otp block10 data register11.
func (o *EFUSE_Type) SetAPB2OTP_BLK10_W11(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_BLK10_W11.Reg, value)
}
func (o *EFUSE_Type) GetAPB2OTP_BLK10_W11() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_BLK10_W11.Reg)
}

// EFUSE.APB2OTP_EN: eFuse apb2otp enable configuration register.
func (o *EFUSE_Type) SetAPB2OTP_EN_APB2OTP_APB2OTP_EN(value uint32) {
	volatile.StoreUint32(&o.APB2OTP_EN.Reg, volatile.LoadUint32(&o.APB2OTP_EN.Reg)&^(0x1)|value)
}
func (o *EFUSE_Type) GetAPB2OTP_EN_APB2OTP_APB2OTP_EN() uint32 {
	return volatile.LoadUint32(&o.APB2OTP_EN.Reg) & 0x1
}

// General Purpose Input/Output
type GPIO_Type struct {
	BT_SELECT            volatile.Register32 // 0x0
	OUT                  volatile.Register32 // 0x4
	OUT_W1TS             volatile.Register32 // 0x8
	OUT_W1TC             volatile.Register32 // 0xC
	OUT1                 volatile.Register32 // 0x10
	OUT1_W1TS            volatile.Register32 // 0x14
	OUT1_W1TC            volatile.Register32 // 0x18
	_                    [4]byte
	ENABLE               volatile.Register32 // 0x20
	ENABLE_W1TS          volatile.Register32 // 0x24
	ENABLE_W1TC          volatile.Register32 // 0x28
	ENABLE1              volatile.Register32 // 0x2C
	ENABLE1_W1TS         volatile.Register32 // 0x30
	ENABLE1_W1TC         volatile.Register32 // 0x34
	STRAP                volatile.Register32 // 0x38
	IN                   volatile.Register32 // 0x3C
	IN1                  volatile.Register32 // 0x40
	STATUS               volatile.Register32 // 0x44
	STATUS_W1TS          volatile.Register32 // 0x48
	STATUS_W1TC          volatile.Register32 // 0x4C
	STATUS1              volatile.Register32 // 0x50
	STATUS1_W1TS         volatile.Register32 // 0x54
	STATUS1_W1TC         volatile.Register32 // 0x58
	INTR_0               volatile.Register32 // 0x5C
	INTR1_0              volatile.Register32 // 0x60
	INTR_1               volatile.Register32 // 0x64
	INTR1_1              volatile.Register32 // 0x68
	STATUS_NEXT          volatile.Register32 // 0x6C
	STATUS_NEXT1         volatile.Register32 // 0x70
	PIN0                 volatile.Register32 // 0x74
	PIN1                 volatile.Register32 // 0x78
	PIN2                 volatile.Register32 // 0x7C
	PIN3                 volatile.Register32 // 0x80
	PIN4                 volatile.Register32 // 0x84
	PIN5                 volatile.Register32 // 0x88
	PIN6                 volatile.Register32 // 0x8C
	PIN7                 volatile.Register32 // 0x90
	PIN8                 volatile.Register32 // 0x94
	PIN9                 volatile.Register32 // 0x98
	PIN10                volatile.Register32 // 0x9C
	PIN11                volatile.Register32 // 0xA0
	PIN12                volatile.Register32 // 0xA4
	PIN13                volatile.Register32 // 0xA8
	PIN14                volatile.Register32 // 0xAC
	PIN15                volatile.Register32 // 0xB0
	PIN16                volatile.Register32 // 0xB4
	PIN17                volatile.Register32 // 0xB8
	PIN18                volatile.Register32 // 0xBC
	PIN19                volatile.Register32 // 0xC0
	PIN20                volatile.Register32 // 0xC4
	PIN21                volatile.Register32 // 0xC8
	PIN22                volatile.Register32 // 0xCC
	PIN23                volatile.Register32 // 0xD0
	PIN24                volatile.Register32 // 0xD4
	PIN25                volatile.Register32 // 0xD8
	PIN26                volatile.Register32 // 0xDC
	PIN27                volatile.Register32 // 0xE0
	PIN28                volatile.Register32 // 0xE4
	PIN29                volatile.Register32 // 0xE8
	PIN30                volatile.Register32 // 0xEC
	PIN31                volatile.Register32 // 0xF0
	PIN32                volatile.Register32 // 0xF4
	PIN33                volatile.Register32 // 0xF8
	PIN34                volatile.Register32 // 0xFC
	PIN35                volatile.Register32 // 0x100
	PIN36                volatile.Register32 // 0x104
	PIN37                volatile.Register32 // 0x108
	PIN38                volatile.Register32 // 0x10C
	PIN39                volatile.Register32 // 0x110
	PIN40                volatile.Register32 // 0x114
	PIN41                volatile.Register32 // 0x118
	PIN42                volatile.Register32 // 0x11C
	PIN43                volatile.Register32 // 0x120
	PIN44                volatile.Register32 // 0x124
	PIN45                volatile.Register32 // 0x128
	PIN46                volatile.Register32 // 0x12C
	PIN47                volatile.Register32 // 0x130
	PIN48                volatile.Register32 // 0x134
	PIN49                volatile.Register32 // 0x138
	PIN50                volatile.Register32 // 0x13C
	PIN51                volatile.Register32 // 0x140
	PIN52                volatile.Register32 // 0x144
	PIN53                volatile.Register32 // 0x148
	PIN54                volatile.Register32 // 0x14C
	PIN55                volatile.Register32 // 0x150
	PIN56                volatile.Register32 // 0x154
	_                    [4]byte
	FUNC1_IN_SEL_CFG     volatile.Register32 // 0x15C
	FUNC2_IN_SEL_CFG     volatile.Register32 // 0x160
	FUNC3_IN_SEL_CFG     volatile.Register32 // 0x164
	FUNC4_IN_SEL_CFG     volatile.Register32 // 0x168
	FUNC5_IN_SEL_CFG     volatile.Register32 // 0x16C
	FUNC6_IN_SEL_CFG     volatile.Register32 // 0x170
	FUNC7_IN_SEL_CFG     volatile.Register32 // 0x174
	FUNC8_IN_SEL_CFG     volatile.Register32 // 0x178
	FUNC9_IN_SEL_CFG     volatile.Register32 // 0x17C
	FUNC10_IN_SEL_CFG    volatile.Register32 // 0x180
	FUNC11_IN_SEL_CFG    volatile.Register32 // 0x184
	FUNC12_IN_SEL_CFG    volatile.Register32 // 0x188
	FUNC13_IN_SEL_CFG    volatile.Register32 // 0x18C
	FUNC14_IN_SEL_CFG    volatile.Register32 // 0x190
	FUNC15_IN_SEL_CFG    volatile.Register32 // 0x194
	FUNC16_IN_SEL_CFG    volatile.Register32 // 0x198
	FUNC17_IN_SEL_CFG    volatile.Register32 // 0x19C
	FUNC18_IN_SEL_CFG    volatile.Register32 // 0x1A0
	FUNC19_IN_SEL_CFG    volatile.Register32 // 0x1A4
	FUNC20_IN_SEL_CFG    volatile.Register32 // 0x1A8
	FUNC21_IN_SEL_CFG    volatile.Register32 // 0x1AC
	FUNC22_IN_SEL_CFG    volatile.Register32 // 0x1B0
	FUNC23_IN_SEL_CFG    volatile.Register32 // 0x1B4
	FUNC24_IN_SEL_CFG    volatile.Register32 // 0x1B8
	FUNC25_IN_SEL_CFG    volatile.Register32 // 0x1BC
	FUNC26_IN_SEL_CFG    volatile.Register32 // 0x1C0
	FUNC27_IN_SEL_CFG    volatile.Register32 // 0x1C4
	FUNC28_IN_SEL_CFG    volatile.Register32 // 0x1C8
	FUNC29_IN_SEL_CFG    volatile.Register32 // 0x1CC
	FUNC30_IN_SEL_CFG    volatile.Register32 // 0x1D0
	FUNC31_IN_SEL_CFG    volatile.Register32 // 0x1D4
	FUNC32_IN_SEL_CFG    volatile.Register32 // 0x1D8
	FUNC33_IN_SEL_CFG    volatile.Register32 // 0x1DC
	FUNC34_IN_SEL_CFG    volatile.Register32 // 0x1E0
	FUNC35_IN_SEL_CFG    volatile.Register32 // 0x1E4
	FUNC36_IN_SEL_CFG    volatile.Register32 // 0x1E8
	FUNC37_IN_SEL_CFG    volatile.Register32 // 0x1EC
	FUNC38_IN_SEL_CFG    volatile.Register32 // 0x1F0
	FUNC39_IN_SEL_CFG    volatile.Register32 // 0x1F4
	FUNC40_IN_SEL_CFG    volatile.Register32 // 0x1F8
	FUNC41_IN_SEL_CFG    volatile.Register32 // 0x1FC
	FUNC42_IN_SEL_CFG    volatile.Register32 // 0x200
	FUNC43_IN_SEL_CFG    volatile.Register32 // 0x204
	FUNC44_IN_SEL_CFG    volatile.Register32 // 0x208
	FUNC45_IN_SEL_CFG    volatile.Register32 // 0x20C
	FUNC46_IN_SEL_CFG    volatile.Register32 // 0x210
	FUNC47_IN_SEL_CFG    volatile.Register32 // 0x214
	FUNC48_IN_SEL_CFG    volatile.Register32 // 0x218
	FUNC49_IN_SEL_CFG    volatile.Register32 // 0x21C
	FUNC50_IN_SEL_CFG    volatile.Register32 // 0x220
	FUNC51_IN_SEL_CFG    volatile.Register32 // 0x224
	FUNC52_IN_SEL_CFG    volatile.Register32 // 0x228
	FUNC53_IN_SEL_CFG    volatile.Register32 // 0x22C
	FUNC54_IN_SEL_CFG    volatile.Register32 // 0x230
	FUNC55_IN_SEL_CFG    volatile.Register32 // 0x234
	FUNC56_IN_SEL_CFG    volatile.Register32 // 0x238
	FUNC57_IN_SEL_CFG    volatile.Register32 // 0x23C
	FUNC58_IN_SEL_CFG    volatile.Register32 // 0x240
	FUNC59_IN_SEL_CFG    volatile.Register32 // 0x244
	FUNC60_IN_SEL_CFG    volatile.Register32 // 0x248
	FUNC61_IN_SEL_CFG    volatile.Register32 // 0x24C
	FUNC62_IN_SEL_CFG    volatile.Register32 // 0x250
	FUNC63_IN_SEL_CFG    volatile.Register32 // 0x254
	FUNC64_IN_SEL_CFG    volatile.Register32 // 0x258
	FUNC65_IN_SEL_CFG    volatile.Register32 // 0x25C
	FUNC66_IN_SEL_CFG    volatile.Register32 // 0x260
	FUNC67_IN_SEL_CFG    volatile.Register32 // 0x264
	FUNC68_IN_SEL_CFG    volatile.Register32 // 0x268
	FUNC69_IN_SEL_CFG    volatile.Register32 // 0x26C
	FUNC70_IN_SEL_CFG    volatile.Register32 // 0x270
	FUNC71_IN_SEL_CFG    volatile.Register32 // 0x274
	FUNC72_IN_SEL_CFG    volatile.Register32 // 0x278
	FUNC73_IN_SEL_CFG    volatile.Register32 // 0x27C
	FUNC74_IN_SEL_CFG    volatile.Register32 // 0x280
	FUNC75_IN_SEL_CFG    volatile.Register32 // 0x284
	FUNC76_IN_SEL_CFG    volatile.Register32 // 0x288
	FUNC77_IN_SEL_CFG    volatile.Register32 // 0x28C
	FUNC78_IN_SEL_CFG    volatile.Register32 // 0x290
	FUNC79_IN_SEL_CFG    volatile.Register32 // 0x294
	FUNC80_IN_SEL_CFG    volatile.Register32 // 0x298
	FUNC81_IN_SEL_CFG    volatile.Register32 // 0x29C
	FUNC82_IN_SEL_CFG    volatile.Register32 // 0x2A0
	FUNC83_IN_SEL_CFG    volatile.Register32 // 0x2A4
	FUNC84_IN_SEL_CFG    volatile.Register32 // 0x2A8
	FUNC85_IN_SEL_CFG    volatile.Register32 // 0x2AC
	FUNC86_IN_SEL_CFG    volatile.Register32 // 0x2B0
	FUNC87_IN_SEL_CFG    volatile.Register32 // 0x2B4
	FUNC88_IN_SEL_CFG    volatile.Register32 // 0x2B8
	FUNC89_IN_SEL_CFG    volatile.Register32 // 0x2BC
	FUNC90_IN_SEL_CFG    volatile.Register32 // 0x2C0
	FUNC91_IN_SEL_CFG    volatile.Register32 // 0x2C4
	FUNC92_IN_SEL_CFG    volatile.Register32 // 0x2C8
	FUNC93_IN_SEL_CFG    volatile.Register32 // 0x2CC
	FUNC94_IN_SEL_CFG    volatile.Register32 // 0x2D0
	FUNC95_IN_SEL_CFG    volatile.Register32 // 0x2D4
	FUNC96_IN_SEL_CFG    volatile.Register32 // 0x2D8
	FUNC97_IN_SEL_CFG    volatile.Register32 // 0x2DC
	FUNC98_IN_SEL_CFG    volatile.Register32 // 0x2E0
	FUNC99_IN_SEL_CFG    volatile.Register32 // 0x2E4
	FUNC100_IN_SEL_CFG   volatile.Register32 // 0x2E8
	FUNC101_IN_SEL_CFG   volatile.Register32 // 0x2EC
	FUNC102_IN_SEL_CFG   volatile.Register32 // 0x2F0
	FUNC103_IN_SEL_CFG   volatile.Register32 // 0x2F4
	FUNC104_IN_SEL_CFG   volatile.Register32 // 0x2F8
	FUNC105_IN_SEL_CFG   volatile.Register32 // 0x2FC
	FUNC106_IN_SEL_CFG   volatile.Register32 // 0x300
	FUNC107_IN_SEL_CFG   volatile.Register32 // 0x304
	FUNC108_IN_SEL_CFG   volatile.Register32 // 0x308
	FUNC109_IN_SEL_CFG   volatile.Register32 // 0x30C
	FUNC110_IN_SEL_CFG   volatile.Register32 // 0x310
	FUNC111_IN_SEL_CFG   volatile.Register32 // 0x314
	FUNC112_IN_SEL_CFG   volatile.Register32 // 0x318
	FUNC113_IN_SEL_CFG   volatile.Register32 // 0x31C
	FUNC114_IN_SEL_CFG   volatile.Register32 // 0x320
	FUNC115_IN_SEL_CFG   volatile.Register32 // 0x324
	FUNC116_IN_SEL_CFG   volatile.Register32 // 0x328
	FUNC117_IN_SEL_CFG   volatile.Register32 // 0x32C
	FUNC118_IN_SEL_CFG   volatile.Register32 // 0x330
	FUNC119_IN_SEL_CFG   volatile.Register32 // 0x334
	FUNC120_IN_SEL_CFG   volatile.Register32 // 0x338
	FUNC121_IN_SEL_CFG   volatile.Register32 // 0x33C
	FUNC122_IN_SEL_CFG   volatile.Register32 // 0x340
	FUNC123_IN_SEL_CFG   volatile.Register32 // 0x344
	FUNC124_IN_SEL_CFG   volatile.Register32 // 0x348
	FUNC125_IN_SEL_CFG   volatile.Register32 // 0x34C
	FUNC126_IN_SEL_CFG   volatile.Register32 // 0x350
	FUNC127_IN_SEL_CFG   volatile.Register32 // 0x354
	FUNC128_IN_SEL_CFG   volatile.Register32 // 0x358
	FUNC129_IN_SEL_CFG   volatile.Register32 // 0x35C
	FUNC130_IN_SEL_CFG   volatile.Register32 // 0x360
	FUNC131_IN_SEL_CFG   volatile.Register32 // 0x364
	FUNC132_IN_SEL_CFG   volatile.Register32 // 0x368
	FUNC133_IN_SEL_CFG   volatile.Register32 // 0x36C
	FUNC134_IN_SEL_CFG   volatile.Register32 // 0x370
	FUNC135_IN_SEL_CFG   volatile.Register32 // 0x374
	FUNC136_IN_SEL_CFG   volatile.Register32 // 0x378
	FUNC137_IN_SEL_CFG   volatile.Register32 // 0x37C
	FUNC138_IN_SEL_CFG   volatile.Register32 // 0x380
	FUNC139_IN_SEL_CFG   volatile.Register32 // 0x384
	FUNC140_IN_SEL_CFG   volatile.Register32 // 0x388
	FUNC141_IN_SEL_CFG   volatile.Register32 // 0x38C
	FUNC142_IN_SEL_CFG   volatile.Register32 // 0x390
	FUNC143_IN_SEL_CFG   volatile.Register32 // 0x394
	FUNC144_IN_SEL_CFG   volatile.Register32 // 0x398
	FUNC145_IN_SEL_CFG   volatile.Register32 // 0x39C
	FUNC146_IN_SEL_CFG   volatile.Register32 // 0x3A0
	FUNC147_IN_SEL_CFG   volatile.Register32 // 0x3A4
	FUNC148_IN_SEL_CFG   volatile.Register32 // 0x3A8
	FUNC149_IN_SEL_CFG   volatile.Register32 // 0x3AC
	FUNC150_IN_SEL_CFG   volatile.Register32 // 0x3B0
	FUNC151_IN_SEL_CFG   volatile.Register32 // 0x3B4
	FUNC152_IN_SEL_CFG   volatile.Register32 // 0x3B8
	FUNC153_IN_SEL_CFG   volatile.Register32 // 0x3BC
	FUNC154_IN_SEL_CFG   volatile.Register32 // 0x3C0
	FUNC155_IN_SEL_CFG   volatile.Register32 // 0x3C4
	FUNC156_IN_SEL_CFG   volatile.Register32 // 0x3C8
	FUNC157_IN_SEL_CFG   volatile.Register32 // 0x3CC
	FUNC158_IN_SEL_CFG   volatile.Register32 // 0x3D0
	FUNC159_IN_SEL_CFG   volatile.Register32 // 0x3D4
	FUNC160_IN_SEL_CFG   volatile.Register32 // 0x3D8
	FUNC161_IN_SEL_CFG   volatile.Register32 // 0x3DC
	FUNC162_IN_SEL_CFG   volatile.Register32 // 0x3E0
	FUNC163_IN_SEL_CFG   volatile.Register32 // 0x3E4
	FUNC164_IN_SEL_CFG   volatile.Register32 // 0x3E8
	FUNC165_IN_SEL_CFG   volatile.Register32 // 0x3EC
	FUNC166_IN_SEL_CFG   volatile.Register32 // 0x3F0
	FUNC167_IN_SEL_CFG   volatile.Register32 // 0x3F4
	FUNC168_IN_SEL_CFG   volatile.Register32 // 0x3F8
	FUNC169_IN_SEL_CFG   volatile.Register32 // 0x3FC
	FUNC170_IN_SEL_CFG   volatile.Register32 // 0x400
	FUNC171_IN_SEL_CFG   volatile.Register32 // 0x404
	FUNC172_IN_SEL_CFG   volatile.Register32 // 0x408
	FUNC173_IN_SEL_CFG   volatile.Register32 // 0x40C
	FUNC174_IN_SEL_CFG   volatile.Register32 // 0x410
	FUNC175_IN_SEL_CFG   volatile.Register32 // 0x414
	FUNC176_IN_SEL_CFG   volatile.Register32 // 0x418
	FUNC177_IN_SEL_CFG   volatile.Register32 // 0x41C
	FUNC178_IN_SEL_CFG   volatile.Register32 // 0x420
	FUNC179_IN_SEL_CFG   volatile.Register32 // 0x424
	FUNC180_IN_SEL_CFG   volatile.Register32 // 0x428
	FUNC181_IN_SEL_CFG   volatile.Register32 // 0x42C
	FUNC182_IN_SEL_CFG   volatile.Register32 // 0x430
	FUNC183_IN_SEL_CFG   volatile.Register32 // 0x434
	FUNC184_IN_SEL_CFG   volatile.Register32 // 0x438
	FUNC185_IN_SEL_CFG   volatile.Register32 // 0x43C
	FUNC186_IN_SEL_CFG   volatile.Register32 // 0x440
	FUNC187_IN_SEL_CFG   volatile.Register32 // 0x444
	FUNC188_IN_SEL_CFG   volatile.Register32 // 0x448
	FUNC189_IN_SEL_CFG   volatile.Register32 // 0x44C
	FUNC190_IN_SEL_CFG   volatile.Register32 // 0x450
	FUNC191_IN_SEL_CFG   volatile.Register32 // 0x454
	FUNC192_IN_SEL_CFG   volatile.Register32 // 0x458
	FUNC193_IN_SEL_CFG   volatile.Register32 // 0x45C
	FUNC194_IN_SEL_CFG   volatile.Register32 // 0x460
	FUNC195_IN_SEL_CFG   volatile.Register32 // 0x464
	FUNC196_IN_SEL_CFG   volatile.Register32 // 0x468
	FUNC197_IN_SEL_CFG   volatile.Register32 // 0x46C
	FUNC198_IN_SEL_CFG   volatile.Register32 // 0x470
	FUNC199_IN_SEL_CFG   volatile.Register32 // 0x474
	FUNC200_IN_SEL_CFG   volatile.Register32 // 0x478
	FUNC201_IN_SEL_CFG   volatile.Register32 // 0x47C
	FUNC202_IN_SEL_CFG   volatile.Register32 // 0x480
	FUNC203_IN_SEL_CFG   volatile.Register32 // 0x484
	FUNC204_IN_SEL_CFG   volatile.Register32 // 0x488
	FUNC205_IN_SEL_CFG   volatile.Register32 // 0x48C
	FUNC206_IN_SEL_CFG   volatile.Register32 // 0x490
	FUNC207_IN_SEL_CFG   volatile.Register32 // 0x494
	FUNC208_IN_SEL_CFG   volatile.Register32 // 0x498
	FUNC209_IN_SEL_CFG   volatile.Register32 // 0x49C
	FUNC210_IN_SEL_CFG   volatile.Register32 // 0x4A0
	FUNC211_IN_SEL_CFG   volatile.Register32 // 0x4A4
	FUNC212_IN_SEL_CFG   volatile.Register32 // 0x4A8
	FUNC213_IN_SEL_CFG   volatile.Register32 // 0x4AC
	FUNC214_IN_SEL_CFG   volatile.Register32 // 0x4B0
	FUNC215_IN_SEL_CFG   volatile.Register32 // 0x4B4
	FUNC216_IN_SEL_CFG   volatile.Register32 // 0x4B8
	FUNC217_IN_SEL_CFG   volatile.Register32 // 0x4BC
	FUNC218_IN_SEL_CFG   volatile.Register32 // 0x4C0
	FUNC219_IN_SEL_CFG   volatile.Register32 // 0x4C4
	FUNC220_IN_SEL_CFG   volatile.Register32 // 0x4C8
	FUNC221_IN_SEL_CFG   volatile.Register32 // 0x4CC
	FUNC222_IN_SEL_CFG   volatile.Register32 // 0x4D0
	FUNC223_IN_SEL_CFG   volatile.Register32 // 0x4D4
	FUNC224_IN_SEL_CFG   volatile.Register32 // 0x4D8
	FUNC225_IN_SEL_CFG   volatile.Register32 // 0x4DC
	FUNC226_IN_SEL_CFG   volatile.Register32 // 0x4E0
	FUNC227_IN_SEL_CFG   volatile.Register32 // 0x4E4
	FUNC228_IN_SEL_CFG   volatile.Register32 // 0x4E8
	FUNC229_IN_SEL_CFG   volatile.Register32 // 0x4EC
	FUNC230_IN_SEL_CFG   volatile.Register32 // 0x4F0
	FUNC231_IN_SEL_CFG   volatile.Register32 // 0x4F4
	FUNC232_IN_SEL_CFG   volatile.Register32 // 0x4F8
	FUNC233_IN_SEL_CFG   volatile.Register32 // 0x4FC
	FUNC234_IN_SEL_CFG   volatile.Register32 // 0x500
	FUNC235_IN_SEL_CFG   volatile.Register32 // 0x504
	FUNC236_IN_SEL_CFG   volatile.Register32 // 0x508
	FUNC237_IN_SEL_CFG   volatile.Register32 // 0x50C
	FUNC238_IN_SEL_CFG   volatile.Register32 // 0x510
	FUNC239_IN_SEL_CFG   volatile.Register32 // 0x514
	FUNC240_IN_SEL_CFG   volatile.Register32 // 0x518
	FUNC241_IN_SEL_CFG   volatile.Register32 // 0x51C
	FUNC242_IN_SEL_CFG   volatile.Register32 // 0x520
	FUNC243_IN_SEL_CFG   volatile.Register32 // 0x524
	FUNC244_IN_SEL_CFG   volatile.Register32 // 0x528
	FUNC245_IN_SEL_CFG   volatile.Register32 // 0x52C
	FUNC246_IN_SEL_CFG   volatile.Register32 // 0x530
	FUNC247_IN_SEL_CFG   volatile.Register32 // 0x534
	FUNC248_IN_SEL_CFG   volatile.Register32 // 0x538
	FUNC249_IN_SEL_CFG   volatile.Register32 // 0x53C
	FUNC250_IN_SEL_CFG   volatile.Register32 // 0x540
	FUNC251_IN_SEL_CFG   volatile.Register32 // 0x544
	FUNC252_IN_SEL_CFG   volatile.Register32 // 0x548
	FUNC253_IN_SEL_CFG   volatile.Register32 // 0x54C
	FUNC254_IN_SEL_CFG   volatile.Register32 // 0x550
	_                    [4]byte
	FUNC0_OUT_SEL_CFG    volatile.Register32 // 0x558
	FUNC1_OUT_SEL_CFG    volatile.Register32 // 0x55C
	FUNC2_OUT_SEL_CFG    volatile.Register32 // 0x560
	FUNC3_OUT_SEL_CFG    volatile.Register32 // 0x564
	FUNC4_OUT_SEL_CFG    volatile.Register32 // 0x568
	FUNC5_OUT_SEL_CFG    volatile.Register32 // 0x56C
	FUNC6_OUT_SEL_CFG    volatile.Register32 // 0x570
	FUNC7_OUT_SEL_CFG    volatile.Register32 // 0x574
	FUNC8_OUT_SEL_CFG    volatile.Register32 // 0x578
	FUNC9_OUT_SEL_CFG    volatile.Register32 // 0x57C
	FUNC10_OUT_SEL_CFG   volatile.Register32 // 0x580
	FUNC11_OUT_SEL_CFG   volatile.Register32 // 0x584
	FUNC12_OUT_SEL_CFG   volatile.Register32 // 0x588
	FUNC13_OUT_SEL_CFG   volatile.Register32 // 0x58C
	FUNC14_OUT_SEL_CFG   volatile.Register32 // 0x590
	FUNC15_OUT_SEL_CFG   volatile.Register32 // 0x594
	FUNC16_OUT_SEL_CFG   volatile.Register32 // 0x598
	FUNC17_OUT_SEL_CFG   volatile.Register32 // 0x59C
	FUNC18_OUT_SEL_CFG   volatile.Register32 // 0x5A0
	FUNC19_OUT_SEL_CFG   volatile.Register32 // 0x5A4
	FUNC20_OUT_SEL_CFG   volatile.Register32 // 0x5A8
	FUNC21_OUT_SEL_CFG   volatile.Register32 // 0x5AC
	FUNC22_OUT_SEL_CFG   volatile.Register32 // 0x5B0
	FUNC23_OUT_SEL_CFG   volatile.Register32 // 0x5B4
	FUNC24_OUT_SEL_CFG   volatile.Register32 // 0x5B8
	FUNC25_OUT_SEL_CFG   volatile.Register32 // 0x5BC
	FUNC26_OUT_SEL_CFG   volatile.Register32 // 0x5C0
	FUNC27_OUT_SEL_CFG   volatile.Register32 // 0x5C4
	FUNC28_OUT_SEL_CFG   volatile.Register32 // 0x5C8
	FUNC29_OUT_SEL_CFG   volatile.Register32 // 0x5CC
	FUNC30_OUT_SEL_CFG   volatile.Register32 // 0x5D0
	FUNC31_OUT_SEL_CFG   volatile.Register32 // 0x5D4
	FUNC32_OUT_SEL_CFG   volatile.Register32 // 0x5D8
	FUNC33_OUT_SEL_CFG   volatile.Register32 // 0x5DC
	FUNC34_OUT_SEL_CFG   volatile.Register32 // 0x5E0
	FUNC35_OUT_SEL_CFG   volatile.Register32 // 0x5E4
	FUNC36_OUT_SEL_CFG   volatile.Register32 // 0x5E8
	FUNC37_OUT_SEL_CFG   volatile.Register32 // 0x5EC
	FUNC38_OUT_SEL_CFG   volatile.Register32 // 0x5F0
	FUNC39_OUT_SEL_CFG   volatile.Register32 // 0x5F4
	FUNC40_OUT_SEL_CFG   volatile.Register32 // 0x5F8
	FUNC41_OUT_SEL_CFG   volatile.Register32 // 0x5FC
	FUNC42_OUT_SEL_CFG   volatile.Register32 // 0x600
	FUNC43_OUT_SEL_CFG   volatile.Register32 // 0x604
	FUNC44_OUT_SEL_CFG   volatile.Register32 // 0x608
	FUNC45_OUT_SEL_CFG   volatile.Register32 // 0x60C
	FUNC46_OUT_SEL_CFG   volatile.Register32 // 0x610
	FUNC47_OUT_SEL_CFG   volatile.Register32 // 0x614
	FUNC48_OUT_SEL_CFG   volatile.Register32 // 0x618
	FUNC49_OUT_SEL_CFG   volatile.Register32 // 0x61C
	FUNC50_OUT_SEL_CFG   volatile.Register32 // 0x620
	FUNC51_OUT_SEL_CFG   volatile.Register32 // 0x624
	FUNC52_OUT_SEL_CFG   volatile.Register32 // 0x628
	FUNC53_OUT_SEL_CFG   volatile.Register32 // 0x62C
	FUNC54_OUT_SEL_CFG   volatile.Register32 // 0x630
	FUNC55_OUT_SEL_CFG   volatile.Register32 // 0x634
	FUNC56_OUT_SEL_CFG   volatile.Register32 // 0x638
	INTR_2               volatile.Register32 // 0x63C
	INTR1_2              volatile.Register32 // 0x640
	INTR_3               volatile.Register32 // 0x644
	INTR1_3              volatile.Register32 // 0x648
	CLOCK_GATE           volatile.Register32 // 0x64C
	_                    [176]byte
	INT_RAW              volatile.Register32 // 0x700
	INT_ST               volatile.Register32 // 0x704
	INT_ENA              volatile.Register32 // 0x708
	INT_CLR              volatile.Register32 // 0x70C
	ZERO_DET0_FILTER_CNT volatile.Register32 // 0x710
	ZERO_DET1_FILTER_CNT volatile.Register32 // 0x714
	SEND_SEQ             volatile.Register32 // 0x718
	RECIVE_SEQ           volatile.Register32 // 0x71C
	BISTIN_SEL           volatile.Register32 // 0x720
	BIST_CTRL            volatile.Register32 // 0x724
	_                    [212]byte
	DATE                 volatile.Register32 // 0x7FC
}

// GPIO.BT_SELECT: GPIO bit select register
func (o *GPIO_Type) SetBT_SELECT(value uint32) {
	volatile.StoreUint32(&o.BT_SELECT.Reg, value)
}
func (o *GPIO_Type) GetBT_SELECT() uint32 {
	return volatile.LoadUint32(&o.BT_SELECT.Reg)
}

// GPIO.OUT: GPIO output register for GPIO0-31
func (o *GPIO_Type) SetOUT(value uint32) {
	volatile.StoreUint32(&o.OUT.Reg, value)
}
func (o *GPIO_Type) GetOUT() uint32 {
	return volatile.LoadUint32(&o.OUT.Reg)
}

// GPIO.OUT_W1TS: GPIO output set register for GPIO0-31
func (o *GPIO_Type) SetOUT_W1TS(value uint32) {
	volatile.StoreUint32(&o.OUT_W1TS.Reg, value)
}
func (o *GPIO_Type) GetOUT_W1TS() uint32 {
	return volatile.LoadUint32(&o.OUT_W1TS.Reg)
}

// GPIO.OUT_W1TC: GPIO output clear register for GPIO0-31
func (o *GPIO_Type) SetOUT_W1TC(value uint32) {
	volatile.StoreUint32(&o.OUT_W1TC.Reg, value)
}
func (o *GPIO_Type) GetOUT_W1TC() uint32 {
	return volatile.LoadUint32(&o.OUT_W1TC.Reg)
}

// GPIO.OUT1: GPIO output register for GPIO32-56
func (o *GPIO_Type) SetOUT1_DATA_ORIG(value uint32) {
	volatile.StoreUint32(&o.OUT1.Reg, volatile.LoadUint32(&o.OUT1.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetOUT1_DATA_ORIG() uint32 {
	return volatile.LoadUint32(&o.OUT1.Reg) & 0x1ffffff
}

// GPIO.OUT1_W1TS: GPIO output set register for GPIO32-56
func (o *GPIO_Type) SetOUT1_W1TS(value uint32) {
	volatile.StoreUint32(&o.OUT1_W1TS.Reg, volatile.LoadUint32(&o.OUT1_W1TS.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetOUT1_W1TS() uint32 {
	return volatile.LoadUint32(&o.OUT1_W1TS.Reg) & 0x1ffffff
}

// GPIO.OUT1_W1TC: GPIO output clear register for GPIO32-56
func (o *GPIO_Type) SetOUT1_W1TC(value uint32) {
	volatile.StoreUint32(&o.OUT1_W1TC.Reg, volatile.LoadUint32(&o.OUT1_W1TC.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetOUT1_W1TC() uint32 {
	return volatile.LoadUint32(&o.OUT1_W1TC.Reg) & 0x1ffffff
}

// GPIO.ENABLE: GPIO output enable register for GPIO0-31
func (o *GPIO_Type) SetENABLE(value uint32) {
	volatile.StoreUint32(&o.ENABLE.Reg, value)
}
func (o *GPIO_Type) GetENABLE() uint32 {
	return volatile.LoadUint32(&o.ENABLE.Reg)
}

// GPIO.ENABLE_W1TS: GPIO output enable set register for GPIO0-31
func (o *GPIO_Type) SetENABLE_W1TS(value uint32) {
	volatile.StoreUint32(&o.ENABLE_W1TS.Reg, value)
}
func (o *GPIO_Type) GetENABLE_W1TS() uint32 {
	return volatile.LoadUint32(&o.ENABLE_W1TS.Reg)
}

// GPIO.ENABLE_W1TC: GPIO output enable clear register for GPIO0-31
func (o *GPIO_Type) SetENABLE_W1TC(value uint32) {
	volatile.StoreUint32(&o.ENABLE_W1TC.Reg, value)
}
func (o *GPIO_Type) GetENABLE_W1TC() uint32 {
	return volatile.LoadUint32(&o.ENABLE_W1TC.Reg)
}

// GPIO.ENABLE1: GPIO output enable register for GPIO32-56
func (o *GPIO_Type) SetENABLE1_DATA(value uint32) {
	volatile.StoreUint32(&o.ENABLE1.Reg, volatile.LoadUint32(&o.ENABLE1.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetENABLE1_DATA() uint32 {
	return volatile.LoadUint32(&o.ENABLE1.Reg) & 0x1ffffff
}

// GPIO.ENABLE1_W1TS: GPIO output enable set register for GPIO32-56
func (o *GPIO_Type) SetENABLE1_W1TS(value uint32) {
	volatile.StoreUint32(&o.ENABLE1_W1TS.Reg, volatile.LoadUint32(&o.ENABLE1_W1TS.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetENABLE1_W1TS() uint32 {
	return volatile.LoadUint32(&o.ENABLE1_W1TS.Reg) & 0x1ffffff
}

// GPIO.ENABLE1_W1TC: GPIO output enable clear register for GPIO32-56
func (o *GPIO_Type) SetENABLE1_W1TC(value uint32) {
	volatile.StoreUint32(&o.ENABLE1_W1TC.Reg, volatile.LoadUint32(&o.ENABLE1_W1TC.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetENABLE1_W1TC() uint32 {
	return volatile.LoadUint32(&o.ENABLE1_W1TC.Reg) & 0x1ffffff
}

// GPIO.STRAP: pad strapping register
func (o *GPIO_Type) SetSTRAP_STRAPPING(value uint32) {
	volatile.StoreUint32(&o.STRAP.Reg, volatile.LoadUint32(&o.STRAP.Reg)&^(0xffff)|value)
}
func (o *GPIO_Type) GetSTRAP_STRAPPING() uint32 {
	return volatile.LoadUint32(&o.STRAP.Reg) & 0xffff
}

// GPIO.IN: GPIO input register for GPIO0-31
func (o *GPIO_Type) SetIN(value uint32) {
	volatile.StoreUint32(&o.IN.Reg, value)
}
func (o *GPIO_Type) GetIN() uint32 {
	return volatile.LoadUint32(&o.IN.Reg)
}

// GPIO.IN1: GPIO input register for GPIO32-56
func (o *GPIO_Type) SetIN1_DATA_NEXT(value uint32) {
	volatile.StoreUint32(&o.IN1.Reg, volatile.LoadUint32(&o.IN1.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetIN1_DATA_NEXT() uint32 {
	return volatile.LoadUint32(&o.IN1.Reg) & 0x1ffffff
}

// GPIO.STATUS: GPIO interrupt status register for GPIO0-31
func (o *GPIO_Type) SetSTATUS(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, value)
}
func (o *GPIO_Type) GetSTATUS() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg)
}

// GPIO.STATUS_W1TS: GPIO interrupt status set register for GPIO0-31
func (o *GPIO_Type) SetSTATUS_W1TS(value uint32) {
	volatile.StoreUint32(&o.STATUS_W1TS.Reg, value)
}
func (o *GPIO_Type) GetSTATUS_W1TS() uint32 {
	return volatile.LoadUint32(&o.STATUS_W1TS.Reg)
}

// GPIO.STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31
func (o *GPIO_Type) SetSTATUS_W1TC(value uint32) {
	volatile.StoreUint32(&o.STATUS_W1TC.Reg, value)
}
func (o *GPIO_Type) GetSTATUS_W1TC() uint32 {
	return volatile.LoadUint32(&o.STATUS_W1TC.Reg)
}

// GPIO.STATUS1: GPIO interrupt status register for GPIO32-56
func (o *GPIO_Type) SetSTATUS1_INTERRUPT(value uint32) {
	volatile.StoreUint32(&o.STATUS1.Reg, volatile.LoadUint32(&o.STATUS1.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetSTATUS1_INTERRUPT() uint32 {
	return volatile.LoadUint32(&o.STATUS1.Reg) & 0x1ffffff
}

// GPIO.STATUS1_W1TS: GPIO interrupt status set register for GPIO32-56
func (o *GPIO_Type) SetSTATUS1_W1TS(value uint32) {
	volatile.StoreUint32(&o.STATUS1_W1TS.Reg, volatile.LoadUint32(&o.STATUS1_W1TS.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetSTATUS1_W1TS() uint32 {
	return volatile.LoadUint32(&o.STATUS1_W1TS.Reg) & 0x1ffffff
}

// GPIO.STATUS1_W1TC: GPIO interrupt status clear register for GPIO32-56
func (o *GPIO_Type) SetSTATUS1_W1TC(value uint32) {
	volatile.StoreUint32(&o.STATUS1_W1TC.Reg, volatile.LoadUint32(&o.STATUS1_W1TC.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetSTATUS1_W1TC() uint32 {
	return volatile.LoadUint32(&o.STATUS1_W1TC.Reg) & 0x1ffffff
}

// GPIO.INTR_0: GPIO interrupt 0 status register for GPIO0-31
func (o *GPIO_Type) SetINTR_0(value uint32) {
	volatile.StoreUint32(&o.INTR_0.Reg, value)
}
func (o *GPIO_Type) GetINTR_0() uint32 {
	return volatile.LoadUint32(&o.INTR_0.Reg)
}

// GPIO.INTR1_0: GPIO interrupt 0 status register for GPIO32-56
func (o *GPIO_Type) SetINTR1_0_INT1_0(value uint32) {
	volatile.StoreUint32(&o.INTR1_0.Reg, volatile.LoadUint32(&o.INTR1_0.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetINTR1_0_INT1_0() uint32 {
	return volatile.LoadUint32(&o.INTR1_0.Reg) & 0x1ffffff
}

// GPIO.INTR_1: GPIO interrupt 1 status register for GPIO0-31
func (o *GPIO_Type) SetINTR_1(value uint32) {
	volatile.StoreUint32(&o.INTR_1.Reg, value)
}
func (o *GPIO_Type) GetINTR_1() uint32 {
	return volatile.LoadUint32(&o.INTR_1.Reg)
}

// GPIO.INTR1_1: GPIO interrupt 1 status register for GPIO32-56
func (o *GPIO_Type) SetINTR1_1_INT1_1(value uint32) {
	volatile.StoreUint32(&o.INTR1_1.Reg, volatile.LoadUint32(&o.INTR1_1.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetINTR1_1_INT1_1() uint32 {
	return volatile.LoadUint32(&o.INTR1_1.Reg) & 0x1ffffff
}

// GPIO.STATUS_NEXT: GPIO interrupt source register for GPIO0-31
func (o *GPIO_Type) SetSTATUS_NEXT(value uint32) {
	volatile.StoreUint32(&o.STATUS_NEXT.Reg, value)
}
func (o *GPIO_Type) GetSTATUS_NEXT() uint32 {
	return volatile.LoadUint32(&o.STATUS_NEXT.Reg)
}

// GPIO.STATUS_NEXT1: GPIO interrupt source register for GPIO32-56
func (o *GPIO_Type) SetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1(value uint32) {
	volatile.StoreUint32(&o.STATUS_NEXT1.Reg, volatile.LoadUint32(&o.STATUS_NEXT1.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetSTATUS_NEXT1_STATUS_INTERRUPT_NEXT1() uint32 {
	return volatile.LoadUint32(&o.STATUS_NEXT1.Reg) & 0x1ffffff
}

// GPIO.PIN0: GPIO pin configuration register
func (o *GPIO_Type) SetPIN0_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN0_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN0.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN0_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN0_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN0_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN0_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN0_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN0_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN0_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN0_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN0_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN0_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x3e000) >> 13
}

// GPIO.PIN1: GPIO pin configuration register
func (o *GPIO_Type) SetPIN1_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN1_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN1.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN1_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN1_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN1_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN1_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN1_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN1_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN1_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN1_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN1_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN1_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x3e000) >> 13
}

// GPIO.PIN2: GPIO pin configuration register
func (o *GPIO_Type) SetPIN2_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN2_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN2.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN2_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN2_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN2_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN2_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN2_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN2_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN2_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN2_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN2_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN2_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x3e000) >> 13
}

// GPIO.PIN3: GPIO pin configuration register
func (o *GPIO_Type) SetPIN3_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN3_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN3.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN3_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN3_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN3_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN3_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN3_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN3_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN3_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN3_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN3_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN3_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x3e000) >> 13
}

// GPIO.PIN4: GPIO pin configuration register
func (o *GPIO_Type) SetPIN4_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN4_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN4.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN4_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN4_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN4_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN4_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN4_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN4_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN4_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN4_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN4_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN4_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x3e000) >> 13
}

// GPIO.PIN5: GPIO pin configuration register
func (o *GPIO_Type) SetPIN5_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN5_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN5.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN5_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN5_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN5_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN5_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN5_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN5_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN5_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN5_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN5_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN5_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN5_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x3e000) >> 13
}

// GPIO.PIN6: GPIO pin configuration register
func (o *GPIO_Type) SetPIN6_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN6_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN6.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN6_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN6_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN6_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN6_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN6_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN6_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN6_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN6_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN6_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN6_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN6_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN6_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x3e000) >> 13
}

// GPIO.PIN7: GPIO pin configuration register
func (o *GPIO_Type) SetPIN7_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN7_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN7.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN7_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN7_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN7_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN7_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN7_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN7_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN7_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN7_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN7_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN7_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN7_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN7_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x3e000) >> 13
}

// GPIO.PIN8: GPIO pin configuration register
func (o *GPIO_Type) SetPIN8_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN8_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN8.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN8_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN8_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN8_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN8_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN8_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN8_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN8_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN8_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN8_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN8_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN8_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN8_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x3e000) >> 13
}

// GPIO.PIN9: GPIO pin configuration register
func (o *GPIO_Type) SetPIN9_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN9_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN9.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN9_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN9_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN9_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN9_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN9_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN9_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN9_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN9_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN9_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN9_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN9_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN9_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x3e000) >> 13
}

// GPIO.PIN10: GPIO pin configuration register
func (o *GPIO_Type) SetPIN10_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN10_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN10.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN10_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN10_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN10_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN10_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN10_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN10_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN10_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN10_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN10_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN10_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN10_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN10_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x3e000) >> 13
}

// GPIO.PIN11: GPIO pin configuration register
func (o *GPIO_Type) SetPIN11_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN11_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN11.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN11_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN11_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN11_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN11_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN11_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN11_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN11_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN11_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN11_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN11_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN11_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN11_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x3e000) >> 13
}

// GPIO.PIN12: GPIO pin configuration register
func (o *GPIO_Type) SetPIN12_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN12_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN12.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN12_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN12_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN12_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN12_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN12_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN12_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN12_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN12_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN12_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN12_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN12_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN12_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x3e000) >> 13
}

// GPIO.PIN13: GPIO pin configuration register
func (o *GPIO_Type) SetPIN13_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN13_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN13.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN13_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN13_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN13_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN13_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN13_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN13_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN13_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN13_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN13_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN13_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN13_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN13_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x3e000) >> 13
}

// GPIO.PIN14: GPIO pin configuration register
func (o *GPIO_Type) SetPIN14_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN14_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN14.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN14_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN14_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN14_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN14_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN14_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN14_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN14_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN14_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN14_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN14_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN14_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN14_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x3e000) >> 13
}

// GPIO.PIN15: GPIO pin configuration register
func (o *GPIO_Type) SetPIN15_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN15_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN15.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN15_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN15_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN15_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN15_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN15_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN15_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN15_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN15_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN15_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN15_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN15_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN15_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x3e000) >> 13
}

// GPIO.PIN16: GPIO pin configuration register
func (o *GPIO_Type) SetPIN16_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN16_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN16.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN16_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN16_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN16.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN16_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN16_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN16.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN16_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN16_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN16.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN16_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN16_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN16.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN16_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN16_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN16.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN16_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN16.Reg, volatile.LoadUint32(&o.PIN16.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN16_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN16.Reg) & 0x3e000) >> 13
}

// GPIO.PIN17: GPIO pin configuration register
func (o *GPIO_Type) SetPIN17_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN17_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN17.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN17_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN17_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN17.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN17_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN17_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN17.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN17_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN17_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN17.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN17_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN17_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN17.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN17_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN17_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN17.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN17_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN17.Reg, volatile.LoadUint32(&o.PIN17.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN17_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN17.Reg) & 0x3e000) >> 13
}

// GPIO.PIN18: GPIO pin configuration register
func (o *GPIO_Type) SetPIN18_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN18_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN18.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN18_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN18_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN18.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN18_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN18_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN18.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN18_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN18_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN18.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN18_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN18_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN18.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN18_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN18_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN18.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN18_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN18.Reg, volatile.LoadUint32(&o.PIN18.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN18_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN18.Reg) & 0x3e000) >> 13
}

// GPIO.PIN19: GPIO pin configuration register
func (o *GPIO_Type) SetPIN19_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN19_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN19.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN19_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN19_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN19.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN19_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN19_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN19.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN19_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN19_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN19.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN19_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN19_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN19.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN19_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN19_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN19.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN19_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN19.Reg, volatile.LoadUint32(&o.PIN19.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN19_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN19.Reg) & 0x3e000) >> 13
}

// GPIO.PIN20: GPIO pin configuration register
func (o *GPIO_Type) SetPIN20_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN20_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN20.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN20_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN20_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN20.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN20_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN20_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN20.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN20_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN20_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN20.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN20_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN20_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN20.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN20_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN20_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN20.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN20_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN20.Reg, volatile.LoadUint32(&o.PIN20.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN20_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN20.Reg) & 0x3e000) >> 13
}

// GPIO.PIN21: GPIO pin configuration register
func (o *GPIO_Type) SetPIN21_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN21_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN21.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN21_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN21_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN21.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN21_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN21_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN21.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN21_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN21_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN21.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN21_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN21_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN21.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN21_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN21_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN21.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN21_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN21.Reg, volatile.LoadUint32(&o.PIN21.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN21_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN21.Reg) & 0x3e000) >> 13
}

// GPIO.PIN22: GPIO pin configuration register
func (o *GPIO_Type) SetPIN22_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN22_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN22.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN22_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN22_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN22.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN22_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN22_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN22.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN22_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN22_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN22.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN22_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN22_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN22.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN22_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN22_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN22.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN22_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN22.Reg, volatile.LoadUint32(&o.PIN22.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN22_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN22.Reg) & 0x3e000) >> 13
}

// GPIO.PIN23: GPIO pin configuration register
func (o *GPIO_Type) SetPIN23_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN23_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN23.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN23_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN23_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN23.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN23_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN23_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN23.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN23_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN23_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN23.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN23_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN23_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN23.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN23_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN23_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN23.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN23_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN23.Reg, volatile.LoadUint32(&o.PIN23.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN23_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN23.Reg) & 0x3e000) >> 13
}

// GPIO.PIN24: GPIO pin configuration register
func (o *GPIO_Type) SetPIN24_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN24_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN24.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN24_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN24_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN24.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN24_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN24_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN24.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN24_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN24_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN24.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN24_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN24_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN24.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN24_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN24_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN24.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN24_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN24.Reg, volatile.LoadUint32(&o.PIN24.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN24_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN24.Reg) & 0x3e000) >> 13
}

// GPIO.PIN25: GPIO pin configuration register
func (o *GPIO_Type) SetPIN25_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN25_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN25.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN25_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN25_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN25.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN25_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN25_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN25.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN25_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN25_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN25.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN25_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN25_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN25.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN25_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN25_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN25.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN25_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN25.Reg, volatile.LoadUint32(&o.PIN25.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN25_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN25.Reg) & 0x3e000) >> 13
}

// GPIO.PIN26: GPIO pin configuration register
func (o *GPIO_Type) SetPIN26_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN26_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN26.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN26_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN26_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN26.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN26_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN26_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN26.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN26_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN26_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN26.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN26_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN26_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN26.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN26_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN26_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN26.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN26_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN26.Reg, volatile.LoadUint32(&o.PIN26.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN26_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN26.Reg) & 0x3e000) >> 13
}

// GPIO.PIN27: GPIO pin configuration register
func (o *GPIO_Type) SetPIN27_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN27_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN27.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN27_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN27_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN27.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN27_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN27_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN27.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN27_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN27_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN27.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN27_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN27_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN27.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN27_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN27_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN27.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN27_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN27.Reg, volatile.LoadUint32(&o.PIN27.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN27_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN27.Reg) & 0x3e000) >> 13
}

// GPIO.PIN28: GPIO pin configuration register
func (o *GPIO_Type) SetPIN28_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN28_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN28.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN28_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN28_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN28.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN28_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN28_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN28.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN28_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN28_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN28.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN28_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN28_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN28.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN28_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN28_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN28.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN28_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN28.Reg, volatile.LoadUint32(&o.PIN28.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN28_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN28.Reg) & 0x3e000) >> 13
}

// GPIO.PIN29: GPIO pin configuration register
func (o *GPIO_Type) SetPIN29_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN29_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN29.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN29_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN29_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN29.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN29_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN29_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN29.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN29_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN29_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN29.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN29_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN29_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN29.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN29_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN29_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN29.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN29_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN29.Reg, volatile.LoadUint32(&o.PIN29.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN29_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN29.Reg) & 0x3e000) >> 13
}

// GPIO.PIN30: GPIO pin configuration register
func (o *GPIO_Type) SetPIN30_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN30_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN30.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN30_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN30_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN30.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN30_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN30_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN30.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN30_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN30_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN30.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN30_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN30_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN30.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN30_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN30_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN30.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN30_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN30.Reg, volatile.LoadUint32(&o.PIN30.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN30_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN30.Reg) & 0x3e000) >> 13
}

// GPIO.PIN31: GPIO pin configuration register
func (o *GPIO_Type) SetPIN31_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN31_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN31.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN31_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN31_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN31.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN31_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN31_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN31.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN31_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN31_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN31.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN31_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN31_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN31.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN31_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN31_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN31.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN31_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN31.Reg, volatile.LoadUint32(&o.PIN31.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN31_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN31.Reg) & 0x3e000) >> 13
}

// GPIO.PIN32: GPIO pin configuration register
func (o *GPIO_Type) SetPIN32_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN32_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN32.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN32_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN32_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN32.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN32_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN32_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN32.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN32_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN32_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN32.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN32_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN32_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN32.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN32_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN32_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN32.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN32_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN32.Reg, volatile.LoadUint32(&o.PIN32.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN32_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN32.Reg) & 0x3e000) >> 13
}

// GPIO.PIN33: GPIO pin configuration register
func (o *GPIO_Type) SetPIN33_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN33_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN33.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN33_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN33_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN33.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN33_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN33_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN33.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN33_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN33_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN33.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN33_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN33_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN33.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN33_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN33_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN33.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN33_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN33.Reg, volatile.LoadUint32(&o.PIN33.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN33_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN33.Reg) & 0x3e000) >> 13
}

// GPIO.PIN34: GPIO pin configuration register
func (o *GPIO_Type) SetPIN34_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN34_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN34.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN34_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN34_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN34.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN34_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN34_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN34.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN34_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN34_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN34.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN34_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN34_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN34.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN34_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN34_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN34.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN34_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN34.Reg, volatile.LoadUint32(&o.PIN34.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN34_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN34.Reg) & 0x3e000) >> 13
}

// GPIO.PIN35: GPIO pin configuration register
func (o *GPIO_Type) SetPIN35_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN35_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN35.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN35_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN35_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN35.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN35_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN35_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN35.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN35_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN35_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN35.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN35_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN35_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN35.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN35_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN35_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN35.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN35_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN35.Reg, volatile.LoadUint32(&o.PIN35.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN35_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN35.Reg) & 0x3e000) >> 13
}

// GPIO.PIN36: GPIO pin configuration register
func (o *GPIO_Type) SetPIN36_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN36_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN36.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN36_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN36_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN36.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN36_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN36_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN36.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN36_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN36_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN36.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN36_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN36_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN36.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN36_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN36_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN36.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN36_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN36.Reg, volatile.LoadUint32(&o.PIN36.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN36_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN36.Reg) & 0x3e000) >> 13
}

// GPIO.PIN37: GPIO pin configuration register
func (o *GPIO_Type) SetPIN37_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN37_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN37.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN37_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN37_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN37.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN37_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN37_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN37.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN37_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN37_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN37.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN37_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN37_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN37.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN37_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN37_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN37.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN37_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN37.Reg, volatile.LoadUint32(&o.PIN37.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN37_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN37.Reg) & 0x3e000) >> 13
}

// GPIO.PIN38: GPIO pin configuration register
func (o *GPIO_Type) SetPIN38_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN38_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN38.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN38_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN38_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN38.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN38_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN38_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN38.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN38_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN38_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN38.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN38_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN38_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN38.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN38_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN38_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN38.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN38_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN38.Reg, volatile.LoadUint32(&o.PIN38.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN38_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN38.Reg) & 0x3e000) >> 13
}

// GPIO.PIN39: GPIO pin configuration register
func (o *GPIO_Type) SetPIN39_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN39_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN39.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN39_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN39_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN39.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN39_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN39_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN39.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN39_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN39_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN39.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN39_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN39_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN39.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN39_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN39_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN39.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN39_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN39.Reg, volatile.LoadUint32(&o.PIN39.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN39_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN39.Reg) & 0x3e000) >> 13
}

// GPIO.PIN40: GPIO pin configuration register
func (o *GPIO_Type) SetPIN40_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN40_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN40.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN40_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN40_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN40.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN40_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN40_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN40.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN40_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN40_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN40.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN40_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN40_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN40.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN40_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN40_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN40.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN40_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN40.Reg, volatile.LoadUint32(&o.PIN40.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN40_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN40.Reg) & 0x3e000) >> 13
}

// GPIO.PIN41: GPIO pin configuration register
func (o *GPIO_Type) SetPIN41_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN41_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN41.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN41_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN41_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN41.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN41_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN41_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN41.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN41_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN41_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN41.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN41_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN41_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN41.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN41_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN41_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN41.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN41_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN41.Reg, volatile.LoadUint32(&o.PIN41.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN41_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN41.Reg) & 0x3e000) >> 13
}

// GPIO.PIN42: GPIO pin configuration register
func (o *GPIO_Type) SetPIN42_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN42_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN42.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN42_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN42_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN42.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN42_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN42_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN42.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN42_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN42_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN42.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN42_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN42_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN42.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN42_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN42_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN42.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN42_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN42.Reg, volatile.LoadUint32(&o.PIN42.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN42_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN42.Reg) & 0x3e000) >> 13
}

// GPIO.PIN43: GPIO pin configuration register
func (o *GPIO_Type) SetPIN43_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN43_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN43.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN43_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN43_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN43.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN43_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN43_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN43.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN43_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN43_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN43.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN43_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN43_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN43.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN43_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN43_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN43.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN43_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN43.Reg, volatile.LoadUint32(&o.PIN43.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN43_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN43.Reg) & 0x3e000) >> 13
}

// GPIO.PIN44: GPIO pin configuration register
func (o *GPIO_Type) SetPIN44_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN44_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN44.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN44_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN44_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN44.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN44_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN44_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN44.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN44_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN44_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN44.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN44_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN44_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN44.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN44_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN44_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN44.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN44_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN44.Reg, volatile.LoadUint32(&o.PIN44.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN44_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN44.Reg) & 0x3e000) >> 13
}

// GPIO.PIN45: GPIO pin configuration register
func (o *GPIO_Type) SetPIN45_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN45_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN45.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN45_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN45_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN45.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN45_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN45_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN45.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN45_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN45_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN45.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN45_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN45_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN45.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN45_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN45_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN45.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN45_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN45.Reg, volatile.LoadUint32(&o.PIN45.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN45_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN45.Reg) & 0x3e000) >> 13
}

// GPIO.PIN46: GPIO pin configuration register
func (o *GPIO_Type) SetPIN46_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN46_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN46.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN46_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN46_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN46.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN46_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN46_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN46.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN46_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN46_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN46.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN46_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN46_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN46.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN46_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN46_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN46.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN46_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN46.Reg, volatile.LoadUint32(&o.PIN46.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN46_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN46.Reg) & 0x3e000) >> 13
}

// GPIO.PIN47: GPIO pin configuration register
func (o *GPIO_Type) SetPIN47_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN47_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN47.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN47_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN47_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN47.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN47_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN47_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN47.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN47_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN47_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN47.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN47_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN47_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN47.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN47_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN47_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN47.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN47_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN47.Reg, volatile.LoadUint32(&o.PIN47.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN47_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN47.Reg) & 0x3e000) >> 13
}

// GPIO.PIN48: GPIO pin configuration register
func (o *GPIO_Type) SetPIN48_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN48_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN48.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN48_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN48_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN48.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN48_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN48_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN48.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN48_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN48_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN48.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN48_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN48_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN48.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN48_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN48_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN48.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN48_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN48.Reg, volatile.LoadUint32(&o.PIN48.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN48_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN48.Reg) & 0x3e000) >> 13
}

// GPIO.PIN49: GPIO pin configuration register
func (o *GPIO_Type) SetPIN49_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN49_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN49.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN49_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN49_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN49.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN49_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN49_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN49.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN49_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN49_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN49.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN49_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN49_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN49.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN49_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN49_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN49.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN49_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN49.Reg, volatile.LoadUint32(&o.PIN49.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN49_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN49.Reg) & 0x3e000) >> 13
}

// GPIO.PIN50: GPIO pin configuration register
func (o *GPIO_Type) SetPIN50_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN50_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN50.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN50_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN50_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN50.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN50_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN50_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN50.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN50_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN50_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN50.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN50_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN50_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN50.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN50_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN50_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN50.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN50_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN50.Reg, volatile.LoadUint32(&o.PIN50.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN50_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN50.Reg) & 0x3e000) >> 13
}

// GPIO.PIN51: GPIO pin configuration register
func (o *GPIO_Type) SetPIN51_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN51_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN51.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN51_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN51_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN51.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN51_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN51_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN51.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN51_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN51_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN51.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN51_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN51_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN51.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN51_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN51_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN51.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN51_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN51.Reg, volatile.LoadUint32(&o.PIN51.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN51_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN51.Reg) & 0x3e000) >> 13
}

// GPIO.PIN52: GPIO pin configuration register
func (o *GPIO_Type) SetPIN52_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN52_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN52.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN52_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN52_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN52.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN52_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN52_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN52.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN52_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN52_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN52.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN52_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN52_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN52.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN52_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN52_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN52.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN52_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN52.Reg, volatile.LoadUint32(&o.PIN52.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN52_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN52.Reg) & 0x3e000) >> 13
}

// GPIO.PIN53: GPIO pin configuration register
func (o *GPIO_Type) SetPIN53_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN53_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN53.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN53_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN53_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN53.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN53_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN53_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN53.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN53_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN53_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN53.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN53_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN53_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN53.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN53_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN53_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN53.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN53_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN53.Reg, volatile.LoadUint32(&o.PIN53.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN53_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN53.Reg) & 0x3e000) >> 13
}

// GPIO.PIN54: GPIO pin configuration register
func (o *GPIO_Type) SetPIN54_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN54_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN54.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN54_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN54_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN54.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN54_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN54_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN54.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN54_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN54_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN54.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN54_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN54_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN54.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN54_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN54_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN54.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN54_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN54.Reg, volatile.LoadUint32(&o.PIN54.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN54_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN54.Reg) & 0x3e000) >> 13
}

// GPIO.PIN55: GPIO pin configuration register
func (o *GPIO_Type) SetPIN55_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN55_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN55.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN55_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN55_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN55.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN55_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN55_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN55.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN55_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN55_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN55.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN55_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN55_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN55.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN55_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN55_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN55.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN55_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN55.Reg, volatile.LoadUint32(&o.PIN55.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN55_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN55.Reg) & 0x3e000) >> 13
}

// GPIO.PIN56: GPIO pin configuration register
func (o *GPIO_Type) SetPIN56_SYNC2_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x3)|value)
}
func (o *GPIO_Type) GetPIN56_SYNC2_BYPASS() uint32 {
	return volatile.LoadUint32(&o.PIN56.Reg) & 0x3
}
func (o *GPIO_Type) SetPIN56_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetPIN56_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN56.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetPIN56_SYNC1_BYPASS(value uint32) {
	volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x18)|value<<3)
}
func (o *GPIO_Type) GetPIN56_SYNC1_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.PIN56.Reg) & 0x18) >> 3
}
func (o *GPIO_Type) SetPIN56_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x380)|value<<7)
}
func (o *GPIO_Type) GetPIN56_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN56.Reg) & 0x380) >> 7
}
func (o *GPIO_Type) SetPIN56_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetPIN56_WAKEUP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.PIN56.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetPIN56_CONFIG(value uint32) {
	volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x1800)|value<<11)
}
func (o *GPIO_Type) GetPIN56_CONFIG() uint32 {
	return (volatile.LoadUint32(&o.PIN56.Reg) & 0x1800) >> 11
}
func (o *GPIO_Type) SetPIN56_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.PIN56.Reg, volatile.LoadUint32(&o.PIN56.Reg)&^(0x3e000)|value<<13)
}
func (o *GPIO_Type) GetPIN56_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.PIN56.Reg) & 0x3e000) >> 13
}

// GPIO.FUNC1_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC1_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC1_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC2_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC2_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC2_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC3_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC3_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC3_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC4_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC4_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC4_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC5_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC5_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC5_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC6_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC6_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC6_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC7_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC7_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC7_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC8_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC8_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC8_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC9_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC9_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC9_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC10_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC10_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC10_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC11_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC11_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC11_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC12_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC12_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC12_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC13_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC13_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC13_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC14_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC14_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC14_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC15_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC15_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC15_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC16_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC16_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC16_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC16_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC16_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC17_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC17_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC17_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC17_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC17_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC18_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC18_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC18_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC18_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC18_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC19_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC19_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC19_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC19_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC19_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC20_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC20_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC20_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC20_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC20_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC21_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC21_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC21_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC21_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC21_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC22_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC22_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC22_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC22_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC22_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC23_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC23_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC23_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC23_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC23_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC24_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC24_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC24_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC24_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC24_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC25_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC25_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC25_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC25_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC25_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC26_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC26_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC26_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC26_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC26_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC27_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC27_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC27_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC27_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC27_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC28_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC28_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC28_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC28_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC28_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC29_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC29_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC29_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC29_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC29_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC30_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC30_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC30_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC30_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC30_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC31_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC31_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC31_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC31_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC31_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC32_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC32_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC32_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC32_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC32_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC33_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC33_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC33_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC33_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC33_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC34_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC34_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC34_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC34_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC34_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC35_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC35_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC35_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC35_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC35_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC36_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC36_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC36_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC36_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC36_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC37_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC37_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC37_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC37_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC37_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC38_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC38_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC38_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC38_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC38_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC39_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC39_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC39_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC39_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC39_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC40_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC40_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC40_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC40_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC40_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC41_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC41_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC41_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC41_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC41_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC42_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC42_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC42_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC42_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC42_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC43_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC43_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC43_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC43_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC43_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC44_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC44_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC44_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC44_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC44_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC45_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC45_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC45_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC45_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC45_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC46_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC46_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC46_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC46_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC46_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC47_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC47_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC47_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC47_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC47_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC48_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC48_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC48_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC48_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC48_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC49_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC49_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC49_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC49_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC49_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC50_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC50_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC50_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC50_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC50_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC51_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC51_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC51_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC51_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC51_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC52_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC52_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC52_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC52_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC52_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC53_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC53_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC53_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC53_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC53_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC54_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC54_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC54_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC54_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC54_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC55_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC55_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC55_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC55_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC55_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC56_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC56_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC56_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC56_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC56_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC57_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC57_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC57_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC57_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC57_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC58_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC58_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC58_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC58_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC58_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC59_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC59_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC59_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC59_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC59_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC60_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC60_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC60_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC60_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC60_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC61_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC61_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC61_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC61_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC61_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC62_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC62_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC62_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC62_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC62_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC63_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC63_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC63_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC63_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC63_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC64_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC64_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC64_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC64_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC64_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC65_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC65_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC65_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC65_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC65_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC66_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC66_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC66_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC66_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC66_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC67_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC67_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC67_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC67_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC67_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC68_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC68_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC68_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC68_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC68_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC69_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC69_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC69_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC69_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC69_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC70_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC70_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC70_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC70_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC70_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC71_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC71_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC71_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC71_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC71_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC72_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC72_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC72_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC72_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC72_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC73_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC73_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC73_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC73_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC73_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC74_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC74_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC74_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC74_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC74_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC75_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC75_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC75_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC75_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC75_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC76_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC76_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC76_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC76_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC76_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC77_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC77_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC77_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC77_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC77_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC78_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC78_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC78_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC78_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC78_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC79_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC79_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC79_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC79_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC79_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC80_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC80_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC80_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC80_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC80_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC81_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC81_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC81_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC81_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC81_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC82_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC82_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC82_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC82_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC82_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC83_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC83_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC83_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC83_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC83_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC84_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC84_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC84_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC84_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC84_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC85_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC85_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC85_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC85_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC85_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC86_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC86_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC86_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC86_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC86_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC87_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC87_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC87_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC87_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC87_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC88_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC88_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC88_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC88_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC88_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC89_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC89_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC89_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC89_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC89_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC90_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC90_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC90_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC90_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC90_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC91_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC91_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC91_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC91_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC91_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC92_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC92_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC92_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC92_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC92_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC93_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC93_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC93_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC93_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC93_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC94_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC94_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC94_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC94_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC94_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC95_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC95_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC95_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC95_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC95_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC96_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC96_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC96_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC96_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC96_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC97_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC97_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC97_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC97_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC97_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC98_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC98_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC98_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC98_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC98_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC99_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC99_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC99_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC99_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC99_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC100_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC100_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC100_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC100_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC100_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC101_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC101_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC101_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC101_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC101_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC102_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC102_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC102_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC102_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC102_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC103_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC103_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC103_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC103_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC103_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC104_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC104_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC104_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC104_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC104_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC105_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC105_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC105_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC105_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC105_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC106_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC106_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC106_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC106_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC106_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC107_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC107_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC107_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC107_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC107_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC108_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC108_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC108_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC108_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC108_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC109_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC109_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC109_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC109_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC109_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC110_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC110_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC110_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC110_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC110_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC111_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC111_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC111_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC111_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC111_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC112_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC112_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC112_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC112_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC112_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC113_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC113_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC113_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC113_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC113_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC114_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC114_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC114_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC114_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC114_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC115_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC115_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC115_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC115_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC115_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC116_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC116_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC116_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC116_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC116_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC117_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC117_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC117_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC117_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC117_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC118_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC118_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC118_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC118_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC118_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC119_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC119_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC119_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC119_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC119_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC120_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC120_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC120_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC120_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC120_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC121_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC121_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC121_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC121_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC121_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC122_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC122_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC122_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC122_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC122_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC123_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC123_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC123_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC123_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC123_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC124_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC124_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC124_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC124_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC124_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC125_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC125_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC125_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC125_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC125_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC126_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC126_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC126_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC126_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC126_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC127_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC127_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC127_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC127_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC127_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC128_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC128_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC128_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC128_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC128_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC129_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC129_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC129_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC129_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC129_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC130_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC130_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC130_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC130_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC130_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC131_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC131_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC131_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC131_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC131_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC132_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC132_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC132_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC132_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC132_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC133_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC133_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC133_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC133_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC133_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC134_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC134_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC134_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC134_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC134_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC135_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC135_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC135_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC135_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC135_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC136_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC136_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC136_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC136_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC136_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC137_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC137_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC137_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC137_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC137_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC138_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC138_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC138_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC138_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC138_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC139_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC139_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC139_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC139_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC139_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC140_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC140_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC140_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC140_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC140_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC141_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC141_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC141_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC141_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC141_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC142_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC142_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC142_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC142_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC142_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC143_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC143_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC143_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC143_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC143_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC144_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC144_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC144_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC144_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC144_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC145_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC145_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC145_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC145_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC145_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC146_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC146_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC146_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC146_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC146_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC147_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC147_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC147_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC147_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC147_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC148_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC148_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC148_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC148_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC148_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC149_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC149_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC149_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC149_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC149_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC150_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC150_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC150_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC150_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC150_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC151_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC151_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC151_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC151_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC151_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC152_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC152_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC152_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC152_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC152_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC153_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC153_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC153_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC153_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC153_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC154_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC154_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC154_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC154_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC154_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC155_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC155_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC155_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC155_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC155_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC156_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC156_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC156_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC156_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC156_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC157_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC157_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC157_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC157_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC157_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC158_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC158_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC158_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC158_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC158_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC159_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC159_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC159_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC159_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC159_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC160_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC160_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC160_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC160_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC160_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC161_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC161_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC161_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC161_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC161_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC162_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC162_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC162_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC162_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC162_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC163_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC163_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC163_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC163_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC163_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC164_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC164_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC164_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC164_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC164_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC165_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC165_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC165_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC165_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC165_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC166_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC166_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC166_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC166_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC166_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC167_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC167_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC167_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC167_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC167_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC168_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC168_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC168_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC168_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC168_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC169_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC169_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC169_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC169_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC169_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC170_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC170_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC170_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC170_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC170_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC171_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC171_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC171_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC171_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC171_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC172_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC172_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC172_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC172_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC172_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC173_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC173_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC173_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC173_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC173_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC174_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC174_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC174_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC174_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC174_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC175_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC175_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC175_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC175_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC175_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC176_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC176_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC176_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC176_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC176_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC177_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC177_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC177_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC177_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC177_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC178_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC178_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC178_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC178_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC178_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC179_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC179_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC179_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC179_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC179_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC180_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC180_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC180_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC180_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC180_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC181_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC181_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC181_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC181_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC181_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC182_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC182_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC182_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC182_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC182_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC183_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC183_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC183_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC183_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC183_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC184_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC184_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC184_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC184_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC184_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC185_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC185_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC185_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC185_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC185_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC186_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC186_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC186_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC186_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC186_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC187_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC187_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC187_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC187_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC187_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC188_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC188_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC188_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC188_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC188_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC189_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC189_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC189_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC189_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC189_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC190_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC190_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC190_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC190_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC190_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC191_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC191_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC191_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC191_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC191_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC192_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC192_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC192_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC192_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC192_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC193_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC193_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC193_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC193_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC193_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC194_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC194_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC194_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC194_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC194_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC195_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC195_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC195_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC195_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC195_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC196_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC196_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC196_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC196_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC196_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC197_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC197_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC197_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC197_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC197_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC198_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC198_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC198_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC198_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC198_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC199_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC199_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC199_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC199_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC199_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC200_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC200_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC200_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC200_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC200_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC201_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC201_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC201_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC201_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC201_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC202_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC202_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC202_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC202_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC202_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC203_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC203_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC203_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC203_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC203_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC204_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC204_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC204_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC204_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC204_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC205_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC205_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC205_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC205_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC205_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC206_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC206_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC206_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC206_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC206_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC207_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC207_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC207_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC207_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC207_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC208_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC208_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC208_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC208_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC208_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC209_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC209_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC209_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC209_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC209_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC210_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC210_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC210_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC210_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC210_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC211_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC211_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC211_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC211_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC211_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC212_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC212_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC212_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC212_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC212_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC213_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC213_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC213_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC213_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC213_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC214_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC214_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC214_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC214_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC214_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC215_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC215_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC215_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC215_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC215_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC216_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC216_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC216_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC216_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC216_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC217_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC217_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC217_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC217_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC217_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC218_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC218_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC218_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC218_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC218_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC219_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC219_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC219_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC219_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC219_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC220_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC220_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC220_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC220_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC220_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC221_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC221_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC221_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC221_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC221_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC222_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC222_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC222_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC222_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC222_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC223_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC223_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC223_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC223_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC223_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC224_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC224_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC224_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC224_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC224_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC225_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC225_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC225_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC225_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC225_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC226_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC226_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC226_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC226_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC226_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC227_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC227_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC227_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC227_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC227_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC228_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC228_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC228_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC228_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC228_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC229_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC229_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC229_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC229_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC229_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC230_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC230_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC230_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC230_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC230_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC231_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC231_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC231_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC231_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC231_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC232_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC232_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC232_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC232_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC232_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC233_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC233_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC233_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC233_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC233_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC234_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC234_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC234_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC234_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC234_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC235_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC235_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC235_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC235_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC235_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC236_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC236_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC236_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC236_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC236_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC237_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC237_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC237_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC237_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC237_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC238_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC238_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC238_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC238_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC238_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC239_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC239_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC239_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC239_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC239_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC240_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC240_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC240_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC240_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC240_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC241_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC241_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC241_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC241_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC241_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC242_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC242_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC242_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC242_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC242_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC243_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC243_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC243_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC243_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC243_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC244_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC244_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC244_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC244_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC244_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC245_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC245_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC245_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC245_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC245_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC246_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC246_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC246_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC246_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC246_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC247_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC247_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC247_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC247_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC247_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC248_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC248_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC248_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC248_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC248_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC249_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC249_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC249_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC249_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC249_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC250_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC250_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC250_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC250_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC250_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC251_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC251_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC251_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC251_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC251_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC252_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC252_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC252_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC252_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC252_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC253_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC253_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC253_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC253_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC253_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC254_IN_SEL_CFG: GPIO input function configuration register
func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x3f
}
func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_IN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetFUNC254_IN_SEL_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC254_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetFUNC254_IN_SEL_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC254_IN_SEL_CFG.Reg) & 0x80) >> 7
}

// GPIO.FUNC0_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC0_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC0_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC1_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC1_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC1_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC2_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC2_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC2_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC3_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC3_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC3_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC4_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC4_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC4_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC5_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC5_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC5_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC6_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC6_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC6_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC7_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC7_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC7_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC8_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC8_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC8_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC9_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC9_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC9_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC10_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC10_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC10_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC11_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC11_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC11_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC12_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC12_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC12_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC13_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC13_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC13_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC14_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC14_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC14_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC15_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC15_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC15_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC16_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC16_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC16_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC16_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC16_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC17_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC17_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC17_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC17_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC17_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC18_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC18_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC18_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC18_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC18_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC19_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC19_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC19_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC19_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC19_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC20_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC20_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC20_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC20_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC20_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC21_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC21_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC21_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC21_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC21_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC22_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC22_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC22_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC22_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC22_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC23_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC23_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC23_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC23_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC23_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC24_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC24_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC24_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC24_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC24_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC25_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC25_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC25_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC25_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC25_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC26_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC26_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC26_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC26_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC26_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC27_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC27_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC27_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC27_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC27_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC28_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC28_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC28_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC28_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC28_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC29_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC29_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC29_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC29_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC29_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC30_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC30_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC30_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC30_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC30_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC31_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC31_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC31_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC31_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC31_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC32_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC32_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC32_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC32_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC32_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC33_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC33_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC33_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC33_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC33_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC34_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC34_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC34_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC34_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC34_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC35_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC35_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC35_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC35_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC35_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC36_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC36_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC36_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC36_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC36_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC37_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC37_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC37_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC37_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC37_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC38_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC38_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC38_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC38_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC38_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC39_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC39_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC39_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC39_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC39_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC40_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC40_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC40_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC40_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC40_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC41_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC41_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC41_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC41_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC41_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC42_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC42_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC42_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC42_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC42_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC43_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC43_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC43_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC43_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC43_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC44_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC44_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC44_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC44_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC44_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC45_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC45_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC45_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC45_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC45_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC46_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC46_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC46_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC46_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC46_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC47_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC47_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC47_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC47_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC47_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC48_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC48_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC48_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC48_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC48_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC49_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC49_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC49_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC49_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC49_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC50_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC50_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC50_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC50_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC50_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC51_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC51_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC51_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC51_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC51_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC52_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC52_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC52_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC52_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC52_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC53_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC53_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC53_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC53_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC53_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC54_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC54_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC54_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC54_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC54_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC55_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC55_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC55_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC55_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC55_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.FUNC56_OUT_SEL_CFG: GPIO output function select register
func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x1ff)|value)
}
func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_OUT_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x1ff
}
func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_OEN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_OEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetFUNC56_OUT_SEL_CFG_OEN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC56_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetFUNC56_OUT_SEL_CFG_OEN_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC56_OUT_SEL_CFG.Reg) & 0x800) >> 11
}

// GPIO.INTR_2: GPIO interrupt 2 status register for GPIO0-31
func (o *GPIO_Type) SetINTR_2(value uint32) {
	volatile.StoreUint32(&o.INTR_2.Reg, value)
}
func (o *GPIO_Type) GetINTR_2() uint32 {
	return volatile.LoadUint32(&o.INTR_2.Reg)
}

// GPIO.INTR1_2: GPIO interrupt 2 status register for GPIO32-56
func (o *GPIO_Type) SetINTR1_2_INT1_2(value uint32) {
	volatile.StoreUint32(&o.INTR1_2.Reg, volatile.LoadUint32(&o.INTR1_2.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetINTR1_2_INT1_2() uint32 {
	return volatile.LoadUint32(&o.INTR1_2.Reg) & 0x1ffffff
}

// GPIO.INTR_3: GPIO interrupt 3 status register for GPIO0-31
func (o *GPIO_Type) SetINTR_3(value uint32) {
	volatile.StoreUint32(&o.INTR_3.Reg, value)
}
func (o *GPIO_Type) GetINTR_3() uint32 {
	return volatile.LoadUint32(&o.INTR_3.Reg)
}

// GPIO.INTR1_3: GPIO interrupt 3 status register for GPIO32-56
func (o *GPIO_Type) SetINTR1_3_INT1_3(value uint32) {
	volatile.StoreUint32(&o.INTR1_3.Reg, volatile.LoadUint32(&o.INTR1_3.Reg)&^(0x1ffffff)|value)
}
func (o *GPIO_Type) GetINTR1_3_INT1_3() uint32 {
	return volatile.LoadUint32(&o.INTR1_3.Reg) & 0x1ffffff
}

// GPIO.CLOCK_GATE: GPIO clock gate register
func (o *GPIO_Type) SetCLOCK_GATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *GPIO_Type) GetCLOCK_GATE_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1
}

// GPIO.INT_RAW: analog comparator interrupt raw
func (o *GPIO_Type) SetINT_RAW_COMP0_NEG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *GPIO_Type) GetINT_RAW_COMP0_NEG_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *GPIO_Type) SetINT_RAW_COMP0_POS_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetINT_RAW_COMP0_POS_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetINT_RAW_COMP0_ALL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetINT_RAW_COMP0_ALL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetINT_RAW_COMP1_NEG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetINT_RAW_COMP1_NEG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetINT_RAW_COMP1_POS_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetINT_RAW_COMP1_POS_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetINT_RAW_COMP1_ALL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetINT_RAW_COMP1_ALL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetINT_RAW_BISTOK_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetINT_RAW_BISTOK_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetINT_RAW_BISTFAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetINT_RAW_BISTFAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}

// GPIO.INT_ST: analog comparator interrupt status
func (o *GPIO_Type) SetINT_ST_COMP0_NEG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *GPIO_Type) GetINT_ST_COMP0_NEG_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *GPIO_Type) SetINT_ST_COMP0_POS_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetINT_ST_COMP0_POS_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetINT_ST_COMP0_ALL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetINT_ST_COMP0_ALL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetINT_ST_COMP1_NEG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetINT_ST_COMP1_NEG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetINT_ST_COMP1_POS_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetINT_ST_COMP1_POS_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetINT_ST_COMP1_ALL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetINT_ST_COMP1_ALL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetINT_ST_BISTOK_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetINT_ST_BISTOK_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetINT_ST_BISTFAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetINT_ST_BISTFAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}

// GPIO.INT_ENA: analog comparator interrupt enable
func (o *GPIO_Type) SetINT_ENA_COMP0_NEG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *GPIO_Type) GetINT_ENA_COMP0_NEG_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *GPIO_Type) SetINT_ENA_COMP0_POS_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetINT_ENA_COMP0_POS_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetINT_ENA_COMP0_ALL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetINT_ENA_COMP0_ALL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetINT_ENA_COMP1_NEG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetINT_ENA_COMP1_NEG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetINT_ENA_COMP1_POS_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetINT_ENA_COMP1_POS_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetINT_ENA_COMP1_ALL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetINT_ENA_COMP1_ALL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetINT_ENA_BISTOK_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetINT_ENA_BISTOK_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetINT_ENA_BISTFAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetINT_ENA_BISTFAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}

// GPIO.INT_CLR: analog comparator interrupt clear
func (o *GPIO_Type) SetINT_CLR_COMP0_NEG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *GPIO_Type) GetINT_CLR_COMP0_NEG_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *GPIO_Type) SetINT_CLR_COMP0_POS_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetINT_CLR_COMP0_POS_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetINT_CLR_COMP0_ALL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetINT_CLR_COMP0_ALL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetINT_CLR_COMP1_NEG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetINT_CLR_COMP1_NEG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetINT_CLR_COMP1_POS_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetINT_CLR_COMP1_POS_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetINT_CLR_COMP1_ALL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetINT_CLR_COMP1_ALL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetINT_CLR_BISTOK_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetINT_CLR_BISTOK_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetINT_CLR_BISTFAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetINT_CLR_BISTFAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}

// GPIO.ZERO_DET0_FILTER_CNT: GPIO analog comparator zero detect filter count
func (o *GPIO_Type) SetZERO_DET0_FILTER_CNT(value uint32) {
	volatile.StoreUint32(&o.ZERO_DET0_FILTER_CNT.Reg, value)
}
func (o *GPIO_Type) GetZERO_DET0_FILTER_CNT() uint32 {
	return volatile.LoadUint32(&o.ZERO_DET0_FILTER_CNT.Reg)
}

// GPIO.ZERO_DET1_FILTER_CNT: GPIO analog comparator zero detect filter count
func (o *GPIO_Type) SetZERO_DET1_FILTER_CNT(value uint32) {
	volatile.StoreUint32(&o.ZERO_DET1_FILTER_CNT.Reg, value)
}
func (o *GPIO_Type) GetZERO_DET1_FILTER_CNT() uint32 {
	return volatile.LoadUint32(&o.ZERO_DET1_FILTER_CNT.Reg)
}

// GPIO.SEND_SEQ: High speed sdio pad bist send sequence
func (o *GPIO_Type) SetSEND_SEQ(value uint32) {
	volatile.StoreUint32(&o.SEND_SEQ.Reg, value)
}
func (o *GPIO_Type) GetSEND_SEQ() uint32 {
	return volatile.LoadUint32(&o.SEND_SEQ.Reg)
}

// GPIO.RECIVE_SEQ: High speed sdio pad bist recive sequence
func (o *GPIO_Type) SetRECIVE_SEQ(value uint32) {
	volatile.StoreUint32(&o.RECIVE_SEQ.Reg, value)
}
func (o *GPIO_Type) GetRECIVE_SEQ() uint32 {
	return volatile.LoadUint32(&o.RECIVE_SEQ.Reg)
}

// GPIO.BISTIN_SEL: High speed sdio pad bist in pad sel
func (o *GPIO_Type) SetBISTIN_SEL(value uint32) {
	volatile.StoreUint32(&o.BISTIN_SEL.Reg, volatile.LoadUint32(&o.BISTIN_SEL.Reg)&^(0xf)|value)
}
func (o *GPIO_Type) GetBISTIN_SEL() uint32 {
	return volatile.LoadUint32(&o.BISTIN_SEL.Reg) & 0xf
}

// GPIO.BIST_CTRL: High speed sdio pad bist control
func (o *GPIO_Type) SetBIST_CTRL_BIST_PAD_OE(value uint32) {
	volatile.StoreUint32(&o.BIST_CTRL.Reg, volatile.LoadUint32(&o.BIST_CTRL.Reg)&^(0x1)|value)
}
func (o *GPIO_Type) GetBIST_CTRL_BIST_PAD_OE() uint32 {
	return volatile.LoadUint32(&o.BIST_CTRL.Reg) & 0x1
}
func (o *GPIO_Type) SetBIST_CTRL_BIST_START(value uint32) {
	volatile.StoreUint32(&o.BIST_CTRL.Reg, volatile.LoadUint32(&o.BIST_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBIST_CTRL_BIST_START() uint32 {
	return (volatile.LoadUint32(&o.BIST_CTRL.Reg) & 0x2) >> 1
}

// GPIO.DATE: GPIO version register
func (o *GPIO_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *GPIO_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// Sigma-Delta Modulation
type GPIOSD_Type struct {
	SIGMADELTA0       volatile.Register32 // 0x0
	SIGMADELTA1       volatile.Register32 // 0x4
	SIGMADELTA2       volatile.Register32 // 0x8
	SIGMADELTA3       volatile.Register32 // 0xC
	SIGMADELTA4       volatile.Register32 // 0x10
	SIGMADELTA5       volatile.Register32 // 0x14
	SIGMADELTA6       volatile.Register32 // 0x18
	SIGMADELTA7       volatile.Register32 // 0x1C
	CLOCK_GATE        volatile.Register32 // 0x20
	SIGMADELTA_MISC   volatile.Register32 // 0x24
	_                 [8]byte
	GLITCH_FILTER_CH0 volatile.Register32 // 0x30
	GLITCH_FILTER_CH1 volatile.Register32 // 0x34
	GLITCH_FILTER_CH2 volatile.Register32 // 0x38
	GLITCH_FILTER_CH3 volatile.Register32 // 0x3C
	GLITCH_FILTER_CH4 volatile.Register32 // 0x40
	GLITCH_FILTER_CH5 volatile.Register32 // 0x44
	GLITCH_FILTER_CH6 volatile.Register32 // 0x48
	GLITCH_FILTER_CH7 volatile.Register32 // 0x4C
	_                 [16]byte
	ETM_EVENT_CH0_CFG volatile.Register32 // 0x60
	ETM_EVENT_CH1_CFG volatile.Register32 // 0x64
	ETM_EVENT_CH2_CFG volatile.Register32 // 0x68
	ETM_EVENT_CH3_CFG volatile.Register32 // 0x6C
	ETM_EVENT_CH4_CFG volatile.Register32 // 0x70
	ETM_EVENT_CH5_CFG volatile.Register32 // 0x74
	ETM_EVENT_CH6_CFG volatile.Register32 // 0x78
	ETM_EVENT_CH7_CFG volatile.Register32 // 0x7C
	_                 [32]byte
	ETM_TASK_P0_CFG   volatile.Register32 // 0xA0
	ETM_TASK_P1_CFG   volatile.Register32 // 0xA4
	ETM_TASK_P2_CFG   volatile.Register32 // 0xA8
	ETM_TASK_P3_CFG   volatile.Register32 // 0xAC
	ETM_TASK_P4_CFG   volatile.Register32 // 0xB0
	ETM_TASK_P5_CFG   volatile.Register32 // 0xB4
	ETM_TASK_P6_CFG   volatile.Register32 // 0xB8
	ETM_TASK_P7_CFG   volatile.Register32 // 0xBC
	ETM_TASK_P8_CFG   volatile.Register32 // 0xC0
	ETM_TASK_P9_CFG   volatile.Register32 // 0xC4
	ETM_TASK_P10_CFG  volatile.Register32 // 0xC8
	ETM_TASK_P11_CFG  volatile.Register32 // 0xCC
	ETM_TASK_P12_CFG  volatile.Register32 // 0xD0
	ETM_TASK_P13_CFG  volatile.Register32 // 0xD4
	_                 [36]byte
	VERSION           volatile.Register32 // 0xFC
}

// GPIOSD.SIGMADELTA0: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA0_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA0_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA0_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA0.Reg, volatile.LoadUint32(&o.SIGMADELTA0.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA0_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA0.Reg) & 0xff00) >> 8
}

// GPIOSD.SIGMADELTA1: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA1_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA1_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA1_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA1.Reg, volatile.LoadUint32(&o.SIGMADELTA1.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA1_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA1.Reg) & 0xff00) >> 8
}

// GPIOSD.SIGMADELTA2: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA2_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA2_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA2_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA2.Reg, volatile.LoadUint32(&o.SIGMADELTA2.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA2_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA2.Reg) & 0xff00) >> 8
}

// GPIOSD.SIGMADELTA3: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA3_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA3_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA3_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA3.Reg, volatile.LoadUint32(&o.SIGMADELTA3.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA3_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA3.Reg) & 0xff00) >> 8
}

// GPIOSD.SIGMADELTA4: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA4_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA4_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA4_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA4.Reg, volatile.LoadUint32(&o.SIGMADELTA4.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA4_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA4.Reg) & 0xff00) >> 8
}

// GPIOSD.SIGMADELTA5: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA5_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA5_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA5_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA5.Reg, volatile.LoadUint32(&o.SIGMADELTA5.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA5_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA5.Reg) & 0xff00) >> 8
}

// GPIOSD.SIGMADELTA6: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA6_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA6_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA6_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA6.Reg, volatile.LoadUint32(&o.SIGMADELTA6.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA6_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA6.Reg) & 0xff00) >> 8
}

// GPIOSD.SIGMADELTA7: Duty Cycle Configure Register of SDM%s
func (o *GPIOSD_Type) SetSIGMADELTA7_SD_IN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff)|value)
}
func (o *GPIOSD_Type) GetSIGMADELTA7_SD_IN() uint32 {
	return volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff
}
func (o *GPIOSD_Type) SetSIGMADELTA7_SD_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA7.Reg, volatile.LoadUint32(&o.SIGMADELTA7.Reg)&^(0xff00)|value<<8)
}
func (o *GPIOSD_Type) GetSIGMADELTA7_SD_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA7.Reg) & 0xff00) >> 8
}

// GPIOSD.CLOCK_GATE: Clock Gating Configure Register
func (o *GPIOSD_Type) SetCLOCK_GATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetCLOCK_GATE_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1
}

// GPIOSD.SIGMADELTA_MISC: MISC Register
func (o *GPIOSD_Type) SetSIGMADELTA_MISC_FUNCTION_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x40000000)|value<<30)
}
func (o *GPIOSD_Type) GetSIGMADELTA_MISC_FUNCTION_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x40000000) >> 30
}
func (o *GPIOSD_Type) SetSIGMADELTA_MISC_SPI_SWAP(value uint32) {
	volatile.StoreUint32(&o.SIGMADELTA_MISC.Reg, volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg)&^(0x80000000)|value<<31)
}
func (o *GPIOSD_Type) GetSIGMADELTA_MISC_SPI_SWAP() uint32 {
	return (volatile.LoadUint32(&o.SIGMADELTA_MISC.Reg) & 0x80000000) >> 31
}

// GPIOSD.GLITCH_FILTER_CH0: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH0.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH0_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH0.Reg) & 0x7e000) >> 13
}

// GPIOSD.GLITCH_FILTER_CH1: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH1.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH1_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH1.Reg) & 0x7e000) >> 13
}

// GPIOSD.GLITCH_FILTER_CH2: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH2.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH2_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH2.Reg) & 0x7e000) >> 13
}

// GPIOSD.GLITCH_FILTER_CH3: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH3.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH3_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH3.Reg) & 0x7e000) >> 13
}

// GPIOSD.GLITCH_FILTER_CH4: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH4.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH4_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH4.Reg) & 0x7e000) >> 13
}

// GPIOSD.GLITCH_FILTER_CH5: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH5.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH5_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH5.Reg) & 0x7e000) >> 13
}

// GPIOSD.GLITCH_FILTER_CH6: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH6.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH6_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH6.Reg) & 0x7e000) >> 13
}

// GPIOSD.GLITCH_FILTER_CH7: Glitch Filter Configure Register of Channel%s
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e)|value<<1)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_INPUT_IO_NUM() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e) >> 1
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x1f80)|value<<7)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_THRES() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x1f80) >> 7
}
func (o *GPIOSD_Type) SetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH(value uint32) {
	volatile.StoreUint32(&o.GLITCH_FILTER_CH7.Reg, volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg)&^(0x7e000)|value<<13)
}
func (o *GPIOSD_Type) GetGLITCH_FILTER_CH7_FILTER_CH0_WINDOW_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.GLITCH_FILTER_CH7.Reg) & 0x7e000) >> 13
}

// GPIOSD.ETM_EVENT_CH0_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH0_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH0_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH0_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_EVENT_CH1_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH1_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH1_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH1_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_EVENT_CH2_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH2_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH2_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH2_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_EVENT_CH3_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH3_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH3_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH3_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_EVENT_CH4_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH4_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH4_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH4_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_EVENT_CH5_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH5_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH5_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH5_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_EVENT_CH6_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH6_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH6_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH6_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_EVENT_CH7_CFG: Etm Config register of Channel%s
func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x3f)|value)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_SEL() uint32 {
	return volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x3f
}
func (o *GPIOSD_Type) SetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_EVENT_CH7_CFG.Reg, volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg)&^(0x80)|value<<7)
}
func (o *GPIOSD_Type) GetETM_EVENT_CH7_CFG_ETM_CH0_EVENT_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_EVENT_CH7_CFG.Reg) & 0x80) >> 7
}

// GPIOSD.ETM_TASK_P0_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P0_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P0_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P1_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P1_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P1_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P2_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P2_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P2_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P3_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P3_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P3_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P4_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P4_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P4_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P5_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P5_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P5_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P6_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P6_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P6_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P7_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO31_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO31_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P7_CFG_ETM_TASK_GPIO31_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P7_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P7_CFG_ETM_TASK_GPIO31_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P7_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P8_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO32_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO32_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO32_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO32_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO33_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO33_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO33_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO33_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO34_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO34_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO34_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO34_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO35_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO35_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P8_CFG_ETM_TASK_GPIO35_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P8_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P8_CFG_ETM_TASK_GPIO35_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P8_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P9_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO36_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO36_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO36_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO36_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO37_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO37_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO37_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO37_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO38_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO38_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO38_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO38_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO39_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO39_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P9_CFG_ETM_TASK_GPIO39_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P9_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P9_CFG_ETM_TASK_GPIO39_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P9_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P10_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO40_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO40_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO40_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO40_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO41_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO41_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO41_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO41_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO42_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO42_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO42_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO42_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO43_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO43_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P10_CFG_ETM_TASK_GPIO43_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P10_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P10_CFG_ETM_TASK_GPIO43_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P10_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P11_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO44_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO44_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO44_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO44_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO45_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO45_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO45_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO45_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO46_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO46_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO46_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO46_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO47_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO47_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P11_CFG_ETM_TASK_GPIO47_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P11_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P11_CFG_ETM_TASK_GPIO47_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P11_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P12_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO48_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO48_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO48_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO48_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO49_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO49_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO49_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO49_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO50_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO50_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO50_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO50_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe0000) >> 17
}
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO51_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO51_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0x1000000) >> 24
}
func (o *GPIOSD_Type) SetETM_TASK_P12_CFG_ETM_TASK_GPIO51_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P12_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg)&^(0xe000000)|value<<25)
}
func (o *GPIOSD_Type) GetETM_TASK_P12_CFG_ETM_TASK_GPIO51_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P12_CFG.Reg) & 0xe000000) >> 25
}

// GPIOSD.ETM_TASK_P13_CFG: Etm Configure Register to decide which GPIO been chosen
func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO52_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0x1)|value)
}
func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO52_EN() uint32 {
	return volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0x1
}
func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO52_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0xe)|value<<1)
}
func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO52_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0xe) >> 1
}
func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO53_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0x100)|value<<8)
}
func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO53_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0x100) >> 8
}
func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO53_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0xe00)|value<<9)
}
func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO53_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0xe00) >> 9
}
func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO54_EN(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO54_EN() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0x10000) >> 16
}
func (o *GPIOSD_Type) SetETM_TASK_P13_CFG_ETM_TASK_GPIO54_SEL(value uint32) {
	volatile.StoreUint32(&o.ETM_TASK_P13_CFG.Reg, volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg)&^(0xe0000)|value<<17)
}
func (o *GPIOSD_Type) GetETM_TASK_P13_CFG_ETM_TASK_GPIO54_SEL() uint32 {
	return (volatile.LoadUint32(&o.ETM_TASK_P13_CFG.Reg) & 0xe0000) >> 17
}

// GPIOSD.VERSION: Version Control Register
func (o *GPIOSD_Type) SetVERSION_GPIO_SD_DATE(value uint32) {
	volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value)
}
func (o *GPIOSD_Type) GetVERSION_GPIO_SD_DATE() uint32 {
	return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff
}

// H264 Encoder (Core)
type H264_Type struct {
	SYS_CTRL                  volatile.Register32 // 0x0
	GOP_CONF                  volatile.Register32 // 0x4
	A_SYS_MB_RES              volatile.Register32 // 0x8
	A_SYS_CONF                volatile.Register32 // 0xC
	A_DECI_SCORE              volatile.Register32 // 0x10
	A_DECI_SCORE_OFFSET       volatile.Register32 // 0x14
	A_RC_CONF0                volatile.Register32 // 0x18
	A_RC_CONF1                volatile.Register32 // 0x1C
	A_DB_BYPASS               volatile.Register32 // 0x20
	A_ROI_REGION0             volatile.Register32 // 0x24
	A_ROI_REGION1             volatile.Register32 // 0x28
	A_ROI_REGION2             volatile.Register32 // 0x2C
	A_ROI_REGION3             volatile.Register32 // 0x30
	A_ROI_REGION4             volatile.Register32 // 0x34
	A_ROI_REGION5             volatile.Register32 // 0x38
	A_ROI_REGION6             volatile.Register32 // 0x3C
	A_ROI_REGION7             volatile.Register32 // 0x40
	A_ROI_REGION0_3_QP        volatile.Register32 // 0x44
	A_ROI_REGION4_7_QP        volatile.Register32 // 0x48
	A_NO_ROI_REGION_QP_OFFSET volatile.Register32 // 0x4C
	A_ROI_CONFIG              volatile.Register32 // 0x50
	B_SYS_MB_RES              volatile.Register32 // 0x54
	B_SYS_CONF                volatile.Register32 // 0x58
	B_DECI_SCORE              volatile.Register32 // 0x5C
	B_DECI_SCORE_OFFSET       volatile.Register32 // 0x60
	B_RC_CONF0                volatile.Register32 // 0x64
	B_RC_CONF1                volatile.Register32 // 0x68
	B_DB_BYPASS               volatile.Register32 // 0x6C
	B_ROI_REGION0             volatile.Register32 // 0x70
	B_ROI_REGION1             volatile.Register32 // 0x74
	B_ROI_REGION2             volatile.Register32 // 0x78
	B_ROI_REGION3             volatile.Register32 // 0x7C
	B_ROI_REGION4             volatile.Register32 // 0x80
	B_ROI_REGION5             volatile.Register32 // 0x84
	B_ROI_REGION6             volatile.Register32 // 0x88
	B_ROI_REGION7             volatile.Register32 // 0x8C
	B_ROI_REGION0_3_QP        volatile.Register32 // 0x90
	B_ROI_REGION4_7_QP        volatile.Register32 // 0x94
	B_NO_ROI_REGION_QP_OFFSET volatile.Register32 // 0x98
	B_ROI_CONFIG              volatile.Register32 // 0x9C
	RC_STATUS0                volatile.Register32 // 0xA0
	RC_STATUS1                volatile.Register32 // 0xA4
	RC_STATUS2                volatile.Register32 // 0xA8
	SLICE_HEADER_REMAIN       volatile.Register32 // 0xAC
	SLICE_HEADER_BYTE_LENGTH  volatile.Register32 // 0xB0
	BS_THRESHOLD              volatile.Register32 // 0xB4
	SLICE_HEADER_BYTE0        volatile.Register32 // 0xB8
	SLICE_HEADER_BYTE1        volatile.Register32 // 0xBC
	INT_RAW                   volatile.Register32 // 0xC0
	INT_ST                    volatile.Register32 // 0xC4
	INT_ENA                   volatile.Register32 // 0xC8
	INT_CLR                   volatile.Register32 // 0xCC
	CONF                      volatile.Register32 // 0xD0
	MV_MERGE_CONFIG           volatile.Register32 // 0xD4
	DEBUG_DMA_SEL             volatile.Register32 // 0xD8
	SYS_STATUS                volatile.Register32 // 0xDC
	FRAME_CODE_LENGTH         volatile.Register32 // 0xE0
	DEBUG_INFO0               volatile.Register32 // 0xE4
	DEBUG_INFO1               volatile.Register32 // 0xE8
	DEBUG_INFO2               volatile.Register32 // 0xEC
	DATE                      volatile.Register32 // 0xF0
}

// H264.SYS_CTRL: H264 system level control register.
func (o *H264_Type) SetSYS_CTRL_FRAME_START(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetSYS_CTRL_FRAME_START() uint32 {
	return volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1
}
func (o *H264_Type) SetSYS_CTRL_DMA_MOVE_START(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetSYS_CTRL_DMA_MOVE_START() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x2) >> 1
}
func (o *H264_Type) SetSYS_CTRL_FRAME_MODE(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetSYS_CTRL_FRAME_MODE() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetSYS_CTRL_SYS_RST_PULSE(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetSYS_CTRL_SYS_RST_PULSE() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x8) >> 3
}

// H264.GOP_CONF: GOP related configuration register.
func (o *H264_Type) SetGOP_CONF_DUAL_STREAM_MODE(value uint32) {
	volatile.StoreUint32(&o.GOP_CONF.Reg, volatile.LoadUint32(&o.GOP_CONF.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetGOP_CONF_DUAL_STREAM_MODE() uint32 {
	return volatile.LoadUint32(&o.GOP_CONF.Reg) & 0x1
}
func (o *H264_Type) SetGOP_CONF_GOP_NUM(value uint32) {
	volatile.StoreUint32(&o.GOP_CONF.Reg, volatile.LoadUint32(&o.GOP_CONF.Reg)&^(0x1fe)|value<<1)
}
func (o *H264_Type) GetGOP_CONF_GOP_NUM() uint32 {
	return (volatile.LoadUint32(&o.GOP_CONF.Reg) & 0x1fe) >> 1
}

// H264.A_SYS_MB_RES: Video A horizontal and vertical MB resolution register.
func (o *H264_Type) SetA_SYS_MB_RES_A_SYS_TOTAL_MB_Y(value uint32) {
	volatile.StoreUint32(&o.A_SYS_MB_RES.Reg, volatile.LoadUint32(&o.A_SYS_MB_RES.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_SYS_MB_RES_A_SYS_TOTAL_MB_Y() uint32 {
	return volatile.LoadUint32(&o.A_SYS_MB_RES.Reg) & 0x7f
}
func (o *H264_Type) SetA_SYS_MB_RES_A_SYS_TOTAL_MB_X(value uint32) {
	volatile.StoreUint32(&o.A_SYS_MB_RES.Reg, volatile.LoadUint32(&o.A_SYS_MB_RES.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_SYS_MB_RES_A_SYS_TOTAL_MB_X() uint32 {
	return (volatile.LoadUint32(&o.A_SYS_MB_RES.Reg) & 0x3f80) >> 7
}

// H264.A_SYS_CONF: Video A system level configuration register.
func (o *H264_Type) SetA_SYS_CONF_A_DB_TMP_READY_TRIGGER_MB_NUM(value uint32) {
	volatile.StoreUint32(&o.A_SYS_CONF.Reg, volatile.LoadUint32(&o.A_SYS_CONF.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_SYS_CONF_A_DB_TMP_READY_TRIGGER_MB_NUM() uint32 {
	return volatile.LoadUint32(&o.A_SYS_CONF.Reg) & 0x7f
}
func (o *H264_Type) SetA_SYS_CONF_A_REC_READY_TRIGGER_MB_LINES(value uint32) {
	volatile.StoreUint32(&o.A_SYS_CONF.Reg, volatile.LoadUint32(&o.A_SYS_CONF.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_SYS_CONF_A_REC_READY_TRIGGER_MB_LINES() uint32 {
	return (volatile.LoadUint32(&o.A_SYS_CONF.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_SYS_CONF_A_INTRA_COST_CMP_OFFSET(value uint32) {
	volatile.StoreUint32(&o.A_SYS_CONF.Reg, volatile.LoadUint32(&o.A_SYS_CONF.Reg)&^(0x3fffc000)|value<<14)
}
func (o *H264_Type) GetA_SYS_CONF_A_INTRA_COST_CMP_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.A_SYS_CONF.Reg) & 0x3fffc000) >> 14
}

// H264.A_DECI_SCORE: Video A luma and chroma MB decimate score Register.
func (o *H264_Type) SetA_DECI_SCORE_A_C_DECI_SCORE(value uint32) {
	volatile.StoreUint32(&o.A_DECI_SCORE.Reg, volatile.LoadUint32(&o.A_DECI_SCORE.Reg)&^(0x3ff)|value)
}
func (o *H264_Type) GetA_DECI_SCORE_A_C_DECI_SCORE() uint32 {
	return volatile.LoadUint32(&o.A_DECI_SCORE.Reg) & 0x3ff
}
func (o *H264_Type) SetA_DECI_SCORE_A_L_DECI_SCORE(value uint32) {
	volatile.StoreUint32(&o.A_DECI_SCORE.Reg, volatile.LoadUint32(&o.A_DECI_SCORE.Reg)&^(0xffc00)|value<<10)
}
func (o *H264_Type) GetA_DECI_SCORE_A_L_DECI_SCORE() uint32 {
	return (volatile.LoadUint32(&o.A_DECI_SCORE.Reg) & 0xffc00) >> 10
}

// H264.A_DECI_SCORE_OFFSET: Video A luma and chroma MB decimate score offset Register.
func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_I16X16_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0x3f)|value)
}
func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_I16X16_DECI_SCORE_OFFSET() uint32 {
	return volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0x3f
}
func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_I_CHROMA_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0xfc0)|value<<6)
}
func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_I_CHROMA_DECI_SCORE_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0xfc0) >> 6
}
func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_P16X16_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0x3f000)|value<<12)
}
func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_P16X16_DECI_SCORE_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0x3f000) >> 12
}
func (o *H264_Type) SetA_DECI_SCORE_OFFSET_A_P_CHROMA_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.A_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg)&^(0xfc0000)|value<<18)
}
func (o *H264_Type) GetA_DECI_SCORE_OFFSET_A_P_CHROMA_DECI_SCORE_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.A_DECI_SCORE_OFFSET.Reg) & 0xfc0000) >> 18
}

// H264.A_RC_CONF0: Video A rate control configuration register0.
func (o *H264_Type) SetA_RC_CONF0_A_QP(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF0.Reg, volatile.LoadUint32(&o.A_RC_CONF0.Reg)&^(0x3f)|value)
}
func (o *H264_Type) GetA_RC_CONF0_A_QP() uint32 {
	return volatile.LoadUint32(&o.A_RC_CONF0.Reg) & 0x3f
}
func (o *H264_Type) SetA_RC_CONF0_A_RATE_CTRL_U(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF0.Reg, volatile.LoadUint32(&o.A_RC_CONF0.Reg)&^(0x3fffc0)|value<<6)
}
func (o *H264_Type) GetA_RC_CONF0_A_RATE_CTRL_U() uint32 {
	return (volatile.LoadUint32(&o.A_RC_CONF0.Reg) & 0x3fffc0) >> 6
}
func (o *H264_Type) SetA_RC_CONF0_A_MB_RATE_CTRL_EN(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF0.Reg, volatile.LoadUint32(&o.A_RC_CONF0.Reg)&^(0x400000)|value<<22)
}
func (o *H264_Type) GetA_RC_CONF0_A_MB_RATE_CTRL_EN() uint32 {
	return (volatile.LoadUint32(&o.A_RC_CONF0.Reg) & 0x400000) >> 22
}

// H264.A_RC_CONF1: Video A rate control configuration register1.
func (o *H264_Type) SetA_RC_CONF1_A_CHROMA_DC_QP_DELTA(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x7)|value)
}
func (o *H264_Type) GetA_RC_CONF1_A_CHROMA_DC_QP_DELTA() uint32 {
	return volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x7
}
func (o *H264_Type) SetA_RC_CONF1_A_CHROMA_QP_DELTA(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x78)|value<<3)
}
func (o *H264_Type) GetA_RC_CONF1_A_CHROMA_QP_DELTA() uint32 {
	return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x78) >> 3
}
func (o *H264_Type) SetA_RC_CONF1_A_QP_MIN(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x1f80)|value<<7)
}
func (o *H264_Type) GetA_RC_CONF1_A_QP_MIN() uint32 {
	return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x1f80) >> 7
}
func (o *H264_Type) SetA_RC_CONF1_A_QP_MAX(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x7e000)|value<<13)
}
func (o *H264_Type) GetA_RC_CONF1_A_QP_MAX() uint32 {
	return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x7e000) >> 13
}
func (o *H264_Type) SetA_RC_CONF1_A_MAD_FRAME_PRED(value uint32) {
	volatile.StoreUint32(&o.A_RC_CONF1.Reg, volatile.LoadUint32(&o.A_RC_CONF1.Reg)&^(0x7ff80000)|value<<19)
}
func (o *H264_Type) GetA_RC_CONF1_A_MAD_FRAME_PRED() uint32 {
	return (volatile.LoadUint32(&o.A_RC_CONF1.Reg) & 0x7ff80000) >> 19
}

// H264.A_DB_BYPASS: Video A Deblocking bypass register
func (o *H264_Type) SetA_DB_BYPASS_A_BYPASS_DB_FILTER(value uint32) {
	volatile.StoreUint32(&o.A_DB_BYPASS.Reg, volatile.LoadUint32(&o.A_DB_BYPASS.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetA_DB_BYPASS_A_BYPASS_DB_FILTER() uint32 {
	return volatile.LoadUint32(&o.A_DB_BYPASS.Reg) & 0x1
}

// H264.A_ROI_REGION0: Video A H264 ROI region0 range configure register.
func (o *H264_Type) SetA_ROI_REGION0_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION0_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION0_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION0_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION0_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION0_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION0_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION0_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION0_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0.Reg, volatile.LoadUint32(&o.A_ROI_REGION0.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION0_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION0.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION1: Video A H264 ROI region1 range configure register.
func (o *H264_Type) SetA_ROI_REGION1_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION1_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION1_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION1_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION1_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION1_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION1_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION1_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION1_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION1.Reg, volatile.LoadUint32(&o.A_ROI_REGION1.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION1_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION1.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION2: Video A H264 ROI region2 range configure register.
func (o *H264_Type) SetA_ROI_REGION2_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION2_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION2_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION2_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION2_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION2_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION2_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION2_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION2_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION2.Reg, volatile.LoadUint32(&o.A_ROI_REGION2.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION2_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION2.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION3: Video A H264 ROI region3 range configure register.
func (o *H264_Type) SetA_ROI_REGION3_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION3_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION3_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION3_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION3_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION3_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION3_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION3_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION3_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION3.Reg, volatile.LoadUint32(&o.A_ROI_REGION3.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION3_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION3.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION4: Video A H264 ROI region4 range configure register.
func (o *H264_Type) SetA_ROI_REGION4_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION4_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION4_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION4_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION4_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION4_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION4_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION4_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION4_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4.Reg, volatile.LoadUint32(&o.A_ROI_REGION4.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION4_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION4.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION5: Video A H264 ROI region5 range configure register.
func (o *H264_Type) SetA_ROI_REGION5_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION5_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION5_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION5_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION5_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION5_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION5_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION5_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION5_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION5.Reg, volatile.LoadUint32(&o.A_ROI_REGION5.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION5_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION5.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION6: Video A H264 ROI region6 range configure register.
func (o *H264_Type) SetA_ROI_REGION6_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION6_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION6_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION6_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION6_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION6_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION6_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION6_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION6_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION6.Reg, volatile.LoadUint32(&o.A_ROI_REGION6.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION6_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION6.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION7: Video A H264 ROI region7 range configure register.
func (o *H264_Type) SetA_ROI_REGION7_X(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION7_X() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION7_Y(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION7_Y() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION7_X_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION7_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION7_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION7_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetA_ROI_REGION7_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION7.Reg, volatile.LoadUint32(&o.A_ROI_REGION7.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetA_ROI_REGION7_EN() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION7.Reg) & 0x10000000) >> 28
}

// H264.A_ROI_REGION0_3_QP: Video A H264 ROI region0, region1,region2,region3 QP register.
func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION0_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION0_QP() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION1_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION1_QP() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION2_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION2_QP() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION0_3_QP_A_ROI_REGION3_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION0_3_QP_A_ROI_REGION3_QP() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION0_3_QP.Reg) & 0xfe00000) >> 21
}

// H264.A_ROI_REGION4_7_QP: Video A H264 ROI region4, region5,region6,region7 QP register.
func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION4_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION4_QP() uint32 {
	return volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0x7f
}
func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION5_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION5_QP() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION6_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION6_QP() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetA_ROI_REGION4_7_QP_A_ROI_REGION7_QP(value uint32) {
	volatile.StoreUint32(&o.A_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetA_ROI_REGION4_7_QP_A_ROI_REGION7_QP() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_REGION4_7_QP.Reg) & 0xfe00000) >> 21
}

// H264.A_NO_ROI_REGION_QP_OFFSET: Video A H264 no roi region QP register.
func (o *H264_Type) SetA_NO_ROI_REGION_QP_OFFSET_A_NO_ROI_REGION_QP(value uint32) {
	volatile.StoreUint32(&o.A_NO_ROI_REGION_QP_OFFSET.Reg, volatile.LoadUint32(&o.A_NO_ROI_REGION_QP_OFFSET.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetA_NO_ROI_REGION_QP_OFFSET_A_NO_ROI_REGION_QP() uint32 {
	return volatile.LoadUint32(&o.A_NO_ROI_REGION_QP_OFFSET.Reg) & 0x7f
}

// H264.A_ROI_CONFIG: Video A H264 ROI configure register.
func (o *H264_Type) SetA_ROI_CONFIG_A_ROI_EN(value uint32) {
	volatile.StoreUint32(&o.A_ROI_CONFIG.Reg, volatile.LoadUint32(&o.A_ROI_CONFIG.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetA_ROI_CONFIG_A_ROI_EN() uint32 {
	return volatile.LoadUint32(&o.A_ROI_CONFIG.Reg) & 0x1
}
func (o *H264_Type) SetA_ROI_CONFIG_A_ROI_MODE(value uint32) {
	volatile.StoreUint32(&o.A_ROI_CONFIG.Reg, volatile.LoadUint32(&o.A_ROI_CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetA_ROI_CONFIG_A_ROI_MODE() uint32 {
	return (volatile.LoadUint32(&o.A_ROI_CONFIG.Reg) & 0x2) >> 1
}

// H264.B_SYS_MB_RES: Video B horizontal and vertical MB resolution register.
func (o *H264_Type) SetB_SYS_MB_RES_B_SYS_TOTAL_MB_Y(value uint32) {
	volatile.StoreUint32(&o.B_SYS_MB_RES.Reg, volatile.LoadUint32(&o.B_SYS_MB_RES.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_SYS_MB_RES_B_SYS_TOTAL_MB_Y() uint32 {
	return volatile.LoadUint32(&o.B_SYS_MB_RES.Reg) & 0x7f
}
func (o *H264_Type) SetB_SYS_MB_RES_B_SYS_TOTAL_MB_X(value uint32) {
	volatile.StoreUint32(&o.B_SYS_MB_RES.Reg, volatile.LoadUint32(&o.B_SYS_MB_RES.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_SYS_MB_RES_B_SYS_TOTAL_MB_X() uint32 {
	return (volatile.LoadUint32(&o.B_SYS_MB_RES.Reg) & 0x3f80) >> 7
}

// H264.B_SYS_CONF: Video B system level configuration register.
func (o *H264_Type) SetB_SYS_CONF_B_DB_TMP_READY_TRIGGER_MB_NUM(value uint32) {
	volatile.StoreUint32(&o.B_SYS_CONF.Reg, volatile.LoadUint32(&o.B_SYS_CONF.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_SYS_CONF_B_DB_TMP_READY_TRIGGER_MB_NUM() uint32 {
	return volatile.LoadUint32(&o.B_SYS_CONF.Reg) & 0x7f
}
func (o *H264_Type) SetB_SYS_CONF_B_REC_READY_TRIGGER_MB_LINES(value uint32) {
	volatile.StoreUint32(&o.B_SYS_CONF.Reg, volatile.LoadUint32(&o.B_SYS_CONF.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_SYS_CONF_B_REC_READY_TRIGGER_MB_LINES() uint32 {
	return (volatile.LoadUint32(&o.B_SYS_CONF.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_SYS_CONF_B_INTRA_COST_CMP_OFFSET(value uint32) {
	volatile.StoreUint32(&o.B_SYS_CONF.Reg, volatile.LoadUint32(&o.B_SYS_CONF.Reg)&^(0x3fffc000)|value<<14)
}
func (o *H264_Type) GetB_SYS_CONF_B_INTRA_COST_CMP_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.B_SYS_CONF.Reg) & 0x3fffc000) >> 14
}

// H264.B_DECI_SCORE: Video B luma and chroma MB decimate score Register.
func (o *H264_Type) SetB_DECI_SCORE_B_C_DECI_SCORE(value uint32) {
	volatile.StoreUint32(&o.B_DECI_SCORE.Reg, volatile.LoadUint32(&o.B_DECI_SCORE.Reg)&^(0x3ff)|value)
}
func (o *H264_Type) GetB_DECI_SCORE_B_C_DECI_SCORE() uint32 {
	return volatile.LoadUint32(&o.B_DECI_SCORE.Reg) & 0x3ff
}
func (o *H264_Type) SetB_DECI_SCORE_B_L_DECI_SCORE(value uint32) {
	volatile.StoreUint32(&o.B_DECI_SCORE.Reg, volatile.LoadUint32(&o.B_DECI_SCORE.Reg)&^(0xffc00)|value<<10)
}
func (o *H264_Type) GetB_DECI_SCORE_B_L_DECI_SCORE() uint32 {
	return (volatile.LoadUint32(&o.B_DECI_SCORE.Reg) & 0xffc00) >> 10
}

// H264.B_DECI_SCORE_OFFSET: Video B luma and chroma MB decimate score offset Register.
func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_I16X16_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0x3f)|value)
}
func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_I16X16_DECI_SCORE_OFFSET() uint32 {
	return volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0x3f
}
func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_I_CHROMA_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0xfc0)|value<<6)
}
func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_I_CHROMA_DECI_SCORE_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0xfc0) >> 6
}
func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_P16X16_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0x3f000)|value<<12)
}
func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_P16X16_DECI_SCORE_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0x3f000) >> 12
}
func (o *H264_Type) SetB_DECI_SCORE_OFFSET_B_P_CHROMA_DECI_SCORE_OFFSET(value uint32) {
	volatile.StoreUint32(&o.B_DECI_SCORE_OFFSET.Reg, volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg)&^(0xfc0000)|value<<18)
}
func (o *H264_Type) GetB_DECI_SCORE_OFFSET_B_P_CHROMA_DECI_SCORE_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.B_DECI_SCORE_OFFSET.Reg) & 0xfc0000) >> 18
}

// H264.B_RC_CONF0: Video B rate control configuration register0.
func (o *H264_Type) SetB_RC_CONF0_B_QP(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF0.Reg, volatile.LoadUint32(&o.B_RC_CONF0.Reg)&^(0x3f)|value)
}
func (o *H264_Type) GetB_RC_CONF0_B_QP() uint32 {
	return volatile.LoadUint32(&o.B_RC_CONF0.Reg) & 0x3f
}
func (o *H264_Type) SetB_RC_CONF0_B_RATE_CTRL_U(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF0.Reg, volatile.LoadUint32(&o.B_RC_CONF0.Reg)&^(0x3fffc0)|value<<6)
}
func (o *H264_Type) GetB_RC_CONF0_B_RATE_CTRL_U() uint32 {
	return (volatile.LoadUint32(&o.B_RC_CONF0.Reg) & 0x3fffc0) >> 6
}
func (o *H264_Type) SetB_RC_CONF0_B_MB_RATE_CTRL_EN(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF0.Reg, volatile.LoadUint32(&o.B_RC_CONF0.Reg)&^(0x400000)|value<<22)
}
func (o *H264_Type) GetB_RC_CONF0_B_MB_RATE_CTRL_EN() uint32 {
	return (volatile.LoadUint32(&o.B_RC_CONF0.Reg) & 0x400000) >> 22
}

// H264.B_RC_CONF1: Video B rate control configuration register1.
func (o *H264_Type) SetB_RC_CONF1_B_CHROMA_DC_QP_DELTA(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x7)|value)
}
func (o *H264_Type) GetB_RC_CONF1_B_CHROMA_DC_QP_DELTA() uint32 {
	return volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x7
}
func (o *H264_Type) SetB_RC_CONF1_B_CHROMA_QP_DELTA(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x78)|value<<3)
}
func (o *H264_Type) GetB_RC_CONF1_B_CHROMA_QP_DELTA() uint32 {
	return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x78) >> 3
}
func (o *H264_Type) SetB_RC_CONF1_B_QP_MIN(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x1f80)|value<<7)
}
func (o *H264_Type) GetB_RC_CONF1_B_QP_MIN() uint32 {
	return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x1f80) >> 7
}
func (o *H264_Type) SetB_RC_CONF1_B_QP_MAX(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x7e000)|value<<13)
}
func (o *H264_Type) GetB_RC_CONF1_B_QP_MAX() uint32 {
	return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x7e000) >> 13
}
func (o *H264_Type) SetB_RC_CONF1_B_MAD_FRAME_PRED(value uint32) {
	volatile.StoreUint32(&o.B_RC_CONF1.Reg, volatile.LoadUint32(&o.B_RC_CONF1.Reg)&^(0x7ff80000)|value<<19)
}
func (o *H264_Type) GetB_RC_CONF1_B_MAD_FRAME_PRED() uint32 {
	return (volatile.LoadUint32(&o.B_RC_CONF1.Reg) & 0x7ff80000) >> 19
}

// H264.B_DB_BYPASS: Video B Deblocking bypass register
func (o *H264_Type) SetB_DB_BYPASS_B_BYPASS_DB_FILTER(value uint32) {
	volatile.StoreUint32(&o.B_DB_BYPASS.Reg, volatile.LoadUint32(&o.B_DB_BYPASS.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetB_DB_BYPASS_B_BYPASS_DB_FILTER() uint32 {
	return volatile.LoadUint32(&o.B_DB_BYPASS.Reg) & 0x1
}

// H264.B_ROI_REGION0: Video B H264 ROI region0 range configure register.
func (o *H264_Type) SetB_ROI_REGION0_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION0_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION0_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION0_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION0_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION0_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION0_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION0_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION0_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0.Reg, volatile.LoadUint32(&o.B_ROI_REGION0.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION0_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION0.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION1: Video B H264 ROI region1 range configure register.
func (o *H264_Type) SetB_ROI_REGION1_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION1_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION1_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION1_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION1_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION1_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION1_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION1_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION1_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION1.Reg, volatile.LoadUint32(&o.B_ROI_REGION1.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION1_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION1.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION2: Video B H264 ROI region2 range configure register.
func (o *H264_Type) SetB_ROI_REGION2_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION2_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION2_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION2_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION2_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION2_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION2_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION2_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION2_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION2.Reg, volatile.LoadUint32(&o.B_ROI_REGION2.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION2_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION2.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION3: Video B H264 ROI region3 range configure register.
func (o *H264_Type) SetB_ROI_REGION3_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION3_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION3_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION3_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION3_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION3_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION3_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION3_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION3_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION3.Reg, volatile.LoadUint32(&o.B_ROI_REGION3.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION3_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION3.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION4: Video B H264 ROI region4 range configure register.
func (o *H264_Type) SetB_ROI_REGION4_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION4_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION4_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION4_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION4_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION4_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION4_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION4_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION4_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4.Reg, volatile.LoadUint32(&o.B_ROI_REGION4.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION4_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION4.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION5: Video B H264 ROI region5 range configure register.
func (o *H264_Type) SetB_ROI_REGION5_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION5_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION5_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION5_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION5_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION5_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION5_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION5_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION5_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION5.Reg, volatile.LoadUint32(&o.B_ROI_REGION5.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION5_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION5.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION6: Video B H264 ROI region6 range configure register.
func (o *H264_Type) SetB_ROI_REGION6_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION6_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION6_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION6_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION6_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION6_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION6_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION6_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION6_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION6.Reg, volatile.LoadUint32(&o.B_ROI_REGION6.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION6_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION6.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION7: Video B H264 ROI region7 range configure register.
func (o *H264_Type) SetB_ROI_REGION7_X(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION7_X() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION7_Y(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION7_Y() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION7_X_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION7_X_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION7_Y_LEN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION7_Y_LEN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0xfe00000) >> 21
}
func (o *H264_Type) SetB_ROI_REGION7_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION7.Reg, volatile.LoadUint32(&o.B_ROI_REGION7.Reg)&^(0x10000000)|value<<28)
}
func (o *H264_Type) GetB_ROI_REGION7_EN() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION7.Reg) & 0x10000000) >> 28
}

// H264.B_ROI_REGION0_3_QP: Video B H264 ROI region0, region1,region2,region3 QP register.
func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION0_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION0_QP() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION1_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION1_QP() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION2_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION2_QP() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION0_3_QP_B_ROI_REGION3_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION0_3_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION0_3_QP_B_ROI_REGION3_QP() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION0_3_QP.Reg) & 0xfe00000) >> 21
}

// H264.B_ROI_REGION4_7_QP: Video B H264 ROI region4, region5,region6,region7 QP register.
func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION4_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION4_QP() uint32 {
	return volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0x7f
}
func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION5_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0x3f80)|value<<7)
}
func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION5_QP() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0x3f80) >> 7
}
func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION6_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0x1fc000)|value<<14)
}
func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION6_QP() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0x1fc000) >> 14
}
func (o *H264_Type) SetB_ROI_REGION4_7_QP_B_ROI_REGION7_QP(value uint32) {
	volatile.StoreUint32(&o.B_ROI_REGION4_7_QP.Reg, volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg)&^(0xfe00000)|value<<21)
}
func (o *H264_Type) GetB_ROI_REGION4_7_QP_B_ROI_REGION7_QP() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_REGION4_7_QP.Reg) & 0xfe00000) >> 21
}

// H264.B_NO_ROI_REGION_QP_OFFSET: Video B H264 no roi region QP register.
func (o *H264_Type) SetB_NO_ROI_REGION_QP_OFFSET_B_NO_ROI_REGION_QP(value uint32) {
	volatile.StoreUint32(&o.B_NO_ROI_REGION_QP_OFFSET.Reg, volatile.LoadUint32(&o.B_NO_ROI_REGION_QP_OFFSET.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetB_NO_ROI_REGION_QP_OFFSET_B_NO_ROI_REGION_QP() uint32 {
	return volatile.LoadUint32(&o.B_NO_ROI_REGION_QP_OFFSET.Reg) & 0x7f
}

// H264.B_ROI_CONFIG: Video B H264 ROI configure register.
func (o *H264_Type) SetB_ROI_CONFIG_B_ROI_EN(value uint32) {
	volatile.StoreUint32(&o.B_ROI_CONFIG.Reg, volatile.LoadUint32(&o.B_ROI_CONFIG.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetB_ROI_CONFIG_B_ROI_EN() uint32 {
	return volatile.LoadUint32(&o.B_ROI_CONFIG.Reg) & 0x1
}
func (o *H264_Type) SetB_ROI_CONFIG_B_ROI_MODE(value uint32) {
	volatile.StoreUint32(&o.B_ROI_CONFIG.Reg, volatile.LoadUint32(&o.B_ROI_CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetB_ROI_CONFIG_B_ROI_MODE() uint32 {
	return (volatile.LoadUint32(&o.B_ROI_CONFIG.Reg) & 0x2) >> 1
}

// H264.RC_STATUS0: Rate control status register0.
func (o *H264_Type) SetRC_STATUS0_FRAME_MAD_SUM(value uint32) {
	volatile.StoreUint32(&o.RC_STATUS0.Reg, volatile.LoadUint32(&o.RC_STATUS0.Reg)&^(0x1fffff)|value)
}
func (o *H264_Type) GetRC_STATUS0_FRAME_MAD_SUM() uint32 {
	return volatile.LoadUint32(&o.RC_STATUS0.Reg) & 0x1fffff
}

// H264.RC_STATUS1: Rate control status register1.
func (o *H264_Type) SetRC_STATUS1_FRAME_ENC_BITS(value uint32) {
	volatile.StoreUint32(&o.RC_STATUS1.Reg, volatile.LoadUint32(&o.RC_STATUS1.Reg)&^(0x7ffffff)|value)
}
func (o *H264_Type) GetRC_STATUS1_FRAME_ENC_BITS() uint32 {
	return volatile.LoadUint32(&o.RC_STATUS1.Reg) & 0x7ffffff
}

// H264.RC_STATUS2: Rate control status register2.
func (o *H264_Type) SetRC_STATUS2_FRAME_QP_SUM(value uint32) {
	volatile.StoreUint32(&o.RC_STATUS2.Reg, volatile.LoadUint32(&o.RC_STATUS2.Reg)&^(0x7ffff)|value)
}
func (o *H264_Type) GetRC_STATUS2_FRAME_QP_SUM() uint32 {
	return volatile.LoadUint32(&o.RC_STATUS2.Reg) & 0x7ffff
}

// H264.SLICE_HEADER_REMAIN: Frame Slice Header remain bit register.
func (o *H264_Type) SetSLICE_HEADER_REMAIN_SLICE_REMAIN_BITLENGTH(value uint32) {
	volatile.StoreUint32(&o.SLICE_HEADER_REMAIN.Reg, volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg)&^(0x7)|value)
}
func (o *H264_Type) GetSLICE_HEADER_REMAIN_SLICE_REMAIN_BITLENGTH() uint32 {
	return volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg) & 0x7
}
func (o *H264_Type) SetSLICE_HEADER_REMAIN_SLICE_REMAIN_BIT(value uint32) {
	volatile.StoreUint32(&o.SLICE_HEADER_REMAIN.Reg, volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg)&^(0x7f8)|value<<3)
}
func (o *H264_Type) GetSLICE_HEADER_REMAIN_SLICE_REMAIN_BIT() uint32 {
	return (volatile.LoadUint32(&o.SLICE_HEADER_REMAIN.Reg) & 0x7f8) >> 3
}

// H264.SLICE_HEADER_BYTE_LENGTH: Frame Slice Header byte length register.
func (o *H264_Type) SetSLICE_HEADER_BYTE_LENGTH_SLICE_BYTE_LENGTH(value uint32) {
	volatile.StoreUint32(&o.SLICE_HEADER_BYTE_LENGTH.Reg, volatile.LoadUint32(&o.SLICE_HEADER_BYTE_LENGTH.Reg)&^(0xf)|value)
}
func (o *H264_Type) GetSLICE_HEADER_BYTE_LENGTH_SLICE_BYTE_LENGTH() uint32 {
	return volatile.LoadUint32(&o.SLICE_HEADER_BYTE_LENGTH.Reg) & 0xf
}

// H264.BS_THRESHOLD: Bitstream buffer overflow threshold register
func (o *H264_Type) SetBS_THRESHOLD_BS_BUFFER_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.BS_THRESHOLD.Reg, volatile.LoadUint32(&o.BS_THRESHOLD.Reg)&^(0x7f)|value)
}
func (o *H264_Type) GetBS_THRESHOLD_BS_BUFFER_THRESHOLD() uint32 {
	return volatile.LoadUint32(&o.BS_THRESHOLD.Reg) & 0x7f
}

// H264.SLICE_HEADER_BYTE0: Frame Slice Header byte low 32 bit register.
func (o *H264_Type) SetSLICE_HEADER_BYTE0(value uint32) {
	volatile.StoreUint32(&o.SLICE_HEADER_BYTE0.Reg, value)
}
func (o *H264_Type) GetSLICE_HEADER_BYTE0() uint32 {
	return volatile.LoadUint32(&o.SLICE_HEADER_BYTE0.Reg)
}

// H264.SLICE_HEADER_BYTE1: Frame Slice Header byte high 32 bit register.
func (o *H264_Type) SetSLICE_HEADER_BYTE1(value uint32) {
	volatile.StoreUint32(&o.SLICE_HEADER_BYTE1.Reg, value)
}
func (o *H264_Type) GetSLICE_HEADER_BYTE1() uint32 {
	return volatile.LoadUint32(&o.SLICE_HEADER_BYTE1.Reg)
}

// H264.INT_RAW: Interrupt raw status register
func (o *H264_Type) SetINT_RAW_DB_TMP_READY_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetINT_RAW_DB_TMP_READY_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *H264_Type) SetINT_RAW_REC_READY_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetINT_RAW_REC_READY_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *H264_Type) SetINT_RAW_FRAME_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetINT_RAW_FRAME_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetINT_RAW_DMA_MOVE_2MB_LINE_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetINT_RAW_DMA_MOVE_2MB_LINE_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}

// H264.INT_ST: Interrupt masked status register
func (o *H264_Type) SetINT_ST_DB_TMP_READY_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetINT_ST_DB_TMP_READY_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *H264_Type) SetINT_ST_REC_READY_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetINT_ST_REC_READY_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *H264_Type) SetINT_ST_FRAME_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetINT_ST_FRAME_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetINT_ST_DMA_MOVE_2MB_LINE_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetINT_ST_DMA_MOVE_2MB_LINE_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}

// H264.INT_ENA: Interrupt enable register
func (o *H264_Type) SetINT_ENA_DB_TMP_READY_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetINT_ENA_DB_TMP_READY_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *H264_Type) SetINT_ENA_REC_READY_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetINT_ENA_REC_READY_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *H264_Type) SetINT_ENA_FRAME_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetINT_ENA_FRAME_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetINT_ENA_DMA_MOVE_2MB_LINE_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetINT_ENA_DMA_MOVE_2MB_LINE_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}

// H264.INT_CLR: Interrupt clear register
func (o *H264_Type) SetINT_CLR_DB_TMP_READY_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetINT_CLR_DB_TMP_READY_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *H264_Type) SetINT_CLR_REC_READY_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetINT_CLR_REC_READY_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *H264_Type) SetINT_CLR_FRAME_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetINT_CLR_FRAME_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetINT_CLR_DMA_MOVE_2MB_LINE_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetINT_CLR_DMA_MOVE_2MB_LINE_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}

// H264.CONF: General configuration register.
func (o *H264_Type) SetCONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetCONF_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CONF.Reg) & 0x1
}
func (o *H264_Type) SetCONF_REC_RAM_CLK_EN2(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetCONF_REC_RAM_CLK_EN2() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1
}
func (o *H264_Type) SetCONF_REC_RAM_CLK_EN1(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetCONF_REC_RAM_CLK_EN1() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetCONF_QUANT_RAM_CLK_EN2(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetCONF_QUANT_RAM_CLK_EN2() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3
}
func (o *H264_Type) SetCONF_QUANT_RAM_CLK_EN1(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4)
}
func (o *H264_Type) GetCONF_QUANT_RAM_CLK_EN1() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4
}
func (o *H264_Type) SetCONF_PRE_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5)
}
func (o *H264_Type) GetCONF_PRE_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5
}
func (o *H264_Type) SetCONF_MVD_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6)
}
func (o *H264_Type) GetCONF_MVD_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6
}
func (o *H264_Type) SetCONF_MC_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7)
}
func (o *H264_Type) GetCONF_MC_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7
}
func (o *H264_Type) SetCONF_REF_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100)|value<<8)
}
func (o *H264_Type) GetCONF_REF_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x100) >> 8
}
func (o *H264_Type) SetCONF_I4X4_REF_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200)|value<<9)
}
func (o *H264_Type) GetCONF_I4X4_REF_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x200) >> 9
}
func (o *H264_Type) SetCONF_IME_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400)|value<<10)
}
func (o *H264_Type) GetCONF_IME_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x400) >> 10
}
func (o *H264_Type) SetCONF_FME_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800)|value<<11)
}
func (o *H264_Type) GetCONF_FME_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x800) >> 11
}
func (o *H264_Type) SetCONF_FETCH_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000)|value<<12)
}
func (o *H264_Type) GetCONF_FETCH_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000) >> 12
}
func (o *H264_Type) SetCONF_DB_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000)|value<<13)
}
func (o *H264_Type) GetCONF_DB_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000) >> 13
}
func (o *H264_Type) SetCONF_CUR_MB_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000)|value<<14)
}
func (o *H264_Type) GetCONF_CUR_MB_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000) >> 14
}
func (o *H264_Type) SetCONF_CAVLC_RAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000)|value<<15)
}
func (o *H264_Type) GetCONF_CAVLC_RAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000) >> 15
}
func (o *H264_Type) SetCONF_IME_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000)|value<<16)
}
func (o *H264_Type) GetCONF_IME_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000) >> 16
}
func (o *H264_Type) SetCONF_FME_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000)|value<<17)
}
func (o *H264_Type) GetCONF_FME_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000) >> 17
}
func (o *H264_Type) SetCONF_MC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000)|value<<18)
}
func (o *H264_Type) GetCONF_MC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000) >> 18
}
func (o *H264_Type) SetCONF_INTERPOLATOR_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000)|value<<19)
}
func (o *H264_Type) GetCONF_INTERPOLATOR_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000) >> 19
}
func (o *H264_Type) SetCONF_DB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100000)|value<<20)
}
func (o *H264_Type) GetCONF_DB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x100000) >> 20
}
func (o *H264_Type) SetCONF_CLAVLC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200000)|value<<21)
}
func (o *H264_Type) GetCONF_CLAVLC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x200000) >> 21
}
func (o *H264_Type) SetCONF_INTRA_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22)
}
func (o *H264_Type) GetCONF_INTRA_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22
}
func (o *H264_Type) SetCONF_DECI_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23)
}
func (o *H264_Type) GetCONF_DECI_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23
}
func (o *H264_Type) SetCONF_BS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_Type) GetCONF_BS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24
}
func (o *H264_Type) SetCONF_MV_MERGE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_Type) GetCONF_MV_MERGE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25
}

// H264.MV_MERGE_CONFIG: Mv merge configuration register.
func (o *H264_Type) SetMV_MERGE_CONFIG_MV_MERGE_TYPE(value uint32) {
	volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x3)|value)
}
func (o *H264_Type) GetMV_MERGE_CONFIG_MV_MERGE_TYPE() uint32 {
	return volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x3
}
func (o *H264_Type) SetMV_MERGE_CONFIG_INT_MV_OUT_EN(value uint32) {
	volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetMV_MERGE_CONFIG_INT_MV_OUT_EN() uint32 {
	return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetMV_MERGE_CONFIG_A_MV_MERGE_EN(value uint32) {
	volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetMV_MERGE_CONFIG_A_MV_MERGE_EN() uint32 {
	return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x8) >> 3
}
func (o *H264_Type) SetMV_MERGE_CONFIG_B_MV_MERGE_EN(value uint32) {
	volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x10)|value<<4)
}
func (o *H264_Type) GetMV_MERGE_CONFIG_B_MV_MERGE_EN() uint32 {
	return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x10) >> 4
}
func (o *H264_Type) SetMV_MERGE_CONFIG_MB_VALID_NUM(value uint32) {
	volatile.StoreUint32(&o.MV_MERGE_CONFIG.Reg, volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg)&^(0x3ffe0)|value<<5)
}
func (o *H264_Type) GetMV_MERGE_CONFIG_MB_VALID_NUM() uint32 {
	return (volatile.LoadUint32(&o.MV_MERGE_CONFIG.Reg) & 0x3ffe0) >> 5
}

// H264.DEBUG_DMA_SEL: Debug H264 DMA select register
func (o *H264_Type) SetDEBUG_DMA_SEL_DBG_DMA_SEL(value uint32) {
	volatile.StoreUint32(&o.DEBUG_DMA_SEL.Reg, volatile.LoadUint32(&o.DEBUG_DMA_SEL.Reg)&^(0xff)|value)
}
func (o *H264_Type) GetDEBUG_DMA_SEL_DBG_DMA_SEL() uint32 {
	return volatile.LoadUint32(&o.DEBUG_DMA_SEL.Reg) & 0xff
}

// H264.SYS_STATUS: System status register.
func (o *H264_Type) SetSYS_STATUS_FRAME_NUM(value uint32) {
	volatile.StoreUint32(&o.SYS_STATUS.Reg, volatile.LoadUint32(&o.SYS_STATUS.Reg)&^(0x1ff)|value)
}
func (o *H264_Type) GetSYS_STATUS_FRAME_NUM() uint32 {
	return volatile.LoadUint32(&o.SYS_STATUS.Reg) & 0x1ff
}
func (o *H264_Type) SetSYS_STATUS_DUAL_STREAM_SEL(value uint32) {
	volatile.StoreUint32(&o.SYS_STATUS.Reg, volatile.LoadUint32(&o.SYS_STATUS.Reg)&^(0x200)|value<<9)
}
func (o *H264_Type) GetSYS_STATUS_DUAL_STREAM_SEL() uint32 {
	return (volatile.LoadUint32(&o.SYS_STATUS.Reg) & 0x200) >> 9
}
func (o *H264_Type) SetSYS_STATUS_INTRA_FLAG(value uint32) {
	volatile.StoreUint32(&o.SYS_STATUS.Reg, volatile.LoadUint32(&o.SYS_STATUS.Reg)&^(0x400)|value<<10)
}
func (o *H264_Type) GetSYS_STATUS_INTRA_FLAG() uint32 {
	return (volatile.LoadUint32(&o.SYS_STATUS.Reg) & 0x400) >> 10
}

// H264.FRAME_CODE_LENGTH: Frame code byte length register.
func (o *H264_Type) SetFRAME_CODE_LENGTH(value uint32) {
	volatile.StoreUint32(&o.FRAME_CODE_LENGTH.Reg, volatile.LoadUint32(&o.FRAME_CODE_LENGTH.Reg)&^(0xffffff)|value)
}
func (o *H264_Type) GetFRAME_CODE_LENGTH() uint32 {
	return volatile.LoadUint32(&o.FRAME_CODE_LENGTH.Reg) & 0xffffff
}

// H264.DEBUG_INFO0: Debug information register0.
func (o *H264_Type) SetDEBUG_INFO0_TOP_CTRL_INTER_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0xf)|value)
}
func (o *H264_Type) GetDEBUG_INFO0_TOP_CTRL_INTER_DEBUG_STATE() uint32 {
	return volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0xf
}
func (o *H264_Type) SetDEBUG_INFO0_TOP_CTRL_INTRA_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x70)|value<<4)
}
func (o *H264_Type) GetDEBUG_INFO0_TOP_CTRL_INTRA_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x70) >> 4
}
func (o *H264_Type) SetDEBUG_INFO0_P_I_CMP_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x380)|value<<7)
}
func (o *H264_Type) GetDEBUG_INFO0_P_I_CMP_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x380) >> 7
}
func (o *H264_Type) SetDEBUG_INFO0_MVD_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x1c00)|value<<10)
}
func (o *H264_Type) GetDEBUG_INFO0_MVD_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x1c00) >> 10
}
func (o *H264_Type) SetDEBUG_INFO0_MC_CHROMA_IP_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x2000)|value<<13)
}
func (o *H264_Type) GetDEBUG_INFO0_MC_CHROMA_IP_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x2000) >> 13
}
func (o *H264_Type) SetDEBUG_INFO0_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x3c000)|value<<14)
}
func (o *H264_Type) GetDEBUG_INFO0_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x3c000) >> 14
}
func (o *H264_Type) SetDEBUG_INFO0_INTRA_4X4_CTRL_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x3c0000)|value<<18)
}
func (o *H264_Type) GetDEBUG_INFO0_INTRA_4X4_CTRL_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x3c0000) >> 18
}
func (o *H264_Type) SetDEBUG_INFO0_INTRA_TOP_CTRL_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0x1c00000)|value<<22)
}
func (o *H264_Type) GetDEBUG_INFO0_INTRA_TOP_CTRL_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0x1c00000) >> 22
}
func (o *H264_Type) SetDEBUG_INFO0_IME_CTRL_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO0.Reg, volatile.LoadUint32(&o.DEBUG_INFO0.Reg)&^(0xe000000)|value<<25)
}
func (o *H264_Type) GetDEBUG_INFO0_IME_CTRL_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO0.Reg) & 0xe000000) >> 25
}

// H264.DEBUG_INFO1: Debug information register1.
func (o *H264_Type) SetDEBUG_INFO1_FME_CTRL_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x7)|value)
}
func (o *H264_Type) GetDEBUG_INFO1_FME_CTRL_DEBUG_STATE() uint32 {
	return volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x7
}
func (o *H264_Type) SetDEBUG_INFO1_DECI_CALC_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x18)|value<<3)
}
func (o *H264_Type) GetDEBUG_INFO1_DECI_CALC_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x18) >> 3
}
func (o *H264_Type) SetDEBUG_INFO1_DB_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0xe0)|value<<5)
}
func (o *H264_Type) GetDEBUG_INFO1_DB_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0xe0) >> 5
}
func (o *H264_Type) SetDEBUG_INFO1_CAVLC_ENC_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0xf00)|value<<8)
}
func (o *H264_Type) GetDEBUG_INFO1_CAVLC_ENC_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0xf00) >> 8
}
func (o *H264_Type) SetDEBUG_INFO1_CAVLC_SCAN_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0xf000)|value<<12)
}
func (o *H264_Type) GetDEBUG_INFO1_CAVLC_SCAN_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0xf000) >> 12
}
func (o *H264_Type) SetDEBUG_INFO1_CAVLC_CTRL_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x30000)|value<<16)
}
func (o *H264_Type) GetDEBUG_INFO1_CAVLC_CTRL_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x30000) >> 16
}
func (o *H264_Type) SetDEBUG_INFO1_BS_BUFFER_DEBUG_STATE(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO1.Reg, volatile.LoadUint32(&o.DEBUG_INFO1.Reg)&^(0x40000)|value<<18)
}
func (o *H264_Type) GetDEBUG_INFO1_BS_BUFFER_DEBUG_STATE() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO1.Reg) & 0x40000) >> 18
}

// H264.DEBUG_INFO2: Debug information register2.
func (o *H264_Type) SetDEBUG_INFO2_P_RC_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x1)|value)
}
func (o *H264_Type) GetDEBUG_INFO2_P_RC_DONE_DEBUG_FLAG() uint32 {
	return volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x1
}
func (o *H264_Type) SetDEBUG_INFO2_P_P_I_CMP_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x2)|value<<1)
}
func (o *H264_Type) GetDEBUG_INFO2_P_P_I_CMP_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x2) >> 1
}
func (o *H264_Type) SetDEBUG_INFO2_P_MV_MERGE_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x4)|value<<2)
}
func (o *H264_Type) GetDEBUG_INFO2_P_MV_MERGE_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x4) >> 2
}
func (o *H264_Type) SetDEBUG_INFO2_P_MOVE_ORI_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x8)|value<<3)
}
func (o *H264_Type) GetDEBUG_INFO2_P_MOVE_ORI_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x8) >> 3
}
func (o *H264_Type) SetDEBUG_INFO2_P_MC_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x10)|value<<4)
}
func (o *H264_Type) GetDEBUG_INFO2_P_MC_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x10) >> 4
}
func (o *H264_Type) SetDEBUG_INFO2_P_IME_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x20)|value<<5)
}
func (o *H264_Type) GetDEBUG_INFO2_P_IME_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x20) >> 5
}
func (o *H264_Type) SetDEBUG_INFO2_P_GET_ORI_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x40)|value<<6)
}
func (o *H264_Type) GetDEBUG_INFO2_P_GET_ORI_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x40) >> 6
}
func (o *H264_Type) SetDEBUG_INFO2_P_FME_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x80)|value<<7)
}
func (o *H264_Type) GetDEBUG_INFO2_P_FME_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x80) >> 7
}
func (o *H264_Type) SetDEBUG_INFO2_P_FETCH_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x100)|value<<8)
}
func (o *H264_Type) GetDEBUG_INFO2_P_FETCH_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x100) >> 8
}
func (o *H264_Type) SetDEBUG_INFO2_P_DB_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x200)|value<<9)
}
func (o *H264_Type) GetDEBUG_INFO2_P_DB_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x200) >> 9
}
func (o *H264_Type) SetDEBUG_INFO2_P_BS_BUF_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x400)|value<<10)
}
func (o *H264_Type) GetDEBUG_INFO2_P_BS_BUF_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x400) >> 10
}
func (o *H264_Type) SetDEBUG_INFO2_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x800)|value<<11)
}
func (o *H264_Type) GetDEBUG_INFO2_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x800) >> 11
}
func (o *H264_Type) SetDEBUG_INFO2_I_P_I_CMP_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x1000)|value<<12)
}
func (o *H264_Type) GetDEBUG_INFO2_I_P_I_CMP_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x1000) >> 12
}
func (o *H264_Type) SetDEBUG_INFO2_I_MOVE_ORI_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x2000)|value<<13)
}
func (o *H264_Type) GetDEBUG_INFO2_I_MOVE_ORI_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x2000) >> 13
}
func (o *H264_Type) SetDEBUG_INFO2_I_GET_ORI_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x4000)|value<<14)
}
func (o *H264_Type) GetDEBUG_INFO2_I_GET_ORI_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x4000) >> 14
}
func (o *H264_Type) SetDEBUG_INFO2_I_EC_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x8000)|value<<15)
}
func (o *H264_Type) GetDEBUG_INFO2_I_EC_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x8000) >> 15
}
func (o *H264_Type) SetDEBUG_INFO2_I_DB_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x10000)|value<<16)
}
func (o *H264_Type) GetDEBUG_INFO2_I_DB_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x10000) >> 16
}
func (o *H264_Type) SetDEBUG_INFO2_I_BS_BUF_DONE_DEBUG_FLAG(value uint32) {
	volatile.StoreUint32(&o.DEBUG_INFO2.Reg, volatile.LoadUint32(&o.DEBUG_INFO2.Reg)&^(0x20000)|value<<17)
}
func (o *H264_Type) GetDEBUG_INFO2_I_BS_BUF_DONE_DEBUG_FLAG() uint32 {
	return (volatile.LoadUint32(&o.DEBUG_INFO2.Reg) & 0x20000) >> 17
}

// H264.DATE: Version control register
func (o *H264_Type) SetDATE_LEDC_DATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *H264_Type) GetDATE_LEDC_DATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// H264 Encoder (DMA)
type H264_DMA_Type struct {
	OUT_CONF0_CH0           volatile.Register32 // 0x0
	OUT_INT_RAW_CH0         volatile.Register32 // 0x4
	OUT_INT_ENA_CH0         volatile.Register32 // 0x8
	OUT_INT_ST_CH0          volatile.Register32 // 0xC
	OUT_INT_CLR_CH0         volatile.Register32 // 0x10
	OUTFIFO_STATUS_CH0      volatile.Register32 // 0x14
	OUT_PUSH_CH0            volatile.Register32 // 0x18
	OUT_LINK_CONF_CH0       volatile.Register32 // 0x1C
	OUT_LINK_ADDR_CH0       volatile.Register32 // 0x20
	OUT_STATE_CH0           volatile.Register32 // 0x24
	OUT_EOF_DES_ADDR_CH0    volatile.Register32 // 0x28
	OUT_DSCR_CH0            volatile.Register32 // 0x2C
	OUT_DSCR_BF0_CH0        volatile.Register32 // 0x30
	OUT_DSCR_BF1_CH0        volatile.Register32 // 0x34
	_                       [4]byte
	OUT_ARB_CH0             volatile.Register32 // 0x3C
	OUT_RO_STATUS_CH0       volatile.Register32 // 0x40
	OUT_RO_PD_CONF_CH0      volatile.Register32 // 0x44
	_                       [8]byte
	OUT_MODE_ENABLE_CH0     volatile.Register32 // 0x50
	OUT_MODE_YUV_CH0        volatile.Register32 // 0x54
	_                       [16]byte
	OUT_ETM_CONF_CH0        volatile.Register32 // 0x68
	_                       [4]byte
	OUT_BUF_LEN_CH0         volatile.Register32 // 0x70
	OUT_FIFO_BCNT_CH0       volatile.Register32 // 0x74
	OUT_PUSH_BYTECNT_CH0    volatile.Register32 // 0x78
	OUT_XADDR_CH0           volatile.Register32 // 0x7C
	_                       [128]byte
	OUT_CONF0_CH1           volatile.Register32 // 0x100
	OUT_INT_RAW_CH1         volatile.Register32 // 0x104
	OUT_INT_ENA_CH1         volatile.Register32 // 0x108
	OUT_INT_ST_CH1          volatile.Register32 // 0x10C
	OUT_INT_CLR_CH1         volatile.Register32 // 0x110
	OUTFIFO_STATUS_CH1      volatile.Register32 // 0x114
	OUT_PUSH_CH1            volatile.Register32 // 0x118
	OUT_LINK_CONF_CH1       volatile.Register32 // 0x11C
	OUT_LINK_ADDR_CH1       volatile.Register32 // 0x120
	OUT_STATE_CH1           volatile.Register32 // 0x124
	OUT_EOF_DES_ADDR_CH1    volatile.Register32 // 0x128
	OUT_DSCR_CH1            volatile.Register32 // 0x12C
	OUT_DSCR_BF0_CH1        volatile.Register32 // 0x130
	OUT_DSCR_BF1_CH1        volatile.Register32 // 0x134
	_                       [4]byte
	OUT_ARB_CH1             volatile.Register32 // 0x13C
	_                       [40]byte
	OUT_ETM_CONF_CH1        volatile.Register32 // 0x168
	_                       [4]byte
	OUT_BUF_LEN_CH1         volatile.Register32 // 0x170
	OUT_FIFO_BCNT_CH1       volatile.Register32 // 0x174
	OUT_PUSH_BYTECNT_CH1    volatile.Register32 // 0x178
	OUT_XADDR_CH1           volatile.Register32 // 0x17C
	_                       [128]byte
	OUT_CONF0_CH2           volatile.Register32 // 0x200
	OUT_INT_RAW_CH2         volatile.Register32 // 0x204
	OUT_INT_ENA_CH2         volatile.Register32 // 0x208
	OUT_INT_ST_CH2          volatile.Register32 // 0x20C
	OUT_INT_CLR_CH2         volatile.Register32 // 0x210
	OUTFIFO_STATUS_CH2      volatile.Register32 // 0x214
	OUT_PUSH_CH2            volatile.Register32 // 0x218
	OUT_LINK_CONF_CH2       volatile.Register32 // 0x21C
	OUT_LINK_ADDR_CH2       volatile.Register32 // 0x220
	OUT_STATE_CH2           volatile.Register32 // 0x224
	OUT_EOF_DES_ADDR_CH2    volatile.Register32 // 0x228
	OUT_DSCR_CH2            volatile.Register32 // 0x22C
	OUT_DSCR_BF0_CH2        volatile.Register32 // 0x230
	OUT_DSCR_BF1_CH2        volatile.Register32 // 0x234
	_                       [4]byte
	OUT_ARB_CH2             volatile.Register32 // 0x23C
	_                       [40]byte
	OUT_ETM_CONF_CH2        volatile.Register32 // 0x268
	_                       [4]byte
	OUT_BUF_LEN_CH2         volatile.Register32 // 0x270
	OUT_FIFO_BCNT_CH2       volatile.Register32 // 0x274
	OUT_PUSH_BYTECNT_CH2    volatile.Register32 // 0x278
	OUT_XADDR_CH2           volatile.Register32 // 0x27C
	_                       [128]byte
	OUT_CONF0_CH3           volatile.Register32 // 0x300
	OUT_INT_RAW_CH3         volatile.Register32 // 0x304
	OUT_INT_ENA_CH3         volatile.Register32 // 0x308
	OUT_INT_ST_CH3          volatile.Register32 // 0x30C
	OUT_INT_CLR_CH3         volatile.Register32 // 0x310
	OUTFIFO_STATUS_CH3      volatile.Register32 // 0x314
	OUT_PUSH_CH3            volatile.Register32 // 0x318
	OUT_LINK_CONF_CH3       volatile.Register32 // 0x31C
	OUT_LINK_ADDR_CH3       volatile.Register32 // 0x320
	OUT_STATE_CH3           volatile.Register32 // 0x324
	OUT_EOF_DES_ADDR_CH3    volatile.Register32 // 0x328
	OUT_DSCR_CH3            volatile.Register32 // 0x32C
	OUT_DSCR_BF0_CH3        volatile.Register32 // 0x330
	OUT_DSCR_BF1_CH3        volatile.Register32 // 0x334
	_                       [4]byte
	OUT_ARB_CH3             volatile.Register32 // 0x33C
	_                       [40]byte
	OUT_ETM_CONF_CH3        volatile.Register32 // 0x368
	_                       [4]byte
	OUT_BUF_LEN_CH3         volatile.Register32 // 0x370
	OUT_FIFO_BCNT_CH3       volatile.Register32 // 0x374
	OUT_PUSH_BYTECNT_CH3    volatile.Register32 // 0x378
	OUT_XADDR_CH3           volatile.Register32 // 0x37C
	OUT_BLOCK_BUF_LEN_CH3   volatile.Register32 // 0x380
	_                       [124]byte
	OUT_CONF0_CH4           volatile.Register32 // 0x400
	OUT_INT_RAW_CH4         volatile.Register32 // 0x404
	OUT_INT_ENA_CH4         volatile.Register32 // 0x408
	OUT_INT_ST_CH4          volatile.Register32 // 0x40C
	OUT_INT_CLR_CH4         volatile.Register32 // 0x410
	OUTFIFO_STATUS_CH4      volatile.Register32 // 0x414
	OUT_PUSH_CH4            volatile.Register32 // 0x418
	OUT_LINK_CONF_CH4       volatile.Register32 // 0x41C
	OUT_LINK_ADDR_CH4       volatile.Register32 // 0x420
	OUT_STATE_CH4           volatile.Register32 // 0x424
	OUT_EOF_DES_ADDR_CH4    volatile.Register32 // 0x428
	OUT_DSCR_CH4            volatile.Register32 // 0x42C
	OUT_DSCR_BF0_CH4        volatile.Register32 // 0x430
	OUT_DSCR_BF1_CH4        volatile.Register32 // 0x434
	_                       [4]byte
	OUT_ARB_CH4             volatile.Register32 // 0x43C
	_                       [40]byte
	OUT_ETM_CONF_CH4        volatile.Register32 // 0x468
	_                       [4]byte
	OUT_BUF_LEN_CH4         volatile.Register32 // 0x470
	OUT_FIFO_BCNT_CH4       volatile.Register32 // 0x474
	OUT_PUSH_BYTECNT_CH4    volatile.Register32 // 0x478
	OUT_XADDR_CH4           volatile.Register32 // 0x47C
	OUT_BLOCK_BUF_LEN_CH4   volatile.Register32 // 0x480
	_                       [124]byte
	IN_CONF0_CH0            volatile.Register32 // 0x500
	IN_INT_RAW_CH0          volatile.Register32 // 0x504
	IN_INT_ENA_CH0          volatile.Register32 // 0x508
	IN_INT_ST_CH0           volatile.Register32 // 0x50C
	IN_INT_CLR_CH0          volatile.Register32 // 0x510
	INFIFO_STATUS_CH0       volatile.Register32 // 0x514
	IN_POP_CH0              volatile.Register32 // 0x518
	IN_LINK_CONF_CH0        volatile.Register32 // 0x51C
	IN_LINK_ADDR_CH0        volatile.Register32 // 0x520
	IN_STATE_CH0            volatile.Register32 // 0x524
	IN_SUC_EOF_DES_ADDR_CH0 volatile.Register32 // 0x528
	IN_ERR_EOF_DES_ADDR_CH0 volatile.Register32 // 0x52C
	IN_DSCR_CH0             volatile.Register32 // 0x530
	IN_DSCR_BF0_CH0         volatile.Register32 // 0x534
	IN_DSCR_BF1_CH0         volatile.Register32 // 0x538
	_                       [4]byte
	IN_ARB_CH0              volatile.Register32 // 0x540
	_                       [4]byte
	IN_RO_PD_CONF_CH0       volatile.Register32 // 0x548
	_                       [32]byte
	IN_ETM_CONF_CH0         volatile.Register32 // 0x56C
	_                       [16]byte
	IN_FIFO_CNT_CH0         volatile.Register32 // 0x580
	IN_POP_DATA_CNT_CH0     volatile.Register32 // 0x584
	IN_XADDR_CH0            volatile.Register32 // 0x588
	IN_BUF_HB_RCV_CH0       volatile.Register32 // 0x58C
	_                       [112]byte
	IN_CONF0_CH1            volatile.Register32 // 0x600
	IN_INT_RAW_CH1          volatile.Register32 // 0x604
	IN_INT_ENA_CH1          volatile.Register32 // 0x608
	IN_INT_ST_CH1           volatile.Register32 // 0x60C
	IN_INT_CLR_CH1          volatile.Register32 // 0x610
	INFIFO_STATUS_CH1       volatile.Register32 // 0x614
	IN_POP_CH1              volatile.Register32 // 0x618
	IN_LINK_CONF_CH1        volatile.Register32 // 0x61C
	IN_LINK_ADDR_CH1        volatile.Register32 // 0x620
	IN_STATE_CH1            volatile.Register32 // 0x624
	IN_SUC_EOF_DES_ADDR_CH1 volatile.Register32 // 0x628
	IN_ERR_EOF_DES_ADDR_CH1 volatile.Register32 // 0x62C
	IN_DSCR_CH1             volatile.Register32 // 0x630
	IN_DSCR_BF0_CH1         volatile.Register32 // 0x634
	IN_DSCR_BF1_CH1         volatile.Register32 // 0x638
	_                       [4]byte
	IN_ARB_CH1              volatile.Register32 // 0x640
	_                       [4]byte
	IN_ETM_CONF_CH1         volatile.Register32 // 0x648
	_                       [52]byte
	IN_FIFO_CNT_CH1         volatile.Register32 // 0x680
	IN_POP_DATA_CNT_CH1     volatile.Register32 // 0x684
	IN_XADDR_CH1            volatile.Register32 // 0x688
	IN_BUF_HB_RCV_CH1       volatile.Register32 // 0x68C
	_                       [112]byte
	IN_CONF0_CH2            volatile.Register32 // 0x700
	IN_INT_RAW_CH2          volatile.Register32 // 0x704
	IN_INT_ENA_CH2          volatile.Register32 // 0x708
	IN_INT_ST_CH2           volatile.Register32 // 0x70C
	IN_INT_CLR_CH2          volatile.Register32 // 0x710
	INFIFO_STATUS_CH2       volatile.Register32 // 0x714
	IN_POP_CH2              volatile.Register32 // 0x718
	IN_LINK_CONF_CH2        volatile.Register32 // 0x71C
	IN_LINK_ADDR_CH2        volatile.Register32 // 0x720
	IN_STATE_CH2            volatile.Register32 // 0x724
	IN_SUC_EOF_DES_ADDR_CH2 volatile.Register32 // 0x728
	IN_ERR_EOF_DES_ADDR_CH2 volatile.Register32 // 0x72C
	IN_DSCR_CH2             volatile.Register32 // 0x730
	IN_DSCR_BF0_CH2         volatile.Register32 // 0x734
	IN_DSCR_BF1_CH2         volatile.Register32 // 0x738
	_                       [4]byte
	IN_ARB_CH2              volatile.Register32 // 0x740
	_                       [4]byte
	IN_ETM_CONF_CH2         volatile.Register32 // 0x748
	_                       [52]byte
	IN_FIFO_CNT_CH2         volatile.Register32 // 0x780
	IN_POP_DATA_CNT_CH2     volatile.Register32 // 0x784
	IN_XADDR_CH2            volatile.Register32 // 0x788
	IN_BUF_HB_RCV_CH2       volatile.Register32 // 0x78C
	_                       [112]byte
	IN_CONF0_CH3            volatile.Register32 // 0x800
	IN_INT_RAW_CH3          volatile.Register32 // 0x804
	IN_INT_ENA_CH3          volatile.Register32 // 0x808
	IN_INT_ST_CH3           volatile.Register32 // 0x80C
	IN_INT_CLR_CH3          volatile.Register32 // 0x810
	INFIFO_STATUS_CH3       volatile.Register32 // 0x814
	IN_POP_CH3              volatile.Register32 // 0x818
	IN_LINK_CONF_CH3        volatile.Register32 // 0x81C
	IN_LINK_ADDR_CH3        volatile.Register32 // 0x820
	IN_STATE_CH3            volatile.Register32 // 0x824
	IN_SUC_EOF_DES_ADDR_CH3 volatile.Register32 // 0x828
	IN_ERR_EOF_DES_ADDR_CH3 volatile.Register32 // 0x82C
	IN_DSCR_CH3             volatile.Register32 // 0x830
	IN_DSCR_BF0_CH3         volatile.Register32 // 0x834
	IN_DSCR_BF1_CH3         volatile.Register32 // 0x838
	_                       [4]byte
	IN_ARB_CH3              volatile.Register32 // 0x840
	_                       [4]byte
	IN_ETM_CONF_CH3         volatile.Register32 // 0x848
	_                       [52]byte
	IN_FIFO_CNT_CH3         volatile.Register32 // 0x880
	IN_POP_DATA_CNT_CH3     volatile.Register32 // 0x884
	IN_XADDR_CH3            volatile.Register32 // 0x888
	IN_BUF_HB_RCV_CH3       volatile.Register32 // 0x88C
	_                       [112]byte
	IN_CONF0_CH4            volatile.Register32 // 0x900
	IN_INT_RAW_CH4          volatile.Register32 // 0x904
	IN_INT_ENA_CH4          volatile.Register32 // 0x908
	IN_INT_ST_CH4           volatile.Register32 // 0x90C
	IN_INT_CLR_CH4          volatile.Register32 // 0x910
	INFIFO_STATUS_CH4       volatile.Register32 // 0x914
	IN_POP_CH4              volatile.Register32 // 0x918
	IN_LINK_CONF_CH4        volatile.Register32 // 0x91C
	IN_LINK_ADDR_CH4        volatile.Register32 // 0x920
	IN_STATE_CH4            volatile.Register32 // 0x924
	IN_SUC_EOF_DES_ADDR_CH4 volatile.Register32 // 0x928
	IN_ERR_EOF_DES_ADDR_CH4 volatile.Register32 // 0x92C
	IN_DSCR_CH4             volatile.Register32 // 0x930
	IN_DSCR_BF0_CH4         volatile.Register32 // 0x934
	IN_DSCR_BF1_CH4         volatile.Register32 // 0x938
	_                       [4]byte
	IN_ARB_CH4              volatile.Register32 // 0x940
	_                       [4]byte
	IN_ETM_CONF_CH4         volatile.Register32 // 0x948
	_                       [52]byte
	IN_FIFO_CNT_CH4         volatile.Register32 // 0x980
	IN_POP_DATA_CNT_CH4     volatile.Register32 // 0x984
	IN_XADDR_CH4            volatile.Register32 // 0x988
	IN_BUF_HB_RCV_CH4       volatile.Register32 // 0x98C
	_                       [112]byte
	IN_CONF0_CH5            volatile.Register32 // 0xA00
	IN_CONF1_CH5            volatile.Register32 // 0xA04
	IN_CONF2_CH5            volatile.Register32 // 0xA08
	IN_CONF3_CH5            volatile.Register32 // 0xA0C
	IN_INT_RAW_CH5          volatile.Register32 // 0xA10
	IN_INT_ENA_CH5          volatile.Register32 // 0xA14
	IN_INT_ST_CH5           volatile.Register32 // 0xA18
	IN_INT_CLR_CH5          volatile.Register32 // 0xA1C
	INFIFO_STATUS_CH5       volatile.Register32 // 0xA20
	IN_POP_CH5              volatile.Register32 // 0xA24
	IN_STATE_CH5            volatile.Register32 // 0xA28
	_                       [20]byte
	IN_ARB_CH5              volatile.Register32 // 0xA40
	_                       [60]byte
	IN_FIFO_CNT_CH5         volatile.Register32 // 0xA80
	IN_POP_DATA_CNT_CH5     volatile.Register32 // 0xA84
	IN_XADDR_CH5            volatile.Register32 // 0xA88
	IN_BUF_HB_RCV_CH5       volatile.Register32 // 0xA8C
	_                       [112]byte
	INTER_AXI_ERR           volatile.Register32 // 0xB00
	EXTER_AXI_ERR           volatile.Register32 // 0xB04
	RST_CONF                volatile.Register32 // 0xB08
	INTER_MEM_START_ADDR0   volatile.Register32 // 0xB0C
	INTER_MEM_END_ADDR0     volatile.Register32 // 0xB10
	INTER_MEM_START_ADDR1   volatile.Register32 // 0xB14
	INTER_MEM_END_ADDR1     volatile.Register32 // 0xB18
	_                       [4]byte
	EXTER_MEM_START_ADDR0   volatile.Register32 // 0xB20
	EXTER_MEM_END_ADDR0     volatile.Register32 // 0xB24
	EXTER_MEM_START_ADDR1   volatile.Register32 // 0xB28
	EXTER_MEM_END_ADDR1     volatile.Register32 // 0xB2C
	OUT_ARB_CONFIG          volatile.Register32 // 0xB30
	IN_ARB_CONFIG           volatile.Register32 // 0xB34
	_                       [4]byte
	DATE                    volatile.Register32 // 0xB3C
	_                       [16]byte
	COUNTER_RST             volatile.Register32 // 0xB50
	RX_CH0_COUNTER          volatile.Register32 // 0xB54
	RX_CH1_COUNTER          volatile.Register32 // 0xB58
	RX_CH2_COUNTER          volatile.Register32 // 0xB5C
	RX_CH5_COUNTER          volatile.Register32 // 0xB60
}

// H264_DMA.OUT_CONF0_CH0: TX CH0 config0 register
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_EOF_MODE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_EOF_MODE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_ECC_AES_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_ECC_AES_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_CHECK_OWNER_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_CHECK_OWNER_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_MEM_BURST_LENGTH_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_MEM_BURST_LENGTH_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_PAGE_BOUND_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_PAGE_BOUND_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_REORDER_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_REORDER_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_CMD_DISABLE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH0_OUT_ARB_WEIGHT_OPT_DIS_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH0.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH0_OUT_ARB_WEIGHT_OPT_DIS_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH0.Reg) & 0x4000000) >> 26
}

// H264_DMA.OUT_INT_RAW_CH0: TX CH0 interrupt raw register
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DONE_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DONE_CH0_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_EOF_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_EOF_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_ERR_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_L1_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_L1_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_L1_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_L1_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_OVF_L2_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_OVF_L2_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUTFIFO_UDF_L2_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUTFIFO_UDF_L2_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH0_OUT_DSCR_TASK_OVF_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH0_OUT_DSCR_TASK_OVF_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH0.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ENA_CH0: TX CH0 interrupt ena register
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DONE_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DONE_CH0_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_EOF_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_EOF_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_ERR_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_L1_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_L1_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_L1_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_L1_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_OVF_L2_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_OVF_L2_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUTFIFO_UDF_L2_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUTFIFO_UDF_L2_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH0.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ST_CH0: TX CH0 interrupt st register
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_DONE_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_DONE_CH0_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_EOF_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_EOF_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_ERR_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_TOTAL_EOF_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_L1_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_L1_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_L1_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_L1_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_OVF_L2_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_OVF_L2_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUTFIFO_UDF_L2_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUTFIFO_UDF_L2_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH0.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_CLR_CH0: TX CH0 interrupt clr register
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DONE_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DONE_CH0_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_EOF_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_EOF_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_ERR_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_L1_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_L1_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_L1_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_L1_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_OVF_L2_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_OVF_L2_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUTFIFO_UDF_L2_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUTFIFO_UDF_L2_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH0_OUT_DSCR_TASK_OVF_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH0_OUT_DSCR_TASK_OVF_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH0.Reg) & 0x100) >> 8
}

// H264_DMA.OUTFIFO_STATUS_CH0: TX CH0 outfifo status register
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2_CH0() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3_CH0(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH0.Reg) & 0xc0000) >> 18
}

// H264_DMA.OUT_PUSH_CH0: TX CH0 outfifo push register
func (o *H264_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_WDATA_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_WDATA_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x3ff
}
func (o *H264_DMA_Type) SetOUT_PUSH_CH0_OUTFIFO_PUSH_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg)&^(0x400)|value<<10)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH0_OUTFIFO_PUSH_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH0.Reg) & 0x400) >> 10
}

// H264_DMA.OUT_LINK_CONF_CH0: TX CH0 out_link dscr ctrl register
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_STOP_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_STOP_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_START_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_START_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_RESTART_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_RESTART_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH0_OUTLINK_PARK_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH0_OUTLINK_PARK_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH0.Reg) & 0x800000) >> 23
}

// H264_DMA.OUT_LINK_ADDR_CH0: TX CH0 out_link dscr addr register
func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH0.Reg)
}

// H264_DMA.OUT_STATE_CH0: TX CH0 state register
func (o *H264_DMA_Type) SetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetOUT_STATE_CH0_OUT_DSCR_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH0_OUT_DSCR_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetOUT_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0xf00000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0xf00000) >> 20
}
func (o *H264_DMA_Type) SetOUT_STATE_CH0_OUT_RESET_AVAIL_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH0.Reg, volatile.LoadUint32(&o.OUT_STATE_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH0_OUT_RESET_AVAIL_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH0.Reg) & 0x1000000) >> 24
}

// H264_DMA.OUT_EOF_DES_ADDR_CH0: TX CH0 eof des addr register
func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH0.Reg)
}

// H264_DMA.OUT_DSCR_CH0: TX CH0 next dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH0.Reg)
}

// H264_DMA.OUT_DSCR_BF0_CH0: TX CH0 last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH0.Reg)
}

// H264_DMA.OUT_DSCR_BF1_CH0: TX CH0 second-to-last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH0.Reg)
}

// H264_DMA.OUT_ARB_CH0: TX CH0 arb register
func (o *H264_DMA_Type) SetOUT_ARB_CH0_OUT_ARB_TOKEN_NUM_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH0.Reg, volatile.LoadUint32(&o.OUT_ARB_CH0.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH0_OUT_ARB_TOKEN_NUM_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_ARB_CH0.Reg) & 0xf
}
func (o *H264_DMA_Type) SetOUT_ARB_CH0_EXTER_OUT_ARB_PRIORITY_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH0.Reg, volatile.LoadUint32(&o.OUT_ARB_CH0.Reg)&^(0x30)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH0_EXTER_OUT_ARB_PRIORITY_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_ARB_CH0.Reg) & 0x30) >> 4
}

// H264_DMA.OUT_RO_STATUS_CH0: TX CH0 reorder status register
func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUTFIFO_RO_CNT_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x3)|value)
}
func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUTFIFO_RO_CNT_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x3
}
func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_RO_WR_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0xc0)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_RO_WR_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0xc0) >> 6
}
func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_RO_RD_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x300)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_RO_RD_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x300) >> 8
}
func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_PIXEL_BYTE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x3c00)|value<<10)
}
func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_PIXEL_BYTE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x3c00) >> 10
}
func (o *H264_DMA_Type) SetOUT_RO_STATUS_CH0_OUT_BURST_BLOCK_NUM_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_STATUS_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg)&^(0x3c000)|value<<14)
}
func (o *H264_DMA_Type) GetOUT_RO_STATUS_CH0_OUT_BURST_BLOCK_NUM_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_RO_STATUS_CH0.Reg) & 0x3c000) >> 14
}

// H264_DMA.OUT_RO_PD_CONF_CH0: TX CH0 reorder power config register
func (o *H264_DMA_Type) SetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PD_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PD_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PU_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PU_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_CLK_FO_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_RO_PD_CONF_CH0_OUT_RO_RAM_CLK_FO_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_RO_PD_CONF_CH0.Reg) & 0x40) >> 6
}

// H264_DMA.OUT_MODE_ENABLE_CH0: tx CH0 mode enable register
func (o *H264_DMA_Type) SetOUT_MODE_ENABLE_CH0_OUT_TEST_MODE_ENABLE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_MODE_ENABLE_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_ENABLE_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_MODE_ENABLE_CH0_OUT_TEST_MODE_ENABLE_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_MODE_ENABLE_CH0.Reg) & 0x1
}

// H264_DMA.OUT_MODE_YUV_CH0: tx CH0 test mode yuv value register
func (o *H264_DMA_Type) SetOUT_MODE_YUV_CH0_OUT_TEST_Y_VALUE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_MODE_YUV_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetOUT_MODE_YUV_CH0_OUT_TEST_Y_VALUE_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg) & 0xff
}
func (o *H264_DMA_Type) SetOUT_MODE_YUV_CH0_OUT_TEST_U_VALUE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_MODE_YUV_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg)&^(0xff00)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_MODE_YUV_CH0_OUT_TEST_U_VALUE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg) & 0xff00) >> 8
}
func (o *H264_DMA_Type) SetOUT_MODE_YUV_CH0_OUT_TEST_V_VALUE_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_MODE_YUV_CH0.Reg, volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg)&^(0xff0000)|value<<16)
}
func (o *H264_DMA_Type) GetOUT_MODE_YUV_CH0_OUT_TEST_V_VALUE_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_MODE_YUV_CH0.Reg) & 0xff0000) >> 16
}

// H264_DMA.OUT_ETM_CONF_CH0: TX CH0 ETM config register
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH0_OUT_ETM_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH0_OUT_ETM_EN_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH0_OUT_ETM_LOOP_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH0_OUT_ETM_LOOP_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH0_OUT_DSCR_TASK_MAK_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH0_OUT_DSCR_TASK_MAK_CH0() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH0.Reg) & 0xc) >> 2
}

// H264_DMA.OUT_BUF_LEN_CH0: tx CH0 buf len register
func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH0_OUT_CMDFIFO_BUF_LEN_HB_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_BUF_LEN_CH0.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH0.Reg)&^(0x1fff)|value)
}
func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH0_OUT_CMDFIFO_BUF_LEN_HB_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_BUF_LEN_CH0.Reg) & 0x1fff
}

// H264_DMA.OUT_FIFO_BCNT_CH0: tx CH0 fifo byte cnt register
func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH0_OUT_CMDFIFO_OUTFIFO_BCNT_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH0.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH0.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH0_OUT_CMDFIFO_OUTFIFO_BCNT_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH0.Reg) & 0x3ff
}

// H264_DMA.OUT_PUSH_BYTECNT_CH0: tx CH0 push byte cnt register
func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH0_OUT_CMDFIFO_PUSH_BYTECNT_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH0.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH0.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH0_OUT_CMDFIFO_PUSH_BYTECNT_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH0.Reg) & 0xff
}

// H264_DMA.OUT_XADDR_CH0: tx CH0 xaddr register
func (o *H264_DMA_Type) SetOUT_XADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.OUT_XADDR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_XADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.OUT_XADDR_CH0.Reg)
}

// H264_DMA.OUT_CONF0_CH1: TX CH1 config0 register
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_EOF_MODE_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_EOF_MODE_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_ECC_AES_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_ECC_AES_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_CHECK_OWNER_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_CHECK_OWNER_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_MEM_BURST_LENGTH_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_MEM_BURST_LENGTH_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_PAGE_BOUND_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_PAGE_BOUND_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_RST_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_RST_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_CMD_DISABLE_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH1_OUT_ARB_WEIGHT_OPT_DIS_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH1.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH1_OUT_ARB_WEIGHT_OPT_DIS_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH1.Reg) & 0x4000000) >> 26
}

// H264_DMA.OUT_INT_RAW_CH1: TX CH1 interrupt raw register
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DONE_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DONE_CH1_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_EOF_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_EOF_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_ERR_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_L1_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_L1_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_L1_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_L1_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_OVF_L2_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_OVF_L2_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUTFIFO_UDF_L2_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUTFIFO_UDF_L2_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH1_OUT_DSCR_TASK_OVF_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH1_OUT_DSCR_TASK_OVF_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH1.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ENA_CH1: TX CH1 interrupt ena register
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DONE_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DONE_CH1_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_EOF_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_EOF_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_ERR_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_L1_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_L1_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_L1_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_L1_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_OVF_L2_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_OVF_L2_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUTFIFO_UDF_L2_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUTFIFO_UDF_L2_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH1.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ST_CH1: TX CH1 interrupt st register
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_DONE_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_DONE_CH1_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_EOF_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_EOF_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_ERR_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_TOTAL_EOF_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_L1_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_L1_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_L1_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_L1_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_OVF_L2_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_OVF_L2_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUTFIFO_UDF_L2_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUTFIFO_UDF_L2_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH1.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_CLR_CH1: TX CH1 interrupt clr register
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DONE_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DONE_CH1_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_EOF_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_EOF_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_ERR_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_L1_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_L1_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_L1_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_L1_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_OVF_L2_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_OVF_L2_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUTFIFO_UDF_L2_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUTFIFO_UDF_L2_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH1_OUT_DSCR_TASK_OVF_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH1_OUT_DSCR_TASK_OVF_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH1.Reg) & 0x100) >> 8
}

// H264_DMA.OUTFIFO_STATUS_CH1: TX CH1 outfifo status register
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2_CH1() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3_CH1(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH1.Reg) & 0xc0000) >> 18
}

// H264_DMA.OUT_PUSH_CH1: TX CH1 outfifo push register
func (o *H264_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_WDATA_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_WDATA_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x3ff
}
func (o *H264_DMA_Type) SetOUT_PUSH_CH1_OUTFIFO_PUSH_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg)&^(0x400)|value<<10)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH1_OUTFIFO_PUSH_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH1.Reg) & 0x400) >> 10
}

// H264_DMA.OUT_LINK_CONF_CH1: TX CH1 out_link dscr ctrl register
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_STOP_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_STOP_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_START_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_START_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_RESTART_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_RESTART_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH1_OUTLINK_PARK_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH1_OUTLINK_PARK_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH1.Reg) & 0x800000) >> 23
}

// H264_DMA.OUT_LINK_ADDR_CH1: TX CH1 out_link dscr addr register
func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH1.Reg)
}

// H264_DMA.OUT_STATE_CH1: TX CH1 state register
func (o *H264_DMA_Type) SetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetOUT_STATE_CH1_OUT_DSCR_STATE_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH1_OUT_DSCR_STATE_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetOUT_STATE_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0xf00000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0xf00000) >> 20
}
func (o *H264_DMA_Type) SetOUT_STATE_CH1_OUT_RESET_AVAIL_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH1.Reg, volatile.LoadUint32(&o.OUT_STATE_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH1_OUT_RESET_AVAIL_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH1.Reg) & 0x1000000) >> 24
}

// H264_DMA.OUT_EOF_DES_ADDR_CH1: TX CH1 eof des addr register
func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH1.Reg)
}

// H264_DMA.OUT_DSCR_CH1: TX CH1 next dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH1.Reg)
}

// H264_DMA.OUT_DSCR_BF0_CH1: TX CH1 last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH1.Reg)
}

// H264_DMA.OUT_DSCR_BF1_CH1: TX CH1 second-to-last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH1.Reg)
}

// H264_DMA.OUT_ARB_CH1: TX CH1 arb register
func (o *H264_DMA_Type) SetOUT_ARB_CH1_OUT_ARB_TOKEN_NUM_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH1.Reg, volatile.LoadUint32(&o.OUT_ARB_CH1.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH1_OUT_ARB_TOKEN_NUM_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_ARB_CH1.Reg) & 0xf
}
func (o *H264_DMA_Type) SetOUT_ARB_CH1_INTER_OUT_ARB_PRIORITY_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH1.Reg, volatile.LoadUint32(&o.OUT_ARB_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH1_INTER_OUT_ARB_PRIORITY_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_ARB_CH1.Reg) & 0x40) >> 6
}

// H264_DMA.OUT_ETM_CONF_CH1: TX CH1 ETM config register
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH1_OUT_ETM_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH1_OUT_ETM_EN_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH1_OUT_ETM_LOOP_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH1_OUT_ETM_LOOP_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH1_OUT_DSCR_TASK_MAK_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH1_OUT_DSCR_TASK_MAK_CH1() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH1.Reg) & 0xc) >> 2
}

// H264_DMA.OUT_BUF_LEN_CH1: tx CH1 buf len register
func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH1_OUT_CMDFIFO_BUF_LEN_HB_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_BUF_LEN_CH1.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH1.Reg)&^(0x1fff)|value)
}
func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH1_OUT_CMDFIFO_BUF_LEN_HB_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_BUF_LEN_CH1.Reg) & 0x1fff
}

// H264_DMA.OUT_FIFO_BCNT_CH1: tx CH1 fifo byte cnt register
func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH1_OUT_CMDFIFO_OUTFIFO_BCNT_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH1.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH1.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH1_OUT_CMDFIFO_OUTFIFO_BCNT_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH1.Reg) & 0x3ff
}

// H264_DMA.OUT_PUSH_BYTECNT_CH1: tx CH1 push byte cnt register
func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH1_OUT_CMDFIFO_PUSH_BYTECNT_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH1.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH1.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH1_OUT_CMDFIFO_PUSH_BYTECNT_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH1.Reg) & 0xff
}

// H264_DMA.OUT_XADDR_CH1: tx CH1 xaddr register
func (o *H264_DMA_Type) SetOUT_XADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.OUT_XADDR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_XADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.OUT_XADDR_CH1.Reg)
}

// H264_DMA.OUT_CONF0_CH2: TX CH2 config0 register
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_EOF_MODE_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_EOF_MODE_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_ECC_AES_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_ECC_AES_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_CHECK_OWNER_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_CHECK_OWNER_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_MEM_BURST_LENGTH_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_MEM_BURST_LENGTH_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_PAGE_BOUND_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_PAGE_BOUND_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_RST_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_RST_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_CMD_DISABLE_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH2_OUT_ARB_WEIGHT_OPT_DIS_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH2.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH2_OUT_ARB_WEIGHT_OPT_DIS_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH2.Reg) & 0x4000000) >> 26
}

// H264_DMA.OUT_INT_RAW_CH2: TX CH2 interrupt raw register
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DONE_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DONE_CH2_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_EOF_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_EOF_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_ERR_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_L1_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_L1_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_L1_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_L1_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_OVF_L2_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_OVF_L2_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUTFIFO_UDF_L2_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUTFIFO_UDF_L2_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH2_OUT_DSCR_TASK_OVF_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH2_OUT_DSCR_TASK_OVF_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH2.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ENA_CH2: TX CH2 interrupt ena register
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DONE_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DONE_CH2_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_EOF_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_EOF_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_ERR_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_L1_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_L1_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_L1_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_L1_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_OVF_L2_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_OVF_L2_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUTFIFO_UDF_L2_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUTFIFO_UDF_L2_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH2.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ST_CH2: TX CH2 interrupt st register
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_DONE_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_DONE_CH2_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_EOF_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_EOF_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_ERR_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_TOTAL_EOF_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_L1_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_L1_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_L1_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_L1_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_OVF_L2_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_OVF_L2_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUTFIFO_UDF_L2_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUTFIFO_UDF_L2_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH2.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_CLR_CH2: TX CH2 interrupt clr register
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DONE_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DONE_CH2_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_EOF_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_EOF_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_ERR_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_L1_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_L1_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_L1_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_L1_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_OVF_L2_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_OVF_L2_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUTFIFO_UDF_L2_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUTFIFO_UDF_L2_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH2_OUT_DSCR_TASK_OVF_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH2_OUT_DSCR_TASK_OVF_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH2.Reg) & 0x100) >> 8
}

// H264_DMA.OUTFIFO_STATUS_CH2: TX CH2 outfifo status register
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2_CH2() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3_CH2(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH2.Reg) & 0xc0000) >> 18
}

// H264_DMA.OUT_PUSH_CH2: TX CH2 outfifo push register
func (o *H264_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_WDATA_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_WDATA_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x3ff
}
func (o *H264_DMA_Type) SetOUT_PUSH_CH2_OUTFIFO_PUSH_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg)&^(0x400)|value<<10)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH2_OUTFIFO_PUSH_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH2.Reg) & 0x400) >> 10
}

// H264_DMA.OUT_LINK_CONF_CH2: TX CH2 out_link dscr ctrl register
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_STOP_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_STOP_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_START_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_START_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_RESTART_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_RESTART_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH2_OUTLINK_PARK_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH2_OUTLINK_PARK_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH2.Reg) & 0x800000) >> 23
}

// H264_DMA.OUT_LINK_ADDR_CH2: TX CH2 out_link dscr addr register
func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH2.Reg)
}

// H264_DMA.OUT_STATE_CH2: TX CH2 state register
func (o *H264_DMA_Type) SetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetOUT_STATE_CH2_OUT_DSCR_STATE_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH2_OUT_DSCR_STATE_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetOUT_STATE_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0xf00000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0xf00000) >> 20
}
func (o *H264_DMA_Type) SetOUT_STATE_CH2_OUT_RESET_AVAIL_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH2.Reg, volatile.LoadUint32(&o.OUT_STATE_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH2_OUT_RESET_AVAIL_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH2.Reg) & 0x1000000) >> 24
}

// H264_DMA.OUT_EOF_DES_ADDR_CH2: TX CH2 eof des addr register
func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH2.Reg)
}

// H264_DMA.OUT_DSCR_CH2: TX CH2 next dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH2.Reg)
}

// H264_DMA.OUT_DSCR_BF0_CH2: TX CH2 last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH2.Reg)
}

// H264_DMA.OUT_DSCR_BF1_CH2: TX CH2 second-to-last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH2.Reg)
}

// H264_DMA.OUT_ARB_CH2: TX CH2 arb register
func (o *H264_DMA_Type) SetOUT_ARB_CH2_OUT_ARB_TOKEN_NUM_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH2.Reg, volatile.LoadUint32(&o.OUT_ARB_CH2.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH2_OUT_ARB_TOKEN_NUM_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_ARB_CH2.Reg) & 0xf
}
func (o *H264_DMA_Type) SetOUT_ARB_CH2_INTER_OUT_ARB_PRIORITY_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH2.Reg, volatile.LoadUint32(&o.OUT_ARB_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH2_INTER_OUT_ARB_PRIORITY_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_ARB_CH2.Reg) & 0x40) >> 6
}

// H264_DMA.OUT_ETM_CONF_CH2: TX CH2 ETM config register
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH2_OUT_ETM_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH2_OUT_ETM_EN_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH2_OUT_ETM_LOOP_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH2_OUT_ETM_LOOP_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH2_OUT_DSCR_TASK_MAK_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH2_OUT_DSCR_TASK_MAK_CH2() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH2.Reg) & 0xc) >> 2
}

// H264_DMA.OUT_BUF_LEN_CH2: tx CH2 buf len register
func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH2_OUT_CMDFIFO_BUF_LEN_HB_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_BUF_LEN_CH2.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH2.Reg)&^(0x1fff)|value)
}
func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH2_OUT_CMDFIFO_BUF_LEN_HB_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_BUF_LEN_CH2.Reg) & 0x1fff
}

// H264_DMA.OUT_FIFO_BCNT_CH2: tx CH2 fifo byte cnt register
func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH2_OUT_CMDFIFO_OUTFIFO_BCNT_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH2.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH2.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH2_OUT_CMDFIFO_OUTFIFO_BCNT_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH2.Reg) & 0x3ff
}

// H264_DMA.OUT_PUSH_BYTECNT_CH2: tx CH2 push byte cnt register
func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH2_OUT_CMDFIFO_PUSH_BYTECNT_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH2.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH2.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH2_OUT_CMDFIFO_PUSH_BYTECNT_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH2.Reg) & 0xff
}

// H264_DMA.OUT_XADDR_CH2: tx CH2 xaddr register
func (o *H264_DMA_Type) SetOUT_XADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.OUT_XADDR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_XADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.OUT_XADDR_CH2.Reg)
}

// H264_DMA.OUT_CONF0_CH3: TX CH3 config0 register
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_AUTO_WRBACK_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_AUTO_WRBACK_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_EOF_MODE_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_EOF_MODE_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUTDSCR_BURST_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUTDSCR_BURST_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_ECC_AES_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_ECC_AES_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_CHECK_OWNER_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_CHECK_OWNER_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_MEM_BURST_LENGTH_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_MEM_BURST_LENGTH_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_PAGE_BOUND_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_PAGE_BOUND_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH3_OUT_ARB_WEIGHT_OPT_DIS_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH3.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH3_OUT_ARB_WEIGHT_OPT_DIS_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH3.Reg) & 0x4000000) >> 26
}

// H264_DMA.OUT_INT_RAW_CH3: TX CH3 interrupt raw register
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_DONE_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_DONE_CH3_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_EOF_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_EOF_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_DSCR_ERR_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_DSCR_ERR_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_TOTAL_EOF_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_TOTAL_EOF_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_OVF_L1_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_OVF_L1_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_UDF_L1_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_UDF_L1_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_OVF_L2_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_OVF_L2_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUTFIFO_UDF_L2_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUTFIFO_UDF_L2_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH3_OUT_DSCR_TASK_OVF_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH3_OUT_DSCR_TASK_OVF_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH3.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ENA_CH3: TX CH3 interrupt ena register
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_DONE_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_DONE_CH3_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_EOF_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_EOF_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_DSCR_ERR_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_DSCR_ERR_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_TOTAL_EOF_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_TOTAL_EOF_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_OVF_L1_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_OVF_L1_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_UDF_L1_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_UDF_L1_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_OVF_L2_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_OVF_L2_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUTFIFO_UDF_L2_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUTFIFO_UDF_L2_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH3.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ST_CH3: TX CH3 interrupt st register
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_DONE_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_DONE_CH3_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_EOF_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_EOF_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_DSCR_ERR_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_DSCR_ERR_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_TOTAL_EOF_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_TOTAL_EOF_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_OVF_L1_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_OVF_L1_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_UDF_L1_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_UDF_L1_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_OVF_L2_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_OVF_L2_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUTFIFO_UDF_L2_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUTFIFO_UDF_L2_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH3.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_CLR_CH3: TX CH3 interrupt clr register
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_DONE_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_DONE_CH3_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_EOF_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_EOF_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_DSCR_ERR_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_DSCR_ERR_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_TOTAL_EOF_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_TOTAL_EOF_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_OVF_L1_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_OVF_L1_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_UDF_L1_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_UDF_L1_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_OVF_L2_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_OVF_L2_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUTFIFO_UDF_L2_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUTFIFO_UDF_L2_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH3_OUT_DSCR_TASK_OVF_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH3_OUT_DSCR_TASK_OVF_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH3.Reg) & 0x100) >> 8
}

// H264_DMA.OUTFIFO_STATUS_CH3: TX CH3 outfifo status register
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2_CH3() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3_CH3(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH3.Reg) & 0xc0000) >> 18
}

// H264_DMA.OUT_PUSH_CH3: TX CH3 outfifo push register
func (o *H264_DMA_Type) SetOUT_PUSH_CH3_OUTFIFO_WDATA_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH3_OUTFIFO_WDATA_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg) & 0x3ff
}
func (o *H264_DMA_Type) SetOUT_PUSH_CH3_OUTFIFO_PUSH_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg)&^(0x400)|value<<10)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH3_OUTFIFO_PUSH_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH3.Reg) & 0x400) >> 10
}

// H264_DMA.OUT_LINK_CONF_CH3: TX CH3 out_link dscr ctrl register
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_STOP_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_STOP_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_START_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_START_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_RESTART_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_RESTART_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH3_OUTLINK_PARK_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH3_OUTLINK_PARK_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH3.Reg) & 0x800000) >> 23
}

// H264_DMA.OUT_LINK_ADDR_CH3: TX CH3 out_link dscr addr register
func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH3.Reg)
}

// H264_DMA.OUT_STATE_CH3: TX CH3 state register
func (o *H264_DMA_Type) SetOUT_STATE_CH3_OUTLINK_DSCR_ADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH3_OUTLINK_DSCR_ADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetOUT_STATE_CH3_OUT_DSCR_STATE_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH3_OUT_DSCR_STATE_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetOUT_STATE_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH3.Reg, volatile.LoadUint32(&o.OUT_STATE_CH3.Reg)&^(0xf00000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH3.Reg) & 0xf00000) >> 20
}

// H264_DMA.OUT_EOF_DES_ADDR_CH3: TX CH3 eof des addr register
func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH3.Reg)
}

// H264_DMA.OUT_DSCR_CH3: TX CH3 next dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH3.Reg)
}

// H264_DMA.OUT_DSCR_BF0_CH3: TX CH3 last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH3.Reg)
}

// H264_DMA.OUT_DSCR_BF1_CH3: TX CH3 second-to-last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH3.Reg)
}

// H264_DMA.OUT_ARB_CH3: TX CH3 arb register
func (o *H264_DMA_Type) SetOUT_ARB_CH3_OUT_ARB_TOKEN_NUM_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH3.Reg, volatile.LoadUint32(&o.OUT_ARB_CH3.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH3_OUT_ARB_TOKEN_NUM_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_ARB_CH3.Reg) & 0xf
}
func (o *H264_DMA_Type) SetOUT_ARB_CH3_EXTER_OUT_ARB_PRIORITY_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH3.Reg, volatile.LoadUint32(&o.OUT_ARB_CH3.Reg)&^(0x30)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH3_EXTER_OUT_ARB_PRIORITY_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_ARB_CH3.Reg) & 0x30) >> 4
}

// H264_DMA.OUT_ETM_CONF_CH3: TX CH3 ETM config register
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH3_OUT_ETM_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH3_OUT_ETM_EN_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH3_OUT_ETM_LOOP_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH3_OUT_ETM_LOOP_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH3_OUT_DSCR_TASK_MAK_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH3_OUT_DSCR_TASK_MAK_CH3() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH3.Reg) & 0xc) >> 2
}

// H264_DMA.OUT_BUF_LEN_CH3: tx CH3 buf len register
func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH3_OUT_CMDFIFO_BUF_LEN_HB_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_BUF_LEN_CH3.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH3.Reg)&^(0x1fff)|value)
}
func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH3_OUT_CMDFIFO_BUF_LEN_HB_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_BUF_LEN_CH3.Reg) & 0x1fff
}

// H264_DMA.OUT_FIFO_BCNT_CH3: tx CH3 fifo byte cnt register
func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH3_OUT_CMDFIFO_OUTFIFO_BCNT_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH3.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH3.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH3_OUT_CMDFIFO_OUTFIFO_BCNT_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH3.Reg) & 0x3ff
}

// H264_DMA.OUT_PUSH_BYTECNT_CH3: tx CH3 push byte cnt register
func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH3_OUT_CMDFIFO_PUSH_BYTECNT_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH3.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH3.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH3_OUT_CMDFIFO_PUSH_BYTECNT_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH3.Reg) & 0xff
}

// H264_DMA.OUT_XADDR_CH3: tx CH3 xaddr register
func (o *H264_DMA_Type) SetOUT_XADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_XADDR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_XADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_XADDR_CH3.Reg)
}

// H264_DMA.OUT_BLOCK_BUF_LEN_CH3: tx CH3 block buf len register
func (o *H264_DMA_Type) SetOUT_BLOCK_BUF_LEN_CH3(value uint32) {
	volatile.StoreUint32(&o.OUT_BLOCK_BUF_LEN_CH3.Reg, volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH3.Reg)&^(0xfffffff)|value)
}
func (o *H264_DMA_Type) GetOUT_BLOCK_BUF_LEN_CH3() uint32 {
	return volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH3.Reg) & 0xfffffff
}

// H264_DMA.OUT_CONF0_CH4: TX CH4 config0 register
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_AUTO_WRBACK_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_AUTO_WRBACK_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_EOF_MODE_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_EOF_MODE_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUTDSCR_BURST_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUTDSCR_BURST_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_ECC_AES_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_ECC_AES_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_CHECK_OWNER_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_CHECK_OWNER_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_MEM_BURST_LENGTH_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_MEM_BURST_LENGTH_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_PAGE_BOUND_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_PAGE_BOUND_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetOUT_CONF0_CH4_OUT_ARB_WEIGHT_OPT_DIS_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_CONF0_CH4.Reg, volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetOUT_CONF0_CH4_OUT_ARB_WEIGHT_OPT_DIS_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_CONF0_CH4.Reg) & 0x4000000) >> 26
}

// H264_DMA.OUT_INT_RAW_CH4: TX CH4 interrupt raw register
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_DONE_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_DONE_CH4_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_EOF_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_EOF_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_DSCR_ERR_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_DSCR_ERR_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_TOTAL_EOF_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_TOTAL_EOF_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_OVF_L1_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_OVF_L1_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_UDF_L1_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_UDF_L1_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_OVF_L2_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_OVF_L2_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUTFIFO_UDF_L2_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUTFIFO_UDF_L2_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_RAW_CH4_OUT_DSCR_TASK_OVF_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_RAW_CH4_OUT_DSCR_TASK_OVF_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_RAW_CH4.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ENA_CH4: TX CH4 interrupt ena register
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_DONE_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_DONE_CH4_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_EOF_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_EOF_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_DSCR_ERR_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_DSCR_ERR_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_TOTAL_EOF_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_TOTAL_EOF_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_OVF_L1_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_OVF_L1_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_UDF_L1_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_UDF_L1_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_OVF_L2_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_OVF_L2_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUTFIFO_UDF_L2_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUTFIFO_UDF_L2_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ENA_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ENA_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ENA_CH4.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_ST_CH4: TX CH4 interrupt st register
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_DONE_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_DONE_CH4_INT_ST() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_EOF_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_EOF_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_DSCR_ERR_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_DSCR_ERR_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_TOTAL_EOF_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_TOTAL_EOF_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_OVF_L1_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_OVF_L1_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_UDF_L1_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_UDF_L1_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_OVF_L2_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_OVF_L2_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUTFIFO_UDF_L2_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUTFIFO_UDF_L2_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_ST_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_ST_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_ST_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_ST_CH4.Reg) & 0x100) >> 8
}

// H264_DMA.OUT_INT_CLR_CH4: TX CH4 interrupt clr register
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_DONE_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_DONE_CH4_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_EOF_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_EOF_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_DSCR_ERR_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_DSCR_ERR_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_TOTAL_EOF_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_TOTAL_EOF_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_OVF_L1_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_OVF_L1_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_UDF_L1_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_UDF_L1_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_OVF_L2_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_OVF_L2_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUTFIFO_UDF_L2_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUTFIFO_UDF_L2_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUT_INT_CLR_CH4_OUT_DSCR_TASK_OVF_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.OUT_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetOUT_INT_CLR_CH4_OUT_DSCR_TASK_OVF_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.OUT_INT_CLR_CH4.Reg) & 0x100) >> 8
}

// H264_DMA.OUTFIFO_STATUS_CH4: TX CH4 outfifo status register
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2_CH4() uint32 {
	return volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3_CH4(value uint32) {
	volatile.StoreUint32(&o.OUTFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUTFIFO_STATUS_CH4.Reg) & 0xc0000) >> 18
}

// H264_DMA.OUT_PUSH_CH4: TX CH4 outfifo push register
func (o *H264_DMA_Type) SetOUT_PUSH_CH4_OUTFIFO_WDATA_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH4_OUTFIFO_WDATA_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg) & 0x3ff
}
func (o *H264_DMA_Type) SetOUT_PUSH_CH4_OUTFIFO_PUSH_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg)&^(0x400)|value<<10)
}
func (o *H264_DMA_Type) GetOUT_PUSH_CH4_OUTFIFO_PUSH_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_PUSH_CH4.Reg) & 0x400) >> 10
}

// H264_DMA.OUT_LINK_CONF_CH4: TX CH4 out_link dscr ctrl register
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_STOP_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_STOP_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_START_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_START_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_RESTART_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_RESTART_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetOUT_LINK_CONF_CH4_OUTLINK_PARK_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetOUT_LINK_CONF_CH4_OUTLINK_PARK_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_LINK_CONF_CH4.Reg) & 0x800000) >> 23
}

// H264_DMA.OUT_LINK_ADDR_CH4: TX CH4 out_link dscr addr register
func (o *H264_DMA_Type) SetOUT_LINK_ADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_LINK_ADDR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_LINK_ADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_LINK_ADDR_CH4.Reg)
}

// H264_DMA.OUT_STATE_CH4: TX CH4 state register
func (o *H264_DMA_Type) SetOUT_STATE_CH4_OUTLINK_DSCR_ADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH4_OUTLINK_DSCR_ADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetOUT_STATE_CH4_OUT_DSCR_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH4_OUT_DSCR_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetOUT_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_STATE_CH4.Reg, volatile.LoadUint32(&o.OUT_STATE_CH4.Reg)&^(0xf00000)|value<<20)
}
func (o *H264_DMA_Type) GetOUT_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_STATE_CH4.Reg) & 0xf00000) >> 20
}

// H264_DMA.OUT_EOF_DES_ADDR_CH4: TX CH4 eof des addr register
func (o *H264_DMA_Type) SetOUT_EOF_DES_ADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_EOF_DES_ADDR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_EOF_DES_ADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_EOF_DES_ADDR_CH4.Reg)
}

// H264_DMA.OUT_DSCR_CH4: TX CH4 next dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_CH4.Reg)
}

// H264_DMA.OUT_DSCR_BF0_CH4: TX CH4 last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF0_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF0_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF0_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF0_CH4.Reg)
}

// H264_DMA.OUT_DSCR_BF1_CH4: TX CH4 second-to-last dscr addr register
func (o *H264_DMA_Type) SetOUT_DSCR_BF1_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_DSCR_BF1_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_DSCR_BF1_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_DSCR_BF1_CH4.Reg)
}

// H264_DMA.OUT_ARB_CH4: TX CH4 arb register
func (o *H264_DMA_Type) SetOUT_ARB_CH4_OUT_ARB_TOKEN_NUM_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH4.Reg, volatile.LoadUint32(&o.OUT_ARB_CH4.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH4_OUT_ARB_TOKEN_NUM_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_ARB_CH4.Reg) & 0xf
}
func (o *H264_DMA_Type) SetOUT_ARB_CH4_EXTER_OUT_ARB_PRIORITY_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CH4.Reg, volatile.LoadUint32(&o.OUT_ARB_CH4.Reg)&^(0x30)|value<<4)
}
func (o *H264_DMA_Type) GetOUT_ARB_CH4_EXTER_OUT_ARB_PRIORITY_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_ARB_CH4.Reg) & 0x30) >> 4
}

// H264_DMA.OUT_ETM_CONF_CH4: TX CH4 ETM config register
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH4_OUT_ETM_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH4_OUT_ETM_EN_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH4_OUT_ETM_LOOP_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH4_OUT_ETM_LOOP_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetOUT_ETM_CONF_CH4_OUT_DSCR_TASK_MAK_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetOUT_ETM_CONF_CH4_OUT_DSCR_TASK_MAK_CH4() uint32 {
	return (volatile.LoadUint32(&o.OUT_ETM_CONF_CH4.Reg) & 0xc) >> 2
}

// H264_DMA.OUT_BUF_LEN_CH4: tx CH4 buf len register
func (o *H264_DMA_Type) SetOUT_BUF_LEN_CH4_OUT_CMDFIFO_BUF_LEN_HB_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_BUF_LEN_CH4.Reg, volatile.LoadUint32(&o.OUT_BUF_LEN_CH4.Reg)&^(0x1fff)|value)
}
func (o *H264_DMA_Type) GetOUT_BUF_LEN_CH4_OUT_CMDFIFO_BUF_LEN_HB_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_BUF_LEN_CH4.Reg) & 0x1fff
}

// H264_DMA.OUT_FIFO_BCNT_CH4: tx CH4 fifo byte cnt register
func (o *H264_DMA_Type) SetOUT_FIFO_BCNT_CH4_OUT_CMDFIFO_OUTFIFO_BCNT_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_FIFO_BCNT_CH4.Reg, volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH4.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetOUT_FIFO_BCNT_CH4_OUT_CMDFIFO_OUTFIFO_BCNT_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_FIFO_BCNT_CH4.Reg) & 0x3ff
}

// H264_DMA.OUT_PUSH_BYTECNT_CH4: tx CH4 push byte cnt register
func (o *H264_DMA_Type) SetOUT_PUSH_BYTECNT_CH4_OUT_CMDFIFO_PUSH_BYTECNT_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_PUSH_BYTECNT_CH4.Reg, volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH4.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetOUT_PUSH_BYTECNT_CH4_OUT_CMDFIFO_PUSH_BYTECNT_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_PUSH_BYTECNT_CH4.Reg) & 0xff
}

// H264_DMA.OUT_XADDR_CH4: tx CH4 xaddr register
func (o *H264_DMA_Type) SetOUT_XADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_XADDR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetOUT_XADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_XADDR_CH4.Reg)
}

// H264_DMA.OUT_BLOCK_BUF_LEN_CH4: tx CH4 block buf len register
func (o *H264_DMA_Type) SetOUT_BLOCK_BUF_LEN_CH4(value uint32) {
	volatile.StoreUint32(&o.OUT_BLOCK_BUF_LEN_CH4.Reg, volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH4.Reg)&^(0xfffffff)|value)
}
func (o *H264_DMA_Type) GetOUT_BLOCK_BUF_LEN_CH4() uint32 {
	return volatile.LoadUint32(&o.OUT_BLOCK_BUF_LEN_CH4.Reg) & 0xfffffff
}

// H264_DMA.IN_CONF0_CH0: RX CH0 config0 register
func (o *H264_DMA_Type) SetIN_CONF0_CH0_INDSCR_BURST_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_INDSCR_BURST_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_ECC_AES_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_ECC_AES_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_CHECK_OWNER_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_CHECK_OWNER_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_MEM_BURST_LENGTH_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_MEM_BURST_LENGTH_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_PAGE_BOUND_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_PAGE_BOUND_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_CMD_DISABLE_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_CMD_DISABLE_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetIN_CONF0_CH0_IN_ARB_WEIGHT_OPT_DIS_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH0.Reg, volatile.LoadUint32(&o.IN_CONF0_CH0.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH0_IN_ARB_WEIGHT_OPT_DIS_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH0.Reg) & 0x4000000) >> 26
}

// H264_DMA.IN_INT_RAW_CH0: RX CH0 interrupt raw register
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DONE_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DONE_CH0_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_SUC_EOF_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_SUC_EOF_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_ERR_EOF_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_ERR_EOF_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_ERR_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_ERR_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_L1_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_L1_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_L1_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_L1_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_OVF_L2_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_OVF_L2_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_INFIFO_UDF_L2_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_INFIFO_UDF_L2_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_EMPTY_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH0_IN_DSCR_TASK_OVF_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH0.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH0_IN_DSCR_TASK_OVF_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH0.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ENA_CH0: RX CH0 interrupt ena register
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DONE_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DONE_CH0_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_SUC_EOF_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_SUC_EOF_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_ERR_EOF_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_ERR_EOF_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_ERR_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_ERR_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_L1_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_L1_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_L1_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_L1_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_OVF_L2_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_OVF_L2_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_INFIFO_UDF_L2_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_INFIFO_UDF_L2_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_EMPTY_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH0_IN_DSCR_TASK_OVF_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH0_IN_DSCR_TASK_OVF_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH0.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ST_CH0: RX CH0 interrupt st register
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DONE_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DONE_CH0_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_SUC_EOF_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_SUC_EOF_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_ERR_EOF_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_ERR_EOF_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_ERR_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_ERR_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_L1_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_L1_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_L1_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_L1_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_OVF_L2_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_OVF_L2_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_INFIFO_UDF_L2_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_INFIFO_UDF_L2_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_EMPTY_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH0_IN_DSCR_TASK_OVF_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH0.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH0_IN_DSCR_TASK_OVF_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH0.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_CLR_CH0: RX CH0 interrupt clr register
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DONE_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DONE_CH0_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_SUC_EOF_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_SUC_EOF_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_ERR_EOF_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_ERR_EOF_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_ERR_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_ERR_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_L1_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_L1_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_L1_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_L1_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_OVF_L2_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_OVF_L2_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_INFIFO_UDF_L2_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_INFIFO_UDF_L2_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_EMPTY_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH0_IN_DSCR_TASK_OVF_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH0.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH0_IN_DSCR_TASK_OVF_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH0.Reg) & 0x200) >> 9
}

// H264_DMA.INFIFO_STATUS_CH0: RX CH0 INFIFO status register
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L2_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L2_CH0() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L2_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L2_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L2_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L2_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L1_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L1_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L1_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L1_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L1_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L1_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_FULL_L3_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_FULL_L3_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_EMPTY_L3_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_EMPTY_L3_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH0_INFIFO_CNT_L3_CH0(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH0.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH0_INFIFO_CNT_L3_CH0() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH0.Reg) & 0xc0000) >> 18
}

// H264_DMA.IN_POP_CH0: RX CH0 INFIFO pop register
func (o *H264_DMA_Type) SetIN_POP_CH0_INFIFO_RDATA_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x7ff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_CH0_INFIFO_RDATA_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x7ff
}
func (o *H264_DMA_Type) SetIN_POP_CH0_INFIFO_POP_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH0.Reg, volatile.LoadUint32(&o.IN_POP_CH0.Reg)&^(0x800)|value<<11)
}
func (o *H264_DMA_Type) GetIN_POP_CH0_INFIFO_POP_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH0.Reg) & 0x800) >> 11
}

// H264_DMA.IN_LINK_CONF_CH0: RX CH0 in_link dscr ctrl register
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_AUTO_RET_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_AUTO_RET_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_STOP_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_STOP_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_START_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_START_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_RESTART_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_RESTART_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x800000) >> 23
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH0_INLINK_PARK_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH0_INLINK_PARK_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH0.Reg) & 0x1000000) >> 24
}

// H264_DMA.IN_LINK_ADDR_CH0: RX CH0 in_link dscr addr register
func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH0.Reg)
}

// H264_DMA.IN_STATE_CH0: RX CH0 state register
func (o *H264_DMA_Type) SetIN_STATE_CH0_INLINK_DSCR_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetIN_STATE_CH0_INLINK_DSCR_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetIN_STATE_CH0_IN_DSCR_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetIN_STATE_CH0_IN_DSCR_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetIN_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x700000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x700000) >> 20
}
func (o *H264_DMA_Type) SetIN_STATE_CH0_IN_RESET_AVAIL_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH0.Reg, volatile.LoadUint32(&o.IN_STATE_CH0.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_STATE_CH0_IN_RESET_AVAIL_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH0.Reg) & 0x800000) >> 23
}

// H264_DMA.IN_SUC_EOF_DES_ADDR_CH0: RX CH0 eof des addr register
func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH0.Reg)
}

// H264_DMA.IN_ERR_EOF_DES_ADDR_CH0: RX CH0 err eof des addr register
func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH0.Reg)
}

// H264_DMA.IN_DSCR_CH0: RX CH0 next dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH0.Reg)
}

// H264_DMA.IN_DSCR_BF0_CH0: RX CH0 last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH0.Reg)
}

// H264_DMA.IN_DSCR_BF1_CH0: RX CH0 second-to-last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH0.Reg)
}

// H264_DMA.IN_ARB_CH0: RX CH0 arb register
func (o *H264_DMA_Type) SetIN_ARB_CH0_IN_ARB_TOKEN_NUM_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH0.Reg, volatile.LoadUint32(&o.IN_ARB_CH0.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetIN_ARB_CH0_IN_ARB_TOKEN_NUM_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_ARB_CH0.Reg) & 0xf
}
func (o *H264_DMA_Type) SetIN_ARB_CH0_EXTER_IN_ARB_PRIORITY_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH0.Reg, volatile.LoadUint32(&o.IN_ARB_CH0.Reg)&^(0x30)|value<<4)
}
func (o *H264_DMA_Type) GetIN_ARB_CH0_EXTER_IN_ARB_PRIORITY_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH0.Reg) & 0x30) >> 4
}
func (o *H264_DMA_Type) SetIN_ARB_CH0_INTER_IN_ARB_PRIORITY_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH0.Reg, volatile.LoadUint32(&o.IN_ARB_CH0.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_ARB_CH0_INTER_IN_ARB_PRIORITY_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH0.Reg) & 0x1c0) >> 6
}

// H264_DMA.IN_RO_PD_CONF_CH0: RX CH0 reorder power config register
func (o *H264_DMA_Type) SetIN_RO_PD_CONF_CH0_IN_RO_RAM_CLK_FO_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_RO_PD_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_RO_PD_CONF_CH0.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_RO_PD_CONF_CH0_IN_RO_RAM_CLK_FO_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_RO_PD_CONF_CH0.Reg) & 0x40) >> 6
}

// H264_DMA.IN_ETM_CONF_CH0: RX CH0 ETM config register
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH0_IN_ETM_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH0_IN_ETM_EN_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH0_IN_ETM_LOOP_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH0_IN_ETM_LOOP_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH0_IN_DSCR_TASK_MAK_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH0.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH0_IN_DSCR_TASK_MAK_CH0() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH0.Reg) & 0xc) >> 2
}

// H264_DMA.IN_FIFO_CNT_CH0: rx CH0 fifo cnt register
func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH0_IN_CMDFIFO_INFIFO_CNT_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_FIFO_CNT_CH0.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH0.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH0_IN_CMDFIFO_INFIFO_CNT_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_FIFO_CNT_CH0.Reg) & 0x3ff
}

// H264_DMA.IN_POP_DATA_CNT_CH0: rx CH0 pop data cnt register
func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH0_IN_CMDFIFO_POP_DATA_CNT_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH0.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH0.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH0_IN_CMDFIFO_POP_DATA_CNT_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH0.Reg) & 0xff
}

// H264_DMA.IN_XADDR_CH0: rx CH0 xaddr register
func (o *H264_DMA_Type) SetIN_XADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_XADDR_CH0.Reg, value)
}
func (o *H264_DMA_Type) GetIN_XADDR_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_XADDR_CH0.Reg)
}

// H264_DMA.IN_BUF_HB_RCV_CH0: rx CH0 buf len hb rcv register
func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH0_IN_CMDFIFO_BUF_HB_RCV_CH0(value uint32) {
	volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH0.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH0.Reg)&^(0x1fffffff)|value)
}
func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH0_IN_CMDFIFO_BUF_HB_RCV_CH0() uint32 {
	return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH0.Reg) & 0x1fffffff
}

// H264_DMA.IN_CONF0_CH1: RX CH1 config0 register
func (o *H264_DMA_Type) SetIN_CONF0_CH1_INDSCR_BURST_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_INDSCR_BURST_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_ECC_AES_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_ECC_AES_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_CHECK_OWNER_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_CHECK_OWNER_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_MEM_BURST_LENGTH_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_MEM_BURST_LENGTH_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_PAGE_BOUND_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_PAGE_BOUND_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_RST_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_RST_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_CMD_DISABLE_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_CMD_DISABLE_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetIN_CONF0_CH1_IN_ARB_WEIGHT_OPT_DIS_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH1.Reg, volatile.LoadUint32(&o.IN_CONF0_CH1.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH1_IN_ARB_WEIGHT_OPT_DIS_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH1.Reg) & 0x4000000) >> 26
}

// H264_DMA.IN_INT_RAW_CH1: RX CH1 interrupt raw register
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DONE_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DONE_CH1_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_SUC_EOF_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_SUC_EOF_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_ERR_EOF_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_ERR_EOF_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_ERR_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_ERR_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_L1_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_L1_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_L1_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_L1_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_OVF_L2_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_OVF_L2_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_INFIFO_UDF_L2_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_INFIFO_UDF_L2_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_EMPTY_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH1_IN_DSCR_TASK_OVF_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH1.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH1_IN_DSCR_TASK_OVF_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH1.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ENA_CH1: RX CH1 interrupt ena register
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DONE_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DONE_CH1_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_SUC_EOF_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_SUC_EOF_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_ERR_EOF_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_ERR_EOF_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_ERR_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_ERR_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_L1_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_L1_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_L1_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_L1_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_OVF_L2_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_OVF_L2_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_INFIFO_UDF_L2_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_INFIFO_UDF_L2_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_EMPTY_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH1_IN_DSCR_TASK_OVF_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH1_IN_DSCR_TASK_OVF_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH1.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ST_CH1: RX CH1 interrupt st register
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DONE_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DONE_CH1_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_SUC_EOF_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_SUC_EOF_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_ERR_EOF_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_ERR_EOF_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_ERR_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_ERR_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_L1_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_L1_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_L1_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_L1_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_OVF_L2_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_OVF_L2_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_INFIFO_UDF_L2_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_INFIFO_UDF_L2_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_EMPTY_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH1_IN_DSCR_TASK_OVF_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH1.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH1_IN_DSCR_TASK_OVF_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH1.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_CLR_CH1: RX CH1 interrupt clr register
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DONE_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DONE_CH1_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_SUC_EOF_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_SUC_EOF_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_ERR_EOF_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_ERR_EOF_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_ERR_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_ERR_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_L1_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_L1_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_L1_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_L1_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_OVF_L2_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_OVF_L2_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_INFIFO_UDF_L2_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_INFIFO_UDF_L2_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_EMPTY_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH1_IN_DSCR_TASK_OVF_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH1.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH1_IN_DSCR_TASK_OVF_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH1.Reg) & 0x200) >> 9
}

// H264_DMA.INFIFO_STATUS_CH1: RX CH1 INFIFO status register
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L2_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L2_CH1() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L2_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L2_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L2_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L2_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L1_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L1_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L1_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L1_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L1_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L1_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_FULL_L3_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_FULL_L3_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_EMPTY_L3_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_EMPTY_L3_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH1_INFIFO_CNT_L3_CH1(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH1.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH1_INFIFO_CNT_L3_CH1() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH1.Reg) & 0xc0000) >> 18
}

// H264_DMA.IN_POP_CH1: RX CH1 INFIFO pop register
func (o *H264_DMA_Type) SetIN_POP_CH1_INFIFO_RDATA_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x7ff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_CH1_INFIFO_RDATA_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x7ff
}
func (o *H264_DMA_Type) SetIN_POP_CH1_INFIFO_POP_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH1.Reg, volatile.LoadUint32(&o.IN_POP_CH1.Reg)&^(0x800)|value<<11)
}
func (o *H264_DMA_Type) GetIN_POP_CH1_INFIFO_POP_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH1.Reg) & 0x800) >> 11
}

// H264_DMA.IN_LINK_CONF_CH1: RX CH1 in_link dscr ctrl register
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_AUTO_RET_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_AUTO_RET_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_STOP_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_STOP_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_START_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_START_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_RESTART_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_RESTART_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x800000) >> 23
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH1_INLINK_PARK_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH1_INLINK_PARK_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH1.Reg) & 0x1000000) >> 24
}

// H264_DMA.IN_LINK_ADDR_CH1: RX CH1 in_link dscr addr register
func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH1.Reg)
}

// H264_DMA.IN_STATE_CH1: RX CH1 state register
func (o *H264_DMA_Type) SetIN_STATE_CH1_INLINK_DSCR_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetIN_STATE_CH1_INLINK_DSCR_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetIN_STATE_CH1_IN_DSCR_STATE_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetIN_STATE_CH1_IN_DSCR_STATE_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetIN_STATE_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x700000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_STATE_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x700000) >> 20
}
func (o *H264_DMA_Type) SetIN_STATE_CH1_IN_RESET_AVAIL_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH1.Reg, volatile.LoadUint32(&o.IN_STATE_CH1.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_STATE_CH1_IN_RESET_AVAIL_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH1.Reg) & 0x800000) >> 23
}

// H264_DMA.IN_SUC_EOF_DES_ADDR_CH1: RX CH1 eof des addr register
func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH1.Reg)
}

// H264_DMA.IN_ERR_EOF_DES_ADDR_CH1: RX CH1 err eof des addr register
func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH1.Reg)
}

// H264_DMA.IN_DSCR_CH1: RX CH1 next dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH1.Reg)
}

// H264_DMA.IN_DSCR_BF0_CH1: RX CH1 last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH1.Reg)
}

// H264_DMA.IN_DSCR_BF1_CH1: RX CH1 second-to-last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH1.Reg)
}

// H264_DMA.IN_ARB_CH1: RX CH1 arb register
func (o *H264_DMA_Type) SetIN_ARB_CH1_IN_ARB_TOKEN_NUM_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH1.Reg, volatile.LoadUint32(&o.IN_ARB_CH1.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetIN_ARB_CH1_IN_ARB_TOKEN_NUM_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_ARB_CH1.Reg) & 0xf
}
func (o *H264_DMA_Type) SetIN_ARB_CH1_EXTER_IN_ARB_PRIORITY_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH1.Reg, volatile.LoadUint32(&o.IN_ARB_CH1.Reg)&^(0x30)|value<<4)
}
func (o *H264_DMA_Type) GetIN_ARB_CH1_EXTER_IN_ARB_PRIORITY_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH1.Reg) & 0x30) >> 4
}
func (o *H264_DMA_Type) SetIN_ARB_CH1_INTER_IN_ARB_PRIORITY_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH1.Reg, volatile.LoadUint32(&o.IN_ARB_CH1.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_ARB_CH1_INTER_IN_ARB_PRIORITY_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH1.Reg) & 0x1c0) >> 6
}

// H264_DMA.IN_ETM_CONF_CH1: RX CH1 ETM config register
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH1_IN_ETM_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH1_IN_ETM_EN_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH1_IN_ETM_LOOP_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH1_IN_ETM_LOOP_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH1_IN_DSCR_TASK_MAK_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH1.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH1_IN_DSCR_TASK_MAK_CH1() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH1.Reg) & 0xc) >> 2
}

// H264_DMA.IN_FIFO_CNT_CH1: rx CH1 fifo cnt register
func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH1_IN_CMDFIFO_INFIFO_CNT_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_FIFO_CNT_CH1.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH1.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH1_IN_CMDFIFO_INFIFO_CNT_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_FIFO_CNT_CH1.Reg) & 0x3ff
}

// H264_DMA.IN_POP_DATA_CNT_CH1: rx CH1 pop data cnt register
func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH1_IN_CMDFIFO_POP_DATA_CNT_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH1.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH1.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH1_IN_CMDFIFO_POP_DATA_CNT_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH1.Reg) & 0xff
}

// H264_DMA.IN_XADDR_CH1: rx CH1 xaddr register
func (o *H264_DMA_Type) SetIN_XADDR_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_XADDR_CH1.Reg, value)
}
func (o *H264_DMA_Type) GetIN_XADDR_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_XADDR_CH1.Reg)
}

// H264_DMA.IN_BUF_HB_RCV_CH1: rx CH1 buf len hb rcv register
func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH1_IN_CMDFIFO_BUF_HB_RCV_CH1(value uint32) {
	volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH1.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH1.Reg)&^(0x1fffffff)|value)
}
func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH1_IN_CMDFIFO_BUF_HB_RCV_CH1() uint32 {
	return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH1.Reg) & 0x1fffffff
}

// H264_DMA.IN_CONF0_CH2: RX CH2 config0 register
func (o *H264_DMA_Type) SetIN_CONF0_CH2_INDSCR_BURST_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_INDSCR_BURST_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_ECC_AES_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_ECC_AES_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_CHECK_OWNER_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_CHECK_OWNER_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_MEM_BURST_LENGTH_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_MEM_BURST_LENGTH_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_PAGE_BOUND_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_PAGE_BOUND_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_RST_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_RST_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_CMD_DISABLE_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_CMD_DISABLE_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetIN_CONF0_CH2_IN_ARB_WEIGHT_OPT_DIS_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH2.Reg, volatile.LoadUint32(&o.IN_CONF0_CH2.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH2_IN_ARB_WEIGHT_OPT_DIS_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH2.Reg) & 0x4000000) >> 26
}

// H264_DMA.IN_INT_RAW_CH2: RX CH2 interrupt raw register
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DONE_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DONE_CH2_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_SUC_EOF_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_SUC_EOF_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_ERR_EOF_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_ERR_EOF_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_ERR_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_ERR_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_L1_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_L1_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_L1_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_L1_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_OVF_L2_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_OVF_L2_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_INFIFO_UDF_L2_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_INFIFO_UDF_L2_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_EMPTY_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH2_IN_DSCR_TASK_OVF_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH2.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH2_IN_DSCR_TASK_OVF_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH2.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ENA_CH2: RX CH2 interrupt ena register
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DONE_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DONE_CH2_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_SUC_EOF_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_SUC_EOF_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_ERR_EOF_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_ERR_EOF_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_ERR_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_ERR_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_L1_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_L1_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_L1_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_L1_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_OVF_L2_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_OVF_L2_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_INFIFO_UDF_L2_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_INFIFO_UDF_L2_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_EMPTY_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH2_IN_DSCR_TASK_OVF_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH2_IN_DSCR_TASK_OVF_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH2.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ST_CH2: RX CH2 interrupt st register
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DONE_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DONE_CH2_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_SUC_EOF_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_SUC_EOF_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_ERR_EOF_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_ERR_EOF_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_ERR_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_ERR_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_L1_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_L1_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_L1_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_L1_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_OVF_L2_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_OVF_L2_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_INFIFO_UDF_L2_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_INFIFO_UDF_L2_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_EMPTY_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH2_IN_DSCR_TASK_OVF_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH2.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH2_IN_DSCR_TASK_OVF_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH2.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_CLR_CH2: RX CH2 interrupt clr register
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DONE_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DONE_CH2_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_SUC_EOF_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_SUC_EOF_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_ERR_EOF_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_ERR_EOF_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_ERR_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_ERR_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_L1_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_L1_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_L1_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_L1_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_OVF_L2_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_OVF_L2_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_INFIFO_UDF_L2_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_INFIFO_UDF_L2_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_EMPTY_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH2_IN_DSCR_TASK_OVF_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH2.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH2_IN_DSCR_TASK_OVF_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH2.Reg) & 0x200) >> 9
}

// H264_DMA.INFIFO_STATUS_CH2: RX CH2 INFIFO status register
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L2_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L2_CH2() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L2_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L2_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L2_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L2_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L1_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L1_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L1_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L1_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L1_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L1_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_FULL_L3_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_FULL_L3_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_EMPTY_L3_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_EMPTY_L3_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH2_INFIFO_CNT_L3_CH2(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH2.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH2_INFIFO_CNT_L3_CH2() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH2.Reg) & 0xc0000) >> 18
}

// H264_DMA.IN_POP_CH2: RX CH2 INFIFO pop register
func (o *H264_DMA_Type) SetIN_POP_CH2_INFIFO_RDATA_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x7ff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_CH2_INFIFO_RDATA_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x7ff
}
func (o *H264_DMA_Type) SetIN_POP_CH2_INFIFO_POP_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH2.Reg, volatile.LoadUint32(&o.IN_POP_CH2.Reg)&^(0x800)|value<<11)
}
func (o *H264_DMA_Type) GetIN_POP_CH2_INFIFO_POP_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH2.Reg) & 0x800) >> 11
}

// H264_DMA.IN_LINK_CONF_CH2: RX CH2 in_link dscr ctrl register
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_AUTO_RET_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_AUTO_RET_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_STOP_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_STOP_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_START_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_START_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_RESTART_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_RESTART_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x800000) >> 23
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH2_INLINK_PARK_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH2_INLINK_PARK_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH2.Reg) & 0x1000000) >> 24
}

// H264_DMA.IN_LINK_ADDR_CH2: RX CH2 in_link dscr addr register
func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH2.Reg)
}

// H264_DMA.IN_STATE_CH2: RX CH2 state register
func (o *H264_DMA_Type) SetIN_STATE_CH2_INLINK_DSCR_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetIN_STATE_CH2_INLINK_DSCR_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetIN_STATE_CH2_IN_DSCR_STATE_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetIN_STATE_CH2_IN_DSCR_STATE_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetIN_STATE_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x700000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_STATE_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x700000) >> 20
}
func (o *H264_DMA_Type) SetIN_STATE_CH2_IN_RESET_AVAIL_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH2.Reg, volatile.LoadUint32(&o.IN_STATE_CH2.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_STATE_CH2_IN_RESET_AVAIL_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH2.Reg) & 0x800000) >> 23
}

// H264_DMA.IN_SUC_EOF_DES_ADDR_CH2: RX CH2 eof des addr register
func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH2.Reg)
}

// H264_DMA.IN_ERR_EOF_DES_ADDR_CH2: RX CH2 err eof des addr register
func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH2.Reg)
}

// H264_DMA.IN_DSCR_CH2: RX CH2 next dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH2.Reg)
}

// H264_DMA.IN_DSCR_BF0_CH2: RX CH2 last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH2.Reg)
}

// H264_DMA.IN_DSCR_BF1_CH2: RX CH2 second-to-last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH2.Reg)
}

// H264_DMA.IN_ARB_CH2: RX CH2 arb register
func (o *H264_DMA_Type) SetIN_ARB_CH2_IN_ARB_TOKEN_NUM_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH2.Reg, volatile.LoadUint32(&o.IN_ARB_CH2.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetIN_ARB_CH2_IN_ARB_TOKEN_NUM_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_ARB_CH2.Reg) & 0xf
}
func (o *H264_DMA_Type) SetIN_ARB_CH2_INTER_IN_ARB_PRIORITY_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH2.Reg, volatile.LoadUint32(&o.IN_ARB_CH2.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_ARB_CH2_INTER_IN_ARB_PRIORITY_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH2.Reg) & 0x1c0) >> 6
}

// H264_DMA.IN_ETM_CONF_CH2: RX CH2 ETM config register
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH2_IN_ETM_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH2_IN_ETM_EN_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH2_IN_ETM_LOOP_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH2_IN_ETM_LOOP_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH2_IN_DSCR_TASK_MAK_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH2.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH2_IN_DSCR_TASK_MAK_CH2() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH2.Reg) & 0xc) >> 2
}

// H264_DMA.IN_FIFO_CNT_CH2: rx CH2 fifo cnt register
func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH2_IN_CMDFIFO_INFIFO_CNT_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_FIFO_CNT_CH2.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH2.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH2_IN_CMDFIFO_INFIFO_CNT_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_FIFO_CNT_CH2.Reg) & 0x3ff
}

// H264_DMA.IN_POP_DATA_CNT_CH2: rx CH2 pop data cnt register
func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH2_IN_CMDFIFO_POP_DATA_CNT_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH2.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH2.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH2_IN_CMDFIFO_POP_DATA_CNT_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH2.Reg) & 0xff
}

// H264_DMA.IN_XADDR_CH2: rx CH2 xaddr register
func (o *H264_DMA_Type) SetIN_XADDR_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_XADDR_CH2.Reg, value)
}
func (o *H264_DMA_Type) GetIN_XADDR_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_XADDR_CH2.Reg)
}

// H264_DMA.IN_BUF_HB_RCV_CH2: rx CH2 buf len hb rcv register
func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH2_IN_CMDFIFO_BUF_HB_RCV_CH2(value uint32) {
	volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH2.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH2.Reg)&^(0x1fffffff)|value)
}
func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH2_IN_CMDFIFO_BUF_HB_RCV_CH2() uint32 {
	return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH2.Reg) & 0x1fffffff
}

// H264_DMA.IN_CONF0_CH3: RX CH3 config0 register
func (o *H264_DMA_Type) SetIN_CONF0_CH3_INDSCR_BURST_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_INDSCR_BURST_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_ECC_AES_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_ECC_AES_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_CHECK_OWNER_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_CHECK_OWNER_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_MEM_BURST_LENGTH_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_MEM_BURST_LENGTH_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_PAGE_BOUND_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_PAGE_BOUND_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_RST_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_RST_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_CMD_DISABLE_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_CMD_DISABLE_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetIN_CONF0_CH3_IN_ARB_WEIGHT_OPT_DIS_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH3.Reg, volatile.LoadUint32(&o.IN_CONF0_CH3.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH3_IN_ARB_WEIGHT_OPT_DIS_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH3.Reg) & 0x4000000) >> 26
}

// H264_DMA.IN_INT_RAW_CH3: RX CH3 interrupt raw register
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DONE_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DONE_CH3_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_SUC_EOF_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_SUC_EOF_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_ERR_EOF_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_ERR_EOF_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_ERR_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_ERR_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_OVF_L1_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_OVF_L1_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_UDF_L1_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_UDF_L1_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_OVF_L2_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_OVF_L2_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_INFIFO_UDF_L2_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_INFIFO_UDF_L2_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_EMPTY_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_EMPTY_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH3_IN_DSCR_TASK_OVF_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH3.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH3_IN_DSCR_TASK_OVF_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH3.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ENA_CH3: RX CH3 interrupt ena register
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DONE_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DONE_CH3_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_SUC_EOF_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_SUC_EOF_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_ERR_EOF_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_ERR_EOF_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_ERR_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_ERR_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_OVF_L1_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_OVF_L1_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_UDF_L1_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_UDF_L1_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_OVF_L2_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_OVF_L2_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_INFIFO_UDF_L2_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_INFIFO_UDF_L2_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_EMPTY_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_EMPTY_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH3_IN_DSCR_TASK_OVF_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH3_IN_DSCR_TASK_OVF_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH3.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ST_CH3: RX CH3 interrupt st register
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DONE_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DONE_CH3_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_SUC_EOF_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_SUC_EOF_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_ERR_EOF_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_ERR_EOF_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_ERR_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_ERR_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_OVF_L1_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_OVF_L1_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_UDF_L1_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_UDF_L1_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_OVF_L2_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_OVF_L2_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_INFIFO_UDF_L2_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_INFIFO_UDF_L2_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_EMPTY_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_EMPTY_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH3_IN_DSCR_TASK_OVF_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH3.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH3_IN_DSCR_TASK_OVF_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH3.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_CLR_CH3: RX CH3 interrupt clr register
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DONE_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DONE_CH3_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_SUC_EOF_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_SUC_EOF_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_ERR_EOF_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_ERR_EOF_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_ERR_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_ERR_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_OVF_L1_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_OVF_L1_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_UDF_L1_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_UDF_L1_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_OVF_L2_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_OVF_L2_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_INFIFO_UDF_L2_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_INFIFO_UDF_L2_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_EMPTY_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_EMPTY_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH3_IN_DSCR_TASK_OVF_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH3.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH3_IN_DSCR_TASK_OVF_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH3.Reg) & 0x200) >> 9
}

// H264_DMA.INFIFO_STATUS_CH3: RX CH3 INFIFO status register
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L2_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L2_CH3() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L2_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L2_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L2_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L2_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L1_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L1_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L1_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L1_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L1_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L1_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_FULL_L3_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_FULL_L3_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_EMPTY_L3_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_EMPTY_L3_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH3_INFIFO_CNT_L3_CH3(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH3.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH3_INFIFO_CNT_L3_CH3() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH3.Reg) & 0xc0000) >> 18
}

// H264_DMA.IN_POP_CH3: RX CH3 INFIFO pop register
func (o *H264_DMA_Type) SetIN_POP_CH3_INFIFO_RDATA_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH3.Reg, volatile.LoadUint32(&o.IN_POP_CH3.Reg)&^(0x7ff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_CH3_INFIFO_RDATA_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH3.Reg) & 0x7ff
}
func (o *H264_DMA_Type) SetIN_POP_CH3_INFIFO_POP_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH3.Reg, volatile.LoadUint32(&o.IN_POP_CH3.Reg)&^(0x800)|value<<11)
}
func (o *H264_DMA_Type) GetIN_POP_CH3_INFIFO_POP_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH3.Reg) & 0x800) >> 11
}

// H264_DMA.IN_LINK_CONF_CH3: RX CH3 in_link dscr ctrl register
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_AUTO_RET_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_AUTO_RET_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_STOP_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_STOP_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_START_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_START_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_RESTART_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_RESTART_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x800000) >> 23
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH3_INLINK_PARK_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH3_INLINK_PARK_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH3.Reg) & 0x1000000) >> 24
}

// H264_DMA.IN_LINK_ADDR_CH3: RX CH3 in_link dscr addr register
func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH3.Reg)
}

// H264_DMA.IN_STATE_CH3: RX CH3 state register
func (o *H264_DMA_Type) SetIN_STATE_CH3_INLINK_DSCR_ADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetIN_STATE_CH3_INLINK_DSCR_ADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetIN_STATE_CH3_IN_DSCR_STATE_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetIN_STATE_CH3_IN_DSCR_STATE_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetIN_STATE_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x700000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_STATE_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x700000) >> 20
}
func (o *H264_DMA_Type) SetIN_STATE_CH3_IN_RESET_AVAIL_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH3.Reg, volatile.LoadUint32(&o.IN_STATE_CH3.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_STATE_CH3_IN_RESET_AVAIL_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH3.Reg) & 0x800000) >> 23
}

// H264_DMA.IN_SUC_EOF_DES_ADDR_CH3: RX CH3 eof des addr register
func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH3.Reg)
}

// H264_DMA.IN_ERR_EOF_DES_ADDR_CH3: RX CH3 err eof des addr register
func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH3.Reg)
}

// H264_DMA.IN_DSCR_CH3: RX CH3 next dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH3.Reg)
}

// H264_DMA.IN_DSCR_BF0_CH3: RX CH3 last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH3.Reg)
}

// H264_DMA.IN_DSCR_BF1_CH3: RX CH3 second-to-last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH3.Reg)
}

// H264_DMA.IN_ARB_CH3: RX CH3 arb register
func (o *H264_DMA_Type) SetIN_ARB_CH3_IN_ARB_TOKEN_NUM_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH3.Reg, volatile.LoadUint32(&o.IN_ARB_CH3.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetIN_ARB_CH3_IN_ARB_TOKEN_NUM_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_ARB_CH3.Reg) & 0xf
}
func (o *H264_DMA_Type) SetIN_ARB_CH3_INTER_IN_ARB_PRIORITY_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH3.Reg, volatile.LoadUint32(&o.IN_ARB_CH3.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_ARB_CH3_INTER_IN_ARB_PRIORITY_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH3.Reg) & 0x1c0) >> 6
}

// H264_DMA.IN_ETM_CONF_CH3: RX CH3 ETM config register
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH3_IN_ETM_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH3_IN_ETM_EN_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH3_IN_ETM_LOOP_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH3_IN_ETM_LOOP_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH3_IN_DSCR_TASK_MAK_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH3.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH3_IN_DSCR_TASK_MAK_CH3() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH3.Reg) & 0xc) >> 2
}

// H264_DMA.IN_FIFO_CNT_CH3: rx CH3 fifo cnt register
func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH3_IN_CMDFIFO_INFIFO_CNT_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_FIFO_CNT_CH3.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH3.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH3_IN_CMDFIFO_INFIFO_CNT_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_FIFO_CNT_CH3.Reg) & 0x3ff
}

// H264_DMA.IN_POP_DATA_CNT_CH3: rx CH3 pop data cnt register
func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH3_IN_CMDFIFO_POP_DATA_CNT_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH3.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH3.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH3_IN_CMDFIFO_POP_DATA_CNT_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH3.Reg) & 0xff
}

// H264_DMA.IN_XADDR_CH3: rx CH3 xaddr register
func (o *H264_DMA_Type) SetIN_XADDR_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_XADDR_CH3.Reg, value)
}
func (o *H264_DMA_Type) GetIN_XADDR_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_XADDR_CH3.Reg)
}

// H264_DMA.IN_BUF_HB_RCV_CH3: rx CH3 buf len hb rcv register
func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH3_IN_CMDFIFO_BUF_HB_RCV_CH3(value uint32) {
	volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH3.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH3.Reg)&^(0x1fffffff)|value)
}
func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH3_IN_CMDFIFO_BUF_HB_RCV_CH3() uint32 {
	return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH3.Reg) & 0x1fffffff
}

// H264_DMA.IN_CONF0_CH4: RX CH4 config0 register
func (o *H264_DMA_Type) SetIN_CONF0_CH4_INDSCR_BURST_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_INDSCR_BURST_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_ECC_AES_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_ECC_AES_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_CHECK_OWNER_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_CHECK_OWNER_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_MEM_BURST_LENGTH_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_MEM_BURST_LENGTH_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_PAGE_BOUND_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_PAGE_BOUND_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_CMD_DISABLE_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_CMD_DISABLE_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x2000000) >> 25
}
func (o *H264_DMA_Type) SetIN_CONF0_CH4_IN_ARB_WEIGHT_OPT_DIS_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH4.Reg, volatile.LoadUint32(&o.IN_CONF0_CH4.Reg)&^(0x4000000)|value<<26)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH4_IN_ARB_WEIGHT_OPT_DIS_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH4.Reg) & 0x4000000) >> 26
}

// H264_DMA.IN_INT_RAW_CH4: RX CH4 interrupt raw register
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DONE_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DONE_CH4_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_SUC_EOF_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_SUC_EOF_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_ERR_EOF_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_ERR_EOF_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_ERR_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_ERR_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_OVF_L1_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_OVF_L1_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_UDF_L1_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_UDF_L1_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_OVF_L2_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_OVF_L2_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_INFIFO_UDF_L2_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_INFIFO_UDF_L2_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_EMPTY_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_EMPTY_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH4_IN_DSCR_TASK_OVF_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH4.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH4_IN_DSCR_TASK_OVF_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH4.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ENA_CH4: RX CH4 interrupt ena register
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DONE_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DONE_CH4_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_SUC_EOF_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_SUC_EOF_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_ERR_EOF_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_ERR_EOF_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_ERR_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_ERR_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_OVF_L1_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_OVF_L1_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_UDF_L1_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_UDF_L1_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_OVF_L2_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_OVF_L2_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_INFIFO_UDF_L2_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_INFIFO_UDF_L2_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_EMPTY_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_EMPTY_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH4_IN_DSCR_TASK_OVF_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH4_IN_DSCR_TASK_OVF_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH4.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_ST_CH4: RX CH4 interrupt st register
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DONE_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DONE_CH4_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_SUC_EOF_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_SUC_EOF_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_ERR_EOF_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_ERR_EOF_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_ERR_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_ERR_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_OVF_L1_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_OVF_L1_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_UDF_L1_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_UDF_L1_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_OVF_L2_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_OVF_L2_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_INFIFO_UDF_L2_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_INFIFO_UDF_L2_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_EMPTY_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_EMPTY_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH4_IN_DSCR_TASK_OVF_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH4.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH4_IN_DSCR_TASK_OVF_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH4.Reg) & 0x200) >> 9
}

// H264_DMA.IN_INT_CLR_CH4: RX CH4 interrupt clr register
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DONE_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DONE_CH4_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_SUC_EOF_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_SUC_EOF_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_ERR_EOF_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_ERR_EOF_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_ERR_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_ERR_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_OVF_L1_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_OVF_L1_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x10) >> 4
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_UDF_L1_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x20)|value<<5)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_UDF_L1_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x20) >> 5
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_OVF_L2_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_OVF_L2_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_INFIFO_UDF_L2_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_INFIFO_UDF_L2_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_EMPTY_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x100)|value<<8)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_EMPTY_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x100) >> 8
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH4_IN_DSCR_TASK_OVF_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH4.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg)&^(0x200)|value<<9)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH4_IN_DSCR_TASK_OVF_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH4.Reg) & 0x200) >> 9
}

// H264_DMA.INFIFO_STATUS_CH4: RX CH4 INFIFO status register
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L2_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L2_CH4() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L2_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L2_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L2_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x3c)|value<<2)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L2_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x3c) >> 2
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L1_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x40)|value<<6)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L1_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x40) >> 6
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L1_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x80)|value<<7)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L1_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x80) >> 7
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L1_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x1f00)|value<<8)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L1_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x1f00) >> 8
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_FULL_L3_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_FULL_L3_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x10000) >> 16
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_EMPTY_L3_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0x20000)|value<<17)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_EMPTY_L3_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0x20000) >> 17
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH4_INFIFO_CNT_L3_CH4(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH4.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH4_INFIFO_CNT_L3_CH4() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH4.Reg) & 0xc0000) >> 18
}

// H264_DMA.IN_POP_CH4: RX CH4 INFIFO pop register
func (o *H264_DMA_Type) SetIN_POP_CH4_INFIFO_RDATA_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH4.Reg, volatile.LoadUint32(&o.IN_POP_CH4.Reg)&^(0x7ff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_CH4_INFIFO_RDATA_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH4.Reg) & 0x7ff
}
func (o *H264_DMA_Type) SetIN_POP_CH4_INFIFO_POP_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH4.Reg, volatile.LoadUint32(&o.IN_POP_CH4.Reg)&^(0x800)|value<<11)
}
func (o *H264_DMA_Type) GetIN_POP_CH4_INFIFO_POP_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH4.Reg) & 0x800) >> 11
}

// H264_DMA.IN_LINK_CONF_CH4: RX CH4 in_link dscr ctrl register
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_AUTO_RET_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x100000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_AUTO_RET_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x100000) >> 20
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_STOP_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x200000)|value<<21)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_STOP_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x200000) >> 21
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_START_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x400000)|value<<22)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_START_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x400000) >> 22
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_RESTART_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_RESTART_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x800000) >> 23
}
func (o *H264_DMA_Type) SetIN_LINK_CONF_CH4_INLINK_PARK_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_LINK_CONF_CH4_INLINK_PARK_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_LINK_CONF_CH4.Reg) & 0x1000000) >> 24
}

// H264_DMA.IN_LINK_ADDR_CH4: RX CH4 in_link dscr addr register
func (o *H264_DMA_Type) SetIN_LINK_ADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_LINK_ADDR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetIN_LINK_ADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_LINK_ADDR_CH4.Reg)
}

// H264_DMA.IN_STATE_CH4: RX CH4 state register
func (o *H264_DMA_Type) SetIN_STATE_CH4_INLINK_DSCR_ADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x3ffff)|value)
}
func (o *H264_DMA_Type) GetIN_STATE_CH4_INLINK_DSCR_ADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x3ffff
}
func (o *H264_DMA_Type) SetIN_STATE_CH4_IN_DSCR_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0xc0000)|value<<18)
}
func (o *H264_DMA_Type) GetIN_STATE_CH4_IN_DSCR_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0xc0000) >> 18
}
func (o *H264_DMA_Type) SetIN_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x700000)|value<<20)
}
func (o *H264_DMA_Type) GetIN_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x700000) >> 20
}
func (o *H264_DMA_Type) SetIN_STATE_CH4_IN_RESET_AVAIL_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH4.Reg, volatile.LoadUint32(&o.IN_STATE_CH4.Reg)&^(0x800000)|value<<23)
}
func (o *H264_DMA_Type) GetIN_STATE_CH4_IN_RESET_AVAIL_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH4.Reg) & 0x800000) >> 23
}

// H264_DMA.IN_SUC_EOF_DES_ADDR_CH4: RX CH4 eof des addr register
func (o *H264_DMA_Type) SetIN_SUC_EOF_DES_ADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_SUC_EOF_DES_ADDR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetIN_SUC_EOF_DES_ADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_SUC_EOF_DES_ADDR_CH4.Reg)
}

// H264_DMA.IN_ERR_EOF_DES_ADDR_CH4: RX CH4 err eof des addr register
func (o *H264_DMA_Type) SetIN_ERR_EOF_DES_ADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_ERR_EOF_DES_ADDR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetIN_ERR_EOF_DES_ADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_ERR_EOF_DES_ADDR_CH4.Reg)
}

// H264_DMA.IN_DSCR_CH4: RX CH4 next dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_CH4.Reg)
}

// H264_DMA.IN_DSCR_BF0_CH4: RX CH4 last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF0_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF0_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF0_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF0_CH4.Reg)
}

// H264_DMA.IN_DSCR_BF1_CH4: RX CH4 second-to-last dscr addr register
func (o *H264_DMA_Type) SetIN_DSCR_BF1_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_DSCR_BF1_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetIN_DSCR_BF1_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_DSCR_BF1_CH4.Reg)
}

// H264_DMA.IN_ARB_CH4: RX CH4 arb register
func (o *H264_DMA_Type) SetIN_ARB_CH4_IN_ARB_TOKEN_NUM_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH4.Reg, volatile.LoadUint32(&o.IN_ARB_CH4.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetIN_ARB_CH4_IN_ARB_TOKEN_NUM_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_ARB_CH4.Reg) & 0xf
}
func (o *H264_DMA_Type) SetIN_ARB_CH4_EXTER_IN_ARB_PRIORITY_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH4.Reg, volatile.LoadUint32(&o.IN_ARB_CH4.Reg)&^(0x30)|value<<4)
}
func (o *H264_DMA_Type) GetIN_ARB_CH4_EXTER_IN_ARB_PRIORITY_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH4.Reg) & 0x30) >> 4
}
func (o *H264_DMA_Type) SetIN_ARB_CH4_INTER_IN_ARB_PRIORITY_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH4.Reg, volatile.LoadUint32(&o.IN_ARB_CH4.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_ARB_CH4_INTER_IN_ARB_PRIORITY_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH4.Reg) & 0x1c0) >> 6
}

// H264_DMA.IN_ETM_CONF_CH4: RX CH4 ETM config register
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH4_IN_ETM_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH4_IN_ETM_EN_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH4_IN_ETM_LOOP_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH4_IN_ETM_LOOP_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_ETM_CONF_CH4_IN_DSCR_TASK_MAK_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_ETM_CONF_CH4.Reg, volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg)&^(0xc)|value<<2)
}
func (o *H264_DMA_Type) GetIN_ETM_CONF_CH4_IN_DSCR_TASK_MAK_CH4() uint32 {
	return (volatile.LoadUint32(&o.IN_ETM_CONF_CH4.Reg) & 0xc) >> 2
}

// H264_DMA.IN_FIFO_CNT_CH4: rx CH4 fifo cnt register
func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH4_IN_CMDFIFO_INFIFO_CNT_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_FIFO_CNT_CH4.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH4.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH4_IN_CMDFIFO_INFIFO_CNT_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_FIFO_CNT_CH4.Reg) & 0x3ff
}

// H264_DMA.IN_POP_DATA_CNT_CH4: rx CH4 pop data cnt register
func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH4_IN_CMDFIFO_POP_DATA_CNT_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH4.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH4.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH4_IN_CMDFIFO_POP_DATA_CNT_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH4.Reg) & 0xff
}

// H264_DMA.IN_XADDR_CH4: rx CH4 xaddr register
func (o *H264_DMA_Type) SetIN_XADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_XADDR_CH4.Reg, value)
}
func (o *H264_DMA_Type) GetIN_XADDR_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_XADDR_CH4.Reg)
}

// H264_DMA.IN_BUF_HB_RCV_CH4: rx CH4 buf len hb rcv register
func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH4_IN_CMDFIFO_BUF_HB_RCV_CH4(value uint32) {
	volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH4.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH4.Reg)&^(0x1fffffff)|value)
}
func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH4_IN_CMDFIFO_BUF_HB_RCV_CH4() uint32 {
	return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH4.Reg) & 0x1fffffff
}

// H264_DMA.IN_CONF0_CH5: RX CH5 config0 register
func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_ECC_AES_EN_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_ECC_AES_EN_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_MEM_BURST_LENGTH_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_MEM_BURST_LENGTH_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x1c0) >> 6
}
func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_PAGE_BOUND_EN_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x1000)|value<<12)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_PAGE_BOUND_EN_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x1000) >> 12
}
func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_RST_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x1000000)|value<<24)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_RST_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x1000000) >> 24
}
func (o *H264_DMA_Type) SetIN_CONF0_CH5_IN_CMD_DISABLE_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF0_CH5.Reg, volatile.LoadUint32(&o.IN_CONF0_CH5.Reg)&^(0x2000000)|value<<25)
}
func (o *H264_DMA_Type) GetIN_CONF0_CH5_IN_CMD_DISABLE_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF0_CH5.Reg) & 0x2000000) >> 25
}

// H264_DMA.IN_CONF1_CH5: RX CH5 config1 register
func (o *H264_DMA_Type) SetIN_CONF1_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF1_CH5.Reg, value)
}
func (o *H264_DMA_Type) GetIN_CONF1_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_CONF1_CH5.Reg)
}

// H264_DMA.IN_CONF2_CH5: RX CH5 config2 register
func (o *H264_DMA_Type) SetIN_CONF2_CH5_BLOCK_ROW_LENGTH_12LINE_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF2_CH5.Reg, volatile.LoadUint32(&o.IN_CONF2_CH5.Reg)&^(0xffff)|value)
}
func (o *H264_DMA_Type) GetIN_CONF2_CH5_BLOCK_ROW_LENGTH_12LINE_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_CONF2_CH5.Reg) & 0xffff
}
func (o *H264_DMA_Type) SetIN_CONF2_CH5_BLOCK_ROW_LENGTH_4LINE_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF2_CH5.Reg, volatile.LoadUint32(&o.IN_CONF2_CH5.Reg)&^(0xffff0000)|value<<16)
}
func (o *H264_DMA_Type) GetIN_CONF2_CH5_BLOCK_ROW_LENGTH_4LINE_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF2_CH5.Reg) & 0xffff0000) >> 16
}

// H264_DMA.IN_CONF3_CH5: RX CH5 config3 register
func (o *H264_DMA_Type) SetIN_CONF3_CH5_BLOCK_LENGTH_12LINE_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF3_CH5.Reg, volatile.LoadUint32(&o.IN_CONF3_CH5.Reg)&^(0x3fff)|value)
}
func (o *H264_DMA_Type) GetIN_CONF3_CH5_BLOCK_LENGTH_12LINE_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_CONF3_CH5.Reg) & 0x3fff
}
func (o *H264_DMA_Type) SetIN_CONF3_CH5_BLOCK_LENGTH_4LINE_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_CONF3_CH5.Reg, volatile.LoadUint32(&o.IN_CONF3_CH5.Reg)&^(0xfffc000)|value<<14)
}
func (o *H264_DMA_Type) GetIN_CONF3_CH5_BLOCK_LENGTH_4LINE_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_CONF3_CH5.Reg) & 0xfffc000) >> 14
}

// H264_DMA.IN_INT_RAW_CH5: RX CH5 interrupt raw register
func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_IN_DONE_CH5_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_IN_DONE_CH5_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_IN_SUC_EOF_CH5_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_IN_SUC_EOF_CH5_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_INFIFO_OVF_L1_CH5_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_INFIFO_OVF_L1_CH5_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_INFIFO_UDF_L1_CH5_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_INFIFO_UDF_L1_CH5_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_RAW_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.IN_INT_RAW_CH5.Reg, volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_RAW_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_RAW_CH5.Reg) & 0x10) >> 4
}

// H264_DMA.IN_INT_ENA_CH5: RX CH5 interrupt ena register
func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_IN_DONE_CH5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_IN_DONE_CH5_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_IN_SUC_EOF_CH5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_IN_SUC_EOF_CH5_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_INFIFO_OVF_L1_CH5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_INFIFO_OVF_L1_CH5_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_INFIFO_UDF_L1_CH5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_INFIFO_UDF_L1_CH5_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ENA_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ENA_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ENA_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ENA_CH5.Reg) & 0x10) >> 4
}

// H264_DMA.IN_INT_ST_CH5: RX CH5 interrupt st register
func (o *H264_DMA_Type) SetIN_INT_ST_CH5_IN_DONE_CH5_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH5_IN_DONE_CH5_INT_ST() uint32 {
	return volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH5_IN_SUC_EOF_CH5_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH5_IN_SUC_EOF_CH5_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH5_INFIFO_OVF_L1_CH5_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH5_INFIFO_OVF_L1_CH5_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH5_INFIFO_UDF_L1_CH5_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH5_INFIFO_UDF_L1_CH5_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_ST_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ST(value uint32) {
	volatile.StoreUint32(&o.IN_INT_ST_CH5.Reg, volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_ST_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_ST_CH5.Reg) & 0x10) >> 4
}

// H264_DMA.IN_INT_CLR_CH5: RX CH5 interrupt clr register
func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_IN_DONE_CH5_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_IN_DONE_CH5_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_IN_SUC_EOF_CH5_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_IN_SUC_EOF_CH5_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_INFIFO_OVF_L1_CH5_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_INFIFO_OVF_L1_CH5_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_INFIFO_UDF_L1_CH5_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_INFIFO_UDF_L1_CH5_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetIN_INT_CLR_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.IN_INT_CLR_CH5.Reg, volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetIN_INT_CLR_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.IN_INT_CLR_CH5.Reg) & 0x10) >> 4
}

// H264_DMA.INFIFO_STATUS_CH5: RX CH5 INFIFO status register
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH5_INFIFO_FULL_L1_CH5(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH5.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH5_INFIFO_FULL_L1_CH5() uint32 {
	return volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg) & 0x1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH5_INFIFO_EMPTY_L1_CH5(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH5.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH5_INFIFO_EMPTY_L1_CH5() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetINFIFO_STATUS_CH5_INFIFO_CNT_L1_CH5(value uint32) {
	volatile.StoreUint32(&o.INFIFO_STATUS_CH5.Reg, volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg)&^(0x7c)|value<<2)
}
func (o *H264_DMA_Type) GetINFIFO_STATUS_CH5_INFIFO_CNT_L1_CH5() uint32 {
	return (volatile.LoadUint32(&o.INFIFO_STATUS_CH5.Reg) & 0x7c) >> 2
}

// H264_DMA.IN_POP_CH5: RX CH5 INFIFO pop register
func (o *H264_DMA_Type) SetIN_POP_CH5_INFIFO_RDATA_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH5.Reg, volatile.LoadUint32(&o.IN_POP_CH5.Reg)&^(0x7ff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_CH5_INFIFO_RDATA_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_POP_CH5.Reg) & 0x7ff
}
func (o *H264_DMA_Type) SetIN_POP_CH5_INFIFO_POP_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_POP_CH5.Reg, volatile.LoadUint32(&o.IN_POP_CH5.Reg)&^(0x800)|value<<11)
}
func (o *H264_DMA_Type) GetIN_POP_CH5_INFIFO_POP_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_POP_CH5.Reg) & 0x800) >> 11
}

// H264_DMA.IN_STATE_CH5: RX CH5 state register
func (o *H264_DMA_Type) SetIN_STATE_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH5.Reg, volatile.LoadUint32(&o.IN_STATE_CH5.Reg)&^(0x7)|value)
}
func (o *H264_DMA_Type) GetIN_STATE_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_STATE_CH5.Reg) & 0x7
}
func (o *H264_DMA_Type) SetIN_STATE_CH5_IN_RESET_AVAIL_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_STATE_CH5.Reg, volatile.LoadUint32(&o.IN_STATE_CH5.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetIN_STATE_CH5_IN_RESET_AVAIL_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_STATE_CH5.Reg) & 0x8) >> 3
}

// H264_DMA.IN_ARB_CH5: RX CH5 arb register
func (o *H264_DMA_Type) SetIN_ARB_CH5_IN_ARB_TOKEN_NUM_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH5.Reg, volatile.LoadUint32(&o.IN_ARB_CH5.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetIN_ARB_CH5_IN_ARB_TOKEN_NUM_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_ARB_CH5.Reg) & 0xf
}
func (o *H264_DMA_Type) SetIN_ARB_CH5_INTER_IN_ARB_PRIORITY_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CH5.Reg, volatile.LoadUint32(&o.IN_ARB_CH5.Reg)&^(0x1c0)|value<<6)
}
func (o *H264_DMA_Type) GetIN_ARB_CH5_INTER_IN_ARB_PRIORITY_CH5() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CH5.Reg) & 0x1c0) >> 6
}

// H264_DMA.IN_FIFO_CNT_CH5: rx CH5 fifo cnt register
func (o *H264_DMA_Type) SetIN_FIFO_CNT_CH5_IN_CMDFIFO_INFIFO_CNT_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_FIFO_CNT_CH5.Reg, volatile.LoadUint32(&o.IN_FIFO_CNT_CH5.Reg)&^(0x3ff)|value)
}
func (o *H264_DMA_Type) GetIN_FIFO_CNT_CH5_IN_CMDFIFO_INFIFO_CNT_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_FIFO_CNT_CH5.Reg) & 0x3ff
}

// H264_DMA.IN_POP_DATA_CNT_CH5: rx CH5 pop data cnt register
func (o *H264_DMA_Type) SetIN_POP_DATA_CNT_CH5_IN_CMDFIFO_POP_DATA_CNT_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_POP_DATA_CNT_CH5.Reg, volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH5.Reg)&^(0xff)|value)
}
func (o *H264_DMA_Type) GetIN_POP_DATA_CNT_CH5_IN_CMDFIFO_POP_DATA_CNT_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_POP_DATA_CNT_CH5.Reg) & 0xff
}

// H264_DMA.IN_XADDR_CH5: rx CH5 xaddr register
func (o *H264_DMA_Type) SetIN_XADDR_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_XADDR_CH5.Reg, value)
}
func (o *H264_DMA_Type) GetIN_XADDR_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_XADDR_CH5.Reg)
}

// H264_DMA.IN_BUF_HB_RCV_CH5: rx CH5 buf len hb rcv register
func (o *H264_DMA_Type) SetIN_BUF_HB_RCV_CH5_IN_CMDFIFO_BUF_HB_RCV_CH5(value uint32) {
	volatile.StoreUint32(&o.IN_BUF_HB_RCV_CH5.Reg, volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH5.Reg)&^(0x1fffffff)|value)
}
func (o *H264_DMA_Type) GetIN_BUF_HB_RCV_CH5_IN_CMDFIFO_BUF_HB_RCV_CH5() uint32 {
	return volatile.LoadUint32(&o.IN_BUF_HB_RCV_CH5.Reg) & 0x1fffffff
}

// H264_DMA.INTER_AXI_ERR: inter memory axi err register
func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RID_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RID_ERR_CNT() uint32 {
	return volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0xf
}
func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RRESP_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0xf0)|value<<4)
}
func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RRESP_ERR_CNT() uint32 {
	return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0xf0) >> 4
}
func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_WRESP_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0xf00)|value<<8)
}
func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_WRESP_ERR_CNT() uint32 {
	return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0xf00) >> 8
}
func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RD_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x7000)|value<<12)
}
func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RD_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x7000) >> 12
}
func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_RD_BAK_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x78000)|value<<15)
}
func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_RD_BAK_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x78000) >> 15
}
func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_WR_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x380000)|value<<19)
}
func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_WR_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x380000) >> 19
}
func (o *H264_DMA_Type) SetINTER_AXI_ERR_INTER_WR_BAK_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.INTER_AXI_ERR.Reg, volatile.LoadUint32(&o.INTER_AXI_ERR.Reg)&^(0x3c00000)|value<<22)
}
func (o *H264_DMA_Type) GetINTER_AXI_ERR_INTER_WR_BAK_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.INTER_AXI_ERR.Reg) & 0x3c00000) >> 22
}

// H264_DMA.EXTER_AXI_ERR: exter memory axi err register
func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RID_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0xf)|value)
}
func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RID_ERR_CNT() uint32 {
	return volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0xf
}
func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RRESP_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0xf0)|value<<4)
}
func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RRESP_ERR_CNT() uint32 {
	return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0xf0) >> 4
}
func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_WRESP_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0xf00)|value<<8)
}
func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_WRESP_ERR_CNT() uint32 {
	return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0xf00) >> 8
}
func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RD_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x7000)|value<<12)
}
func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RD_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x7000) >> 12
}
func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_RD_BAK_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x78000)|value<<15)
}
func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_RD_BAK_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x78000) >> 15
}
func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_WR_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x380000)|value<<19)
}
func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_WR_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x380000) >> 19
}
func (o *H264_DMA_Type) SetEXTER_AXI_ERR_EXTER_WR_BAK_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.EXTER_AXI_ERR.Reg, volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg)&^(0x3c00000)|value<<22)
}
func (o *H264_DMA_Type) GetEXTER_AXI_ERR_EXTER_WR_BAK_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.EXTER_AXI_ERR.Reg) & 0x3c00000) >> 22
}

// H264_DMA.RST_CONF: axi reset config register
func (o *H264_DMA_Type) SetRST_CONF_INTER_AXIM_RD_RST(value uint32) {
	volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetRST_CONF_INTER_AXIM_RD_RST() uint32 {
	return volatile.LoadUint32(&o.RST_CONF.Reg) & 0x1
}
func (o *H264_DMA_Type) SetRST_CONF_INTER_AXIM_WR_RST(value uint32) {
	volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetRST_CONF_INTER_AXIM_WR_RST() uint32 {
	return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetRST_CONF_EXTER_AXIM_RD_RST(value uint32) {
	volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetRST_CONF_EXTER_AXIM_RD_RST() uint32 {
	return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetRST_CONF_EXTER_AXIM_WR_RST(value uint32) {
	volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetRST_CONF_EXTER_AXIM_WR_RST() uint32 {
	return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x8) >> 3
}
func (o *H264_DMA_Type) SetRST_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.RST_CONF.Reg, volatile.LoadUint32(&o.RST_CONF.Reg)&^(0x10)|value<<4)
}
func (o *H264_DMA_Type) GetRST_CONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.RST_CONF.Reg) & 0x10) >> 4
}

// H264_DMA.INTER_MEM_START_ADDR0: Start address of inter memory range0 register
func (o *H264_DMA_Type) SetINTER_MEM_START_ADDR0(value uint32) {
	volatile.StoreUint32(&o.INTER_MEM_START_ADDR0.Reg, value)
}
func (o *H264_DMA_Type) GetINTER_MEM_START_ADDR0() uint32 {
	return volatile.LoadUint32(&o.INTER_MEM_START_ADDR0.Reg)
}

// H264_DMA.INTER_MEM_END_ADDR0: end address of inter memory range0 register
func (o *H264_DMA_Type) SetINTER_MEM_END_ADDR0(value uint32) {
	volatile.StoreUint32(&o.INTER_MEM_END_ADDR0.Reg, value)
}
func (o *H264_DMA_Type) GetINTER_MEM_END_ADDR0() uint32 {
	return volatile.LoadUint32(&o.INTER_MEM_END_ADDR0.Reg)
}

// H264_DMA.INTER_MEM_START_ADDR1: Start address of inter memory range1 register
func (o *H264_DMA_Type) SetINTER_MEM_START_ADDR1(value uint32) {
	volatile.StoreUint32(&o.INTER_MEM_START_ADDR1.Reg, value)
}
func (o *H264_DMA_Type) GetINTER_MEM_START_ADDR1() uint32 {
	return volatile.LoadUint32(&o.INTER_MEM_START_ADDR1.Reg)
}

// H264_DMA.INTER_MEM_END_ADDR1: end address of inter memory range1 register
func (o *H264_DMA_Type) SetINTER_MEM_END_ADDR1(value uint32) {
	volatile.StoreUint32(&o.INTER_MEM_END_ADDR1.Reg, value)
}
func (o *H264_DMA_Type) GetINTER_MEM_END_ADDR1() uint32 {
	return volatile.LoadUint32(&o.INTER_MEM_END_ADDR1.Reg)
}

// H264_DMA.EXTER_MEM_START_ADDR0: Start address of exter memory range0 register
func (o *H264_DMA_Type) SetEXTER_MEM_START_ADDR0(value uint32) {
	volatile.StoreUint32(&o.EXTER_MEM_START_ADDR0.Reg, value)
}
func (o *H264_DMA_Type) GetEXTER_MEM_START_ADDR0() uint32 {
	return volatile.LoadUint32(&o.EXTER_MEM_START_ADDR0.Reg)
}

// H264_DMA.EXTER_MEM_END_ADDR0: end address of exter memory range0 register
func (o *H264_DMA_Type) SetEXTER_MEM_END_ADDR0(value uint32) {
	volatile.StoreUint32(&o.EXTER_MEM_END_ADDR0.Reg, value)
}
func (o *H264_DMA_Type) GetEXTER_MEM_END_ADDR0() uint32 {
	return volatile.LoadUint32(&o.EXTER_MEM_END_ADDR0.Reg)
}

// H264_DMA.EXTER_MEM_START_ADDR1: Start address of exter memory range1 register
func (o *H264_DMA_Type) SetEXTER_MEM_START_ADDR1(value uint32) {
	volatile.StoreUint32(&o.EXTER_MEM_START_ADDR1.Reg, value)
}
func (o *H264_DMA_Type) GetEXTER_MEM_START_ADDR1() uint32 {
	return volatile.LoadUint32(&o.EXTER_MEM_START_ADDR1.Reg)
}

// H264_DMA.EXTER_MEM_END_ADDR1: end address of exter memory range1 register
func (o *H264_DMA_Type) SetEXTER_MEM_END_ADDR1(value uint32) {
	volatile.StoreUint32(&o.EXTER_MEM_END_ADDR1.Reg, value)
}
func (o *H264_DMA_Type) GetEXTER_MEM_END_ADDR1() uint32 {
	return volatile.LoadUint32(&o.EXTER_MEM_END_ADDR1.Reg)
}

// H264_DMA.OUT_ARB_CONFIG: reserved
func (o *H264_DMA_Type) SetOUT_ARB_CONFIG_OUT_ARB_TIMEOUT_NUM(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CONFIG.Reg, volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg)&^(0xffff)|value)
}
func (o *H264_DMA_Type) GetOUT_ARB_CONFIG_OUT_ARB_TIMEOUT_NUM() uint32 {
	return volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg) & 0xffff
}
func (o *H264_DMA_Type) SetOUT_ARB_CONFIG_OUT_WEIGHT_EN(value uint32) {
	volatile.StoreUint32(&o.OUT_ARB_CONFIG.Reg, volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetOUT_ARB_CONFIG_OUT_WEIGHT_EN() uint32 {
	return (volatile.LoadUint32(&o.OUT_ARB_CONFIG.Reg) & 0x10000) >> 16
}

// H264_DMA.IN_ARB_CONFIG: reserved
func (o *H264_DMA_Type) SetIN_ARB_CONFIG_IN_ARB_TIMEOUT_NUM(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CONFIG.Reg, volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg)&^(0xffff)|value)
}
func (o *H264_DMA_Type) GetIN_ARB_CONFIG_IN_ARB_TIMEOUT_NUM() uint32 {
	return volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg) & 0xffff
}
func (o *H264_DMA_Type) SetIN_ARB_CONFIG_IN_WEIGHT_EN(value uint32) {
	volatile.StoreUint32(&o.IN_ARB_CONFIG.Reg, volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg)&^(0x10000)|value<<16)
}
func (o *H264_DMA_Type) GetIN_ARB_CONFIG_IN_WEIGHT_EN() uint32 {
	return (volatile.LoadUint32(&o.IN_ARB_CONFIG.Reg) & 0x10000) >> 16
}

// H264_DMA.DATE: reserved
func (o *H264_DMA_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *H264_DMA_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// H264_DMA.COUNTER_RST: counter reset register
func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH0_EXTER_COUNTER_RST(value uint32) {
	volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x1)|value)
}
func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH0_EXTER_COUNTER_RST() uint32 {
	return volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x1
}
func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH1_EXTER_COUNTER_RST(value uint32) {
	volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x2)|value<<1)
}
func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH1_EXTER_COUNTER_RST() uint32 {
	return (volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x2) >> 1
}
func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH2_INTER_COUNTER_RST(value uint32) {
	volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x4)|value<<2)
}
func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH2_INTER_COUNTER_RST() uint32 {
	return (volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x4) >> 2
}
func (o *H264_DMA_Type) SetCOUNTER_RST_RX_CH5_INTER_COUNTER_RST(value uint32) {
	volatile.StoreUint32(&o.COUNTER_RST.Reg, volatile.LoadUint32(&o.COUNTER_RST.Reg)&^(0x8)|value<<3)
}
func (o *H264_DMA_Type) GetCOUNTER_RST_RX_CH5_INTER_COUNTER_RST() uint32 {
	return (volatile.LoadUint32(&o.COUNTER_RST.Reg) & 0x8) >> 3
}

// H264_DMA.RX_CH0_COUNTER: rx ch0 counter register
func (o *H264_DMA_Type) SetRX_CH0_COUNTER_RX_CH0_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_CH0_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH0_COUNTER.Reg)&^(0x7fffff)|value)
}
func (o *H264_DMA_Type) GetRX_CH0_COUNTER_RX_CH0_CNT() uint32 {
	return volatile.LoadUint32(&o.RX_CH0_COUNTER.Reg) & 0x7fffff
}

// H264_DMA.RX_CH1_COUNTER: rx ch1 counter register
func (o *H264_DMA_Type) SetRX_CH1_COUNTER_RX_CH1_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_CH1_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH1_COUNTER.Reg)&^(0x1fffff)|value)
}
func (o *H264_DMA_Type) GetRX_CH1_COUNTER_RX_CH1_CNT() uint32 {
	return volatile.LoadUint32(&o.RX_CH1_COUNTER.Reg) & 0x1fffff
}

// H264_DMA.RX_CH2_COUNTER: rx ch2 counter register
func (o *H264_DMA_Type) SetRX_CH2_COUNTER_RX_CH2_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_CH2_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH2_COUNTER.Reg)&^(0x7ff)|value)
}
func (o *H264_DMA_Type) GetRX_CH2_COUNTER_RX_CH2_CNT() uint32 {
	return volatile.LoadUint32(&o.RX_CH2_COUNTER.Reg) & 0x7ff
}

// H264_DMA.RX_CH5_COUNTER: rx ch5 counter register
func (o *H264_DMA_Type) SetRX_CH5_COUNTER_RX_CH5_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_CH5_COUNTER.Reg, volatile.LoadUint32(&o.RX_CH5_COUNTER.Reg)&^(0x1ffff)|value)
}
func (o *H264_DMA_Type) GetRX_CH5_COUNTER_RX_CH5_CNT() uint32 {
	return volatile.LoadUint32(&o.RX_CH5_COUNTER.Reg) & 0x1ffff
}

// HMAC (Hash-based Message Authentication Code) Accelerator
type HMAC_Type struct {
	_                   [64]byte
	SET_START           volatile.Register32 // 0x40
	SET_PARA_PURPOSE    volatile.Register32 // 0x44
	SET_PARA_KEY        volatile.Register32 // 0x48
	SET_PARA_FINISH     volatile.Register32 // 0x4C
	SET_MESSAGE_ONE     volatile.Register32 // 0x50
	SET_MESSAGE_ING     volatile.Register32 // 0x54
	SET_MESSAGE_END     volatile.Register32 // 0x58
	SET_RESULT_FINISH   volatile.Register32 // 0x5C
	SET_INVALIDATE_JTAG volatile.Register32 // 0x60
	SET_INVALIDATE_DS   volatile.Register32 // 0x64
	QUERY_ERROR         volatile.Register32 // 0x68
	QUERY_BUSY          volatile.Register32 // 0x6C
	_                   [16]byte
	WR_MESSAGE_MEM      [16]volatile.Register32 // 0x80
	RD_RESULT_MEM       [8]volatile.Register32  // 0xC0
	_                   [16]byte
	SET_MESSAGE_PAD     volatile.Register32 // 0xF0
	ONE_BLOCK           volatile.Register32 // 0xF4
	SOFT_JTAG_CTRL      volatile.Register32 // 0xF8
	WR_JTAG             volatile.Register32 // 0xFC
	_                   [252]byte
	DATE                volatile.Register32 // 0x1FC
}

// HMAC.SET_START: Process control register 0.
func (o *HMAC_Type) SetSET_START(value uint32) {
	volatile.StoreUint32(&o.SET_START.Reg, volatile.LoadUint32(&o.SET_START.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_START() uint32 {
	return volatile.LoadUint32(&o.SET_START.Reg) & 0x1
}

// HMAC.SET_PARA_PURPOSE: Configure purpose.
func (o *HMAC_Type) SetSET_PARA_PURPOSE_PURPOSE_SET(value uint32) {
	volatile.StoreUint32(&o.SET_PARA_PURPOSE.Reg, volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg)&^(0xf)|value)
}
func (o *HMAC_Type) GetSET_PARA_PURPOSE_PURPOSE_SET() uint32 {
	return volatile.LoadUint32(&o.SET_PARA_PURPOSE.Reg) & 0xf
}

// HMAC.SET_PARA_KEY: Configure key.
func (o *HMAC_Type) SetSET_PARA_KEY_KEY_SET(value uint32) {
	volatile.StoreUint32(&o.SET_PARA_KEY.Reg, volatile.LoadUint32(&o.SET_PARA_KEY.Reg)&^(0x7)|value)
}
func (o *HMAC_Type) GetSET_PARA_KEY_KEY_SET() uint32 {
	return volatile.LoadUint32(&o.SET_PARA_KEY.Reg) & 0x7
}

// HMAC.SET_PARA_FINISH: Finish initial configuration.
func (o *HMAC_Type) SetSET_PARA_FINISH_SET_PARA_END(value uint32) {
	volatile.StoreUint32(&o.SET_PARA_FINISH.Reg, volatile.LoadUint32(&o.SET_PARA_FINISH.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_PARA_FINISH_SET_PARA_END() uint32 {
	return volatile.LoadUint32(&o.SET_PARA_FINISH.Reg) & 0x1
}

// HMAC.SET_MESSAGE_ONE: Process control register 1.
func (o *HMAC_Type) SetSET_MESSAGE_ONE_SET_TEXT_ONE(value uint32) {
	volatile.StoreUint32(&o.SET_MESSAGE_ONE.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_MESSAGE_ONE_SET_TEXT_ONE() uint32 {
	return volatile.LoadUint32(&o.SET_MESSAGE_ONE.Reg) & 0x1
}

// HMAC.SET_MESSAGE_ING: Process control register 2.
func (o *HMAC_Type) SetSET_MESSAGE_ING_SET_TEXT_ING(value uint32) {
	volatile.StoreUint32(&o.SET_MESSAGE_ING.Reg, volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_MESSAGE_ING_SET_TEXT_ING() uint32 {
	return volatile.LoadUint32(&o.SET_MESSAGE_ING.Reg) & 0x1
}

// HMAC.SET_MESSAGE_END: Process control register 3.
func (o *HMAC_Type) SetSET_MESSAGE_END_SET_TEXT_END(value uint32) {
	volatile.StoreUint32(&o.SET_MESSAGE_END.Reg, volatile.LoadUint32(&o.SET_MESSAGE_END.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_MESSAGE_END_SET_TEXT_END() uint32 {
	return volatile.LoadUint32(&o.SET_MESSAGE_END.Reg) & 0x1
}

// HMAC.SET_RESULT_FINISH: Process control register 4.
func (o *HMAC_Type) SetSET_RESULT_FINISH_SET_RESULT_END(value uint32) {
	volatile.StoreUint32(&o.SET_RESULT_FINISH.Reg, volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_RESULT_FINISH_SET_RESULT_END() uint32 {
	return volatile.LoadUint32(&o.SET_RESULT_FINISH.Reg) & 0x1
}

// HMAC.SET_INVALIDATE_JTAG: Invalidate register 0.
func (o *HMAC_Type) SetSET_INVALIDATE_JTAG(value uint32) {
	volatile.StoreUint32(&o.SET_INVALIDATE_JTAG.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_INVALIDATE_JTAG() uint32 {
	return volatile.LoadUint32(&o.SET_INVALIDATE_JTAG.Reg) & 0x1
}

// HMAC.SET_INVALIDATE_DS: Invalidate register 1.
func (o *HMAC_Type) SetSET_INVALIDATE_DS(value uint32) {
	volatile.StoreUint32(&o.SET_INVALIDATE_DS.Reg, volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_INVALIDATE_DS() uint32 {
	return volatile.LoadUint32(&o.SET_INVALIDATE_DS.Reg) & 0x1
}

// HMAC.QUERY_ERROR: Error register.
func (o *HMAC_Type) SetQUERY_ERROR_QUERY_CHECK(value uint32) {
	volatile.StoreUint32(&o.QUERY_ERROR.Reg, volatile.LoadUint32(&o.QUERY_ERROR.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetQUERY_ERROR_QUERY_CHECK() uint32 {
	return volatile.LoadUint32(&o.QUERY_ERROR.Reg) & 0x1
}

// HMAC.QUERY_BUSY: Busy register.
func (o *HMAC_Type) SetQUERY_BUSY_BUSY_STATE(value uint32) {
	volatile.StoreUint32(&o.QUERY_BUSY.Reg, volatile.LoadUint32(&o.QUERY_BUSY.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetQUERY_BUSY_BUSY_STATE() uint32 {
	return volatile.LoadUint32(&o.QUERY_BUSY.Reg) & 0x1
}

// HMAC.SET_MESSAGE_PAD: Process control register 5.
func (o *HMAC_Type) SetSET_MESSAGE_PAD_SET_TEXT_PAD(value uint32) {
	volatile.StoreUint32(&o.SET_MESSAGE_PAD.Reg, volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSET_MESSAGE_PAD_SET_TEXT_PAD() uint32 {
	return volatile.LoadUint32(&o.SET_MESSAGE_PAD.Reg) & 0x1
}

// HMAC.ONE_BLOCK: Process control register 6.
func (o *HMAC_Type) SetONE_BLOCK_SET_ONE_BLOCK(value uint32) {
	volatile.StoreUint32(&o.ONE_BLOCK.Reg, volatile.LoadUint32(&o.ONE_BLOCK.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetONE_BLOCK_SET_ONE_BLOCK() uint32 {
	return volatile.LoadUint32(&o.ONE_BLOCK.Reg) & 0x1
}

// HMAC.SOFT_JTAG_CTRL: Jtag register 0.
func (o *HMAC_Type) SetSOFT_JTAG_CTRL(value uint32) {
	volatile.StoreUint32(&o.SOFT_JTAG_CTRL.Reg, volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg)&^(0x1)|value)
}
func (o *HMAC_Type) GetSOFT_JTAG_CTRL() uint32 {
	return volatile.LoadUint32(&o.SOFT_JTAG_CTRL.Reg) & 0x1
}

// HMAC.WR_JTAG: Jtag register 1.
func (o *HMAC_Type) SetWR_JTAG(value uint32) {
	volatile.StoreUint32(&o.WR_JTAG.Reg, value)
}
func (o *HMAC_Type) GetWR_JTAG() uint32 {
	return volatile.LoadUint32(&o.WR_JTAG.Reg)
}

// HMAC.DATE: Date register.
func (o *HMAC_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value)
}
func (o *HMAC_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff
}

// High-Power System
type HP_SYS_Type struct {
	VER_DATE                     volatile.Register32 // 0x0
	CLK_EN                       volatile.Register32 // 0x4
	_                            [8]byte
	CPU_INTR_FROM_CPU_0          volatile.Register32 // 0x10
	CPU_INTR_FROM_CPU_1          volatile.Register32 // 0x14
	CPU_INTR_FROM_CPU_2          volatile.Register32 // 0x18
	CPU_INTR_FROM_CPU_3          volatile.Register32 // 0x1C
	CACHE_CLK_CONFIG             volatile.Register32 // 0x20
	CACHE_RESET_CONFIG           volatile.Register32 // 0x24
	_                            [4]byte
	DMA_ADDR_CTRL                volatile.Register32 // 0x2C
	_                            [4]byte
	TCM_RAM_WRR_CONFIG           volatile.Register32 // 0x34
	TCM_SW_PARITY_BWE_MASK       volatile.Register32 // 0x38
	TCM_RAM_PWR_CTRL0            volatile.Register32 // 0x3C
	L2_ROM_PWR_CTRL0             volatile.Register32 // 0x40
	_                            [12]byte
	PROBEA_CTRL                  volatile.Register32 // 0x50
	PROBEB_CTRL                  volatile.Register32 // 0x54
	_                            [4]byte
	PROBE_OUT                    volatile.Register32 // 0x5C
	L2_MEM_RAM_PWR_CTRL0         volatile.Register32 // 0x60
	CPU_CORESTALLED_ST           volatile.Register32 // 0x64
	_                            [8]byte
	CRYPTO_CTRL                  volatile.Register32 // 0x70
	GPIO_O_HOLD_CTRL0            volatile.Register32 // 0x74
	GPIO_O_HOLD_CTRL1            volatile.Register32 // 0x78
	RDN_ECO_CS                   volatile.Register32 // 0x7C
	CACHE_APB_POSTW_EN           volatile.Register32 // 0x80
	L2_MEM_SUBSIZE               volatile.Register32 // 0x84
	_                            [20]byte
	L2_MEM_INT_RAW               volatile.Register32 // 0x9C
	L2_MEM_INT_ST                volatile.Register32 // 0xA0
	L2_MEM_INT_ENA               volatile.Register32 // 0xA4
	L2_MEM_INT_CLR               volatile.Register32 // 0xA8
	L2_MEM_L2_RAM_ECC            volatile.Register32 // 0xAC
	L2_MEM_INT_RECORD0           volatile.Register32 // 0xB0
	L2_MEM_INT_RECORD1           volatile.Register32 // 0xB4
	_                            [12]byte
	L2_MEM_L2_CACHE_ECC          volatile.Register32 // 0xC4
	L1CACHE_BUS0_ID              volatile.Register32 // 0xC8
	L1CACHE_BUS1_ID              volatile.Register32 // 0xCC
	_                            [8]byte
	L2_MEM_RDN_ECO_CS            volatile.Register32 // 0xD8
	L2_MEM_RDN_ECO_LOW           volatile.Register32 // 0xDC
	L2_MEM_RDN_ECO_HIGH          volatile.Register32 // 0xE0
	TCM_RDN_ECO_CS               volatile.Register32 // 0xE4
	TCM_RDN_ECO_LOW              volatile.Register32 // 0xE8
	TCM_RDN_ECO_HIGH             volatile.Register32 // 0xEC
	GPIO_DED_HOLD_CTRL           volatile.Register32 // 0xF0
	L2_MEM_SW_ECC_BWE_MASK       volatile.Register32 // 0xF4
	USB20OTG_MEM_CTRL            volatile.Register32 // 0xF8
	TCM_INT_RAW                  volatile.Register32 // 0xFC
	TCM_INT_ST                   volatile.Register32 // 0x100
	TCM_INT_ENA                  volatile.Register32 // 0x104
	TCM_INT_CLR                  volatile.Register32 // 0x108
	TCM_PARITY_INT_RECORD        volatile.Register32 // 0x10C
	L1_CACHE_PWR_CTRL            volatile.Register32 // 0x110
	L2_CACHE_PWR_CTRL            volatile.Register32 // 0x114
	CPU_WAITI_CONF               volatile.Register32 // 0x118
	CORE_DEBUG_RUNSTALL_CONF     volatile.Register32 // 0x11C
	CORE_AHB_TIMEOUT             volatile.Register32 // 0x120
	CORE_IBUS_TIMEOUT            volatile.Register32 // 0x124
	CORE_DBUS_TIMEOUT            volatile.Register32 // 0x128
	_                            [12]byte
	ICM_CPU_H2X_CFG              volatile.Register32 // 0x138
	PERI1_APB_POSTW_EN           volatile.Register32 // 0x13C
	BITSCRAMBLER_PERI_SEL        volatile.Register32 // 0x140
	APB_SYNC_POSTW_EN            volatile.Register32 // 0x144
	GDMA_CTRL                    volatile.Register32 // 0x148
	GMAC_CTRL0                   volatile.Register32 // 0x14C
	GMAC_CTRL1                   volatile.Register32 // 0x150
	GMAC_CTRL2                   volatile.Register32 // 0x154
	VPU_CTRL                     volatile.Register32 // 0x158
	USBOTG20_CTRL                volatile.Register32 // 0x15C
	TCM_ERR_RESP_CTRL            volatile.Register32 // 0x160
	L2_MEM_REFRESH               volatile.Register32 // 0x164
	TCM_INIT                     volatile.Register32 // 0x168
	TCM_PARITY_CHECK_CTRL        volatile.Register32 // 0x16C
	DESIGN_FOR_VERIFICATION0     volatile.Register32 // 0x170
	DESIGN_FOR_VERIFICATION1     volatile.Register32 // 0x174
	_                            [8]byte
	PSRAM_FLASH_ADDR_INTERCHANGE volatile.Register32 // 0x180
	_                            [4]byte
	AHB2AXI_BRESP_ERR_INT_RAW    volatile.Register32 // 0x188
	AHB2AXI_BRESP_ERR_INT_ST     volatile.Register32 // 0x18C
	AHB2AXI_BRESP_ERR_INT_ENA    volatile.Register32 // 0x190
	AHB2AXI_BRESP_ERR_INT_CLR    volatile.Register32 // 0x194
	L2_MEM_ERR_RESP_CTRL         volatile.Register32 // 0x198
	L2_MEM_AHB_BUFFER_CTRL       volatile.Register32 // 0x19C
	CORE_DMACTIVE_LPCORE         volatile.Register32 // 0x1A0
	CORE_ERR_RESP_DIS            volatile.Register32 // 0x1A4
	CORE_TIMEOUT_INT_RAW         volatile.Register32 // 0x1A8
	CORE_TIMEOUT_INT_ST          volatile.Register32 // 0x1AC
	CORE_TIMEOUT_INT_ENA         volatile.Register32 // 0x1B0
	CORE_TIMEOUT_INT_CLR         volatile.Register32 // 0x1B4
	_                            [8]byte
	GPIO_O_HYS_CTRL0             volatile.Register32 // 0x1C0
	GPIO_O_HYS_CTRL1             volatile.Register32 // 0x1C4
	_                            [8]byte
	RSA_PD_CTRL                  volatile.Register32 // 0x1D0
	ECC_PD_CTRL                  volatile.Register32 // 0x1D4
	RNG_CFG                      volatile.Register32 // 0x1D8
	UART_PD_CTRL                 volatile.Register32 // 0x1DC
	PERI_MEM_CLK_FORCE_ON        volatile.Register32 // 0x1E0
}

// HP_SYS.VER_DATE: NA
func (o *HP_SYS_Type) SetVER_DATE(value uint32) {
	volatile.StoreUint32(&o.VER_DATE.Reg, value)
}
func (o *HP_SYS_Type) GetVER_DATE() uint32 {
	return volatile.LoadUint32(&o.VER_DATE.Reg)
}

// HP_SYS.CLK_EN: NA
func (o *HP_SYS_Type) SetCLK_EN_REG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCLK_EN_REG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1
}

// HP_SYS.CPU_INTR_FROM_CPU_0: NA
func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_0(value uint32) {
	volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_0.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_0() uint32 {
	return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_0.Reg) & 0x1
}

// HP_SYS.CPU_INTR_FROM_CPU_1: NA
func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_1(value uint32) {
	volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_1.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_1() uint32 {
	return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_1.Reg) & 0x1
}

// HP_SYS.CPU_INTR_FROM_CPU_2: NA
func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_2(value uint32) {
	volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_2.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_2() uint32 {
	return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_2.Reg) & 0x1
}

// HP_SYS.CPU_INTR_FROM_CPU_3: NA
func (o *HP_SYS_Type) SetCPU_INTR_FROM_CPU_3(value uint32) {
	volatile.StoreUint32(&o.CPU_INTR_FROM_CPU_3.Reg, volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCPU_INTR_FROM_CPU_3() uint32 {
	return volatile.LoadUint32(&o.CPU_INTR_FROM_CPU_3.Reg) & 0x1
}

// HP_SYS.CACHE_CLK_CONFIG: NA
func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L2_CACHE_CLK_ON(value uint32) {
	volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L2_CACHE_CLK_ON() uint32 {
	return volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L1_D_CACHE_CLK_ON(value uint32) {
	volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L1_D_CACHE_CLK_ON() uint32 {
	return (volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L1_I1_CACHE_CLK_ON(value uint32) {
	volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L1_I1_CACHE_CLK_ON() uint32 {
	return (volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetCACHE_CLK_CONFIG_REG_L1_I0_CACHE_CLK_ON(value uint32) {
	volatile.StoreUint32(&o.CACHE_CLK_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetCACHE_CLK_CONFIG_REG_L1_I0_CACHE_CLK_ON() uint32 {
	return (volatile.LoadUint32(&o.CACHE_CLK_CONFIG.Reg) & 0x20) >> 5
}

// HP_SYS.CACHE_RESET_CONFIG: NA
func (o *HP_SYS_Type) SetCACHE_RESET_CONFIG_REG_L1_D_CACHE_RESET(value uint32) {
	volatile.StoreUint32(&o.CACHE_RESET_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCACHE_RESET_CONFIG_REG_L1_D_CACHE_RESET() uint32 {
	return (volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetCACHE_RESET_CONFIG_REG_L1_I1_CACHE_RESET(value uint32) {
	volatile.StoreUint32(&o.CACHE_RESET_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetCACHE_RESET_CONFIG_REG_L1_I1_CACHE_RESET() uint32 {
	return (volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetCACHE_RESET_CONFIG_REG_L1_I0_CACHE_RESET(value uint32) {
	volatile.StoreUint32(&o.CACHE_RESET_CONFIG.Reg, volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetCACHE_RESET_CONFIG_REG_L1_I0_CACHE_RESET() uint32 {
	return (volatile.LoadUint32(&o.CACHE_RESET_CONFIG.Reg) & 0x20) >> 5
}

// HP_SYS.DMA_ADDR_CTRL: NA
func (o *HP_SYS_Type) SetDMA_ADDR_CTRL_REG_SYS_DMA_ADDR_SEL(value uint32) {
	volatile.StoreUint32(&o.DMA_ADDR_CTRL.Reg, volatile.LoadUint32(&o.DMA_ADDR_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetDMA_ADDR_CTRL_REG_SYS_DMA_ADDR_SEL() uint32 {
	return volatile.LoadUint32(&o.DMA_ADDR_CTRL.Reg) & 0x1
}

// HP_SYS.TCM_RAM_WRR_CONFIG: NA
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS0_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x7)|value)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS0_WT() uint32 {
	return volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x7
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS1_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x38)|value<<3)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS1_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x38) >> 3
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS2_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x1c0)|value<<6)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS2_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x1c0) >> 6
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS3_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0xe00)|value<<9)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS3_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0xe00) >> 9
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS0_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x7000)|value<<12)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS0_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x7000) >> 12
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS1_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x38000)|value<<15)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS1_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x38000) >> 15
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS2_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x1c0000)|value<<18)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS2_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x1c0000) >> 18
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS3_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0xe00000)|value<<21)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS3_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0xe00000) >> 21
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DMA_WT(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x7000000)|value<<24)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_DMA_WT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x7000000) >> 24
}
func (o *HP_SYS_Type) SetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_WRR_HIGH(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_WRR_CONFIG.Reg, volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetTCM_RAM_WRR_CONFIG_REG_TCM_RAM_WRR_HIGH() uint32 {
	return (volatile.LoadUint32(&o.TCM_RAM_WRR_CONFIG.Reg) & 0x80000000) >> 31
}

// HP_SYS.TCM_SW_PARITY_BWE_MASK: NA
func (o *HP_SYS_Type) SetTCM_SW_PARITY_BWE_MASK_REG_TCM_SW_PARITY_BWE_MASK_CTRL(value uint32) {
	volatile.StoreUint32(&o.TCM_SW_PARITY_BWE_MASK.Reg, volatile.LoadUint32(&o.TCM_SW_PARITY_BWE_MASK.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetTCM_SW_PARITY_BWE_MASK_REG_TCM_SW_PARITY_BWE_MASK_CTRL() uint32 {
	return volatile.LoadUint32(&o.TCM_SW_PARITY_BWE_MASK.Reg) & 0x1
}

// HP_SYS.TCM_RAM_PWR_CTRL0: NA
func (o *HP_SYS_Type) SetTCM_RAM_PWR_CTRL0_REG_HP_TCM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.TCM_RAM_PWR_CTRL0.Reg, volatile.LoadUint32(&o.TCM_RAM_PWR_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetTCM_RAM_PWR_CTRL0_REG_HP_TCM_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.TCM_RAM_PWR_CTRL0.Reg) & 0x1
}

// HP_SYS.L2_ROM_PWR_CTRL0: NA
func (o *HP_SYS_Type) SetL2_ROM_PWR_CTRL0_REG_L2_ROM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L2_ROM_PWR_CTRL0.Reg, volatile.LoadUint32(&o.L2_ROM_PWR_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_ROM_PWR_CTRL0_REG_L2_ROM_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.L2_ROM_PWR_CTRL0.Reg) & 0x1
}

// HP_SYS.PROBEA_CTRL: NA
func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_A_MOD_SEL(value uint32) {
	volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0xffff)|value)
}
func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_A_MOD_SEL() uint32 {
	return volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0xffff
}
func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_A_TOP_SEL(value uint32) {
	volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_A_TOP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_L_SEL(value uint32) {
	volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0x3000000)|value<<24)
}
func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_L_SEL() uint32 {
	return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0x3000000) >> 24
}
func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_H_SEL(value uint32) {
	volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0xc000000)|value<<26)
}
func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_H_SEL() uint32 {
	return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0xc000000) >> 26
}
func (o *HP_SYS_Type) SetPROBEA_CTRL_REG_PROBE_GLOBAL_EN(value uint32) {
	volatile.StoreUint32(&o.PROBEA_CTRL.Reg, volatile.LoadUint32(&o.PROBEA_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_Type) GetPROBEA_CTRL_REG_PROBE_GLOBAL_EN() uint32 {
	return (volatile.LoadUint32(&o.PROBEA_CTRL.Reg) & 0x10000000) >> 28
}

// HP_SYS.PROBEB_CTRL: NA
func (o *HP_SYS_Type) SetPROBEB_CTRL_REG_PROBE_B_MOD_SEL(value uint32) {
	volatile.StoreUint32(&o.PROBEB_CTRL.Reg, volatile.LoadUint32(&o.PROBEB_CTRL.Reg)&^(0xffff)|value)
}
func (o *HP_SYS_Type) GetPROBEB_CTRL_REG_PROBE_B_MOD_SEL() uint32 {
	return volatile.LoadUint32(&o.PROBEB_CTRL.Reg) & 0xffff
}
func (o *HP_SYS_Type) SetPROBEB_CTRL_REG_PROBE_B_TOP_SEL(value uint32) {
	volatile.StoreUint32(&o.PROBEB_CTRL.Reg, volatile.LoadUint32(&o.PROBEB_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_Type) GetPROBEB_CTRL_REG_PROBE_B_TOP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PROBEB_CTRL.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_Type) SetPROBEB_CTRL_REG_PROBE_B_EN(value uint32) {
	volatile.StoreUint32(&o.PROBEB_CTRL.Reg, volatile.LoadUint32(&o.PROBEB_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_Type) GetPROBEB_CTRL_REG_PROBE_B_EN() uint32 {
	return (volatile.LoadUint32(&o.PROBEB_CTRL.Reg) & 0x1000000) >> 24
}

// HP_SYS.PROBE_OUT: NA
func (o *HP_SYS_Type) SetPROBE_OUT(value uint32) {
	volatile.StoreUint32(&o.PROBE_OUT.Reg, value)
}
func (o *HP_SYS_Type) GetPROBE_OUT() uint32 {
	return volatile.LoadUint32(&o.PROBE_OUT.Reg)
}

// HP_SYS.L2_MEM_RAM_PWR_CTRL0: NA
func (o *HP_SYS_Type) SetL2_MEM_RAM_PWR_CTRL0_REG_L2_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_RAM_PWR_CTRL0.Reg, volatile.LoadUint32(&o.L2_MEM_RAM_PWR_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_RAM_PWR_CTRL0_REG_L2_MEM_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_RAM_PWR_CTRL0.Reg) & 0x1
}

// HP_SYS.CPU_CORESTALLED_ST: NA
func (o *HP_SYS_Type) SetCPU_CORESTALLED_ST_REG_CORE0_CORESTALLED_ST(value uint32) {
	volatile.StoreUint32(&o.CPU_CORESTALLED_ST.Reg, volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCPU_CORESTALLED_ST_REG_CORE0_CORESTALLED_ST() uint32 {
	return volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCPU_CORESTALLED_ST_REG_CORE1_CORESTALLED_ST(value uint32) {
	volatile.StoreUint32(&o.CPU_CORESTALLED_ST.Reg, volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCPU_CORESTALLED_ST_REG_CORE1_CORESTALLED_ST() uint32 {
	return (volatile.LoadUint32(&o.CPU_CORESTALLED_ST.Reg) & 0x2) >> 1
}

// HP_SYS.CRYPTO_CTRL: NA
func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_SPI_MANUAL_ENCRYPT(value uint32) {
	volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_SPI_MANUAL_ENCRYPT() uint32 {
	return volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_DB_ENCRYPT(value uint32) {
	volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_DB_ENCRYPT() uint32 {
	return (volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT(value uint32) {
	volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT() uint32 {
	return (volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT(value uint32) {
	volatile.StoreUint32(&o.CRYPTO_CTRL.Reg, volatile.LoadUint32(&o.CRYPTO_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetCRYPTO_CTRL_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT() uint32 {
	return (volatile.LoadUint32(&o.CRYPTO_CTRL.Reg) & 0x8) >> 3
}

// HP_SYS.GPIO_O_HOLD_CTRL0: NA
func (o *HP_SYS_Type) SetGPIO_O_HOLD_CTRL0(value uint32) {
	volatile.StoreUint32(&o.GPIO_O_HOLD_CTRL0.Reg, value)
}
func (o *HP_SYS_Type) GetGPIO_O_HOLD_CTRL0() uint32 {
	return volatile.LoadUint32(&o.GPIO_O_HOLD_CTRL0.Reg)
}

// HP_SYS.GPIO_O_HOLD_CTRL1: NA
func (o *HP_SYS_Type) SetGPIO_O_HOLD_CTRL1_REG_GPIO_0_HOLD_HIGH(value uint32) {
	volatile.StoreUint32(&o.GPIO_O_HOLD_CTRL1.Reg, volatile.LoadUint32(&o.GPIO_O_HOLD_CTRL1.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_Type) GetGPIO_O_HOLD_CTRL1_REG_GPIO_0_HOLD_HIGH() uint32 {
	return volatile.LoadUint32(&o.GPIO_O_HOLD_CTRL1.Reg) & 0x1ff
}

// HP_SYS.RDN_ECO_CS: NA
func (o *HP_SYS_Type) SetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1
}
func (o *HP_SYS_Type) SetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetRDN_ECO_CS_REG_HP_SYS_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1
}

// HP_SYS.CACHE_APB_POSTW_EN: NA
func (o *HP_SYS_Type) SetCACHE_APB_POSTW_EN_REG_CACHE_APB_POSTW_EN(value uint32) {
	volatile.StoreUint32(&o.CACHE_APB_POSTW_EN.Reg, volatile.LoadUint32(&o.CACHE_APB_POSTW_EN.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCACHE_APB_POSTW_EN_REG_CACHE_APB_POSTW_EN() uint32 {
	return volatile.LoadUint32(&o.CACHE_APB_POSTW_EN.Reg) & 0x1
}

// HP_SYS.L2_MEM_SUBSIZE: NA
func (o *HP_SYS_Type) SetL2_MEM_SUBSIZE_REG_L2_MEM_SUB_BLKSIZE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_SUBSIZE.Reg, volatile.LoadUint32(&o.L2_MEM_SUBSIZE.Reg)&^(0x3)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_SUBSIZE_REG_L2_MEM_SUB_BLKSIZE() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_SUBSIZE.Reg) & 0x3
}

// HP_SYS.L2_MEM_INT_RAW: NA
func (o *HP_SYS_Type) SetL2_MEM_INT_RAW_REG_L2_MEM_ECC_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RAW_REG_L2_MEM_ECC_ERR_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RAW_REG_L2_MEM_EXCEED_ADDR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RAW_REG_L2_MEM_EXCEED_ADDR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RAW_REG_L2_MEM_ERR_RESP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RAW_REG_L2_MEM_ERR_RESP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RAW.Reg) & 0x4) >> 2
}

// HP_SYS.L2_MEM_INT_ST: NA
func (o *HP_SYS_Type) SetL2_MEM_INT_ST_REG_L2_MEM_ECC_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_ST.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_ST_REG_L2_MEM_ECC_ERR_INT_ST() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_ST_REG_L2_MEM_EXCEED_ADDR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_ST.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_ST_REG_L2_MEM_EXCEED_ADDR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_ST_REG_L2_MEM_ERR_RESP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_ST.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_ST_REG_L2_MEM_ERR_RESP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_ST.Reg) & 0x4) >> 2
}

// HP_SYS.L2_MEM_INT_ENA: NA
func (o *HP_SYS_Type) SetL2_MEM_INT_ENA_REG_L2_MEM_ECC_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_ENA_REG_L2_MEM_ECC_ERR_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_ENA_REG_L2_MEM_EXCEED_ADDR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_ENA_REG_L2_MEM_EXCEED_ADDR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_ENA_REG_L2_MEM_ERR_RESP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_ENA_REG_L2_MEM_ERR_RESP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_ENA.Reg) & 0x4) >> 2
}

// HP_SYS.L2_MEM_INT_CLR: NA
func (o *HP_SYS_Type) SetL2_MEM_INT_CLR_REG_L2_MEM_ECC_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_CLR_REG_L2_MEM_ECC_ERR_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_CLR_REG_L2_MEM_EXCEED_ADDR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_CLR_REG_L2_MEM_EXCEED_ADDR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetL2_MEM_INT_CLR_REG_L2_MEM_ERR_RESP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_CLR_REG_L2_MEM_ERR_RESP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_CLR.Reg) & 0x4) >> 2
}

// HP_SYS.L2_MEM_L2_RAM_ECC: NA
func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT0_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT0_ECC_EN() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT1_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT1_ECC_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT2_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT2_ECC_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT3_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT3_ECC_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x8) >> 3
}
func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT4_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT4_ECC_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT5_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_L2_RAM_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetL2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT5_ECC_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_L2_RAM_ECC.Reg) & 0x20) >> 5
}

// HP_SYS.L2_MEM_INT_RECORD0: NA
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD0.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg)&^(0x1fffff)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg) & 0x1fffff
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_WE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD0.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_WE() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_MASTER(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD0.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg)&^(0x1c00000)|value<<22)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_MASTER() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD0.Reg) & 0x1c00000) >> 22
}

// HP_SYS.L2_MEM_INT_RECORD1: NA
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_INT_ADDR(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x7fff)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_INT_ADDR() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x7fff
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ONE_BIT_ERR(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ONE_BIT_ERR() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_TWO_BIT_ERR(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_TWO_BIT_ERR() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_BIT(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x3fe0000)|value<<17)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_BIT() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x3fe0000) >> 17
}
func (o *HP_SYS_Type) SetL2_MEM_INT_RECORD1_REG_L2_CACHE_ERR_BANK(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_INT_RECORD1.Reg, volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_Type) GetL2_MEM_INT_RECORD1_REG_L2_CACHE_ERR_BANK() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_INT_RECORD1.Reg) & 0x4000000) >> 26
}

// HP_SYS.L2_MEM_L2_CACHE_ECC: NA
func (o *HP_SYS_Type) SetL2_MEM_L2_CACHE_ECC_REG_L2_CACHE_ECC_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_L2_CACHE_ECC.Reg, volatile.LoadUint32(&o.L2_MEM_L2_CACHE_ECC.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_L2_CACHE_ECC_REG_L2_CACHE_ECC_EN() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_L2_CACHE_ECC.Reg) & 0x1
}

// HP_SYS.L1CACHE_BUS0_ID: NA
func (o *HP_SYS_Type) SetL1CACHE_BUS0_ID_REG_L1_CACHE_BUS0_ID(value uint32) {
	volatile.StoreUint32(&o.L1CACHE_BUS0_ID.Reg, volatile.LoadUint32(&o.L1CACHE_BUS0_ID.Reg)&^(0xf)|value)
}
func (o *HP_SYS_Type) GetL1CACHE_BUS0_ID_REG_L1_CACHE_BUS0_ID() uint32 {
	return volatile.LoadUint32(&o.L1CACHE_BUS0_ID.Reg) & 0xf
}

// HP_SYS.L1CACHE_BUS1_ID: NA
func (o *HP_SYS_Type) SetL1CACHE_BUS1_ID_REG_L1_CACHE_BUS1_ID(value uint32) {
	volatile.StoreUint32(&o.L1CACHE_BUS1_ID.Reg, volatile.LoadUint32(&o.L1CACHE_BUS1_ID.Reg)&^(0xf)|value)
}
func (o *HP_SYS_Type) GetL1CACHE_BUS1_ID_REG_L1_CACHE_BUS1_ID() uint32 {
	return volatile.LoadUint32(&o.L1CACHE_BUS1_ID.Reg) & 0xf
}

// HP_SYS.L2_MEM_RDN_ECO_CS: NA
func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_RDN_ECO_CS.Reg) & 0x2) >> 1
}

// HP_SYS.L2_MEM_RDN_ECO_LOW: NA
func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_RDN_ECO_LOW.Reg, value)
}
func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_RDN_ECO_LOW.Reg)
}

// HP_SYS.L2_MEM_RDN_ECO_HIGH: NA
func (o *HP_SYS_Type) SetL2_MEM_RDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_RDN_ECO_HIGH.Reg, value)
}
func (o *HP_SYS_Type) GetL2_MEM_RDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_RDN_ECO_HIGH.Reg)
}

// HP_SYS.TCM_RDN_ECO_CS: NA
func (o *HP_SYS_Type) SetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.TCM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg) & 0x1
}
func (o *HP_SYS_Type) SetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.TCM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetTCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.TCM_RDN_ECO_CS.Reg) & 0x2) >> 1
}

// HP_SYS.TCM_RDN_ECO_LOW: NA
func (o *HP_SYS_Type) SetTCM_RDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.TCM_RDN_ECO_LOW.Reg, value)
}
func (o *HP_SYS_Type) GetTCM_RDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.TCM_RDN_ECO_LOW.Reg)
}

// HP_SYS.TCM_RDN_ECO_HIGH: NA
func (o *HP_SYS_Type) SetTCM_RDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.TCM_RDN_ECO_HIGH.Reg, value)
}
func (o *HP_SYS_Type) GetTCM_RDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.TCM_RDN_ECO_HIGH.Reg)
}

// HP_SYS.GPIO_DED_HOLD_CTRL: NA
func (o *HP_SYS_Type) SetGPIO_DED_HOLD_CTRL_REG_GPIO_DED_HOLD(value uint32) {
	volatile.StoreUint32(&o.GPIO_DED_HOLD_CTRL.Reg, volatile.LoadUint32(&o.GPIO_DED_HOLD_CTRL.Reg)&^(0x3ffffff)|value)
}
func (o *HP_SYS_Type) GetGPIO_DED_HOLD_CTRL_REG_GPIO_DED_HOLD() uint32 {
	return volatile.LoadUint32(&o.GPIO_DED_HOLD_CTRL.Reg) & 0x3ffffff
}

// HP_SYS.L2_MEM_SW_ECC_BWE_MASK: NA
func (o *HP_SYS_Type) SetL2_MEM_SW_ECC_BWE_MASK_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_SW_ECC_BWE_MASK.Reg, volatile.LoadUint32(&o.L2_MEM_SW_ECC_BWE_MASK.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_SW_ECC_BWE_MASK_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_SW_ECC_BWE_MASK.Reg) & 0x1
}

// HP_SYS.USB20OTG_MEM_CTRL: NA
func (o *HP_SYS_Type) SetUSB20OTG_MEM_CTRL_REG_USB20_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.USB20OTG_MEM_CTRL.Reg, volatile.LoadUint32(&o.USB20OTG_MEM_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetUSB20OTG_MEM_CTRL_REG_USB20_MEM_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.USB20OTG_MEM_CTRL.Reg) & 0x1
}

// HP_SYS.TCM_INT_RAW: need_des
func (o *HP_SYS_Type) SetTCM_INT_RAW_TCM_PARITY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.TCM_INT_RAW.Reg, volatile.LoadUint32(&o.TCM_INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetTCM_INT_RAW_TCM_PARITY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.TCM_INT_RAW.Reg) & 0x80000000) >> 31
}

// HP_SYS.TCM_INT_ST: need_des
func (o *HP_SYS_Type) SetTCM_INT_ST_TCM_PARITY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.TCM_INT_ST.Reg, volatile.LoadUint32(&o.TCM_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetTCM_INT_ST_TCM_PARITY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.TCM_INT_ST.Reg) & 0x80000000) >> 31
}

// HP_SYS.TCM_INT_ENA: need_des
func (o *HP_SYS_Type) SetTCM_INT_ENA_TCM_PARITY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.TCM_INT_ENA.Reg, volatile.LoadUint32(&o.TCM_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetTCM_INT_ENA_TCM_PARITY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.TCM_INT_ENA.Reg) & 0x80000000) >> 31
}

// HP_SYS.TCM_INT_CLR: need_des
func (o *HP_SYS_Type) SetTCM_INT_CLR_TCM_PARITY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.TCM_INT_CLR.Reg, volatile.LoadUint32(&o.TCM_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetTCM_INT_CLR_TCM_PARITY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.TCM_INT_CLR.Reg) & 0x80000000) >> 31
}

// HP_SYS.TCM_PARITY_INT_RECORD: need_des
func (o *HP_SYS_Type) SetTCM_PARITY_INT_RECORD_TCM_PARITY_ERR_INT_ADDR(value uint32) {
	volatile.StoreUint32(&o.TCM_PARITY_INT_RECORD.Reg, volatile.LoadUint32(&o.TCM_PARITY_INT_RECORD.Reg)&^(0x1fff)|value)
}
func (o *HP_SYS_Type) GetTCM_PARITY_INT_RECORD_TCM_PARITY_ERR_INT_ADDR() uint32 {
	return volatile.LoadUint32(&o.TCM_PARITY_INT_RECORD.Reg) & 0x1fff
}

// HP_SYS.L1_CACHE_PWR_CTRL: NA
func (o *HP_SYS_Type) SetL1_CACHE_PWR_CTRL_REG_L1_CACHE_MEM_FO(value uint32) {
	volatile.StoreUint32(&o.L1_CACHE_PWR_CTRL.Reg, volatile.LoadUint32(&o.L1_CACHE_PWR_CTRL.Reg)&^(0x3f)|value)
}
func (o *HP_SYS_Type) GetL1_CACHE_PWR_CTRL_REG_L1_CACHE_MEM_FO() uint32 {
	return volatile.LoadUint32(&o.L1_CACHE_PWR_CTRL.Reg) & 0x3f
}

// HP_SYS.L2_CACHE_PWR_CTRL: NA
func (o *HP_SYS_Type) SetL2_CACHE_PWR_CTRL_REG_L2_CACHE_MEM_FO(value uint32) {
	volatile.StoreUint32(&o.L2_CACHE_PWR_CTRL.Reg, volatile.LoadUint32(&o.L2_CACHE_PWR_CTRL.Reg)&^(0x3)|value)
}
func (o *HP_SYS_Type) GetL2_CACHE_PWR_CTRL_REG_L2_CACHE_MEM_FO() uint32 {
	return volatile.LoadUint32(&o.L2_CACHE_PWR_CTRL.Reg) & 0x3
}

// HP_SYS.CPU_WAITI_CONF: CPU_WAITI configuration register
func (o *HP_SYS_Type) SetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM(value uint32) {
	volatile.StoreUint32(&o.CPU_WAITI_CONF.Reg, volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg)&^(0x1e)|value<<1)
}
func (o *HP_SYS_Type) GetCPU_WAITI_CONF_CPU_WAITI_DELAY_NUM() uint32 {
	return (volatile.LoadUint32(&o.CPU_WAITI_CONF.Reg) & 0x1e) >> 1
}

// HP_SYS.CORE_DEBUG_RUNSTALL_CONF: Core Debug runstall configure register
func (o *HP_SYS_Type) SetCORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg, volatile.LoadUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE() uint32 {
	return volatile.LoadUint32(&o.CORE_DEBUG_RUNSTALL_CONF.Reg) & 0x1
}

// HP_SYS.CORE_AHB_TIMEOUT: need_des
func (o *HP_SYS_Type) SetCORE_AHB_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_AHB_TIMEOUT_EN() uint32 {
	return volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCORE_AHB_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg)&^(0x1fffe)|value<<1)
}
func (o *HP_SYS_Type) GetCORE_AHB_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.CORE_AHB_TIMEOUT.Reg) & 0x1fffe) >> 1
}

// HP_SYS.CORE_IBUS_TIMEOUT: need_des
func (o *HP_SYS_Type) SetCORE_IBUS_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_IBUS_TIMEOUT_EN() uint32 {
	return volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCORE_IBUS_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1)
}
func (o *HP_SYS_Type) GetCORE_IBUS_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.CORE_IBUS_TIMEOUT.Reg) & 0x1fffe) >> 1
}

// HP_SYS.CORE_DBUS_TIMEOUT: need_des
func (o *HP_SYS_Type) SetCORE_DBUS_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_DBUS_TIMEOUT_EN() uint32 {
	return volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCORE_DBUS_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1)
}
func (o *HP_SYS_Type) GetCORE_DBUS_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.CORE_DBUS_TIMEOUT.Reg) & 0x1fffe) >> 1
}

// HP_SYS.ICM_CPU_H2X_CFG: need_des
func (o *HP_SYS_Type) SetICM_CPU_H2X_CFG_CPU_ICM_H2X_POST_WR_EN(value uint32) {
	volatile.StoreUint32(&o.ICM_CPU_H2X_CFG.Reg, volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetICM_CPU_H2X_CFG_CPU_ICM_H2X_POST_WR_EN() uint32 {
	return volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg) & 0x1
}
func (o *HP_SYS_Type) SetICM_CPU_H2X_CFG_CPU_ICM_H2X_CUT_THROUGH_EN(value uint32) {
	volatile.StoreUint32(&o.ICM_CPU_H2X_CFG.Reg, volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetICM_CPU_H2X_CFG_CPU_ICM_H2X_CUT_THROUGH_EN() uint32 {
	return (volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetICM_CPU_H2X_CFG_CPU_ICM_H2X_BRIDGE_BUSY(value uint32) {
	volatile.StoreUint32(&o.ICM_CPU_H2X_CFG.Reg, volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetICM_CPU_H2X_CFG_CPU_ICM_H2X_BRIDGE_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ICM_CPU_H2X_CFG.Reg) & 0x4) >> 2
}

// HP_SYS.PERI1_APB_POSTW_EN: NA
func (o *HP_SYS_Type) SetPERI1_APB_POSTW_EN(value uint32) {
	volatile.StoreUint32(&o.PERI1_APB_POSTW_EN.Reg, volatile.LoadUint32(&o.PERI1_APB_POSTW_EN.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetPERI1_APB_POSTW_EN() uint32 {
	return volatile.LoadUint32(&o.PERI1_APB_POSTW_EN.Reg) & 0x1
}

// HP_SYS.BITSCRAMBLER_PERI_SEL: Bitscrambler Peri Sel
func (o *HP_SYS_Type) SetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_RX_SEL(value uint32) {
	volatile.StoreUint32(&o.BITSCRAMBLER_PERI_SEL.Reg, volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg)&^(0xf)|value)
}
func (o *HP_SYS_Type) GetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_RX_SEL() uint32 {
	return volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg) & 0xf
}
func (o *HP_SYS_Type) SetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_TX_SEL(value uint32) {
	volatile.StoreUint32(&o.BITSCRAMBLER_PERI_SEL.Reg, volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg)&^(0xf0)|value<<4)
}
func (o *HP_SYS_Type) GetBITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_TX_SEL() uint32 {
	return (volatile.LoadUint32(&o.BITSCRAMBLER_PERI_SEL.Reg) & 0xf0) >> 4
}

// HP_SYS.APB_SYNC_POSTW_EN: N/A
func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_GMAC_APB_POSTW_EN(value uint32) {
	volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_GMAC_APB_POSTW_EN() uint32 {
	return volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x1
}
func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_DSI_HOST_APB_POSTW_EN(value uint32) {
	volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_DSI_HOST_APB_POSTW_EN() uint32 {
	return (volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_CSI_HOST_APB_SYNC_POSTW_EN(value uint32) {
	volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_CSI_HOST_APB_SYNC_POSTW_EN() uint32 {
	return (volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetAPB_SYNC_POSTW_EN_CSI_HOST_APB_ASYNC_POSTW_EN(value uint32) {
	volatile.StoreUint32(&o.APB_SYNC_POSTW_EN.Reg, volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetAPB_SYNC_POSTW_EN_CSI_HOST_APB_ASYNC_POSTW_EN() uint32 {
	return (volatile.LoadUint32(&o.APB_SYNC_POSTW_EN.Reg) & 0x8) >> 3
}

// HP_SYS.GDMA_CTRL: N/A
func (o *HP_SYS_Type) SetGDMA_CTRL_DEBUG_CH_NUM(value uint32) {
	volatile.StoreUint32(&o.GDMA_CTRL.Reg, volatile.LoadUint32(&o.GDMA_CTRL.Reg)&^(0x3)|value)
}
func (o *HP_SYS_Type) GetGDMA_CTRL_DEBUG_CH_NUM() uint32 {
	return volatile.LoadUint32(&o.GDMA_CTRL.Reg) & 0x3
}

// HP_SYS.GMAC_CTRL0: N/A
func (o *HP_SYS_Type) SetGMAC_CTRL0_PTP_PPS(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetGMAC_CTRL0_PTP_PPS() uint32 {
	return volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x1
}
func (o *HP_SYS_Type) SetGMAC_CTRL0_SBD_FLOWCTRL(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetGMAC_CTRL0_SBD_FLOWCTRL() uint32 {
	return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetGMAC_CTRL0_PHY_INTF_SEL(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x1c)|value<<2)
}
func (o *HP_SYS_Type) GetGMAC_CTRL0_PHY_INTF_SEL() uint32 {
	return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x1c) >> 2
}
func (o *HP_SYS_Type) SetGMAC_CTRL0_GMAC_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetGMAC_CTRL0_GMAC_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x20) >> 5
}
func (o *HP_SYS_Type) SetGMAC_CTRL0_GMAC_RST_CLK_TX_N(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_Type) GetGMAC_CTRL0_GMAC_RST_CLK_TX_N() uint32 {
	return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x40) >> 6
}
func (o *HP_SYS_Type) SetGMAC_CTRL0_GMAC_RST_CLK_RX_N(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL0.Reg, volatile.LoadUint32(&o.GMAC_CTRL0.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_Type) GetGMAC_CTRL0_GMAC_RST_CLK_RX_N() uint32 {
	return (volatile.LoadUint32(&o.GMAC_CTRL0.Reg) & 0x80) >> 7
}

// HP_SYS.GMAC_CTRL1: N/A
func (o *HP_SYS_Type) SetGMAC_CTRL1(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL1.Reg, value)
}
func (o *HP_SYS_Type) GetGMAC_CTRL1() uint32 {
	return volatile.LoadUint32(&o.GMAC_CTRL1.Reg)
}

// HP_SYS.GMAC_CTRL2: N/A
func (o *HP_SYS_Type) SetGMAC_CTRL2(value uint32) {
	volatile.StoreUint32(&o.GMAC_CTRL2.Reg, value)
}
func (o *HP_SYS_Type) GetGMAC_CTRL2() uint32 {
	return volatile.LoadUint32(&o.GMAC_CTRL2.Reg)
}

// HP_SYS.VPU_CTRL: N/A
func (o *HP_SYS_Type) SetVPU_CTRL_PPA_LSLP_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetVPU_CTRL_PPA_LSLP_MEM_PD() uint32 {
	return volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x1
}
func (o *HP_SYS_Type) SetVPU_CTRL_JPEG_SDSLP_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetVPU_CTRL_JPEG_SDSLP_MEM_PD() uint32 {
	return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetVPU_CTRL_JPEG_LSLP_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetVPU_CTRL_JPEG_LSLP_MEM_PD() uint32 {
	return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetVPU_CTRL_JPEG_DSLP_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetVPU_CTRL_JPEG_DSLP_MEM_PD() uint32 {
	return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x8) >> 3
}
func (o *HP_SYS_Type) SetVPU_CTRL_DMA2D_LSLP_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.VPU_CTRL.Reg, volatile.LoadUint32(&o.VPU_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetVPU_CTRL_DMA2D_LSLP_MEM_PD() uint32 {
	return (volatile.LoadUint32(&o.VPU_CTRL.Reg) & 0x10) >> 4
}

// HP_SYS.USBOTG20_CTRL: N/A
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_TEST_DONE(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_TEST_DONE() uint32 {
	return volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x1
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_USB_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x7ffe)|value<<1)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_USB_MEM_AUX_CTRL() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x7ffe) >> 1
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_SUSPENDM(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_SUSPENDM() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_SUSPEND_FORCE_EN(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_SUSPEND_FORCE_EN() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_RSTN(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_RSTN() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_RESET_FORCE_EN(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_RESET_FORCE_EN() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_PLL_FORCE_EN(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_PLL_FORCE_EN() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_PHY_PLL_EN(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_PHY_PLL_EN() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_SUSPENDM(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_SUSPENDM() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_TXBITSTUFF_EN(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_TXBITSTUFF_EN() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_REFCLK_MODE(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_REFCLK_MODE() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_Type) SetUSBOTG20_CTRL_OTG_PHY_BISTEN(value uint32) {
	volatile.StoreUint32(&o.USBOTG20_CTRL.Reg, volatile.LoadUint32(&o.USBOTG20_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_Type) GetUSBOTG20_CTRL_OTG_PHY_BISTEN() uint32 {
	return (volatile.LoadUint32(&o.USBOTG20_CTRL.Reg) & 0x1000000) >> 24
}

// HP_SYS.TCM_ERR_RESP_CTRL: need_des
func (o *HP_SYS_Type) SetTCM_ERR_RESP_CTRL_TCM_ERR_RESP_EN(value uint32) {
	volatile.StoreUint32(&o.TCM_ERR_RESP_CTRL.Reg, volatile.LoadUint32(&o.TCM_ERR_RESP_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetTCM_ERR_RESP_CTRL_TCM_ERR_RESP_EN() uint32 {
	return volatile.LoadUint32(&o.TCM_ERR_RESP_CTRL.Reg) & 0x1
}

// HP_SYS.L2_MEM_REFRESH: NA
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFERSH_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFERSH_EN() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFERSH_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFERSH_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFERSH_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFERSH_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFERSH_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFERSH_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x8) >> 3
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFERSH_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFERSH_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFERSH_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFERSH_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x20) >> 5
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_REFERSH_CNT_RESET(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_REFERSH_CNT_RESET() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x40) >> 6
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFRESH_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFRESH_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x80) >> 7
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFRESH_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFRESH_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x100) >> 8
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFRESH_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFRESH_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x200) >> 9
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFRESH_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFRESH_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x400) >> 10
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFRESH_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFRESH_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x800) >> 11
}
func (o *HP_SYS_Type) SetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFRESH_DONE(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_REFRESH.Reg, volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_Type) GetL2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFRESH_DONE() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_REFRESH.Reg) & 0x1000) >> 12
}

// HP_SYS.TCM_INIT: NA
func (o *HP_SYS_Type) SetTCM_INIT_REG_TCM_INIT_EN(value uint32) {
	volatile.StoreUint32(&o.TCM_INIT.Reg, volatile.LoadUint32(&o.TCM_INIT.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetTCM_INIT_REG_TCM_INIT_EN() uint32 {
	return volatile.LoadUint32(&o.TCM_INIT.Reg) & 0x1
}
func (o *HP_SYS_Type) SetTCM_INIT_REG_TCM_INIT_CNT_RESET(value uint32) {
	volatile.StoreUint32(&o.TCM_INIT.Reg, volatile.LoadUint32(&o.TCM_INIT.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetTCM_INIT_REG_TCM_INIT_CNT_RESET() uint32 {
	return (volatile.LoadUint32(&o.TCM_INIT.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetTCM_INIT_REG_TCM_INIT_DONE(value uint32) {
	volatile.StoreUint32(&o.TCM_INIT.Reg, volatile.LoadUint32(&o.TCM_INIT.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetTCM_INIT_REG_TCM_INIT_DONE() uint32 {
	return (volatile.LoadUint32(&o.TCM_INIT.Reg) & 0x4) >> 2
}

// HP_SYS.TCM_PARITY_CHECK_CTRL: need_des
func (o *HP_SYS_Type) SetTCM_PARITY_CHECK_CTRL_TCM_PARITY_CHECK_EN(value uint32) {
	volatile.StoreUint32(&o.TCM_PARITY_CHECK_CTRL.Reg, volatile.LoadUint32(&o.TCM_PARITY_CHECK_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetTCM_PARITY_CHECK_CTRL_TCM_PARITY_CHECK_EN() uint32 {
	return volatile.LoadUint32(&o.TCM_PARITY_CHECK_CTRL.Reg) & 0x1
}

// HP_SYS.DESIGN_FOR_VERIFICATION0: need_des
func (o *HP_SYS_Type) SetDESIGN_FOR_VERIFICATION0(value uint32) {
	volatile.StoreUint32(&o.DESIGN_FOR_VERIFICATION0.Reg, value)
}
func (o *HP_SYS_Type) GetDESIGN_FOR_VERIFICATION0() uint32 {
	return volatile.LoadUint32(&o.DESIGN_FOR_VERIFICATION0.Reg)
}

// HP_SYS.DESIGN_FOR_VERIFICATION1: need_des
func (o *HP_SYS_Type) SetDESIGN_FOR_VERIFICATION1(value uint32) {
	volatile.StoreUint32(&o.DESIGN_FOR_VERIFICATION1.Reg, value)
}
func (o *HP_SYS_Type) GetDESIGN_FOR_VERIFICATION1() uint32 {
	return volatile.LoadUint32(&o.DESIGN_FOR_VERIFICATION1.Reg)
}

// HP_SYS.PSRAM_FLASH_ADDR_INTERCHANGE: need_des
func (o *HP_SYS_Type) SetPSRAM_FLASH_ADDR_INTERCHANGE_CPU(value uint32) {
	volatile.StoreUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg, volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetPSRAM_FLASH_ADDR_INTERCHANGE_CPU() uint32 {
	return volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg) & 0x1
}
func (o *HP_SYS_Type) SetPSRAM_FLASH_ADDR_INTERCHANGE_DMA(value uint32) {
	volatile.StoreUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg, volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetPSRAM_FLASH_ADDR_INTERCHANGE_DMA() uint32 {
	return (volatile.LoadUint32(&o.PSRAM_FLASH_ADDR_INTERCHANGE.Reg) & 0x2) >> 1
}

// HP_SYS.AHB2AXI_BRESP_ERR_INT_RAW: NA
func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_RAW_CPU_ICM_H2X_BRESP_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_RAW.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_RAW.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_RAW_CPU_ICM_H2X_BRESP_ERR_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_RAW.Reg) & 0x1
}

// HP_SYS.AHB2AXI_BRESP_ERR_INT_ST: need_des
func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_ST_CPU_ICM_H2X_BRESP_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_ST.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_ST_CPU_ICM_H2X_BRESP_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ST.Reg) & 0x80000000) >> 31
}

// HP_SYS.AHB2AXI_BRESP_ERR_INT_ENA: need_des
func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_ENA_CPU_ICM_H2X_BRESP_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_ENA.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_ENA_CPU_ICM_H2X_BRESP_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_ENA.Reg) & 0x80000000) >> 31
}

// HP_SYS.AHB2AXI_BRESP_ERR_INT_CLR: need_des
func (o *HP_SYS_Type) SetAHB2AXI_BRESP_ERR_INT_CLR_CPU_ICM_H2X_BRESP_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.AHB2AXI_BRESP_ERR_INT_CLR.Reg, volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_Type) GetAHB2AXI_BRESP_ERR_INT_CLR_CPU_ICM_H2X_BRESP_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.AHB2AXI_BRESP_ERR_INT_CLR.Reg) & 0x80000000) >> 31
}

// HP_SYS.L2_MEM_ERR_RESP_CTRL: need_des
func (o *HP_SYS_Type) SetL2_MEM_ERR_RESP_CTRL_L2_MEM_ERR_RESP_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_ERR_RESP_CTRL.Reg, volatile.LoadUint32(&o.L2_MEM_ERR_RESP_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_ERR_RESP_CTRL_L2_MEM_ERR_RESP_EN() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_ERR_RESP_CTRL.Reg) & 0x1
}

// HP_SYS.L2_MEM_AHB_BUFFER_CTRL: need_des
func (o *HP_SYS_Type) SetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_WRBUFFER_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg, volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_WRBUFFER_EN() uint32 {
	return volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg) & 0x1
}
func (o *HP_SYS_Type) SetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_RDBUFFER_EN(value uint32) {
	volatile.StoreUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg, volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetL2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_RDBUFFER_EN() uint32 {
	return (volatile.LoadUint32(&o.L2_MEM_AHB_BUFFER_CTRL.Reg) & 0x2) >> 1
}

// HP_SYS.CORE_DMACTIVE_LPCORE: need_des
func (o *HP_SYS_Type) SetCORE_DMACTIVE_LPCORE(value uint32) {
	volatile.StoreUint32(&o.CORE_DMACTIVE_LPCORE.Reg, volatile.LoadUint32(&o.CORE_DMACTIVE_LPCORE.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_DMACTIVE_LPCORE() uint32 {
	return volatile.LoadUint32(&o.CORE_DMACTIVE_LPCORE.Reg) & 0x1
}

// HP_SYS.CORE_ERR_RESP_DIS: need_des
func (o *HP_SYS_Type) SetCORE_ERR_RESP_DIS(value uint32) {
	volatile.StoreUint32(&o.CORE_ERR_RESP_DIS.Reg, volatile.LoadUint32(&o.CORE_ERR_RESP_DIS.Reg)&^(0x7)|value)
}
func (o *HP_SYS_Type) GetCORE_ERR_RESP_DIS() uint32 {
	return volatile.LoadUint32(&o.CORE_ERR_RESP_DIS.Reg) & 0x7
}

// HP_SYS.CORE_TIMEOUT_INT_RAW: Hp core bus timeout interrupt raw register
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE0_AHB_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE0_AHB_TIMEOUT_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE1_AHB_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE1_AHB_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE0_IBUS_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE0_IBUS_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE1_IBUS_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE1_IBUS_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x8) >> 3
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE0_DBUS_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE0_DBUS_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_RAW_CORE1_DBUS_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_RAW.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_RAW_CORE1_DBUS_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_RAW.Reg) & 0x20) >> 5
}

// HP_SYS.CORE_TIMEOUT_INT_ST: masked interrupt register
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE0_AHB_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE0_AHB_TIMEOUT_INT_ST() uint32 {
	return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE1_AHB_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE1_AHB_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE0_IBUS_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE0_IBUS_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE1_IBUS_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE1_IBUS_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x8) >> 3
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE0_DBUS_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE0_DBUS_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ST_CORE1_DBUS_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ST.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ST_CORE1_DBUS_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ST.Reg) & 0x20) >> 5
}

// HP_SYS.CORE_TIMEOUT_INT_ENA: masked interrupt register
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE0_AHB_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE0_AHB_TIMEOUT_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE1_AHB_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE1_AHB_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE0_IBUS_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE0_IBUS_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE1_IBUS_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE1_IBUS_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x8) >> 3
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE0_DBUS_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE0_DBUS_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_ENA_CORE1_DBUS_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_ENA.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_ENA_CORE1_DBUS_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_ENA.Reg) & 0x20) >> 5
}

// HP_SYS.CORE_TIMEOUT_INT_CLR: interrupt clear register
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE0_AHB_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE0_AHB_TIMEOUT_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE1_AHB_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE1_AHB_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE0_IBUS_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE0_IBUS_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE1_IBUS_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE1_IBUS_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x8) >> 3
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE0_DBUS_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE0_DBUS_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x10) >> 4
}
func (o *HP_SYS_Type) SetCORE_TIMEOUT_INT_CLR_CORE1_DBUS_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.CORE_TIMEOUT_INT_CLR.Reg, volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_Type) GetCORE_TIMEOUT_INT_CLR_CORE1_DBUS_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.CORE_TIMEOUT_INT_CLR.Reg) & 0x20) >> 5
}

// HP_SYS.GPIO_O_HYS_CTRL0: NA
func (o *HP_SYS_Type) SetGPIO_O_HYS_CTRL0(value uint32) {
	volatile.StoreUint32(&o.GPIO_O_HYS_CTRL0.Reg, value)
}
func (o *HP_SYS_Type) GetGPIO_O_HYS_CTRL0() uint32 {
	return volatile.LoadUint32(&o.GPIO_O_HYS_CTRL0.Reg)
}

// HP_SYS.GPIO_O_HYS_CTRL1: NA
func (o *HP_SYS_Type) SetGPIO_O_HYS_CTRL1_REG_GPIO_0_HYS_HIGH(value uint32) {
	volatile.StoreUint32(&o.GPIO_O_HYS_CTRL1.Reg, volatile.LoadUint32(&o.GPIO_O_HYS_CTRL1.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_Type) GetGPIO_O_HYS_CTRL1_REG_GPIO_0_HYS_HIGH() uint32 {
	return volatile.LoadUint32(&o.GPIO_O_HYS_CTRL1.Reg) & 0x1ff
}

// HP_SYS.RSA_PD_CTRL: rsa pd ctrl register
func (o *HP_SYS_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PD() uint32 {
	return volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x1
}
func (o *HP_SYS_Type) SetRSA_PD_CTRL_RSA_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetRSA_PD_CTRL_RSA_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetRSA_PD_CTRL_RSA_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.RSA_PD_CTRL.Reg, volatile.LoadUint32(&o.RSA_PD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetRSA_PD_CTRL_RSA_MEM_PD() uint32 {
	return (volatile.LoadUint32(&o.RSA_PD_CTRL.Reg) & 0x4) >> 2
}

// HP_SYS.ECC_PD_CTRL: ecc pd ctrl register
func (o *HP_SYS_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PD() uint32 {
	return volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x1
}
func (o *HP_SYS_Type) SetECC_PD_CTRL_ECC_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetECC_PD_CTRL_ECC_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetECC_PD_CTRL_ECC_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.ECC_PD_CTRL.Reg, volatile.LoadUint32(&o.ECC_PD_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetECC_PD_CTRL_ECC_MEM_PD() uint32 {
	return (volatile.LoadUint32(&o.ECC_PD_CTRL.Reg) & 0x4) >> 2
}

// HP_SYS.RNG_CFG: rng cfg register
func (o *HP_SYS_Type) SetRNG_CFG_RNG_SAMPLE_ENABLE(value uint32) {
	volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetRNG_CFG_RNG_SAMPLE_ENABLE() uint32 {
	return volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1
}
func (o *HP_SYS_Type) SetRNG_CFG_RNG_CHAIN_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_Type) GetRNG_CFG_RNG_CHAIN_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_Type) SetRNG_CFG_RNG_SAMPLE_CNT(value uint32) {
	volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0xff000000)|value<<24)
}
func (o *HP_SYS_Type) GetRNG_CFG_RNG_SAMPLE_CNT() uint32 {
	return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0xff000000) >> 24
}

// HP_SYS.UART_PD_CTRL: ecc pd ctrl register
func (o *HP_SYS_Type) SetUART_PD_CTRL_UART_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.UART_PD_CTRL.Reg, volatile.LoadUint32(&o.UART_PD_CTRL.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetUART_PD_CTRL_UART_MEM_FORCE_PD() uint32 {
	return volatile.LoadUint32(&o.UART_PD_CTRL.Reg) & 0x1
}
func (o *HP_SYS_Type) SetUART_PD_CTRL_UART_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.UART_PD_CTRL.Reg, volatile.LoadUint32(&o.UART_PD_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetUART_PD_CTRL_UART_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.UART_PD_CTRL.Reg) & 0x2) >> 1
}

// HP_SYS.PERI_MEM_CLK_FORCE_ON: hp peri mem clk force on regpster
func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_RMT_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x1)|value)
}
func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_RMT_MEM_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x1
}
func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x2) >> 1
}
func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x4) >> 2
}
func (o *HP_SYS_Type) SetPERI_MEM_CLK_FORCE_ON_GDMA_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg, volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_Type) GetPERI_MEM_CLK_FORCE_ON_GDMA_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.PERI_MEM_CLK_FORCE_ON.Reg) & 0x8) >> 3
}

// HP_SYS_CLKRST Peripheral
type HP_SYS_CLKRST_Type struct {
	CLK_EN0                  volatile.Register32 // 0x0
	ROOT_CLK_CTRL0           volatile.Register32 // 0x4
	ROOT_CLK_CTRL1           volatile.Register32 // 0x8
	ROOT_CLK_CTRL2           volatile.Register32 // 0xC
	ROOT_CLK_CTRL3           volatile.Register32 // 0x10
	SOC_CLK_CTRL0            volatile.Register32 // 0x14
	SOC_CLK_CTRL1            volatile.Register32 // 0x18
	SOC_CLK_CTRL2            volatile.Register32 // 0x1C
	SOC_CLK_CTRL3            volatile.Register32 // 0x20
	REF_CLK_CTRL0            volatile.Register32 // 0x24
	REF_CLK_CTRL1            volatile.Register32 // 0x28
	REF_CLK_CTRL2            volatile.Register32 // 0x2C
	PERI_CLK_CTRL00          volatile.Register32 // 0x30
	PERI_CLK_CTRL01          volatile.Register32 // 0x34
	PERI_CLK_CTRL02          volatile.Register32 // 0x38
	PERI_CLK_CTRL03          volatile.Register32 // 0x3C
	PERI_CLK_CTRL10          volatile.Register32 // 0x40
	PERI_CLK_CTRL11          volatile.Register32 // 0x44
	PERI_CLK_CTRL12          volatile.Register32 // 0x48
	PERI_CLK_CTRL13          volatile.Register32 // 0x4C
	PERI_CLK_CTRL14          volatile.Register32 // 0x50
	PERI_CLK_CTRL15          volatile.Register32 // 0x54
	PERI_CLK_CTRL16          volatile.Register32 // 0x58
	PERI_CLK_CTRL17          volatile.Register32 // 0x5C
	PERI_CLK_CTRL18          volatile.Register32 // 0x60
	PERI_CLK_CTRL19          volatile.Register32 // 0x64
	PERI_CLK_CTRL110         volatile.Register32 // 0x68
	PERI_CLK_CTRL111         volatile.Register32 // 0x6C
	PERI_CLK_CTRL112         volatile.Register32 // 0x70
	PERI_CLK_CTRL113         volatile.Register32 // 0x74
	PERI_CLK_CTRL114         volatile.Register32 // 0x78
	PERI_CLK_CTRL115         volatile.Register32 // 0x7C
	PERI_CLK_CTRL116         volatile.Register32 // 0x80
	PERI_CLK_CTRL117         volatile.Register32 // 0x84
	PERI_CLK_CTRL118         volatile.Register32 // 0x88
	PERI_CLK_CTRL119         volatile.Register32 // 0x8C
	PERI_CLK_CTRL120         volatile.Register32 // 0x90
	PERI_CLK_CTRL20          volatile.Register32 // 0x94
	PERI_CLK_CTRL21          volatile.Register32 // 0x98
	PERI_CLK_CTRL22          volatile.Register32 // 0x9C
	PERI_CLK_CTRL23          volatile.Register32 // 0xA0
	PERI_CLK_CTRL24          volatile.Register32 // 0xA4
	PERI_CLK_CTRL25          volatile.Register32 // 0xA8
	PERI_CLK_CTRL26          volatile.Register32 // 0xAC
	PERI_CLK_CTRL27          volatile.Register32 // 0xB0
	CLK_FORCE_ON_CTRL0       volatile.Register32 // 0xB4
	DPA_CTRL0                volatile.Register32 // 0xB8
	ANA_PLL_CTRL0            volatile.Register32 // 0xBC
	HP_RST_EN0               volatile.Register32 // 0xC0
	HP_RST_EN1               volatile.Register32 // 0xC4
	HP_RST_EN2               volatile.Register32 // 0xC8
	HP_FORCE_NORST0          volatile.Register32 // 0xCC
	HP_FORCE_NORST1          volatile.Register32 // 0xD0
	HPWDT_CORE0_RST_CTRL0    volatile.Register32 // 0xD4
	HPWDT_CORE1_RST_CTRL0    volatile.Register32 // 0xD8
	CPU_SRC_FREQ0            volatile.Register32 // 0xDC
	CPU_CLK_STATUS0          volatile.Register32 // 0xE0
	DBG_CLK_CTRL0            volatile.Register32 // 0xE4
	DBG_CLK_CTRL1            volatile.Register32 // 0xE8
	HPCORE_WDT_RESET_SOURCE0 volatile.Register32 // 0xEC
}

// HP_SYS_CLKRST.CLK_EN0: Reserved
func (o *HP_SYS_CLKRST_Type) SetCLK_EN0_REG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN0.Reg, volatile.LoadUint32(&o.CLK_EN0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_EN0_REG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN0.Reg) & 0x1
}

// HP_SYS_CLKRST.ROOT_CLK_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPUICM_DELAY_NUM(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0xf)|value)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPUICM_DELAY_NUM() uint32 {
	return volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0xf
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_SOC_CLK_DIV_UPDATE(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_SOC_CLK_DIV_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x1fe0)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x1fe0) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x1fe000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x1fe000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL0.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg)&^(0x1fe00000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL0_REG_CPU_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL0.Reg) & 0x1fe00000) >> 21
}

// HP_SYS_CLKRST.ROOT_CLK_CTRL1: Reserved
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_MEM_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL1_REG_SYS_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL1.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg)&^(0xff000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL1_REG_SYS_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL1.Reg) & 0xff000000) >> 24
}

// HP_SYS_CLKRST.ROOT_CLK_CTRL2: Reserved
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_NUMERATOR() uint32 {
	return volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_SYS_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL2.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg)&^(0xff000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.ROOT_CLK_CTRL2.Reg) & 0xff000000) >> 24
}

// HP_SYS_CLKRST.ROOT_CLK_CTRL3: Reserved
func (o *HP_SYS_CLKRST_Type) SetROOT_CLK_CTRL3_REG_APB_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.ROOT_CLK_CTRL3.Reg, volatile.LoadUint32(&o.ROOT_CLK_CTRL3.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetROOT_CLK_CTRL3_REG_APB_CLK_DIV_DENOMINATOR() uint32 {
	return volatile.LoadUint32(&o.ROOT_CLK_CTRL3.Reg) & 0xff
}

// HP_SYS_CLKRST.SOC_CLK_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE0_CLIC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE0_CLIC_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE1_CLIC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE1_CLIC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_MISC_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_MISC_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE0_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE0_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_CORE1_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_CORE1_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TCM_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TCM_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_BUSMON_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_BUSMON_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_D_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_D_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I0_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I0_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I1_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I1_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TRACE_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TRACE_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_ICM_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_ICM_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_GDMA_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_GDMA_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_VPU_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_VPU_CPU_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_D_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_D_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I0_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I0_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L1CACHE_I1_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L1CACHE_I1_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2CACHE_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2CACHE_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEM_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEM_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEMMON_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEMMON_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_ICM_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_ICM_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_MISC_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_MISC_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TRACE_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TRACE_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2CACHE_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2CACHE_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEM_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEM_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_L2MEMMON_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_L2MEMMON_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_TCMMON_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_TCMMON_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_ICM_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_ICM_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_FLASH_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_FLASH_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL0_REG_PSRAM_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL0.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL0_REG_PSRAM_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL0.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.SOC_CLK_CTRL1: Reserved
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_GPSPI2_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_GPSPI2_SYS_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_GPSPI3_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_GPSPI3_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_REGDMA_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_REGDMA_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_AHB_PDMA_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_AHB_PDMA_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_AXI_PDMA_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_AXI_PDMA_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_GDMA_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_GDMA_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_DMA2D_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_DMA2D_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_VPU_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_VPU_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_JPEG_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_JPEG_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_PPA_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_PPA_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_CSI_BRG_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_CSI_BRG_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_CSI_HOST_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_CSI_HOST_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_DSI_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_DSI_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_EMAC_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_EMAC_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_SDMMC_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_SDMMC_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_USB_OTG11_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_USB_OTG11_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_USB_OTG20_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_USB_OTG20_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UHCI_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UHCI_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART0_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART0_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART1_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART1_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART2_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART2_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART3_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART3_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_UART4_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_UART4_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_PARLIO_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_PARLIO_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_ETM_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_ETM_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_PVT_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_PVT_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_CRYPTO_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_CRYPTO_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_KEY_MANAGER_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_KEY_MANAGER_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_BITSRAMBLER_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_BITSRAMBLER_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_BITSRAMBLER_RX_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_BITSRAMBLER_RX_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_BITSRAMBLER_TX_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_BITSRAMBLER_TX_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL1_REG_H264_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL1.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL1_REG_H264_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL1.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.SOC_CLK_CTRL2: Reserved
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_RMT_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_RMT_SYS_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_HP_CLKRST_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_HP_CLKRST_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_SYSREG_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_SYSREG_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_ICM_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_ICM_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_INTRMTX_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_INTRMTX_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_ADC_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_ADC_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UHCI_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UHCI_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART0_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART0_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART1_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART1_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART2_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART2_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART3_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART3_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_UART4_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_UART4_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2C0_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2C0_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2C1_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2C1_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2S0_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2S0_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2S1_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2S1_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I2S2_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I2S2_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I3C_MST_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I3C_MST_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_I3C_SLV_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_I3C_SLV_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_GPSPI2_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_GPSPI2_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_GPSPI3_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_GPSPI3_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TIMERGRP0_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TIMERGRP0_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TIMERGRP1_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TIMERGRP1_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_SYSTIMER_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_SYSTIMER_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TWAI0_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TWAI0_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TWAI1_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TWAI1_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_TWAI2_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_TWAI2_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_MCPWM0_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_MCPWM0_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_MCPWM1_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_MCPWM1_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_USB_DEVICE_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_USB_DEVICE_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_PCNT_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_PCNT_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL2_REG_PARLIO_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL2.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL2_REG_PARLIO_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL2.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.SOC_CLK_CTRL3: Reserved
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_LEDC_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_LEDC_APB_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_LCDCAM_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_LCDCAM_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_ETM_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_ETM_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetSOC_CLK_CTRL3_REG_IOMUX_APB_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SOC_CLK_CTRL3.Reg, volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetSOC_CLK_CTRL3_REG_IOMUX_APB_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SOC_CLK_CTRL3.Reg) & 0x8) >> 3
}

// HP_SYS_CLKRST.REF_CLK_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_50M_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_50M_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_25M_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_25M_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_240M_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_240M_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL0_REG_REF_160M_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL0.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg)&^(0xff000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL0_REG_REF_160M_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL0.Reg) & 0xff000000) >> 24
}

// HP_SYS_CLKRST.REF_CLK_CTRL1: Reserved
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_120M_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_120M_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_80M_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_80M_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_20M_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_20M_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_400M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_400M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_200M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_200M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_100M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_100M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_50M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_50M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_25M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_25M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_480M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_480M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_REF_240M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_REF_240M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL1_REG_TM_240M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL1.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL1_REG_TM_240M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL1.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.REF_CLK_CTRL2: Reserved
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_160M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_160M_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_160M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_160M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_120M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_120M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_120M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_120M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_80M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_80M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_80M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_80M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_60M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_60M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_48M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_48M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_REF_20M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_REF_20M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetREF_CLK_CTRL2_REG_TM_20M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REF_CLK_CTRL2.Reg, volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetREF_CLK_CTRL2_REG_TM_20M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REF_CLK_CTRL2.Reg) & 0x200) >> 9
}

// HP_SYS_CLKRST.PERI_CLK_CTRL00: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x3)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_CLK_SRC_SEL() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x3
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_PLL_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_PLL_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0xff0)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_FLASH_CORE_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0xff0) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x3000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x3000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_PLL_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_PLL_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_PAD_EMAC_REF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_PAD_EMAC_REF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x6000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x6000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RMII_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL00.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL00_REG_EMAC_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL00.Reg) & 0x20000000) >> 29
}

// HP_SYS_CLKRST.PERI_CLK_CTRL01: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_RX_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_RX_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x3fc00)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_TX_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x3fc00) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_UNUSED0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_UNUSED0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_EMAC_UNUSED1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_EMAC_UNUSED1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_SDIO_HS_MODE(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_SDIO_HS_MODE() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL01.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL01_REG_SDIO_LS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL01.Reg) & 0x1000000) >> 24
}

// HP_SYS_CLKRST.PERI_CLK_CTRL02: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_L(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1e00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_L() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1e00) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_H(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1e000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_H() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1e000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_N(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1e0000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_N() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1e0000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EDGE_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x600000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EDGE_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x600000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EDGE_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x1800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EDGE_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x1800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EDGE_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x6000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EDGE_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x6000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL02_REG_MIPI_DSI_DPHY_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL02.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg)&^(0xc0000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL02_REG_MIPI_DSI_DPHY_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL02.Reg) & 0xc0000000) >> 30
}

// HP_SYS_CLKRST.PERI_CLK_CTRL03: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_CFG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_CFG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0xc)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0xc) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CFG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CFG_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x60)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x60) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL03.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL03.Reg) & 0xff00) >> 8
}

// HP_SYS_CLKRST.PERI_CLK_CTRL10: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_SRC_SEL() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x3fc)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x3fc) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x3fc00)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x3fc00) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x3fc0000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C0_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x3fc0000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C1_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C1_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL10_REG_I2C1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL10.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL10_REG_I2C1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL10.Reg) & 0x8000000) >> 27
}

// HP_SYS_CLKRST.PERI_CLK_CTRL11: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2C1_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL11.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg)&^(0x6000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL11_REG_I2S0_RX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL11.Reg) & 0x6000000) >> 25
}

// HP_SYS_CLKRST.PERI_CLK_CTRL12: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_N(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL12.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_N() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_X(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL12.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg)&^(0x1ff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_X() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg) & 0x1ff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL12.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg)&^(0x3fe0000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL12_REG_I2S0_RX_DIV_Y() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL12.Reg) & 0x3fe0000) >> 17
}

// HP_SYS_CLKRST.PERI_CLK_CTRL13: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_Z() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x1ff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_RX_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x1800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x1800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_N(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x1fe000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_N() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x1fe000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_X(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL13.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg)&^(0x3fe00000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL13_REG_I2S0_TX_DIV_X() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL13.Reg) & 0x3fe00000) >> 21
}

// HP_SYS_CLKRST.PERI_CLK_CTRL14: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Y() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x1ff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x3fe00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_Z() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x3fe00) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_TX_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S0_MST_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S0_MST_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x600000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S1_RX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x600000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL14_REG_I2S1_RX_DIV_N(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL14.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg)&^(0x7f800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL14_REG_I2S1_RX_DIV_N() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL14.Reg) & 0x7f800000) >> 23
}

// HP_SYS_CLKRST.PERI_CLK_CTRL15: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_X(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_X() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x1ff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x3fe00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Y() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x3fe00) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x7fc0000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_Z() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x7fc0000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_RX_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL15.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg)&^(0x60000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL15_REG_I2S1_TX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL15.Reg) & 0x60000000) >> 29
}

// HP_SYS_CLKRST.PERI_CLK_CTRL16: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_N(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL16.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_N() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_X(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL16.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg)&^(0x1ff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_X() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg) & 0x1ff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL16.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg)&^(0x3fe0000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL16_REG_I2S1_TX_DIV_Y() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL16.Reg) & 0x3fe0000) >> 17
}

// HP_SYS_CLKRST.PERI_CLK_CTRL17: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_Z() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x1ff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S1_TX_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S1_MST_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S1_MST_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x3000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x3000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_N(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x3fc000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_N() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x3fc000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_X(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL17.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg)&^(0x7fc00000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL17_REG_I2S2_RX_DIV_X() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL17.Reg) & 0x7fc00000) >> 22
}

// HP_SYS_CLKRST.PERI_CLK_CTRL18: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Y() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x1ff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x3fe00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_Z() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x3fe00) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_RX_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x300000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_TX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x300000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL18_REG_I2S2_TX_DIV_N(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL18.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg)&^(0x3fc00000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL18_REG_I2S2_TX_DIV_N() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL18.Reg) & 0x3fc00000) >> 22
}

// HP_SYS_CLKRST.PERI_CLK_CTRL19: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_X(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x1ff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_X() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x1ff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x3fe00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Y() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x3fe00) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x7fc0000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_Z() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x7fc0000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_TX_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_I2S2_MST_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_I2S2_MST_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_LCD_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x60000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_LCD_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x60000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL19_REG_LCD_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL19.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL19_REG_LCD_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL19.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.PERI_CLK_CTRL110: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_LCD_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_UART0_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0x3000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_UART0_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0x3000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL110_REG_UART0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL110.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL110_REG_UART0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL110.Reg) & 0x4000000) >> 26
}

// HP_SYS_CLKRST.PERI_CLK_CTRL111: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART0_SCLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART1_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0x3000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART1_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0x3000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL111_REG_UART1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL111.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL111_REG_UART1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL111.Reg) & 0x4000000) >> 26
}

// HP_SYS_CLKRST.PERI_CLK_CTRL112: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART1_SCLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART2_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0x3000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART2_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0x3000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL112_REG_UART2_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL112.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL112_REG_UART2_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL112.Reg) & 0x4000000) >> 26
}

// HP_SYS_CLKRST.PERI_CLK_CTRL113: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART2_SCLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART3_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0x3000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART3_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0x3000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL113_REG_UART3_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL113.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL113_REG_UART3_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL113.Reg) & 0x4000000) >> 26
}

// HP_SYS_CLKRST.PERI_CLK_CTRL114: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART3_SCLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART4_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0x3000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART4_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0x3000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL114_REG_UART4_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL114.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL114_REG_UART4_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL114.Reg) & 0x4000000) >> 26
}

// HP_SYS_CLKRST.PERI_CLK_CTRL115: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_UART4_SCLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI0_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI0_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI1_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI1_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI2_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI2_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL115_REG_TWAI2_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL115.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL115_REG_TWAI2_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL115.Reg) & 0x20000000) >> 29
}

// HP_SYS_CLKRST.PERI_CLK_CTRL116: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x7)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_CLK_SRC_SEL() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x7
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0xff0)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0xff0) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0xff000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0xff000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI3_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0xe00000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI3_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0xe00000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL116_REG_GPSPI3_HS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL116.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL116_REG_GPSPI3_HS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL116.Reg) & 0x1000000) >> 24
}

// HP_SYS_CLKRST.PERI_CLK_CTRL117: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_GPSPI3_HS_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_GPSPI3_HS_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0x60000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0x60000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL117.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg)&^(0xff00000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL117_REG_PARLIO_RX_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL117.Reg) & 0xff00000) >> 20
}

// HP_SYS_CLKRST.PERI_CLK_CTRL118: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_NUMERATOR() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0x30000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0x30000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL118.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg)&^(0x7f80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL118_REG_PARLIO_TX_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL118.Reg) & 0x7f80000) >> 19
}

// HP_SYS_CLKRST.PERI_CLK_CTRL119: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_NUMERATOR() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_I3C_MST_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x30000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_I3C_MST_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x30000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_I3C_MST_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_I3C_MST_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_I3C_MST_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x7f80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_I3C_MST_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x7f80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_CAM_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x18000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_CAM_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x18000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL119_REG_CAM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL119.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL119_REG_CAM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL119.Reg) & 0x20000000) >> 29
}

// HP_SYS_CLKRST.PERI_CLK_CTRL120: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL120.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL120.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL120.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL120_REG_CAM_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL120.Reg) & 0xff0000) >> 16
}

// HP_SYS_CLKRST.PERI_CLK_CTRL20: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM0_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x3)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM0_CLK_SRC_SEL() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x3
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM0_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x7f8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM0_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x7f8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM1_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x1800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM1_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x1800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_MCPWM1_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x3fc000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_MCPWM1_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x3fc000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0xc00000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0xc00000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x6000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x6000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_T1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x30000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x30000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_WDT_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL20_REG_TIMERGRP0_TGRT_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL20.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL20_REG_TIMERGRP0_TGRT_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL20.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.PERI_CLK_CTRL21: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0xf)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_SRC_SEL() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0xf
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0xffff0)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0xffff0) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x300000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x300000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x1800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x1800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_T1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0xc000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0xc000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_TIMERGRP1_WDT_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL21.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL21_REG_SYSTIMER_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL21.Reg) & 0x40000000) >> 30
}

// HP_SYS_CLKRST.PERI_CLK_CTRL22: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_LEDC_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_LEDC_CLK_SRC_SEL() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_LEDC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_LEDC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x18)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x18) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3fc0)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3fc0) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3fc000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3fc000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0x3fc00000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_RMT_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0x3fc00000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL22_REG_ADC_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL22.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg)&^(0xc0000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL22_REG_ADC_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL22.Reg) & 0xc0000000) >> 30
}

// HP_SYS_CLKRST.PERI_CLK_CTRL23: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1fe)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1fe) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUMERATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1fe00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUMERATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1fe00) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_DENOMINATOR(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL23.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg)&^(0x1fe0000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL23_REG_ADC_CLK_DIV_DENOMINATOR() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL23.Reg) & 0x1fe0000) >> 17
}

// HP_SYS_CLKRST.PERI_CLK_CTRL24: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_ADC_SAR1_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_ADC_SAR1_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_ADC_SAR2_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_ADC_SAR2_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_PVT_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_PVT_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL24_REG_PVT_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL24.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL24_REG_PVT_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL24.Reg) & 0x1000000) >> 24
}

// HP_SYS_CLKRST.PERI_CLK_CTRL25: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP2_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP2_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP3_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP3_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP4_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_PVT_PERI_GROUP4_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x3000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x3000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_AES_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_AES_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_DS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_DS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_ECC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_ECC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_HMAC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_HMAC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_RSA_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_RSA_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_SEC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_SEC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_SHA_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_SHA_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_ECDSA_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_ECDSA_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_CRYPTO_KM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_CRYPTO_KM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_ISP_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x1800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_ISP_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x1800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL25_REG_ISP_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL25.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL25_REG_ISP_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL25.Reg) & 0x2000000) >> 25
}

// HP_SYS_CLKRST.PERI_CLK_CTRL26: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_ISP_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_ISP_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_IOMUX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_IOMUX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_IOMUX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_IOMUX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_IOMUX_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x3fc00)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_IOMUX_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x3fc00) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_H264_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_H264_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_H264_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_H264_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_H264_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0xff00000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_H264_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0xff00000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL26.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL26_REG_PADBIST_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL26.Reg) & 0x20000000) >> 29
}

// HP_SYS_CLKRST.PERI_CLK_CTRL27: Reserved
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_RX_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_RX_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.PERI_CLK_CTRL27.Reg, volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg)&^(0x3fc00)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetPERI_CLK_CTRL27_REG_PADBIST_TX_CLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.PERI_CLK_CTRL27.Reg) & 0x3fc00) >> 10
}

// HP_SYS_CLKRST.CLK_FORCE_ON_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_CPUICM_GATED_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_CPUICM_GATED_CLK_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_TCM_CPU_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_TCM_CPU_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_BUSMON_CPU_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_BUSMON_CPU_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_CPU_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_CPU_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_CPU_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_CPU_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_CPU_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_CPU_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_CPU_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_CPU_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_TRACE_CPU_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_TRACE_CPU_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_TRACE_SYS_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_TRACE_SYS_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_D_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L2CACHE_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L2CACHE_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_L2MEM_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_L2MEM_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_SAR1_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_SAR1_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_SAR2_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_SAR2_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetCLK_FORCE_ON_CTRL0_REG_GMAC_TX_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_FORCE_ON_CTRL0.Reg, volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetCLK_FORCE_ON_CTRL0_REG_GMAC_TX_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_FORCE_ON_CTRL0.Reg) & 0x20000) >> 17
}

// HP_SYS_CLKRST.DPA_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetDPA_CTRL0_REG_SEC_DPA_LEVEL(value uint32) {
	volatile.StoreUint32(&o.DPA_CTRL0.Reg, volatile.LoadUint32(&o.DPA_CTRL0.Reg)&^(0x3)|value)
}
func (o *HP_SYS_CLKRST_Type) GetDPA_CTRL0_REG_SEC_DPA_LEVEL() uint32 {
	return volatile.LoadUint32(&o.DPA_CTRL0.Reg) & 0x3
}
func (o *HP_SYS_CLKRST_Type) SetDPA_CTRL0_REG_SEC_DPA_CFG_SEL(value uint32) {
	volatile.StoreUint32(&o.DPA_CTRL0.Reg, volatile.LoadUint32(&o.DPA_CTRL0.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetDPA_CTRL0_REG_SEC_DPA_CFG_SEL() uint32 {
	return (volatile.LoadUint32(&o.DPA_CTRL0.Reg) & 0x4) >> 2
}

// HP_SYS_CLKRST.ANA_PLL_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_PLLA_CAL_END(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_PLLA_CAL_END() uint32 {
	return volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_PLLA_CAL_STOP(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_PLLA_CAL_STOP() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_CPU_PLL_CAL_END(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_CPU_PLL_CAL_END() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_CPU_PLL_CAL_STOP(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_CPU_PLL_CAL_STOP() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_END(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_END() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_STOP(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SDIO_PLL_CAL_STOP() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SYS_PLL_CAL_END(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SYS_PLL_CAL_END() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_SYS_PLL_CAL_STOP(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_SYS_PLL_CAL_STOP() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_MSPI_CAL_END(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_MSPI_CAL_END() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetANA_PLL_CTRL0_REG_MSPI_CAL_STOP(value uint32) {
	volatile.StoreUint32(&o.ANA_PLL_CTRL0.Reg, volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetANA_PLL_CTRL0_REG_MSPI_CAL_STOP() uint32 {
	return (volatile.LoadUint32(&o.ANA_PLL_CTRL0.Reg) & 0x200) >> 9
}

// HP_SYS_CLKRST.HP_RST_EN0: Reserved
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORECTRL(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORECTRL() uint32 {
	return volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_TOP(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_TOP() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP1(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP1() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP2(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP2() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP3(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP3() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP4(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP4() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_REGDMA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_REGDMA() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORE0_GLOBAL(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORE0_GLOBAL() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORE1_GLOBAL(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORE1_GLOBAL() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORETRACE0(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORETRACE0() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CORETRACE1(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CORETRACE1() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_HP_TCM(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_HP_TCM() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_HP_CACHE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_HP_CACHE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L1_I0_CACHE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L1_I0_CACHE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L1_I1_CACHE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L1_I1_CACHE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L1_D_CACHE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L1_D_CACHE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L2_CACHE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L2_CACHE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L2_MEM(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L2_MEM() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_L2MEMMON(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_L2MEMMON() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_TCMMON(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_TCMMON() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_PVT_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_PVT_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_GDMA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_GDMA() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_MSPI_AXI(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_MSPI_AXI() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_AXI(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_AXI() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_MSPI_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_MSPI_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DUAL_MSPI_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DSI_BRG(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DSI_BRG() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CSI_HOST(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CSI_HOST() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_CSI_BRG(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_CSI_BRG() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_ISP(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_ISP() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_JPEG(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_JPEG() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN0_REG_RST_EN_DMA2D(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN0.Reg, volatile.LoadUint32(&o.HP_RST_EN0.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN0_REG_RST_EN_DMA2D() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN0.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.HP_RST_EN1: Reserved
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PPA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PPA() uint32 {
	return volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_AHB_PDMA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_AHB_PDMA() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_AXI_PDMA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_AXI_PDMA() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_IOMUX(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_IOMUX() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PADBIST(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PADBIST() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_STIMER(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_STIMER() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_TIMERGRP0(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_TIMERGRP0() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_TIMERGRP1(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_TIMERGRP1() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART0_CORE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART0_CORE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART1_CORE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART1_CORE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART2_CORE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART2_CORE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART3_CORE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART3_CORE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART4_CORE(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART4_CORE() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART0_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART0_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART1_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART1_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART2_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART2_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART3_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART3_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UART4_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UART4_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_UHCI(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_UHCI() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I3CMST(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I3CMST() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I3CSLV(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I3CSLV() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I2C1(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I2C1() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_I2C0(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_I2C0() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_RMT(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_RMT() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PWM0(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PWM0() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PWM1(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PWM1() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_CAN0(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_CAN0() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_CAN1(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_CAN1() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_CAN2(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_CAN2() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_LEDC(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_LEDC() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_PCNT(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_PCNT() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN1_REG_RST_EN_ETM(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN1.Reg, volatile.LoadUint32(&o.HP_RST_EN1.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN1_REG_RST_EN_ETM() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN1.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.HP_RST_EN2: Reserved
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_INTRMTX(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_INTRMTX() uint32 {
	return volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_PARLIO(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_PARLIO() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_PARLIO_RX(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_PARLIO_RX() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_PARLIO_TX(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_PARLIO_TX() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_I2S0_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_I2S0_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_I2S1_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_I2S1_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_I2S2_APB(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_I2S2_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SPI2(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SPI2() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SPI3(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SPI3() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_LCDCAM(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_LCDCAM() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_ADC(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_ADC() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_BITSRAMBLER(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_BITSRAMBLER() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_RX(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_RX() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_TX(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_BITSRAMBLER_TX() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_CRYPTO(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_CRYPTO() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SEC(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SEC() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_AES(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_AES() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_DS(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_DS() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_SHA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_SHA() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_HMAC(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_HMAC() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_ECDSA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_ECDSA() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_RSA(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_RSA() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_ECC(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_ECC() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_KM(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_KM() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetHP_RST_EN2_REG_RST_EN_H264(value uint32) {
	volatile.StoreUint32(&o.HP_RST_EN2.Reg, volatile.LoadUint32(&o.HP_RST_EN2.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetHP_RST_EN2_REG_RST_EN_H264() uint32 {
	return (volatile.LoadUint32(&o.HP_RST_EN2.Reg) & 0x1000000) >> 24
}

// HP_SYS_CLKRST.HP_FORCE_NORST0: Reserved
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORE0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORE0() uint32 {
	return volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORE1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORE1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE0() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_L2MEMMON(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_L2MEMMON() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_TCMMON(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_TCMMON() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_GDMA(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_GDMA() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_AXI(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_AXI() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_AXI(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_AXI() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_APB(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_MSPI_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_APB(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_APB() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DSI_BRG(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DSI_BRG() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_HOST(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_HOST() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_BRG(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_CSI_BRG() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_ISP(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_ISP() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_JPEG(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_JPEG() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_DMA2D(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_DMA2D() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_PPA(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_PPA() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_AHB_PDMA(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_AHB_PDMA() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_AXI_PDMA(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_AXI_PDMA() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_IOMUX(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_IOMUX() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_PADBIST(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_PADBIST() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_STIMER(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_STIMER() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP0() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART0() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x4000000) >> 26
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART2(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x8000000)|value<<27)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART2() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x8000000) >> 27
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART3(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x10000000)|value<<28)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART3() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x10000000) >> 28
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UART4(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x20000000)|value<<29)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UART4() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x20000000) >> 29
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_UHCI(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x40000000)|value<<30)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_UHCI() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x40000000) >> 30
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST0_REG_FORCE_NORST_I3CMST(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST0.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg)&^(0x80000000)|value<<31)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST0_REG_FORCE_NORST_I3CMST() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST0.Reg) & 0x80000000) >> 31
}

// HP_SYS_CLKRST.HP_FORCE_NORST1: Reserved
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I3CSLV(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I3CSLV() uint32 {
	return volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2C1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2C1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2C0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2C0() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_RMT(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_RMT() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PWM0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x10)|value<<4)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PWM0() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x10) >> 4
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PWM1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x20)|value<<5)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PWM1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x20) >> 5
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_CAN0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x40)|value<<6)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_CAN0() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x40) >> 6
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_CAN1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x80)|value<<7)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_CAN1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x80) >> 7
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_CAN2(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x100)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_CAN2() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x100) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_LEDC(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x200)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_LEDC() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x200) >> 9
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PCNT(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x400)|value<<10)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PCNT() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x400) >> 10
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_ETM(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_ETM() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_INTRMTX(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x1000)|value<<12)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_INTRMTX() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x1000) >> 12
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x2000)|value<<13)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x2000) >> 13
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_RX(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x4000)|value<<14)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_RX() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x4000) >> 14
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_TX(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x8000)|value<<15)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_TX() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x8000) >> 15
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2S0(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2S0() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2S1(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2S1() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_I2S2(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_I2S2() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x40000) >> 18
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_SPI2(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_SPI2() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x80000) >> 19
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_SPI3(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x100000)|value<<20)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_SPI3() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x100000) >> 20
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_LCDCAM(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x200000)|value<<21)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_LCDCAM() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x200000) >> 21
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_ADC(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x400000)|value<<22)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_ADC() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x400000) >> 22
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x800000)|value<<23)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x800000) >> 23
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_RX(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x1000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_RX() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x1000000) >> 24
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_TX(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x2000000)|value<<25)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_TX() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x2000000) >> 25
}
func (o *HP_SYS_CLKRST_Type) SetHP_FORCE_NORST1_REG_FORCE_NORST_H264(value uint32) {
	volatile.StoreUint32(&o.HP_FORCE_NORST1.Reg, volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg)&^(0x4000000)|value<<26)
}
func (o *HP_SYS_CLKRST_Type) GetHP_FORCE_NORST1_REG_FORCE_NORST_H264() uint32 {
	return (volatile.LoadUint32(&o.HP_FORCE_NORST1.Reg) & 0x4000000) >> 26
}

// HP_SYS_CLKRST.HPWDT_CORE0_RST_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_EN() uint32 {
	return volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_WAIT_NUM(value uint32) {
	volatile.StoreUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg)&^(0x1fe)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_WAIT_NUM() uint32 {
	return (volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg) & 0x1fe) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE0_RST_CTRL0_REG_WDT_HPCORE0_RST_LEN(value uint32) {
	volatile.StoreUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg)&^(0x1fe00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE0_RST_CTRL0_REG_WDT_HPCORE0_RST_LEN() uint32 {
	return (volatile.LoadUint32(&o.HPWDT_CORE0_RST_CTRL0.Reg) & 0x1fe00) >> 9
}

// HP_SYS_CLKRST.HPWDT_CORE1_RST_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_EN() uint32 {
	return volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_WAIT_NUM(value uint32) {
	volatile.StoreUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg)&^(0x1fe)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_WAIT_NUM() uint32 {
	return (volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg) & 0x1fe) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetHPWDT_CORE1_RST_CTRL0_REG_WDT_HPCORE1_RST_LEN(value uint32) {
	volatile.StoreUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg, volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg)&^(0x1fe00)|value<<9)
}
func (o *HP_SYS_CLKRST_Type) GetHPWDT_CORE1_RST_CTRL0_REG_WDT_HPCORE1_RST_LEN() uint32 {
	return (volatile.LoadUint32(&o.HPWDT_CORE1_RST_CTRL0.Reg) & 0x1fe00) >> 9
}

// HP_SYS_CLKRST.CPU_SRC_FREQ0: CPU Source Frequency
func (o *HP_SYS_CLKRST_Type) SetCPU_SRC_FREQ0(value uint32) {
	volatile.StoreUint32(&o.CPU_SRC_FREQ0.Reg, value)
}
func (o *HP_SYS_CLKRST_Type) GetCPU_SRC_FREQ0() uint32 {
	return volatile.LoadUint32(&o.CPU_SRC_FREQ0.Reg)
}

// HP_SYS_CLKRST.CPU_CLK_STATUS0: CPU Clock Status
func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_ASIC_OR_FPGA(value uint32) {
	volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_ASIC_OR_FPGA() uint32 {
	return volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_EFFECT(value uint32) {
	volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_EFFECT() uint32 {
	return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x2) >> 1
}
func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_SRC_IS_CPLL(value uint32) {
	volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x4)|value<<2)
}
func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_SRC_IS_CPLL() uint32 {
	return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x4) >> 2
}
func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_NUM_CUR(value uint32) {
	volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x7f8)|value<<3)
}
func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_NUM_CUR() uint32 {
	return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x7f8) >> 3
}
func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_NUMERATOR_CUR(value uint32) {
	volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x7f800)|value<<11)
}
func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_NUMERATOR_CUR() uint32 {
	return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x7f800) >> 11
}
func (o *HP_SYS_CLKRST_Type) SetCPU_CLK_STATUS0_REG_CPU_DIV_DENOMINATOR_CUR(value uint32) {
	volatile.StoreUint32(&o.CPU_CLK_STATUS0.Reg, volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg)&^(0x7f80000)|value<<19)
}
func (o *HP_SYS_CLKRST_Type) GetCPU_CLK_STATUS0_REG_CPU_DIV_DENOMINATOR_CUR() uint32 {
	return (volatile.LoadUint32(&o.CPU_CLK_STATUS0.Reg) & 0x7f80000) >> 19
}

// HP_SYS_CLKRST.DBG_CLK_CTRL0: Reserved
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH0_SEL(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH0_SEL() uint32 {
	return volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH1_SEL(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH1_SEL() uint32 {
	return (volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH2_SEL(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff0000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH2_SEL() uint32 {
	return (volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff0000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL0_REG_DBG_CH0_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL0.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg)&^(0xff000000)|value<<24)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL0_REG_DBG_CH0_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.DBG_CLK_CTRL0.Reg) & 0xff000000) >> 24
}

// HP_SYS_CLKRST.DBG_CLK_CTRL1: Reserved
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH1_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0xff)|value)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH1_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0xff
}
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH2_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0xff00)|value<<8)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH2_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0xff00) >> 8
}
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0x10000)|value<<16)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH0_EN() uint32 {
	return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0x10000) >> 16
}
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0x20000)|value<<17)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0x20000) >> 17
}
func (o *HP_SYS_CLKRST_Type) SetDBG_CLK_CTRL1_REG_DBG_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.DBG_CLK_CTRL1.Reg, volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg)&^(0x40000)|value<<18)
}
func (o *HP_SYS_CLKRST_Type) GetDBG_CLK_CTRL1_REG_DBG_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.DBG_CLK_CTRL1.Reg) & 0x40000) >> 18
}

// HP_SYS_CLKRST.HPCORE_WDT_RESET_SOURCE0: Reserved
func (o *HP_SYS_CLKRST_Type) SetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE0_WDT_RESET_SOURCE_SEL(value uint32) {
	volatile.StoreUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg, volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg)&^(0x1)|value)
}
func (o *HP_SYS_CLKRST_Type) GetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE0_WDT_RESET_SOURCE_SEL() uint32 {
	return volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg) & 0x1
}
func (o *HP_SYS_CLKRST_Type) SetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE1_WDT_RESET_SOURCE_SEL(value uint32) {
	volatile.StoreUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg, volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg)&^(0x2)|value<<1)
}
func (o *HP_SYS_CLKRST_Type) GetHPCORE_WDT_RESET_SOURCE0_REG_HPCORE1_WDT_RESET_SOURCE_SEL() uint32 {
	return (volatile.LoadUint32(&o.HPCORE_WDT_RESET_SOURCE0.Reg) & 0x2) >> 1
}

// LP_HUK Peripheral
type HUK_Type struct {
	_        [4]byte
	CLK      volatile.Register32 // 0x4
	INT_RAW  volatile.Register32 // 0x8
	INT_ST   volatile.Register32 // 0xC
	INT_ENA  volatile.Register32 // 0x10
	INT_CLR  volatile.Register32 // 0x14
	_        [8]byte
	CONF     volatile.Register32 // 0x20
	START    volatile.Register32 // 0x24
	STATE    volatile.Register32 // 0x28
	_        [8]byte
	STATUS   volatile.Register32 // 0x34
	_        [196]byte
	DATE     volatile.Register32     // 0xFC
	INFO_MEM [96]volatile.Register32 // 0x100
}

// HUK.CLK: HUK Generator clock gate control register
func (o *HUK_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value)
}
func (o *HUK_Type) GetCLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK.Reg) & 0x1
}
func (o *HUK_Type) SetCLK_MEM_CG_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x2)|value<<1)
}
func (o *HUK_Type) GetCLK_MEM_CG_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0x2) >> 1
}

// HUK.INT_RAW: HUK Generator interrupt raw register, valid in level.
func (o *HUK_Type) SetINT_RAW_PREP_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *HUK_Type) GetINT_RAW_PREP_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *HUK_Type) SetINT_RAW_PROC_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *HUK_Type) GetINT_RAW_PROC_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *HUK_Type) SetINT_RAW_POST_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *HUK_Type) GetINT_RAW_POST_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}

// HUK.INT_ST: HUK Generator interrupt status register.
func (o *HUK_Type) SetINT_ST_PREP_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *HUK_Type) GetINT_ST_PREP_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *HUK_Type) SetINT_ST_PROC_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *HUK_Type) GetINT_ST_PROC_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *HUK_Type) SetINT_ST_POST_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *HUK_Type) GetINT_ST_POST_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}

// HUK.INT_ENA: HUK Generator interrupt enable register.
func (o *HUK_Type) SetINT_ENA_PREP_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *HUK_Type) GetINT_ENA_PREP_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *HUK_Type) SetINT_ENA_PROC_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *HUK_Type) GetINT_ENA_PROC_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *HUK_Type) SetINT_ENA_POST_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *HUK_Type) GetINT_ENA_POST_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}

// HUK.INT_CLR: HUK Generator interrupt clear register.
func (o *HUK_Type) SetINT_CLR_PREP_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *HUK_Type) GetINT_CLR_PREP_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *HUK_Type) SetINT_CLR_PROC_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *HUK_Type) GetINT_CLR_PROC_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *HUK_Type) SetINT_CLR_POST_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *HUK_Type) GetINT_CLR_POST_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}

// HUK.CONF: HUK Generator configuration register
func (o *HUK_Type) SetCONF_MODE(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value)
}
func (o *HUK_Type) GetCONF_MODE() uint32 {
	return volatile.LoadUint32(&o.CONF.Reg) & 0x1
}

// HUK.START: HUK Generator control register
func (o *HUK_Type) SetSTART(value uint32) {
	volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x1)|value)
}
func (o *HUK_Type) GetSTART() uint32 {
	return volatile.LoadUint32(&o.START.Reg) & 0x1
}
func (o *HUK_Type) SetSTART_CONTINUE(value uint32) {
	volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0x2)|value<<1)
}
func (o *HUK_Type) GetSTART_CONTINUE() uint32 {
	return (volatile.LoadUint32(&o.START.Reg) & 0x2) >> 1
}

// HUK.STATE: HUK Generator state register
func (o *HUK_Type) SetSTATE(value uint32) {
	volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x3)|value)
}
func (o *HUK_Type) GetSTATE() uint32 {
	return volatile.LoadUint32(&o.STATE.Reg) & 0x3
}

// HUK.STATUS: HUK Generator HUK status register
func (o *HUK_Type) SetSTATUS(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3)|value)
}
func (o *HUK_Type) GetSTATUS() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg) & 0x3
}
func (o *HUK_Type) SetSTATUS_RISK_LEVEL(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1c)|value<<2)
}
func (o *HUK_Type) GetSTATUS_RISK_LEVEL() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1c) >> 2
}

// HUK.DATE: Version control register
func (o *HUK_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *HUK_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// I2C (Inter-Integrated Circuit) Controller 0
type I2C_Type struct {
	SCL_LOW_PERIOD       volatile.Register32 // 0x0
	CTR                  volatile.Register32 // 0x4
	SR                   volatile.Register32 // 0x8
	TO                   volatile.Register32 // 0xC
	SLAVE_ADDR           volatile.Register32 // 0x10
	FIFO_ST              volatile.Register32 // 0x14
	FIFO_CONF            volatile.Register32 // 0x18
	DATA                 volatile.Register32 // 0x1C
	INT_RAW              volatile.Register32 // 0x20
	INT_CLR              volatile.Register32 // 0x24
	INT_ENA              volatile.Register32 // 0x28
	INT_STATUS           volatile.Register32 // 0x2C
	SDA_HOLD             volatile.Register32 // 0x30
	SDA_SAMPLE           volatile.Register32 // 0x34
	SCL_HIGH_PERIOD      volatile.Register32 // 0x38
	_                    [4]byte
	SCL_START_HOLD       volatile.Register32 // 0x40
	SCL_RSTART_SETUP     volatile.Register32 // 0x44
	SCL_STOP_HOLD        volatile.Register32 // 0x48
	SCL_STOP_SETUP       volatile.Register32 // 0x4C
	FILTER_CFG           volatile.Register32 // 0x50
	CLK_CONF             volatile.Register32 // 0x54
	COMD0                volatile.Register32 // 0x58
	COMD1                volatile.Register32 // 0x5C
	COMD2                volatile.Register32 // 0x60
	COMD3                volatile.Register32 // 0x64
	COMD4                volatile.Register32 // 0x68
	COMD5                volatile.Register32 // 0x6C
	COMD6                volatile.Register32 // 0x70
	COMD7                volatile.Register32 // 0x74
	SCL_ST_TIME_OUT      volatile.Register32 // 0x78
	SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C
	SCL_SP_CONF          volatile.Register32 // 0x80
	SCL_STRETCH_CONF     volatile.Register32 // 0x84
	_                    [112]byte
	DATE                 volatile.Register32 // 0xF8
	_                    [4]byte
	TXFIFO_START_ADDR    volatile.Register32 // 0x100
	_                    [124]byte
	RXFIFO_START_ADDR    volatile.Register32 // 0x180
}

// I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock.
func (o *I2C_Type) SetSCL_LOW_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSCL_LOW_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff
}

// I2C.CTR: Transmission setting
func (o *I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 {
	return volatile.LoadUint32(&o.CTR.Reg) & 0x1
}
func (o *I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetCTR_MS_MODE(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetCTR_MS_MODE() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetCTR_TRANS_START(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetCTR_TRANS_START() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetCTR_TX_LSB_FIRST() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetCTR_RX_LSB_FIRST() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetCTR_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetCTR_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetCTR_ARBITRATION_EN(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetCTR_ARBITRATION_EN() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetCTR_FSM_RST(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetCTR_FSM_RST() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetCTR_CONF_UPGATE(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetCTR_CONF_UPGATE() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetCTR_SLV_TX_AUTO_START_EN(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCTR_SLV_TX_AUTO_START_EN() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCTR_ADDR_10BIT_RW_CHECK_EN(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetCTR_ADDR_10BIT_RW_CHECK_EN() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetCTR_ADDR_BROADCASTING_EN(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCTR_ADDR_BROADCASTING_EN() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x4000) >> 14
}

// I2C.SR: Describe I2C work status.
func (o *I2C_Type) SetSR_RESP_REC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetSR_RESP_REC() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *I2C_Type) SetSR_SLAVE_RW(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetSR_SLAVE_RW() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetSR_ARB_LOST(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetSR_ARB_LOST() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetSR_BUS_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetSR_BUS_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetSR_SLAVE_ADDRESSED(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetSR_SLAVE_ADDRESSED() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetSR_RXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8)
}
func (o *I2C_Type) GetSR_RXFIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8
}
func (o *I2C_Type) SetSR_STRETCH_CAUSE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc000)|value<<14)
}
func (o *I2C_Type) GetSR_STRETCH_CAUSE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0xc000) >> 14
}
func (o *I2C_Type) SetSR_TXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xfc0000)|value<<18)
}
func (o *I2C_Type) GetSR_TXFIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0xfc0000) >> 18
}
func (o *I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24)
}
func (o *I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24
}
func (o *I2C_Type) SetSR_SCL_STATE_LAST(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28)
}
func (o *I2C_Type) GetSR_SCL_STATE_LAST() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28
}

// I2C.TO: Setting time out control for receiving data.
func (o *I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) {
	volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value)
}
func (o *I2C_Type) GetTO_TIME_OUT_VALUE() uint32 {
	return volatile.LoadUint32(&o.TO.Reg) & 0x1f
}
func (o *I2C_Type) SetTO_TIME_OUT_EN(value uint32) {
	volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetTO_TIME_OUT_EN() uint32 {
	return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5
}

// I2C.SLAVE_ADDR: Local slave address setting
func (o *I2C_Type) SetSLAVE_ADDR(value uint32) {
	volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x7fff)|value)
}
func (o *I2C_Type) GetSLAVE_ADDR() uint32 {
	return volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x7fff
}
func (o *I2C_Type) SetSLAVE_ADDR_ADDR_10BIT_EN(value uint32) {
	volatile.StoreUint32(&o.SLAVE_ADDR.Reg, volatile.LoadUint32(&o.SLAVE_ADDR.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetSLAVE_ADDR_ADDR_10BIT_EN() uint32 {
	return (volatile.LoadUint32(&o.SLAVE_ADDR.Reg) & 0x80000000) >> 31
}

// I2C.FIFO_ST: FIFO status register.
func (o *I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1f)|value)
}
func (o *I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 {
	return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1f
}
func (o *I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3e0)|value<<5)
}
func (o *I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 {
	return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3e0) >> 5
}
func (o *I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x7c00)|value<<10)
}
func (o *I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 {
	return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x7c00) >> 10
}
func (o *I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf8000)|value<<15)
}
func (o *I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 {
	return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf8000) >> 15
}
func (o *I2C_Type) SetFIFO_ST_SLAVE_RW_POINT(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3fc00000)|value<<22)
}
func (o *I2C_Type) GetFIFO_ST_SLAVE_RW_POINT() uint32 {
	return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3fc00000) >> 22
}

// I2C.FIFO_CONF: FIFO configuration register.
func (o *I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1f)|value)
}
func (o *I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 {
	return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1f
}
func (o *I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x3e0)|value<<5)
}
func (o *I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x3e0) >> 5
}
func (o *I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetFIFO_CONF_FIFO_ADDR_CFG_EN(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetFIFO_CONF_FIFO_ADDR_CFG_EN() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14
}

// I2C.DATA: Rx FIFO read data.
func (o *I2C_Type) SetDATA_FIFO_RDATA(value uint32) {
	volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetDATA_FIFO_RDATA() uint32 {
	return volatile.LoadUint32(&o.DATA.Reg) & 0xff
}

// I2C.INT_RAW: Raw interrupt status
func (o *I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetINT_RAW_SLAVE_STRETCH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetINT_RAW_SLAVE_STRETCH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetINT_RAW_GENERAL_CALL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetINT_RAW_GENERAL_CALL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetINT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}

// I2C.INT_CLR: Interrupt clear bits
func (o *I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetINT_CLR_SLAVE_STRETCH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetINT_CLR_SLAVE_STRETCH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetINT_CLR_GENERAL_CALL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetINT_CLR_GENERAL_CALL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetINT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}

// I2C.INT_ENA: Interrupt enable bits
func (o *I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetINT_ENA_SLAVE_STRETCH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetINT_ENA_SLAVE_STRETCH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetINT_ENA_GENERAL_CALL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetINT_ENA_GENERAL_CALL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetINT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}

// I2C.INT_STATUS: Status of captured I2C communication events
func (o *I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1
}
func (o *I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetINT_STATUS_SLAVE_STRETCH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetINT_STATUS_SLAVE_STRETCH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetINT_STATUS_GENERAL_CALL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetINT_STATUS_GENERAL_CALL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetINT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40000) >> 18
}

// I2C.SDA_HOLD: Configures the hold time after a negative SCL edge.
func (o *I2C_Type) SetSDA_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSDA_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff
}

// I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge.
func (o *I2C_Type) SetSDA_SAMPLE_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSDA_SAMPLE_TIME() uint32 {
	return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff
}

// I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL
func (o *I2C_Type) SetSCL_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSCL_HIGH_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff
}
func (o *I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9)
}
func (o *I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9
}

// I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition
func (o *I2C_Type) SetSCL_START_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSCL_START_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff
}

// I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA
func (o *I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff
}

// I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition
func (o *I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff
}

// I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL rising edge for a stop condition. Measurement unit: i2c_sclk
func (o *I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value)
}
func (o *I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff
}

// I2C.FILTER_CFG: SCL and SDA filter configuration register
func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value)
}
func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 {
	return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf
}
func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4
}
func (o *I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9
}

// I2C.CLK_CONF: I2C CLK configuration register
func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff
}
func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8)
}
func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8
}
func (o *I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14)
}
func (o *I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14
}
func (o *I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20
}
func (o *I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21
}

// I2C.COMD0: I2C command register 0
func (o *I2C_Type) SetCOMD0_COMMAND0(value uint32) {
	volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD0_COMMAND0() uint32 {
	return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD0_COMMAND0_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD0_COMMAND0_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31
}

// I2C.COMD1: I2C command register 1
func (o *I2C_Type) SetCOMD1_COMMAND1(value uint32) {
	volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD1_COMMAND1() uint32 {
	return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD1_COMMAND1_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD1_COMMAND1_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31
}

// I2C.COMD2: I2C command register 2
func (o *I2C_Type) SetCOMD2_COMMAND2(value uint32) {
	volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD2_COMMAND2() uint32 {
	return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD2_COMMAND2_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD2_COMMAND2_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31
}

// I2C.COMD3: I2C command register 3
func (o *I2C_Type) SetCOMD3_COMMAND3(value uint32) {
	volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD3_COMMAND3() uint32 {
	return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD3_COMMAND3_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD3_COMMAND3_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31
}

// I2C.COMD4: I2C command register 4
func (o *I2C_Type) SetCOMD4_COMMAND4(value uint32) {
	volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD4_COMMAND4() uint32 {
	return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD4_COMMAND4_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD4_COMMAND4_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31
}

// I2C.COMD5: I2C command register 5
func (o *I2C_Type) SetCOMD5_COMMAND5(value uint32) {
	volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD5_COMMAND5() uint32 {
	return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD5_COMMAND5_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD5_COMMAND5_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31
}

// I2C.COMD6: I2C command register 6
func (o *I2C_Type) SetCOMD6_COMMAND6(value uint32) {
	volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD6_COMMAND6() uint32 {
	return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD6_COMMAND6_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD6_COMMAND6_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31
}

// I2C.COMD7: I2C command register 7
func (o *I2C_Type) SetCOMD7_COMMAND7(value uint32) {
	volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value)
}
func (o *I2C_Type) GetCOMD7_COMMAND7() uint32 {
	return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff
}
func (o *I2C_Type) SetCOMD7_COMMAND7_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCOMD7_COMMAND7_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31
}

// I2C.SCL_ST_TIME_OUT: SCL status time out register
func (o *I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) {
	volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value)
}
func (o *I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 {
	return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f
}

// I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register
func (o *I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) {
	volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value)
}
func (o *I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 {
	return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f
}

// I2C.SCL_SP_CONF: Power configuration register
func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 {
	return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1
}
func (o *I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1)
}
func (o *I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 {
	return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1
}
func (o *I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7
}

// I2C.SCL_STRETCH_CONF: Set SCL stretch of I2C slave
func (o *I2C_Type) SetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM(value uint32) {
	volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetSCL_STRETCH_CONF_STRETCH_PROTECT_NUM() uint32 {
	return volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x3ff
}
func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN() uint32 {
	return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR(value uint32) {
	volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR() uint32 {
	return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN() uint32 {
	return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL(value uint32) {
	volatile.StoreUint32(&o.SCL_STRETCH_CONF.Reg, volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetSCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL() uint32 {
	return (volatile.LoadUint32(&o.SCL_STRETCH_CONF.Reg) & 0x2000) >> 13
}

// I2C.DATE: Version register
func (o *I2C_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *I2C_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register
func (o *I2C_Type) SetTXFIFO_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value)
}
func (o *I2C_Type) GetTXFIFO_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg)
}

// I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register
func (o *I2C_Type) SetRXFIFO_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value)
}
func (o *I2C_Type) GetRXFIFO_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg)
}

// I2S (Inter-IC Sound) Controller 0
type I2S_Type struct {
	_                [12]byte
	INT_RAW          volatile.Register32 // 0xC
	INT_ST           volatile.Register32 // 0x10
	INT_ENA          volatile.Register32 // 0x14
	INT_CLR          volatile.Register32 // 0x18
	_                [4]byte
	RX_CONF          volatile.Register32 // 0x20
	TX_CONF          volatile.Register32 // 0x24
	RX_CONF1         volatile.Register32 // 0x28
	TX_CONF1         volatile.Register32 // 0x2C
	_                [16]byte
	TX_PCM2PDM_CONF  volatile.Register32 // 0x40
	TX_PCM2PDM_CONF1 volatile.Register32 // 0x44
	RX_PDM2PCM_CONF  volatile.Register32 // 0x48
	_                [4]byte
	RX_TDM_CTRL      volatile.Register32 // 0x50
	TX_TDM_CTRL      volatile.Register32 // 0x54
	RX_TIMING        volatile.Register32 // 0x58
	TX_TIMING        volatile.Register32 // 0x5C
	LC_HUNG_CONF     volatile.Register32 // 0x60
	RXEOF_NUM        volatile.Register32 // 0x64
	CONF_SIGLE_DATA  volatile.Register32 // 0x68
	STATE            volatile.Register32 // 0x6C
	ETM_CONF         volatile.Register32 // 0x70
	FIFO_CNT         volatile.Register32 // 0x74
	BCK_CNT          volatile.Register32 // 0x78
	CLK_GATE         volatile.Register32 // 0x7C
	DATE             volatile.Register32 // 0x80
}

// I2S.INT_RAW: I2S interrupt raw register, valid in level.
func (o *I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *I2S_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}

// I2S.INT_ST: I2S interrupt status register.
func (o *I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *I2S_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetINT_ST_TX_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}

// I2S.INT_ENA: I2S interrupt enable register.
func (o *I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *I2S_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}

// I2S.INT_CLR: I2S interrupt clear register.
func (o *I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *I2S_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}

// I2S.RX_CONF: I2S RX configure register
func (o *I2S_Type) SetRX_CONF_RX_RESET(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetRX_CONF_RX_RESET() uint32 {
	return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1
}
func (o *I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetRX_CONF_RX_START(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetRX_CONF_RX_START() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3
}
func (o *I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x30)|value<<4)
}
func (o *I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x30) >> 4
}
func (o *I2S_Type) SetRX_CONF_RX_MONO(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40)|value<<6)
}
func (o *I2S_Type) GetRX_CONF_RX_MONO() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40) >> 6
}
func (o *I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7)
}
func (o *I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7
}
func (o *I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8)
}
func (o *I2S_Type) GetRX_CONF_RX_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8
}
func (o *I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9)
}
func (o *I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9
}
func (o *I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10)
}
func (o *I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10
}
func (o *I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12
}
func (o *I2S_Type) SetRX_CONF_RX_MSB_SHIFT(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *I2S_Type) GetRX_CONF_RX_MSB_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2000) >> 13
}
func (o *I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15)
}
func (o *I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15
}
func (o *I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16)
}
func (o *I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16
}
func (o *I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17)
}
func (o *I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17
}
func (o *I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18)
}
func (o *I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18
}
func (o *I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19
}
func (o *I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20
}
func (o *I2S_Type) SetRX_CONF_RX_BCK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x7e00000)|value<<21)
}
func (o *I2S_Type) GetRX_CONF_RX_BCK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x7e00000) >> 21
}

// I2S.TX_CONF: I2S TX configure register
func (o *I2S_Type) SetTX_CONF_TX_RESET(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetTX_CONF_TX_RESET() uint32 {
	return volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1
}
func (o *I2S_Type) SetTX_CONF_TX_FIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetTX_CONF_TX_FIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetTX_CONF_TX_START(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetTX_CONF_TX_START() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetTX_CONF_TX_SLAVE_MOD(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetTX_CONF_TX_SLAVE_MOD() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8) >> 3
}
func (o *I2S_Type) SetTX_CONF_TX_STOP_EN(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10)|value<<4)
}
func (o *I2S_Type) GetTX_CONF_TX_STOP_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10) >> 4
}
func (o *I2S_Type) SetTX_CONF_TX_CHAN_EQUAL(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20)|value<<5)
}
func (o *I2S_Type) GetTX_CONF_TX_CHAN_EQUAL() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20) >> 5
}
func (o *I2S_Type) SetTX_CONF_TX_MONO(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40)|value<<6)
}
func (o *I2S_Type) GetTX_CONF_TX_MONO() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40) >> 6
}
func (o *I2S_Type) SetTX_CONF_TX_BIG_ENDIAN(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80)|value<<7)
}
func (o *I2S_Type) GetTX_CONF_TX_BIG_ENDIAN() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80) >> 7
}
func (o *I2S_Type) SetTX_CONF_TX_UPDATE(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100)|value<<8)
}
func (o *I2S_Type) GetTX_CONF_TX_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100) >> 8
}
func (o *I2S_Type) SetTX_CONF_TX_MONO_FST_VLD(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x200)|value<<9)
}
func (o *I2S_Type) GetTX_CONF_TX_MONO_FST_VLD() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x200) >> 9
}
func (o *I2S_Type) SetTX_CONF_TX_PCM_CONF(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0xc00)|value<<10)
}
func (o *I2S_Type) GetTX_CONF_TX_PCM_CONF() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0xc00) >> 10
}
func (o *I2S_Type) SetTX_CONF_TX_PCM_BYPASS(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *I2S_Type) GetTX_CONF_TX_PCM_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x1000) >> 12
}
func (o *I2S_Type) SetTX_CONF_TX_MSB_SHIFT(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *I2S_Type) GetTX_CONF_TX_MSB_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x2000) >> 13
}
func (o *I2S_Type) SetTX_CONF_TX_BCK_NO_DLY(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x4000)|value<<14)
}
func (o *I2S_Type) GetTX_CONF_TX_BCK_NO_DLY() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x4000) >> 14
}
func (o *I2S_Type) SetTX_CONF_TX_LEFT_ALIGN(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x8000)|value<<15)
}
func (o *I2S_Type) GetTX_CONF_TX_LEFT_ALIGN() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x8000) >> 15
}
func (o *I2S_Type) SetTX_CONF_TX_24_FILL_EN(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x10000)|value<<16)
}
func (o *I2S_Type) GetTX_CONF_TX_24_FILL_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x10000) >> 16
}
func (o *I2S_Type) SetTX_CONF_TX_WS_IDLE_POL(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x20000)|value<<17)
}
func (o *I2S_Type) GetTX_CONF_TX_WS_IDLE_POL() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x20000) >> 17
}
func (o *I2S_Type) SetTX_CONF_TX_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000)|value<<18)
}
func (o *I2S_Type) GetTX_CONF_TX_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000) >> 18
}
func (o *I2S_Type) SetTX_CONF_TX_TDM_EN(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *I2S_Type) GetTX_CONF_TX_TDM_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x80000) >> 19
}
func (o *I2S_Type) SetTX_CONF_TX_PDM_EN(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *I2S_Type) GetTX_CONF_TX_PDM_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x100000) >> 20
}
func (o *I2S_Type) SetTX_CONF_TX_BCK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x7e00000)|value<<21)
}
func (o *I2S_Type) GetTX_CONF_TX_BCK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x7e00000) >> 21
}
func (o *I2S_Type) SetTX_CONF_TX_CHAN_MOD(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x38000000)|value<<27)
}
func (o *I2S_Type) GetTX_CONF_TX_CHAN_MOD() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x38000000) >> 27
}
func (o *I2S_Type) SetTX_CONF_SIG_LOOPBACK(value uint32) {
	volatile.StoreUint32(&o.TX_CONF.Reg, volatile.LoadUint32(&o.TX_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *I2S_Type) GetTX_CONF_SIG_LOOPBACK() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF.Reg) & 0x40000000) >> 30
}

// I2S.RX_CONF1: I2S RX configure register 1
func (o *I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1ff)|value)
}
func (o *I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 {
	return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1ff
}
func (o *I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7c000)|value<<14)
}
func (o *I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7c000) >> 14
}
func (o *I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f80000)|value<<19)
}
func (o *I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f80000) >> 19
}
func (o *I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xf8000000)|value<<27)
}
func (o *I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xf8000000) >> 27
}

// I2S.TX_CONF1: I2S TX configure register 1
func (o *I2S_Type) SetTX_CONF1_TX_TDM_WS_WIDTH(value uint32) {
	volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x1ff)|value)
}
func (o *I2S_Type) GetTX_CONF1_TX_TDM_WS_WIDTH() uint32 {
	return volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x1ff
}
func (o *I2S_Type) SetTX_CONF1_TX_BITS_MOD(value uint32) {
	volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7c000)|value<<14)
}
func (o *I2S_Type) GetTX_CONF1_TX_BITS_MOD() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7c000) >> 14
}
func (o *I2S_Type) SetTX_CONF1_TX_HALF_SAMPLE_BITS(value uint32) {
	volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0x7f80000)|value<<19)
}
func (o *I2S_Type) GetTX_CONF1_TX_HALF_SAMPLE_BITS() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0x7f80000) >> 19
}
func (o *I2S_Type) SetTX_CONF1_TX_TDM_CHAN_BITS(value uint32) {
	volatile.StoreUint32(&o.TX_CONF1.Reg, volatile.LoadUint32(&o.TX_CONF1.Reg)&^(0xf8000000)|value<<27)
}
func (o *I2S_Type) GetTX_CONF1_TX_TDM_CHAN_BITS() uint32 {
	return (volatile.LoadUint32(&o.TX_CONF1.Reg) & 0xf8000000) >> 27
}

// I2S.TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_BYPASS() uint32 {
	return volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1e)|value<<1)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_OSR2() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1e) >> 1
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1fe0)|value<<5)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1fe0) >> 5
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x6000)|value<<13)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x6000) >> 13
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x18000)|value<<15)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x18000) >> 15
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x60000)|value<<17)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x60000) >> 17
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x180000)|value<<19)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x180000) >> 19
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x200000) >> 21
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x400000)|value<<22)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x400000) >> 22
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x800000)|value<<23)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x800000) >> 23
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x1000000) >> 24
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF_PCM2PDM_CONV_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF.Reg) & 0x2000000) >> 25
}

// I2S.TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register
func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FP(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3ff)|value)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FP() uint32 {
	return volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3ff
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_PDM_FS(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0xffc00)|value<<10)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_PDM_FS() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0xffc00) >> 10
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x700000)|value<<20)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x700000) >> 20
}
func (o *I2S_Type) SetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0(value uint32) {
	volatile.StoreUint32(&o.TX_PCM2PDM_CONF1.Reg, volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg)&^(0x3800000)|value<<23)
}
func (o *I2S_Type) GetTX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0() uint32 {
	return (volatile.LoadUint32(&o.TX_PCM2PDM_CONF1.Reg) & 0x3800000) >> 23
}

// I2S.RX_PDM2PCM_CONF: I2S RX configure register
func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM2PCM_EN(value uint32) {
	volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM2PCM_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x80000) >> 19
}
func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM_SINC_DSR_16_EN(value uint32) {
	volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM_SINC_DSR_16_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x100000) >> 20
}
func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM2PCM_AMPLIFY_NUM(value uint32) {
	volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x1e00000)|value<<21)
}
func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM2PCM_AMPLIFY_NUM() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x1e00000) >> 21
}
func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_PDM_HP_BYPASS(value uint32) {
	volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_PDM_HP_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x2000000) >> 25
}
func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_5(value uint32) {
	volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0x1c000000)|value<<26)
}
func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_5() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0x1c000000) >> 26
}
func (o *I2S_Type) SetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_0(value uint32) {
	volatile.StoreUint32(&o.RX_PDM2PCM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg)&^(0xe0000000)|value<<29)
}
func (o *I2S_Type) GetRX_PDM2PCM_CONF_RX_IIR_HP_MULT12_0() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM2PCM_CONF.Reg) & 0xe0000000) >> 29
}

// I2S.RX_TDM_CTRL: I2S TX TDM mode control register
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 {
	return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8) >> 3
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x10) >> 4
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x20) >> 5
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x40) >> 6
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x80) >> 7
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN8_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN8_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x100) >> 8
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN9_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN9_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x200) >> 9
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN10_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN10_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x400) >> 10
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN11_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN11_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x800) >> 11
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN12_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN12_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1000) >> 12
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN13_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN13_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2000) >> 13
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN14_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN14_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x4000) >> 14
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_CHAN15_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_CHAN15_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x8000) >> 15
}
func (o *I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16)
}
func (o *I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16
}

// I2S.TX_TDM_CTRL: I2S TX TDM mode control register
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN0_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN0_EN() uint32 {
	return volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN1_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN1_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2) >> 1
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN2_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN2_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4) >> 2
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN3_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN3_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8) >> 3
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN4_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN4_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x10) >> 4
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN5_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN5_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x20) >> 5
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN6_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN6_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x40) >> 6
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN7_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN7_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x80) >> 7
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN8_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN8_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100) >> 8
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN9_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN9_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x200) >> 9
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN10_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN10_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x400) >> 10
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN11_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN11_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x800) >> 11
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN12_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN12_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x1000) >> 12
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN13_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN13_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x2000) >> 13
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN14_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN14_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x4000) >> 14
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_CHAN15_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_CHAN15_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x8000) >> 15
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0xf0000)|value<<16)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0xf0000) >> 16
}
func (o *I2S_Type) SetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN(value uint32) {
	volatile.StoreUint32(&o.TX_TDM_CTRL.Reg, volatile.LoadUint32(&o.TX_TDM_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *I2S_Type) GetTX_TDM_CTRL_TX_TDM_SKIP_MSK_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_TDM_CTRL.Reg) & 0x100000) >> 20
}

// I2S.RX_TIMING: I2S RX timing control register
func (o *I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value)
}
func (o *I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 {
	return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3
}
func (o *I2S_Type) SetRX_TIMING_RX_SD1_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30)|value<<4)
}
func (o *I2S_Type) GetRX_TIMING_RX_SD1_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30) >> 4
}
func (o *I2S_Type) SetRX_TIMING_RX_SD2_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300)|value<<8)
}
func (o *I2S_Type) GetRX_TIMING_RX_SD2_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300) >> 8
}
func (o *I2S_Type) SetRX_TIMING_RX_SD3_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000)|value<<12)
}
func (o *I2S_Type) GetRX_TIMING_RX_SD3_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000) >> 12
}
func (o *I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16)
}
func (o *I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16
}
func (o *I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20)
}
func (o *I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20
}
func (o *I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24)
}
func (o *I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24
}
func (o *I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28)
}
func (o *I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28
}

// I2S.TX_TIMING: I2S TX timing control register
func (o *I2S_Type) SetTX_TIMING_TX_SD_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3)|value)
}
func (o *I2S_Type) GetTX_TIMING_TX_SD_OUT_DM() uint32 {
	return volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3
}
func (o *I2S_Type) SetTX_TIMING_TX_SD1_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30)|value<<4)
}
func (o *I2S_Type) GetTX_TIMING_TX_SD1_OUT_DM() uint32 {
	return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30) >> 4
}
func (o *I2S_Type) SetTX_TIMING_TX_WS_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000)|value<<16)
}
func (o *I2S_Type) GetTX_TIMING_TX_WS_OUT_DM() uint32 {
	return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000) >> 16
}
func (o *I2S_Type) SetTX_TIMING_TX_BCK_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x300000)|value<<20)
}
func (o *I2S_Type) GetTX_TIMING_TX_BCK_OUT_DM() uint32 {
	return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x300000) >> 20
}
func (o *I2S_Type) SetTX_TIMING_TX_WS_IN_DM(value uint32) {
	volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x3000000)|value<<24)
}
func (o *I2S_Type) GetTX_TIMING_TX_WS_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x3000000) >> 24
}
func (o *I2S_Type) SetTX_TIMING_TX_BCK_IN_DM(value uint32) {
	volatile.StoreUint32(&o.TX_TIMING.Reg, volatile.LoadUint32(&o.TX_TIMING.Reg)&^(0x30000000)|value<<28)
}
func (o *I2S_Type) GetTX_TIMING_TX_BCK_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.TX_TIMING.Reg) & 0x30000000) >> 28
}

// I2S.LC_HUNG_CONF: I2S HUNG configure register.
func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value)
}
func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 {
	return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff
}
func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) {
	volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8)
}
func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8
}
func (o *I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) {
	volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11)
}
func (o *I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11
}

// I2S.RXEOF_NUM: I2S RX data number control register.
func (o *I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) {
	volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value)
}
func (o *I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 {
	return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff
}

// I2S.CONF_SIGLE_DATA: I2S signal data register
func (o *I2S_Type) SetCONF_SIGLE_DATA(value uint32) {
	volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value)
}
func (o *I2S_Type) GetCONF_SIGLE_DATA() uint32 {
	return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg)
}

// I2S.STATE: I2S TX status register
func (o *I2S_Type) SetSTATE_TX_IDLE(value uint32) {
	volatile.StoreUint32(&o.STATE.Reg, volatile.LoadUint32(&o.STATE.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetSTATE_TX_IDLE() uint32 {
	return volatile.LoadUint32(&o.STATE.Reg) & 0x1
}

// I2S.ETM_CONF: I2S ETM configure register
func (o *I2S_Type) SetETM_CONF_ETM_TX_SEND_WORD_NUM(value uint32) {
	volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0x3ff)|value)
}
func (o *I2S_Type) GetETM_CONF_ETM_TX_SEND_WORD_NUM() uint32 {
	return volatile.LoadUint32(&o.ETM_CONF.Reg) & 0x3ff
}
func (o *I2S_Type) SetETM_CONF_ETM_RX_RECEIVE_WORD_NUM(value uint32) {
	volatile.StoreUint32(&o.ETM_CONF.Reg, volatile.LoadUint32(&o.ETM_CONF.Reg)&^(0xffc00)|value<<10)
}
func (o *I2S_Type) GetETM_CONF_ETM_RX_RECEIVE_WORD_NUM() uint32 {
	return (volatile.LoadUint32(&o.ETM_CONF.Reg) & 0xffc00) >> 10
}

// I2S.FIFO_CNT: I2S sync counter register
func (o *I2S_Type) SetFIFO_CNT_TX_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.FIFO_CNT.Reg, volatile.LoadUint32(&o.FIFO_CNT.Reg)&^(0x7fffffff)|value)
}
func (o *I2S_Type) GetFIFO_CNT_TX_FIFO_CNT() uint32 {
	return volatile.LoadUint32(&o.FIFO_CNT.Reg) & 0x7fffffff
}
func (o *I2S_Type) SetFIFO_CNT_TX_FIFO_CNT_RST(value uint32) {
	volatile.StoreUint32(&o.FIFO_CNT.Reg, volatile.LoadUint32(&o.FIFO_CNT.Reg)&^(0x80000000)|value<<31)
}
func (o *I2S_Type) GetFIFO_CNT_TX_FIFO_CNT_RST() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CNT.Reg) & 0x80000000) >> 31
}

// I2S.BCK_CNT: I2S sync counter register
func (o *I2S_Type) SetBCK_CNT_TX_BCK_CNT(value uint32) {
	volatile.StoreUint32(&o.BCK_CNT.Reg, volatile.LoadUint32(&o.BCK_CNT.Reg)&^(0x7fffffff)|value)
}
func (o *I2S_Type) GetBCK_CNT_TX_BCK_CNT() uint32 {
	return volatile.LoadUint32(&o.BCK_CNT.Reg) & 0x7fffffff
}
func (o *I2S_Type) SetBCK_CNT_TX_BCK_CNT_RST(value uint32) {
	volatile.StoreUint32(&o.BCK_CNT.Reg, volatile.LoadUint32(&o.BCK_CNT.Reg)&^(0x80000000)|value<<31)
}
func (o *I2S_Type) GetBCK_CNT_TX_BCK_CNT_RST() uint32 {
	return (volatile.LoadUint32(&o.BCK_CNT.Reg) & 0x80000000) >> 31
}

// I2S.CLK_GATE: Clock gate register
func (o *I2S_Type) SetCLK_GATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value)
}
func (o *I2S_Type) GetCLK_GATE_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1
}

// I2S.DATE: Version control register
func (o *I2S_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *I2S_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// I3C Controller (Master)
type I3C_MST_Type struct {
	DEVICE_CTRL              volatile.Register32 // 0x0
	_                        [24]byte
	BUFFER_THLD_CTRL         volatile.Register32 // 0x1C
	DATA_BUFFER_THLD_CTRL    volatile.Register32 // 0x20
	IBI_NOTIFY_CTRL          volatile.Register32 // 0x24
	IBI_SIR_REQ_PAYLOAD      volatile.Register32 // 0x28
	IBI_SIR_REQ_REJECT       volatile.Register32 // 0x2C
	INT_CLR                  volatile.Register32 // 0x30
	INT_RAW                  volatile.Register32 // 0x34
	INT_ST                   volatile.Register32 // 0x38
	INT_ST_ENA               volatile.Register32 // 0x3C
	_                        [4]byte
	RESET_CTRL               volatile.Register32 // 0x44
	BUFFER_STATUS_LEVEL      volatile.Register32 // 0x48
	DATA_BUFFER_STATUS_LEVEL volatile.Register32 // 0x4C
	PRESENT_STATE0           volatile.Register32 // 0x50
	PRESENT_STATE1           volatile.Register32 // 0x54
	DEVICE_TABLE             volatile.Register32 // 0x58
	TIME_OUT_VALUE           volatile.Register32 // 0x5C
	SCL_I3C_MST_OD_TIME      volatile.Register32 // 0x60
	SCL_I3C_MST_PP_TIME      volatile.Register32 // 0x64
	SCL_I2C_FM_TIME          volatile.Register32 // 0x68
	SCL_I2C_FMP_TIME         volatile.Register32 // 0x6C
	SCL_EXT_LOW_TIME         volatile.Register32 // 0x70
	SDA_SAMPLE_TIME          volatile.Register32 // 0x74
	SDA_HOLD_TIME            volatile.Register32 // 0x78
	SCL_START_HOLD           volatile.Register32 // 0x7C
	SCL_RSTART_SETUP         volatile.Register32 // 0x80
	SCL_STOP_HOLD            volatile.Register32 // 0x84
	SCL_STOP_SETUP           volatile.Register32 // 0x88
	_                        [4]byte
	BUS_FREE_TIME            volatile.Register32 // 0x90
	SCL_TERMN_T_EXT_LOW_TIME volatile.Register32 // 0x94
	_                        [8]byte
	VER_ID                   volatile.Register32 // 0xA0
	VER_TYPE                 volatile.Register32 // 0xA4
	_                        [4]byte
	FPGA_DEBUG_PROBE         volatile.Register32 // 0xAC
	RND_ECO_CS               volatile.Register32 // 0xB0
	RND_ECO_LOW              volatile.Register32 // 0xB4
	RND_ECO_HIGH             volatile.Register32 // 0xB8
}

// I3C_MST.DEVICE_CTRL: DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities.
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_BA_INCLUDE(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_BA_INCLUDE() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x2) >> 1
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_TRANS_START(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_TRANS_START() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x4) >> 2
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x8) >> 3
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_IBI_RSTART_TRANS_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_IBI_RSTART_TRANS_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x10) >> 4
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_AUTO_DIS_IBI_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_AUTO_DIS_IBI_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x20) >> 5
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_DMA_RX_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_DMA_RX_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x40) >> 6
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_DMA_TX_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_DMA_TX_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x80) >> 7
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_MULTI_SLV_SINGLE_CCC_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_MULTI_SLV_SINGLE_CCC_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x100) >> 8
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_RX_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_RX_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x200) >> 9
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_RX_BYTE_ORDER(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_RX_BYTE_ORDER() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x400) >> 10
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SCL_PULLUP_FORCE_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SCL_PULLUP_FORCE_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x800) >> 11
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SCL_OE_FORCE_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SCL_OE_FORCE_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x1000) >> 12
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SDA_PP_RD_PULLUP_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SDA_PP_RD_PULLUP_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x2000) >> 13
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SDA_RD_TBIT_HLVL_PULLUP_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SDA_RD_TBIT_HLVL_PULLUP_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x4000) >> 14
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_SDA_PP_WR_PULLUP_EN(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_SDA_PP_WR_PULLUP_EN() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x8000) >> 15
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_DATA_BYTE_CNT_UNLATCH(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_DATA_BYTE_CNT_UNLATCH() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x10000) >> 16
}
func (o *I3C_MST_Type) SetDEVICE_CTRL_REG_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.DEVICE_CTRL.Reg, volatile.LoadUint32(&o.DEVICE_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *I3C_MST_Type) GetDEVICE_CTRL_REG_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_CTRL.Reg) & 0x20000) >> 17
}

// I3C_MST.BUFFER_THLD_CTRL: In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_CMD_BUF_EMPTY_THLD(value uint32) {
	volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0xf)|value)
}
func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_CMD_BUF_EMPTY_THLD() uint32 {
	return volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0xf
}
func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_RESP_BUF_THLD(value uint32) {
	volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0x1c0)|value<<6)
}
func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_RESP_BUF_THLD() uint32 {
	return (volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0x1c0) >> 6
}
func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_IBI_DATA_BUF_THLD(value uint32) {
	volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0x7000)|value<<12)
}
func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_IBI_DATA_BUF_THLD() uint32 {
	return (volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0x7000) >> 12
}
func (o *I3C_MST_Type) SetBUFFER_THLD_CTRL_REG_IBI_STATUS_BUF_THLD(value uint32) {
	volatile.StoreUint32(&o.BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg)&^(0x1c0000)|value<<18)
}
func (o *I3C_MST_Type) GetBUFFER_THLD_CTRL_REG_IBI_STATUS_BUF_THLD() uint32 {
	return (volatile.LoadUint32(&o.BUFFER_THLD_CTRL.Reg) & 0x1c0000) >> 18
}

// I3C_MST.DATA_BUFFER_THLD_CTRL: NA
func (o *I3C_MST_Type) SetDATA_BUFFER_THLD_CTRL_REG_TX_DATA_BUF_THLD(value uint32) {
	volatile.StoreUint32(&o.DATA_BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg)&^(0x7)|value)
}
func (o *I3C_MST_Type) GetDATA_BUFFER_THLD_CTRL_REG_TX_DATA_BUF_THLD() uint32 {
	return volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg) & 0x7
}
func (o *I3C_MST_Type) SetDATA_BUFFER_THLD_CTRL_REG_RX_DATA_BUF_THLD(value uint32) {
	volatile.StoreUint32(&o.DATA_BUFFER_THLD_CTRL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg)&^(0x38)|value<<3)
}
func (o *I3C_MST_Type) GetDATA_BUFFER_THLD_CTRL_REG_RX_DATA_BUF_THLD() uint32 {
	return (volatile.LoadUint32(&o.DATA_BUFFER_THLD_CTRL.Reg) & 0x38) >> 3
}

// I3C_MST.IBI_NOTIFY_CTRL: NA
func (o *I3C_MST_Type) SetIBI_NOTIFY_CTRL_REG_NOTIFY_SIR_REJECTED(value uint32) {
	volatile.StoreUint32(&o.IBI_NOTIFY_CTRL.Reg, volatile.LoadUint32(&o.IBI_NOTIFY_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetIBI_NOTIFY_CTRL_REG_NOTIFY_SIR_REJECTED() uint32 {
	return (volatile.LoadUint32(&o.IBI_NOTIFY_CTRL.Reg) & 0x4) >> 2
}

// I3C_MST.IBI_SIR_REQ_PAYLOAD: NA
func (o *I3C_MST_Type) SetIBI_SIR_REQ_PAYLOAD(value uint32) {
	volatile.StoreUint32(&o.IBI_SIR_REQ_PAYLOAD.Reg, value)
}
func (o *I3C_MST_Type) GetIBI_SIR_REQ_PAYLOAD() uint32 {
	return volatile.LoadUint32(&o.IBI_SIR_REQ_PAYLOAD.Reg)
}

// I3C_MST.IBI_SIR_REQ_REJECT: NA
func (o *I3C_MST_Type) SetIBI_SIR_REQ_REJECT(value uint32) {
	volatile.StoreUint32(&o.IBI_SIR_REQ_REJECT.Reg, value)
}
func (o *I3C_MST_Type) GetIBI_SIR_REQ_REJECT() uint32 {
	return volatile.LoadUint32(&o.IBI_SIR_REQ_REJECT.Reg)
}

// I3C_MST.INT_CLR: NA
func (o *I3C_MST_Type) SetINT_CLR_TX_DATA_BUF_THLD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *I3C_MST_Type) GetINT_CLR_TX_DATA_BUF_THLD_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *I3C_MST_Type) SetINT_CLR_RX_DATA_BUF_THLD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetINT_CLR_RX_DATA_BUF_THLD_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *I3C_MST_Type) SetINT_CLR_IBI_STATUS_THLD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetINT_CLR_IBI_STATUS_THLD_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *I3C_MST_Type) SetINT_CLR_CMD_BUF_EMPTY_THLD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *I3C_MST_Type) GetINT_CLR_CMD_BUF_EMPTY_THLD_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *I3C_MST_Type) SetINT_CLR_RESP_READY_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *I3C_MST_Type) GetINT_CLR_RESP_READY_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *I3C_MST_Type) SetINT_CLR_NXT_CMD_REQ_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *I3C_MST_Type) GetINT_CLR_NXT_CMD_REQ_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *I3C_MST_Type) SetINT_CLR_TRANSFER_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *I3C_MST_Type) GetINT_CLR_TRANSFER_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *I3C_MST_Type) SetINT_CLR_TRANSFER_COMPLETE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *I3C_MST_Type) GetINT_CLR_TRANSFER_COMPLETE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *I3C_MST_Type) SetINT_CLR_COMMAND_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *I3C_MST_Type) GetINT_CLR_COMMAND_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *I3C_MST_Type) SetINT_CLR_DETECT_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *I3C_MST_Type) GetINT_CLR_DETECT_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *I3C_MST_Type) SetINT_CLR_RESP_BUF_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *I3C_MST_Type) GetINT_CLR_RESP_BUF_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *I3C_MST_Type) SetINT_CLR_IBI_DATA_BUF_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *I3C_MST_Type) GetINT_CLR_IBI_DATA_BUF_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *I3C_MST_Type) SetINT_CLR_IBI_STATUS_BUF_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_MST_Type) GetINT_CLR_IBI_STATUS_BUF_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *I3C_MST_Type) SetINT_CLR_IBI_HANDLE_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_MST_Type) GetINT_CLR_IBI_HANDLE_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *I3C_MST_Type) SetINT_CLR_IBI_DETECT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_MST_Type) GetINT_CLR_IBI_DETECT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *I3C_MST_Type) SetINT_CLR_CMD_CCC_MISMATCH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_MST_Type) GetINT_CLR_CMD_CCC_MISMATCH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}

// I3C_MST.INT_RAW: NA
func (o *I3C_MST_Type) SetINT_RAW_TX_DATA_BUF_THLD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *I3C_MST_Type) GetINT_RAW_TX_DATA_BUF_THLD_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *I3C_MST_Type) SetINT_RAW_RX_DATA_BUF_THLD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetINT_RAW_RX_DATA_BUF_THLD_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *I3C_MST_Type) SetINT_RAW_IBI_STATUS_THLD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetINT_RAW_IBI_STATUS_THLD_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *I3C_MST_Type) SetINT_RAW_CMD_BUF_EMPTY_THLD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *I3C_MST_Type) GetINT_RAW_CMD_BUF_EMPTY_THLD_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *I3C_MST_Type) SetINT_RAW_RESP_READY_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *I3C_MST_Type) GetINT_RAW_RESP_READY_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *I3C_MST_Type) SetINT_RAW_NXT_CMD_REQ_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *I3C_MST_Type) GetINT_RAW_NXT_CMD_REQ_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *I3C_MST_Type) SetINT_RAW_TRANSFER_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *I3C_MST_Type) GetINT_RAW_TRANSFER_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *I3C_MST_Type) SetINT_RAW_TRANSFER_COMPLETE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *I3C_MST_Type) GetINT_RAW_TRANSFER_COMPLETE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *I3C_MST_Type) SetINT_RAW_COMMAND_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *I3C_MST_Type) GetINT_RAW_COMMAND_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *I3C_MST_Type) SetINT_RAW_DETECT_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *I3C_MST_Type) GetINT_RAW_DETECT_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *I3C_MST_Type) SetINT_RAW_RESP_BUF_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *I3C_MST_Type) GetINT_RAW_RESP_BUF_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *I3C_MST_Type) SetINT_RAW_IBI_DATA_BUF_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *I3C_MST_Type) GetINT_RAW_IBI_DATA_BUF_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *I3C_MST_Type) SetINT_RAW_IBI_STATUS_BUF_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_MST_Type) GetINT_RAW_IBI_STATUS_BUF_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *I3C_MST_Type) SetINT_RAW_IBI_HANDLE_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_MST_Type) GetINT_RAW_IBI_HANDLE_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *I3C_MST_Type) SetINT_RAW_IBI_DETECT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_MST_Type) GetINT_RAW_IBI_DETECT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *I3C_MST_Type) SetINT_RAW_CMD_CCC_MISMATCH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_MST_Type) GetINT_RAW_CMD_CCC_MISMATCH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}

// I3C_MST.INT_ST: NA
func (o *I3C_MST_Type) SetINT_ST_TX_DATA_BUF_THLD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *I3C_MST_Type) GetINT_ST_TX_DATA_BUF_THLD_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *I3C_MST_Type) SetINT_ST_RX_DATA_BUF_THLD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetINT_ST_RX_DATA_BUF_THLD_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *I3C_MST_Type) SetINT_ST_IBI_STATUS_THLD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetINT_ST_IBI_STATUS_THLD_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *I3C_MST_Type) SetINT_ST_CMD_BUF_EMPTY_THLD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *I3C_MST_Type) GetINT_ST_CMD_BUF_EMPTY_THLD_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *I3C_MST_Type) SetINT_ST_RESP_READY_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *I3C_MST_Type) GetINT_ST_RESP_READY_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *I3C_MST_Type) SetINT_ST_NXT_CMD_REQ_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *I3C_MST_Type) GetINT_ST_NXT_CMD_REQ_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *I3C_MST_Type) SetINT_ST_TRANSFER_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *I3C_MST_Type) GetINT_ST_TRANSFER_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *I3C_MST_Type) SetINT_ST_TRANSFER_COMPLETE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *I3C_MST_Type) GetINT_ST_TRANSFER_COMPLETE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *I3C_MST_Type) SetINT_ST_COMMAND_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *I3C_MST_Type) GetINT_ST_COMMAND_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *I3C_MST_Type) SetINT_ST_DETECT_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *I3C_MST_Type) GetINT_ST_DETECT_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *I3C_MST_Type) SetINT_ST_RESP_BUF_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *I3C_MST_Type) GetINT_ST_RESP_BUF_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *I3C_MST_Type) SetINT_ST_IBI_DATA_BUF_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *I3C_MST_Type) GetINT_ST_IBI_DATA_BUF_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *I3C_MST_Type) SetINT_ST_IBI_STATUS_BUF_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_MST_Type) GetINT_ST_IBI_STATUS_BUF_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *I3C_MST_Type) SetINT_ST_IBI_HANDLE_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_MST_Type) GetINT_ST_IBI_HANDLE_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *I3C_MST_Type) SetINT_ST_IBI_DETECT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_MST_Type) GetINT_ST_IBI_DETECT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *I3C_MST_Type) SetINT_ST_CMD_CCC_MISMATCH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_MST_Type) GetINT_ST_CMD_CCC_MISMATCH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}

// I3C_MST.INT_ST_ENA: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.
func (o *I3C_MST_Type) SetINT_ST_ENA_TX_DATA_BUF_THLD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x1)|value)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_TX_DATA_BUF_THLD_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x1
}
func (o *I3C_MST_Type) SetINT_ST_ENA_RX_DATA_BUF_THLD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_RX_DATA_BUF_THLD_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x2) >> 1
}
func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_STATUS_THLD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_STATUS_THLD_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x4) >> 2
}
func (o *I3C_MST_Type) SetINT_ST_ENA_CMD_BUF_EMPTY_THLD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x8)|value<<3)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_CMD_BUF_EMPTY_THLD_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x8) >> 3
}
func (o *I3C_MST_Type) SetINT_ST_ENA_RESP_READY_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x10)|value<<4)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_RESP_READY_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x10) >> 4
}
func (o *I3C_MST_Type) SetINT_ST_ENA_NXT_CMD_REQ_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x20)|value<<5)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_NXT_CMD_REQ_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x20) >> 5
}
func (o *I3C_MST_Type) SetINT_ST_ENA_TRANSFER_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x40)|value<<6)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_TRANSFER_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x40) >> 6
}
func (o *I3C_MST_Type) SetINT_ST_ENA_TRANSFER_COMPLETE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x80)|value<<7)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_TRANSFER_COMPLETE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x80) >> 7
}
func (o *I3C_MST_Type) SetINT_ST_ENA_COMMAND_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x100)|value<<8)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_COMMAND_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x100) >> 8
}
func (o *I3C_MST_Type) SetINT_ST_ENA_DETECT_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x200)|value<<9)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_DETECT_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x200) >> 9
}
func (o *I3C_MST_Type) SetINT_ST_ENA_RESP_BUF_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x400)|value<<10)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_RESP_BUF_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x400) >> 10
}
func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_DATA_BUF_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x800)|value<<11)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_DATA_BUF_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x800) >> 11
}
func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_STATUS_BUF_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_STATUS_BUF_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x1000) >> 12
}
func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_HANDLE_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_HANDLE_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x2000) >> 13
}
func (o *I3C_MST_Type) SetINT_ST_ENA_IBI_DETECT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_IBI_DETECT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x4000) >> 14
}
func (o *I3C_MST_Type) SetINT_ST_ENA_CMD_CCC_MISMATCH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ST_ENA.Reg, volatile.LoadUint32(&o.INT_ST_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_MST_Type) GetINT_ST_ENA_CMD_CCC_MISMATCH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_ENA.Reg) & 0x8000) >> 15
}

// I3C_MST.RESET_CTRL: NA
func (o *I3C_MST_Type) SetRESET_CTRL_REG_CORE_SOFT_RST(value uint32) {
	volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x1)|value)
}
func (o *I3C_MST_Type) GetRESET_CTRL_REG_CORE_SOFT_RST() uint32 {
	return volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x1
}
func (o *I3C_MST_Type) SetRESET_CTRL_REG_CMD_BUF_RST(value uint32) {
	volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetRESET_CTRL_REG_CMD_BUF_RST() uint32 {
	return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x2) >> 1
}
func (o *I3C_MST_Type) SetRESET_CTRL_REG_RESP_BUF_RST(value uint32) {
	volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetRESET_CTRL_REG_RESP_BUF_RST() uint32 {
	return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x4) >> 2
}
func (o *I3C_MST_Type) SetRESET_CTRL_REG_TX_DATA_BUF_BUF_RST(value uint32) {
	volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *I3C_MST_Type) GetRESET_CTRL_REG_TX_DATA_BUF_BUF_RST() uint32 {
	return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x8) >> 3
}
func (o *I3C_MST_Type) SetRESET_CTRL_REG_RX_DATA_BUF_RST(value uint32) {
	volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *I3C_MST_Type) GetRESET_CTRL_REG_RX_DATA_BUF_RST() uint32 {
	return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x10) >> 4
}
func (o *I3C_MST_Type) SetRESET_CTRL_REG_IBI_DATA_BUF_RST(value uint32) {
	volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *I3C_MST_Type) GetRESET_CTRL_REG_IBI_DATA_BUF_RST() uint32 {
	return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x20) >> 5
}
func (o *I3C_MST_Type) SetRESET_CTRL_REG_IBI_STATUS_BUF_RST(value uint32) {
	volatile.StoreUint32(&o.RESET_CTRL.Reg, volatile.LoadUint32(&o.RESET_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *I3C_MST_Type) GetRESET_CTRL_REG_IBI_STATUS_BUF_RST() uint32 {
	return (volatile.LoadUint32(&o.RESET_CTRL.Reg) & 0x40) >> 6
}

// I3C_MST.BUFFER_STATUS_LEVEL: BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_CMD_BUF_EMPTY_CNT(value uint32) {
	volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0x1f)|value)
}
func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_CMD_BUF_EMPTY_CNT() uint32 {
	return volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0x1f
}
func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_RESP_BUF_CNT(value uint32) {
	volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0xf00)|value<<8)
}
func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_RESP_BUF_CNT() uint32 {
	return (volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0xf00) >> 8
}
func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_IBI_DATA_BUF_CNT(value uint32) {
	volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0xf0000)|value<<16)
}
func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_IBI_DATA_BUF_CNT() uint32 {
	return (volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0xf0000) >> 16
}
func (o *I3C_MST_Type) SetBUFFER_STATUS_LEVEL_IBI_STATUS_BUF_CNT(value uint32) {
	volatile.StoreUint32(&o.BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg)&^(0xf000000)|value<<24)
}
func (o *I3C_MST_Type) GetBUFFER_STATUS_LEVEL_IBI_STATUS_BUF_CNT() uint32 {
	return (volatile.LoadUint32(&o.BUFFER_STATUS_LEVEL.Reg) & 0xf000000) >> 24
}

// I3C_MST.DATA_BUFFER_STATUS_LEVEL: DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
func (o *I3C_MST_Type) SetDATA_BUFFER_STATUS_LEVEL_TX_DATA_BUF_EMPTY_CNT(value uint32) {
	volatile.StoreUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg)&^(0x3f)|value)
}
func (o *I3C_MST_Type) GetDATA_BUFFER_STATUS_LEVEL_TX_DATA_BUF_EMPTY_CNT() uint32 {
	return volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg) & 0x3f
}
func (o *I3C_MST_Type) SetDATA_BUFFER_STATUS_LEVEL_RX_DATA_BUF_CNT(value uint32) {
	volatile.StoreUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg, volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg)&^(0x3f0000)|value<<16)
}
func (o *I3C_MST_Type) GetDATA_BUFFER_STATUS_LEVEL_RX_DATA_BUF_CNT() uint32 {
	return (volatile.LoadUint32(&o.DATA_BUFFER_STATUS_LEVEL.Reg) & 0x3f0000) >> 16
}

// I3C_MST.PRESENT_STATE0: NA
func (o *I3C_MST_Type) SetPRESENT_STATE0_SDA_LVL(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x1)|value)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_SDA_LVL() uint32 {
	return volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x1
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_SCL_LVL(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_SCL_LVL() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x2) >> 1
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_BUS_BUSY(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x4)|value<<2)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_BUS_BUSY() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x4) >> 2
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_BUS_FREE(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x8)|value<<3)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_BUS_FREE() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x8) >> 3
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_CMD_TID(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x1e00)|value<<9)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_CMD_TID() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x1e00) >> 9
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_SCL_GEN_FSM_STATE(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0xe000)|value<<13)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_SCL_GEN_FSM_STATE() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0xe000) >> 13
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_IBI_EV_HANDLE_FSM_STATE(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x70000)|value<<16)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_IBI_EV_HANDLE_FSM_STATE() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x70000) >> 16
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_I2C_MODE_FSM_STATE(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x380000)|value<<19)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_I2C_MODE_FSM_STATE() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x380000) >> 19
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_SDR_MODE_FSM_STATE(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x3c00000)|value<<22)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_SDR_MODE_FSM_STATE() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x3c00000) >> 22
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_DAA_MODE_FSM_STATE(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0x1c000000)|value<<26)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_DAA_MODE_FSM_STATE() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0x1c000000) >> 26
}
func (o *I3C_MST_Type) SetPRESENT_STATE0_MAIN_FSM_STATE(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE0.Reg, volatile.LoadUint32(&o.PRESENT_STATE0.Reg)&^(0xe0000000)|value<<29)
}
func (o *I3C_MST_Type) GetPRESENT_STATE0_MAIN_FSM_STATE() uint32 {
	return (volatile.LoadUint32(&o.PRESENT_STATE0.Reg) & 0xe0000000) >> 29
}

// I3C_MST.PRESENT_STATE1: NA
func (o *I3C_MST_Type) SetPRESENT_STATE1_DATA_BYTE_CNT(value uint32) {
	volatile.StoreUint32(&o.PRESENT_STATE1.Reg, volatile.LoadUint32(&o.PRESENT_STATE1.Reg)&^(0xffff)|value)
}
func (o *I3C_MST_Type) GetPRESENT_STATE1_DATA_BYTE_CNT() uint32 {
	return volatile.LoadUint32(&o.PRESENT_STATE1.Reg) & 0xffff
}

// I3C_MST.DEVICE_TABLE: Pointer for Device Address Table
func (o *I3C_MST_Type) SetDEVICE_TABLE_REG_DCT_DAA_INIT_INDEX(value uint32) {
	volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf)|value)
}
func (o *I3C_MST_Type) GetDEVICE_TABLE_REG_DCT_DAA_INIT_INDEX() uint32 {
	return volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf
}
func (o *I3C_MST_Type) SetDEVICE_TABLE_REG_DAT_DAA_INIT_INDEX(value uint32) {
	volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf0)|value<<4)
}
func (o *I3C_MST_Type) GetDEVICE_TABLE_REG_DAT_DAA_INIT_INDEX() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf0) >> 4
}
func (o *I3C_MST_Type) SetDEVICE_TABLE_PRESENT_DCT_INDEX(value uint32) {
	volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf00)|value<<8)
}
func (o *I3C_MST_Type) GetDEVICE_TABLE_PRESENT_DCT_INDEX() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf00) >> 8
}
func (o *I3C_MST_Type) SetDEVICE_TABLE_PRESENT_DAT_INDEX(value uint32) {
	volatile.StoreUint32(&o.DEVICE_TABLE.Reg, volatile.LoadUint32(&o.DEVICE_TABLE.Reg)&^(0xf000)|value<<12)
}
func (o *I3C_MST_Type) GetDEVICE_TABLE_PRESENT_DAT_INDEX() uint32 {
	return (volatile.LoadUint32(&o.DEVICE_TABLE.Reg) & 0xf000) >> 12
}

// I3C_MST.TIME_OUT_VALUE: NA
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RESP_BUF_TO_VALUE(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x1f)|value)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RESP_BUF_TO_VALUE() uint32 {
	return volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x1f
}
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RESP_BUF_TO_EN(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x20)|value<<5)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RESP_BUF_TO_EN() uint32 {
	return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x20) >> 5
}
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_VALUE(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x7c0)|value<<6)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_VALUE() uint32 {
	return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x7c0) >> 6
}
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_EN(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x800)|value<<11)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_EN() uint32 {
	return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x800) >> 11
}
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_VALUE(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x1f000)|value<<12)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_VALUE() uint32 {
	return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x1f000) >> 12
}
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_EN(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x20000)|value<<17)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_EN() uint32 {
	return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x20000) >> 17
}
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_VALUE(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x7c0000)|value<<18)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_VALUE() uint32 {
	return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x7c0000) >> 18
}
func (o *I3C_MST_Type) SetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_EN(value uint32) {
	volatile.StoreUint32(&o.TIME_OUT_VALUE.Reg, volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg)&^(0x800000)|value<<23)
}
func (o *I3C_MST_Type) GetTIME_OUT_VALUE_REG_RX_DATA_BUF_TO_EN() uint32 {
	return (volatile.LoadUint32(&o.TIME_OUT_VALUE.Reg) & 0x800000) >> 23
}

// I3C_MST.SCL_I3C_MST_OD_TIME: NA
func (o *I3C_MST_Type) SetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_LOW_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I3C_MST_OD_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg)&^(0xffff)|value)
}
func (o *I3C_MST_Type) GetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_LOW_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg) & 0xffff
}
func (o *I3C_MST_Type) SetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I3C_MST_OD_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg)&^(0xffff0000)|value<<16)
}
func (o *I3C_MST_Type) GetSCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_HIGH_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.SCL_I3C_MST_OD_TIME.Reg) & 0xffff0000) >> 16
}

// I3C_MST.SCL_I3C_MST_PP_TIME: NA
func (o *I3C_MST_Type) SetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_LOW_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I3C_MST_PP_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg)&^(0xff)|value)
}
func (o *I3C_MST_Type) GetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_LOW_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg) & 0xff
}
func (o *I3C_MST_Type) SetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I3C_MST_PP_TIME.Reg, volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_Type) GetSCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_HIGH_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.SCL_I3C_MST_PP_TIME.Reg) & 0xff0000) >> 16
}

// I3C_MST.SCL_I2C_FM_TIME: NA
func (o *I3C_MST_Type) SetSCL_I2C_FM_TIME_REG_I2C_FM_LOW_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I2C_FM_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg)&^(0xffff)|value)
}
func (o *I3C_MST_Type) GetSCL_I2C_FM_TIME_REG_I2C_FM_LOW_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg) & 0xffff
}
func (o *I3C_MST_Type) SetSCL_I2C_FM_TIME_REG_I2C_FM_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I2C_FM_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg)&^(0xffff0000)|value<<16)
}
func (o *I3C_MST_Type) GetSCL_I2C_FM_TIME_REG_I2C_FM_HIGH_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.SCL_I2C_FM_TIME.Reg) & 0xffff0000) >> 16
}

// I3C_MST.SCL_I2C_FMP_TIME: NA
func (o *I3C_MST_Type) SetSCL_I2C_FMP_TIME_REG_I2C_FMP_LOW_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I2C_FMP_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg)&^(0xffff)|value)
}
func (o *I3C_MST_Type) GetSCL_I2C_FMP_TIME_REG_I2C_FMP_LOW_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg) & 0xffff
}
func (o *I3C_MST_Type) SetSCL_I2C_FMP_TIME_REG_I2C_FMP_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_I2C_FMP_TIME.Reg, volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_Type) GetSCL_I2C_FMP_TIME_REG_I2C_FMP_HIGH_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.SCL_I2C_FMP_TIME.Reg) & 0xff0000) >> 16
}

// I3C_MST.SCL_EXT_LOW_TIME: NA
func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD1(value uint32) {
	volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff)|value)
}
func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD1() uint32 {
	return volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff
}
func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD2(value uint32) {
	volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD2() uint32 {
	return (volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff00) >> 8
}
func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD3(value uint32) {
	volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD3() uint32 {
	return (volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_Type) SetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD4(value uint32) {
	volatile.StoreUint32(&o.SCL_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg)&^(0xff000000)|value<<24)
}
func (o *I3C_MST_Type) GetSCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD4() uint32 {
	return (volatile.LoadUint32(&o.SCL_EXT_LOW_TIME.Reg) & 0xff000000) >> 24
}

// I3C_MST.SDA_SAMPLE_TIME: NA
func (o *I3C_MST_Type) SetSDA_SAMPLE_TIME_REG_SDA_OD_SAMPLE_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_SAMPLE_TIME.Reg, volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg)&^(0x1ff)|value)
}
func (o *I3C_MST_Type) GetSDA_SAMPLE_TIME_REG_SDA_OD_SAMPLE_TIME() uint32 {
	return volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg) & 0x1ff
}
func (o *I3C_MST_Type) SetSDA_SAMPLE_TIME_REG_SDA_PP_SAMPLE_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_SAMPLE_TIME.Reg, volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg)&^(0x3e00)|value<<9)
}
func (o *I3C_MST_Type) GetSDA_SAMPLE_TIME_REG_SDA_PP_SAMPLE_TIME() uint32 {
	return (volatile.LoadUint32(&o.SDA_SAMPLE_TIME.Reg) & 0x3e00) >> 9
}

// I3C_MST.SDA_HOLD_TIME: NA
func (o *I3C_MST_Type) SetSDA_HOLD_TIME_REG_SDA_OD_TX_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_HOLD_TIME.Reg, volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg)&^(0x1ff)|value)
}
func (o *I3C_MST_Type) GetSDA_HOLD_TIME_REG_SDA_OD_TX_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg) & 0x1ff
}
func (o *I3C_MST_Type) SetSDA_HOLD_TIME_REG_SDA_PP_TX_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_HOLD_TIME.Reg, volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg)&^(0x3e00)|value<<9)
}
func (o *I3C_MST_Type) GetSDA_HOLD_TIME_REG_SDA_PP_TX_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SDA_HOLD_TIME.Reg) & 0x3e00) >> 9
}

// I3C_MST.SCL_START_HOLD: NA
func (o *I3C_MST_Type) SetSCL_START_HOLD_REG_SCL_START_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value)
}
func (o *I3C_MST_Type) GetSCL_START_HOLD_REG_SCL_START_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff
}
func (o *I3C_MST_Type) SetSCL_START_HOLD_REG_START_DET_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x600)|value<<9)
}
func (o *I3C_MST_Type) GetSCL_START_HOLD_REG_START_DET_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x600) >> 9
}

// I3C_MST.SCL_RSTART_SETUP: NA
func (o *I3C_MST_Type) SetSCL_RSTART_SETUP_REG_SCL_RSTART_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value)
}
func (o *I3C_MST_Type) GetSCL_RSTART_SETUP_REG_SCL_RSTART_SETUP_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff
}

// I3C_MST.SCL_STOP_HOLD: NA
func (o *I3C_MST_Type) SetSCL_STOP_HOLD_REG_SCL_STOP_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value)
}
func (o *I3C_MST_Type) GetSCL_STOP_HOLD_REG_SCL_STOP_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff
}

// I3C_MST.SCL_STOP_SETUP: NA
func (o *I3C_MST_Type) SetSCL_STOP_SETUP_REG_SCL_STOP_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value)
}
func (o *I3C_MST_Type) GetSCL_STOP_SETUP_REG_SCL_STOP_SETUP_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff
}

// I3C_MST.BUS_FREE_TIME: NA
func (o *I3C_MST_Type) SetBUS_FREE_TIME_REG_BUS_FREE_TIME(value uint32) {
	volatile.StoreUint32(&o.BUS_FREE_TIME.Reg, volatile.LoadUint32(&o.BUS_FREE_TIME.Reg)&^(0xffff)|value)
}
func (o *I3C_MST_Type) GetBUS_FREE_TIME_REG_BUS_FREE_TIME() uint32 {
	return volatile.LoadUint32(&o.BUS_FREE_TIME.Reg) & 0xffff
}

// I3C_MST.SCL_TERMN_T_EXT_LOW_TIME: NA
func (o *I3C_MST_Type) SetSCL_TERMN_T_EXT_LOW_TIME_REG_I3C_MST_TERMN_T_EXT_LOW_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_TERMN_T_EXT_LOW_TIME.Reg, volatile.LoadUint32(&o.SCL_TERMN_T_EXT_LOW_TIME.Reg)&^(0xff)|value)
}
func (o *I3C_MST_Type) GetSCL_TERMN_T_EXT_LOW_TIME_REG_I3C_MST_TERMN_T_EXT_LOW_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_TERMN_T_EXT_LOW_TIME.Reg) & 0xff
}

// I3C_MST.VER_ID: NA
func (o *I3C_MST_Type) SetVER_ID(value uint32) {
	volatile.StoreUint32(&o.VER_ID.Reg, value)
}
func (o *I3C_MST_Type) GetVER_ID() uint32 {
	return volatile.LoadUint32(&o.VER_ID.Reg)
}

// I3C_MST.VER_TYPE: NA
func (o *I3C_MST_Type) SetVER_TYPE(value uint32) {
	volatile.StoreUint32(&o.VER_TYPE.Reg, value)
}
func (o *I3C_MST_Type) GetVER_TYPE() uint32 {
	return volatile.LoadUint32(&o.VER_TYPE.Reg)
}

// I3C_MST.FPGA_DEBUG_PROBE: NA
func (o *I3C_MST_Type) SetFPGA_DEBUG_PROBE(value uint32) {
	volatile.StoreUint32(&o.FPGA_DEBUG_PROBE.Reg, value)
}
func (o *I3C_MST_Type) GetFPGA_DEBUG_PROBE() uint32 {
	return volatile.LoadUint32(&o.FPGA_DEBUG_PROBE.Reg)
}

// I3C_MST.RND_ECO_CS: NA
func (o *I3C_MST_Type) SetRND_ECO_CS_REG_RND_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value)
}
func (o *I3C_MST_Type) GetRND_ECO_CS_REG_RND_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1
}
func (o *I3C_MST_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *I3C_MST_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1
}

// I3C_MST.RND_ECO_LOW: NA
func (o *I3C_MST_Type) SetRND_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value)
}
func (o *I3C_MST_Type) GetRND_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_LOW.Reg)
}

// I3C_MST.RND_ECO_HIGH: NA
func (o *I3C_MST_Type) SetRND_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value)
}
func (o *I3C_MST_Type) GetRND_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg)
}

// I3C_MST_MEM Peripheral
type I3C_MST_MEM_Type struct {
	_                     [8]byte
	COMMAND_BUF_PORT      volatile.Register32 // 0x8
	RESPONSE_BUF_PORT     volatile.Register32 // 0xC
	RX_DATA_PORT          volatile.Register32 // 0x10
	TX_DATA_PORT          volatile.Register32 // 0x14
	IBI_STATUS_BUF        volatile.Register32 // 0x18
	_                     [36]byte
	IBI_DATA_BUF          volatile.Register32 // 0x40
	_                     [124]byte
	DEV_ADDR_TABLE1_LOC   volatile.Register32 // 0xC0
	DEV_ADDR_TABLE2_LOC   volatile.Register32 // 0xC4
	DEV_ADDR_TABLE3_LOC   volatile.Register32 // 0xC8
	DEV_ADDR_TABLE4_LOC   volatile.Register32 // 0xCC
	DEV_ADDR_TABLE5_LOC   volatile.Register32 // 0xD0
	DEV_ADDR_TABLE6_LOC   volatile.Register32 // 0xD4
	DEV_ADDR_TABLE7_LOC   volatile.Register32 // 0xD8
	DEV_ADDR_TABLE8_LOC   volatile.Register32 // 0xDC
	DEV_ADDR_TABLE9_LOC   volatile.Register32 // 0xE0
	DEV_ADDR_TABLE10_LOC  volatile.Register32 // 0xE4
	DEV_ADDR_TABLE11_LOC  volatile.Register32 // 0xE8
	DEV_ADDR_TABLE12_LOC  volatile.Register32 // 0xEC
	_                     [16]byte
	DEV_CHAR_TABLE1_LOC1  volatile.Register32 // 0x100
	DEV_CHAR_TABLE1_LOC2  volatile.Register32 // 0x104
	DEV_CHAR_TABLE1_LOC3  volatile.Register32 // 0x108
	DEV_CHAR_TABLE1_LOC4  volatile.Register32 // 0x10C
	DEV_CHAR_TABLE2_LOC1  volatile.Register32 // 0x110
	DEV_CHAR_TABLE2_LOC2  volatile.Register32 // 0x114
	DEV_CHAR_TABLE2_LOC3  volatile.Register32 // 0x118
	DEV_CHAR_TABLE2_LOC4  volatile.Register32 // 0x11C
	DEV_CHAR_TABLE3_LOC1  volatile.Register32 // 0x120
	DEV_CHAR_TABLE3_LOC2  volatile.Register32 // 0x124
	DEV_CHAR_TABLE3_LOC3  volatile.Register32 // 0x128
	DEV_CHAR_TABLE3_LOC4  volatile.Register32 // 0x12C
	DEV_CHAR_TABLE4_LOC1  volatile.Register32 // 0x130
	DEV_CHAR_TABLE4_LOC2  volatile.Register32 // 0x134
	DEV_CHAR_TABLE4_LOC3  volatile.Register32 // 0x138
	DEV_CHAR_TABLE4_LOC4  volatile.Register32 // 0x13C
	DEV_CHAR_TABLE5_LOC1  volatile.Register32 // 0x140
	DEV_CHAR_TABLE5_LOC2  volatile.Register32 // 0x144
	DEV_CHAR_TABLE5_LOC3  volatile.Register32 // 0x148
	DEV_CHAR_TABLE5_LOC4  volatile.Register32 // 0x14C
	DEV_CHAR_TABLE6_LOC1  volatile.Register32 // 0x150
	DEV_CHAR_TABLE6_LOC2  volatile.Register32 // 0x154
	DEV_CHAR_TABLE6_LOC3  volatile.Register32 // 0x158
	DEV_CHAR_TABLE6_LOC4  volatile.Register32 // 0x15C
	DEV_CHAR_TABLE7_LOC1  volatile.Register32 // 0x160
	DEV_CHAR_TABLE7_LOC2  volatile.Register32 // 0x164
	DEV_CHAR_TABLE7_LOC3  volatile.Register32 // 0x168
	DEV_CHAR_TABLE7_LOC4  volatile.Register32 // 0x16C
	DEV_CHAR_TABLE8_LOC1  volatile.Register32 // 0x170
	DEV_CHAR_TABLE8_LOC2  volatile.Register32 // 0x174
	DEV_CHAR_TABLE8_LOC3  volatile.Register32 // 0x178
	DEV_CHAR_TABLE8_LOC4  volatile.Register32 // 0x17C
	DEV_CHAR_TABLE9_LOC1  volatile.Register32 // 0x180
	DEV_CHAR_TABLE9_LOC2  volatile.Register32 // 0x184
	DEV_CHAR_TABLE9_LOC3  volatile.Register32 // 0x188
	DEV_CHAR_TABLE9_LOC4  volatile.Register32 // 0x18C
	DEV_CHAR_TABLE10_LOC1 volatile.Register32 // 0x190
	DEV_CHAR_TABLE10_LOC2 volatile.Register32 // 0x194
	DEV_CHAR_TABLE10_LOC3 volatile.Register32 // 0x198
	DEV_CHAR_TABLE10_LOC4 volatile.Register32 // 0x19C
	DEV_CHAR_TABLE11_LOC1 volatile.Register32 // 0x1A0
	DEV_CHAR_TABLE11_LOC2 volatile.Register32 // 0x1A4
	DEV_CHAR_TABLE11_LOC3 volatile.Register32 // 0x1A8
	DEV_CHAR_TABLE11_LOC4 volatile.Register32 // 0x1AC
	DEV_CHAR_TABLE12_LOC1 volatile.Register32 // 0x1B0
	DEV_CHAR_TABLE12_LOC2 volatile.Register32 // 0x1B4
	DEV_CHAR_TABLE12_LOC3 volatile.Register32 // 0x1B8
	DEV_CHAR_TABLE12_LOC4 volatile.Register32 // 0x1BC
}

// I3C_MST_MEM.COMMAND_BUF_PORT: NA
func (o *I3C_MST_MEM_Type) SetCOMMAND_BUF_PORT(value uint32) {
	volatile.StoreUint32(&o.COMMAND_BUF_PORT.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetCOMMAND_BUF_PORT() uint32 {
	return volatile.LoadUint32(&o.COMMAND_BUF_PORT.Reg)
}

// I3C_MST_MEM.RESPONSE_BUF_PORT: NA
func (o *I3C_MST_MEM_Type) SetRESPONSE_BUF_PORT(value uint32) {
	volatile.StoreUint32(&o.RESPONSE_BUF_PORT.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetRESPONSE_BUF_PORT() uint32 {
	return volatile.LoadUint32(&o.RESPONSE_BUF_PORT.Reg)
}

// I3C_MST_MEM.RX_DATA_PORT: NA
func (o *I3C_MST_MEM_Type) SetRX_DATA_PORT(value uint32) {
	volatile.StoreUint32(&o.RX_DATA_PORT.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetRX_DATA_PORT() uint32 {
	return volatile.LoadUint32(&o.RX_DATA_PORT.Reg)
}

// I3C_MST_MEM.TX_DATA_PORT: NA
func (o *I3C_MST_MEM_Type) SetTX_DATA_PORT(value uint32) {
	volatile.StoreUint32(&o.TX_DATA_PORT.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetTX_DATA_PORT() uint32 {
	return volatile.LoadUint32(&o.TX_DATA_PORT.Reg)
}

// I3C_MST_MEM.IBI_STATUS_BUF: In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
func (o *I3C_MST_MEM_Type) SetIBI_STATUS_BUF_DATA_LENGTH(value uint32) {
	volatile.StoreUint32(&o.IBI_STATUS_BUF.Reg, volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg)&^(0xff)|value)
}
func (o *I3C_MST_MEM_Type) GetIBI_STATUS_BUF_DATA_LENGTH() uint32 {
	return volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg) & 0xff
}
func (o *I3C_MST_MEM_Type) SetIBI_STATUS_BUF_IBI_ID(value uint32) {
	volatile.StoreUint32(&o.IBI_STATUS_BUF.Reg, volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_MST_MEM_Type) GetIBI_STATUS_BUF_IBI_ID() uint32 {
	return (volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg) & 0xff00) >> 8
}
func (o *I3C_MST_MEM_Type) SetIBI_STATUS_BUF_IBI_STS(value uint32) {
	volatile.StoreUint32(&o.IBI_STATUS_BUF.Reg, volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg)&^(0x10000000)|value<<28)
}
func (o *I3C_MST_MEM_Type) GetIBI_STATUS_BUF_IBI_STS() uint32 {
	return (volatile.LoadUint32(&o.IBI_STATUS_BUF.Reg) & 0x10000000) >> 28
}

// I3C_MST_MEM.IBI_DATA_BUF: NA
func (o *I3C_MST_MEM_Type) SetIBI_DATA_BUF(value uint32) {
	volatile.StoreUint32(&o.IBI_DATA_BUF.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetIBI_DATA_BUF() uint32 {
	return volatile.LoadUint32(&o.IBI_DATA_BUF.Reg)
}

// I3C_MST_MEM.DEV_ADDR_TABLE1_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE1_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE1_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE2_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE2_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE2_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE3_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE3_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE3_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE4_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE4_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE4_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE5_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE5_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE5_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE6_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE6_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE6_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE7_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE7_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE7_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE8_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE8_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE8_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE9_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE9_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE9_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE10_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE10_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE10_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE11_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE11_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE11_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_ADDR_TABLE12_LOC: NA
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_STATIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0x7f)|value)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_STATIC_ADDR() uint32 {
	return volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0x7f
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_DYNAMIC_ADDR(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_DYNAMIC_ADDR() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0xff0000) >> 16
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_NACK_RETRY_CNT(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_NACK_RETRY_CNT() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0x60000000) >> 29
}
func (o *I3C_MST_MEM_Type) SetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_I2C(value uint32) {
	volatile.StoreUint32(&o.DEV_ADDR_TABLE12_LOC.Reg, volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_MST_MEM_Type) GetDEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_I2C() uint32 {
	return (volatile.LoadUint32(&o.DEV_ADDR_TABLE12_LOC.Reg) & 0x80000000) >> 31
}

// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE1_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE1_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE1_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE1_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE1_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE2_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE2_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE2_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE2_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE2_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE3_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE3_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE3_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE3_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE3_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE4_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE4_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE4_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE4_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE4_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE5_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE5_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE5_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE5_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE5_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE6_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE6_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE6_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE6_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE6_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE7_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE7_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE7_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE7_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE7_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE8_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE8_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE8_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE8_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE8_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE9_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE9_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE9_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE9_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE9_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE10_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE10_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE10_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE10_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE10_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE11_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE11_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE11_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE11_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE11_LOC4.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC1: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC1(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC1.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC1() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC1.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC2: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC2(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC2.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC2() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC2.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC3: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC3(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC3.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC3() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC3.Reg)
}

// I3C_MST_MEM.DEV_CHAR_TABLE12_LOC4: NA
func (o *I3C_MST_MEM_Type) SetDEV_CHAR_TABLE12_LOC4(value uint32) {
	volatile.StoreUint32(&o.DEV_CHAR_TABLE12_LOC4.Reg, value)
}
func (o *I3C_MST_MEM_Type) GetDEV_CHAR_TABLE12_LOC4() uint32 {
	return volatile.LoadUint32(&o.DEV_CHAR_TABLE12_LOC4.Reg)
}

// I3C Controller (Slave)
type I3C_SLV_Type struct {
	_             [4]byte
	CONFIG        volatile.Register32 // 0x4
	STATUS        volatile.Register32 // 0x8
	CTRL          volatile.Register32 // 0xC
	INTSET        volatile.Register32 // 0x10
	INTCLR        volatile.Register32 // 0x14
	INTMASKED     volatile.Register32 // 0x18
	_             [16]byte
	DATACTRL      volatile.Register32 // 0x2C
	WDATAB        volatile.Register32 // 0x30
	WDATABE       volatile.Register32 // 0x34
	_             [8]byte
	RDARAB        volatile.Register32 // 0x40
	_             [4]byte
	RDATAH        volatile.Register32 // 0x48
	_             [16]byte
	CAPABILITIES2 volatile.Register32 // 0x5C
	CAPABILITIES  volatile.Register32 // 0x60
	_             [8]byte
	IDPARTNO      volatile.Register32 // 0x6C
	IDEXT         volatile.Register32 // 0x70
	VENDORID      volatile.Register32 // 0x74
}

// I3C_SLV.CONFIG: NA
func (o *I3C_SLV_Type) SetCONFIG_SLVENA(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1)|value)
}
func (o *I3C_SLV_Type) GetCONFIG_SLVENA() uint32 {
	return volatile.LoadUint32(&o.CONFIG.Reg) & 0x1
}
func (o *I3C_SLV_Type) SetCONFIG_NACK(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *I3C_SLV_Type) GetCONFIG_NACK() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2) >> 1
}
func (o *I3C_SLV_Type) SetCONFIG_MATCHSS(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4)|value<<2)
}
func (o *I3C_SLV_Type) GetCONFIG_MATCHSS() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4) >> 2
}
func (o *I3C_SLV_Type) SetCONFIG_S0IGNORE(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8)|value<<3)
}
func (o *I3C_SLV_Type) GetCONFIG_S0IGNORE() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8) >> 3
}
func (o *I3C_SLV_Type) SetCONFIG_DDROK(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10)|value<<4)
}
func (o *I3C_SLV_Type) GetCONFIG_DDROK() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10) >> 4
}
func (o *I3C_SLV_Type) SetCONFIG_IDRAND(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x100)|value<<8)
}
func (o *I3C_SLV_Type) GetCONFIG_IDRAND() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x100) >> 8
}
func (o *I3C_SLV_Type) SetCONFIG_OFFLINE(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x200)|value<<9)
}
func (o *I3C_SLV_Type) GetCONFIG_OFFLINE() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x200) >> 9
}
func (o *I3C_SLV_Type) SetCONFIG_BAMATCH(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_SLV_Type) GetCONFIG_BAMATCH() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0xff0000) >> 16
}
func (o *I3C_SLV_Type) SetCONFIG_SADDR(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0xfe000000)|value<<25)
}
func (o *I3C_SLV_Type) GetCONFIG_SADDR() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0xfe000000) >> 25
}

// I3C_SLV.STATUS: NA
func (o *I3C_SLV_Type) SetSTATUS_STNOTSTOP(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value)
}
func (o *I3C_SLV_Type) GetSTATUS_STNOTSTOP() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg) & 0x1
}
func (o *I3C_SLV_Type) SetSTATUS_STMSG(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1)
}
func (o *I3C_SLV_Type) GetSTATUS_STMSG() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1
}
func (o *I3C_SLV_Type) SetSTATUS_STCCCH(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2)
}
func (o *I3C_SLV_Type) GetSTATUS_STCCCH() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2
}
func (o *I3C_SLV_Type) SetSTATUS_STREQRD(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3)
}
func (o *I3C_SLV_Type) GetSTATUS_STREQRD() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3
}
func (o *I3C_SLV_Type) SetSTATUS_STREQWR(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4)
}
func (o *I3C_SLV_Type) GetSTATUS_STREQWR() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4
}
func (o *I3C_SLV_Type) SetSTATUS_STDAA(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5)
}
func (o *I3C_SLV_Type) GetSTATUS_STDAA() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5
}
func (o *I3C_SLV_Type) SetSTATUS_STHDR(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6)
}
func (o *I3C_SLV_Type) GetSTATUS_STHDR() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6
}
func (o *I3C_SLV_Type) SetSTATUS_START(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8)
}
func (o *I3C_SLV_Type) GetSTATUS_START() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8
}
func (o *I3C_SLV_Type) SetSTATUS_MATCHED(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9)
}
func (o *I3C_SLV_Type) GetSTATUS_MATCHED() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9
}
func (o *I3C_SLV_Type) SetSTATUS_STOP(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10)
}
func (o *I3C_SLV_Type) GetSTATUS_STOP() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10
}
func (o *I3C_SLV_Type) SetSTATUS_RXPEND(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x800)|value<<11)
}
func (o *I3C_SLV_Type) GetSTATUS_RXPEND() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x800) >> 11
}
func (o *I3C_SLV_Type) SetSTATUS_TXNOTFULL(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_SLV_Type) GetSTATUS_TXNOTFULL() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1000) >> 12
}
func (o *I3C_SLV_Type) SetSTATUS_DACHG(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_SLV_Type) GetSTATUS_DACHG() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13
}
func (o *I3C_SLV_Type) SetSTATUS_CCC(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_SLV_Type) GetSTATUS_CCC() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14
}
func (o *I3C_SLV_Type) SetSTATUS_ERRWARN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_SLV_Type) GetSTATUS_ERRWARN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15
}
func (o *I3C_SLV_Type) SetSTATUS_HDRMATCH(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *I3C_SLV_Type) GetSTATUS_HDRMATCH() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10000) >> 16
}

// I3C_SLV.CTRL: NA
func (o *I3C_SLV_Type) SetCTRL_SLV_EVENT(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3)|value)
}
func (o *I3C_SLV_Type) GetCTRL_SLV_EVENT() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0x3
}
func (o *I3C_SLV_Type) SetCTRL_EXTDATA(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3)
}
func (o *I3C_SLV_Type) GetCTRL_EXTDATA() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3
}
func (o *I3C_SLV_Type) SetCTRL_MAPIDX(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xf0)|value<<4)
}
func (o *I3C_SLV_Type) GetCTRL_MAPIDX() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0xf0) >> 4
}
func (o *I3C_SLV_Type) SetCTRL_IBIDATA(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_SLV_Type) GetCTRL_IBIDATA() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0xff00) >> 8
}
func (o *I3C_SLV_Type) SetCTRL_PENDINT(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xf0000)|value<<16)
}
func (o *I3C_SLV_Type) GetCTRL_PENDINT() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0xf0000) >> 16
}
func (o *I3C_SLV_Type) SetCTRL_ACTSTATE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x300000)|value<<20)
}
func (o *I3C_SLV_Type) GetCTRL_ACTSTATE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x300000) >> 20
}
func (o *I3C_SLV_Type) SetCTRL_VENDINFO(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xff000000)|value<<24)
}
func (o *I3C_SLV_Type) GetCTRL_VENDINFO() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0xff000000) >> 24
}

// I3C_SLV.INTSET: INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor)
func (o *I3C_SLV_Type) SetINTSET_STOP_ENA(value uint32) {
	volatile.StoreUint32(&o.INTSET.Reg, volatile.LoadUint32(&o.INTSET.Reg)&^(0x400)|value<<10)
}
func (o *I3C_SLV_Type) GetINTSET_STOP_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTSET.Reg) & 0x400) >> 10
}
func (o *I3C_SLV_Type) SetINTSET_RXPEND_ENA(value uint32) {
	volatile.StoreUint32(&o.INTSET.Reg, volatile.LoadUint32(&o.INTSET.Reg)&^(0x800)|value<<11)
}
func (o *I3C_SLV_Type) GetINTSET_RXPEND_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTSET.Reg) & 0x800) >> 11
}
func (o *I3C_SLV_Type) SetINTSET_TXSEND_ENA(value uint32) {
	volatile.StoreUint32(&o.INTSET.Reg, volatile.LoadUint32(&o.INTSET.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_SLV_Type) GetINTSET_TXSEND_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTSET.Reg) & 0x1000) >> 12
}

// I3C_SLV.INTCLR: NA
func (o *I3C_SLV_Type) SetINTCLR_STOP_CLR(value uint32) {
	volatile.StoreUint32(&o.INTCLR.Reg, volatile.LoadUint32(&o.INTCLR.Reg)&^(0x400)|value<<10)
}
func (o *I3C_SLV_Type) GetINTCLR_STOP_CLR() uint32 {
	return (volatile.LoadUint32(&o.INTCLR.Reg) & 0x400) >> 10
}
func (o *I3C_SLV_Type) SetINTCLR_RXPEND_CLR(value uint32) {
	volatile.StoreUint32(&o.INTCLR.Reg, volatile.LoadUint32(&o.INTCLR.Reg)&^(0x800)|value<<11)
}
func (o *I3C_SLV_Type) GetINTCLR_RXPEND_CLR() uint32 {
	return (volatile.LoadUint32(&o.INTCLR.Reg) & 0x800) >> 11
}
func (o *I3C_SLV_Type) SetINTCLR_TXSEND_CLR(value uint32) {
	volatile.StoreUint32(&o.INTCLR.Reg, volatile.LoadUint32(&o.INTCLR.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_SLV_Type) GetINTCLR_TXSEND_CLR() uint32 {
	return (volatile.LoadUint32(&o.INTCLR.Reg) & 0x1000) >> 12
}

// I3C_SLV.INTMASKED: NA
func (o *I3C_SLV_Type) SetINTMASKED_STOP_MASK(value uint32) {
	volatile.StoreUint32(&o.INTMASKED.Reg, volatile.LoadUint32(&o.INTMASKED.Reg)&^(0x400)|value<<10)
}
func (o *I3C_SLV_Type) GetINTMASKED_STOP_MASK() uint32 {
	return (volatile.LoadUint32(&o.INTMASKED.Reg) & 0x400) >> 10
}
func (o *I3C_SLV_Type) SetINTMASKED_RXPEND_MASK(value uint32) {
	volatile.StoreUint32(&o.INTMASKED.Reg, volatile.LoadUint32(&o.INTMASKED.Reg)&^(0x800)|value<<11)
}
func (o *I3C_SLV_Type) GetINTMASKED_RXPEND_MASK() uint32 {
	return (volatile.LoadUint32(&o.INTMASKED.Reg) & 0x800) >> 11
}
func (o *I3C_SLV_Type) SetINTMASKED_TXSEND_MASK(value uint32) {
	volatile.StoreUint32(&o.INTMASKED.Reg, volatile.LoadUint32(&o.INTMASKED.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_SLV_Type) GetINTMASKED_TXSEND_MASK() uint32 {
	return (volatile.LoadUint32(&o.INTMASKED.Reg) & 0x1000) >> 12
}

// I3C_SLV.DATACTRL: NA
func (o *I3C_SLV_Type) SetDATACTRL_FLUSHTB(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x1)|value)
}
func (o *I3C_SLV_Type) GetDATACTRL_FLUSHTB() uint32 {
	return volatile.LoadUint32(&o.DATACTRL.Reg) & 0x1
}
func (o *I3C_SLV_Type) SetDATACTRL_FLUSHFB(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_SLV_Type) GetDATACTRL_FLUSHFB() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x2) >> 1
}
func (o *I3C_SLV_Type) SetDATACTRL_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x8)|value<<3)
}
func (o *I3C_SLV_Type) GetDATACTRL_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x8) >> 3
}
func (o *I3C_SLV_Type) SetDATACTRL_TXTRIG(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x30)|value<<4)
}
func (o *I3C_SLV_Type) GetDATACTRL_TXTRIG() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x30) >> 4
}
func (o *I3C_SLV_Type) SetDATACTRL_RXTRIG(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0xc0)|value<<6)
}
func (o *I3C_SLV_Type) GetDATACTRL_RXTRIG() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0xc0) >> 6
}
func (o *I3C_SLV_Type) SetDATACTRL_TXCOUNT(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x1f0000)|value<<16)
}
func (o *I3C_SLV_Type) GetDATACTRL_TXCOUNT() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x1f0000) >> 16
}
func (o *I3C_SLV_Type) SetDATACTRL_RXCOUNT(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x1f000000)|value<<24)
}
func (o *I3C_SLV_Type) GetDATACTRL_RXCOUNT() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x1f000000) >> 24
}
func (o *I3C_SLV_Type) SetDATACTRL_TXFULL(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *I3C_SLV_Type) GetDATACTRL_TXFULL() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x40000000) >> 30
}
func (o *I3C_SLV_Type) SetDATACTRL_RXEMPTY(value uint32) {
	volatile.StoreUint32(&o.DATACTRL.Reg, volatile.LoadUint32(&o.DATACTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_SLV_Type) GetDATACTRL_RXEMPTY() uint32 {
	return (volatile.LoadUint32(&o.DATACTRL.Reg) & 0x80000000) >> 31
}

// I3C_SLV.WDATAB: NA
func (o *I3C_SLV_Type) SetWDATAB(value uint32) {
	volatile.StoreUint32(&o.WDATAB.Reg, volatile.LoadUint32(&o.WDATAB.Reg)&^(0xff)|value)
}
func (o *I3C_SLV_Type) GetWDATAB() uint32 {
	return volatile.LoadUint32(&o.WDATAB.Reg) & 0xff
}
func (o *I3C_SLV_Type) SetWDATAB_WDATA_END(value uint32) {
	volatile.StoreUint32(&o.WDATAB.Reg, volatile.LoadUint32(&o.WDATAB.Reg)&^(0x100)|value<<8)
}
func (o *I3C_SLV_Type) GetWDATAB_WDATA_END() uint32 {
	return (volatile.LoadUint32(&o.WDATAB.Reg) & 0x100) >> 8
}

// I3C_SLV.WDATABE: NA
func (o *I3C_SLV_Type) SetWDATABE(value uint32) {
	volatile.StoreUint32(&o.WDATABE.Reg, volatile.LoadUint32(&o.WDATABE.Reg)&^(0xff)|value)
}
func (o *I3C_SLV_Type) GetWDATABE() uint32 {
	return volatile.LoadUint32(&o.WDATABE.Reg) & 0xff
}

// I3C_SLV.RDARAB: Read Byte Data (from-bus) register
func (o *I3C_SLV_Type) SetRDARAB_DATA0(value uint32) {
	volatile.StoreUint32(&o.RDARAB.Reg, volatile.LoadUint32(&o.RDARAB.Reg)&^(0xff)|value)
}
func (o *I3C_SLV_Type) GetRDARAB_DATA0() uint32 {
	return volatile.LoadUint32(&o.RDARAB.Reg) & 0xff
}

// I3C_SLV.RDATAH: Read Half-word Data (from-bus) register
func (o *I3C_SLV_Type) SetRDATAH_DATA_LSB(value uint32) {
	volatile.StoreUint32(&o.RDATAH.Reg, volatile.LoadUint32(&o.RDATAH.Reg)&^(0xff)|value)
}
func (o *I3C_SLV_Type) GetRDATAH_DATA_LSB() uint32 {
	return volatile.LoadUint32(&o.RDATAH.Reg) & 0xff
}
func (o *I3C_SLV_Type) SetRDATAH_DATA_MSB(value uint32) {
	volatile.StoreUint32(&o.RDATAH.Reg, volatile.LoadUint32(&o.RDATAH.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_SLV_Type) GetRDATAH_DATA_MSB() uint32 {
	return (volatile.LoadUint32(&o.RDATAH.Reg) & 0xff00) >> 8
}

// I3C_SLV.CAPABILITIES2: NA
func (o *I3C_SLV_Type) SetCAPABILITIES2(value uint32) {
	volatile.StoreUint32(&o.CAPABILITIES2.Reg, value)
}
func (o *I3C_SLV_Type) GetCAPABILITIES2() uint32 {
	return volatile.LoadUint32(&o.CAPABILITIES2.Reg)
}

// I3C_SLV.CAPABILITIES: NA
func (o *I3C_SLV_Type) SetCAPABILITIES(value uint32) {
	volatile.StoreUint32(&o.CAPABILITIES.Reg, value)
}
func (o *I3C_SLV_Type) GetCAPABILITIES() uint32 {
	return volatile.LoadUint32(&o.CAPABILITIES.Reg)
}

// I3C_SLV.IDPARTNO: NA
func (o *I3C_SLV_Type) SetIDPARTNO(value uint32) {
	volatile.StoreUint32(&o.IDPARTNO.Reg, value)
}
func (o *I3C_SLV_Type) GetIDPARTNO() uint32 {
	return volatile.LoadUint32(&o.IDPARTNO.Reg)
}

// I3C_SLV.IDEXT: NA
func (o *I3C_SLV_Type) SetIDEXT(value uint32) {
	volatile.StoreUint32(&o.IDEXT.Reg, value)
}
func (o *I3C_SLV_Type) GetIDEXT() uint32 {
	return volatile.LoadUint32(&o.IDEXT.Reg)
}

// I3C_SLV.VENDORID: NA
func (o *I3C_SLV_Type) SetVENDORID_VID(value uint32) {
	volatile.StoreUint32(&o.VENDORID.Reg, volatile.LoadUint32(&o.VENDORID.Reg)&^(0x7fff)|value)
}
func (o *I3C_SLV_Type) GetVENDORID_VID() uint32 {
	return volatile.LoadUint32(&o.VENDORID.Reg) & 0x7fff
}

// AXI_ICM Peripheral
type ICM_AXI_Type struct {
	VERID_FILEDS volatile.Register32 // 0x0
	HW_CFG       volatile.Register32 // 0x4
	CMD          volatile.Register32 // 0x8
	DATA         volatile.Register32 // 0xC
}

// ICM_AXI.VERID_FILEDS: NA
func (o *ICM_AXI_Type) SetVERID_FILEDS(value uint32) {
	volatile.StoreUint32(&o.VERID_FILEDS.Reg, value)
}
func (o *ICM_AXI_Type) GetVERID_FILEDS() uint32 {
	return volatile.LoadUint32(&o.VERID_FILEDS.Reg)
}

// ICM_AXI.HW_CFG: NA
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_QOS_SUPPORT(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1)|value)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_QOS_SUPPORT() uint32 {
	return volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_APB3_SUPPORT(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x2)|value<<1)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_APB3_SUPPORT() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x2) >> 1
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_AXI4_SUPPORT(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x4)|value<<2)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_AXI4_SUPPORT() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x4) >> 2
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_LOCK_EN(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x8)|value<<3)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_LOCK_EN() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x8) >> 3
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_TRUST_ZONE_EN(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x10)|value<<4)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_TRUST_ZONE_EN() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x10) >> 4
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_DECODER_TYPE(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x20)|value<<5)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_DECODER_TYPE() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x20) >> 5
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_REMAP_EN(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x40)|value<<6)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_REMAP_EN() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x40) >> 6
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x80)|value<<7)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x80) >> 7
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x100)|value<<8)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x100) >> 8
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1f000)|value<<12)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1f000) >> 12
}
func (o *ICM_AXI_Type) SetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1f00000)|value<<20)
}
func (o *ICM_AXI_Type) GetHW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES() uint32 {
	return (volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1f00000) >> 20
}

// ICM_AXI.CMD: NA
func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_CMD(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x7)|value)
}
func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_CMD() uint32 {
	return volatile.LoadUint32(&o.CMD.Reg) & 0x7
}
func (o *ICM_AXI_Type) SetCMD_ICM_REG_RD_WR_CHAN(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80)|value<<7)
}
func (o *ICM_AXI_Type) GetCMD_ICM_REG_RD_WR_CHAN() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x80) >> 7
}
func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_MASTER_PORT(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0xf00)|value<<8)
}
func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_MASTER_PORT() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0xf00) >> 8
}
func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_ERR_BIT(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10000000)|value<<28)
}
func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_ERR_BIT() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x10000000) >> 28
}
func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_SOFT_RESET_BIT(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29)
}
func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_SOFT_RESET_BIT() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29
}
func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_RD_WR_CMD(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40000000)|value<<30)
}
func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_RD_WR_CMD() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x40000000) >> 30
}
func (o *ICM_AXI_Type) SetCMD_ICM_REG_AXI_CMD_EN(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31)
}
func (o *ICM_AXI_Type) GetCMD_ICM_REG_AXI_CMD_EN() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31
}

// ICM_AXI.DATA: NA
func (o *ICM_AXI_Type) SetDATA(value uint32) {
	volatile.StoreUint32(&o.DATA.Reg, value)
}
func (o *ICM_AXI_Type) GetDATA() uint32 {
	return volatile.LoadUint32(&o.DATA.Reg)
}

// Input/Output Multiplexer
type IO_MUX_Type struct {
	_      [4]byte
	GPIO0  volatile.Register32 // 0x4
	GPIO1  volatile.Register32 // 0x8
	GPIO2  volatile.Register32 // 0xC
	GPIO3  volatile.Register32 // 0x10
	GPIO4  volatile.Register32 // 0x14
	GPIO5  volatile.Register32 // 0x18
	GPIO6  volatile.Register32 // 0x1C
	GPIO7  volatile.Register32 // 0x20
	GPIO8  volatile.Register32 // 0x24
	GPIO9  volatile.Register32 // 0x28
	GPIO10 volatile.Register32 // 0x2C
	GPIO11 volatile.Register32 // 0x30
	GPIO12 volatile.Register32 // 0x34
	GPIO13 volatile.Register32 // 0x38
	GPIO14 volatile.Register32 // 0x3C
	GPIO15 volatile.Register32 // 0x40
	GPIO16 volatile.Register32 // 0x44
	GPIO17 volatile.Register32 // 0x48
	GPIO18 volatile.Register32 // 0x4C
	GPIO19 volatile.Register32 // 0x50
	GPIO20 volatile.Register32 // 0x54
	GPIO21 volatile.Register32 // 0x58
	GPIO22 volatile.Register32 // 0x5C
	GPIO23 volatile.Register32 // 0x60
	GPIO24 volatile.Register32 // 0x64
	GPIO25 volatile.Register32 // 0x68
	GPIO26 volatile.Register32 // 0x6C
	GPIO27 volatile.Register32 // 0x70
	GPIO28 volatile.Register32 // 0x74
	GPIO29 volatile.Register32 // 0x78
	GPIO30 volatile.Register32 // 0x7C
	GPIO31 volatile.Register32 // 0x80
	GPIO32 volatile.Register32 // 0x84
	GPIO33 volatile.Register32 // 0x88
	GPIO34 volatile.Register32 // 0x8C
	GPIO35 volatile.Register32 // 0x90
	GPIO36 volatile.Register32 // 0x94
	GPIO37 volatile.Register32 // 0x98
	GPIO38 volatile.Register32 // 0x9C
	GPIO39 volatile.Register32 // 0xA0
	GPIO40 volatile.Register32 // 0xA4
	GPIO41 volatile.Register32 // 0xA8
	GPIO42 volatile.Register32 // 0xAC
	GPIO43 volatile.Register32 // 0xB0
	GPIO44 volatile.Register32 // 0xB4
	GPIO45 volatile.Register32 // 0xB8
	GPIO46 volatile.Register32 // 0xBC
	GPIO47 volatile.Register32 // 0xC0
	GPIO48 volatile.Register32 // 0xC4
	GPIO49 volatile.Register32 // 0xC8
	GPIO50 volatile.Register32 // 0xCC
	GPIO51 volatile.Register32 // 0xD0
	GPIO52 volatile.Register32 // 0xD4
	GPIO53 volatile.Register32 // 0xD8
	_      [40]byte
	DATE   volatile.Register32 // 0x104
}

// IO_MUX.GPIO0: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO0_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO0_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO0.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO0_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO0_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO0_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO0_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO0_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO0_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO0_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO0_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO0_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO0_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO0_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO0_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO0_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO0_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO0_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO0_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO0_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO0_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO0_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO0_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO0_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO0.Reg, volatile.LoadUint32(&o.GPIO0.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO0_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO0.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO1: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO1_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO1_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO1.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO1_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO1_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO1_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO1_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO1_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO1_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO1_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO1_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO1_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO1_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO1_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO1_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO1_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO1_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO1_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO1_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO1_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO1_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO1_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO1_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO1_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO1.Reg, volatile.LoadUint32(&o.GPIO1.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO1_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO1.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO2: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO2_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO2_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO2.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO2_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO2_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO2_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO2_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO2_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO2_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO2_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO2_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO2_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO2_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO2_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO2_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO2_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO2_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO2_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO2_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO2_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO2_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO2_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO2_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO2_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO2.Reg, volatile.LoadUint32(&o.GPIO2.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO2_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO2.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO3: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO3_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO3_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO3.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO3_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO3_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO3_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO3_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO3_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO3_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO3_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO3_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO3_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO3_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO3_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO3_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO3_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO3_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO3_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO3_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO3_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO3_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO3_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO3_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO3_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO3.Reg, volatile.LoadUint32(&o.GPIO3.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO3_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO3.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO4: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO4_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO4_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO4.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO4_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO4_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO4_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO4_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO4_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO4_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO4_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO4_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO4_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO4_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO4_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO4_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO4_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO4_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO4_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO4_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO4_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO4_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO4_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO4_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO4_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO4.Reg, volatile.LoadUint32(&o.GPIO4.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO4_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO4.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO5: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO5_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO5_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO5.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO5_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO5_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO5_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO5_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO5_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO5_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO5_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO5_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO5_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO5_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO5_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO5_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO5_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO5_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO5_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO5_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO5_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO5_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO5_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO5_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO5_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO5.Reg, volatile.LoadUint32(&o.GPIO5.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO5_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO5.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO6: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO6_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO6_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO6.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO6_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO6_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO6_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO6_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO6_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO6_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO6_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO6_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO6_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO6_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO6_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO6_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO6_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO6_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO6_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO6_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO6_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO6_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO6_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO6_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO6_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO6.Reg, volatile.LoadUint32(&o.GPIO6.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO6_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO6.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO7: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO7_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO7_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO7.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO7_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO7_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO7_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO7_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO7_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO7_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO7_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO7_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO7_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO7_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO7_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO7_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO7_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO7_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO7_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO7_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO7_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO7_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO7_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO7_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO7_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO7.Reg, volatile.LoadUint32(&o.GPIO7.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO7_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO7.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO8: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO8_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO8_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO8.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO8_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO8_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO8_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO8_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO8_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO8_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO8_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO8_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO8_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO8_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO8_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO8_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO8_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO8_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO8_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO8_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO8_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO8_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO8_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO8_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO8_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO8.Reg, volatile.LoadUint32(&o.GPIO8.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO8_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO8.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO9: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO9_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO9_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO9.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO9_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO9_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO9_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO9_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO9_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO9_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO9_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO9_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO9_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO9_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO9_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO9_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO9_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO9_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO9_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO9_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO9_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO9_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO9_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO9_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO9_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO9.Reg, volatile.LoadUint32(&o.GPIO9.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO9_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO9.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO10: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO10_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO10_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO10.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO10_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO10_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO10_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO10_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO10_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO10_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO10_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO10_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO10_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO10_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO10_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO10_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO10_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO10_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO10_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO10_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO10_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO10_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO10_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO10_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO10_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO10.Reg, volatile.LoadUint32(&o.GPIO10.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO10_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO10.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO11: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO11_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO11_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO11.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO11_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO11_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO11_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO11_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO11_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO11_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO11_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO11_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO11_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO11_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO11_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO11_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO11_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO11_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO11_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO11_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO11_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO11_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO11_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO11_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO11_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO11.Reg, volatile.LoadUint32(&o.GPIO11.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO11_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO11.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO12: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO12_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO12_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO12.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO12_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO12_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO12_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO12_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO12_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO12_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO12_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO12_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO12_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO12_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO12_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO12_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO12_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO12_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO12_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO12_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO12_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO12_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO12_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO12_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO12_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO12.Reg, volatile.LoadUint32(&o.GPIO12.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO12_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO12.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO13: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO13_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO13_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO13.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO13_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO13_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO13_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO13_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO13_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO13_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO13_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO13_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO13_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO13_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO13_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO13_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO13_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO13_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO13_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO13_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO13_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO13_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO13_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO13_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO13_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO13.Reg, volatile.LoadUint32(&o.GPIO13.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO13_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO13.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO14: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO14_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO14_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO14.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO14_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO14_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO14_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO14_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO14_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO14_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO14_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO14_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO14_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO14_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO14_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO14_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO14_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO14_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO14_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO14_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO14_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO14_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO14_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO14_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO14_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO14.Reg, volatile.LoadUint32(&o.GPIO14.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO14_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO14.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO15: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO15_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO15_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO15.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO15_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO15_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO15_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO15_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO15_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO15_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO15_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO15_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO15_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO15_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO15_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO15_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO15_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO15_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO15_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO15_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO15_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO15_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO15_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO15_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO15_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO15.Reg, volatile.LoadUint32(&o.GPIO15.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO15_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO15.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO16: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO16_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO16_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO16.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO16_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO16_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO16_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO16_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO16_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO16_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO16_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO16_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO16_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO16_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO16_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO16_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO16_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO16_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO16_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO16_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO16_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO16_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO16_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO16_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO16_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO16.Reg, volatile.LoadUint32(&o.GPIO16.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO16_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO16.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO17: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO17_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO17_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO17.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO17_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO17_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO17_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO17_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO17_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO17_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO17_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO17_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO17_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO17_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO17_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO17_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO17_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO17_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO17_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO17_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO17_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO17_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO17_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO17_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO17_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO17.Reg, volatile.LoadUint32(&o.GPIO17.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO17_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO17.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO18: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO18_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO18_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO18.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO18_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO18_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO18_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO18_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO18_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO18_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO18_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO18_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO18_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO18_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO18_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO18_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO18_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO18_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO18_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO18_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO18_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO18_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO18_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO18_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO18_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO18.Reg, volatile.LoadUint32(&o.GPIO18.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO18_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO18.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO19: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO19_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO19_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO19.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO19_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO19_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO19_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO19_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO19_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO19_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO19_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO19_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO19_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO19_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO19_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO19_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO19_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO19_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO19_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO19_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO19_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO19_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO19_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO19_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO19_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO19.Reg, volatile.LoadUint32(&o.GPIO19.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO19_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO19.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO20: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO20_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO20_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO20.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO20_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO20_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO20_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO20_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO20_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO20_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO20_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO20_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO20_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO20_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO20_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO20_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO20_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO20_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO20_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO20_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO20_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO20_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO20_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO20_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO20_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO20.Reg, volatile.LoadUint32(&o.GPIO20.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO20_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO20.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO21: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO21_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO21_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO21.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO21_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO21_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO21_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO21_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO21_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO21_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO21_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO21_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO21_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO21_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO21_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO21_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO21_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO21_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO21_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO21_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO21_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO21_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO21_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO21_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO21_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO21.Reg, volatile.LoadUint32(&o.GPIO21.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO21_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO21.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO22: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO22_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO22_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO22.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO22_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO22_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO22_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO22_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO22_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO22_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO22_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO22_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO22_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO22_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO22_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO22_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO22_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO22_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO22_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO22_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO22_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO22_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO22_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO22_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO22_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO22.Reg, volatile.LoadUint32(&o.GPIO22.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO22_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO22.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO23: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO23_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO23_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO23.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO23_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO23_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO23_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO23_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO23_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO23_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO23_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO23_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO23_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO23_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO23_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO23_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO23_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO23_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO23_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO23_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO23_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO23_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO23_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO23_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO23_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO23.Reg, volatile.LoadUint32(&o.GPIO23.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO23_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO23.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO24: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO24_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO24_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO24.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO24_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO24_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO24_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO24_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO24_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO24_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO24_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO24_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO24_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO24_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO24_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO24_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO24_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO24_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO24_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO24_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO24_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO24_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO24_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO24_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO24_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO24.Reg, volatile.LoadUint32(&o.GPIO24.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO24_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO24.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO25: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO25_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO25_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO25.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO25_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO25_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO25_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO25_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO25_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO25_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO25_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO25_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO25_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO25_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO25_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO25_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO25_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO25_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO25_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO25_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO25_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO25_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO25_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO25_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO25_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO25.Reg, volatile.LoadUint32(&o.GPIO25.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO25_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO25.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO26: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO26_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO26_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO26.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO26_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO26_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO26_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO26_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO26_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO26_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO26_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO26_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO26_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO26_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO26_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO26_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO26_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO26_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO26_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO26_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO26_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO26_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO26_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO26_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO26_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO26.Reg, volatile.LoadUint32(&o.GPIO26.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO26_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO26.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO27: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO27_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO27_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO27.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO27_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO27_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO27_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO27_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO27_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO27_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO27_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO27_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO27_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO27_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO27_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO27_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO27_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO27_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO27_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO27_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO27_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO27_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO27_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO27_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO27_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO27.Reg, volatile.LoadUint32(&o.GPIO27.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO27_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO27.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO28: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO28_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO28_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO28.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO28_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO28_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO28_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO28_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO28_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO28_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO28_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO28_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO28_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO28_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO28_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO28_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO28_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO28_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO28_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO28_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO28_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO28_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO28_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO28_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO28_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO28.Reg, volatile.LoadUint32(&o.GPIO28.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO28_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO28.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO29: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO29_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO29_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO29.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO29_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO29_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO29_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO29_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO29_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO29_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO29_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO29_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO29_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO29_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO29_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO29_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO29_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO29_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO29_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO29_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO29_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO29_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO29_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO29_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO29_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO29.Reg, volatile.LoadUint32(&o.GPIO29.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO29_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO29.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO30: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO30_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO30_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO30.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO30_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO30_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO30_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO30_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO30_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO30_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO30_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO30_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO30_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO30_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO30_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO30_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO30_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO30_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO30_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO30_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO30_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO30_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO30_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO30_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO30_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO30.Reg, volatile.LoadUint32(&o.GPIO30.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO30_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO30.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO31: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO31_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO31_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO31.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO31_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO31_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO31_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO31_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO31_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO31_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO31_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO31_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO31_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO31_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO31_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO31_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO31_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO31_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO31_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO31_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO31_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO31_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO31_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO31_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO31_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO31.Reg, volatile.LoadUint32(&o.GPIO31.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO31_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO31.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO32: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO32_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO32_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO32.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO32_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO32_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO32_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO32_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO32_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO32_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO32_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO32_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO32_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO32_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO32_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO32_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO32_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO32_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO32_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO32_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO32_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO32_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO32_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO32_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO32_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO32.Reg, volatile.LoadUint32(&o.GPIO32.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO32_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO32.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO33: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO33_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO33_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO33.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO33_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO33_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO33_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO33_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO33_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO33_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO33_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO33_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO33_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO33_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO33_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO33_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO33_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO33_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO33_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO33_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO33_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO33_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO33_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO33_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO33_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO33.Reg, volatile.LoadUint32(&o.GPIO33.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO33_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO33.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO34: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO34_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO34_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO34.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO34_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO34_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO34_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO34_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO34_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO34_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO34_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO34_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO34_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO34_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO34_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO34_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO34_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO34_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO34_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO34_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO34_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO34_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO34_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO34_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO34_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO34.Reg, volatile.LoadUint32(&o.GPIO34.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO34_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO34.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO35: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO35_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO35_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO35.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO35_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO35_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO35_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO35_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO35_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO35_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO35_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO35_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO35_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO35_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO35_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO35_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO35_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO35_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO35_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO35_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO35_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO35_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO35_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO35_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO35_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO35.Reg, volatile.LoadUint32(&o.GPIO35.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO35_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO35.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO36: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO36_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO36_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO36.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO36_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO36_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO36_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO36_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO36_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO36_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO36_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO36_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO36_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO36_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO36_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO36_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO36_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO36_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO36_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO36_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO36_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO36_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO36_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO36_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO36_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO36.Reg, volatile.LoadUint32(&o.GPIO36.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO36_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO36.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO37: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO37_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO37_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO37.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO37_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO37_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO37_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO37_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO37_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO37_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO37_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO37_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO37_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO37_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO37_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO37_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO37_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO37_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO37_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO37_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO37_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO37_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO37_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO37_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO37_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO37.Reg, volatile.LoadUint32(&o.GPIO37.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO37_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO37.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO38: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO38_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO38_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO38.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO38_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO38_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO38_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO38_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO38_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO38_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO38_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO38_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO38_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO38_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO38_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO38_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO38_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO38_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO38_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO38_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO38_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO38_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO38_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO38_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO38_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO38.Reg, volatile.LoadUint32(&o.GPIO38.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO38_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO38.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO39: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO39_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO39_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO39.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO39_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO39_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO39_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO39_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO39_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO39_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO39_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO39_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO39_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO39_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO39_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO39_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO39_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO39_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO39_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO39_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO39_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO39_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO39_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO39_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO39_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO39.Reg, volatile.LoadUint32(&o.GPIO39.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO39_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO39.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO40: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO40_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO40_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO40.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO40_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO40_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO40_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO40_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO40_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO40_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO40_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO40_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO40_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO40_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO40_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO40_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO40_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO40_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO40_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO40_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO40_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO40_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO40_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO40_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO40_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO40.Reg, volatile.LoadUint32(&o.GPIO40.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO40_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO40.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO41: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO41_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO41_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO41.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO41_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO41_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO41_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO41_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO41_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO41_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO41_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO41_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO41_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO41_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO41_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO41_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO41_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO41_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO41_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO41_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO41_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO41_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO41_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO41_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO41_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO41.Reg, volatile.LoadUint32(&o.GPIO41.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO41_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO41.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO42: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO42_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO42_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO42.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO42_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO42_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO42_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO42_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO42_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO42_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO42_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO42_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO42_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO42_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO42_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO42_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO42_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO42_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO42_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO42_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO42_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO42_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO42_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO42_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO42_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO42.Reg, volatile.LoadUint32(&o.GPIO42.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO42_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO42.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO43: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO43_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO43_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO43.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO43_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO43_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO43_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO43_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO43_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO43_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO43_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO43_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO43_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO43_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO43_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO43_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO43_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO43_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO43_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO43_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO43_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO43_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO43_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO43_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO43_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO43.Reg, volatile.LoadUint32(&o.GPIO43.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO43_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO43.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO44: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO44_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO44_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO44.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO44_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO44_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO44_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO44_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO44_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO44_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO44_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO44_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO44_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO44_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO44_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO44_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO44_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO44_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO44_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO44_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO44_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO44_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO44_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO44_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO44_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO44.Reg, volatile.LoadUint32(&o.GPIO44.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO44_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO44.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO45: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO45_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO45_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO45.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO45_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO45_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO45_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO45_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO45_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO45_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO45_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO45_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO45_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO45_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO45_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO45_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO45_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO45_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO45_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO45_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO45_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO45_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO45_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO45_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO45_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO45.Reg, volatile.LoadUint32(&o.GPIO45.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO45_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO45.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO46: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO46_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO46_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO46.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO46_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO46_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO46_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO46_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO46_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO46_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO46_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO46_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO46_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO46_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO46_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO46_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO46_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO46_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO46_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO46_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO46_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO46_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO46_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO46_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO46_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO46.Reg, volatile.LoadUint32(&o.GPIO46.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO46_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO46.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO47: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO47_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO47_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO47.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO47_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO47_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO47_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO47_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO47_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO47_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO47_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO47_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO47_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO47_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO47_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO47_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO47_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO47_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO47_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO47_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO47_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO47_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO47_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO47_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO47_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO47.Reg, volatile.LoadUint32(&o.GPIO47.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO47_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO47.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO48: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO48_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO48_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO48.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO48_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO48_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO48_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO48_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO48_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO48_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO48_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO48_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO48_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO48_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO48_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO48_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO48_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO48_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO48_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO48_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO48_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO48_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO48_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO48_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO48_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO48.Reg, volatile.LoadUint32(&o.GPIO48.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO48_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO48.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO49: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO49_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO49_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO49.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO49_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO49_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO49_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO49_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO49_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO49_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO49_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO49_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO49_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO49_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO49_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO49_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO49_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO49_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO49_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO49_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO49_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO49_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO49_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO49_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO49_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO49.Reg, volatile.LoadUint32(&o.GPIO49.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO49_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO49.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO50: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO50_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO50_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO50.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO50_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO50_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO50_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO50_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO50_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO50_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO50_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO50_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO50_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO50_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO50_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO50_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO50_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO50_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO50_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO50_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO50_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO50_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO50_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO50_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO50_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO50.Reg, volatile.LoadUint32(&o.GPIO50.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO50_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO50.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO51: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO51_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO51_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO51.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO51_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO51_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO51_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO51_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO51_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO51_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO51_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO51_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO51_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO51_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO51_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO51_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO51_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO51_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO51_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO51_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO51_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO51_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO51_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO51_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO51_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO51.Reg, volatile.LoadUint32(&o.GPIO51.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO51_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO51.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO52: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO52_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO52_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO52.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO52_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO52_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO52_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO52_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO52_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO52_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO52_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO52_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO52_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO52_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO52_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO52_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO52_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO52_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO52_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO52_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO52_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO52_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO52_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO52_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO52_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO52.Reg, volatile.LoadUint32(&o.GPIO52.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO52_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO52.Reg) & 0x8000) >> 15
}

// IO_MUX.GPIO53: IO_MUX Control Register
func (o *IO_MUX_Type) SetGPIO53_MCU_OE(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x1)|value)
}
func (o *IO_MUX_Type) GetGPIO53_MCU_OE() uint32 {
	return volatile.LoadUint32(&o.GPIO53.Reg) & 0x1
}
func (o *IO_MUX_Type) SetGPIO53_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x2)|value<<1)
}
func (o *IO_MUX_Type) GetGPIO53_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x2) >> 1
}
func (o *IO_MUX_Type) SetGPIO53_MCU_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x4)|value<<2)
}
func (o *IO_MUX_Type) GetGPIO53_MCU_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x4) >> 2
}
func (o *IO_MUX_Type) SetGPIO53_MCU_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x8)|value<<3)
}
func (o *IO_MUX_Type) GetGPIO53_MCU_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x8) >> 3
}
func (o *IO_MUX_Type) SetGPIO53_MCU_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x10)|value<<4)
}
func (o *IO_MUX_Type) GetGPIO53_MCU_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x10) >> 4
}
func (o *IO_MUX_Type) SetGPIO53_MCU_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x60)|value<<5)
}
func (o *IO_MUX_Type) GetGPIO53_MCU_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x60) >> 5
}
func (o *IO_MUX_Type) SetGPIO53_FUN_WPD(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x80)|value<<7)
}
func (o *IO_MUX_Type) GetGPIO53_FUN_WPD() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x80) >> 7
}
func (o *IO_MUX_Type) SetGPIO53_FUN_WPU(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x100)|value<<8)
}
func (o *IO_MUX_Type) GetGPIO53_FUN_WPU() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x100) >> 8
}
func (o *IO_MUX_Type) SetGPIO53_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x200)|value<<9)
}
func (o *IO_MUX_Type) GetGPIO53_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x200) >> 9
}
func (o *IO_MUX_Type) SetGPIO53_FUN_DRV(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0xc00)|value<<10)
}
func (o *IO_MUX_Type) GetGPIO53_FUN_DRV() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0xc00) >> 10
}
func (o *IO_MUX_Type) SetGPIO53_MCU_SEL(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x7000)|value<<12)
}
func (o *IO_MUX_Type) GetGPIO53_MCU_SEL() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x7000) >> 12
}
func (o *IO_MUX_Type) SetGPIO53_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.GPIO53.Reg, volatile.LoadUint32(&o.GPIO53.Reg)&^(0x8000)|value<<15)
}
func (o *IO_MUX_Type) GetGPIO53_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.GPIO53.Reg) & 0x8000) >> 15
}

// IO_MUX.DATE: iomux version
func (o *IO_MUX_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *IO_MUX_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// ISP Peripheral
type ISP_Type struct {
	VER_DATE             volatile.Register32 // 0x0
	CLK_EN               volatile.Register32 // 0x4
	CNTL                 volatile.Register32 // 0x8
	HSYNC_CNT            volatile.Register32 // 0xC
	FRAME_CFG            volatile.Register32 // 0x10
	CCM_COEF0            volatile.Register32 // 0x14
	CCM_COEF1            volatile.Register32 // 0x18
	CCM_COEF3            volatile.Register32 // 0x1C
	CCM_COEF4            volatile.Register32 // 0x20
	CCM_COEF5            volatile.Register32 // 0x24
	BF_MATRIX_CTRL       volatile.Register32 // 0x28
	BF_SIGMA             volatile.Register32 // 0x2C
	BF_GAU0              volatile.Register32 // 0x30
	BF_GAU1              volatile.Register32 // 0x34
	DPC_CTRL             volatile.Register32 // 0x38
	DPC_CONF             volatile.Register32 // 0x3C
	DPC_MATRIX_CTRL      volatile.Register32 // 0x40
	DPC_DEADPIX_CNT      volatile.Register32 // 0x44
	LUT_CMD              volatile.Register32 // 0x48
	LUT_WDATA            volatile.Register32 // 0x4C
	LUT_RDATA            volatile.Register32 // 0x50
	LSC_TABLESIZE        volatile.Register32 // 0x54
	DEMOSAIC_MATRIX_CTRL volatile.Register32 // 0x58
	DEMOSAIC_GRAD_RATIO  volatile.Register32 // 0x5C
	MEDIAN_MATRIX_CTRL   volatile.Register32 // 0x60
	INT_RAW              volatile.Register32 // 0x64
	INT_ST               volatile.Register32 // 0x68
	INT_ENA              volatile.Register32 // 0x6C
	INT_CLR              volatile.Register32 // 0x70
	GAMMA_CTRL           volatile.Register32 // 0x74
	GAMMA_RY1            volatile.Register32 // 0x78
	GAMMA_RY2            volatile.Register32 // 0x7C
	GAMMA_RY3            volatile.Register32 // 0x80
	GAMMA_RY4            volatile.Register32 // 0x84
	GAMMA_GY1            volatile.Register32 // 0x88
	GAMMA_GY2            volatile.Register32 // 0x8C
	GAMMA_GY3            volatile.Register32 // 0x90
	GAMMA_GY4            volatile.Register32 // 0x94
	GAMMA_BY1            volatile.Register32 // 0x98
	GAMMA_BY2            volatile.Register32 // 0x9C
	GAMMA_BY3            volatile.Register32 // 0xA0
	GAMMA_BY4            volatile.Register32 // 0xA4
	GAMMA_RX1            volatile.Register32 // 0xA8
	GAMMA_RX2            volatile.Register32 // 0xAC
	GAMMA_GX1            volatile.Register32 // 0xB0
	GAMMA_GX2            volatile.Register32 // 0xB4
	GAMMA_BX1            volatile.Register32 // 0xB8
	GAMMA_BX2            volatile.Register32 // 0xBC
	AE_CTRL              volatile.Register32 // 0xC0
	AE_MONITOR           volatile.Register32 // 0xC4
	AE_BX                volatile.Register32 // 0xC8
	AE_BY                volatile.Register32 // 0xCC
	AE_WINPIXNUM         volatile.Register32 // 0xD0
	AE_WIN_RECIPROCAL    volatile.Register32 // 0xD4
	AE_BLOCK_MEAN_0      volatile.Register32 // 0xD8
	AE_BLOCK_MEAN_1      volatile.Register32 // 0xDC
	AE_BLOCK_MEAN_2      volatile.Register32 // 0xE0
	AE_BLOCK_MEAN_3      volatile.Register32 // 0xE4
	AE_BLOCK_MEAN_4      volatile.Register32 // 0xE8
	AE_BLOCK_MEAN_5      volatile.Register32 // 0xEC
	AE_BLOCK_MEAN_6      volatile.Register32 // 0xF0
	SHARP_CTRL0          volatile.Register32 // 0xF4
	SHARP_FILTER0        volatile.Register32 // 0xF8
	SHARP_FILTER1        volatile.Register32 // 0xFC
	SHARP_FILTER2        volatile.Register32 // 0x100
	SHARP_MATRIX_CTRL    volatile.Register32 // 0x104
	SHARP_CTRL1          volatile.Register32 // 0x108
	DMA_CNTL             volatile.Register32 // 0x10C
	DMA_RAW_DATA         volatile.Register32 // 0x110
	CAM_CNTL             volatile.Register32 // 0x114
	CAM_CONF             volatile.Register32 // 0x118
	AF_CTRL0             volatile.Register32 // 0x11C
	AF_CTRL1             volatile.Register32 // 0x120
	AF_GEN_TH_CTRL       volatile.Register32 // 0x124
	AF_ENV_USER_TH_SUM   volatile.Register32 // 0x128
	AF_ENV_USER_TH_LUM   volatile.Register32 // 0x12C
	AF_THRESHOLD         volatile.Register32 // 0x130
	AF_HSCALE_A          volatile.Register32 // 0x134
	AF_VSCALE_A          volatile.Register32 // 0x138
	AF_HSCALE_B          volatile.Register32 // 0x13C
	AF_VSCALE_B          volatile.Register32 // 0x140
	AF_HSCALE_C          volatile.Register32 // 0x144
	AF_VSCALE_C          volatile.Register32 // 0x148
	AF_SUM_A             volatile.Register32 // 0x14C
	AF_SUM_B             volatile.Register32 // 0x150
	AF_SUM_C             volatile.Register32 // 0x154
	AF_LUM_A             volatile.Register32 // 0x158
	AF_LUM_B             volatile.Register32 // 0x15C
	AF_LUM_C             volatile.Register32 // 0x160
	AWB_MODE             volatile.Register32 // 0x164
	AWB_HSCALE           volatile.Register32 // 0x168
	AWB_VSCALE           volatile.Register32 // 0x16C
	AWB_TH_LUM           volatile.Register32 // 0x170
	AWB_TH_RG            volatile.Register32 // 0x174
	AWB_TH_BG            volatile.Register32 // 0x178
	AWB0_WHITE_CNT       volatile.Register32 // 0x17C
	AWB0_ACC_R           volatile.Register32 // 0x180
	AWB0_ACC_G           volatile.Register32 // 0x184
	AWB0_ACC_B           volatile.Register32 // 0x188
	COLOR_CTRL           volatile.Register32 // 0x18C
	BLC_VALUE            volatile.Register32 // 0x190
	BLC_CTRL0            volatile.Register32 // 0x194
	BLC_CTRL1            volatile.Register32 // 0x198
	BLC_CTRL2            volatile.Register32 // 0x19C
	BLC_MEAN             volatile.Register32 // 0x1A0
	HIST_MODE            volatile.Register32 // 0x1A4
	HIST_COEFF           volatile.Register32 // 0x1A8
	HIST_OFFS            volatile.Register32 // 0x1AC
	HIST_SIZE            volatile.Register32 // 0x1B0
	HIST_SEG0            volatile.Register32 // 0x1B4
	HIST_SEG1            volatile.Register32 // 0x1B8
	HIST_SEG2            volatile.Register32 // 0x1BC
	HIST_SEG3            volatile.Register32 // 0x1C0
	HIST_WEIGHT0         volatile.Register32 // 0x1C4
	HIST_WEIGHT1         volatile.Register32 // 0x1C8
	HIST_WEIGHT2         volatile.Register32 // 0x1CC
	HIST_WEIGHT3         volatile.Register32 // 0x1D0
	HIST_WEIGHT4         volatile.Register32 // 0x1D4
	HIST_WEIGHT5         volatile.Register32 // 0x1D8
	HIST_WEIGHT6         volatile.Register32 // 0x1DC
	HIST_BIN0            volatile.Register32 // 0x1E0
	HIST_BIN1            volatile.Register32 // 0x1E4
	HIST_BIN2            volatile.Register32 // 0x1E8
	HIST_BIN3            volatile.Register32 // 0x1EC
	HIST_BIN4            volatile.Register32 // 0x1F0
	HIST_BIN5            volatile.Register32 // 0x1F4
	HIST_BIN6            volatile.Register32 // 0x1F8
	HIST_BIN7            volatile.Register32 // 0x1FC
	HIST_BIN8            volatile.Register32 // 0x200
	HIST_BIN9            volatile.Register32 // 0x204
	HIST_BIN10           volatile.Register32 // 0x208
	HIST_BIN11           volatile.Register32 // 0x20C
	HIST_BIN12           volatile.Register32 // 0x210
	HIST_BIN13           volatile.Register32 // 0x214
	HIST_BIN14           volatile.Register32 // 0x218
	HIST_BIN15           volatile.Register32 // 0x21C
	MEM_AUX_CTRL_0       volatile.Register32 // 0x220
	MEM_AUX_CTRL_1       volatile.Register32 // 0x224
	MEM_AUX_CTRL_2       volatile.Register32 // 0x228
	MEM_AUX_CTRL_3       volatile.Register32 // 0x22C
	MEM_AUX_CTRL_4       volatile.Register32 // 0x230
	YUV_FORMAT           volatile.Register32 // 0x234
	RDN_ECO_CS           volatile.Register32 // 0x238
	RDN_ECO_LOW          volatile.Register32 // 0x23C
	RDN_ECO_HIGH         volatile.Register32 // 0x240
}

// ISP.VER_DATE: version control register
func (o *ISP_Type) SetVER_DATE(value uint32) {
	volatile.StoreUint32(&o.VER_DATE.Reg, value)
}
func (o *ISP_Type) GetVER_DATE() uint32 {
	return volatile.LoadUint32(&o.VER_DATE.Reg)
}

// ISP.CLK_EN: isp clk control register
func (o *ISP_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetCLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1
}
func (o *ISP_Type) SetCLK_EN_CLK_BLC_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetCLK_EN_CLK_BLC_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetCLK_EN_CLK_DPC_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetCLK_EN_CLK_DPC_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetCLK_EN_CLK_BF_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetCLK_EN_CLK_BF_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8) >> 3
}
func (o *ISP_Type) SetCLK_EN_CLK_LSC_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetCLK_EN_CLK_LSC_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetCLK_EN_CLK_DEMOSAIC_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20)|value<<5)
}
func (o *ISP_Type) GetCLK_EN_CLK_DEMOSAIC_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20) >> 5
}
func (o *ISP_Type) SetCLK_EN_CLK_MEDIAN_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40)|value<<6)
}
func (o *ISP_Type) GetCLK_EN_CLK_MEDIAN_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40) >> 6
}
func (o *ISP_Type) SetCLK_EN_CLK_CCM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80)|value<<7)
}
func (o *ISP_Type) GetCLK_EN_CLK_CCM_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80) >> 7
}
func (o *ISP_Type) SetCLK_EN_CLK_GAMMA_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetCLK_EN_CLK_GAMMA_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x100) >> 8
}
func (o *ISP_Type) SetCLK_EN_CLK_RGB2YUV_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x200)|value<<9)
}
func (o *ISP_Type) GetCLK_EN_CLK_RGB2YUV_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x200) >> 9
}
func (o *ISP_Type) SetCLK_EN_CLK_SHARP_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x400)|value<<10)
}
func (o *ISP_Type) GetCLK_EN_CLK_SHARP_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x400) >> 10
}
func (o *ISP_Type) SetCLK_EN_CLK_COLOR_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x800)|value<<11)
}
func (o *ISP_Type) GetCLK_EN_CLK_COLOR_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x800) >> 11
}
func (o *ISP_Type) SetCLK_EN_CLK_YUV2RGB_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1000)|value<<12)
}
func (o *ISP_Type) GetCLK_EN_CLK_YUV2RGB_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1000) >> 12
}
func (o *ISP_Type) SetCLK_EN_CLK_AE_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2000)|value<<13)
}
func (o *ISP_Type) GetCLK_EN_CLK_AE_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2000) >> 13
}
func (o *ISP_Type) SetCLK_EN_CLK_AF_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4000)|value<<14)
}
func (o *ISP_Type) GetCLK_EN_CLK_AF_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4000) >> 14
}
func (o *ISP_Type) SetCLK_EN_CLK_AWB_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8000)|value<<15)
}
func (o *ISP_Type) GetCLK_EN_CLK_AWB_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8000) >> 15
}
func (o *ISP_Type) SetCLK_EN_CLK_HIST_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000)|value<<16)
}
func (o *ISP_Type) GetCLK_EN_CLK_HIST_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000) >> 16
}
func (o *ISP_Type) SetCLK_EN_CLK_MIPI_IDI_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000)|value<<17)
}
func (o *ISP_Type) GetCLK_EN_CLK_MIPI_IDI_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000) >> 17
}
func (o *ISP_Type) SetCLK_EN_ISP_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000)|value<<18)
}
func (o *ISP_Type) GetCLK_EN_ISP_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000) >> 18
}

// ISP.CNTL: isp module enable control register
func (o *ISP_Type) SetCNTL_MIPI_DATA_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetCNTL_MIPI_DATA_EN() uint32 {
	return volatile.LoadUint32(&o.CNTL.Reg) & 0x1
}
func (o *ISP_Type) SetCNTL_ISP_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetCNTL_ISP_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetCNTL_BLC_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetCNTL_BLC_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetCNTL_DPC_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetCNTL_DPC_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x8) >> 3
}
func (o *ISP_Type) SetCNTL_BF_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetCNTL_BF_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetCNTL_LSC_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x20)|value<<5)
}
func (o *ISP_Type) GetCNTL_LSC_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x20) >> 5
}
func (o *ISP_Type) SetCNTL_DEMOSAIC_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x40)|value<<6)
}
func (o *ISP_Type) GetCNTL_DEMOSAIC_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x40) >> 6
}
func (o *ISP_Type) SetCNTL_MEDIAN_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x80)|value<<7)
}
func (o *ISP_Type) GetCNTL_MEDIAN_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x80) >> 7
}
func (o *ISP_Type) SetCNTL_CCM_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetCNTL_CCM_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x100) >> 8
}
func (o *ISP_Type) SetCNTL_GAMMA_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x200)|value<<9)
}
func (o *ISP_Type) GetCNTL_GAMMA_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x200) >> 9
}
func (o *ISP_Type) SetCNTL_RGB2YUV_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x400)|value<<10)
}
func (o *ISP_Type) GetCNTL_RGB2YUV_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x400) >> 10
}
func (o *ISP_Type) SetCNTL_SHARP_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x800)|value<<11)
}
func (o *ISP_Type) GetCNTL_SHARP_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x800) >> 11
}
func (o *ISP_Type) SetCNTL_COLOR_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x1000)|value<<12)
}
func (o *ISP_Type) GetCNTL_COLOR_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x1000) >> 12
}
func (o *ISP_Type) SetCNTL_YUV2RGB_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x2000)|value<<13)
}
func (o *ISP_Type) GetCNTL_YUV2RGB_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x2000) >> 13
}
func (o *ISP_Type) SetCNTL_AE_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x4000)|value<<14)
}
func (o *ISP_Type) GetCNTL_AE_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x4000) >> 14
}
func (o *ISP_Type) SetCNTL_AF_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x8000)|value<<15)
}
func (o *ISP_Type) GetCNTL_AF_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x8000) >> 15
}
func (o *ISP_Type) SetCNTL_AWB_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x10000)|value<<16)
}
func (o *ISP_Type) GetCNTL_AWB_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x10000) >> 16
}
func (o *ISP_Type) SetCNTL_HIST_EN(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x20000)|value<<17)
}
func (o *ISP_Type) GetCNTL_HIST_EN() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x20000) >> 17
}
func (o *ISP_Type) SetCNTL_BYTE_ENDIAN_ORDER(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetCNTL_BYTE_ENDIAN_ORDER() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x1000000) >> 24
}
func (o *ISP_Type) SetCNTL_ISP_DATA_TYPE(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x6000000)|value<<25)
}
func (o *ISP_Type) GetCNTL_ISP_DATA_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x6000000) >> 25
}
func (o *ISP_Type) SetCNTL_ISP_IN_SRC(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0x18000000)|value<<27)
}
func (o *ISP_Type) GetCNTL_ISP_IN_SRC() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0x18000000) >> 27
}
func (o *ISP_Type) SetCNTL_ISP_OUT_TYPE(value uint32) {
	volatile.StoreUint32(&o.CNTL.Reg, volatile.LoadUint32(&o.CNTL.Reg)&^(0xe0000000)|value<<29)
}
func (o *ISP_Type) GetCNTL_ISP_OUT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CNTL.Reg) & 0xe0000000) >> 29
}

// ISP.HSYNC_CNT: header hsync interval control register
func (o *ISP_Type) SetHSYNC_CNT(value uint32) {
	volatile.StoreUint32(&o.HSYNC_CNT.Reg, volatile.LoadUint32(&o.HSYNC_CNT.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHSYNC_CNT() uint32 {
	return volatile.LoadUint32(&o.HSYNC_CNT.Reg) & 0xff
}

// ISP.FRAME_CFG: frame control parameter register
func (o *ISP_Type) SetFRAME_CFG_VADR_NUM(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetFRAME_CFG_VADR_NUM() uint32 {
	return volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff
}
func (o *ISP_Type) SetFRAME_CFG_HADR_NUM(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0xfff000)|value<<12)
}
func (o *ISP_Type) GetFRAME_CFG_HADR_NUM() uint32 {
	return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0xfff000) >> 12
}
func (o *ISP_Type) SetFRAME_CFG_BAYER_MODE(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x18000000)|value<<27)
}
func (o *ISP_Type) GetFRAME_CFG_BAYER_MODE() uint32 {
	return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x18000000) >> 27
}
func (o *ISP_Type) SetFRAME_CFG_HSYNC_START_EXIST(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x20000000)|value<<29)
}
func (o *ISP_Type) GetFRAME_CFG_HSYNC_START_EXIST() uint32 {
	return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x20000000) >> 29
}
func (o *ISP_Type) SetFRAME_CFG_HSYNC_END_EXIST(value uint32) {
	volatile.StoreUint32(&o.FRAME_CFG.Reg, volatile.LoadUint32(&o.FRAME_CFG.Reg)&^(0x40000000)|value<<30)
}
func (o *ISP_Type) GetFRAME_CFG_HSYNC_END_EXIST() uint32 {
	return (volatile.LoadUint32(&o.FRAME_CFG.Reg) & 0x40000000) >> 30
}

// ISP.CCM_COEF0: ccm coef register 0
func (o *ISP_Type) SetCCM_COEF0_CCM_RR(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF0.Reg, volatile.LoadUint32(&o.CCM_COEF0.Reg)&^(0x1fff)|value)
}
func (o *ISP_Type) GetCCM_COEF0_CCM_RR() uint32 {
	return volatile.LoadUint32(&o.CCM_COEF0.Reg) & 0x1fff
}
func (o *ISP_Type) SetCCM_COEF0_CCM_RG(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF0.Reg, volatile.LoadUint32(&o.CCM_COEF0.Reg)&^(0x3ffe000)|value<<13)
}
func (o *ISP_Type) GetCCM_COEF0_CCM_RG() uint32 {
	return (volatile.LoadUint32(&o.CCM_COEF0.Reg) & 0x3ffe000) >> 13
}

// ISP.CCM_COEF1: ccm coef register 1
func (o *ISP_Type) SetCCM_COEF1_CCM_RB(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF1.Reg, volatile.LoadUint32(&o.CCM_COEF1.Reg)&^(0x1fff)|value)
}
func (o *ISP_Type) GetCCM_COEF1_CCM_RB() uint32 {
	return volatile.LoadUint32(&o.CCM_COEF1.Reg) & 0x1fff
}
func (o *ISP_Type) SetCCM_COEF1_CCM_GR(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF1.Reg, volatile.LoadUint32(&o.CCM_COEF1.Reg)&^(0x3ffe000)|value<<13)
}
func (o *ISP_Type) GetCCM_COEF1_CCM_GR() uint32 {
	return (volatile.LoadUint32(&o.CCM_COEF1.Reg) & 0x3ffe000) >> 13
}

// ISP.CCM_COEF3: ccm coef register 3
func (o *ISP_Type) SetCCM_COEF3_CCM_GG(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF3.Reg, volatile.LoadUint32(&o.CCM_COEF3.Reg)&^(0x1fff)|value)
}
func (o *ISP_Type) GetCCM_COEF3_CCM_GG() uint32 {
	return volatile.LoadUint32(&o.CCM_COEF3.Reg) & 0x1fff
}
func (o *ISP_Type) SetCCM_COEF3_CCM_GB(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF3.Reg, volatile.LoadUint32(&o.CCM_COEF3.Reg)&^(0x3ffe000)|value<<13)
}
func (o *ISP_Type) GetCCM_COEF3_CCM_GB() uint32 {
	return (volatile.LoadUint32(&o.CCM_COEF3.Reg) & 0x3ffe000) >> 13
}

// ISP.CCM_COEF4: ccm coef register 4
func (o *ISP_Type) SetCCM_COEF4_CCM_BR(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF4.Reg, volatile.LoadUint32(&o.CCM_COEF4.Reg)&^(0x1fff)|value)
}
func (o *ISP_Type) GetCCM_COEF4_CCM_BR() uint32 {
	return volatile.LoadUint32(&o.CCM_COEF4.Reg) & 0x1fff
}
func (o *ISP_Type) SetCCM_COEF4_CCM_BG(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF4.Reg, volatile.LoadUint32(&o.CCM_COEF4.Reg)&^(0x3ffe000)|value<<13)
}
func (o *ISP_Type) GetCCM_COEF4_CCM_BG() uint32 {
	return (volatile.LoadUint32(&o.CCM_COEF4.Reg) & 0x3ffe000) >> 13
}

// ISP.CCM_COEF5: ccm coef register 5
func (o *ISP_Type) SetCCM_COEF5_CCM_BB(value uint32) {
	volatile.StoreUint32(&o.CCM_COEF5.Reg, volatile.LoadUint32(&o.CCM_COEF5.Reg)&^(0x1fff)|value)
}
func (o *ISP_Type) GetCCM_COEF5_CCM_BB() uint32 {
	return volatile.LoadUint32(&o.CCM_COEF5.Reg) & 0x1fff
}

// ISP.BF_MATRIX_CTRL: bf pix2matrix ctrl
func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TL(value uint32) {
	volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TL() uint32 {
	return volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0xff
}
func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TH(value uint32) {
	volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TH() uint32 {
	return (volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_PADDING_DATA(value uint32) {
	volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_PADDING_DATA() uint32 {
	return (volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetBF_MATRIX_CTRL_BF_PADDING_MODE(value uint32) {
	volatile.StoreUint32(&o.BF_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetBF_MATRIX_CTRL_BF_PADDING_MODE() uint32 {
	return (volatile.LoadUint32(&o.BF_MATRIX_CTRL.Reg) & 0x1000000) >> 24
}

// ISP.BF_SIGMA: bf denoising level control register
func (o *ISP_Type) SetBF_SIGMA_SIGMA(value uint32) {
	volatile.StoreUint32(&o.BF_SIGMA.Reg, volatile.LoadUint32(&o.BF_SIGMA.Reg)&^(0x3f)|value)
}
func (o *ISP_Type) GetBF_SIGMA_SIGMA() uint32 {
	return volatile.LoadUint32(&o.BF_SIGMA.Reg) & 0x3f
}

// ISP.BF_GAU0: bf gau template register 0
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE21(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf)|value)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE21() uint32 {
	return volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf
}
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE20(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf0)|value<<4)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE20() uint32 {
	return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf0) >> 4
}
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE12(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf00)|value<<8)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE12() uint32 {
	return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf00) >> 8
}
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE11(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf000)|value<<12)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE11() uint32 {
	return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf000) >> 12
}
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE10(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf0000)|value<<16)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE10() uint32 {
	return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf0000) >> 16
}
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE02(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf00000)|value<<20)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE02() uint32 {
	return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf00000) >> 20
}
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE01(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf000000)|value<<24)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE01() uint32 {
	return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf000000) >> 24
}
func (o *ISP_Type) SetBF_GAU0_GAU_TEMPLATE00(value uint32) {
	volatile.StoreUint32(&o.BF_GAU0.Reg, volatile.LoadUint32(&o.BF_GAU0.Reg)&^(0xf0000000)|value<<28)
}
func (o *ISP_Type) GetBF_GAU0_GAU_TEMPLATE00() uint32 {
	return (volatile.LoadUint32(&o.BF_GAU0.Reg) & 0xf0000000) >> 28
}

// ISP.BF_GAU1: bf gau template register 1
func (o *ISP_Type) SetBF_GAU1_GAU_TEMPLATE22(value uint32) {
	volatile.StoreUint32(&o.BF_GAU1.Reg, volatile.LoadUint32(&o.BF_GAU1.Reg)&^(0xf)|value)
}
func (o *ISP_Type) GetBF_GAU1_GAU_TEMPLATE22() uint32 {
	return volatile.LoadUint32(&o.BF_GAU1.Reg) & 0xf
}

// ISP.DPC_CTRL: DPC mode control register
func (o *ISP_Type) SetDPC_CTRL_DPC_CHECK_EN(value uint32) {
	volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetDPC_CTRL_DPC_CHECK_EN() uint32 {
	return volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x1
}
func (o *ISP_Type) SetDPC_CTRL_STA_EN(value uint32) {
	volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetDPC_CTRL_STA_EN() uint32 {
	return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetDPC_CTRL_DYN_EN(value uint32) {
	volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetDPC_CTRL_DYN_EN() uint32 {
	return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetDPC_CTRL_DPC_BLACK_EN(value uint32) {
	volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetDPC_CTRL_DPC_BLACK_EN() uint32 {
	return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x8) >> 3
}
func (o *ISP_Type) SetDPC_CTRL_DPC_METHOD_SEL(value uint32) {
	volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetDPC_CTRL_DPC_METHOD_SEL() uint32 {
	return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetDPC_CTRL_DPC_CHECK_OD_EN(value uint32) {
	volatile.StoreUint32(&o.DPC_CTRL.Reg, volatile.LoadUint32(&o.DPC_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *ISP_Type) GetDPC_CTRL_DPC_CHECK_OD_EN() uint32 {
	return (volatile.LoadUint32(&o.DPC_CTRL.Reg) & 0x20) >> 5
}

// ISP.DPC_CONF: DPC parameter config register
func (o *ISP_Type) SetDPC_CONF_DPC_THRESHOLD_L(value uint32) {
	volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetDPC_CONF_DPC_THRESHOLD_L() uint32 {
	return volatile.LoadUint32(&o.DPC_CONF.Reg) & 0xff
}
func (o *ISP_Type) SetDPC_CONF_DPC_THRESHOLD_H(value uint32) {
	volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetDPC_CONF_DPC_THRESHOLD_H() uint32 {
	return (volatile.LoadUint32(&o.DPC_CONF.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetDPC_CONF_DPC_FACTOR_DARK(value uint32) {
	volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0x3f0000)|value<<16)
}
func (o *ISP_Type) GetDPC_CONF_DPC_FACTOR_DARK() uint32 {
	return (volatile.LoadUint32(&o.DPC_CONF.Reg) & 0x3f0000) >> 16
}
func (o *ISP_Type) SetDPC_CONF_DPC_FACTOR_BRIG(value uint32) {
	volatile.StoreUint32(&o.DPC_CONF.Reg, volatile.LoadUint32(&o.DPC_CONF.Reg)&^(0xfc00000)|value<<22)
}
func (o *ISP_Type) GetDPC_CONF_DPC_FACTOR_BRIG() uint32 {
	return (volatile.LoadUint32(&o.DPC_CONF.Reg) & 0xfc00000) >> 22
}

// ISP.DPC_MATRIX_CTRL: dpc pix2matrix ctrl
func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TL(value uint32) {
	volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TL() uint32 {
	return volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0xff
}
func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TH(value uint32) {
	volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TH() uint32 {
	return (volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_PADDING_DATA(value uint32) {
	volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_PADDING_DATA() uint32 {
	return (volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetDPC_MATRIX_CTRL_DPC_PADDING_MODE(value uint32) {
	volatile.StoreUint32(&o.DPC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetDPC_MATRIX_CTRL_DPC_PADDING_MODE() uint32 {
	return (volatile.LoadUint32(&o.DPC_MATRIX_CTRL.Reg) & 0x1000000) >> 24
}

// ISP.DPC_DEADPIX_CNT: DPC dead-pix number register
func (o *ISP_Type) SetDPC_DEADPIX_CNT(value uint32) {
	volatile.StoreUint32(&o.DPC_DEADPIX_CNT.Reg, volatile.LoadUint32(&o.DPC_DEADPIX_CNT.Reg)&^(0x3ff)|value)
}
func (o *ISP_Type) GetDPC_DEADPIX_CNT() uint32 {
	return volatile.LoadUint32(&o.DPC_DEADPIX_CNT.Reg) & 0x3ff
}

// ISP.LUT_CMD: LUT command register
func (o *ISP_Type) SetLUT_CMD_LUT_ADDR(value uint32) {
	volatile.StoreUint32(&o.LUT_CMD.Reg, volatile.LoadUint32(&o.LUT_CMD.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetLUT_CMD_LUT_ADDR() uint32 {
	return volatile.LoadUint32(&o.LUT_CMD.Reg) & 0xfff
}
func (o *ISP_Type) SetLUT_CMD_LUT_NUM(value uint32) {
	volatile.StoreUint32(&o.LUT_CMD.Reg, volatile.LoadUint32(&o.LUT_CMD.Reg)&^(0xf000)|value<<12)
}
func (o *ISP_Type) GetLUT_CMD_LUT_NUM() uint32 {
	return (volatile.LoadUint32(&o.LUT_CMD.Reg) & 0xf000) >> 12
}
func (o *ISP_Type) SetLUT_CMD(value uint32) {
	volatile.StoreUint32(&o.LUT_CMD.Reg, volatile.LoadUint32(&o.LUT_CMD.Reg)&^(0x10000)|value<<16)
}
func (o *ISP_Type) GetLUT_CMD() uint32 {
	return (volatile.LoadUint32(&o.LUT_CMD.Reg) & 0x10000) >> 16
}

// ISP.LUT_WDATA: LUT write data register
func (o *ISP_Type) SetLUT_WDATA(value uint32) {
	volatile.StoreUint32(&o.LUT_WDATA.Reg, value)
}
func (o *ISP_Type) GetLUT_WDATA() uint32 {
	return volatile.LoadUint32(&o.LUT_WDATA.Reg)
}

// ISP.LUT_RDATA: LUT read data register
func (o *ISP_Type) SetLUT_RDATA(value uint32) {
	volatile.StoreUint32(&o.LUT_RDATA.Reg, value)
}
func (o *ISP_Type) GetLUT_RDATA() uint32 {
	return volatile.LoadUint32(&o.LUT_RDATA.Reg)
}

// ISP.LSC_TABLESIZE: LSC point in x-direction
func (o *ISP_Type) SetLSC_TABLESIZE_LSC_XTABLESIZE(value uint32) {
	volatile.StoreUint32(&o.LSC_TABLESIZE.Reg, volatile.LoadUint32(&o.LSC_TABLESIZE.Reg)&^(0x1f)|value)
}
func (o *ISP_Type) GetLSC_TABLESIZE_LSC_XTABLESIZE() uint32 {
	return volatile.LoadUint32(&o.LSC_TABLESIZE.Reg) & 0x1f
}

// ISP.DEMOSAIC_MATRIX_CTRL: demosaic pix2matrix ctrl
func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TL(value uint32) {
	volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TL() uint32 {
	return volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0xff
}
func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TH(value uint32) {
	volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TH() uint32 {
	return (volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_DATA(value uint32) {
	volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_DATA() uint32 {
	return (volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_MODE(value uint32) {
	volatile.StoreUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetDEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_MODE() uint32 {
	return (volatile.LoadUint32(&o.DEMOSAIC_MATRIX_CTRL.Reg) & 0x1000000) >> 24
}

// ISP.DEMOSAIC_GRAD_RATIO: demosaic gradient select ratio
func (o *ISP_Type) SetDEMOSAIC_GRAD_RATIO(value uint32) {
	volatile.StoreUint32(&o.DEMOSAIC_GRAD_RATIO.Reg, volatile.LoadUint32(&o.DEMOSAIC_GRAD_RATIO.Reg)&^(0x3f)|value)
}
func (o *ISP_Type) GetDEMOSAIC_GRAD_RATIO() uint32 {
	return volatile.LoadUint32(&o.DEMOSAIC_GRAD_RATIO.Reg) & 0x3f
}

// ISP.MEDIAN_MATRIX_CTRL: median pix2matrix ctrl
func (o *ISP_Type) SetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_DATA(value uint32) {
	volatile.StoreUint32(&o.MEDIAN_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_DATA() uint32 {
	return volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg) & 0xff
}
func (o *ISP_Type) SetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_MODE(value uint32) {
	volatile.StoreUint32(&o.MEDIAN_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetMEDIAN_MATRIX_CTRL_MEDIAN_PADDING_MODE() uint32 {
	return (volatile.LoadUint32(&o.MEDIAN_MATRIX_CTRL.Reg) & 0x100) >> 8
}

// ISP.INT_RAW: raw interrupt register
func (o *ISP_Type) SetINT_RAW_ISP_DATA_TYPE_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetINT_RAW_ISP_DATA_TYPE_ERR_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *ISP_Type) SetINT_RAW_ISP_ASYNC_FIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetINT_RAW_ISP_ASYNC_FIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetINT_RAW_ISP_BUF_FULL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetINT_RAW_ISP_BUF_FULL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetINT_RAW_ISP_HVNUM_SETTING_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetINT_RAW_ISP_HVNUM_SETTING_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *ISP_Type) SetINT_RAW_ISP_DATA_TYPE_SETTING_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetINT_RAW_ISP_DATA_TYPE_SETTING_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetINT_RAW_ISP_MIPI_HNUM_UNMATCH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *ISP_Type) GetINT_RAW_ISP_MIPI_HNUM_UNMATCH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *ISP_Type) SetINT_RAW_DPC_CHECK_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *ISP_Type) GetINT_RAW_DPC_CHECK_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *ISP_Type) SetINT_RAW_GAMMA_XCOORD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *ISP_Type) GetINT_RAW_GAMMA_XCOORD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *ISP_Type) SetINT_RAW_AE_MONITOR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetINT_RAW_AE_MONITOR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *ISP_Type) SetINT_RAW_AE_FRAME_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *ISP_Type) GetINT_RAW_AE_FRAME_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *ISP_Type) SetINT_RAW_AF_FDONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *ISP_Type) GetINT_RAW_AF_FDONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *ISP_Type) SetINT_RAW_AF_ENV_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *ISP_Type) GetINT_RAW_AF_ENV_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *ISP_Type) SetINT_RAW_AWB_FDONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *ISP_Type) GetINT_RAW_AWB_FDONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *ISP_Type) SetINT_RAW_HIST_FDONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *ISP_Type) GetINT_RAW_HIST_FDONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *ISP_Type) SetINT_RAW_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *ISP_Type) GetINT_RAW_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *ISP_Type) SetINT_RAW_BLC_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *ISP_Type) GetINT_RAW_BLC_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *ISP_Type) SetINT_RAW_LSC_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *ISP_Type) GetINT_RAW_LSC_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *ISP_Type) SetINT_RAW_DPC_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *ISP_Type) GetINT_RAW_DPC_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *ISP_Type) SetINT_RAW_BF_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *ISP_Type) GetINT_RAW_BF_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *ISP_Type) SetINT_RAW_DEMOSAIC_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *ISP_Type) GetINT_RAW_DEMOSAIC_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}
func (o *ISP_Type) SetINT_RAW_MEDIAN_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *ISP_Type) GetINT_RAW_MEDIAN_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20
}
func (o *ISP_Type) SetINT_RAW_CCM_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21)
}
func (o *ISP_Type) GetINT_RAW_CCM_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21
}
func (o *ISP_Type) SetINT_RAW_GAMMA_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22)
}
func (o *ISP_Type) GetINT_RAW_GAMMA_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22
}
func (o *ISP_Type) SetINT_RAW_RGB2YUV_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23)
}
func (o *ISP_Type) GetINT_RAW_RGB2YUV_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23
}
func (o *ISP_Type) SetINT_RAW_SHARP_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetINT_RAW_SHARP_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24
}
func (o *ISP_Type) SetINT_RAW_COLOR_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25)
}
func (o *ISP_Type) GetINT_RAW_COLOR_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25
}
func (o *ISP_Type) SetINT_RAW_YUV2RGB_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26)
}
func (o *ISP_Type) GetINT_RAW_YUV2RGB_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26
}
func (o *ISP_Type) SetINT_RAW_TAIL_IDI_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27)
}
func (o *ISP_Type) GetINT_RAW_TAIL_IDI_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27
}
func (o *ISP_Type) SetINT_RAW_HEADER_IDI_FRAME_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *ISP_Type) GetINT_RAW_HEADER_IDI_FRAME_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28
}

// ISP.INT_ST: masked interrupt register
func (o *ISP_Type) SetINT_ST_ISP_DATA_TYPE_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetINT_ST_ISP_DATA_TYPE_ERR_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *ISP_Type) SetINT_ST_ISP_ASYNC_FIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetINT_ST_ISP_ASYNC_FIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetINT_ST_ISP_BUF_FULL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetINT_ST_ISP_BUF_FULL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetINT_ST_ISP_HVNUM_SETTING_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetINT_ST_ISP_HVNUM_SETTING_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *ISP_Type) SetINT_ST_ISP_DATA_TYPE_SETTING_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetINT_ST_ISP_DATA_TYPE_SETTING_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetINT_ST_ISP_MIPI_HNUM_UNMATCH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *ISP_Type) GetINT_ST_ISP_MIPI_HNUM_UNMATCH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *ISP_Type) SetINT_ST_DPC_CHECK_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *ISP_Type) GetINT_ST_DPC_CHECK_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *ISP_Type) SetINT_ST_GAMMA_XCOORD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *ISP_Type) GetINT_ST_GAMMA_XCOORD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *ISP_Type) SetINT_ST_AE_MONITOR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetINT_ST_AE_MONITOR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *ISP_Type) SetINT_ST_AE_FRAME_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *ISP_Type) GetINT_ST_AE_FRAME_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *ISP_Type) SetINT_ST_AF_FDONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *ISP_Type) GetINT_ST_AF_FDONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *ISP_Type) SetINT_ST_AF_ENV_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *ISP_Type) GetINT_ST_AF_ENV_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *ISP_Type) SetINT_ST_AWB_FDONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *ISP_Type) GetINT_ST_AWB_FDONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *ISP_Type) SetINT_ST_HIST_FDONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *ISP_Type) GetINT_ST_HIST_FDONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *ISP_Type) SetINT_ST_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *ISP_Type) GetINT_ST_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *ISP_Type) SetINT_ST_BLC_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *ISP_Type) GetINT_ST_BLC_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}
func (o *ISP_Type) SetINT_ST_LSC_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *ISP_Type) GetINT_ST_LSC_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16
}
func (o *ISP_Type) SetINT_ST_DPC_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *ISP_Type) GetINT_ST_DPC_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17
}
func (o *ISP_Type) SetINT_ST_BF_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *ISP_Type) GetINT_ST_BF_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18
}
func (o *ISP_Type) SetINT_ST_DEMOSAIC_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *ISP_Type) GetINT_ST_DEMOSAIC_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19
}
func (o *ISP_Type) SetINT_ST_MEDIAN_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *ISP_Type) GetINT_ST_MEDIAN_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20
}
func (o *ISP_Type) SetINT_ST_CCM_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21)
}
func (o *ISP_Type) GetINT_ST_CCM_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21
}
func (o *ISP_Type) SetINT_ST_GAMMA_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22)
}
func (o *ISP_Type) GetINT_ST_GAMMA_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22
}
func (o *ISP_Type) SetINT_ST_RGB2YUV_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23)
}
func (o *ISP_Type) GetINT_ST_RGB2YUV_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23
}
func (o *ISP_Type) SetINT_ST_SHARP_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetINT_ST_SHARP_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24
}
func (o *ISP_Type) SetINT_ST_COLOR_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25)
}
func (o *ISP_Type) GetINT_ST_COLOR_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25
}
func (o *ISP_Type) SetINT_ST_YUV2RGB_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26)
}
func (o *ISP_Type) GetINT_ST_YUV2RGB_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26
}
func (o *ISP_Type) SetINT_ST_TAIL_IDI_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27)
}
func (o *ISP_Type) GetINT_ST_TAIL_IDI_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27
}
func (o *ISP_Type) SetINT_ST_HEADER_IDI_FRAME_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *ISP_Type) GetINT_ST_HEADER_IDI_FRAME_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28
}

// ISP.INT_ENA: interrupt enable register
func (o *ISP_Type) SetINT_ENA_ISP_DATA_TYPE_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetINT_ENA_ISP_DATA_TYPE_ERR_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *ISP_Type) SetINT_ENA_ISP_ASYNC_FIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetINT_ENA_ISP_ASYNC_FIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetINT_ENA_ISP_BUF_FULL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetINT_ENA_ISP_BUF_FULL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetINT_ENA_ISP_HVNUM_SETTING_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetINT_ENA_ISP_HVNUM_SETTING_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *ISP_Type) SetINT_ENA_ISP_DATA_TYPE_SETTING_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetINT_ENA_ISP_DATA_TYPE_SETTING_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetINT_ENA_ISP_MIPI_HNUM_UNMATCH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *ISP_Type) GetINT_ENA_ISP_MIPI_HNUM_UNMATCH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *ISP_Type) SetINT_ENA_DPC_CHECK_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *ISP_Type) GetINT_ENA_DPC_CHECK_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *ISP_Type) SetINT_ENA_GAMMA_XCOORD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *ISP_Type) GetINT_ENA_GAMMA_XCOORD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *ISP_Type) SetINT_ENA_AE_MONITOR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetINT_ENA_AE_MONITOR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *ISP_Type) SetINT_ENA_AE_FRAME_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *ISP_Type) GetINT_ENA_AE_FRAME_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *ISP_Type) SetINT_ENA_AF_FDONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *ISP_Type) GetINT_ENA_AF_FDONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *ISP_Type) SetINT_ENA_AF_ENV_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *ISP_Type) GetINT_ENA_AF_ENV_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *ISP_Type) SetINT_ENA_AWB_FDONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *ISP_Type) GetINT_ENA_AWB_FDONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *ISP_Type) SetINT_ENA_HIST_FDONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *ISP_Type) GetINT_ENA_HIST_FDONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *ISP_Type) SetINT_ENA_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *ISP_Type) GetINT_ENA_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *ISP_Type) SetINT_ENA_BLC_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *ISP_Type) GetINT_ENA_BLC_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}
func (o *ISP_Type) SetINT_ENA_LSC_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *ISP_Type) GetINT_ENA_LSC_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16
}
func (o *ISP_Type) SetINT_ENA_DPC_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *ISP_Type) GetINT_ENA_DPC_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17
}
func (o *ISP_Type) SetINT_ENA_BF_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *ISP_Type) GetINT_ENA_BF_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}
func (o *ISP_Type) SetINT_ENA_DEMOSAIC_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *ISP_Type) GetINT_ENA_DEMOSAIC_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19
}
func (o *ISP_Type) SetINT_ENA_MEDIAN_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *ISP_Type) GetINT_ENA_MEDIAN_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20
}
func (o *ISP_Type) SetINT_ENA_CCM_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21)
}
func (o *ISP_Type) GetINT_ENA_CCM_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21
}
func (o *ISP_Type) SetINT_ENA_GAMMA_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22)
}
func (o *ISP_Type) GetINT_ENA_GAMMA_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22
}
func (o *ISP_Type) SetINT_ENA_RGB2YUV_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23)
}
func (o *ISP_Type) GetINT_ENA_RGB2YUV_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23
}
func (o *ISP_Type) SetINT_ENA_SHARP_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetINT_ENA_SHARP_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24
}
func (o *ISP_Type) SetINT_ENA_COLOR_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25)
}
func (o *ISP_Type) GetINT_ENA_COLOR_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25
}
func (o *ISP_Type) SetINT_ENA_YUV2RGB_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26)
}
func (o *ISP_Type) GetINT_ENA_YUV2RGB_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26
}
func (o *ISP_Type) SetINT_ENA_TAIL_IDI_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27)
}
func (o *ISP_Type) GetINT_ENA_TAIL_IDI_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27
}
func (o *ISP_Type) SetINT_ENA_HEADER_IDI_FRAME_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *ISP_Type) GetINT_ENA_HEADER_IDI_FRAME_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28
}

// ISP.INT_CLR: interrupt clear register
func (o *ISP_Type) SetINT_CLR_ISP_DATA_TYPE_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetINT_CLR_ISP_DATA_TYPE_ERR_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *ISP_Type) SetINT_CLR_ISP_ASYNC_FIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetINT_CLR_ISP_ASYNC_FIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetINT_CLR_ISP_BUF_FULL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetINT_CLR_ISP_BUF_FULL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetINT_CLR_ISP_HVNUM_SETTING_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetINT_CLR_ISP_HVNUM_SETTING_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *ISP_Type) SetINT_CLR_ISP_DATA_TYPE_SETTING_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetINT_CLR_ISP_DATA_TYPE_SETTING_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetINT_CLR_ISP_MIPI_HNUM_UNMATCH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *ISP_Type) GetINT_CLR_ISP_MIPI_HNUM_UNMATCH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *ISP_Type) SetINT_CLR_DPC_CHECK_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *ISP_Type) GetINT_CLR_DPC_CHECK_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *ISP_Type) SetINT_CLR_GAMMA_XCOORD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *ISP_Type) GetINT_CLR_GAMMA_XCOORD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *ISP_Type) SetINT_CLR_AE_MONITOR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetINT_CLR_AE_MONITOR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *ISP_Type) SetINT_CLR_AE_FRAME_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *ISP_Type) GetINT_CLR_AE_FRAME_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *ISP_Type) SetINT_CLR_AF_FDONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *ISP_Type) GetINT_CLR_AF_FDONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *ISP_Type) SetINT_CLR_AF_ENV_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *ISP_Type) GetINT_CLR_AF_ENV_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *ISP_Type) SetINT_CLR_AWB_FDONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *ISP_Type) GetINT_CLR_AWB_FDONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *ISP_Type) SetINT_CLR_HIST_FDONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *ISP_Type) GetINT_CLR_HIST_FDONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *ISP_Type) SetINT_CLR_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *ISP_Type) GetINT_CLR_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *ISP_Type) SetINT_CLR_BLC_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *ISP_Type) GetINT_CLR_BLC_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}
func (o *ISP_Type) SetINT_CLR_LSC_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *ISP_Type) GetINT_CLR_LSC_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16
}
func (o *ISP_Type) SetINT_CLR_DPC_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *ISP_Type) GetINT_CLR_DPC_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17
}
func (o *ISP_Type) SetINT_CLR_BF_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *ISP_Type) GetINT_CLR_BF_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}
func (o *ISP_Type) SetINT_CLR_DEMOSAIC_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *ISP_Type) GetINT_CLR_DEMOSAIC_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19
}
func (o *ISP_Type) SetINT_CLR_MEDIAN_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *ISP_Type) GetINT_CLR_MEDIAN_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20
}
func (o *ISP_Type) SetINT_CLR_CCM_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *ISP_Type) GetINT_CLR_CCM_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21
}
func (o *ISP_Type) SetINT_CLR_GAMMA_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *ISP_Type) GetINT_CLR_GAMMA_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22
}
func (o *ISP_Type) SetINT_CLR_RGB2YUV_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *ISP_Type) GetINT_CLR_RGB2YUV_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23
}
func (o *ISP_Type) SetINT_CLR_SHARP_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetINT_CLR_SHARP_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24
}
func (o *ISP_Type) SetINT_CLR_COLOR_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *ISP_Type) GetINT_CLR_COLOR_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25
}
func (o *ISP_Type) SetINT_CLR_YUV2RGB_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *ISP_Type) GetINT_CLR_YUV2RGB_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26
}
func (o *ISP_Type) SetINT_CLR_TAIL_IDI_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *ISP_Type) GetINT_CLR_TAIL_IDI_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27
}
func (o *ISP_Type) SetINT_CLR_HEADER_IDI_FRAME_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *ISP_Type) GetINT_CLR_HEADER_IDI_FRAME_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28
}

// ISP.GAMMA_CTRL: gamma control register
func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_UPDATE(value uint32) {
	volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_UPDATE() uint32 {
	return volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x1
}
func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_B_LAST_CORRECT(value uint32) {
	volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_B_LAST_CORRECT() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_G_LAST_CORRECT(value uint32) {
	volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_G_LAST_CORRECT() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetGAMMA_CTRL_GAMMA_R_LAST_CORRECT(value uint32) {
	volatile.StoreUint32(&o.GAMMA_CTRL.Reg, volatile.LoadUint32(&o.GAMMA_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetGAMMA_CTRL_GAMMA_R_LAST_CORRECT() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_CTRL.Reg) & 0x8) >> 3
}

// ISP.GAMMA_RY1: point of Y-axis of r channel gamma curve register 1
func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y03(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y03() uint32 {
	return volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y02(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y02() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y01(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y01() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_RY1_GAMMA_R_Y00(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY1.Reg, volatile.LoadUint32(&o.GAMMA_RY1.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_RY1_GAMMA_R_Y00() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY1.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_RY2: point of Y-axis of r channel gamma curve register 2
func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y07(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y07() uint32 {
	return volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y06(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y06() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y05(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y05() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_RY2_GAMMA_R_Y04(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY2.Reg, volatile.LoadUint32(&o.GAMMA_RY2.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_RY2_GAMMA_R_Y04() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY2.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_RY3: point of Y-axis of r channel gamma curve register 3
func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y0B(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y0B() uint32 {
	return volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y0A(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y0A() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y09(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y09() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_RY3_GAMMA_R_Y08(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY3.Reg, volatile.LoadUint32(&o.GAMMA_RY3.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_RY3_GAMMA_R_Y08() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY3.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_RY4: point of Y-axis of r channel gamma curve register 4
func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0F(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0F() uint32 {
	return volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0E(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0E() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0D(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0D() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_RY4_GAMMA_R_Y0C(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RY4.Reg, volatile.LoadUint32(&o.GAMMA_RY4.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_RY4_GAMMA_R_Y0C() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RY4.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_GY1: point of Y-axis of g channel gamma curve register 1
func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y03(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y03() uint32 {
	return volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y02(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y02() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y01(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y01() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_GY1_GAMMA_G_Y00(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY1.Reg, volatile.LoadUint32(&o.GAMMA_GY1.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_GY1_GAMMA_G_Y00() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY1.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_GY2: point of Y-axis of g channel gamma curve register 2
func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y07(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y07() uint32 {
	return volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y06(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y06() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y05(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y05() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_GY2_GAMMA_G_Y04(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY2.Reg, volatile.LoadUint32(&o.GAMMA_GY2.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_GY2_GAMMA_G_Y04() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY2.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_GY3: point of Y-axis of g channel gamma curve register 3
func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y0B(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y0B() uint32 {
	return volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y0A(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y0A() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y09(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y09() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_GY3_GAMMA_G_Y08(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY3.Reg, volatile.LoadUint32(&o.GAMMA_GY3.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_GY3_GAMMA_G_Y08() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY3.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_GY4: point of Y-axis of g channel gamma curve register 4
func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0F(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0F() uint32 {
	return volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0E(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0E() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0D(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0D() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_GY4_GAMMA_G_Y0C(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GY4.Reg, volatile.LoadUint32(&o.GAMMA_GY4.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_GY4_GAMMA_G_Y0C() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GY4.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_BY1: point of Y-axis of b channel gamma curve register 1
func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y03(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y03() uint32 {
	return volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y02(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y02() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y01(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y01() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_BY1_GAMMA_B_Y00(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY1.Reg, volatile.LoadUint32(&o.GAMMA_BY1.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_BY1_GAMMA_B_Y00() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY1.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_BY2: point of Y-axis of b channel gamma curve register 2
func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y07(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y07() uint32 {
	return volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y06(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y06() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y05(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y05() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_BY2_GAMMA_B_Y04(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY2.Reg, volatile.LoadUint32(&o.GAMMA_BY2.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_BY2_GAMMA_B_Y04() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY2.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_BY3: point of Y-axis of b channel gamma curve register 3
func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y0B(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y0B() uint32 {
	return volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y0A(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y0A() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y09(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y09() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_BY3_GAMMA_B_Y08(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY3.Reg, volatile.LoadUint32(&o.GAMMA_BY3.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_BY3_GAMMA_B_Y08() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY3.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_BY4: point of Y-axis of b channel gamma curve register 4
func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0F(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0F() uint32 {
	return volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff
}
func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0E(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0E() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0D(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0D() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetGAMMA_BY4_GAMMA_B_Y0C(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BY4.Reg, volatile.LoadUint32(&o.GAMMA_BY4.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetGAMMA_BY4_GAMMA_B_Y0C() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BY4.Reg) & 0xff000000) >> 24
}

// ISP.GAMMA_RX1: point of X-axis of r channel gamma curve register 1
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X07(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x7)|value)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X07() uint32 {
	return volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x7
}
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X06(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x38)|value<<3)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X06() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x38) >> 3
}
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X05(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x1c0)|value<<6)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X05() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x1c0) >> 6
}
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X04(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0xe00)|value<<9)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X04() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0xe00) >> 9
}
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X03(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x7000)|value<<12)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X03() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x7000) >> 12
}
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X02(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x38000)|value<<15)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X02() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x38000) >> 15
}
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X01(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0x1c0000)|value<<18)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X01() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0x1c0000) >> 18
}
func (o *ISP_Type) SetGAMMA_RX1_GAMMA_R_X00(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX1.Reg, volatile.LoadUint32(&o.GAMMA_RX1.Reg)&^(0xe00000)|value<<21)
}
func (o *ISP_Type) GetGAMMA_RX1_GAMMA_R_X00() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX1.Reg) & 0xe00000) >> 21
}

// ISP.GAMMA_RX2: point of X-axis of r channel gamma curve register 2
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0F(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x7)|value)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0F() uint32 {
	return volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x7
}
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0E(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x38)|value<<3)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0E() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x38) >> 3
}
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0D(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x1c0)|value<<6)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0D() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x1c0) >> 6
}
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0C(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0xe00)|value<<9)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0C() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0xe00) >> 9
}
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0B(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x7000)|value<<12)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0B() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x7000) >> 12
}
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X0A(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x38000)|value<<15)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X0A() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x38000) >> 15
}
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X09(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0x1c0000)|value<<18)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X09() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0x1c0000) >> 18
}
func (o *ISP_Type) SetGAMMA_RX2_GAMMA_R_X08(value uint32) {
	volatile.StoreUint32(&o.GAMMA_RX2.Reg, volatile.LoadUint32(&o.GAMMA_RX2.Reg)&^(0xe00000)|value<<21)
}
func (o *ISP_Type) GetGAMMA_RX2_GAMMA_R_X08() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_RX2.Reg) & 0xe00000) >> 21
}

// ISP.GAMMA_GX1: point of X-axis of g channel gamma curve register 1
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X07(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x7)|value)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X07() uint32 {
	return volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x7
}
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X06(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x38)|value<<3)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X06() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x38) >> 3
}
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X05(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x1c0)|value<<6)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X05() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x1c0) >> 6
}
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X04(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0xe00)|value<<9)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X04() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0xe00) >> 9
}
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X03(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x7000)|value<<12)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X03() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x7000) >> 12
}
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X02(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x38000)|value<<15)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X02() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x38000) >> 15
}
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X01(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0x1c0000)|value<<18)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X01() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0x1c0000) >> 18
}
func (o *ISP_Type) SetGAMMA_GX1_GAMMA_G_X00(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX1.Reg, volatile.LoadUint32(&o.GAMMA_GX1.Reg)&^(0xe00000)|value<<21)
}
func (o *ISP_Type) GetGAMMA_GX1_GAMMA_G_X00() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX1.Reg) & 0xe00000) >> 21
}

// ISP.GAMMA_GX2: point of X-axis of g channel gamma curve register 2
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0F(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x7)|value)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0F() uint32 {
	return volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x7
}
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0E(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x38)|value<<3)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0E() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x38) >> 3
}
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0D(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x1c0)|value<<6)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0D() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x1c0) >> 6
}
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0C(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0xe00)|value<<9)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0C() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0xe00) >> 9
}
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0B(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x7000)|value<<12)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0B() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x7000) >> 12
}
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X0A(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x38000)|value<<15)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X0A() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x38000) >> 15
}
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X09(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0x1c0000)|value<<18)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X09() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0x1c0000) >> 18
}
func (o *ISP_Type) SetGAMMA_GX2_GAMMA_G_X08(value uint32) {
	volatile.StoreUint32(&o.GAMMA_GX2.Reg, volatile.LoadUint32(&o.GAMMA_GX2.Reg)&^(0xe00000)|value<<21)
}
func (o *ISP_Type) GetGAMMA_GX2_GAMMA_G_X08() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_GX2.Reg) & 0xe00000) >> 21
}

// ISP.GAMMA_BX1: point of X-axis of b channel gamma curve register 1
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X07(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x7)|value)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X07() uint32 {
	return volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x7
}
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X06(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x38)|value<<3)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X06() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x38) >> 3
}
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X05(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x1c0)|value<<6)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X05() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x1c0) >> 6
}
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X04(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0xe00)|value<<9)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X04() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0xe00) >> 9
}
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X03(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x7000)|value<<12)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X03() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x7000) >> 12
}
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X02(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x38000)|value<<15)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X02() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x38000) >> 15
}
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X01(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0x1c0000)|value<<18)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X01() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0x1c0000) >> 18
}
func (o *ISP_Type) SetGAMMA_BX1_GAMMA_B_X00(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX1.Reg, volatile.LoadUint32(&o.GAMMA_BX1.Reg)&^(0xe00000)|value<<21)
}
func (o *ISP_Type) GetGAMMA_BX1_GAMMA_B_X00() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX1.Reg) & 0xe00000) >> 21
}

// ISP.GAMMA_BX2: point of X-axis of b channel gamma curve register 2
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0F(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x7)|value)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0F() uint32 {
	return volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x7
}
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0E(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x38)|value<<3)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0E() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x38) >> 3
}
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0D(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x1c0)|value<<6)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0D() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x1c0) >> 6
}
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0C(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0xe00)|value<<9)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0C() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0xe00) >> 9
}
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0B(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x7000)|value<<12)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0B() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x7000) >> 12
}
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X0A(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x38000)|value<<15)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X0A() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x38000) >> 15
}
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X09(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0x1c0000)|value<<18)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X09() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0x1c0000) >> 18
}
func (o *ISP_Type) SetGAMMA_BX2_GAMMA_B_X08(value uint32) {
	volatile.StoreUint32(&o.GAMMA_BX2.Reg, volatile.LoadUint32(&o.GAMMA_BX2.Reg)&^(0xe00000)|value<<21)
}
func (o *ISP_Type) GetGAMMA_BX2_GAMMA_B_X08() uint32 {
	return (volatile.LoadUint32(&o.GAMMA_BX2.Reg) & 0xe00000) >> 21
}

// ISP.AE_CTRL: ae control register
func (o *ISP_Type) SetAE_CTRL_AE_UPDATE(value uint32) {
	volatile.StoreUint32(&o.AE_CTRL.Reg, volatile.LoadUint32(&o.AE_CTRL.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetAE_CTRL_AE_UPDATE() uint32 {
	return volatile.LoadUint32(&o.AE_CTRL.Reg) & 0x1
}
func (o *ISP_Type) SetAE_CTRL_AE_SELECT(value uint32) {
	volatile.StoreUint32(&o.AE_CTRL.Reg, volatile.LoadUint32(&o.AE_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetAE_CTRL_AE_SELECT() uint32 {
	return (volatile.LoadUint32(&o.AE_CTRL.Reg) & 0x2) >> 1
}

// ISP.AE_MONITOR: ae monitor control register
func (o *ISP_Type) SetAE_MONITOR_TL(value uint32) {
	volatile.StoreUint32(&o.AE_MONITOR.Reg, volatile.LoadUint32(&o.AE_MONITOR.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetAE_MONITOR_TL() uint32 {
	return volatile.LoadUint32(&o.AE_MONITOR.Reg) & 0xff
}
func (o *ISP_Type) SetAE_MONITOR_TH(value uint32) {
	volatile.StoreUint32(&o.AE_MONITOR.Reg, volatile.LoadUint32(&o.AE_MONITOR.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetAE_MONITOR_TH() uint32 {
	return (volatile.LoadUint32(&o.AE_MONITOR.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetAE_MONITOR_PERIOD(value uint32) {
	volatile.StoreUint32(&o.AE_MONITOR.Reg, volatile.LoadUint32(&o.AE_MONITOR.Reg)&^(0x3f0000)|value<<16)
}
func (o *ISP_Type) GetAE_MONITOR_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.AE_MONITOR.Reg) & 0x3f0000) >> 16
}

// ISP.AE_BX: ae window register in x-direction
func (o *ISP_Type) SetAE_BX_AE_X_BSIZE(value uint32) {
	volatile.StoreUint32(&o.AE_BX.Reg, volatile.LoadUint32(&o.AE_BX.Reg)&^(0x7ff)|value)
}
func (o *ISP_Type) GetAE_BX_AE_X_BSIZE() uint32 {
	return volatile.LoadUint32(&o.AE_BX.Reg) & 0x7ff
}
func (o *ISP_Type) SetAE_BX_AE_X_START(value uint32) {
	volatile.StoreUint32(&o.AE_BX.Reg, volatile.LoadUint32(&o.AE_BX.Reg)&^(0x3ff800)|value<<11)
}
func (o *ISP_Type) GetAE_BX_AE_X_START() uint32 {
	return (volatile.LoadUint32(&o.AE_BX.Reg) & 0x3ff800) >> 11
}

// ISP.AE_BY: ae window register in y-direction
func (o *ISP_Type) SetAE_BY_AE_Y_BSIZE(value uint32) {
	volatile.StoreUint32(&o.AE_BY.Reg, volatile.LoadUint32(&o.AE_BY.Reg)&^(0x7ff)|value)
}
func (o *ISP_Type) GetAE_BY_AE_Y_BSIZE() uint32 {
	return volatile.LoadUint32(&o.AE_BY.Reg) & 0x7ff
}
func (o *ISP_Type) SetAE_BY_AE_Y_START(value uint32) {
	volatile.StoreUint32(&o.AE_BY.Reg, volatile.LoadUint32(&o.AE_BY.Reg)&^(0x3ff800)|value<<11)
}
func (o *ISP_Type) GetAE_BY_AE_Y_START() uint32 {
	return (volatile.LoadUint32(&o.AE_BY.Reg) & 0x3ff800) >> 11
}

// ISP.AE_WINPIXNUM: ae sub-window pix num register
func (o *ISP_Type) SetAE_WINPIXNUM_AE_SUBWIN_PIXNUM(value uint32) {
	volatile.StoreUint32(&o.AE_WINPIXNUM.Reg, volatile.LoadUint32(&o.AE_WINPIXNUM.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetAE_WINPIXNUM_AE_SUBWIN_PIXNUM() uint32 {
	return volatile.LoadUint32(&o.AE_WINPIXNUM.Reg) & 0x1ffff
}

// ISP.AE_WIN_RECIPROCAL: reciprocal of ae sub-window pixel number
func (o *ISP_Type) SetAE_WIN_RECIPROCAL_AE_SUBWIN_RECIP(value uint32) {
	volatile.StoreUint32(&o.AE_WIN_RECIPROCAL.Reg, volatile.LoadUint32(&o.AE_WIN_RECIPROCAL.Reg)&^(0xfffff)|value)
}
func (o *ISP_Type) GetAE_WIN_RECIPROCAL_AE_SUBWIN_RECIP() uint32 {
	return volatile.LoadUint32(&o.AE_WIN_RECIPROCAL.Reg) & 0xfffff
}

// ISP.AE_BLOCK_MEAN_0: ae statistic result register 0
func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B03_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B03_MEAN() uint32 {
	return volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B02_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B02_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B01_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B01_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_0_AE_B00_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_0.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_0_AE_B00_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_0.Reg) & 0xff000000) >> 24
}

// ISP.AE_BLOCK_MEAN_1: ae statistic result register 1
func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B12_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B12_MEAN() uint32 {
	return volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B11_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B11_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B10_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B10_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_1_AE_B04_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_1.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_1_AE_B04_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_1.Reg) & 0xff000000) >> 24
}

// ISP.AE_BLOCK_MEAN_2: ae statistic result register 2
func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B21_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B21_MEAN() uint32 {
	return volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B20_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B20_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B14_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B14_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_2_AE_B13_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_2.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_2_AE_B13_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_2.Reg) & 0xff000000) >> 24
}

// ISP.AE_BLOCK_MEAN_3: ae statistic result register 3
func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B30_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B30_MEAN() uint32 {
	return volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B24_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B24_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B23_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B23_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_3_AE_B22_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_3.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_3_AE_B22_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_3.Reg) & 0xff000000) >> 24
}

// ISP.AE_BLOCK_MEAN_4: ae statistic result register 4
func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B34_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B34_MEAN() uint32 {
	return volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B33_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B33_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B32_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B32_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_4_AE_B31_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_4.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_4_AE_B31_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_4.Reg) & 0xff000000) >> 24
}

// ISP.AE_BLOCK_MEAN_5: ae statistic result register 5
func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B43_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B43_MEAN() uint32 {
	return volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B42_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B42_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B41_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B41_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetAE_BLOCK_MEAN_5_AE_B40_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_5.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_5_AE_B40_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_5.Reg) & 0xff000000) >> 24
}

// ISP.AE_BLOCK_MEAN_6: ae statistic result register 6
func (o *ISP_Type) SetAE_BLOCK_MEAN_6_AE_B44_MEAN(value uint32) {
	volatile.StoreUint32(&o.AE_BLOCK_MEAN_6.Reg, volatile.LoadUint32(&o.AE_BLOCK_MEAN_6.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetAE_BLOCK_MEAN_6_AE_B44_MEAN() uint32 {
	return (volatile.LoadUint32(&o.AE_BLOCK_MEAN_6.Reg) & 0xff000000) >> 24
}

// ISP.SHARP_CTRL0: sharp control register 0
func (o *ISP_Type) SetSHARP_CTRL0_SHARP_THRESHOLD_LOW(value uint32) {
	volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetSHARP_CTRL0_SHARP_THRESHOLD_LOW() uint32 {
	return volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff
}
func (o *ISP_Type) SetSHARP_CTRL0_SHARP_THRESHOLD_HIGH(value uint32) {
	volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetSHARP_CTRL0_SHARP_THRESHOLD_HIGH() uint32 {
	return (volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetSHARP_CTRL0_SHARP_AMOUNT_LOW(value uint32) {
	volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetSHARP_CTRL0_SHARP_AMOUNT_LOW() uint32 {
	return (volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetSHARP_CTRL0_SHARP_AMOUNT_HIGH(value uint32) {
	volatile.StoreUint32(&o.SHARP_CTRL0.Reg, volatile.LoadUint32(&o.SHARP_CTRL0.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetSHARP_CTRL0_SHARP_AMOUNT_HIGH() uint32 {
	return (volatile.LoadUint32(&o.SHARP_CTRL0.Reg) & 0xff000000) >> 24
}

// ISP.SHARP_FILTER0: sharp usm config register 0
func (o *ISP_Type) SetSHARP_FILTER0_SHARP_FILTER_COE00(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER0.Reg, volatile.LoadUint32(&o.SHARP_FILTER0.Reg)&^(0x1f)|value)
}
func (o *ISP_Type) GetSHARP_FILTER0_SHARP_FILTER_COE00() uint32 {
	return volatile.LoadUint32(&o.SHARP_FILTER0.Reg) & 0x1f
}
func (o *ISP_Type) SetSHARP_FILTER0_SHARP_FILTER_COE01(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER0.Reg, volatile.LoadUint32(&o.SHARP_FILTER0.Reg)&^(0x3e0)|value<<5)
}
func (o *ISP_Type) GetSHARP_FILTER0_SHARP_FILTER_COE01() uint32 {
	return (volatile.LoadUint32(&o.SHARP_FILTER0.Reg) & 0x3e0) >> 5
}
func (o *ISP_Type) SetSHARP_FILTER0_SHARP_FILTER_COE02(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER0.Reg, volatile.LoadUint32(&o.SHARP_FILTER0.Reg)&^(0x7c00)|value<<10)
}
func (o *ISP_Type) GetSHARP_FILTER0_SHARP_FILTER_COE02() uint32 {
	return (volatile.LoadUint32(&o.SHARP_FILTER0.Reg) & 0x7c00) >> 10
}

// ISP.SHARP_FILTER1: sharp usm config register 1
func (o *ISP_Type) SetSHARP_FILTER1_SHARP_FILTER_COE10(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER1.Reg, volatile.LoadUint32(&o.SHARP_FILTER1.Reg)&^(0x1f)|value)
}
func (o *ISP_Type) GetSHARP_FILTER1_SHARP_FILTER_COE10() uint32 {
	return volatile.LoadUint32(&o.SHARP_FILTER1.Reg) & 0x1f
}
func (o *ISP_Type) SetSHARP_FILTER1_SHARP_FILTER_COE11(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER1.Reg, volatile.LoadUint32(&o.SHARP_FILTER1.Reg)&^(0x3e0)|value<<5)
}
func (o *ISP_Type) GetSHARP_FILTER1_SHARP_FILTER_COE11() uint32 {
	return (volatile.LoadUint32(&o.SHARP_FILTER1.Reg) & 0x3e0) >> 5
}
func (o *ISP_Type) SetSHARP_FILTER1_SHARP_FILTER_COE12(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER1.Reg, volatile.LoadUint32(&o.SHARP_FILTER1.Reg)&^(0x7c00)|value<<10)
}
func (o *ISP_Type) GetSHARP_FILTER1_SHARP_FILTER_COE12() uint32 {
	return (volatile.LoadUint32(&o.SHARP_FILTER1.Reg) & 0x7c00) >> 10
}

// ISP.SHARP_FILTER2: sharp usm config register 2
func (o *ISP_Type) SetSHARP_FILTER2_SHARP_FILTER_COE20(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER2.Reg, volatile.LoadUint32(&o.SHARP_FILTER2.Reg)&^(0x1f)|value)
}
func (o *ISP_Type) GetSHARP_FILTER2_SHARP_FILTER_COE20() uint32 {
	return volatile.LoadUint32(&o.SHARP_FILTER2.Reg) & 0x1f
}
func (o *ISP_Type) SetSHARP_FILTER2_SHARP_FILTER_COE21(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER2.Reg, volatile.LoadUint32(&o.SHARP_FILTER2.Reg)&^(0x3e0)|value<<5)
}
func (o *ISP_Type) GetSHARP_FILTER2_SHARP_FILTER_COE21() uint32 {
	return (volatile.LoadUint32(&o.SHARP_FILTER2.Reg) & 0x3e0) >> 5
}
func (o *ISP_Type) SetSHARP_FILTER2_SHARP_FILTER_COE22(value uint32) {
	volatile.StoreUint32(&o.SHARP_FILTER2.Reg, volatile.LoadUint32(&o.SHARP_FILTER2.Reg)&^(0x7c00)|value<<10)
}
func (o *ISP_Type) GetSHARP_FILTER2_SHARP_FILTER_COE22() uint32 {
	return (volatile.LoadUint32(&o.SHARP_FILTER2.Reg) & 0x7c00) >> 10
}

// ISP.SHARP_MATRIX_CTRL: sharp pix2matrix ctrl
func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TL(value uint32) {
	volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TL() uint32 {
	return volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0xff
}
func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TH(value uint32) {
	volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TH() uint32 {
	return (volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_PADDING_DATA(value uint32) {
	volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_PADDING_DATA() uint32 {
	return (volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetSHARP_MATRIX_CTRL_SHARP_PADDING_MODE(value uint32) {
	volatile.StoreUint32(&o.SHARP_MATRIX_CTRL.Reg, volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *ISP_Type) GetSHARP_MATRIX_CTRL_SHARP_PADDING_MODE() uint32 {
	return (volatile.LoadUint32(&o.SHARP_MATRIX_CTRL.Reg) & 0x1000000) >> 24
}

// ISP.SHARP_CTRL1: sharp control register 1
func (o *ISP_Type) SetSHARP_CTRL1_SHARP_GRADIENT_MAX(value uint32) {
	volatile.StoreUint32(&o.SHARP_CTRL1.Reg, volatile.LoadUint32(&o.SHARP_CTRL1.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetSHARP_CTRL1_SHARP_GRADIENT_MAX() uint32 {
	return volatile.LoadUint32(&o.SHARP_CTRL1.Reg) & 0xff
}

// ISP.DMA_CNTL: isp dma source trans control register
func (o *ISP_Type) SetDMA_CNTL_DMA_EN(value uint32) {
	volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetDMA_CNTL_DMA_EN() uint32 {
	return volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0x1
}
func (o *ISP_Type) SetDMA_CNTL_DMA_UPDATE(value uint32) {
	volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetDMA_CNTL_DMA_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetDMA_CNTL_DMA_DATA_TYPE(value uint32) {
	volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0xfc)|value<<2)
}
func (o *ISP_Type) GetDMA_CNTL_DMA_DATA_TYPE() uint32 {
	return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0xfc) >> 2
}
func (o *ISP_Type) SetDMA_CNTL_DMA_BURST_LEN(value uint32) {
	volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0xfff00)|value<<8)
}
func (o *ISP_Type) GetDMA_CNTL_DMA_BURST_LEN() uint32 {
	return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0xfff00) >> 8
}
func (o *ISP_Type) SetDMA_CNTL_DMA_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.DMA_CNTL.Reg, volatile.LoadUint32(&o.DMA_CNTL.Reg)&^(0xfff00000)|value<<20)
}
func (o *ISP_Type) GetDMA_CNTL_DMA_INTERVAL() uint32 {
	return (volatile.LoadUint32(&o.DMA_CNTL.Reg) & 0xfff00000) >> 20
}

// ISP.DMA_RAW_DATA: isp dma source total raw number set register
func (o *ISP_Type) SetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL(value uint32) {
	volatile.StoreUint32(&o.DMA_RAW_DATA.Reg, volatile.LoadUint32(&o.DMA_RAW_DATA.Reg)&^(0x3fffff)|value)
}
func (o *ISP_Type) GetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL() uint32 {
	return volatile.LoadUint32(&o.DMA_RAW_DATA.Reg) & 0x3fffff
}
func (o *ISP_Type) SetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL_SET(value uint32) {
	volatile.StoreUint32(&o.DMA_RAW_DATA.Reg, volatile.LoadUint32(&o.DMA_RAW_DATA.Reg)&^(0x80000000)|value<<31)
}
func (o *ISP_Type) GetDMA_RAW_DATA_DMA_RAW_NUM_TOTAL_SET() uint32 {
	return (volatile.LoadUint32(&o.DMA_RAW_DATA.Reg) & 0x80000000) >> 31
}

// ISP.CAM_CNTL: isp cam source control register
func (o *ISP_Type) SetCAM_CNTL_CAM_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetCAM_CNTL_CAM_EN() uint32 {
	return volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x1
}
func (o *ISP_Type) SetCAM_CNTL_CAM_UPDATE(value uint32) {
	volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetCAM_CNTL_CAM_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetCAM_CNTL_CAM_RESET(value uint32) {
	volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetCAM_CNTL_CAM_RESET() uint32 {
	return (volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetCAM_CNTL_CAM_CLK_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CNTL.Reg, volatile.LoadUint32(&o.CAM_CNTL.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetCAM_CNTL_CAM_CLK_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CNTL.Reg) & 0x8) >> 3
}

// ISP.CAM_CONF: isp cam source config register
func (o *ISP_Type) SetCAM_CONF_CAM_DATA_ORDER(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetCAM_CONF_CAM_DATA_ORDER() uint32 {
	return volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x1
}
func (o *ISP_Type) SetCAM_CONF_CAM_2BYTE_MODE(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetCAM_CONF_CAM_2BYTE_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetCAM_CONF_CAM_DATA_TYPE(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0xfc)|value<<2)
}
func (o *ISP_Type) GetCAM_CONF_CAM_DATA_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0xfc) >> 2
}
func (o *ISP_Type) SetCAM_CONF_CAM_DE_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x100)|value<<8)
}
func (o *ISP_Type) GetCAM_CONF_CAM_DE_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x100) >> 8
}
func (o *ISP_Type) SetCAM_CONF_CAM_HSYNC_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x200)|value<<9)
}
func (o *ISP_Type) GetCAM_CONF_CAM_HSYNC_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x200) >> 9
}
func (o *ISP_Type) SetCAM_CONF_CAM_VSYNC_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x400)|value<<10)
}
func (o *ISP_Type) GetCAM_CONF_CAM_VSYNC_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x400) >> 10
}
func (o *ISP_Type) SetCAM_CONF_CAM_VSYNC_FILTER_THRES(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x3800)|value<<11)
}
func (o *ISP_Type) GetCAM_CONF_CAM_VSYNC_FILTER_THRES() uint32 {
	return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x3800) >> 11
}
func (o *ISP_Type) SetCAM_CONF_CAM_VSYNC_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CONF.Reg, volatile.LoadUint32(&o.CAM_CONF.Reg)&^(0x4000)|value<<14)
}
func (o *ISP_Type) GetCAM_CONF_CAM_VSYNC_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.CAM_CONF.Reg) & 0x4000) >> 14
}

// ISP.AF_CTRL0: af control register 0
func (o *ISP_Type) SetAF_CTRL0_AF_AUTO_UPDATE(value uint32) {
	volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetAF_CTRL0_AF_AUTO_UPDATE() uint32 {
	return volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0x1
}
func (o *ISP_Type) SetAF_CTRL0_AF_MANUAL_UPDATE(value uint32) {
	volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetAF_CTRL0_AF_MANUAL_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0x10) >> 4
}
func (o *ISP_Type) SetAF_CTRL0_AF_ENV_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0xf00)|value<<8)
}
func (o *ISP_Type) GetAF_CTRL0_AF_ENV_THRESHOLD() uint32 {
	return (volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0xf00) >> 8
}
func (o *ISP_Type) SetAF_CTRL0_AF_ENV_PERIOD(value uint32) {
	volatile.StoreUint32(&o.AF_CTRL0.Reg, volatile.LoadUint32(&o.AF_CTRL0.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetAF_CTRL0_AF_ENV_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.AF_CTRL0.Reg) & 0xff0000) >> 16
}

// ISP.AF_CTRL1: af control register 1
func (o *ISP_Type) SetAF_CTRL1_AF_THPIXNUM(value uint32) {
	volatile.StoreUint32(&o.AF_CTRL1.Reg, volatile.LoadUint32(&o.AF_CTRL1.Reg)&^(0x3fffff)|value)
}
func (o *ISP_Type) GetAF_CTRL1_AF_THPIXNUM() uint32 {
	return volatile.LoadUint32(&o.AF_CTRL1.Reg) & 0x3fffff
}

// ISP.AF_GEN_TH_CTRL: af gen threshold control register
func (o *ISP_Type) SetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MIN(value uint32) {
	volatile.StoreUint32(&o.AF_GEN_TH_CTRL.Reg, volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg)&^(0xffff)|value)
}
func (o *ISP_Type) GetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MIN() uint32 {
	return volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg) & 0xffff
}
func (o *ISP_Type) SetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MAX(value uint32) {
	volatile.StoreUint32(&o.AF_GEN_TH_CTRL.Reg, volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg)&^(0xffff0000)|value<<16)
}
func (o *ISP_Type) GetAF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MAX() uint32 {
	return (volatile.LoadUint32(&o.AF_GEN_TH_CTRL.Reg) & 0xffff0000) >> 16
}

// ISP.AF_ENV_USER_TH_SUM: af monitor user sum threshold register
func (o *ISP_Type) SetAF_ENV_USER_TH_SUM(value uint32) {
	volatile.StoreUint32(&o.AF_ENV_USER_TH_SUM.Reg, value)
}
func (o *ISP_Type) GetAF_ENV_USER_TH_SUM() uint32 {
	return volatile.LoadUint32(&o.AF_ENV_USER_TH_SUM.Reg)
}

// ISP.AF_ENV_USER_TH_LUM: af monitor user lum threshold register
func (o *ISP_Type) SetAF_ENV_USER_TH_LUM_AF_ENV_USER_THRESHOLD_LUM(value uint32) {
	volatile.StoreUint32(&o.AF_ENV_USER_TH_LUM.Reg, volatile.LoadUint32(&o.AF_ENV_USER_TH_LUM.Reg)&^(0x3fffffff)|value)
}
func (o *ISP_Type) GetAF_ENV_USER_TH_LUM_AF_ENV_USER_THRESHOLD_LUM() uint32 {
	return volatile.LoadUint32(&o.AF_ENV_USER_TH_LUM.Reg) & 0x3fffffff
}

// ISP.AF_THRESHOLD: af threshold register
func (o *ISP_Type) SetAF_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.AF_THRESHOLD.Reg, volatile.LoadUint32(&o.AF_THRESHOLD.Reg)&^(0xffff)|value)
}
func (o *ISP_Type) GetAF_THRESHOLD() uint32 {
	return volatile.LoadUint32(&o.AF_THRESHOLD.Reg) & 0xffff
}
func (o *ISP_Type) SetAF_THRESHOLD_AF_GEN_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.AF_THRESHOLD.Reg, volatile.LoadUint32(&o.AF_THRESHOLD.Reg)&^(0xffff0000)|value<<16)
}
func (o *ISP_Type) GetAF_THRESHOLD_AF_GEN_THRESHOLD() uint32 {
	return (volatile.LoadUint32(&o.AF_THRESHOLD.Reg) & 0xffff0000) >> 16
}

// ISP.AF_HSCALE_A: h-scale of af window a register
func (o *ISP_Type) SetAF_HSCALE_A_AF_RPOINT_A(value uint32) {
	volatile.StoreUint32(&o.AF_HSCALE_A.Reg, volatile.LoadUint32(&o.AF_HSCALE_A.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAF_HSCALE_A_AF_RPOINT_A() uint32 {
	return volatile.LoadUint32(&o.AF_HSCALE_A.Reg) & 0xfff
}
func (o *ISP_Type) SetAF_HSCALE_A_AF_LPOINT_A(value uint32) {
	volatile.StoreUint32(&o.AF_HSCALE_A.Reg, volatile.LoadUint32(&o.AF_HSCALE_A.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAF_HSCALE_A_AF_LPOINT_A() uint32 {
	return (volatile.LoadUint32(&o.AF_HSCALE_A.Reg) & 0xfff0000) >> 16
}

// ISP.AF_VSCALE_A: v-scale of af window a register
func (o *ISP_Type) SetAF_VSCALE_A_AF_BPOINT_A(value uint32) {
	volatile.StoreUint32(&o.AF_VSCALE_A.Reg, volatile.LoadUint32(&o.AF_VSCALE_A.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAF_VSCALE_A_AF_BPOINT_A() uint32 {
	return volatile.LoadUint32(&o.AF_VSCALE_A.Reg) & 0xfff
}
func (o *ISP_Type) SetAF_VSCALE_A_AF_TPOINT_A(value uint32) {
	volatile.StoreUint32(&o.AF_VSCALE_A.Reg, volatile.LoadUint32(&o.AF_VSCALE_A.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAF_VSCALE_A_AF_TPOINT_A() uint32 {
	return (volatile.LoadUint32(&o.AF_VSCALE_A.Reg) & 0xfff0000) >> 16
}

// ISP.AF_HSCALE_B: h-scale of af window b register
func (o *ISP_Type) SetAF_HSCALE_B_AF_RPOINT_B(value uint32) {
	volatile.StoreUint32(&o.AF_HSCALE_B.Reg, volatile.LoadUint32(&o.AF_HSCALE_B.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAF_HSCALE_B_AF_RPOINT_B() uint32 {
	return volatile.LoadUint32(&o.AF_HSCALE_B.Reg) & 0xfff
}
func (o *ISP_Type) SetAF_HSCALE_B_AF_LPOINT_B(value uint32) {
	volatile.StoreUint32(&o.AF_HSCALE_B.Reg, volatile.LoadUint32(&o.AF_HSCALE_B.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAF_HSCALE_B_AF_LPOINT_B() uint32 {
	return (volatile.LoadUint32(&o.AF_HSCALE_B.Reg) & 0xfff0000) >> 16
}

// ISP.AF_VSCALE_B: v-scale of af window b register
func (o *ISP_Type) SetAF_VSCALE_B_AF_BPOINT_B(value uint32) {
	volatile.StoreUint32(&o.AF_VSCALE_B.Reg, volatile.LoadUint32(&o.AF_VSCALE_B.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAF_VSCALE_B_AF_BPOINT_B() uint32 {
	return volatile.LoadUint32(&o.AF_VSCALE_B.Reg) & 0xfff
}
func (o *ISP_Type) SetAF_VSCALE_B_AF_TPOINT_B(value uint32) {
	volatile.StoreUint32(&o.AF_VSCALE_B.Reg, volatile.LoadUint32(&o.AF_VSCALE_B.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAF_VSCALE_B_AF_TPOINT_B() uint32 {
	return (volatile.LoadUint32(&o.AF_VSCALE_B.Reg) & 0xfff0000) >> 16
}

// ISP.AF_HSCALE_C: v-scale of af window c register
func (o *ISP_Type) SetAF_HSCALE_C_AF_RPOINT_C(value uint32) {
	volatile.StoreUint32(&o.AF_HSCALE_C.Reg, volatile.LoadUint32(&o.AF_HSCALE_C.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAF_HSCALE_C_AF_RPOINT_C() uint32 {
	return volatile.LoadUint32(&o.AF_HSCALE_C.Reg) & 0xfff
}
func (o *ISP_Type) SetAF_HSCALE_C_AF_LPOINT_C(value uint32) {
	volatile.StoreUint32(&o.AF_HSCALE_C.Reg, volatile.LoadUint32(&o.AF_HSCALE_C.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAF_HSCALE_C_AF_LPOINT_C() uint32 {
	return (volatile.LoadUint32(&o.AF_HSCALE_C.Reg) & 0xfff0000) >> 16
}

// ISP.AF_VSCALE_C: v-scale of af window c register
func (o *ISP_Type) SetAF_VSCALE_C_AF_BPOINT_C(value uint32) {
	volatile.StoreUint32(&o.AF_VSCALE_C.Reg, volatile.LoadUint32(&o.AF_VSCALE_C.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAF_VSCALE_C_AF_BPOINT_C() uint32 {
	return volatile.LoadUint32(&o.AF_VSCALE_C.Reg) & 0xfff
}
func (o *ISP_Type) SetAF_VSCALE_C_AF_TPOINT_C(value uint32) {
	volatile.StoreUint32(&o.AF_VSCALE_C.Reg, volatile.LoadUint32(&o.AF_VSCALE_C.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAF_VSCALE_C_AF_TPOINT_C() uint32 {
	return (volatile.LoadUint32(&o.AF_VSCALE_C.Reg) & 0xfff0000) >> 16
}

// ISP.AF_SUM_A: result of sum of af window a
func (o *ISP_Type) SetAF_SUM_A_AF_SUMA(value uint32) {
	volatile.StoreUint32(&o.AF_SUM_A.Reg, volatile.LoadUint32(&o.AF_SUM_A.Reg)&^(0x3fffffff)|value)
}
func (o *ISP_Type) GetAF_SUM_A_AF_SUMA() uint32 {
	return volatile.LoadUint32(&o.AF_SUM_A.Reg) & 0x3fffffff
}

// ISP.AF_SUM_B: result of sum of af window b
func (o *ISP_Type) SetAF_SUM_B_AF_SUMB(value uint32) {
	volatile.StoreUint32(&o.AF_SUM_B.Reg, volatile.LoadUint32(&o.AF_SUM_B.Reg)&^(0x3fffffff)|value)
}
func (o *ISP_Type) GetAF_SUM_B_AF_SUMB() uint32 {
	return volatile.LoadUint32(&o.AF_SUM_B.Reg) & 0x3fffffff
}

// ISP.AF_SUM_C: result of sum of af window c
func (o *ISP_Type) SetAF_SUM_C_AF_SUMC(value uint32) {
	volatile.StoreUint32(&o.AF_SUM_C.Reg, volatile.LoadUint32(&o.AF_SUM_C.Reg)&^(0x3fffffff)|value)
}
func (o *ISP_Type) GetAF_SUM_C_AF_SUMC() uint32 {
	return volatile.LoadUint32(&o.AF_SUM_C.Reg) & 0x3fffffff
}

// ISP.AF_LUM_A: result of lum of af window a
func (o *ISP_Type) SetAF_LUM_A_AF_LUMA(value uint32) {
	volatile.StoreUint32(&o.AF_LUM_A.Reg, volatile.LoadUint32(&o.AF_LUM_A.Reg)&^(0xfffffff)|value)
}
func (o *ISP_Type) GetAF_LUM_A_AF_LUMA() uint32 {
	return volatile.LoadUint32(&o.AF_LUM_A.Reg) & 0xfffffff
}

// ISP.AF_LUM_B: result of lum of af window b
func (o *ISP_Type) SetAF_LUM_B_AF_LUMB(value uint32) {
	volatile.StoreUint32(&o.AF_LUM_B.Reg, volatile.LoadUint32(&o.AF_LUM_B.Reg)&^(0xfffffff)|value)
}
func (o *ISP_Type) GetAF_LUM_B_AF_LUMB() uint32 {
	return volatile.LoadUint32(&o.AF_LUM_B.Reg) & 0xfffffff
}

// ISP.AF_LUM_C: result of lum of af window c
func (o *ISP_Type) SetAF_LUM_C_AF_LUMC(value uint32) {
	volatile.StoreUint32(&o.AF_LUM_C.Reg, volatile.LoadUint32(&o.AF_LUM_C.Reg)&^(0xfffffff)|value)
}
func (o *ISP_Type) GetAF_LUM_C_AF_LUMC() uint32 {
	return volatile.LoadUint32(&o.AF_LUM_C.Reg) & 0xfffffff
}

// ISP.AWB_MODE: awb mode control register
func (o *ISP_Type) SetAWB_MODE(value uint32) {
	volatile.StoreUint32(&o.AWB_MODE.Reg, volatile.LoadUint32(&o.AWB_MODE.Reg)&^(0x3)|value)
}
func (o *ISP_Type) GetAWB_MODE() uint32 {
	return volatile.LoadUint32(&o.AWB_MODE.Reg) & 0x3
}
func (o *ISP_Type) SetAWB_MODE_AWB_SAMPLE(value uint32) {
	volatile.StoreUint32(&o.AWB_MODE.Reg, volatile.LoadUint32(&o.AWB_MODE.Reg)&^(0x10)|value<<4)
}
func (o *ISP_Type) GetAWB_MODE_AWB_SAMPLE() uint32 {
	return (volatile.LoadUint32(&o.AWB_MODE.Reg) & 0x10) >> 4
}

// ISP.AWB_HSCALE: h-scale of awb window
func (o *ISP_Type) SetAWB_HSCALE_AWB_RPOINT(value uint32) {
	volatile.StoreUint32(&o.AWB_HSCALE.Reg, volatile.LoadUint32(&o.AWB_HSCALE.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAWB_HSCALE_AWB_RPOINT() uint32 {
	return volatile.LoadUint32(&o.AWB_HSCALE.Reg) & 0xfff
}
func (o *ISP_Type) SetAWB_HSCALE_AWB_LPOINT(value uint32) {
	volatile.StoreUint32(&o.AWB_HSCALE.Reg, volatile.LoadUint32(&o.AWB_HSCALE.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAWB_HSCALE_AWB_LPOINT() uint32 {
	return (volatile.LoadUint32(&o.AWB_HSCALE.Reg) & 0xfff0000) >> 16
}

// ISP.AWB_VSCALE: v-scale of awb window
func (o *ISP_Type) SetAWB_VSCALE_AWB_BPOINT(value uint32) {
	volatile.StoreUint32(&o.AWB_VSCALE.Reg, volatile.LoadUint32(&o.AWB_VSCALE.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetAWB_VSCALE_AWB_BPOINT() uint32 {
	return volatile.LoadUint32(&o.AWB_VSCALE.Reg) & 0xfff
}
func (o *ISP_Type) SetAWB_VSCALE_AWB_TPOINT(value uint32) {
	volatile.StoreUint32(&o.AWB_VSCALE.Reg, volatile.LoadUint32(&o.AWB_VSCALE.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetAWB_VSCALE_AWB_TPOINT() uint32 {
	return (volatile.LoadUint32(&o.AWB_VSCALE.Reg) & 0xfff0000) >> 16
}

// ISP.AWB_TH_LUM: awb lum threshold register
func (o *ISP_Type) SetAWB_TH_LUM_AWB_MIN_LUM(value uint32) {
	volatile.StoreUint32(&o.AWB_TH_LUM.Reg, volatile.LoadUint32(&o.AWB_TH_LUM.Reg)&^(0x3ff)|value)
}
func (o *ISP_Type) GetAWB_TH_LUM_AWB_MIN_LUM() uint32 {
	return volatile.LoadUint32(&o.AWB_TH_LUM.Reg) & 0x3ff
}
func (o *ISP_Type) SetAWB_TH_LUM_AWB_MAX_LUM(value uint32) {
	volatile.StoreUint32(&o.AWB_TH_LUM.Reg, volatile.LoadUint32(&o.AWB_TH_LUM.Reg)&^(0x3ff0000)|value<<16)
}
func (o *ISP_Type) GetAWB_TH_LUM_AWB_MAX_LUM() uint32 {
	return (volatile.LoadUint32(&o.AWB_TH_LUM.Reg) & 0x3ff0000) >> 16
}

// ISP.AWB_TH_RG: awb r/g threshold register
func (o *ISP_Type) SetAWB_TH_RG_AWB_MIN_RG(value uint32) {
	volatile.StoreUint32(&o.AWB_TH_RG.Reg, volatile.LoadUint32(&o.AWB_TH_RG.Reg)&^(0x3ff)|value)
}
func (o *ISP_Type) GetAWB_TH_RG_AWB_MIN_RG() uint32 {
	return volatile.LoadUint32(&o.AWB_TH_RG.Reg) & 0x3ff
}
func (o *ISP_Type) SetAWB_TH_RG_AWB_MAX_RG(value uint32) {
	volatile.StoreUint32(&o.AWB_TH_RG.Reg, volatile.LoadUint32(&o.AWB_TH_RG.Reg)&^(0x3ff0000)|value<<16)
}
func (o *ISP_Type) GetAWB_TH_RG_AWB_MAX_RG() uint32 {
	return (volatile.LoadUint32(&o.AWB_TH_RG.Reg) & 0x3ff0000) >> 16
}

// ISP.AWB_TH_BG: awb b/g threshold register
func (o *ISP_Type) SetAWB_TH_BG_AWB_MIN_BG(value uint32) {
	volatile.StoreUint32(&o.AWB_TH_BG.Reg, volatile.LoadUint32(&o.AWB_TH_BG.Reg)&^(0x3ff)|value)
}
func (o *ISP_Type) GetAWB_TH_BG_AWB_MIN_BG() uint32 {
	return volatile.LoadUint32(&o.AWB_TH_BG.Reg) & 0x3ff
}
func (o *ISP_Type) SetAWB_TH_BG_AWB_MAX_BG(value uint32) {
	volatile.StoreUint32(&o.AWB_TH_BG.Reg, volatile.LoadUint32(&o.AWB_TH_BG.Reg)&^(0x3ff0000)|value<<16)
}
func (o *ISP_Type) GetAWB_TH_BG_AWB_MAX_BG() uint32 {
	return (volatile.LoadUint32(&o.AWB_TH_BG.Reg) & 0x3ff0000) >> 16
}

// ISP.AWB0_WHITE_CNT: result of awb white point number
func (o *ISP_Type) SetAWB0_WHITE_CNT(value uint32) {
	volatile.StoreUint32(&o.AWB0_WHITE_CNT.Reg, volatile.LoadUint32(&o.AWB0_WHITE_CNT.Reg)&^(0xffffff)|value)
}
func (o *ISP_Type) GetAWB0_WHITE_CNT() uint32 {
	return volatile.LoadUint32(&o.AWB0_WHITE_CNT.Reg) & 0xffffff
}

// ISP.AWB0_ACC_R: result of accumulate of r channel of all white points
func (o *ISP_Type) SetAWB0_ACC_R(value uint32) {
	volatile.StoreUint32(&o.AWB0_ACC_R.Reg, value)
}
func (o *ISP_Type) GetAWB0_ACC_R() uint32 {
	return volatile.LoadUint32(&o.AWB0_ACC_R.Reg)
}

// ISP.AWB0_ACC_G: result of accumulate of g channel of all white points
func (o *ISP_Type) SetAWB0_ACC_G(value uint32) {
	volatile.StoreUint32(&o.AWB0_ACC_G.Reg, value)
}
func (o *ISP_Type) GetAWB0_ACC_G() uint32 {
	return volatile.LoadUint32(&o.AWB0_ACC_G.Reg)
}

// ISP.AWB0_ACC_B: result of accumulate of b channel of all white points
func (o *ISP_Type) SetAWB0_ACC_B(value uint32) {
	volatile.StoreUint32(&o.AWB0_ACC_B.Reg, value)
}
func (o *ISP_Type) GetAWB0_ACC_B() uint32 {
	return volatile.LoadUint32(&o.AWB0_ACC_B.Reg)
}

// ISP.COLOR_CTRL: color control register
func (o *ISP_Type) SetCOLOR_CTRL_COLOR_SATURATION(value uint32) {
	volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetCOLOR_CTRL_COLOR_SATURATION() uint32 {
	return volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff
}
func (o *ISP_Type) SetCOLOR_CTRL_COLOR_HUE(value uint32) {
	volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetCOLOR_CTRL_COLOR_HUE() uint32 {
	return (volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetCOLOR_CTRL_COLOR_CONTRAST(value uint32) {
	volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetCOLOR_CTRL_COLOR_CONTRAST() uint32 {
	return (volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetCOLOR_CTRL_COLOR_BRIGHTNESS(value uint32) {
	volatile.StoreUint32(&o.COLOR_CTRL.Reg, volatile.LoadUint32(&o.COLOR_CTRL.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetCOLOR_CTRL_COLOR_BRIGHTNESS() uint32 {
	return (volatile.LoadUint32(&o.COLOR_CTRL.Reg) & 0xff000000) >> 24
}

// ISP.BLC_VALUE: blc black level register
func (o *ISP_Type) SetBLC_VALUE_BLC_R3_VALUE(value uint32) {
	volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetBLC_VALUE_BLC_R3_VALUE() uint32 {
	return volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff
}
func (o *ISP_Type) SetBLC_VALUE_BLC_R2_VALUE(value uint32) {
	volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetBLC_VALUE_BLC_R2_VALUE() uint32 {
	return (volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetBLC_VALUE_BLC_R1_VALUE(value uint32) {
	volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetBLC_VALUE_BLC_R1_VALUE() uint32 {
	return (volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetBLC_VALUE_BLC_R0_VALUE(value uint32) {
	volatile.StoreUint32(&o.BLC_VALUE.Reg, volatile.LoadUint32(&o.BLC_VALUE.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetBLC_VALUE_BLC_R0_VALUE() uint32 {
	return (volatile.LoadUint32(&o.BLC_VALUE.Reg) & 0xff000000) >> 24
}

// ISP.BLC_CTRL0: blc stretch control register
func (o *ISP_Type) SetBLC_CTRL0_BLC_R3_STRETCH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetBLC_CTRL0_BLC_R3_STRETCH() uint32 {
	return volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x1
}
func (o *ISP_Type) SetBLC_CTRL0_BLC_R2_STRETCH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetBLC_CTRL0_BLC_R2_STRETCH() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x2) >> 1
}
func (o *ISP_Type) SetBLC_CTRL0_BLC_R1_STRETCH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x4)|value<<2)
}
func (o *ISP_Type) GetBLC_CTRL0_BLC_R1_STRETCH() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x4) >> 2
}
func (o *ISP_Type) SetBLC_CTRL0_BLC_R0_STRETCH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL0.Reg, volatile.LoadUint32(&o.BLC_CTRL0.Reg)&^(0x8)|value<<3)
}
func (o *ISP_Type) GetBLC_CTRL0_BLC_R0_STRETCH() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL0.Reg) & 0x8) >> 3
}

// ISP.BLC_CTRL1: blc window control register
func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_TOP(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x7ff)|value)
}
func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_TOP() uint32 {
	return volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x7ff
}
func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_LEFT(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x3ff800)|value<<11)
}
func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_LEFT() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x3ff800) >> 11
}
func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_VNUM(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x3c00000)|value<<22)
}
func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_VNUM() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x3c00000) >> 22
}
func (o *ISP_Type) SetBLC_CTRL1_BLC_WINDOW_HNUM(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x3c000000)|value<<26)
}
func (o *ISP_Type) GetBLC_CTRL1_BLC_WINDOW_HNUM() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x3c000000) >> 26
}
func (o *ISP_Type) SetBLC_CTRL1_BLC_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL1.Reg, volatile.LoadUint32(&o.BLC_CTRL1.Reg)&^(0x40000000)|value<<30)
}
func (o *ISP_Type) GetBLC_CTRL1_BLC_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL1.Reg) & 0x40000000) >> 30
}

// ISP.BLC_CTRL2: blc black threshold control register
func (o *ISP_Type) SetBLC_CTRL2_BLC_R3_TH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetBLC_CTRL2_BLC_R3_TH() uint32 {
	return volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff
}
func (o *ISP_Type) SetBLC_CTRL2_BLC_R2_TH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetBLC_CTRL2_BLC_R2_TH() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetBLC_CTRL2_BLC_R1_TH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetBLC_CTRL2_BLC_R1_TH() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetBLC_CTRL2_BLC_R0_TH(value uint32) {
	volatile.StoreUint32(&o.BLC_CTRL2.Reg, volatile.LoadUint32(&o.BLC_CTRL2.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetBLC_CTRL2_BLC_R0_TH() uint32 {
	return (volatile.LoadUint32(&o.BLC_CTRL2.Reg) & 0xff000000) >> 24
}

// ISP.BLC_MEAN: results of the average of black window
func (o *ISP_Type) SetBLC_MEAN_BLC_R3_MEAN(value uint32) {
	volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetBLC_MEAN_BLC_R3_MEAN() uint32 {
	return volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff
}
func (o *ISP_Type) SetBLC_MEAN_BLC_R2_MEAN(value uint32) {
	volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetBLC_MEAN_BLC_R2_MEAN() uint32 {
	return (volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetBLC_MEAN_BLC_R1_MEAN(value uint32) {
	volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetBLC_MEAN_BLC_R1_MEAN() uint32 {
	return (volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetBLC_MEAN_BLC_R0_MEAN(value uint32) {
	volatile.StoreUint32(&o.BLC_MEAN.Reg, volatile.LoadUint32(&o.BLC_MEAN.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetBLC_MEAN_BLC_R0_MEAN() uint32 {
	return (volatile.LoadUint32(&o.BLC_MEAN.Reg) & 0xff000000) >> 24
}

// ISP.HIST_MODE: histogram mode control register
func (o *ISP_Type) SetHIST_MODE(value uint32) {
	volatile.StoreUint32(&o.HIST_MODE.Reg, volatile.LoadUint32(&o.HIST_MODE.Reg)&^(0x7)|value)
}
func (o *ISP_Type) GetHIST_MODE() uint32 {
	return volatile.LoadUint32(&o.HIST_MODE.Reg) & 0x7
}

// ISP.HIST_COEFF: histogram rgb to gray coefficients register
func (o *ISP_Type) SetHIST_COEFF_B(value uint32) {
	volatile.StoreUint32(&o.HIST_COEFF.Reg, volatile.LoadUint32(&o.HIST_COEFF.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_COEFF_B() uint32 {
	return volatile.LoadUint32(&o.HIST_COEFF.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_COEFF_G(value uint32) {
	volatile.StoreUint32(&o.HIST_COEFF.Reg, volatile.LoadUint32(&o.HIST_COEFF.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_COEFF_G() uint32 {
	return (volatile.LoadUint32(&o.HIST_COEFF.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_COEFF_R(value uint32) {
	volatile.StoreUint32(&o.HIST_COEFF.Reg, volatile.LoadUint32(&o.HIST_COEFF.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_COEFF_R() uint32 {
	return (volatile.LoadUint32(&o.HIST_COEFF.Reg) & 0xff0000) >> 16
}

// ISP.HIST_OFFS: histogram window offsets register
func (o *ISP_Type) SetHIST_OFFS_HIST_Y_OFFS(value uint32) {
	volatile.StoreUint32(&o.HIST_OFFS.Reg, volatile.LoadUint32(&o.HIST_OFFS.Reg)&^(0xfff)|value)
}
func (o *ISP_Type) GetHIST_OFFS_HIST_Y_OFFS() uint32 {
	return volatile.LoadUint32(&o.HIST_OFFS.Reg) & 0xfff
}
func (o *ISP_Type) SetHIST_OFFS_HIST_X_OFFS(value uint32) {
	volatile.StoreUint32(&o.HIST_OFFS.Reg, volatile.LoadUint32(&o.HIST_OFFS.Reg)&^(0xfff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_OFFS_HIST_X_OFFS() uint32 {
	return (volatile.LoadUint32(&o.HIST_OFFS.Reg) & 0xfff0000) >> 16
}

// ISP.HIST_SIZE: histogram sub-window size register
func (o *ISP_Type) SetHIST_SIZE_HIST_Y_SIZE(value uint32) {
	volatile.StoreUint32(&o.HIST_SIZE.Reg, volatile.LoadUint32(&o.HIST_SIZE.Reg)&^(0x1ff)|value)
}
func (o *ISP_Type) GetHIST_SIZE_HIST_Y_SIZE() uint32 {
	return volatile.LoadUint32(&o.HIST_SIZE.Reg) & 0x1ff
}
func (o *ISP_Type) SetHIST_SIZE_HIST_X_SIZE(value uint32) {
	volatile.StoreUint32(&o.HIST_SIZE.Reg, volatile.LoadUint32(&o.HIST_SIZE.Reg)&^(0x1ff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_SIZE_HIST_X_SIZE() uint32 {
	return (volatile.LoadUint32(&o.HIST_SIZE.Reg) & 0x1ff0000) >> 16
}

// ISP.HIST_SEG0: histogram bin control register 0
func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_3_4(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_3_4() uint32 {
	return volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_2_3(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_2_3() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_1_2(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_1_2() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_SEG0_HIST_SEG_0_1(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG0.Reg, volatile.LoadUint32(&o.HIST_SEG0.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_SEG0_HIST_SEG_0_1() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG0.Reg) & 0xff000000) >> 24
}

// ISP.HIST_SEG1: histogram bin control register 1
func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_7_8(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_7_8() uint32 {
	return volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_6_7(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_6_7() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_5_6(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_5_6() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_SEG1_HIST_SEG_4_5(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG1.Reg, volatile.LoadUint32(&o.HIST_SEG1.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_SEG1_HIST_SEG_4_5() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG1.Reg) & 0xff000000) >> 24
}

// ISP.HIST_SEG2: histogram bin control register 2
func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_11_12(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_11_12() uint32 {
	return volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_10_11(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_10_11() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_9_10(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_9_10() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_SEG2_HIST_SEG_8_9(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG2.Reg, volatile.LoadUint32(&o.HIST_SEG2.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_SEG2_HIST_SEG_8_9() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG2.Reg) & 0xff000000) >> 24
}

// ISP.HIST_SEG3: histogram bin control register 3
func (o *ISP_Type) SetHIST_SEG3_HIST_SEG_14_15(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG3.Reg, volatile.LoadUint32(&o.HIST_SEG3.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_SEG3_HIST_SEG_14_15() uint32 {
	return volatile.LoadUint32(&o.HIST_SEG3.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_SEG3_HIST_SEG_13_14(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG3.Reg, volatile.LoadUint32(&o.HIST_SEG3.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_SEG3_HIST_SEG_13_14() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG3.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_SEG3_HIST_SEG_12_13(value uint32) {
	volatile.StoreUint32(&o.HIST_SEG3.Reg, volatile.LoadUint32(&o.HIST_SEG3.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_SEG3_HIST_SEG_12_13() uint32 {
	return (volatile.LoadUint32(&o.HIST_SEG3.Reg) & 0xff0000) >> 16
}

// ISP.HIST_WEIGHT0: histogram sub-window weight register 0
func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_03(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_03() uint32 {
	return volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_02(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_02() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_01(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_01() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_WEIGHT0_HIST_WEIGHT_00(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT0.Reg, volatile.LoadUint32(&o.HIST_WEIGHT0.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_WEIGHT0_HIST_WEIGHT_00() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT0.Reg) & 0xff000000) >> 24
}

// ISP.HIST_WEIGHT1: histogram sub-window weight register 1
func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_12(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_12() uint32 {
	return volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_11(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_11() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_10(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_10() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_WEIGHT1_HIST_WEIGHT_04(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT1.Reg, volatile.LoadUint32(&o.HIST_WEIGHT1.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_WEIGHT1_HIST_WEIGHT_04() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT1.Reg) & 0xff000000) >> 24
}

// ISP.HIST_WEIGHT2: histogram sub-window weight register 2
func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_21(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_21() uint32 {
	return volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_20(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_20() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_14(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_14() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_WEIGHT2_HIST_WEIGHT_13(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT2.Reg, volatile.LoadUint32(&o.HIST_WEIGHT2.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_WEIGHT2_HIST_WEIGHT_13() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT2.Reg) & 0xff000000) >> 24
}

// ISP.HIST_WEIGHT3: histogram sub-window weight register 3
func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_30(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_30() uint32 {
	return volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_24(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_24() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_23(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_23() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_WEIGHT3_HIST_WEIGHT_22(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT3.Reg, volatile.LoadUint32(&o.HIST_WEIGHT3.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_WEIGHT3_HIST_WEIGHT_22() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT3.Reg) & 0xff000000) >> 24
}

// ISP.HIST_WEIGHT4: histogram sub-window weight register 4
func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_34(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_34() uint32 {
	return volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_33(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_33() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_32(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_32() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_WEIGHT4_HIST_WEIGHT_31(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT4.Reg, volatile.LoadUint32(&o.HIST_WEIGHT4.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_WEIGHT4_HIST_WEIGHT_31() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT4.Reg) & 0xff000000) >> 24
}

// ISP.HIST_WEIGHT5: histogram sub-window weight register 5
func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_43(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_43() uint32 {
	return volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff
}
func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_42(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff00)|value<<8)
}
func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_42() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff00) >> 8
}
func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_41(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff0000)|value<<16)
}
func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_41() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff0000) >> 16
}
func (o *ISP_Type) SetHIST_WEIGHT5_HIST_WEIGHT_40(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT5.Reg, volatile.LoadUint32(&o.HIST_WEIGHT5.Reg)&^(0xff000000)|value<<24)
}
func (o *ISP_Type) GetHIST_WEIGHT5_HIST_WEIGHT_40() uint32 {
	return (volatile.LoadUint32(&o.HIST_WEIGHT5.Reg) & 0xff000000) >> 24
}

// ISP.HIST_WEIGHT6: histogram sub-window weight register 6
func (o *ISP_Type) SetHIST_WEIGHT6_HIST_WEIGHT_44(value uint32) {
	volatile.StoreUint32(&o.HIST_WEIGHT6.Reg, volatile.LoadUint32(&o.HIST_WEIGHT6.Reg)&^(0xff)|value)
}
func (o *ISP_Type) GetHIST_WEIGHT6_HIST_WEIGHT_44() uint32 {
	return volatile.LoadUint32(&o.HIST_WEIGHT6.Reg) & 0xff
}

// ISP.HIST_BIN0: result of histogram bin 0
func (o *ISP_Type) SetHIST_BIN0_HIST_BIN_0(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN0.Reg, volatile.LoadUint32(&o.HIST_BIN0.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN0_HIST_BIN_0() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN0.Reg) & 0x1ffff
}

// ISP.HIST_BIN1: result of histogram bin 1
func (o *ISP_Type) SetHIST_BIN1_HIST_BIN_1(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN1.Reg, volatile.LoadUint32(&o.HIST_BIN1.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN1_HIST_BIN_1() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN1.Reg) & 0x1ffff
}

// ISP.HIST_BIN2: result of histogram bin 2
func (o *ISP_Type) SetHIST_BIN2_HIST_BIN_2(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN2.Reg, volatile.LoadUint32(&o.HIST_BIN2.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN2_HIST_BIN_2() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN2.Reg) & 0x1ffff
}

// ISP.HIST_BIN3: result of histogram bin 3
func (o *ISP_Type) SetHIST_BIN3_HIST_BIN_3(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN3.Reg, volatile.LoadUint32(&o.HIST_BIN3.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN3_HIST_BIN_3() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN3.Reg) & 0x1ffff
}

// ISP.HIST_BIN4: result of histogram bin 4
func (o *ISP_Type) SetHIST_BIN4_HIST_BIN_4(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN4.Reg, volatile.LoadUint32(&o.HIST_BIN4.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN4_HIST_BIN_4() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN4.Reg) & 0x1ffff
}

// ISP.HIST_BIN5: result of histogram bin 5
func (o *ISP_Type) SetHIST_BIN5_HIST_BIN_5(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN5.Reg, volatile.LoadUint32(&o.HIST_BIN5.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN5_HIST_BIN_5() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN5.Reg) & 0x1ffff
}

// ISP.HIST_BIN6: result of histogram bin 6
func (o *ISP_Type) SetHIST_BIN6_HIST_BIN_6(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN6.Reg, volatile.LoadUint32(&o.HIST_BIN6.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN6_HIST_BIN_6() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN6.Reg) & 0x1ffff
}

// ISP.HIST_BIN7: result of histogram bin 7
func (o *ISP_Type) SetHIST_BIN7_HIST_BIN_7(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN7.Reg, volatile.LoadUint32(&o.HIST_BIN7.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN7_HIST_BIN_7() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN7.Reg) & 0x1ffff
}

// ISP.HIST_BIN8: result of histogram bin 8
func (o *ISP_Type) SetHIST_BIN8_HIST_BIN_8(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN8.Reg, volatile.LoadUint32(&o.HIST_BIN8.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN8_HIST_BIN_8() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN8.Reg) & 0x1ffff
}

// ISP.HIST_BIN9: result of histogram bin 9
func (o *ISP_Type) SetHIST_BIN9_HIST_BIN_9(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN9.Reg, volatile.LoadUint32(&o.HIST_BIN9.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN9_HIST_BIN_9() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN9.Reg) & 0x1ffff
}

// ISP.HIST_BIN10: result of histogram bin 10
func (o *ISP_Type) SetHIST_BIN10_HIST_BIN_10(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN10.Reg, volatile.LoadUint32(&o.HIST_BIN10.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN10_HIST_BIN_10() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN10.Reg) & 0x1ffff
}

// ISP.HIST_BIN11: result of histogram bin 11
func (o *ISP_Type) SetHIST_BIN11_HIST_BIN_11(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN11.Reg, volatile.LoadUint32(&o.HIST_BIN11.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN11_HIST_BIN_11() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN11.Reg) & 0x1ffff
}

// ISP.HIST_BIN12: result of histogram bin 12
func (o *ISP_Type) SetHIST_BIN12_HIST_BIN_12(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN12.Reg, volatile.LoadUint32(&o.HIST_BIN12.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN12_HIST_BIN_12() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN12.Reg) & 0x1ffff
}

// ISP.HIST_BIN13: result of histogram bin 13
func (o *ISP_Type) SetHIST_BIN13_HIST_BIN_13(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN13.Reg, volatile.LoadUint32(&o.HIST_BIN13.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN13_HIST_BIN_13() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN13.Reg) & 0x1ffff
}

// ISP.HIST_BIN14: result of histogram bin 14
func (o *ISP_Type) SetHIST_BIN14_HIST_BIN_14(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN14.Reg, volatile.LoadUint32(&o.HIST_BIN14.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN14_HIST_BIN_14() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN14.Reg) & 0x1ffff
}

// ISP.HIST_BIN15: result of histogram bin 15
func (o *ISP_Type) SetHIST_BIN15_HIST_BIN_15(value uint32) {
	volatile.StoreUint32(&o.HIST_BIN15.Reg, volatile.LoadUint32(&o.HIST_BIN15.Reg)&^(0x1ffff)|value)
}
func (o *ISP_Type) GetHIST_BIN15_HIST_BIN_15() uint32 {
	return volatile.LoadUint32(&o.HIST_BIN15.Reg) & 0x1ffff
}

// ISP.MEM_AUX_CTRL_0: mem aux control register 0
func (o *ISP_Type) SetMEM_AUX_CTRL_0_HEADER_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_0.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg)&^(0x3fff)|value)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_0_HEADER_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg) & 0x3fff
}
func (o *ISP_Type) SetMEM_AUX_CTRL_0_DPC_LUT_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_0.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg)&^(0x3fff0000)|value<<16)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_0_DPC_LUT_MEM_AUX_CTRL() uint32 {
	return (volatile.LoadUint32(&o.MEM_AUX_CTRL_0.Reg) & 0x3fff0000) >> 16
}

// ISP.MEM_AUX_CTRL_1: mem aux control register 1
func (o *ISP_Type) SetMEM_AUX_CTRL_1_LSC_LUT_R_GR_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_1.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg)&^(0x3fff)|value)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_1_LSC_LUT_R_GR_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg) & 0x3fff
}
func (o *ISP_Type) SetMEM_AUX_CTRL_1_LSC_LUT_GB_B_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_1.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg)&^(0x3fff0000)|value<<16)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_1_LSC_LUT_GB_B_MEM_AUX_CTRL() uint32 {
	return (volatile.LoadUint32(&o.MEM_AUX_CTRL_1.Reg) & 0x3fff0000) >> 16
}

// ISP.MEM_AUX_CTRL_2: mem aux control register 2
func (o *ISP_Type) SetMEM_AUX_CTRL_2_BF_MATRIX_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_2.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg)&^(0x3fff)|value)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_2_BF_MATRIX_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg) & 0x3fff
}
func (o *ISP_Type) SetMEM_AUX_CTRL_2_DPC_MATRIX_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_2.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg)&^(0x3fff0000)|value<<16)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_2_DPC_MATRIX_MEM_AUX_CTRL() uint32 {
	return (volatile.LoadUint32(&o.MEM_AUX_CTRL_2.Reg) & 0x3fff0000) >> 16
}

// ISP.MEM_AUX_CTRL_3: mem aux control register 3
func (o *ISP_Type) SetMEM_AUX_CTRL_3_SHARP_MATRIX_Y_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_3.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg)&^(0x3fff)|value)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_3_SHARP_MATRIX_Y_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg) & 0x3fff
}
func (o *ISP_Type) SetMEM_AUX_CTRL_3_DEMOSAIC_MATRIX_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_3.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg)&^(0x3fff0000)|value<<16)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_3_DEMOSAIC_MATRIX_MEM_AUX_CTRL() uint32 {
	return (volatile.LoadUint32(&o.MEM_AUX_CTRL_3.Reg) & 0x3fff0000) >> 16
}

// ISP.MEM_AUX_CTRL_4: mem aux control register 4
func (o *ISP_Type) SetMEM_AUX_CTRL_4_SHARP_MATRIX_UV_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.MEM_AUX_CTRL_4.Reg, volatile.LoadUint32(&o.MEM_AUX_CTRL_4.Reg)&^(0x3fff)|value)
}
func (o *ISP_Type) GetMEM_AUX_CTRL_4_SHARP_MATRIX_UV_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.MEM_AUX_CTRL_4.Reg) & 0x3fff
}

// ISP.YUV_FORMAT: yuv format control register
func (o *ISP_Type) SetYUV_FORMAT_YUV_MODE(value uint32) {
	volatile.StoreUint32(&o.YUV_FORMAT.Reg, volatile.LoadUint32(&o.YUV_FORMAT.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetYUV_FORMAT_YUV_MODE() uint32 {
	return volatile.LoadUint32(&o.YUV_FORMAT.Reg) & 0x1
}
func (o *ISP_Type) SetYUV_FORMAT_YUV_RANGE(value uint32) {
	volatile.StoreUint32(&o.YUV_FORMAT.Reg, volatile.LoadUint32(&o.YUV_FORMAT.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetYUV_FORMAT_YUV_RANGE() uint32 {
	return (volatile.LoadUint32(&o.YUV_FORMAT.Reg) & 0x2) >> 1
}

// ISP.RDN_ECO_CS: rdn eco cs register
func (o *ISP_Type) SetRDN_ECO_CS_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *ISP_Type) GetRDN_ECO_CS_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x1
}
func (o *ISP_Type) SetRDN_ECO_CS_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_CS.Reg, volatile.LoadUint32(&o.RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *ISP_Type) GetRDN_ECO_CS_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RDN_ECO_CS.Reg) & 0x2) >> 1
}

// ISP.RDN_ECO_LOW: rdn eco all low register
func (o *ISP_Type) SetRDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_LOW.Reg, value)
}
func (o *ISP_Type) GetRDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_LOW.Reg)
}

// ISP.RDN_ECO_HIGH: rdn eco all high register
func (o *ISP_Type) SetRDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO_HIGH.Reg, value)
}
func (o *ISP_Type) GetRDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO_HIGH.Reg)
}

// JPEG Codec
type JPEG_Type struct {
	CONFIG          volatile.Register32 // 0x0
	DQT_INFO        volatile.Register32 // 0x4
	PIC_SIZE        volatile.Register32 // 0x8
	_               [4]byte
	T0QNR           volatile.Register32 // 0x10
	T1QNR           volatile.Register32 // 0x14
	T2QNR           volatile.Register32 // 0x18
	T3QNR           volatile.Register32 // 0x1C
	DECODE_CONF     volatile.Register32 // 0x20
	C0              volatile.Register32 // 0x24
	C1              volatile.Register32 // 0x28
	C2              volatile.Register32 // 0x2C
	C3              volatile.Register32 // 0x30
	DHT_INFO        volatile.Register32 // 0x34
	INT_RAW         volatile.Register32 // 0x38
	INT_ENA         volatile.Register32 // 0x3C
	INT_ST          volatile.Register32 // 0x40
	INT_CLR         volatile.Register32 // 0x44
	STATUS0         volatile.Register32 // 0x48
	STATUS2         volatile.Register32 // 0x4C
	STATUS3         volatile.Register32 // 0x50
	STATUS4         volatile.Register32 // 0x54
	DHT_TOTLEN_DC0  volatile.Register32 // 0x58
	DHT_VAl_DC0     volatile.Register32 // 0x5C
	DHT_TOTLEN_AC0  volatile.Register32 // 0x60
	DHT_VAl_AC0     volatile.Register32 // 0x64
	DHT_TOTLEN_DC1  volatile.Register32 // 0x68
	DHT_VAl_DC1     volatile.Register32 // 0x6C
	DHT_TOTLEN_AC1  volatile.Register32 // 0x70
	DHT_VAl_AC1     volatile.Register32 // 0x74
	DHT_CODEMIN_DC0 volatile.Register32 // 0x78
	DHT_CODEMIN_AC0 volatile.Register32 // 0x7C
	DHT_CODEMIN_DC1 volatile.Register32 // 0x80
	DHT_CODEMIN_AC1 volatile.Register32 // 0x84
	DECODER_STATUS0 volatile.Register32 // 0x88
	DECODER_STATUS1 volatile.Register32 // 0x8C
	DECODER_STATUS2 volatile.Register32 // 0x90
	DECODER_STATUS3 volatile.Register32 // 0x94
	DECODER_STATUS4 volatile.Register32 // 0x98
	DECODER_STATUS5 volatile.Register32 // 0x9C
	STATUS5         volatile.Register32 // 0xA0
	ECO_LOW         volatile.Register32 // 0xA4
	ECO_HIGH        volatile.Register32 // 0xA8
	_               [76]byte
	SYS             volatile.Register32 // 0xF8
	VERSION         volatile.Register32 // 0xFC
}

// JPEG.CONFIG: Control and configuration registers
func (o *JPEG_Type) SetCONFIG_FSM_RST(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1)|value)
}
func (o *JPEG_Type) GetCONFIG_FSM_RST() uint32 {
	return volatile.LoadUint32(&o.CONFIG.Reg) & 0x1
}
func (o *JPEG_Type) SetCONFIG_JPEG_START(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *JPEG_Type) GetCONFIG_JPEG_START() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2) >> 1
}
func (o *JPEG_Type) SetCONFIG_QNR_PRESITION(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4)|value<<2)
}
func (o *JPEG_Type) GetCONFIG_QNR_PRESITION() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4) >> 2
}
func (o *JPEG_Type) SetCONFIG_FF_CHECK_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8)|value<<3)
}
func (o *JPEG_Type) GetCONFIG_FF_CHECK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8) >> 3
}
func (o *JPEG_Type) SetCONFIG_SAMPLE_SEL(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x30)|value<<4)
}
func (o *JPEG_Type) GetCONFIG_SAMPLE_SEL() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x30) >> 4
}
func (o *JPEG_Type) SetCONFIG_DMA_LINKLIST_MODE(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x40)|value<<6)
}
func (o *JPEG_Type) GetCONFIG_DMA_LINKLIST_MODE() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x40) >> 6
}
func (o *JPEG_Type) SetCONFIG_DEBUG_DIRECT_OUT_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x80)|value<<7)
}
func (o *JPEG_Type) GetCONFIG_DEBUG_DIRECT_OUT_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x80) >> 7
}
func (o *JPEG_Type) SetCONFIG_GRAY_SEL(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x100)|value<<8)
}
func (o *JPEG_Type) GetCONFIG_GRAY_SEL() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x100) >> 8
}
func (o *JPEG_Type) SetCONFIG_LQNR_TBL_SEL(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x600)|value<<9)
}
func (o *JPEG_Type) GetCONFIG_LQNR_TBL_SEL() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x600) >> 9
}
func (o *JPEG_Type) SetCONFIG_CQNR_TBL_SEL(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1800)|value<<11)
}
func (o *JPEG_Type) GetCONFIG_CQNR_TBL_SEL() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x1800) >> 11
}
func (o *JPEG_Type) SetCONFIG_COLOR_SPACE(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x6000)|value<<13)
}
func (o *JPEG_Type) GetCONFIG_COLOR_SPACE() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x6000) >> 13
}
func (o *JPEG_Type) SetCONFIG_DHT_FIFO_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8000)|value<<15)
}
func (o *JPEG_Type) GetCONFIG_DHT_FIFO_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8000) >> 15
}
func (o *JPEG_Type) SetCONFIG_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10000)|value<<16)
}
func (o *JPEG_Type) GetCONFIG_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10000) >> 16
}
func (o *JPEG_Type) SetCONFIG_JFIF_VER(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x7e0000)|value<<17)
}
func (o *JPEG_Type) GetCONFIG_JFIF_VER() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x7e0000) >> 17
}
func (o *JPEG_Type) SetCONFIG_DECODE_TIMEOUT_TASK_SEL(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x800000)|value<<23)
}
func (o *JPEG_Type) GetCONFIG_DECODE_TIMEOUT_TASK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x800000) >> 23
}
func (o *JPEG_Type) SetCONFIG_SOFT_RST(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1000000)|value<<24)
}
func (o *JPEG_Type) GetCONFIG_SOFT_RST() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x1000000) >> 24
}
func (o *JPEG_Type) SetCONFIG_FIFO_RST(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2000000)|value<<25)
}
func (o *JPEG_Type) GetCONFIG_FIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2000000) >> 25
}
func (o *JPEG_Type) SetCONFIG_PIXEL_REV(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4000000)|value<<26)
}
func (o *JPEG_Type) GetCONFIG_PIXEL_REV() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4000000) >> 26
}
func (o *JPEG_Type) SetCONFIG_TAILER_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8000000)|value<<27)
}
func (o *JPEG_Type) GetCONFIG_TAILER_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8000000) >> 27
}
func (o *JPEG_Type) SetCONFIG_PAUSE_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10000000)|value<<28)
}
func (o *JPEG_Type) GetCONFIG_PAUSE_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10000000) >> 28
}
func (o *JPEG_Type) SetCONFIG_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x20000000)|value<<29)
}
func (o *JPEG_Type) GetCONFIG_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x20000000) >> 29
}
func (o *JPEG_Type) SetCONFIG_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x40000000)|value<<30)
}
func (o *JPEG_Type) GetCONFIG_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x40000000) >> 30
}
func (o *JPEG_Type) SetCONFIG_MODE(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x80000000)|value<<31)
}
func (o *JPEG_Type) GetCONFIG_MODE() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x80000000) >> 31
}

// JPEG.DQT_INFO: Control and configuration registers
func (o *JPEG_Type) SetDQT_INFO_T0_DQT_INFO(value uint32) {
	volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff)|value)
}
func (o *JPEG_Type) GetDQT_INFO_T0_DQT_INFO() uint32 {
	return volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff
}
func (o *JPEG_Type) SetDQT_INFO_T1_DQT_INFO(value uint32) {
	volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff00)|value<<8)
}
func (o *JPEG_Type) GetDQT_INFO_T1_DQT_INFO() uint32 {
	return (volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff00) >> 8
}
func (o *JPEG_Type) SetDQT_INFO_T2_DQT_INFO(value uint32) {
	volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff0000)|value<<16)
}
func (o *JPEG_Type) GetDQT_INFO_T2_DQT_INFO() uint32 {
	return (volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff0000) >> 16
}
func (o *JPEG_Type) SetDQT_INFO_T3_DQT_INFO(value uint32) {
	volatile.StoreUint32(&o.DQT_INFO.Reg, volatile.LoadUint32(&o.DQT_INFO.Reg)&^(0xff000000)|value<<24)
}
func (o *JPEG_Type) GetDQT_INFO_T3_DQT_INFO() uint32 {
	return (volatile.LoadUint32(&o.DQT_INFO.Reg) & 0xff000000) >> 24
}

// JPEG.PIC_SIZE: Control and configuration registers
func (o *JPEG_Type) SetPIC_SIZE_VA(value uint32) {
	volatile.StoreUint32(&o.PIC_SIZE.Reg, volatile.LoadUint32(&o.PIC_SIZE.Reg)&^(0xffff)|value)
}
func (o *JPEG_Type) GetPIC_SIZE_VA() uint32 {
	return volatile.LoadUint32(&o.PIC_SIZE.Reg) & 0xffff
}
func (o *JPEG_Type) SetPIC_SIZE_HA(value uint32) {
	volatile.StoreUint32(&o.PIC_SIZE.Reg, volatile.LoadUint32(&o.PIC_SIZE.Reg)&^(0xffff0000)|value<<16)
}
func (o *JPEG_Type) GetPIC_SIZE_HA() uint32 {
	return (volatile.LoadUint32(&o.PIC_SIZE.Reg) & 0xffff0000) >> 16
}

// JPEG.T0QNR: Control and configuration registers
func (o *JPEG_Type) SetT0QNR(value uint32) {
	volatile.StoreUint32(&o.T0QNR.Reg, value)
}
func (o *JPEG_Type) GetT0QNR() uint32 {
	return volatile.LoadUint32(&o.T0QNR.Reg)
}

// JPEG.T1QNR: Control and configuration registers
func (o *JPEG_Type) SetT1QNR(value uint32) {
	volatile.StoreUint32(&o.T1QNR.Reg, value)
}
func (o *JPEG_Type) GetT1QNR() uint32 {
	return volatile.LoadUint32(&o.T1QNR.Reg)
}

// JPEG.T2QNR: Control and configuration registers
func (o *JPEG_Type) SetT2QNR(value uint32) {
	volatile.StoreUint32(&o.T2QNR.Reg, value)
}
func (o *JPEG_Type) GetT2QNR() uint32 {
	return volatile.LoadUint32(&o.T2QNR.Reg)
}

// JPEG.T3QNR: Control and configuration registers
func (o *JPEG_Type) SetT3QNR(value uint32) {
	volatile.StoreUint32(&o.T3QNR.Reg, value)
}
func (o *JPEG_Type) GetT3QNR() uint32 {
	return volatile.LoadUint32(&o.T3QNR.Reg)
}

// JPEG.DECODE_CONF: Control and configuration registers
func (o *JPEG_Type) SetDECODE_CONF_RESTART_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0xffff)|value)
}
func (o *JPEG_Type) GetDECODE_CONF_RESTART_INTERVAL() uint32 {
	return volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0xffff
}
func (o *JPEG_Type) SetDECODE_CONF_COMPONENT_NUM(value uint32) {
	volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0xff0000)|value<<16)
}
func (o *JPEG_Type) GetDECODE_CONF_COMPONENT_NUM() uint32 {
	return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0xff0000) >> 16
}
func (o *JPEG_Type) SetDECODE_CONF_SW_DHT_EN(value uint32) {
	volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *JPEG_Type) GetDECODE_CONF_SW_DHT_EN() uint32 {
	return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x1000000) >> 24
}
func (o *JPEG_Type) SetDECODE_CONF_SOS_CHECK_BYTE_NUM(value uint32) {
	volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x6000000)|value<<25)
}
func (o *JPEG_Type) GetDECODE_CONF_SOS_CHECK_BYTE_NUM() uint32 {
	return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x6000000) >> 25
}
func (o *JPEG_Type) SetDECODE_CONF_RST_CHECK_BYTE_NUM(value uint32) {
	volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x18000000)|value<<27)
}
func (o *JPEG_Type) GetDECODE_CONF_RST_CHECK_BYTE_NUM() uint32 {
	return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x18000000) >> 27
}
func (o *JPEG_Type) SetDECODE_CONF_MULTI_SCAN_ERR_CHECK(value uint32) {
	volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x20000000)|value<<29)
}
func (o *JPEG_Type) GetDECODE_CONF_MULTI_SCAN_ERR_CHECK() uint32 {
	return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x20000000) >> 29
}
func (o *JPEG_Type) SetDECODE_CONF_DEZIGZAG_READY_CTL(value uint32) {
	volatile.StoreUint32(&o.DECODE_CONF.Reg, volatile.LoadUint32(&o.DECODE_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *JPEG_Type) GetDECODE_CONF_DEZIGZAG_READY_CTL() uint32 {
	return (volatile.LoadUint32(&o.DECODE_CONF.Reg) & 0x40000000) >> 30
}

// JPEG.C0: Control and configuration registers
func (o *JPEG_Type) SetC0_DQT_TBL_SEL(value uint32) {
	volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xff)|value)
}
func (o *JPEG_Type) GetC0_DQT_TBL_SEL() uint32 {
	return volatile.LoadUint32(&o.C0.Reg) & 0xff
}
func (o *JPEG_Type) SetC0_Y_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xf00)|value<<8)
}
func (o *JPEG_Type) GetC0_Y_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C0.Reg) & 0xf00) >> 8
}
func (o *JPEG_Type) SetC0_X_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xf000)|value<<12)
}
func (o *JPEG_Type) GetC0_X_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C0.Reg) & 0xf000) >> 12
}
func (o *JPEG_Type) SetC0_ID(value uint32) {
	volatile.StoreUint32(&o.C0.Reg, volatile.LoadUint32(&o.C0.Reg)&^(0xff0000)|value<<16)
}
func (o *JPEG_Type) GetC0_ID() uint32 {
	return (volatile.LoadUint32(&o.C0.Reg) & 0xff0000) >> 16
}

// JPEG.C1: Control and configuration registers
func (o *JPEG_Type) SetC1_DQT_TBL_SEL(value uint32) {
	volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xff)|value)
}
func (o *JPEG_Type) GetC1_DQT_TBL_SEL() uint32 {
	return volatile.LoadUint32(&o.C1.Reg) & 0xff
}
func (o *JPEG_Type) SetC1_Y_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xf00)|value<<8)
}
func (o *JPEG_Type) GetC1_Y_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C1.Reg) & 0xf00) >> 8
}
func (o *JPEG_Type) SetC1_X_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xf000)|value<<12)
}
func (o *JPEG_Type) GetC1_X_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C1.Reg) & 0xf000) >> 12
}
func (o *JPEG_Type) SetC1_ID(value uint32) {
	volatile.StoreUint32(&o.C1.Reg, volatile.LoadUint32(&o.C1.Reg)&^(0xff0000)|value<<16)
}
func (o *JPEG_Type) GetC1_ID() uint32 {
	return (volatile.LoadUint32(&o.C1.Reg) & 0xff0000) >> 16
}

// JPEG.C2: Control and configuration registers
func (o *JPEG_Type) SetC2_DQT_TBL_SEL(value uint32) {
	volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xff)|value)
}
func (o *JPEG_Type) GetC2_DQT_TBL_SEL() uint32 {
	return volatile.LoadUint32(&o.C2.Reg) & 0xff
}
func (o *JPEG_Type) SetC2_Y_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xf00)|value<<8)
}
func (o *JPEG_Type) GetC2_Y_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C2.Reg) & 0xf00) >> 8
}
func (o *JPEG_Type) SetC2_X_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xf000)|value<<12)
}
func (o *JPEG_Type) GetC2_X_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C2.Reg) & 0xf000) >> 12
}
func (o *JPEG_Type) SetC2_ID(value uint32) {
	volatile.StoreUint32(&o.C2.Reg, volatile.LoadUint32(&o.C2.Reg)&^(0xff0000)|value<<16)
}
func (o *JPEG_Type) GetC2_ID() uint32 {
	return (volatile.LoadUint32(&o.C2.Reg) & 0xff0000) >> 16
}

// JPEG.C3: Control and configuration registers
func (o *JPEG_Type) SetC3_DQT_TBL_SEL(value uint32) {
	volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xff)|value)
}
func (o *JPEG_Type) GetC3_DQT_TBL_SEL() uint32 {
	return volatile.LoadUint32(&o.C3.Reg) & 0xff
}
func (o *JPEG_Type) SetC3_Y_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xf00)|value<<8)
}
func (o *JPEG_Type) GetC3_Y_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C3.Reg) & 0xf00) >> 8
}
func (o *JPEG_Type) SetC3_X_FACTOR(value uint32) {
	volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xf000)|value<<12)
}
func (o *JPEG_Type) GetC3_X_FACTOR() uint32 {
	return (volatile.LoadUint32(&o.C3.Reg) & 0xf000) >> 12
}
func (o *JPEG_Type) SetC3_ID(value uint32) {
	volatile.StoreUint32(&o.C3.Reg, volatile.LoadUint32(&o.C3.Reg)&^(0xff0000)|value<<16)
}
func (o *JPEG_Type) GetC3_ID() uint32 {
	return (volatile.LoadUint32(&o.C3.Reg) & 0xff0000) >> 16
}

// JPEG.DHT_INFO: Control and configuration registers
func (o *JPEG_Type) SetDHT_INFO_DC0_DHT_ID(value uint32) {
	volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf)|value)
}
func (o *JPEG_Type) GetDHT_INFO_DC0_DHT_ID() uint32 {
	return volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf
}
func (o *JPEG_Type) SetDHT_INFO_DC1_DHT_ID(value uint32) {
	volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf0)|value<<4)
}
func (o *JPEG_Type) GetDHT_INFO_DC1_DHT_ID() uint32 {
	return (volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf0) >> 4
}
func (o *JPEG_Type) SetDHT_INFO_AC0_DHT_ID(value uint32) {
	volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf00)|value<<8)
}
func (o *JPEG_Type) GetDHT_INFO_AC0_DHT_ID() uint32 {
	return (volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf00) >> 8
}
func (o *JPEG_Type) SetDHT_INFO_AC1_DHT_ID(value uint32) {
	volatile.StoreUint32(&o.DHT_INFO.Reg, volatile.LoadUint32(&o.DHT_INFO.Reg)&^(0xf000)|value<<12)
}
func (o *JPEG_Type) GetDHT_INFO_AC1_DHT_ID() uint32 {
	return (volatile.LoadUint32(&o.DHT_INFO.Reg) & 0xf000) >> 12
}

// JPEG.INT_RAW: Interrupt raw registers
func (o *JPEG_Type) SetINT_RAW_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *JPEG_Type) GetINT_RAW_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *JPEG_Type) SetINT_RAW_RLE_PARALLEL_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *JPEG_Type) GetINT_RAW_RLE_PARALLEL_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *JPEG_Type) SetINT_RAW_CID_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *JPEG_Type) GetINT_RAW_CID_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *JPEG_Type) SetINT_RAW_C_DHT_DC_ID_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *JPEG_Type) GetINT_RAW_C_DHT_DC_ID_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *JPEG_Type) SetINT_RAW_C_DHT_AC_ID_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *JPEG_Type) GetINT_RAW_C_DHT_AC_ID_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *JPEG_Type) SetINT_RAW_C_DQT_ID_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *JPEG_Type) GetINT_RAW_C_DQT_ID_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *JPEG_Type) SetINT_RAW_RST_UXP_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *JPEG_Type) GetINT_RAW_RST_UXP_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *JPEG_Type) SetINT_RAW_RST_CHECK_NONE_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *JPEG_Type) GetINT_RAW_RST_CHECK_NONE_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *JPEG_Type) SetINT_RAW_RST_CHECK_POS_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *JPEG_Type) GetINT_RAW_RST_CHECK_POS_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *JPEG_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *JPEG_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *JPEG_Type) SetINT_RAW_SR_COLOR_MODE_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *JPEG_Type) GetINT_RAW_SR_COLOR_MODE_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *JPEG_Type) SetINT_RAW_DCT_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *JPEG_Type) GetINT_RAW_DCT_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *JPEG_Type) SetINT_RAW_BS_LAST_BLOCK_EOF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *JPEG_Type) GetINT_RAW_BS_LAST_BLOCK_EOF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *JPEG_Type) SetINT_RAW_SCAN_CHECK_NONE_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *JPEG_Type) GetINT_RAW_SCAN_CHECK_NONE_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *JPEG_Type) SetINT_RAW_SCAN_CHECK_POS_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *JPEG_Type) GetINT_RAW_SCAN_CHECK_POS_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *JPEG_Type) SetINT_RAW_UXP_DET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *JPEG_Type) GetINT_RAW_UXP_DET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *JPEG_Type) SetINT_RAW_EN_FRAME_EOF_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *JPEG_Type) GetINT_RAW_EN_FRAME_EOF_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *JPEG_Type) SetINT_RAW_EN_FRAME_EOF_LACK_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *JPEG_Type) GetINT_RAW_EN_FRAME_EOF_LACK_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *JPEG_Type) SetINT_RAW_DE_FRAME_EOF_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *JPEG_Type) GetINT_RAW_DE_FRAME_EOF_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *JPEG_Type) SetINT_RAW_DE_FRAME_EOF_LACK_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *JPEG_Type) GetINT_RAW_DE_FRAME_EOF_LACK_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}
func (o *JPEG_Type) SetINT_RAW_SOS_UNMATCH_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *JPEG_Type) GetINT_RAW_SOS_UNMATCH_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20
}
func (o *JPEG_Type) SetINT_RAW_MARKER_ERR_FST_SCAN_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21)
}
func (o *JPEG_Type) GetINT_RAW_MARKER_ERR_FST_SCAN_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21
}
func (o *JPEG_Type) SetINT_RAW_MARKER_ERR_OTHER_SCAN_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22)
}
func (o *JPEG_Type) GetINT_RAW_MARKER_ERR_OTHER_SCAN_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22
}
func (o *JPEG_Type) SetINT_RAW_UNDET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23)
}
func (o *JPEG_Type) GetINT_RAW_UNDET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23
}
func (o *JPEG_Type) SetINT_RAW_DECODE_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24)
}
func (o *JPEG_Type) GetINT_RAW_DECODE_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24
}

// JPEG.INT_ENA: Interrupt enable registers
func (o *JPEG_Type) SetINT_ENA_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *JPEG_Type) GetINT_ENA_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *JPEG_Type) SetINT_ENA_RLE_PARALLEL_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *JPEG_Type) GetINT_ENA_RLE_PARALLEL_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *JPEG_Type) SetINT_ENA_CID_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *JPEG_Type) GetINT_ENA_CID_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *JPEG_Type) SetINT_ENA_C_DHT_DC_ID_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *JPEG_Type) GetINT_ENA_C_DHT_DC_ID_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *JPEG_Type) SetINT_ENA_C_DHT_AC_ID_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *JPEG_Type) GetINT_ENA_C_DHT_AC_ID_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *JPEG_Type) SetINT_ENA_C_DQT_ID_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *JPEG_Type) GetINT_ENA_C_DQT_ID_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *JPEG_Type) SetINT_ENA_RST_UXP_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *JPEG_Type) GetINT_ENA_RST_UXP_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *JPEG_Type) SetINT_ENA_RST_CHECK_NONE_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *JPEG_Type) GetINT_ENA_RST_CHECK_NONE_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *JPEG_Type) SetINT_ENA_RST_CHECK_POS_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *JPEG_Type) GetINT_ENA_RST_CHECK_POS_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *JPEG_Type) SetINT_ENA_OUT_EOF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *JPEG_Type) GetINT_ENA_OUT_EOF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *JPEG_Type) SetINT_ENA_SR_COLOR_MODE_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *JPEG_Type) GetINT_ENA_SR_COLOR_MODE_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *JPEG_Type) SetINT_ENA_DCT_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *JPEG_Type) GetINT_ENA_DCT_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *JPEG_Type) SetINT_ENA_BS_LAST_BLOCK_EOF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *JPEG_Type) GetINT_ENA_BS_LAST_BLOCK_EOF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *JPEG_Type) SetINT_ENA_SCAN_CHECK_NONE_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *JPEG_Type) GetINT_ENA_SCAN_CHECK_NONE_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *JPEG_Type) SetINT_ENA_SCAN_CHECK_POS_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *JPEG_Type) GetINT_ENA_SCAN_CHECK_POS_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *JPEG_Type) SetINT_ENA_UXP_DET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *JPEG_Type) GetINT_ENA_UXP_DET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}
func (o *JPEG_Type) SetINT_ENA_EN_FRAME_EOF_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *JPEG_Type) GetINT_ENA_EN_FRAME_EOF_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16
}
func (o *JPEG_Type) SetINT_ENA_EN_FRAME_EOF_LACK_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *JPEG_Type) GetINT_ENA_EN_FRAME_EOF_LACK_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17
}
func (o *JPEG_Type) SetINT_ENA_DE_FRAME_EOF_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *JPEG_Type) GetINT_ENA_DE_FRAME_EOF_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}
func (o *JPEG_Type) SetINT_ENA_DE_FRAME_EOF_LACK_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *JPEG_Type) GetINT_ENA_DE_FRAME_EOF_LACK_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19
}
func (o *JPEG_Type) SetINT_ENA_SOS_UNMATCH_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *JPEG_Type) GetINT_ENA_SOS_UNMATCH_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20
}
func (o *JPEG_Type) SetINT_ENA_MARKER_ERR_FST_SCAN_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21)
}
func (o *JPEG_Type) GetINT_ENA_MARKER_ERR_FST_SCAN_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21
}
func (o *JPEG_Type) SetINT_ENA_MARKER_ERR_OTHER_SCAN_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22)
}
func (o *JPEG_Type) GetINT_ENA_MARKER_ERR_OTHER_SCAN_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22
}
func (o *JPEG_Type) SetINT_ENA_UNDET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23)
}
func (o *JPEG_Type) GetINT_ENA_UNDET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23
}
func (o *JPEG_Type) SetINT_ENA_DECODE_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24)
}
func (o *JPEG_Type) GetINT_ENA_DECODE_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24
}

// JPEG.INT_ST: Interrupt status registers
func (o *JPEG_Type) SetINT_ST_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *JPEG_Type) GetINT_ST_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *JPEG_Type) SetINT_ST_RLE_PARALLEL_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *JPEG_Type) GetINT_ST_RLE_PARALLEL_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *JPEG_Type) SetINT_ST_CID_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *JPEG_Type) GetINT_ST_CID_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *JPEG_Type) SetINT_ST_C_DHT_DC_ID_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *JPEG_Type) GetINT_ST_C_DHT_DC_ID_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *JPEG_Type) SetINT_ST_C_DHT_AC_ID_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *JPEG_Type) GetINT_ST_C_DHT_AC_ID_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *JPEG_Type) SetINT_ST_C_DQT_ID_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *JPEG_Type) GetINT_ST_C_DQT_ID_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *JPEG_Type) SetINT_ST_RST_UXP_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *JPEG_Type) GetINT_ST_RST_UXP_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *JPEG_Type) SetINT_ST_RST_CHECK_NONE_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *JPEG_Type) GetINT_ST_RST_CHECK_NONE_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *JPEG_Type) SetINT_ST_RST_CHECK_POS_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *JPEG_Type) GetINT_ST_RST_CHECK_POS_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *JPEG_Type) SetINT_ST_OUT_EOF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *JPEG_Type) GetINT_ST_OUT_EOF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *JPEG_Type) SetINT_ST_SR_COLOR_MODE_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *JPEG_Type) GetINT_ST_SR_COLOR_MODE_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *JPEG_Type) SetINT_ST_DCT_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *JPEG_Type) GetINT_ST_DCT_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *JPEG_Type) SetINT_ST_BS_LAST_BLOCK_EOF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *JPEG_Type) GetINT_ST_BS_LAST_BLOCK_EOF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *JPEG_Type) SetINT_ST_SCAN_CHECK_NONE_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *JPEG_Type) GetINT_ST_SCAN_CHECK_NONE_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *JPEG_Type) SetINT_ST_SCAN_CHECK_POS_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *JPEG_Type) GetINT_ST_SCAN_CHECK_POS_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *JPEG_Type) SetINT_ST_UXP_DET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *JPEG_Type) GetINT_ST_UXP_DET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}
func (o *JPEG_Type) SetINT_ST_EN_FRAME_EOF_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *JPEG_Type) GetINT_ST_EN_FRAME_EOF_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16
}
func (o *JPEG_Type) SetINT_ST_EN_FRAME_EOF_LACK_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *JPEG_Type) GetINT_ST_EN_FRAME_EOF_LACK_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17
}
func (o *JPEG_Type) SetINT_ST_DE_FRAME_EOF_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *JPEG_Type) GetINT_ST_DE_FRAME_EOF_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18
}
func (o *JPEG_Type) SetINT_ST_DE_FRAME_EOF_LACK_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *JPEG_Type) GetINT_ST_DE_FRAME_EOF_LACK_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19
}
func (o *JPEG_Type) SetINT_ST_SOS_UNMATCH_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *JPEG_Type) GetINT_ST_SOS_UNMATCH_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20
}
func (o *JPEG_Type) SetINT_ST_MARKER_ERR_FST_SCAN_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21)
}
func (o *JPEG_Type) GetINT_ST_MARKER_ERR_FST_SCAN_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21
}
func (o *JPEG_Type) SetINT_ST_MARKER_ERR_OTHER_SCAN_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22)
}
func (o *JPEG_Type) GetINT_ST_MARKER_ERR_OTHER_SCAN_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22
}
func (o *JPEG_Type) SetINT_ST_UNDET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23)
}
func (o *JPEG_Type) GetINT_ST_UNDET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23
}
func (o *JPEG_Type) SetINT_ST_DECODE_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24)
}
func (o *JPEG_Type) GetINT_ST_DECODE_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24
}

// JPEG.INT_CLR: Interrupt clear registers
func (o *JPEG_Type) SetINT_CLR_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *JPEG_Type) GetINT_CLR_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *JPEG_Type) SetINT_CLR_RLE_PARALLEL_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *JPEG_Type) GetINT_CLR_RLE_PARALLEL_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *JPEG_Type) SetINT_CLR_CID_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *JPEG_Type) GetINT_CLR_CID_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *JPEG_Type) SetINT_CLR_C_DHT_DC_ID_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *JPEG_Type) GetINT_CLR_C_DHT_DC_ID_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *JPEG_Type) SetINT_CLR_C_DHT_AC_ID_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *JPEG_Type) GetINT_CLR_C_DHT_AC_ID_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *JPEG_Type) SetINT_CLR_C_DQT_ID_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *JPEG_Type) GetINT_CLR_C_DQT_ID_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *JPEG_Type) SetINT_CLR_RST_UXP_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *JPEG_Type) GetINT_CLR_RST_UXP_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *JPEG_Type) SetINT_CLR_RST_CHECK_NONE_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *JPEG_Type) GetINT_CLR_RST_CHECK_NONE_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *JPEG_Type) SetINT_CLR_RST_CHECK_POS_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *JPEG_Type) GetINT_CLR_RST_CHECK_POS_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *JPEG_Type) SetINT_CLR_OUT_EOF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *JPEG_Type) GetINT_CLR_OUT_EOF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *JPEG_Type) SetINT_CLR_SR_COLOR_MODE_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *JPEG_Type) GetINT_CLR_SR_COLOR_MODE_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *JPEG_Type) SetINT_CLR_DCT_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *JPEG_Type) GetINT_CLR_DCT_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *JPEG_Type) SetINT_CLR_BS_LAST_BLOCK_EOF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *JPEG_Type) GetINT_CLR_BS_LAST_BLOCK_EOF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *JPEG_Type) SetINT_CLR_SCAN_CHECK_NONE_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *JPEG_Type) GetINT_CLR_SCAN_CHECK_NONE_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *JPEG_Type) SetINT_CLR_SCAN_CHECK_POS_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *JPEG_Type) GetINT_CLR_SCAN_CHECK_POS_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *JPEG_Type) SetINT_CLR_UXP_DET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *JPEG_Type) GetINT_CLR_UXP_DET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}
func (o *JPEG_Type) SetINT_CLR_EN_FRAME_EOF_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *JPEG_Type) GetINT_CLR_EN_FRAME_EOF_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16
}
func (o *JPEG_Type) SetINT_CLR_EN_FRAME_EOF_LACK_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *JPEG_Type) GetINT_CLR_EN_FRAME_EOF_LACK_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17
}
func (o *JPEG_Type) SetINT_CLR_DE_FRAME_EOF_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *JPEG_Type) GetINT_CLR_DE_FRAME_EOF_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}
func (o *JPEG_Type) SetINT_CLR_DE_FRAME_EOF_LACK_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *JPEG_Type) GetINT_CLR_DE_FRAME_EOF_LACK_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19
}
func (o *JPEG_Type) SetINT_CLR_SOS_UNMATCH_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *JPEG_Type) GetINT_CLR_SOS_UNMATCH_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20
}
func (o *JPEG_Type) SetINT_CLR_MARKER_ERR_FST_SCAN_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *JPEG_Type) GetINT_CLR_MARKER_ERR_FST_SCAN_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21
}
func (o *JPEG_Type) SetINT_CLR_MARKER_ERR_OTHER_SCAN_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *JPEG_Type) GetINT_CLR_MARKER_ERR_OTHER_SCAN_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22
}
func (o *JPEG_Type) SetINT_CLR_UNDET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *JPEG_Type) GetINT_CLR_UNDET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23
}
func (o *JPEG_Type) SetINT_CLR_DECODE_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *JPEG_Type) GetINT_CLR_DECODE_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24
}

// JPEG.STATUS0: Trace and Debug registers
func (o *JPEG_Type) SetSTATUS0_BITSTREAM_EOF_VLD_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0x1f800)|value<<11)
}
func (o *JPEG_Type) GetSTATUS0_BITSTREAM_EOF_VLD_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS0.Reg) & 0x1f800) >> 11
}
func (o *JPEG_Type) SetSTATUS0_DCTOUT_ZZSCAN_ADDR(value uint32) {
	volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0x7e0000)|value<<17)
}
func (o *JPEG_Type) GetSTATUS0_DCTOUT_ZZSCAN_ADDR() uint32 {
	return (volatile.LoadUint32(&o.STATUS0.Reg) & 0x7e0000) >> 17
}
func (o *JPEG_Type) SetSTATUS0_QNRVAL_ZZSCAN_ADDR(value uint32) {
	volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0x1f800000)|value<<23)
}
func (o *JPEG_Type) GetSTATUS0_QNRVAL_ZZSCAN_ADDR() uint32 {
	return (volatile.LoadUint32(&o.STATUS0.Reg) & 0x1f800000) >> 23
}
func (o *JPEG_Type) SetSTATUS0_REG_STATE_YUV(value uint32) {
	volatile.StoreUint32(&o.STATUS0.Reg, volatile.LoadUint32(&o.STATUS0.Reg)&^(0xe0000000)|value<<29)
}
func (o *JPEG_Type) GetSTATUS0_REG_STATE_YUV() uint32 {
	return (volatile.LoadUint32(&o.STATUS0.Reg) & 0xe0000000) >> 29
}

// JPEG.STATUS2: Trace and Debug registers
func (o *JPEG_Type) SetSTATUS2_SOURCE_PIXEL(value uint32) {
	volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0xffffff)|value)
}
func (o *JPEG_Type) GetSTATUS2_SOURCE_PIXEL() uint32 {
	return volatile.LoadUint32(&o.STATUS2.Reg) & 0xffffff
}
func (o *JPEG_Type) SetSTATUS2_LAST_BLOCK(value uint32) {
	volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x1000000)|value<<24)
}
func (o *JPEG_Type) GetSTATUS2_LAST_BLOCK() uint32 {
	return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x1000000) >> 24
}
func (o *JPEG_Type) SetSTATUS2_LAST_MCU(value uint32) {
	volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x2000000)|value<<25)
}
func (o *JPEG_Type) GetSTATUS2_LAST_MCU() uint32 {
	return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x2000000) >> 25
}
func (o *JPEG_Type) SetSTATUS2_LAST_DC(value uint32) {
	volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x4000000)|value<<26)
}
func (o *JPEG_Type) GetSTATUS2_LAST_DC() uint32 {
	return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x4000000) >> 26
}
func (o *JPEG_Type) SetSTATUS2_PACKFIFO_READY(value uint32) {
	volatile.StoreUint32(&o.STATUS2.Reg, volatile.LoadUint32(&o.STATUS2.Reg)&^(0x8000000)|value<<27)
}
func (o *JPEG_Type) GetSTATUS2_PACKFIFO_READY() uint32 {
	return (volatile.LoadUint32(&o.STATUS2.Reg) & 0x8000000) >> 27
}

// JPEG.STATUS3: Trace and Debug registers
func (o *JPEG_Type) SetSTATUS3_YO(value uint32) {
	volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x1ff)|value)
}
func (o *JPEG_Type) GetSTATUS3_YO() uint32 {
	return volatile.LoadUint32(&o.STATUS3.Reg) & 0x1ff
}
func (o *JPEG_Type) SetSTATUS3_Y_READY(value uint32) {
	volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x200)|value<<9)
}
func (o *JPEG_Type) GetSTATUS3_Y_READY() uint32 {
	return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x200) >> 9
}
func (o *JPEG_Type) SetSTATUS3_CBO(value uint32) {
	volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x7fc00)|value<<10)
}
func (o *JPEG_Type) GetSTATUS3_CBO() uint32 {
	return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x7fc00) >> 10
}
func (o *JPEG_Type) SetSTATUS3_CB_READY(value uint32) {
	volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x80000)|value<<19)
}
func (o *JPEG_Type) GetSTATUS3_CB_READY() uint32 {
	return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x80000) >> 19
}
func (o *JPEG_Type) SetSTATUS3_CRO(value uint32) {
	volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x1ff00000)|value<<20)
}
func (o *JPEG_Type) GetSTATUS3_CRO() uint32 {
	return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x1ff00000) >> 20
}
func (o *JPEG_Type) SetSTATUS3_CR_READY(value uint32) {
	volatile.StoreUint32(&o.STATUS3.Reg, volatile.LoadUint32(&o.STATUS3.Reg)&^(0x20000000)|value<<29)
}
func (o *JPEG_Type) GetSTATUS3_CR_READY() uint32 {
	return (volatile.LoadUint32(&o.STATUS3.Reg) & 0x20000000) >> 29
}

// JPEG.STATUS4: Trace and Debug registers
func (o *JPEG_Type) SetSTATUS4(value uint32) {
	volatile.StoreUint32(&o.STATUS4.Reg, value)
}
func (o *JPEG_Type) GetSTATUS4() uint32 {
	return volatile.LoadUint32(&o.STATUS4.Reg)
}

// JPEG.DHT_TOTLEN_DC0: Trace and Debug registers
func (o *JPEG_Type) SetDHT_TOTLEN_DC0(value uint32) {
	volatile.StoreUint32(&o.DHT_TOTLEN_DC0.Reg, value)
}
func (o *JPEG_Type) GetDHT_TOTLEN_DC0() uint32 {
	return volatile.LoadUint32(&o.DHT_TOTLEN_DC0.Reg)
}

// JPEG.DHT_VAl_DC0: Trace and Debug registers
func (o *JPEG_Type) SetDHT_VAl_DC0(value uint32) {
	volatile.StoreUint32(&o.DHT_VAl_DC0.Reg, value)
}
func (o *JPEG_Type) GetDHT_VAl_DC0() uint32 {
	return volatile.LoadUint32(&o.DHT_VAl_DC0.Reg)
}

// JPEG.DHT_TOTLEN_AC0: Trace and Debug registers
func (o *JPEG_Type) SetDHT_TOTLEN_AC0(value uint32) {
	volatile.StoreUint32(&o.DHT_TOTLEN_AC0.Reg, value)
}
func (o *JPEG_Type) GetDHT_TOTLEN_AC0() uint32 {
	return volatile.LoadUint32(&o.DHT_TOTLEN_AC0.Reg)
}

// JPEG.DHT_VAl_AC0: Trace and Debug registers
func (o *JPEG_Type) SetDHT_VAl_AC0(value uint32) {
	volatile.StoreUint32(&o.DHT_VAl_AC0.Reg, value)
}
func (o *JPEG_Type) GetDHT_VAl_AC0() uint32 {
	return volatile.LoadUint32(&o.DHT_VAl_AC0.Reg)
}

// JPEG.DHT_TOTLEN_DC1: Trace and Debug registers
func (o *JPEG_Type) SetDHT_TOTLEN_DC1(value uint32) {
	volatile.StoreUint32(&o.DHT_TOTLEN_DC1.Reg, value)
}
func (o *JPEG_Type) GetDHT_TOTLEN_DC1() uint32 {
	return volatile.LoadUint32(&o.DHT_TOTLEN_DC1.Reg)
}

// JPEG.DHT_VAl_DC1: Trace and Debug registers
func (o *JPEG_Type) SetDHT_VAl_DC1(value uint32) {
	volatile.StoreUint32(&o.DHT_VAl_DC1.Reg, value)
}
func (o *JPEG_Type) GetDHT_VAl_DC1() uint32 {
	return volatile.LoadUint32(&o.DHT_VAl_DC1.Reg)
}

// JPEG.DHT_TOTLEN_AC1: Trace and Debug registers
func (o *JPEG_Type) SetDHT_TOTLEN_AC1(value uint32) {
	volatile.StoreUint32(&o.DHT_TOTLEN_AC1.Reg, value)
}
func (o *JPEG_Type) GetDHT_TOTLEN_AC1() uint32 {
	return volatile.LoadUint32(&o.DHT_TOTLEN_AC1.Reg)
}

// JPEG.DHT_VAl_AC1: Trace and Debug registers
func (o *JPEG_Type) SetDHT_VAl_AC1(value uint32) {
	volatile.StoreUint32(&o.DHT_VAl_AC1.Reg, value)
}
func (o *JPEG_Type) GetDHT_VAl_AC1() uint32 {
	return volatile.LoadUint32(&o.DHT_VAl_AC1.Reg)
}

// JPEG.DHT_CODEMIN_DC0: Trace and Debug registers
func (o *JPEG_Type) SetDHT_CODEMIN_DC0(value uint32) {
	volatile.StoreUint32(&o.DHT_CODEMIN_DC0.Reg, value)
}
func (o *JPEG_Type) GetDHT_CODEMIN_DC0() uint32 {
	return volatile.LoadUint32(&o.DHT_CODEMIN_DC0.Reg)
}

// JPEG.DHT_CODEMIN_AC0: Trace and Debug registers
func (o *JPEG_Type) SetDHT_CODEMIN_AC0(value uint32) {
	volatile.StoreUint32(&o.DHT_CODEMIN_AC0.Reg, value)
}
func (o *JPEG_Type) GetDHT_CODEMIN_AC0() uint32 {
	return volatile.LoadUint32(&o.DHT_CODEMIN_AC0.Reg)
}

// JPEG.DHT_CODEMIN_DC1: Trace and Debug registers
func (o *JPEG_Type) SetDHT_CODEMIN_DC1(value uint32) {
	volatile.StoreUint32(&o.DHT_CODEMIN_DC1.Reg, value)
}
func (o *JPEG_Type) GetDHT_CODEMIN_DC1() uint32 {
	return volatile.LoadUint32(&o.DHT_CODEMIN_DC1.Reg)
}

// JPEG.DHT_CODEMIN_AC1: Trace and Debug registers
func (o *JPEG_Type) SetDHT_CODEMIN_AC1(value uint32) {
	volatile.StoreUint32(&o.DHT_CODEMIN_AC1.Reg, value)
}
func (o *JPEG_Type) GetDHT_CODEMIN_AC1() uint32 {
	return volatile.LoadUint32(&o.DHT_CODEMIN_AC1.Reg)
}

// JPEG.DECODER_STATUS0: Trace and Debug registers
func (o *JPEG_Type) SetDECODER_STATUS0_DECODE_BYTE_CNT(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS0.Reg, volatile.LoadUint32(&o.DECODER_STATUS0.Reg)&^(0x3ffffff)|value)
}
func (o *JPEG_Type) GetDECODER_STATUS0_DECODE_BYTE_CNT() uint32 {
	return volatile.LoadUint32(&o.DECODER_STATUS0.Reg) & 0x3ffffff
}
func (o *JPEG_Type) SetDECODER_STATUS0_HEADER_DEC_ST(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS0.Reg, volatile.LoadUint32(&o.DECODER_STATUS0.Reg)&^(0x3c000000)|value<<26)
}
func (o *JPEG_Type) GetDECODER_STATUS0_HEADER_DEC_ST() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS0.Reg) & 0x3c000000) >> 26
}
func (o *JPEG_Type) SetDECODER_STATUS0_DECODE_SAMPLE_SEL(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS0.Reg, volatile.LoadUint32(&o.DECODER_STATUS0.Reg)&^(0xc0000000)|value<<30)
}
func (o *JPEG_Type) GetDECODER_STATUS0_DECODE_SAMPLE_SEL() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS0.Reg) & 0xc0000000) >> 30
}

// JPEG.DECODER_STATUS1: Trace and Debug registers
func (o *JPEG_Type) SetDECODER_STATUS1_ENCODE_DATA(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0xffff)|value)
}
func (o *JPEG_Type) GetDECODER_STATUS1_ENCODE_DATA() uint32 {
	return volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0xffff
}
func (o *JPEG_Type) SetDECODER_STATUS1_COUNT_Q(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0x7f0000)|value<<16)
}
func (o *JPEG_Type) GetDECODER_STATUS1_COUNT_Q() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0x7f0000) >> 16
}
func (o *JPEG_Type) SetDECODER_STATUS1_MCU_FSM_READY(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0x800000)|value<<23)
}
func (o *JPEG_Type) GetDECODER_STATUS1_MCU_FSM_READY() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0x800000) >> 23
}
func (o *JPEG_Type) SetDECODER_STATUS1_DECODE_DATA(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS1.Reg, volatile.LoadUint32(&o.DECODER_STATUS1.Reg)&^(0xff000000)|value<<24)
}
func (o *JPEG_Type) GetDECODER_STATUS1_DECODE_DATA() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS1.Reg) & 0xff000000) >> 24
}

// JPEG.DECODER_STATUS2: Trace and Debug registers
func (o *JPEG_Type) SetDECODER_STATUS2_COMP_BLOCK_NUM(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x3ffffff)|value)
}
func (o *JPEG_Type) GetDECODER_STATUS2_COMP_BLOCK_NUM() uint32 {
	return volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x3ffffff
}
func (o *JPEG_Type) SetDECODER_STATUS2_SCAN_NUM(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x1c000000)|value<<26)
}
func (o *JPEG_Type) GetDECODER_STATUS2_SCAN_NUM() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x1c000000) >> 26
}
func (o *JPEG_Type) SetDECODER_STATUS2_RST_CHECK_WAIT(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x20000000)|value<<29)
}
func (o *JPEG_Type) GetDECODER_STATUS2_RST_CHECK_WAIT() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x20000000) >> 29
}
func (o *JPEG_Type) SetDECODER_STATUS2_SCAN_CHECK_WAIT(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x40000000)|value<<30)
}
func (o *JPEG_Type) GetDECODER_STATUS2_SCAN_CHECK_WAIT() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x40000000) >> 30
}
func (o *JPEG_Type) SetDECODER_STATUS2_MCU_IN_PROC(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS2.Reg, volatile.LoadUint32(&o.DECODER_STATUS2.Reg)&^(0x80000000)|value<<31)
}
func (o *JPEG_Type) GetDECODER_STATUS2_MCU_IN_PROC() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS2.Reg) & 0x80000000) >> 31
}

// JPEG.DECODER_STATUS3: Trace and Debug registers
func (o *JPEG_Type) SetDECODER_STATUS3(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS3.Reg, value)
}
func (o *JPEG_Type) GetDECODER_STATUS3() uint32 {
	return volatile.LoadUint32(&o.DECODER_STATUS3.Reg)
}

// JPEG.DECODER_STATUS4: Trace and Debug registers
func (o *JPEG_Type) SetDECODER_STATUS4_BLOCK_EOF_CNT(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x3ffffff)|value)
}
func (o *JPEG_Type) GetDECODER_STATUS4_BLOCK_EOF_CNT() uint32 {
	return volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x3ffffff
}
func (o *JPEG_Type) SetDECODER_STATUS4_DEZIGZAG_READY(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x4000000)|value<<26)
}
func (o *JPEG_Type) GetDECODER_STATUS4_DEZIGZAG_READY() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x4000000) >> 26
}
func (o *JPEG_Type) SetDECODER_STATUS4_DE_FRAME_EOF_CHECK(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x8000000)|value<<27)
}
func (o *JPEG_Type) GetDECODER_STATUS4_DE_FRAME_EOF_CHECK() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x8000000) >> 27
}
func (o *JPEG_Type) SetDECODER_STATUS4_DE_DMA2D_IN_PUSH(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS4.Reg, volatile.LoadUint32(&o.DECODER_STATUS4.Reg)&^(0x10000000)|value<<28)
}
func (o *JPEG_Type) GetDECODER_STATUS4_DE_DMA2D_IN_PUSH() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS4.Reg) & 0x10000000) >> 28
}

// JPEG.DECODER_STATUS5: Trace and Debug registers
func (o *JPEG_Type) SetDECODER_STATUS5_IDCT_HFM_DATA(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0xffff)|value)
}
func (o *JPEG_Type) GetDECODER_STATUS5_IDCT_HFM_DATA() uint32 {
	return volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0xffff
}
func (o *JPEG_Type) SetDECODER_STATUS5_NS0(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x70000)|value<<16)
}
func (o *JPEG_Type) GetDECODER_STATUS5_NS0() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x70000) >> 16
}
func (o *JPEG_Type) SetDECODER_STATUS5_NS1(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x380000)|value<<19)
}
func (o *JPEG_Type) GetDECODER_STATUS5_NS1() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x380000) >> 19
}
func (o *JPEG_Type) SetDECODER_STATUS5_NS2(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x1c00000)|value<<22)
}
func (o *JPEG_Type) GetDECODER_STATUS5_NS2() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x1c00000) >> 22
}
func (o *JPEG_Type) SetDECODER_STATUS5_NS3(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0xe000000)|value<<25)
}
func (o *JPEG_Type) GetDECODER_STATUS5_NS3() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0xe000000) >> 25
}
func (o *JPEG_Type) SetDECODER_STATUS5_DATA_LAST_O(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x10000000)|value<<28)
}
func (o *JPEG_Type) GetDECODER_STATUS5_DATA_LAST_O() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x10000000) >> 28
}
func (o *JPEG_Type) SetDECODER_STATUS5_RDN_RESULT(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x20000000)|value<<29)
}
func (o *JPEG_Type) GetDECODER_STATUS5_RDN_RESULT() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x20000000) >> 29
}
func (o *JPEG_Type) SetDECODER_STATUS5_RDN_ENA(value uint32) {
	volatile.StoreUint32(&o.DECODER_STATUS5.Reg, volatile.LoadUint32(&o.DECODER_STATUS5.Reg)&^(0x40000000)|value<<30)
}
func (o *JPEG_Type) GetDECODER_STATUS5_RDN_ENA() uint32 {
	return (volatile.LoadUint32(&o.DECODER_STATUS5.Reg) & 0x40000000) >> 30
}

// JPEG.STATUS5: Trace and Debug registers
func (o *JPEG_Type) SetSTATUS5_PIC_BLOCK_NUM(value uint32) {
	volatile.StoreUint32(&o.STATUS5.Reg, volatile.LoadUint32(&o.STATUS5.Reg)&^(0xffffff)|value)
}
func (o *JPEG_Type) GetSTATUS5_PIC_BLOCK_NUM() uint32 {
	return volatile.LoadUint32(&o.STATUS5.Reg) & 0xffffff
}

// JPEG.ECO_LOW: Trace and Debug registers
func (o *JPEG_Type) SetECO_LOW(value uint32) {
	volatile.StoreUint32(&o.ECO_LOW.Reg, value)
}
func (o *JPEG_Type) GetECO_LOW() uint32 {
	return volatile.LoadUint32(&o.ECO_LOW.Reg)
}

// JPEG.ECO_HIGH: Trace and Debug registers
func (o *JPEG_Type) SetECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.ECO_HIGH.Reg, value)
}
func (o *JPEG_Type) GetECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.ECO_HIGH.Reg)
}

// JPEG.SYS: Trace and Debug registers
func (o *JPEG_Type) SetSYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SYS.Reg, volatile.LoadUint32(&o.SYS.Reg)&^(0x80000000)|value<<31)
}
func (o *JPEG_Type) GetSYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SYS.Reg) & 0x80000000) >> 31
}

// JPEG.VERSION: Trace and Debug registers
func (o *JPEG_Type) SetVERSION_JPEG_VER(value uint32) {
	volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value)
}
func (o *JPEG_Type) GetVERSION_JPEG_VER() uint32 {
	return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff
}

// Camera/LCD Controller
type LCDCAM_Type struct {
	LCD_CLOCK          volatile.Register32 // 0x0
	CAM_CTRL           volatile.Register32 // 0x4
	CAM_CTRL1          volatile.Register32 // 0x8
	CAM_RGB_YUV        volatile.Register32 // 0xC
	LCD_RGB_YUV        volatile.Register32 // 0x10
	LCD_USER           volatile.Register32 // 0x14
	LCD_MISC           volatile.Register32 // 0x18
	LCD_CTRL           volatile.Register32 // 0x1C
	LCD_CTRL1          volatile.Register32 // 0x20
	LCD_CTRL2          volatile.Register32 // 0x24
	LCD_FIRST_CMD_VAL  volatile.Register32 // 0x28
	LCD_LATTER_CMD_VAL volatile.Register32 // 0x2C
	LCD_DLY_MODE_CFG1  volatile.Register32 // 0x30
	_                  [4]byte
	LCD_DLY_MODE_CFG2  volatile.Register32 // 0x38
	_                  [40]byte
	LC_DMA_INT_ENA     volatile.Register32 // 0x64
	LC_DMA_INT_RAW     volatile.Register32 // 0x68
	LC_DMA_INT_ST      volatile.Register32 // 0x6C
	LC_DMA_INT_CLR     volatile.Register32 // 0x70
	_                  [136]byte
	LC_REG_DATE        volatile.Register32 // 0xFC
}

// LCDCAM.LCD_CLOCK: LCD clock config register.
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKCNT_N(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x3f)|value)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKCNT_N() uint32 {
	return volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x3f
}
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLK_EQU_SYSCLK(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x40)|value<<6)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLK_EQU_SYSCLK() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x40) >> 6
}
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CK_IDLE_EDGE(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x80)|value<<7)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CK_IDLE_EDGE() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x80) >> 7
}
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CK_OUT_EDGE(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x100)|value<<8)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CK_OUT_EDGE() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x100) >> 8
}
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x1fe00)|value<<9)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x1fe00) >> 9
}
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_B(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x7e0000)|value<<17)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_B() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x7e0000) >> 17
}
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLKM_DIV_A(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x1f800000)|value<<23)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLKM_DIV_A() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x1f800000) >> 23
}
func (o *LCDCAM_Type) SetLCD_CLOCK_LCD_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x60000000)|value<<29)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_LCD_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x60000000) >> 29
}
func (o *LCDCAM_Type) SetLCD_CLOCK_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LCD_CLOCK.Reg, volatile.LoadUint32(&o.LCD_CLOCK.Reg)&^(0x80000000)|value<<31)
}
func (o *LCDCAM_Type) GetLCD_CLOCK_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LCD_CLOCK.Reg) & 0x80000000) >> 31
}

// LCDCAM.CAM_CTRL: CAM config register.
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_STOP_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1)|value)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_STOP_EN() uint32 {
	return volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_VSYNC_FILTER_THRES(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0xe)|value<<1)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_VSYNC_FILTER_THRES() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0xe) >> 1
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_UPDATE(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x10) >> 4
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_BYTE_ORDER(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_BYTE_ORDER() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x20) >> 5
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x40) >> 6
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_LINE_INT_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_LINE_INT_EN() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x80) >> 7
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_VS_EOF_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_VS_EOF_EN() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x100) >> 8
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1fe00)|value<<9)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1fe00) >> 9
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_B(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x7e0000)|value<<17)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_B() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x7e0000) >> 17
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLKM_DIV_A(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x1f800000)|value<<23)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLKM_DIV_A() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x1f800000) >> 23
}
func (o *LCDCAM_Type) SetCAM_CTRL_CAM_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL.Reg, volatile.LoadUint32(&o.CAM_CTRL.Reg)&^(0x60000000)|value<<29)
}
func (o *LCDCAM_Type) GetCAM_CTRL_CAM_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL.Reg) & 0x60000000) >> 29
}

// LCDCAM.CAM_CTRL1: CAM config register.
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_REC_DATA_BYTELEN(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0xffff)|value)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_REC_DATA_BYTELEN() uint32 {
	return volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0xffff
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_LINE_INT_NUM(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x3f0000)|value<<16)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_LINE_INT_NUM() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x3f0000) >> 16
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_CLK_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x400000)|value<<22)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_CLK_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x400000) >> 22
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_VSYNC_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x800000)|value<<23)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_VSYNC_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x800000) >> 23
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_2BYTE_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x1000000)|value<<24)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_2BYTE_EN() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x1000000) >> 24
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_DE_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x2000000)|value<<25)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_DE_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x2000000) >> 25
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_HSYNC_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x4000000)|value<<26)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_HSYNC_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x4000000) >> 26
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_VSYNC_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x8000000)|value<<27)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_VSYNC_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x8000000) >> 27
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_VH_DE_MODE_EN(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x10000000)|value<<28)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_VH_DE_MODE_EN() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x10000000) >> 28
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_START(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x20000000)|value<<29)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_START() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x20000000) >> 29
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_RESET(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x40000000)|value<<30)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_RESET() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x40000000) >> 30
}
func (o *LCDCAM_Type) SetCAM_CTRL1_CAM_AFIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.CAM_CTRL1.Reg, volatile.LoadUint32(&o.CAM_CTRL1.Reg)&^(0x80000000)|value<<31)
}
func (o *LCDCAM_Type) GetCAM_CTRL1_CAM_AFIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.CAM_CTRL1.Reg) & 0x80000000) >> 31
}

// LCDCAM.CAM_RGB_YUV: CAM YUV/RGB converter configuration register.
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x200000)|value<<21)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x200000) >> 21
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0xc00000)|value<<22)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0xc00000) >> 22
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_YUV_MODE(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x3000000)|value<<24)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_YUV_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x3000000) >> 24
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x4000000)|value<<26)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x4000000) >> 26
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x8000000)|value<<27)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x8000000) >> 27
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_DATA_IN_MODE(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x10000000)|value<<28)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_DATA_IN_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x10000000) >> 28
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x20000000)|value<<29)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x20000000) >> 29
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_TRANS_MODE(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x40000000)|value<<30)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_TRANS_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x40000000) >> 30
}
func (o *LCDCAM_Type) SetCAM_RGB_YUV_CAM_CONV_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CAM_RGB_YUV.Reg, volatile.LoadUint32(&o.CAM_RGB_YUV.Reg)&^(0x80000000)|value<<31)
}
func (o *LCDCAM_Type) GetCAM_RGB_YUV_CAM_CONV_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.CAM_RGB_YUV.Reg) & 0x80000000) >> 31
}

// LCDCAM.LCD_RGB_YUV: LCD YUV/RGB converter configuration register.
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x100000)|value<<20)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x100000) >> 20
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_TXTORX(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x200000)|value<<21)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_TXTORX() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x200000) >> 21
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0xc00000)|value<<22)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0xc00000) >> 22
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_YUV_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x3000000)|value<<24)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_YUV_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x3000000) >> 24
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x4000000)|value<<26)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x4000000) >> 26
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x8000000)|value<<27)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x8000000) >> 27
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_DATA_IN_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x10000000)|value<<28)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_DATA_IN_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x10000000) >> 28
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x20000000)|value<<29)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x20000000) >> 29
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_TRANS_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x40000000)|value<<30)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_TRANS_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x40000000) >> 30
}
func (o *LCDCAM_Type) SetLCD_RGB_YUV_LCD_CONV_ENABLE(value uint32) {
	volatile.StoreUint32(&o.LCD_RGB_YUV.Reg, volatile.LoadUint32(&o.LCD_RGB_YUV.Reg)&^(0x80000000)|value<<31)
}
func (o *LCDCAM_Type) GetLCD_RGB_YUV_LCD_CONV_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.LCD_RGB_YUV.Reg) & 0x80000000) >> 31
}

// LCDCAM.LCD_USER: LCD config register.
func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1fff)|value)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_CYCLELEN() uint32 {
	return volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1fff
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_ALWAYS_OUT_EN(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x2000)|value<<13)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_ALWAYS_OUT_EN() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x2000) >> 13
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1c000)|value<<14)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1c000) >> 14
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_ENABLE(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x20000)|value<<17)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_BYTE_SWIZZLE_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x20000) >> 17
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x40000)|value<<18)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x40000) >> 18
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_BYTE_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x180000)|value<<19)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_BYTE_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x180000) >> 19
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_UPDATE(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x200000)|value<<21)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x200000) >> 21
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x400000)|value<<22)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x400000) >> 22
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_BYTE_ORDER(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x800000)|value<<23)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_BYTE_ORDER() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x800000) >> 23
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_DOUT(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x1000000)|value<<24)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_DOUT() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x1000000) >> 24
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_DUMMY(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x2000000)|value<<25)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x2000000) >> 25
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_CMD(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x4000000)|value<<26)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_CMD() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x4000000) >> 26
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_START(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x8000000)|value<<27)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_START() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x8000000) >> 27
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_RESET(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x10000000)|value<<28)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_RESET() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x10000000) >> 28
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x60000000)|value<<29)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_DUMMY_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x60000000) >> 29
}
func (o *LCDCAM_Type) SetLCD_USER_LCD_CMD_2_CYCLE_EN(value uint32) {
	volatile.StoreUint32(&o.LCD_USER.Reg, volatile.LoadUint32(&o.LCD_USER.Reg)&^(0x80000000)|value<<31)
}
func (o *LCDCAM_Type) GetLCD_USER_LCD_CMD_2_CYCLE_EN() uint32 {
	return (volatile.LoadUint32(&o.LCD_USER.Reg) & 0x80000000) >> 31
}

// LCDCAM.LCD_MISC: LCD config register.
func (o *LCDCAM_Type) SetLCD_MISC_LCD_WIRE_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x30)|value<<4)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_WIRE_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x30) >> 4
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_VFK_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0xfc0)|value<<6)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_VFK_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0xfc0) >> 6
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_VBK_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x1fff000)|value<<12)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_VBK_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x1fff000) >> 12
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_NEXT_FRAME_EN(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x2000000)|value<<25)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_NEXT_FRAME_EN() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x2000000) >> 25
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_BK_EN(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x4000000)|value<<26)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_BK_EN() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x4000000) >> 26
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_AFIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x8000000)|value<<27)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_AFIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x8000000) >> 27
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_DATA_SET(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x10000000)|value<<28)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_DATA_SET() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x10000000) >> 28
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_DUMMY_SET(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x20000000)|value<<29)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_DUMMY_SET() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x20000000) >> 29
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_CMD_SET(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x40000000)|value<<30)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_CMD_SET() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x40000000) >> 30
}
func (o *LCDCAM_Type) SetLCD_MISC_LCD_CD_IDLE_EDGE(value uint32) {
	volatile.StoreUint32(&o.LCD_MISC.Reg, volatile.LoadUint32(&o.LCD_MISC.Reg)&^(0x80000000)|value<<31)
}
func (o *LCDCAM_Type) GetLCD_MISC_LCD_CD_IDLE_EDGE() uint32 {
	return (volatile.LoadUint32(&o.LCD_MISC.Reg) & 0x80000000) >> 31
}

// LCDCAM.LCD_CTRL: LCD config register.
func (o *LCDCAM_Type) SetLCD_CTRL_LCD_HB_FRONT(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7ff)|value)
}
func (o *LCDCAM_Type) GetLCD_CTRL_LCD_HB_FRONT() uint32 {
	return volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7ff
}
func (o *LCDCAM_Type) SetLCD_CTRL_LCD_VA_HEIGHT(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x1ff800)|value<<11)
}
func (o *LCDCAM_Type) GetLCD_CTRL_LCD_VA_HEIGHT() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x1ff800) >> 11
}
func (o *LCDCAM_Type) SetLCD_CTRL_LCD_VT_HEIGHT(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x7fe00000)|value<<21)
}
func (o *LCDCAM_Type) GetLCD_CTRL_LCD_VT_HEIGHT() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x7fe00000) >> 21
}
func (o *LCDCAM_Type) SetLCD_CTRL_LCD_RGB_MODE_EN(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL.Reg, volatile.LoadUint32(&o.LCD_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *LCDCAM_Type) GetLCD_CTRL_LCD_RGB_MODE_EN() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL.Reg) & 0x80000000) >> 31
}

// LCDCAM.LCD_CTRL1: LCD config register.
func (o *LCDCAM_Type) SetLCD_CTRL1_LCD_VB_FRONT(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xff)|value)
}
func (o *LCDCAM_Type) GetLCD_CTRL1_LCD_VB_FRONT() uint32 {
	return volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xff
}
func (o *LCDCAM_Type) SetLCD_CTRL1_LCD_HA_WIDTH(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00)|value<<8)
}
func (o *LCDCAM_Type) GetLCD_CTRL1_LCD_HA_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00) >> 8
}
func (o *LCDCAM_Type) SetLCD_CTRL1_LCD_HT_WIDTH(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL1.Reg, volatile.LoadUint32(&o.LCD_CTRL1.Reg)&^(0xfff00000)|value<<20)
}
func (o *LCDCAM_Type) GetLCD_CTRL1_LCD_HT_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL1.Reg) & 0xfff00000) >> 20
}

// LCDCAM.LCD_CTRL2: LCD config register.
func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_VSYNC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f)|value)
}
func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_VSYNC_WIDTH() uint32 {
	return volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f
}
func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_VSYNC_IDLE_POL(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x80)|value<<7)
}
func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_VSYNC_IDLE_POL() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x80) >> 7
}
func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_DE_IDLE_POL(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x100)|value<<8)
}
func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_DE_IDLE_POL() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x100) >> 8
}
func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HS_BLANK_EN(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x200)|value<<9)
}
func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HS_BLANK_EN() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x200) >> 9
}
func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HSYNC_WIDTH(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x7f0000)|value<<16)
}
func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HSYNC_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x7f0000) >> 16
}
func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HSYNC_IDLE_POL(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0x800000)|value<<23)
}
func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HSYNC_IDLE_POL() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0x800000) >> 23
}
func (o *LCDCAM_Type) SetLCD_CTRL2_LCD_HSYNC_POSITION(value uint32) {
	volatile.StoreUint32(&o.LCD_CTRL2.Reg, volatile.LoadUint32(&o.LCD_CTRL2.Reg)&^(0xff000000)|value<<24)
}
func (o *LCDCAM_Type) GetLCD_CTRL2_LCD_HSYNC_POSITION() uint32 {
	return (volatile.LoadUint32(&o.LCD_CTRL2.Reg) & 0xff000000) >> 24
}

// LCDCAM.LCD_FIRST_CMD_VAL: LCD config register.
func (o *LCDCAM_Type) SetLCD_FIRST_CMD_VAL(value uint32) {
	volatile.StoreUint32(&o.LCD_FIRST_CMD_VAL.Reg, value)
}
func (o *LCDCAM_Type) GetLCD_FIRST_CMD_VAL() uint32 {
	return volatile.LoadUint32(&o.LCD_FIRST_CMD_VAL.Reg)
}

// LCDCAM.LCD_LATTER_CMD_VAL: LCD config register.
func (o *LCDCAM_Type) SetLCD_LATTER_CMD_VAL(value uint32) {
	volatile.StoreUint32(&o.LCD_LATTER_CMD_VAL.Reg, value)
}
func (o *LCDCAM_Type) GetLCD_LATTER_CMD_VAL() uint32 {
	return volatile.LoadUint32(&o.LCD_LATTER_CMD_VAL.Reg)
}

// LCDCAM.LCD_DLY_MODE_CFG1: LCD config register.
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT16_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x3)|value)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT16_MODE() uint32 {
	return volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x3
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT17_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc)|value<<2)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT17_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc) >> 2
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT18_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x30)|value<<4)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT18_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x30) >> 4
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT19_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc0)|value<<6)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT19_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc0) >> 6
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT20_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x300)|value<<8)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT20_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x300) >> 8
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT21_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc00)|value<<10)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT21_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc00) >> 10
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT22_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x3000)|value<<12)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT22_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x3000) >> 12
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_DOUT23_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc000)|value<<14)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_DOUT23_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc000) >> 14
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_CD_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x30000)|value<<16)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_CD_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x30000) >> 16
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_DE_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc0000)|value<<18)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_DE_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc0000) >> 18
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_HSYNC_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0x300000)|value<<20)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_HSYNC_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0x300000) >> 20
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG1_LCD_VSYNC_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG1.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg)&^(0xc00000)|value<<22)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG1_LCD_VSYNC_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG1.Reg) & 0xc00000) >> 22
}

// LCDCAM.LCD_DLY_MODE_CFG2: LCD config register.
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT0_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x3)|value)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT0_MODE() uint32 {
	return volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x3
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT1_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc)|value<<2)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT1_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc) >> 2
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT2_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x30)|value<<4)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT2_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x30) >> 4
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT3_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc0)|value<<6)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT3_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc0) >> 6
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT4_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x300)|value<<8)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT4_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x300) >> 8
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT5_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc00)|value<<10)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT5_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc00) >> 10
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT6_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x3000)|value<<12)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT6_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x3000) >> 12
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT7_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc000)|value<<14)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT7_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc000) >> 14
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT8_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x30000)|value<<16)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT8_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x30000) >> 16
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT9_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc0000)|value<<18)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT9_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc0000) >> 18
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT10_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x300000)|value<<20)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT10_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x300000) >> 20
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT11_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc00000)|value<<22)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT11_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc00000) >> 22
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT12_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x3000000)|value<<24)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT12_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x3000000) >> 24
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT13_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc000000)|value<<26)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT13_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc000000) >> 26
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT14_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0x30000000)|value<<28)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT14_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0x30000000) >> 28
}
func (o *LCDCAM_Type) SetLCD_DLY_MODE_CFG2_DOUT15_MODE(value uint32) {
	volatile.StoreUint32(&o.LCD_DLY_MODE_CFG2.Reg, volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg)&^(0xc0000000)|value<<30)
}
func (o *LCDCAM_Type) GetLCD_DLY_MODE_CFG2_DOUT15_MODE() uint32 {
	return (volatile.LoadUint32(&o.LCD_DLY_MODE_CFG2.Reg) & 0xc0000000) >> 30
}

// LCDCAM.LC_DMA_INT_ENA: LCDCAM interrupt enable register.
func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_LCD_VSYNC_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x1)|value)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_LCD_VSYNC_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x2) >> 1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_CAM_VSYNC_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_CAM_VSYNC_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x4) >> 2
}
func (o *LCDCAM_Type) SetLC_DMA_INT_ENA_CAM_HS_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ENA_CAM_HS_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_ENA.Reg) & 0x8) >> 3
}

// LCDCAM.LC_DMA_INT_RAW: LCDCAM interrupt raw register, valid in level.
func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_LCD_VSYNC_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x1)|value)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_LCD_VSYNC_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x2) >> 1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_CAM_VSYNC_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_CAM_VSYNC_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x4) >> 2
}
func (o *LCDCAM_Type) SetLC_DMA_INT_RAW_CAM_HS_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_RAW_CAM_HS_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_RAW.Reg) & 0x8) >> 3
}

// LCDCAM.LC_DMA_INT_ST: LCDCAM interrupt status register.
func (o *LCDCAM_Type) SetLC_DMA_INT_ST_LCD_VSYNC_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x1)|value)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ST_LCD_VSYNC_INT_ST() uint32 {
	return volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x2) >> 1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_ST_CAM_VSYNC_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ST_CAM_VSYNC_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x4) >> 2
}
func (o *LCDCAM_Type) SetLC_DMA_INT_ST_CAM_HS_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_ST.Reg, volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_ST_CAM_HS_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_ST.Reg) & 0x8) >> 3
}

// LCDCAM.LC_DMA_INT_CLR: LCDCAM interrupt clear register.
func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_LCD_VSYNC_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x1)|value)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_LCD_VSYNC_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x2) >> 1
}
func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_CAM_VSYNC_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_CAM_VSYNC_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x4) >> 2
}
func (o *LCDCAM_Type) SetLC_DMA_INT_CLR_CAM_HS_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LC_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *LCDCAM_Type) GetLC_DMA_INT_CLR_CAM_HS_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LC_DMA_INT_CLR.Reg) & 0x8) >> 3
}

// LCDCAM.LC_REG_DATE: Version register
func (o *LCDCAM_Type) SetLC_REG_DATE_LC_DATE(value uint32) {
	volatile.StoreUint32(&o.LC_REG_DATE.Reg, volatile.LoadUint32(&o.LC_REG_DATE.Reg)&^(0xfffffff)|value)
}
func (o *LCDCAM_Type) GetLC_REG_DATE_LC_DATE() uint32 {
	return volatile.LoadUint32(&o.LC_REG_DATE.Reg) & 0xfffffff
}

// LED Control PWM (Pulse Width Modulation)
type LEDC_Type struct {
	CH0_CONF0      volatile.Register32 // 0x0
	CH0_HPOINT     volatile.Register32 // 0x4
	CH0_DUTY       volatile.Register32 // 0x8
	CH0_CONF1      volatile.Register32 // 0xC
	CH0_DUTY_R     volatile.Register32 // 0x10
	CH1_CONF0      volatile.Register32 // 0x14
	CH1_HPOINT     volatile.Register32 // 0x18
	CH1_DUTY       volatile.Register32 // 0x1C
	CH1_CONF1      volatile.Register32 // 0x20
	CH1_DUTY_R     volatile.Register32 // 0x24
	CH2_CONF0      volatile.Register32 // 0x28
	CH2_HPOINT     volatile.Register32 // 0x2C
	CH2_DUTY       volatile.Register32 // 0x30
	CH2_CONF1      volatile.Register32 // 0x34
	CH2_DUTY_R     volatile.Register32 // 0x38
	CH3_CONF0      volatile.Register32 // 0x3C
	CH3_HPOINT     volatile.Register32 // 0x40
	CH3_DUTY       volatile.Register32 // 0x44
	CH3_CONF1      volatile.Register32 // 0x48
	CH3_DUTY_R     volatile.Register32 // 0x4C
	CH4_CONF0      volatile.Register32 // 0x50
	CH4_HPOINT     volatile.Register32 // 0x54
	CH4_DUTY       volatile.Register32 // 0x58
	CH4_CONF1      volatile.Register32 // 0x5C
	CH4_DUTY_R     volatile.Register32 // 0x60
	CH5_CONF0      volatile.Register32 // 0x64
	CH5_HPOINT     volatile.Register32 // 0x68
	CH5_DUTY       volatile.Register32 // 0x6C
	CH5_CONF1      volatile.Register32 // 0x70
	CH5_DUTY_R     volatile.Register32 // 0x74
	CH6_CONF0      volatile.Register32 // 0x78
	CH6_HPOINT     volatile.Register32 // 0x7C
	CH6_DUTY       volatile.Register32 // 0x80
	CH6_CONF1      volatile.Register32 // 0x84
	CH6_DUTY_R     volatile.Register32 // 0x88
	CH7_CONF0      volatile.Register32 // 0x8C
	CH7_HPOINT     volatile.Register32 // 0x90
	CH7_DUTY       volatile.Register32 // 0x94
	CH7_CONF1      volatile.Register32 // 0x98
	CH7_DUTY_R     volatile.Register32 // 0x9C
	TIMER0_CONF    volatile.Register32 // 0xA0
	TIMER0_VALUE   volatile.Register32 // 0xA4
	TIMER1_CONF    volatile.Register32 // 0xA8
	TIMER1_VALUE   volatile.Register32 // 0xAC
	TIMER2_CONF    volatile.Register32 // 0xB0
	TIMER2_VALUE   volatile.Register32 // 0xB4
	TIMER3_CONF    volatile.Register32 // 0xB8
	TIMER3_VALUE   volatile.Register32 // 0xBC
	INT_RAW        volatile.Register32 // 0xC0
	INT_ST         volatile.Register32 // 0xC4
	INT_ENA        volatile.Register32 // 0xC8
	INT_CLR        volatile.Register32 // 0xCC
	_              [48]byte
	CH0_GAMMA_CONF volatile.Register32 // 0x100
	CH1_GAMMA_CONF volatile.Register32 // 0x104
	CH2_GAMMA_CONF volatile.Register32 // 0x108
	CH3_GAMMA_CONF volatile.Register32 // 0x10C
	CH4_GAMMA_CONF volatile.Register32 // 0x110
	CH5_GAMMA_CONF volatile.Register32 // 0x114
	CH6_GAMMA_CONF volatile.Register32 // 0x118
	CH7_GAMMA_CONF volatile.Register32 // 0x11C
	EVT_TASK_EN0   volatile.Register32 // 0x120
	EVT_TASK_EN1   volatile.Register32 // 0x124
	EVT_TASK_EN2   volatile.Register32 // 0x128
	_              [20]byte
	TIMER0_CMP     volatile.Register32 // 0x140
	TIMER1_CMP     volatile.Register32 // 0x144
	TIMER2_CMP     volatile.Register32 // 0x148
	TIMER3_CMP     volatile.Register32 // 0x14C
	TIMER0_CNT_CAP volatile.Register32 // 0x150
	TIMER1_CNT_CAP volatile.Register32 // 0x154
	TIMER2_CNT_CAP volatile.Register32 // 0x158
	TIMER3_CNT_CAP volatile.Register32 // 0x15C
	_              [16]byte
	CONF           volatile.Register32 // 0x170
	DATE           volatile.Register32 // 0x174
}

// LEDC.CH0_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH0_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH0_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH0_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH0_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH0_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH0_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH0_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH0_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH0_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH0_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH0_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF0.Reg, volatile.LoadUint32(&o.CH0_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH0_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH0_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH0_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_HPOINT.Reg, volatile.LoadUint32(&o.CH0_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH0_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH0_HPOINT.Reg) & 0xfffff
}

// LEDC.CH0_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH0_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_DUTY.Reg, volatile.LoadUint32(&o.CH0_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH0_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH0_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH0_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH0_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_CONF1.Reg, volatile.LoadUint32(&o.CH0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH0_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH0_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH0_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH0_DUTY_R.Reg, volatile.LoadUint32(&o.CH0_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH0_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH0_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.CH1_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH1_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH1_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH1_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH1_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH1_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH1_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH1_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH1_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH1_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH1_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH1_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF0.Reg, volatile.LoadUint32(&o.CH1_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH1_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH1_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH1_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_HPOINT.Reg, volatile.LoadUint32(&o.CH1_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH1_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH1_HPOINT.Reg) & 0xfffff
}

// LEDC.CH1_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH1_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_DUTY.Reg, volatile.LoadUint32(&o.CH1_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH1_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH1_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH1_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH1_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_CONF1.Reg, volatile.LoadUint32(&o.CH1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH1_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH1_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH1_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH1_DUTY_R.Reg, volatile.LoadUint32(&o.CH1_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH1_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH1_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.CH2_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH2_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH2_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH2_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH2_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH2_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH2_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH2_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH2_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH2_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH2_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH2_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF0.Reg, volatile.LoadUint32(&o.CH2_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH2_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH2_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH2_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_HPOINT.Reg, volatile.LoadUint32(&o.CH2_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH2_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH2_HPOINT.Reg) & 0xfffff
}

// LEDC.CH2_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH2_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_DUTY.Reg, volatile.LoadUint32(&o.CH2_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH2_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH2_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH2_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH2_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_CONF1.Reg, volatile.LoadUint32(&o.CH2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH2_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH2_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH2_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH2_DUTY_R.Reg, volatile.LoadUint32(&o.CH2_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH2_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH2_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.CH3_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH3_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH3_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH3_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH3_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH3_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH3_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH3_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH3_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH3_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH3_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH3_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF0.Reg, volatile.LoadUint32(&o.CH3_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH3_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH3_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH3_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_HPOINT.Reg, volatile.LoadUint32(&o.CH3_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH3_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH3_HPOINT.Reg) & 0xfffff
}

// LEDC.CH3_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH3_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_DUTY.Reg, volatile.LoadUint32(&o.CH3_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH3_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH3_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH3_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH3_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_CONF1.Reg, volatile.LoadUint32(&o.CH3_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH3_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH3_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH3_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH3_DUTY_R.Reg, volatile.LoadUint32(&o.CH3_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH3_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH3_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.CH4_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH4_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH4_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH4_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH4_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH4_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH4_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH4_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH4_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH4_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH4_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH4_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF0.Reg, volatile.LoadUint32(&o.CH4_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH4_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH4_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH4_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_HPOINT.Reg, volatile.LoadUint32(&o.CH4_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH4_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH4_HPOINT.Reg) & 0xfffff
}

// LEDC.CH4_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH4_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_DUTY.Reg, volatile.LoadUint32(&o.CH4_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH4_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH4_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH4_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH4_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH4_CONF1.Reg, volatile.LoadUint32(&o.CH4_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH4_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH4_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH4_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH4_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH4_DUTY_R.Reg, volatile.LoadUint32(&o.CH4_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH4_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH4_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.CH5_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH5_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH5_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH5_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH5_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH5_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH5_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH5_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH5_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH5_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH5_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH5_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF0.Reg, volatile.LoadUint32(&o.CH5_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH5_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH5_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH5_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH5_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_HPOINT.Reg, volatile.LoadUint32(&o.CH5_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH5_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH5_HPOINT.Reg) & 0xfffff
}

// LEDC.CH5_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH5_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_DUTY.Reg, volatile.LoadUint32(&o.CH5_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH5_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH5_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH5_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH5_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH5_CONF1.Reg, volatile.LoadUint32(&o.CH5_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH5_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH5_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH5_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH5_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH5_DUTY_R.Reg, volatile.LoadUint32(&o.CH5_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH5_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH5_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.CH6_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH6_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH6_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH6_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH6_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH6_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH6_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH6_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH6_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH6_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH6_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH6_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF0.Reg, volatile.LoadUint32(&o.CH6_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH6_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH6_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH6_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH6_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_HPOINT.Reg, volatile.LoadUint32(&o.CH6_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH6_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH6_HPOINT.Reg) & 0xfffff
}

// LEDC.CH6_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH6_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_DUTY.Reg, volatile.LoadUint32(&o.CH6_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH6_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH6_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH6_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH6_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH6_CONF1.Reg, volatile.LoadUint32(&o.CH6_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH6_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH6_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH6_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH6_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH6_DUTY_R.Reg, volatile.LoadUint32(&o.CH6_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH6_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH6_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.CH7_CONF0: Configuration register 0 for channel %s
func (o *LEDC_Type) SetCH7_CONF0_TIMER_SEL_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCH7_CONF0_TIMER_SEL_CH() uint32 {
	return volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x3
}
func (o *LEDC_Type) SetCH7_CONF0_SIG_OUT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCH7_CONF0_SIG_OUT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCH7_CONF0_IDLE_LV_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCH7_CONF0_IDLE_LV_CH() uint32 {
	return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCH7_CONF0_PARA_UP_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCH7_CONF0_PARA_UP_CH() uint32 {
	return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCH7_CONF0_OVF_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x7fe0)|value<<5)
}
func (o *LEDC_Type) GetCH7_CONF0_OVF_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x7fe0) >> 5
}
func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetCH7_CONF0_OVF_CNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF0.Reg, volatile.LoadUint32(&o.CH7_CONF0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetCH7_CONF0_OVF_CNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH7_CONF0.Reg) & 0x10000) >> 16
}

// LEDC.CH7_HPOINT: High point register for channel %s
func (o *LEDC_Type) SetCH7_HPOINT_HPOINT_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_HPOINT.Reg, volatile.LoadUint32(&o.CH7_HPOINT.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetCH7_HPOINT_HPOINT_CH() uint32 {
	return volatile.LoadUint32(&o.CH7_HPOINT.Reg) & 0xfffff
}

// LEDC.CH7_DUTY: Initial duty cycle register for channel %s
func (o *LEDC_Type) SetCH7_DUTY_DUTY_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_DUTY.Reg, volatile.LoadUint32(&o.CH7_DUTY.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH7_DUTY_DUTY_CH() uint32 {
	return volatile.LoadUint32(&o.CH7_DUTY.Reg) & 0x1ffffff
}

// LEDC.CH7_CONF1: Configuration register 1 for channel %s
func (o *LEDC_Type) SetCH7_CONF1_DUTY_START_CH(value uint32) {
	volatile.StoreUint32(&o.CH7_CONF1.Reg, volatile.LoadUint32(&o.CH7_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCH7_CONF1_DUTY_START_CH() uint32 {
	return (volatile.LoadUint32(&o.CH7_CONF1.Reg) & 0x80000000) >> 31
}

// LEDC.CH7_DUTY_R: Current duty cycle register for channel %s
func (o *LEDC_Type) SetCH7_DUTY_R_DUTY_CH_R(value uint32) {
	volatile.StoreUint32(&o.CH7_DUTY_R.Reg, volatile.LoadUint32(&o.CH7_DUTY_R.Reg)&^(0x1ffffff)|value)
}
func (o *LEDC_Type) GetCH7_DUTY_R_DUTY_CH_R() uint32 {
	return volatile.LoadUint32(&o.CH7_DUTY_R.Reg) & 0x1ffffff
}

// LEDC.TIMER0_CONF: Timer %s configuration register
func (o *LEDC_Type) SetTIMER0_CONF_TIMER_DUTY_RES(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetTIMER0_CONF_TIMER_DUTY_RES() uint32 {
	return volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetTIMER0_CONF_CLK_DIV_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x7fffe0)|value<<5)
}
func (o *LEDC_Type) GetTIMER0_CONF_CLK_DIV_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x7fffe0) >> 5
}
func (o *LEDC_Type) SetTIMER0_CONF_TIMER_PAUSE(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x800000)|value<<23)
}
func (o *LEDC_Type) GetTIMER0_CONF_TIMER_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x800000) >> 23
}
func (o *LEDC_Type) SetTIMER0_CONF_TIMER_RST(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *LEDC_Type) GetTIMER0_CONF_TIMER_RST() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x1000000) >> 24
}
func (o *LEDC_Type) SetTIMER0_CONF_TICK_SEL_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *LEDC_Type) GetTIMER0_CONF_TICK_SEL_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x2000000) >> 25
}
func (o *LEDC_Type) SetTIMER0_CONF_TIMER_PARA_UP(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CONF.Reg, volatile.LoadUint32(&o.TIMER0_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *LEDC_Type) GetTIMER0_CONF_TIMER_PARA_UP() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CONF.Reg) & 0x4000000) >> 26
}

// LEDC.TIMER0_VALUE: Timer %s current counter value register
func (o *LEDC_Type) SetTIMER0_VALUE_TIMER_CNT(value uint32) {
	volatile.StoreUint32(&o.TIMER0_VALUE.Reg, volatile.LoadUint32(&o.TIMER0_VALUE.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER0_VALUE_TIMER_CNT() uint32 {
	return volatile.LoadUint32(&o.TIMER0_VALUE.Reg) & 0xfffff
}

// LEDC.TIMER1_CONF: Timer %s configuration register
func (o *LEDC_Type) SetTIMER1_CONF_TIMER_DUTY_RES(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetTIMER1_CONF_TIMER_DUTY_RES() uint32 {
	return volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetTIMER1_CONF_CLK_DIV_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x7fffe0)|value<<5)
}
func (o *LEDC_Type) GetTIMER1_CONF_CLK_DIV_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x7fffe0) >> 5
}
func (o *LEDC_Type) SetTIMER1_CONF_TIMER_PAUSE(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x800000)|value<<23)
}
func (o *LEDC_Type) GetTIMER1_CONF_TIMER_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x800000) >> 23
}
func (o *LEDC_Type) SetTIMER1_CONF_TIMER_RST(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *LEDC_Type) GetTIMER1_CONF_TIMER_RST() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x1000000) >> 24
}
func (o *LEDC_Type) SetTIMER1_CONF_TICK_SEL_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *LEDC_Type) GetTIMER1_CONF_TICK_SEL_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x2000000) >> 25
}
func (o *LEDC_Type) SetTIMER1_CONF_TIMER_PARA_UP(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CONF.Reg, volatile.LoadUint32(&o.TIMER1_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *LEDC_Type) GetTIMER1_CONF_TIMER_PARA_UP() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CONF.Reg) & 0x4000000) >> 26
}

// LEDC.TIMER1_VALUE: Timer %s current counter value register
func (o *LEDC_Type) SetTIMER1_VALUE_TIMER_CNT(value uint32) {
	volatile.StoreUint32(&o.TIMER1_VALUE.Reg, volatile.LoadUint32(&o.TIMER1_VALUE.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER1_VALUE_TIMER_CNT() uint32 {
	return volatile.LoadUint32(&o.TIMER1_VALUE.Reg) & 0xfffff
}

// LEDC.TIMER2_CONF: Timer %s configuration register
func (o *LEDC_Type) SetTIMER2_CONF_TIMER_DUTY_RES(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetTIMER2_CONF_TIMER_DUTY_RES() uint32 {
	return volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetTIMER2_CONF_CLK_DIV_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x7fffe0)|value<<5)
}
func (o *LEDC_Type) GetTIMER2_CONF_CLK_DIV_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x7fffe0) >> 5
}
func (o *LEDC_Type) SetTIMER2_CONF_TIMER_PAUSE(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x800000)|value<<23)
}
func (o *LEDC_Type) GetTIMER2_CONF_TIMER_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x800000) >> 23
}
func (o *LEDC_Type) SetTIMER2_CONF_TIMER_RST(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *LEDC_Type) GetTIMER2_CONF_TIMER_RST() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x1000000) >> 24
}
func (o *LEDC_Type) SetTIMER2_CONF_TICK_SEL_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *LEDC_Type) GetTIMER2_CONF_TICK_SEL_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x2000000) >> 25
}
func (o *LEDC_Type) SetTIMER2_CONF_TIMER_PARA_UP(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CONF.Reg, volatile.LoadUint32(&o.TIMER2_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *LEDC_Type) GetTIMER2_CONF_TIMER_PARA_UP() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CONF.Reg) & 0x4000000) >> 26
}

// LEDC.TIMER2_VALUE: Timer %s current counter value register
func (o *LEDC_Type) SetTIMER2_VALUE_TIMER_CNT(value uint32) {
	volatile.StoreUint32(&o.TIMER2_VALUE.Reg, volatile.LoadUint32(&o.TIMER2_VALUE.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER2_VALUE_TIMER_CNT() uint32 {
	return volatile.LoadUint32(&o.TIMER2_VALUE.Reg) & 0xfffff
}

// LEDC.TIMER3_CONF: Timer %s configuration register
func (o *LEDC_Type) SetTIMER3_CONF_TIMER_DUTY_RES(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetTIMER3_CONF_TIMER_DUTY_RES() uint32 {
	return volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetTIMER3_CONF_CLK_DIV_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x7fffe0)|value<<5)
}
func (o *LEDC_Type) GetTIMER3_CONF_CLK_DIV_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x7fffe0) >> 5
}
func (o *LEDC_Type) SetTIMER3_CONF_TIMER_PAUSE(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x800000)|value<<23)
}
func (o *LEDC_Type) GetTIMER3_CONF_TIMER_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x800000) >> 23
}
func (o *LEDC_Type) SetTIMER3_CONF_TIMER_RST(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *LEDC_Type) GetTIMER3_CONF_TIMER_RST() uint32 {
	return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x1000000) >> 24
}
func (o *LEDC_Type) SetTIMER3_CONF_TICK_SEL_TIMER(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *LEDC_Type) GetTIMER3_CONF_TICK_SEL_TIMER() uint32 {
	return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x2000000) >> 25
}
func (o *LEDC_Type) SetTIMER3_CONF_TIMER_PARA_UP(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CONF.Reg, volatile.LoadUint32(&o.TIMER3_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *LEDC_Type) GetTIMER3_CONF_TIMER_PARA_UP() uint32 {
	return (volatile.LoadUint32(&o.TIMER3_CONF.Reg) & 0x4000000) >> 26
}

// LEDC.TIMER3_VALUE: Timer %s current counter value register
func (o *LEDC_Type) SetTIMER3_VALUE_TIMER_CNT(value uint32) {
	volatile.StoreUint32(&o.TIMER3_VALUE.Reg, volatile.LoadUint32(&o.TIMER3_VALUE.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER3_VALUE_TIMER_CNT() uint32 {
	return volatile.LoadUint32(&o.TIMER3_VALUE.Reg) & 0xfffff
}

// LEDC.INT_RAW: Interrupt raw status register
func (o *LEDC_Type) SetINT_RAW_TIMER0_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *LEDC_Type) GetINT_RAW_TIMER0_OVF_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *LEDC_Type) SetINT_RAW_TIMER1_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *LEDC_Type) GetINT_RAW_TIMER1_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *LEDC_Type) SetINT_RAW_TIMER2_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetINT_RAW_TIMER2_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetINT_RAW_TIMER3_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetINT_RAW_TIMER3_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH5_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH6_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *LEDC_Type) SetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *LEDC_Type) GetINT_RAW_DUTY_CHNG_END_CH7_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH4_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH4_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH5_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH5_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH6_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH6_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *LEDC_Type) SetINT_RAW_OVF_CNT_CH7_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *LEDC_Type) GetINT_RAW_OVF_CNT_CH7_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}

// LEDC.INT_ST: Interrupt masked status register
func (o *LEDC_Type) SetINT_ST_TIMER0_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *LEDC_Type) GetINT_ST_TIMER0_OVF_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *LEDC_Type) SetINT_ST_TIMER1_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *LEDC_Type) GetINT_ST_TIMER1_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *LEDC_Type) SetINT_ST_TIMER2_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetINT_ST_TIMER2_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetINT_ST_TIMER3_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetINT_ST_TIMER3_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH5_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH5_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH6_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH6_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *LEDC_Type) SetINT_ST_DUTY_CHNG_END_CH7_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *LEDC_Type) GetINT_ST_DUTY_CHNG_END_CH7_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH4_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH4_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH5_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH5_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH6_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH6_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18
}
func (o *LEDC_Type) SetINT_ST_OVF_CNT_CH7_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *LEDC_Type) GetINT_ST_OVF_CNT_CH7_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19
}

// LEDC.INT_ENA: Interrupt enable register
func (o *LEDC_Type) SetINT_ENA_TIMER0_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *LEDC_Type) GetINT_ENA_TIMER0_OVF_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *LEDC_Type) SetINT_ENA_TIMER1_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *LEDC_Type) GetINT_ENA_TIMER1_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *LEDC_Type) SetINT_ENA_TIMER2_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetINT_ENA_TIMER2_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetINT_ENA_TIMER3_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetINT_ENA_TIMER3_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH5_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH6_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *LEDC_Type) SetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *LEDC_Type) GetINT_ENA_DUTY_CHNG_END_CH7_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH4_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH4_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH5_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH5_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH6_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH6_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}
func (o *LEDC_Type) SetINT_ENA_OVF_CNT_CH7_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *LEDC_Type) GetINT_ENA_OVF_CNT_CH7_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19
}

// LEDC.INT_CLR: Interrupt clear register
func (o *LEDC_Type) SetINT_CLR_TIMER0_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *LEDC_Type) GetINT_CLR_TIMER0_OVF_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *LEDC_Type) SetINT_CLR_TIMER1_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *LEDC_Type) GetINT_CLR_TIMER1_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *LEDC_Type) SetINT_CLR_TIMER2_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetINT_CLR_TIMER2_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetINT_CLR_TIMER3_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetINT_CLR_TIMER3_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH5_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH6_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *LEDC_Type) SetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *LEDC_Type) GetINT_CLR_DUTY_CHNG_END_CH7_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH4_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH4_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH5_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH5_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH6_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH6_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}
func (o *LEDC_Type) SetINT_CLR_OVF_CNT_CH7_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *LEDC_Type) GetINT_CLR_OVF_CNT_CH7_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19
}

// LEDC.CH0_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH0_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH0_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH0_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH0_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.CH1_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH1_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH1_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH1_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH1_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.CH2_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH2_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH2_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH2_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH2_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.CH3_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH3_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH3_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH3_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH3_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.CH4_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH4_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH4_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH4_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH4_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.CH5_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH5_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH5_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH5_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH5_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.CH6_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH6_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH6_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH6_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH6_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH6_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH6_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH6_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH6_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH6_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH6_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.CH7_GAMMA_CONF: Ledc ch%s gamma config register.
func (o *LEDC_Type) SetCH7_GAMMA_CONF_CH_GAMMA_ENTRY_NUM(value uint32) {
	volatile.StoreUint32(&o.CH7_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg)&^(0x1f)|value)
}
func (o *LEDC_Type) GetCH7_GAMMA_CONF_CH_GAMMA_ENTRY_NUM() uint32 {
	return volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg) & 0x1f
}
func (o *LEDC_Type) SetCH7_GAMMA_CONF_CH_GAMMA_PAUSE(value uint32) {
	volatile.StoreUint32(&o.CH7_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCH7_GAMMA_CONF_CH_GAMMA_PAUSE() uint32 {
	return (volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCH7_GAMMA_CONF_CH_GAMMA_RESUME(value uint32) {
	volatile.StoreUint32(&o.CH7_GAMMA_CONF.Reg, volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCH7_GAMMA_CONF_CH_GAMMA_RESUME() uint32 {
	return (volatile.LoadUint32(&o.CH7_GAMMA_CONF.Reg) & 0x40) >> 6
}

// LEDC.EVT_TASK_EN0: Ledc event task enable bit register0.
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1)|value)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2)|value<<1)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2) >> 1
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_DUTY_CHNG_END_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400)|value<<10)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400) >> 10
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800)|value<<11)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800) >> 11
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000)|value<<12)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000) >> 12
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000)|value<<13)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000) >> 13
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4000)|value<<14)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4000) >> 14
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_OVF_CNT_PLS_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000) >> 16
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000)|value<<17)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000) >> 17
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40000)|value<<18)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40000) >> 18
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80000)|value<<19)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80000) >> 19
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME0_CMP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x100000)|value<<20)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME0_CMP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x100000) >> 20
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME1_CMP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x200000)|value<<21)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME1_CMP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x200000) >> 21
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME2_CMP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x400000)|value<<22)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME2_CMP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x400000) >> 22
}
func (o *LEDC_Type) SetEVT_TASK_EN0_EVT_TIME3_CMP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x800000)|value<<23)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_EVT_TIME3_CMP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x800000) >> 23
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x1000000)|value<<24)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x1000000) >> 24
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x2000000)|value<<25)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x2000000) >> 25
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x4000000)|value<<26)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x4000000) >> 26
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x8000000)|value<<27)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x8000000) >> 27
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x10000000)|value<<28)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x10000000) >> 28
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x20000000)|value<<29)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x20000000) >> 29
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x40000000)|value<<30)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x40000000) >> 30
}
func (o *LEDC_Type) SetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN0.Reg, volatile.LoadUint32(&o.EVT_TASK_EN0.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetEVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN0.Reg) & 0x80000000) >> 31
}

// LEDC.EVT_TASK_EN1: Ledc event task enable bit register1.
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1)|value)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN() uint32 {
	return volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2)|value<<1)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2) >> 1
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_CAP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_CAP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_CAP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_CAP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_CAP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_CAP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_CAP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_CAP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x400)|value<<10)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x400) >> 10
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x800)|value<<11)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x800) >> 11
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000)|value<<12)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000) >> 12
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000)|value<<13)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000) >> 13
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4000)|value<<14)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4000) >> 14
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_SIG_OUT_DIS_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000) >> 16
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000)|value<<17)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000) >> 17
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000)|value<<18)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000) >> 18
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000)|value<<19)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000) >> 19
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x100000)|value<<20)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x100000) >> 20
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x200000)|value<<21)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x200000) >> 21
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x400000)|value<<22)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x400000) >> 22
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x800000)|value<<23)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_OVF_CNT_RST_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x800000) >> 23
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_RST_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x1000000)|value<<24)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_RST_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x1000000) >> 24
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_RST_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x2000000)|value<<25)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_RST_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x2000000) >> 25
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_RST_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x4000000)|value<<26)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_RST_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x4000000) >> 26
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_RST_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x8000000)|value<<27)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_RST_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x8000000) >> 27
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x10000000)|value<<28)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x10000000) >> 28
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x20000000)|value<<29)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x20000000) >> 29
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x40000000)|value<<30)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x40000000) >> 30
}
func (o *LEDC_Type) SetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN1.Reg, volatile.LoadUint32(&o.EVT_TASK_EN1.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetEVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN1.Reg) & 0x80000000) >> 31
}

// LEDC.EVT_TASK_EN2: Ledc event task enable bit register2.
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1)|value)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN() uint32 {
	return volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2)|value<<1)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2) >> 1
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESTART_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x400)|value<<10)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x400) >> 10
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x800)|value<<11)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x800) >> 11
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x1000)|value<<12)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x1000) >> 12
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x2000)|value<<13)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x2000) >> 13
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x4000)|value<<14)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x4000) >> 14
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x8000)|value<<15)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_PAUSE_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x8000) >> 15
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x10000)|value<<16)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x10000) >> 16
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x20000)|value<<17)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x20000) >> 17
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x40000)|value<<18)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x40000) >> 18
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x80000)|value<<19)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x80000) >> 19
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x100000)|value<<20)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x100000) >> 20
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x200000)|value<<21)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x200000) >> 21
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH6_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x400000)|value<<22)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH6_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x400000) >> 22
}
func (o *LEDC_Type) SetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH7_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_TASK_EN2.Reg, volatile.LoadUint32(&o.EVT_TASK_EN2.Reg)&^(0x800000)|value<<23)
}
func (o *LEDC_Type) GetEVT_TASK_EN2_TASK_GAMMA_RESUME_CH7_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_TASK_EN2.Reg) & 0x800000) >> 23
}

// LEDC.TIMER0_CMP: Ledc timer%s compare value register.
func (o *LEDC_Type) SetTIMER0_CMP_TIMER_CMP(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CMP.Reg, volatile.LoadUint32(&o.TIMER0_CMP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER0_CMP_TIMER_CMP() uint32 {
	return volatile.LoadUint32(&o.TIMER0_CMP.Reg) & 0xfffff
}

// LEDC.TIMER1_CMP: Ledc timer%s compare value register.
func (o *LEDC_Type) SetTIMER1_CMP_TIMER_CMP(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CMP.Reg, volatile.LoadUint32(&o.TIMER1_CMP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER1_CMP_TIMER_CMP() uint32 {
	return volatile.LoadUint32(&o.TIMER1_CMP.Reg) & 0xfffff
}

// LEDC.TIMER2_CMP: Ledc timer%s compare value register.
func (o *LEDC_Type) SetTIMER2_CMP_TIMER_CMP(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CMP.Reg, volatile.LoadUint32(&o.TIMER2_CMP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER2_CMP_TIMER_CMP() uint32 {
	return volatile.LoadUint32(&o.TIMER2_CMP.Reg) & 0xfffff
}

// LEDC.TIMER3_CMP: Ledc timer%s compare value register.
func (o *LEDC_Type) SetTIMER3_CMP_TIMER_CMP(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CMP.Reg, volatile.LoadUint32(&o.TIMER3_CMP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER3_CMP_TIMER_CMP() uint32 {
	return volatile.LoadUint32(&o.TIMER3_CMP.Reg) & 0xfffff
}

// LEDC.TIMER0_CNT_CAP: Ledc timer%s captured count value register.
func (o *LEDC_Type) SetTIMER0_CNT_CAP_TIMER_CNT_CAP(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER0_CNT_CAP_TIMER_CNT_CAP() uint32 {
	return volatile.LoadUint32(&o.TIMER0_CNT_CAP.Reg) & 0xfffff
}

// LEDC.TIMER1_CNT_CAP: Ledc timer%s captured count value register.
func (o *LEDC_Type) SetTIMER1_CNT_CAP_TIMER_CNT_CAP(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER1_CNT_CAP_TIMER_CNT_CAP() uint32 {
	return volatile.LoadUint32(&o.TIMER1_CNT_CAP.Reg) & 0xfffff
}

// LEDC.TIMER2_CNT_CAP: Ledc timer%s captured count value register.
func (o *LEDC_Type) SetTIMER2_CNT_CAP_TIMER_CNT_CAP(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER2_CNT_CAP_TIMER_CNT_CAP() uint32 {
	return volatile.LoadUint32(&o.TIMER2_CNT_CAP.Reg) & 0xfffff
}

// LEDC.TIMER3_CNT_CAP: Ledc timer%s captured count value register.
func (o *LEDC_Type) SetTIMER3_CNT_CAP_TIMER_CNT_CAP(value uint32) {
	volatile.StoreUint32(&o.TIMER3_CNT_CAP.Reg, volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg)&^(0xfffff)|value)
}
func (o *LEDC_Type) GetTIMER3_CNT_CAP_TIMER_CNT_CAP() uint32 {
	return volatile.LoadUint32(&o.TIMER3_CNT_CAP.Reg) & 0xfffff
}

// LEDC.CONF: LEDC global configuration register
func (o *LEDC_Type) SetCONF_APB_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3)|value)
}
func (o *LEDC_Type) GetCONF_APB_CLK_SEL() uint32 {
	return volatile.LoadUint32(&o.CONF.Reg) & 0x3
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4)|value<<2)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x4) >> 2
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH1(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8)|value<<3)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH1() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x8) >> 3
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH2(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10)|value<<4)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH2() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x10) >> 4
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH3(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20)|value<<5)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH3() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x20) >> 5
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH5(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80)|value<<7)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH5() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x80) >> 7
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH6(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x100)|value<<8)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH6() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x100) >> 8
}
func (o *LEDC_Type) SetCONF_GAMMA_RAM_CLK_EN_CH7(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x200)|value<<9)
}
func (o *LEDC_Type) GetCONF_GAMMA_RAM_CLK_EN_CH7() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x200) >> 9
}
func (o *LEDC_Type) SetCONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *LEDC_Type) GetCONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31
}

// LEDC.DATE: Version control register
func (o *LEDC_Type) SetDATE_LEDC_DATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *LEDC_Type) GetDATE_LEDC_DATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// Low-power Interrupt Controller
type LPINTR_Type struct {
	SW_INT_RAW volatile.Register32 // 0x0
	SW_INT_ST  volatile.Register32 // 0x4
	SW_INT_ENA volatile.Register32 // 0x8
	SW_INT_CLR volatile.Register32 // 0xC
	STATUS     volatile.Register32 // 0x10
	_          [1000]byte
	DATE       volatile.Register32 // 0x3FC
}

// LPINTR.SW_INT_RAW: need_des
func (o *LPINTR_Type) SetSW_INT_RAW_LP_SW_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SW_INT_RAW.Reg, volatile.LoadUint32(&o.SW_INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *LPINTR_Type) GetSW_INT_RAW_LP_SW_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SW_INT_RAW.Reg) & 0x80000000) >> 31
}

// LPINTR.SW_INT_ST: need_des
func (o *LPINTR_Type) SetSW_INT_ST_LP_SW_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SW_INT_ST.Reg, volatile.LoadUint32(&o.SW_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *LPINTR_Type) GetSW_INT_ST_LP_SW_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SW_INT_ST.Reg) & 0x80000000) >> 31
}

// LPINTR.SW_INT_ENA: need_des
func (o *LPINTR_Type) SetSW_INT_ENA_LP_SW_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SW_INT_ENA.Reg, volatile.LoadUint32(&o.SW_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *LPINTR_Type) GetSW_INT_ENA_LP_SW_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SW_INT_ENA.Reg) & 0x80000000) >> 31
}

// LPINTR.SW_INT_CLR: need_des
func (o *LPINTR_Type) SetSW_INT_CLR_LP_SW_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SW_INT_CLR.Reg, volatile.LoadUint32(&o.SW_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *LPINTR_Type) GetSW_INT_CLR_LP_SW_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SW_INT_CLR.Reg) & 0x80000000) >> 31
}

// LPINTR.STATUS: need_des
func (o *LPINTR_Type) SetSTATUS_LP_HUK_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10)
}
func (o *LPINTR_Type) GetSTATUS_LP_HUK_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10
}
func (o *LPINTR_Type) SetSTATUS_SYSREG_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x800)|value<<11)
}
func (o *LPINTR_Type) GetSTATUS_SYSREG_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x800) >> 11
}
func (o *LPINTR_Type) SetSTATUS_LP_SW_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1000)|value<<12)
}
func (o *LPINTR_Type) GetSTATUS_LP_SW_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1000) >> 12
}
func (o *LPINTR_Type) SetSTATUS_LP_EFUSE_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13)
}
func (o *LPINTR_Type) GetSTATUS_LP_EFUSE_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13
}
func (o *LPINTR_Type) SetSTATUS_LP_UART_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14)
}
func (o *LPINTR_Type) GetSTATUS_LP_UART_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14
}
func (o *LPINTR_Type) SetSTATUS_LP_TSENS_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *LPINTR_Type) GetSTATUS_LP_TSENS_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15
}
func (o *LPINTR_Type) SetSTATUS_LP_TOUCH_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *LPINTR_Type) GetSTATUS_LP_TOUCH_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10000) >> 16
}
func (o *LPINTR_Type) SetSTATUS_LP_SPI_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000)|value<<17)
}
func (o *LPINTR_Type) GetSTATUS_LP_SPI_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000) >> 17
}
func (o *LPINTR_Type) SetSTATUS_LP_I2S_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000)|value<<18)
}
func (o *LPINTR_Type) GetSTATUS_LP_I2S_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000) >> 18
}
func (o *LPINTR_Type) SetSTATUS_LP_I2C_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000)|value<<19)
}
func (o *LPINTR_Type) GetSTATUS_LP_I2C_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000) >> 19
}
func (o *LPINTR_Type) SetSTATUS_LP_GPIO_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100000)|value<<20)
}
func (o *LPINTR_Type) GetSTATUS_LP_GPIO_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100000) >> 20
}
func (o *LPINTR_Type) SetSTATUS_LP_ADC_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200000)|value<<21)
}
func (o *LPINTR_Type) GetSTATUS_LP_ADC_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200000) >> 21
}
func (o *LPINTR_Type) SetSTATUS_ANAPERI_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400000)|value<<22)
}
func (o *LPINTR_Type) GetSTATUS_ANAPERI_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400000) >> 22
}
func (o *LPINTR_Type) SetSTATUS_PMU_REG_1_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x800000)|value<<23)
}
func (o *LPINTR_Type) GetSTATUS_PMU_REG_1_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x800000) >> 23
}
func (o *LPINTR_Type) SetSTATUS_PMU_REG_0_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1000000)|value<<24)
}
func (o *LPINTR_Type) GetSTATUS_PMU_REG_0_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1000000) >> 24
}
func (o *LPINTR_Type) SetSTATUS_MB_LP_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *LPINTR_Type) GetSTATUS_MB_LP_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000000) >> 25
}
func (o *LPINTR_Type) SetSTATUS_MB_HP_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *LPINTR_Type) GetSTATUS_MB_HP_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000000) >> 26
}
func (o *LPINTR_Type) SetSTATUS_LP_TIMER_REG_1_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000000)|value<<27)
}
func (o *LPINTR_Type) GetSTATUS_LP_TIMER_REG_1_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000000) >> 27
}
func (o *LPINTR_Type) SetSTATUS_LP_TIMER_REG_0_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10000000)|value<<28)
}
func (o *LPINTR_Type) GetSTATUS_LP_TIMER_REG_0_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10000000) >> 28
}
func (o *LPINTR_Type) SetSTATUS_LP_WDT_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29)
}
func (o *LPINTR_Type) GetSTATUS_LP_WDT_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29
}
func (o *LPINTR_Type) SetSTATUS_LP_RTC_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30)
}
func (o *LPINTR_Type) GetSTATUS_LP_RTC_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30
}
func (o *LPINTR_Type) SetSTATUS_HP_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31)
}
func (o *LPINTR_Type) GetSTATUS_HP_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31
}

// LPINTR.DATE: need_des
func (o *LPINTR_Type) SetDATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *LPINTR_Type) GetDATE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31
}

// LP_PERI Peripheral
type LPPERI_Type struct {
	CLK_EN               volatile.Register32 // 0x0
	CORE_CLK_SEL         volatile.Register32 // 0x4
	RESET_EN             volatile.Register32 // 0x8
	CPU                  volatile.Register32 // 0xC
	_                    [24]byte
	MEM_CTRL             volatile.Register32 // 0x28
	ADC_CTRL             volatile.Register32 // 0x2C
	LP_I2S_RXCLK_DIV_NUM volatile.Register32 // 0x30
	LP_I2S_RXCLK_DIV_XYZ volatile.Register32 // 0x34
	LP_I2S_TXCLK_DIV_NUM volatile.Register32 // 0x38
	LP_I2S_TXCLK_DIV_XYZ volatile.Register32 // 0x3C
	_                    [956]byte
	DATE                 volatile.Register32 // 0x3FC
}

// LPPERI.CLK_EN: need_des
func (o *LPPERI_Type) SetCLK_EN_CK_EN_RNG(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000)|value<<16)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_RNG() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000) >> 16
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_TSENS(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000)|value<<17)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_TSENS() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000) >> 17
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_PMS(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000)|value<<18)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_PMS() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000) >> 18
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_EFUSE(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80000)|value<<19)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_EFUSE() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80000) >> 19
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_IOMUX(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x100000)|value<<20)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_IOMUX() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x100000) >> 20
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_TOUCH(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x200000)|value<<21)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_TOUCH() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x200000) >> 21
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_SPI(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x400000)|value<<22)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_SPI() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x400000) >> 22
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_ADC(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x800000)|value<<23)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_ADC() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x800000) >> 23
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2S_TX(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1000000)|value<<24)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2S_TX() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1000000) >> 24
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2S_RX(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x2000000)|value<<25)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2S_RX() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x2000000) >> 25
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2S(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x4000000)|value<<26)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2S() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x4000000) >> 26
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2CMST(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x8000000)|value<<27)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2CMST() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x8000000) >> 27
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_I2C(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x10000000)|value<<28)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_I2C() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x10000000) >> 28
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_UART(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x20000000)|value<<29)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_UART() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x20000000) >> 29
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_INTR(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x40000000)|value<<30)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_INTR() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x40000000) >> 30
}
func (o *LPPERI_Type) SetCLK_EN_CK_EN_LP_CORE(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x80000000)|value<<31)
}
func (o *LPPERI_Type) GetCLK_EN_CK_EN_LP_CORE() uint32 {
	return (volatile.LoadUint32(&o.CLK_EN.Reg) & 0x80000000) >> 31
}

// LPPERI.CORE_CLK_SEL: need_des
func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_I2S_TX_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0x3000000)|value<<24)
}
func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_I2S_TX_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0x3000000) >> 24
}
func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_I2S_RX_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0xc000000)|value<<26)
}
func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_I2S_RX_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0xc000000) >> 26
}
func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_I2C_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0x30000000)|value<<28)
}
func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_I2C_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0x30000000) >> 28
}
func (o *LPPERI_Type) SetCORE_CLK_SEL_LP_UART_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CORE_CLK_SEL.Reg, volatile.LoadUint32(&o.CORE_CLK_SEL.Reg)&^(0xc0000000)|value<<30)
}
func (o *LPPERI_Type) GetCORE_CLK_SEL_LP_UART_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CORE_CLK_SEL.Reg) & 0xc0000000) >> 30
}

// LPPERI.RESET_EN: need_des
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_TSENS(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x40000)|value<<18)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_TSENS() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x40000) >> 18
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_PMS(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x80000)|value<<19)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_PMS() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x80000) >> 19
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_EFUSE(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x100000)|value<<20)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_EFUSE() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x100000) >> 20
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_IOMUX(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x200000)|value<<21)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_IOMUX() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x200000) >> 21
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_TOUCH(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x400000)|value<<22)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_TOUCH() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x400000) >> 22
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_SPI(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x800000)|value<<23)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_SPI() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x800000) >> 23
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_ADC(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x1000000)|value<<24)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_ADC() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x1000000) >> 24
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_I2S(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x2000000)|value<<25)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_I2S() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x2000000) >> 25
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_I2CMST(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x4000000)|value<<26)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_I2CMST() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x4000000) >> 26
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_I2C(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x8000000)|value<<27)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_I2C() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x8000000) >> 27
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_UART(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x10000000)|value<<28)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_UART() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x10000000) >> 28
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_INTR(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x20000000)|value<<29)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_INTR() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x20000000) >> 29
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_ROM(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x40000000)|value<<30)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_ROM() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x40000000) >> 30
}
func (o *LPPERI_Type) SetRESET_EN_RST_EN_LP_CORE(value uint32) {
	volatile.StoreUint32(&o.RESET_EN.Reg, volatile.LoadUint32(&o.RESET_EN.Reg)&^(0x80000000)|value<<31)
}
func (o *LPPERI_Type) GetRESET_EN_RST_EN_LP_CORE() uint32 {
	return (volatile.LoadUint32(&o.RESET_EN.Reg) & 0x80000000) >> 31
}

// LPPERI.CPU: need_des
func (o *LPPERI_Type) SetCPU_LPCORE_DBGM_UNAVAILABLE(value uint32) {
	volatile.StoreUint32(&o.CPU.Reg, volatile.LoadUint32(&o.CPU.Reg)&^(0x80000000)|value<<31)
}
func (o *LPPERI_Type) GetCPU_LPCORE_DBGM_UNAVAILABLE() uint32 {
	return (volatile.LoadUint32(&o.CPU.Reg) & 0x80000000) >> 31
}

// LPPERI.MEM_CTRL: need_des
func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_WAKEUP_FLAG_CLR(value uint32) {
	volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x1)|value)
}
func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_WAKEUP_FLAG_CLR() uint32 {
	return volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x1
}
func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_WAKEUP_FLAG(value uint32) {
	volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_WAKEUP_FLAG() uint32 {
	return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x2) >> 1
}
func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x20000000) >> 29
}
func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x40000000) >> 30
}
func (o *LPPERI_Type) SetMEM_CTRL_LP_UART_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.MEM_CTRL.Reg, volatile.LoadUint32(&o.MEM_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *LPPERI_Type) GetMEM_CTRL_LP_UART_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.MEM_CTRL.Reg) & 0x80000000) >> 31
}

// LPPERI.ADC_CTRL: need_des
func (o *LPPERI_Type) SetADC_CTRL_SAR2_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *LPPERI_Type) GetADC_CTRL_SAR2_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0x40) >> 6
}
func (o *LPPERI_Type) SetADC_CTRL_SAR1_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *LPPERI_Type) GetADC_CTRL_SAR1_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0x80) >> 7
}
func (o *LPPERI_Type) SetADC_CTRL_LPADC_FUNC_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *LPPERI_Type) GetADC_CTRL_LPADC_FUNC_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0xff00) >> 8
}
func (o *LPPERI_Type) SetADC_CTRL_LPADC_SAR2_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *LPPERI_Type) GetADC_CTRL_LPADC_SAR2_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0xff0000) >> 16
}
func (o *LPPERI_Type) SetADC_CTRL_LPADC_SAR1_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.ADC_CTRL.Reg, volatile.LoadUint32(&o.ADC_CTRL.Reg)&^(0xff000000)|value<<24)
}
func (o *LPPERI_Type) GetADC_CTRL_LPADC_SAR1_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.ADC_CTRL.Reg) & 0xff000000) >> 24
}

// LPPERI.LP_I2S_RXCLK_DIV_NUM: need_des
func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_NUM_LP_I2S_RX_CLKM_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_NUM.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_NUM.Reg)&^(0xff000000)|value<<24)
}
func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_NUM_LP_I2S_RX_CLKM_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_NUM.Reg) & 0xff000000) >> 24
}

// LPPERI.LP_I2S_RXCLK_DIV_XYZ: need_des
func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0x10)|value<<4)
}
func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0x10) >> 4
}
func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0x3fe0)|value<<5)
}
func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Z() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0x3fe0) >> 5
}
func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0x7fc000)|value<<14)
}
func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Y() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0x7fc000) >> 14
}
func (o *LPPERI_Type) SetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_X(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg)&^(0xff800000)|value<<23)
}
func (o *LPPERI_Type) GetLP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_X() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_RXCLK_DIV_XYZ.Reg) & 0xff800000) >> 23
}

// LPPERI.LP_I2S_TXCLK_DIV_NUM: need_des
func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_NUM_LP_I2S_TX_CLKM_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_NUM.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_NUM.Reg)&^(0xff000000)|value<<24)
}
func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_NUM_LP_I2S_TX_CLKM_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_NUM.Reg) & 0xff000000) >> 24
}

// LPPERI.LP_I2S_TXCLK_DIV_XYZ: need_des
func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_YN1(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0x10)|value<<4)
}
func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_YN1() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0x10) >> 4
}
func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Z(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0x3fe0)|value<<5)
}
func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Z() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0x3fe0) >> 5
}
func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Y(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0x7fc000)|value<<14)
}
func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Y() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0x7fc000) >> 14
}
func (o *LPPERI_Type) SetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_X(value uint32) {
	volatile.StoreUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg, volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg)&^(0xff800000)|value<<23)
}
func (o *LPPERI_Type) GetLP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_X() uint32 {
	return (volatile.LoadUint32(&o.LP_I2S_TXCLK_DIV_XYZ.Reg) & 0xff800000) >> 23
}

// LPPERI.DATE: need_des
func (o *LPPERI_Type) SetDATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *LPPERI_Type) GetDATE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31
}

// LP_SYS Peripheral
type LPSYSREG_Type struct {
	LP_SYS_VER_DATE         volatile.Register32 // 0x0
	CLK_SEL_CTRL            volatile.Register32 // 0x4
	SYS_CTRL                volatile.Register32 // 0x8
	LP_CLK_CTRL             volatile.Register32 // 0xC
	LP_RST_CTRL             volatile.Register32 // 0x10
	_                       [4]byte
	LP_CORE_BOOT_ADDR       volatile.Register32 // 0x18
	EXT_WAKEUP1             volatile.Register32 // 0x1C
	EXT_WAKEUP1_STATUS      volatile.Register32 // 0x20
	LP_TCM_PWR_CTRL         volatile.Register32 // 0x24
	BOOT_ADDR_HP_LP         volatile.Register32 // 0x28
	LP_STORE0               volatile.Register32 // 0x2C
	LP_STORE1               volatile.Register32 // 0x30
	LP_STORE2               volatile.Register32 // 0x34
	LP_STORE3               volatile.Register32 // 0x38
	LP_STORE4               volatile.Register32 // 0x3C
	LP_STORE5               volatile.Register32 // 0x40
	LP_STORE6               volatile.Register32 // 0x44
	LP_STORE7               volatile.Register32 // 0x48
	LP_STORE8               volatile.Register32 // 0x4C
	LP_STORE9               volatile.Register32 // 0x50
	LP_STORE10              volatile.Register32 // 0x54
	LP_STORE11              volatile.Register32 // 0x58
	LP_STORE12              volatile.Register32 // 0x5C
	LP_STORE13              volatile.Register32 // 0x60
	LP_STORE14              volatile.Register32 // 0x64
	LP_STORE15              volatile.Register32 // 0x68
	LP_PROBEA_CTRL          volatile.Register32 // 0x6C
	LP_PROBEB_CTRL          volatile.Register32 // 0x70
	LP_PROBE_OUT            volatile.Register32 // 0x74
	_                       [36]byte
	F2S_APB_BRG_CNTL        volatile.Register32 // 0x9C
	_                       [96]byte
	USB_CTRL                volatile.Register32 // 0x100
	_                       [8]byte
	ANA_XPD_PAD_GROUP       volatile.Register32 // 0x10C
	LP_TCM_RAM_RDN_ECO_CS   volatile.Register32 // 0x110
	LP_TCM_RAM_RDN_ECO_LOW  volatile.Register32 // 0x114
	LP_TCM_RAM_RDN_ECO_HIGH volatile.Register32 // 0x118
	LP_TCM_ROM_RDN_ECO_CS   volatile.Register32 // 0x11C
	LP_TCM_ROM_RDN_ECO_LOW  volatile.Register32 // 0x120
	LP_TCM_ROM_RDN_ECO_HIGH volatile.Register32 // 0x124
	_                       [8]byte
	HP_ROOT_CLK_CTRL        volatile.Register32 // 0x130
	_                       [4]byte
	LP_PMU_RDN_ECO_LOW      volatile.Register32 // 0x138
	LP_PMU_RDN_ECO_HIGH     volatile.Register32 // 0x13C
	_                       [8]byte
	PAD_COMP0               volatile.Register32 // 0x148
	PAD_COMP1               volatile.Register32 // 0x14C
	_                       [4]byte
	BACKUP_DMA_CFG0         volatile.Register32 // 0x154
	BACKUP_DMA_CFG1         volatile.Register32 // 0x158
	BACKUP_DMA_CFG2         volatile.Register32 // 0x15C
	_                       [4]byte
	BOOT_ADDR_HP_CORE1      volatile.Register32 // 0x164
	LP_ADDRHOLE_ADDR        volatile.Register32 // 0x168
	LP_ADDRHOLE_INFO        volatile.Register32 // 0x16C
	INT_RAW                 volatile.Register32 // 0x170
	INT_ST                  volatile.Register32 // 0x174
	INT_ENA                 volatile.Register32 // 0x178
	INT_CLR                 volatile.Register32 // 0x17C
	HP_MEM_AUX_CTRL         volatile.Register32 // 0x180
	LP_MEM_AUX_CTRL         volatile.Register32 // 0x184
	HP_ROM_AUX_CTRL         volatile.Register32 // 0x188
	LP_ROM_AUX_CTRL         volatile.Register32 // 0x18C
	LP_CPU_DBG_PC           volatile.Register32 // 0x190
	LP_CPU_EXC_PC           volatile.Register32 // 0x194
	IDBUS_ADDRHOLE_ADDR     volatile.Register32 // 0x198
	IDBUS_ADDRHOLE_INFO     volatile.Register32 // 0x19C
	HP_POR_RST_BYPASS_CTRL  volatile.Register32 // 0x1A0
	RNG_DATA                volatile.Register32 // 0x1A4
	_                       [8]byte
	LP_CORE_AHB_TIMEOUT     volatile.Register32 // 0x1B0
	LP_CORE_IBUS_TIMEOUT    volatile.Register32 // 0x1B4
	LP_CORE_DBUS_TIMEOUT    volatile.Register32 // 0x1B8
	LP_CORE_ERR_RESP_DIS    volatile.Register32 // 0x1BC
	RNG_CFG                 volatile.Register32 // 0x1C0
}

// LPSYSREG.LP_SYS_VER_DATE: need_des
func (o *LPSYSREG_Type) SetLP_SYS_VER_DATE(value uint32) {
	volatile.StoreUint32(&o.LP_SYS_VER_DATE.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_SYS_VER_DATE() uint32 {
	return volatile.LoadUint32(&o.LP_SYS_VER_DATE.Reg)
}

// LPSYSREG.CLK_SEL_CTRL: need_des
func (o *LPSYSREG_Type) SetCLK_SEL_CTRL_ENA_SW_SEL_SYS_CLK(value uint32) {
	volatile.StoreUint32(&o.CLK_SEL_CTRL.Reg, volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *LPSYSREG_Type) GetCLK_SEL_CTRL_ENA_SW_SEL_SYS_CLK() uint32 {
	return (volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg) & 0x10000) >> 16
}
func (o *LPSYSREG_Type) SetCLK_SEL_CTRL_SW_SYS_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.CLK_SEL_CTRL.Reg, volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *LPSYSREG_Type) GetCLK_SEL_CTRL_SW_SYS_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.CLK_SEL_CTRL.Reg) & 0x20000) >> 17
}

// LPSYSREG.SYS_CTRL: need_des
func (o *LPSYSREG_Type) SetSYS_CTRL_LP_CORE_DISABLE(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_LP_CORE_DISABLE() uint32 {
	return volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetSYS_CTRL_SYS_SW_RST(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_SYS_SW_RST() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x2) >> 1
}
func (o *LPSYSREG_Type) SetSYS_CTRL_FORCE_DOWNLOAD_BOOT(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_FORCE_DOWNLOAD_BOOT() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x4) >> 2
}
func (o *LPSYSREG_Type) SetSYS_CTRL_DIG_FIB(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x7f8)|value<<3)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_DIG_FIB() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x7f8) >> 3
}
func (o *LPSYSREG_Type) SetSYS_CTRL_IO_MUX_RESET_DISABLE(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_IO_MUX_RESET_DISABLE() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x800) >> 11
}
func (o *LPSYSREG_Type) SetSYS_CTRL_ANA_FIB(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1fc000)|value<<14)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_ANA_FIB() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1fc000) >> 14
}
func (o *LPSYSREG_Type) SetSYS_CTRL_LP_FIB_SEL(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x1fe00000)|value<<21)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_LP_FIB_SEL() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x1fe00000) >> 21
}
func (o *LPSYSREG_Type) SetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_CLR(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_CLR() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x20000000) >> 29
}
func (o *LPSYSREG_Type) SetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x40000000) >> 30
}
func (o *LPSYSREG_Type) SetSYS_CTRL_SYSTIMER_STALL_SEL(value uint32) {
	volatile.StoreUint32(&o.SYS_CTRL.Reg, volatile.LoadUint32(&o.SYS_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *LPSYSREG_Type) GetSYS_CTRL_SYSTIMER_STALL_SEL() uint32 {
	return (volatile.LoadUint32(&o.SYS_CTRL.Reg) & 0x80000000) >> 31
}

// LPSYSREG.LP_CLK_CTRL: need_des
func (o *LPSYSREG_Type) SetLP_CLK_CTRL_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_CLK_CTRL.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetLP_CLK_CTRL_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.LP_CLK_CTRL.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetLP_CLK_CTRL_LP_FOSC_HP_CKEN(value uint32) {
	volatile.StoreUint32(&o.LP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_CLK_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *LPSYSREG_Type) GetLP_CLK_CTRL_LP_FOSC_HP_CKEN() uint32 {
	return (volatile.LoadUint32(&o.LP_CLK_CTRL.Reg) & 0x4000) >> 14
}

// LPSYSREG.LP_RST_CTRL: need_des
func (o *LPSYSREG_Type) SetLP_RST_CTRL_ANA_RST_BYPASS(value uint32) {
	volatile.StoreUint32(&o.LP_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_RST_CTRL.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetLP_RST_CTRL_ANA_RST_BYPASS() uint32 {
	return volatile.LoadUint32(&o.LP_RST_CTRL.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetLP_RST_CTRL_SYS_RST_BYPASS(value uint32) {
	volatile.StoreUint32(&o.LP_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_RST_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetLP_RST_CTRL_SYS_RST_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.LP_RST_CTRL.Reg) & 0x2) >> 1
}
func (o *LPSYSREG_Type) SetLP_RST_CTRL_EFUSE_FORCE_NORST(value uint32) {
	volatile.StoreUint32(&o.LP_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_RST_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *LPSYSREG_Type) GetLP_RST_CTRL_EFUSE_FORCE_NORST() uint32 {
	return (volatile.LoadUint32(&o.LP_RST_CTRL.Reg) & 0x4) >> 2
}

// LPSYSREG.LP_CORE_BOOT_ADDR: need_des
func (o *LPSYSREG_Type) SetLP_CORE_BOOT_ADDR(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_BOOT_ADDR.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_CORE_BOOT_ADDR() uint32 {
	return volatile.LoadUint32(&o.LP_CORE_BOOT_ADDR.Reg)
}

// LPSYSREG.EXT_WAKEUP1: need_des
func (o *LPSYSREG_Type) SetEXT_WAKEUP1_SEL(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0xffff)|value)
}
func (o *LPSYSREG_Type) GetEXT_WAKEUP1_SEL() uint32 {
	return volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0xffff
}
func (o *LPSYSREG_Type) SetEXT_WAKEUP1_STATUS_CLR(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP1.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1.Reg)&^(0x10000)|value<<16)
}
func (o *LPSYSREG_Type) GetEXT_WAKEUP1_STATUS_CLR() uint32 {
	return (volatile.LoadUint32(&o.EXT_WAKEUP1.Reg) & 0x10000) >> 16
}

// LPSYSREG.EXT_WAKEUP1_STATUS: need_des
func (o *LPSYSREG_Type) SetEXT_WAKEUP1_STATUS(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP1_STATUS.Reg, volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg)&^(0xffff)|value)
}
func (o *LPSYSREG_Type) GetEXT_WAKEUP1_STATUS() uint32 {
	return volatile.LoadUint32(&o.EXT_WAKEUP1_STATUS.Reg) & 0xffff
}

// LPSYSREG.LP_TCM_PWR_CTRL: need_des
func (o *LPSYSREG_Type) SetLP_TCM_PWR_CTRL_LP_TCM_ROM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_PWR_CTRL.Reg, volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *LPSYSREG_Type) GetLP_TCM_PWR_CTRL_LP_TCM_ROM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg) & 0x20) >> 5
}
func (o *LPSYSREG_Type) SetLP_TCM_PWR_CTRL_LP_TCM_RAM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_PWR_CTRL.Reg, volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *LPSYSREG_Type) GetLP_TCM_PWR_CTRL_LP_TCM_RAM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.LP_TCM_PWR_CTRL.Reg) & 0x80) >> 7
}

// LPSYSREG.BOOT_ADDR_HP_LP: need_des
func (o *LPSYSREG_Type) SetBOOT_ADDR_HP_LP(value uint32) {
	volatile.StoreUint32(&o.BOOT_ADDR_HP_LP.Reg, value)
}
func (o *LPSYSREG_Type) GetBOOT_ADDR_HP_LP() uint32 {
	return volatile.LoadUint32(&o.BOOT_ADDR_HP_LP.Reg)
}

// LPSYSREG.LP_STORE0: need_des
func (o *LPSYSREG_Type) SetLP_STORE0(value uint32) {
	volatile.StoreUint32(&o.LP_STORE0.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE0() uint32 {
	return volatile.LoadUint32(&o.LP_STORE0.Reg)
}

// LPSYSREG.LP_STORE1: need_des
func (o *LPSYSREG_Type) SetLP_STORE1(value uint32) {
	volatile.StoreUint32(&o.LP_STORE1.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE1() uint32 {
	return volatile.LoadUint32(&o.LP_STORE1.Reg)
}

// LPSYSREG.LP_STORE2: need_des
func (o *LPSYSREG_Type) SetLP_STORE2(value uint32) {
	volatile.StoreUint32(&o.LP_STORE2.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE2() uint32 {
	return volatile.LoadUint32(&o.LP_STORE2.Reg)
}

// LPSYSREG.LP_STORE3: need_des
func (o *LPSYSREG_Type) SetLP_STORE3(value uint32) {
	volatile.StoreUint32(&o.LP_STORE3.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE3() uint32 {
	return volatile.LoadUint32(&o.LP_STORE3.Reg)
}

// LPSYSREG.LP_STORE4: need_des
func (o *LPSYSREG_Type) SetLP_STORE4(value uint32) {
	volatile.StoreUint32(&o.LP_STORE4.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE4() uint32 {
	return volatile.LoadUint32(&o.LP_STORE4.Reg)
}

// LPSYSREG.LP_STORE5: need_des
func (o *LPSYSREG_Type) SetLP_STORE5(value uint32) {
	volatile.StoreUint32(&o.LP_STORE5.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE5() uint32 {
	return volatile.LoadUint32(&o.LP_STORE5.Reg)
}

// LPSYSREG.LP_STORE6: need_des
func (o *LPSYSREG_Type) SetLP_STORE6(value uint32) {
	volatile.StoreUint32(&o.LP_STORE6.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE6() uint32 {
	return volatile.LoadUint32(&o.LP_STORE6.Reg)
}

// LPSYSREG.LP_STORE7: need_des
func (o *LPSYSREG_Type) SetLP_STORE7(value uint32) {
	volatile.StoreUint32(&o.LP_STORE7.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE7() uint32 {
	return volatile.LoadUint32(&o.LP_STORE7.Reg)
}

// LPSYSREG.LP_STORE8: need_des
func (o *LPSYSREG_Type) SetLP_STORE8(value uint32) {
	volatile.StoreUint32(&o.LP_STORE8.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE8() uint32 {
	return volatile.LoadUint32(&o.LP_STORE8.Reg)
}

// LPSYSREG.LP_STORE9: need_des
func (o *LPSYSREG_Type) SetLP_STORE9(value uint32) {
	volatile.StoreUint32(&o.LP_STORE9.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE9() uint32 {
	return volatile.LoadUint32(&o.LP_STORE9.Reg)
}

// LPSYSREG.LP_STORE10: need_des
func (o *LPSYSREG_Type) SetLP_STORE10(value uint32) {
	volatile.StoreUint32(&o.LP_STORE10.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE10() uint32 {
	return volatile.LoadUint32(&o.LP_STORE10.Reg)
}

// LPSYSREG.LP_STORE11: need_des
func (o *LPSYSREG_Type) SetLP_STORE11(value uint32) {
	volatile.StoreUint32(&o.LP_STORE11.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE11() uint32 {
	return volatile.LoadUint32(&o.LP_STORE11.Reg)
}

// LPSYSREG.LP_STORE12: need_des
func (o *LPSYSREG_Type) SetLP_STORE12(value uint32) {
	volatile.StoreUint32(&o.LP_STORE12.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE12() uint32 {
	return volatile.LoadUint32(&o.LP_STORE12.Reg)
}

// LPSYSREG.LP_STORE13: need_des
func (o *LPSYSREG_Type) SetLP_STORE13(value uint32) {
	volatile.StoreUint32(&o.LP_STORE13.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE13() uint32 {
	return volatile.LoadUint32(&o.LP_STORE13.Reg)
}

// LPSYSREG.LP_STORE14: need_des
func (o *LPSYSREG_Type) SetLP_STORE14(value uint32) {
	volatile.StoreUint32(&o.LP_STORE14.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE14() uint32 {
	return volatile.LoadUint32(&o.LP_STORE14.Reg)
}

// LPSYSREG.LP_STORE15: need_des
func (o *LPSYSREG_Type) SetLP_STORE15(value uint32) {
	volatile.StoreUint32(&o.LP_STORE15.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_STORE15() uint32 {
	return volatile.LoadUint32(&o.LP_STORE15.Reg)
}

// LPSYSREG.LP_PROBEA_CTRL: need_des
func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_A_MOD_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0xffff)|value)
}
func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_A_MOD_SEL() uint32 {
	return volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0xffff
}
func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_A_TOP_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_A_TOP_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0xff0000) >> 16
}
func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_L_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0x3000000)|value<<24)
}
func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_L_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0x3000000) >> 24
}
func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_H_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0xc000000)|value<<26)
}
func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_H_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0xc000000) >> 26
}
func (o *LPSYSREG_Type) SetLP_PROBEA_CTRL_PROBE_GLOBAL_EN(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEA_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *LPSYSREG_Type) GetLP_PROBEA_CTRL_PROBE_GLOBAL_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_PROBEA_CTRL.Reg) & 0x10000000) >> 28
}

// LPSYSREG.LP_PROBEB_CTRL: need_des
func (o *LPSYSREG_Type) SetLP_PROBEB_CTRL_PROBE_B_MOD_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEB_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg)&^(0xffff)|value)
}
func (o *LPSYSREG_Type) GetLP_PROBEB_CTRL_PROBE_B_MOD_SEL() uint32 {
	return volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg) & 0xffff
}
func (o *LPSYSREG_Type) SetLP_PROBEB_CTRL_PROBE_B_TOP_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEB_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *LPSYSREG_Type) GetLP_PROBEB_CTRL_PROBE_B_TOP_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg) & 0xff0000) >> 16
}
func (o *LPSYSREG_Type) SetLP_PROBEB_CTRL_PROBE_B_EN(value uint32) {
	volatile.StoreUint32(&o.LP_PROBEB_CTRL.Reg, volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *LPSYSREG_Type) GetLP_PROBEB_CTRL_PROBE_B_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_PROBEB_CTRL.Reg) & 0x1000000) >> 24
}

// LPSYSREG.LP_PROBE_OUT: need_des
func (o *LPSYSREG_Type) SetLP_PROBE_OUT(value uint32) {
	volatile.StoreUint32(&o.LP_PROBE_OUT.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_PROBE_OUT() uint32 {
	return volatile.LoadUint32(&o.LP_PROBE_OUT.Reg)
}

// LPSYSREG.F2S_APB_BRG_CNTL: need_des
func (o *LPSYSREG_Type) SetF2S_APB_BRG_CNTL_F2S_APB_POSTW_EN(value uint32) {
	volatile.StoreUint32(&o.F2S_APB_BRG_CNTL.Reg, volatile.LoadUint32(&o.F2S_APB_BRG_CNTL.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetF2S_APB_BRG_CNTL_F2S_APB_POSTW_EN() uint32 {
	return volatile.LoadUint32(&o.F2S_APB_BRG_CNTL.Reg) & 0x1
}

// LPSYSREG.USB_CTRL: need_des
func (o *LPSYSREG_Type) SetUSB_CTRL_SW_HW_USB_PHY_SEL(value uint32) {
	volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetUSB_CTRL_SW_HW_USB_PHY_SEL() uint32 {
	return volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetUSB_CTRL_SW_USB_PHY_SEL(value uint32) {
	volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetUSB_CTRL_SW_USB_PHY_SEL() uint32 {
	return (volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x2) >> 1
}
func (o *LPSYSREG_Type) SetUSB_CTRL_USBOTG20_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *LPSYSREG_Type) GetUSB_CTRL_USBOTG20_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x4) >> 2
}
func (o *LPSYSREG_Type) SetUSB_CTRL_USBOTG20_IN_SUSPEND(value uint32) {
	volatile.StoreUint32(&o.USB_CTRL.Reg, volatile.LoadUint32(&o.USB_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *LPSYSREG_Type) GetUSB_CTRL_USBOTG20_IN_SUSPEND() uint32 {
	return (volatile.LoadUint32(&o.USB_CTRL.Reg) & 0x8) >> 3
}

// LPSYSREG.ANA_XPD_PAD_GROUP: need_des
func (o *LPSYSREG_Type) SetANA_XPD_PAD_GROUP_ANA_REG_XPD_PAD_GROUP(value uint32) {
	volatile.StoreUint32(&o.ANA_XPD_PAD_GROUP.Reg, volatile.LoadUint32(&o.ANA_XPD_PAD_GROUP.Reg)&^(0xff)|value)
}
func (o *LPSYSREG_Type) GetANA_XPD_PAD_GROUP_ANA_REG_XPD_PAD_GROUP() uint32 {
	return volatile.LoadUint32(&o.ANA_XPD_PAD_GROUP.Reg) & 0xff
}

// LPSYSREG.LP_TCM_RAM_RDN_ECO_CS: need_des
func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_CS.Reg) & 0x2) >> 1
}

// LPSYSREG.LP_TCM_RAM_RDN_ECO_LOW: need_des
func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_LOW.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_LOW.Reg)
}

// LPSYSREG.LP_TCM_RAM_RDN_ECO_HIGH: need_des
func (o *LPSYSREG_Type) SetLP_TCM_RAM_RDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_RAM_RDN_ECO_HIGH.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_TCM_RAM_RDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.LP_TCM_RAM_RDN_ECO_HIGH.Reg)
}

// LPSYSREG.LP_TCM_ROM_RDN_ECO_CS: need_des
func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg, volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_CS.Reg) & 0x2) >> 1
}

// LPSYSREG.LP_TCM_ROM_RDN_ECO_LOW: need_des
func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_LOW.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_LOW.Reg)
}

// LPSYSREG.LP_TCM_ROM_RDN_ECO_HIGH: need_des
func (o *LPSYSREG_Type) SetLP_TCM_ROM_RDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.LP_TCM_ROM_RDN_ECO_HIGH.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_TCM_ROM_RDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.LP_TCM_ROM_RDN_ECO_HIGH.Reg)
}

// LPSYSREG.HP_ROOT_CLK_CTRL: need_des
func (o *LPSYSREG_Type) SetHP_ROOT_CLK_CTRL_CPU_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ROOT_CLK_CTRL.Reg, volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetHP_ROOT_CLK_CTRL_CPU_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetHP_ROOT_CLK_CTRL_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ROOT_CLK_CTRL.Reg, volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetHP_ROOT_CLK_CTRL_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ROOT_CLK_CTRL.Reg) & 0x2) >> 1
}

// LPSYSREG.LP_PMU_RDN_ECO_LOW: need_des
func (o *LPSYSREG_Type) SetLP_PMU_RDN_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.LP_PMU_RDN_ECO_LOW.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_PMU_RDN_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.LP_PMU_RDN_ECO_LOW.Reg)
}

// LPSYSREG.LP_PMU_RDN_ECO_HIGH: need_des
func (o *LPSYSREG_Type) SetLP_PMU_RDN_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.LP_PMU_RDN_ECO_HIGH.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_PMU_RDN_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.LP_PMU_RDN_ECO_HIGH.Reg)
}

// LPSYSREG.PAD_COMP0: need_des
func (o *LPSYSREG_Type) SetPAD_COMP0_DREF_COMP0(value uint32) {
	volatile.StoreUint32(&o.PAD_COMP0.Reg, volatile.LoadUint32(&o.PAD_COMP0.Reg)&^(0x7)|value)
}
func (o *LPSYSREG_Type) GetPAD_COMP0_DREF_COMP0() uint32 {
	return volatile.LoadUint32(&o.PAD_COMP0.Reg) & 0x7
}
func (o *LPSYSREG_Type) SetPAD_COMP0_MODE_COMP0(value uint32) {
	volatile.StoreUint32(&o.PAD_COMP0.Reg, volatile.LoadUint32(&o.PAD_COMP0.Reg)&^(0x8)|value<<3)
}
func (o *LPSYSREG_Type) GetPAD_COMP0_MODE_COMP0() uint32 {
	return (volatile.LoadUint32(&o.PAD_COMP0.Reg) & 0x8) >> 3
}
func (o *LPSYSREG_Type) SetPAD_COMP0_XPD_COMP0(value uint32) {
	volatile.StoreUint32(&o.PAD_COMP0.Reg, volatile.LoadUint32(&o.PAD_COMP0.Reg)&^(0x10)|value<<4)
}
func (o *LPSYSREG_Type) GetPAD_COMP0_XPD_COMP0() uint32 {
	return (volatile.LoadUint32(&o.PAD_COMP0.Reg) & 0x10) >> 4
}

// LPSYSREG.PAD_COMP1: need_des
func (o *LPSYSREG_Type) SetPAD_COMP1_DREF_COMP1(value uint32) {
	volatile.StoreUint32(&o.PAD_COMP1.Reg, volatile.LoadUint32(&o.PAD_COMP1.Reg)&^(0x7)|value)
}
func (o *LPSYSREG_Type) GetPAD_COMP1_DREF_COMP1() uint32 {
	return volatile.LoadUint32(&o.PAD_COMP1.Reg) & 0x7
}
func (o *LPSYSREG_Type) SetPAD_COMP1_MODE_COMP1(value uint32) {
	volatile.StoreUint32(&o.PAD_COMP1.Reg, volatile.LoadUint32(&o.PAD_COMP1.Reg)&^(0x8)|value<<3)
}
func (o *LPSYSREG_Type) GetPAD_COMP1_MODE_COMP1() uint32 {
	return (volatile.LoadUint32(&o.PAD_COMP1.Reg) & 0x8) >> 3
}
func (o *LPSYSREG_Type) SetPAD_COMP1_XPD_COMP1(value uint32) {
	volatile.StoreUint32(&o.PAD_COMP1.Reg, volatile.LoadUint32(&o.PAD_COMP1.Reg)&^(0x10)|value<<4)
}
func (o *LPSYSREG_Type) GetPAD_COMP1_XPD_COMP1() uint32 {
	return (volatile.LoadUint32(&o.PAD_COMP1.Reg) & 0x10) >> 4
}

// LPSYSREG.BACKUP_DMA_CFG0: need_des
func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_BURST_LIMIT_AON(value uint32) {
	volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0x1f)|value)
}
func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_BURST_LIMIT_AON() uint32 {
	return volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0x1f
}
func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_READ_INTERVAL_AON(value uint32) {
	volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0xfe0)|value<<5)
}
func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_READ_INTERVAL_AON() uint32 {
	return (volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0xfe0) >> 5
}
func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_LINK_BACKUP_TOUT_THRES_AON(value uint32) {
	volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0x3ff000)|value<<12)
}
func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_LINK_BACKUP_TOUT_THRES_AON() uint32 {
	return (volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0x3ff000) >> 12
}
func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG0_LINK_TOUT_THRES_AON(value uint32) {
	volatile.StoreUint32(&o.BACKUP_DMA_CFG0.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg)&^(0xffc00000)|value<<22)
}
func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG0_LINK_TOUT_THRES_AON() uint32 {
	return (volatile.LoadUint32(&o.BACKUP_DMA_CFG0.Reg) & 0xffc00000) >> 22
}

// LPSYSREG.BACKUP_DMA_CFG1: need_des
func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG1_AON_BYPASS(value uint32) {
	volatile.StoreUint32(&o.BACKUP_DMA_CFG1.Reg, volatile.LoadUint32(&o.BACKUP_DMA_CFG1.Reg)&^(0x80000000)|value<<31)
}
func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG1_AON_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.BACKUP_DMA_CFG1.Reg) & 0x80000000) >> 31
}

// LPSYSREG.BACKUP_DMA_CFG2: need_des
func (o *LPSYSREG_Type) SetBACKUP_DMA_CFG2(value uint32) {
	volatile.StoreUint32(&o.BACKUP_DMA_CFG2.Reg, value)
}
func (o *LPSYSREG_Type) GetBACKUP_DMA_CFG2() uint32 {
	return volatile.LoadUint32(&o.BACKUP_DMA_CFG2.Reg)
}

// LPSYSREG.BOOT_ADDR_HP_CORE1: need_des
func (o *LPSYSREG_Type) SetBOOT_ADDR_HP_CORE1(value uint32) {
	volatile.StoreUint32(&o.BOOT_ADDR_HP_CORE1.Reg, value)
}
func (o *LPSYSREG_Type) GetBOOT_ADDR_HP_CORE1() uint32 {
	return volatile.LoadUint32(&o.BOOT_ADDR_HP_CORE1.Reg)
}

// LPSYSREG.LP_ADDRHOLE_ADDR: need_des
func (o *LPSYSREG_Type) SetLP_ADDRHOLE_ADDR(value uint32) {
	volatile.StoreUint32(&o.LP_ADDRHOLE_ADDR.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_ADDRHOLE_ADDR() uint32 {
	return volatile.LoadUint32(&o.LP_ADDRHOLE_ADDR.Reg)
}

// LPSYSREG.LP_ADDRHOLE_INFO: need_des
func (o *LPSYSREG_Type) SetLP_ADDRHOLE_INFO_LP_ADDRHOLE_ID(value uint32) {
	volatile.StoreUint32(&o.LP_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg)&^(0x1f)|value)
}
func (o *LPSYSREG_Type) GetLP_ADDRHOLE_INFO_LP_ADDRHOLE_ID() uint32 {
	return volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg) & 0x1f
}
func (o *LPSYSREG_Type) SetLP_ADDRHOLE_INFO_LP_ADDRHOLE_WR(value uint32) {
	volatile.StoreUint32(&o.LP_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg)&^(0x20)|value<<5)
}
func (o *LPSYSREG_Type) GetLP_ADDRHOLE_INFO_LP_ADDRHOLE_WR() uint32 {
	return (volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg) & 0x20) >> 5
}
func (o *LPSYSREG_Type) SetLP_ADDRHOLE_INFO_LP_ADDRHOLE_SECURE(value uint32) {
	volatile.StoreUint32(&o.LP_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg)&^(0x40)|value<<6)
}
func (o *LPSYSREG_Type) GetLP_ADDRHOLE_INFO_LP_ADDRHOLE_SECURE() uint32 {
	return (volatile.LoadUint32(&o.LP_ADDRHOLE_INFO.Reg) & 0x40) >> 6
}

// LPSYSREG.INT_RAW: raw interrupt register
func (o *LPSYSREG_Type) SetINT_RAW_LP_ADDRHOLE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetINT_RAW_LP_ADDRHOLE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetINT_RAW_IDBUS_ADDRHOLE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetINT_RAW_IDBUS_ADDRHOLE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *LPSYSREG_Type) SetINT_RAW_LP_CORE_AHB_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *LPSYSREG_Type) GetINT_RAW_LP_CORE_AHB_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *LPSYSREG_Type) SetINT_RAW_LP_CORE_IBUS_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *LPSYSREG_Type) GetINT_RAW_LP_CORE_IBUS_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *LPSYSREG_Type) SetINT_RAW_LP_CORE_DBUS_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *LPSYSREG_Type) GetINT_RAW_LP_CORE_DBUS_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *LPSYSREG_Type) SetINT_RAW_ETM_TASK_ULP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *LPSYSREG_Type) GetINT_RAW_ETM_TASK_ULP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *LPSYSREG_Type) SetINT_RAW_SLOW_CLK_TICK_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *LPSYSREG_Type) GetINT_RAW_SLOW_CLK_TICK_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}

// LPSYSREG.INT_ST: masked interrupt register
func (o *LPSYSREG_Type) SetINT_ST_LP_ADDRHOLE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetINT_ST_LP_ADDRHOLE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetINT_ST_IDBUS_ADDRHOLE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetINT_ST_IDBUS_ADDRHOLE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *LPSYSREG_Type) SetINT_ST_LP_CORE_AHB_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *LPSYSREG_Type) GetINT_ST_LP_CORE_AHB_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *LPSYSREG_Type) SetINT_ST_LP_CORE_IBUS_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *LPSYSREG_Type) GetINT_ST_LP_CORE_IBUS_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *LPSYSREG_Type) SetINT_ST_LP_CORE_DBUS_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *LPSYSREG_Type) GetINT_ST_LP_CORE_DBUS_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *LPSYSREG_Type) SetINT_ST_ETM_TASK_ULP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *LPSYSREG_Type) GetINT_ST_ETM_TASK_ULP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *LPSYSREG_Type) SetINT_ST_SLOW_CLK_TICK_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *LPSYSREG_Type) GetINT_ST_SLOW_CLK_TICK_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}

// LPSYSREG.INT_ENA: masked interrupt register
func (o *LPSYSREG_Type) SetINT_ENA_LP_ADDRHOLE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetINT_ENA_LP_ADDRHOLE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetINT_ENA_IDBUS_ADDRHOLE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetINT_ENA_IDBUS_ADDRHOLE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *LPSYSREG_Type) SetINT_ENA_LP_CORE_AHB_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *LPSYSREG_Type) GetINT_ENA_LP_CORE_AHB_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *LPSYSREG_Type) SetINT_ENA_LP_CORE_IBUS_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *LPSYSREG_Type) GetINT_ENA_LP_CORE_IBUS_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *LPSYSREG_Type) SetINT_ENA_LP_CORE_DBUS_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *LPSYSREG_Type) GetINT_ENA_LP_CORE_DBUS_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *LPSYSREG_Type) SetINT_ENA_ETM_TASK_ULP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *LPSYSREG_Type) GetINT_ENA_ETM_TASK_ULP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *LPSYSREG_Type) SetINT_ENA_SLOW_CLK_TICK_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *LPSYSREG_Type) GetINT_ENA_SLOW_CLK_TICK_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}

// LPSYSREG.INT_CLR: interrupt clear register
func (o *LPSYSREG_Type) SetINT_CLR_LP_ADDRHOLE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetINT_CLR_LP_ADDRHOLE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetINT_CLR_IDBUS_ADDRHOLE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *LPSYSREG_Type) GetINT_CLR_IDBUS_ADDRHOLE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *LPSYSREG_Type) SetINT_CLR_LP_CORE_AHB_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *LPSYSREG_Type) GetINT_CLR_LP_CORE_AHB_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *LPSYSREG_Type) SetINT_CLR_LP_CORE_IBUS_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *LPSYSREG_Type) GetINT_CLR_LP_CORE_IBUS_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *LPSYSREG_Type) SetINT_CLR_LP_CORE_DBUS_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *LPSYSREG_Type) GetINT_CLR_LP_CORE_DBUS_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *LPSYSREG_Type) SetINT_CLR_ETM_TASK_ULP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *LPSYSREG_Type) GetINT_CLR_ETM_TASK_ULP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *LPSYSREG_Type) SetINT_CLR_SLOW_CLK_TICK_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *LPSYSREG_Type) GetINT_CLR_SLOW_CLK_TICK_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}

// LPSYSREG.HP_MEM_AUX_CTRL: need_des
func (o *LPSYSREG_Type) SetHP_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.HP_MEM_AUX_CTRL.Reg, value)
}
func (o *LPSYSREG_Type) GetHP_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.HP_MEM_AUX_CTRL.Reg)
}

// LPSYSREG.LP_MEM_AUX_CTRL: need_des
func (o *LPSYSREG_Type) SetLP_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.LP_MEM_AUX_CTRL.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.LP_MEM_AUX_CTRL.Reg)
}

// LPSYSREG.HP_ROM_AUX_CTRL: need_des
func (o *LPSYSREG_Type) SetHP_ROM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.HP_ROM_AUX_CTRL.Reg, value)
}
func (o *LPSYSREG_Type) GetHP_ROM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.HP_ROM_AUX_CTRL.Reg)
}

// LPSYSREG.LP_ROM_AUX_CTRL: need_des
func (o *LPSYSREG_Type) SetLP_ROM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.LP_ROM_AUX_CTRL.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_ROM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.LP_ROM_AUX_CTRL.Reg)
}

// LPSYSREG.LP_CPU_DBG_PC: need_des
func (o *LPSYSREG_Type) SetLP_CPU_DBG_PC(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_DBG_PC.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_CPU_DBG_PC() uint32 {
	return volatile.LoadUint32(&o.LP_CPU_DBG_PC.Reg)
}

// LPSYSREG.LP_CPU_EXC_PC: need_des
func (o *LPSYSREG_Type) SetLP_CPU_EXC_PC(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_EXC_PC.Reg, value)
}
func (o *LPSYSREG_Type) GetLP_CPU_EXC_PC() uint32 {
	return volatile.LoadUint32(&o.LP_CPU_EXC_PC.Reg)
}

// LPSYSREG.IDBUS_ADDRHOLE_ADDR: need_des
func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_ADDR(value uint32) {
	volatile.StoreUint32(&o.IDBUS_ADDRHOLE_ADDR.Reg, value)
}
func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_ADDR() uint32 {
	return volatile.LoadUint32(&o.IDBUS_ADDRHOLE_ADDR.Reg)
}

// LPSYSREG.IDBUS_ADDRHOLE_INFO: need_des
func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_ID(value uint32) {
	volatile.StoreUint32(&o.IDBUS_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg)&^(0x1f)|value)
}
func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_ID() uint32 {
	return volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg) & 0x1f
}
func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_WR(value uint32) {
	volatile.StoreUint32(&o.IDBUS_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg)&^(0x20)|value<<5)
}
func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_WR() uint32 {
	return (volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg) & 0x20) >> 5
}
func (o *LPSYSREG_Type) SetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_SECURE(value uint32) {
	volatile.StoreUint32(&o.IDBUS_ADDRHOLE_INFO.Reg, volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg)&^(0x40)|value<<6)
}
func (o *LPSYSREG_Type) GetIDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_SECURE() uint32 {
	return (volatile.LoadUint32(&o.IDBUS_ADDRHOLE_INFO.Reg) & 0x40) >> 6
}

// LPSYSREG.HP_POR_RST_BYPASS_CTRL: need_des
func (o *LPSYSREG_Type) SetHP_POR_RST_BYPASS_CTRL_HP_PO_CNNT_RSTN_BYPASS_CTRL(value uint32) {
	volatile.StoreUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg, volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg)&^(0xff00)|value<<8)
}
func (o *LPSYSREG_Type) GetHP_POR_RST_BYPASS_CTRL_HP_PO_CNNT_RSTN_BYPASS_CTRL() uint32 {
	return (volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg) & 0xff00) >> 8
}
func (o *LPSYSREG_Type) SetHP_POR_RST_BYPASS_CTRL_HP_PO_RSTN_BYPASS_CTRL(value uint32) {
	volatile.StoreUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg, volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg)&^(0xff000000)|value<<24)
}
func (o *LPSYSREG_Type) GetHP_POR_RST_BYPASS_CTRL_HP_PO_RSTN_BYPASS_CTRL() uint32 {
	return (volatile.LoadUint32(&o.HP_POR_RST_BYPASS_CTRL.Reg) & 0xff000000) >> 24
}

// LPSYSREG.RNG_DATA: rng data register
func (o *LPSYSREG_Type) SetRNG_DATA(value uint32) {
	volatile.StoreUint32(&o.RNG_DATA.Reg, value)
}
func (o *LPSYSREG_Type) GetRNG_DATA() uint32 {
	return volatile.LoadUint32(&o.RNG_DATA.Reg)
}

// LPSYSREG.LP_CORE_AHB_TIMEOUT: need_des
func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_EN() uint32 {
	return volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x1fffe)|value<<1)
}
func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x1fffe) >> 1
}
func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x20000)|value<<17)
}
func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x20000) >> 17
}
func (o *LPSYSREG_Type) SetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_AHB_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg)&^(0x7c0000)|value<<18)
}
func (o *LPSYSREG_Type) GetLP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_CORE_AHB_TIMEOUT.Reg) & 0x7c0000) >> 18
}

// LPSYSREG.LP_CORE_IBUS_TIMEOUT: need_des
func (o *LPSYSREG_Type) SetLP_CORE_IBUS_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetLP_CORE_IBUS_TIMEOUT_EN() uint32 {
	return volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetLP_CORE_IBUS_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1)
}
func (o *LPSYSREG_Type) GetLP_CORE_IBUS_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_CORE_IBUS_TIMEOUT.Reg) & 0x1fffe) >> 1
}

// LPSYSREG.LP_CORE_DBUS_TIMEOUT: need_des
func (o *LPSYSREG_Type) SetLP_CORE_DBUS_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetLP_CORE_DBUS_TIMEOUT_EN() uint32 {
	return volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetLP_CORE_DBUS_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg, volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg)&^(0x1fffe)|value<<1)
}
func (o *LPSYSREG_Type) GetLP_CORE_DBUS_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_CORE_DBUS_TIMEOUT.Reg) & 0x1fffe) >> 1
}

// LPSYSREG.LP_CORE_ERR_RESP_DIS: need_des
func (o *LPSYSREG_Type) SetLP_CORE_ERR_RESP_DIS(value uint32) {
	volatile.StoreUint32(&o.LP_CORE_ERR_RESP_DIS.Reg, volatile.LoadUint32(&o.LP_CORE_ERR_RESP_DIS.Reg)&^(0x7)|value)
}
func (o *LPSYSREG_Type) GetLP_CORE_ERR_RESP_DIS() uint32 {
	return volatile.LoadUint32(&o.LP_CORE_ERR_RESP_DIS.Reg) & 0x7
}

// LPSYSREG.RNG_CFG: rng cfg register
func (o *LPSYSREG_Type) SetRNG_CFG_RNG_TIMER_EN(value uint32) {
	volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1)|value)
}
func (o *LPSYSREG_Type) GetRNG_CFG_RNG_TIMER_EN() uint32 {
	return volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1
}
func (o *LPSYSREG_Type) SetRNG_CFG_RNG_TIMER_PSCALE(value uint32) {
	volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1fe)|value<<1)
}
func (o *LPSYSREG_Type) GetRNG_CFG_RNG_TIMER_PSCALE() uint32 {
	return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1fe) >> 1
}
func (o *LPSYSREG_Type) SetRNG_CFG_RNG_SAR_ENABLE(value uint32) {
	volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x200)|value<<9)
}
func (o *LPSYSREG_Type) GetRNG_CFG_RNG_SAR_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x200) >> 9
}
func (o *LPSYSREG_Type) SetRNG_CFG_RNG_SAR_DATA(value uint32) {
	volatile.StoreUint32(&o.RNG_CFG.Reg, volatile.LoadUint32(&o.RNG_CFG.Reg)&^(0x1fff0000)|value<<16)
}
func (o *LPSYSREG_Type) GetRNG_CFG_RNG_SAR_DATA() uint32 {
	return (volatile.LoadUint32(&o.RNG_CFG.Reg) & 0x1fff0000) >> 16
}

// LP_ANA_PERI Peripheral
type LP_ANA_PERI_Type struct {
	LP_ANA_BOD_MODE0_CNTL               volatile.Register32 // 0x0
	LP_ANA_BOD_MODE1_CNTL               volatile.Register32 // 0x4
	LP_ANA_VDD_SOURCE_CNTL              volatile.Register32 // 0x8
	LP_ANA_VDDBAT_BOD_CNTL              volatile.Register32 // 0xC
	LP_ANA_VDDBAT_CHARGE_CNTL           volatile.Register32 // 0x10
	LP_ANA_CK_GLITCH_CNTL               volatile.Register32 // 0x14
	LP_ANA_PG_GLITCH_CNTL               volatile.Register32 // 0x18
	LP_ANA_FIB_ENABLE                   volatile.Register32 // 0x1C
	LP_ANA_INT_RAW                      volatile.Register32 // 0x20
	LP_ANA_INT_ST                       volatile.Register32 // 0x24
	LP_ANA_INT_ENA                      volatile.Register32 // 0x28
	LP_ANA_INT_CLR                      volatile.Register32 // 0x2C
	LP_ANA_LP_INT_RAW                   volatile.Register32 // 0x30
	LP_ANA_LP_INT_ST                    volatile.Register32 // 0x34
	LP_ANA_LP_INT_ENA                   volatile.Register32 // 0x38
	LP_ANA_LP_INT_CLR                   volatile.Register32 // 0x3C
	_                                   [188]byte
	LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM volatile.Register32 // 0xFC
	LP_ANA_TOUCH_SCAN_CTRL1             volatile.Register32 // 0x100
	LP_ANA_TOUCH_SCAN_CTRL2             volatile.Register32 // 0x104
	LP_ANA_TOUCH_WORK                   volatile.Register32 // 0x108
	LP_ANA_TOUCH_WORK_MEAS_NUM          volatile.Register32 // 0x10C
	LP_ANA_TOUCH_FILTER1                volatile.Register32 // 0x110
	LP_ANA_TOUCH_FILTER2                volatile.Register32 // 0x114
	LP_ANA_TOUCH_FILTER3                volatile.Register32 // 0x118
	LP_ANA_TOUCH_SLP0                   volatile.Register32 // 0x11C
	LP_ANA_TOUCH_SLP1                   volatile.Register32 // 0x120
	LP_ANA_TOUCH_CLR                    volatile.Register32 // 0x124
	LP_ANA_TOUCH_APPROACH               volatile.Register32 // 0x128
	LP_ANA_TOUCH_FREQ0_SCAN_PARA        volatile.Register32 // 0x12C
	LP_ANA_TOUCH_FREQ1_SCAN_PARA        volatile.Register32 // 0x130
	LP_ANA_TOUCH_FREQ2_SCAN_PARA        volatile.Register32 // 0x134
	LP_ANA_TOUCH_ANA_PARA               volatile.Register32 // 0x138
	LP_ANA_TOUCH_MUX0                   volatile.Register32 // 0x13C
	LP_ANA_TOUCH_MUX1                   volatile.Register32 // 0x140
	LP_ANA_TOUCH_PAD0_TH0               volatile.Register32 // 0x144
	LP_ANA_TOUCH_PAD0_TH1               volatile.Register32 // 0x148
	LP_ANA_TOUCH_PAD0_TH2               volatile.Register32 // 0x14C
	LP_ANA_TOUCH_PAD1_TH0               volatile.Register32 // 0x150
	LP_ANA_TOUCH_PAD1_TH1               volatile.Register32 // 0x154
	LP_ANA_TOUCH_PAD1_TH2               volatile.Register32 // 0x158
	LP_ANA_TOUCH_PAD2_TH0               volatile.Register32 // 0x15C
	LP_ANA_TOUCH_PAD2_TH1               volatile.Register32 // 0x160
	LP_ANA_TOUCH_PAD2_TH2               volatile.Register32 // 0x164
	LP_ANA_TOUCH_PAD3_TH0               volatile.Register32 // 0x168
	LP_ANA_TOUCH_PAD3_TH1               volatile.Register32 // 0x16C
	LP_ANA_TOUCH_PAD3_TH2               volatile.Register32 // 0x170
	LP_ANA_TOUCH_PAD4_TH0               volatile.Register32 // 0x174
	LP_ANA_TOUCH_PAD4_TH1               volatile.Register32 // 0x178
	LP_ANA_TOUCH_PAD4_TH2               volatile.Register32 // 0x17C
	LP_ANA_TOUCH_PAD5_TH0               volatile.Register32 // 0x180
	LP_ANA_TOUCH_PAD5_TH1               volatile.Register32 // 0x184
	LP_ANA_TOUCH_PAD5_TH2               volatile.Register32 // 0x188
	LP_ANA_TOUCH_PAD6_TH0               volatile.Register32 // 0x18C
	LP_ANA_TOUCH_PAD6_TH1               volatile.Register32 // 0x190
	LP_ANA_TOUCH_PAD6_TH2               volatile.Register32 // 0x194
	LP_ANA_TOUCH_PAD7_TH0               volatile.Register32 // 0x198
	LP_ANA_TOUCH_PAD7_TH1               volatile.Register32 // 0x19C
	LP_ANA_TOUCH_PAD7_TH2               volatile.Register32 // 0x1A0
	LP_ANA_TOUCH_PAD8_TH0               volatile.Register32 // 0x1A4
	LP_ANA_TOUCH_PAD8_TH1               volatile.Register32 // 0x1A8
	LP_ANA_TOUCH_PAD8_TH2               volatile.Register32 // 0x1AC
	LP_ANA_TOUCH_PAD9_TH0               volatile.Register32 // 0x1B0
	LP_ANA_TOUCH_PAD9_TH1               volatile.Register32 // 0x1B4
	LP_ANA_TOUCH_PAD9_TH2               volatile.Register32 // 0x1B8
	LP_ANA_TOUCH_PAD10_TH0              volatile.Register32 // 0x1BC
	LP_ANA_TOUCH_PAD10_TH1              volatile.Register32 // 0x1C0
	LP_ANA_TOUCH_PAD10_TH2              volatile.Register32 // 0x1C4
	LP_ANA_TOUCH_PAD11_TH0              volatile.Register32 // 0x1C8
	LP_ANA_TOUCH_PAD11_TH1              volatile.Register32 // 0x1CC
	LP_ANA_TOUCH_PAD11_TH2              volatile.Register32 // 0x1D0
	LP_ANA_TOUCH_PAD12_TH0              volatile.Register32 // 0x1D4
	LP_ANA_TOUCH_PAD12_TH1              volatile.Register32 // 0x1D8
	LP_ANA_TOUCH_PAD12_TH2              volatile.Register32 // 0x1DC
	LP_ANA_TOUCH_PAD13_TH0              volatile.Register32 // 0x1E0
	LP_ANA_TOUCH_PAD13_TH1              volatile.Register32 // 0x1E4
	LP_ANA_TOUCH_PAD13_TH2              volatile.Register32 // 0x1E8
	LP_ANA_TOUCH_PAD14_TH0              volatile.Register32 // 0x1EC
	LP_ANA_TOUCH_PAD14_TH1              volatile.Register32 // 0x1F0
	LP_ANA_TOUCH_PAD14_TH2              volatile.Register32 // 0x1F4
	_                                   [516]byte
	LP_ANA_DATE                         volatile.Register32 // 0x3FC
}

// LP_ANA_PERI.LP_ANA_BOD_MODE0_CNTL: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x40)|value<<6)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x40) >> 6
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_PD_RF_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x80)|value<<7)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_PD_RF_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x80) >> 7
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_WAIT(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x3ff00)|value<<8)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_WAIT() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x3ff00) >> 8
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_WAIT(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0xffc0000)|value<<18)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_WAIT() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0xffc0000) >> 18
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x10000000) >> 28
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x20000000) >> 29
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x40000000) >> 30
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE0_CNTL.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_BOD_MODE1_CNTL: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_BOD_MODE1_CNTL_LP_ANA_BOD_MODE1_RESET_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_BOD_MODE1_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_BOD_MODE1_CNTL.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_BOD_MODE1_CNTL_LP_ANA_BOD_MODE1_RESET_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_BOD_MODE1_CNTL.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_VDD_SOURCE_CNTL: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_DETMODE_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_DETMODE_SEL() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VGOOD_EVENT_RECORD(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff00)|value<<8)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VGOOD_EVENT_RECORD() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff00) >> 8
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VBAT_EVENT_RECORD_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_VBAT_EVENT_RECORD_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff0000) >> 16
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_BOD_SOURCE_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg)&^(0xff000000)|value<<24)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDD_SOURCE_CNTL_LP_ANA_BOD_SOURCE_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDD_SOURCE_CNTL.Reg) & 0xff000000) >> 24
}

// LP_ANA_PERI.LP_ANA_VDDBAT_BOD_CNTL: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x1)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x1
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CHARGER(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x400)|value<<10)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CHARGER() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x400) >> 10
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x800)|value<<11)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x800) >> 11
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UPVOLTAGE_TARGET(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0x3ff000)|value<<12)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UPVOLTAGE_TARGET() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0x3ff000) >> 12
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg)&^(0xffc00000)|value<<22)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_BOD_CNTL.Reg) & 0xffc00000) >> 22
}

// LP_ANA_PERI.LP_ANA_VDDBAT_CHARGE_CNTL: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x1)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x1
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CHARGER(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x400)|value<<10)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CHARGER() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x400) >> 10
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CNT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x800)|value<<11)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CNT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x800) >> 11
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0x3ff000)|value<<12)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0x3ff000) >> 12
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg)&^(0xffc00000)|value<<22)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_VDDBAT_CHARGE_CNTL.Reg) & 0xffc00000) >> 22
}

// LP_ANA_PERI.LP_ANA_CK_GLITCH_CNTL: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_CK_GLITCH_CNTL_LP_ANA_CK_GLITCH_RESET_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_CK_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_CK_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_CK_GLITCH_CNTL_LP_ANA_CK_GLITCH_RESET_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_CK_GLITCH_CNTL.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_PG_GLITCH_CNTL: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_PG_GLITCH_CNTL_LP_ANA_POWER_GLITCH_RESET_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_PG_GLITCH_CNTL.Reg, volatile.LoadUint32(&o.LP_ANA_PG_GLITCH_CNTL.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_PG_GLITCH_CNTL_LP_ANA_POWER_GLITCH_RESET_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_PG_GLITCH_CNTL.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_FIB_ENABLE: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_FIB_ENABLE(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_FIB_ENABLE.Reg, value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_FIB_ENABLE() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_FIB_ENABLE.Reg)
}

// LP_ANA_PERI.LP_ANA_INT_RAW: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x8000000) >> 27
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x10000000) >> 28
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x20000000) >> 29
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_RAW_LP_ANA_BOD_MODE0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_RAW_LP_ANA_BOD_MODE0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_RAW.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_INT_ST: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x8000000) >> 27
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x10000000) >> 28
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x20000000) >> 29
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x40000000) >> 30
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ST_LP_ANA_BOD_MODE0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ST_LP_ANA_BOD_MODE0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ST.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_INT_ENA: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x8000000) >> 27
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x10000000) >> 28
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x20000000) >> 29
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_ENA_LP_ANA_BOD_MODE0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_ENA_LP_ANA_BOD_MODE0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_ENA.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_INT_CLR: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x8000000) >> 27
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x10000000) >> 28
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x20000000) >> 29
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_INT_CLR_LP_ANA_BOD_MODE0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_INT_CLR_LP_ANA_BOD_MODE0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_INT_CLR.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_LP_INT_RAW: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_RAW_LP_ANA_BOD_MODE0_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_RAW_LP_ANA_BOD_MODE0_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_LP_INT_RAW.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_LP_INT_ST: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_ST_LP_ANA_BOD_MODE0_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_ST_LP_ANA_BOD_MODE0_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_LP_INT_ST.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_LP_INT_ENA: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_ENA_LP_ANA_BOD_MODE0_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_ENA_LP_ANA_BOD_MODE0_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_LP_INT_ENA.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_LP_INT_CLR: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_LP_INT_CLR_LP_ANA_BOD_MODE0_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_LP_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_LP_INT_CLR_LP_ANA_BOD_MODE0_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_LP_INT_CLR.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg)&^(0x3ff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM2() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg) & 0x3ff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg)&^(0xffc00)|value<<10)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg) & 0xffc00) >> 10
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg)&^(0x3ff00000)|value<<20)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM.Reg) & 0x3ff00000) >> 20
}

// LP_ANA_PERI.LP_ANA_TOUCH_SCAN_CTRL1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SHIELD_PAD_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0x1)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SHIELD_PAD_EN() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0x1
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_INACTIVE_CONNECTION(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0x2)|value<<1)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_INACTIVE_CONNECTION() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0x2) >> 1
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SCAN_PAD_MAP(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0x1fffc)|value<<2)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SCAN_PAD_MAP() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0x1fffc) >> 2
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_XPD_WAIT(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg)&^(0xfffe0000)|value<<17)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_XPD_WAIT() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL1.Reg) & 0xfffe0000) >> 17
}

// LP_ANA_PERI.LP_ANA_TOUCH_SCAN_CTRL2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_NUM(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x3fffc0)|value<<6)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_NUM() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x3fffc0) >> 6
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x400000)|value<<22)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x400000) >> 22
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_OUT_RING(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x7800000)|value<<23)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_OUT_RING() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x7800000) >> 23
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x8000000) >> 27
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_CNT_LIMIT(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg)&^(0x30000000)|value<<28)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_CNT_LIMIT() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SCAN_CTRL2.Reg) & 0x30000000) >> 28
}

// LP_ANA_PERI.LP_ANA_TOUCH_WORK: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x70000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x70000) >> 16
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x380000)|value<<19)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x380000) >> 19
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x1c00000)|value<<22)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x1c00000) >> 22
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x2000000)|value<<25)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x2000000) >> 25
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_RESET(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x4000000)|value<<26)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_RESET() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x4000000) >> 26
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_GATE(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_GATE() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK.Reg) & 0x8000000) >> 27
}

// LP_ANA_PERI.LP_ANA_TOUCH_WORK_MEAS_NUM: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg)&^(0x3ff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM2() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg) & 0x3ff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg)&^(0xffc00)|value<<10)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg) & 0xffc00) >> 10
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg)&^(0x3ff00000)|value<<20)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_WORK_MEAS_NUM.Reg) & 0x3ff00000) >> 20
}

// LP_ANA_PERI.LP_ANA_TOUCH_FILTER1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_HYSTERESIS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x6)|value<<1)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_HYSTERESIS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x6) >> 1
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x18)|value<<3)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x18) >> 3
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NOISE_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x60)|value<<5)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NOISE_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x60) >> 5
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_SMOOTH_LVL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x180)|value<<7)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_SMOOTH_LVL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x180) >> 7
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_JITTER_STEP(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1e00)|value<<9)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_JITTER_STEP() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1e00) >> 9
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_MODE(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0xe000)|value<<13)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_MODE() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0xe000) >> 13
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x10000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x10000) >> 16
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_LIMIT(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1e0000)|value<<17)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_LIMIT() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1e0000) >> 17
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_APPROACH_LIMIT(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0x1fe00000)|value<<21)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_APPROACH_LIMIT() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0x1fe00000) >> 21
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_DEBOUNCE_LIMIT(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg)&^(0xe0000000)|value<<29)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_DEBOUNCE_LIMIT() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER1.Reg) & 0xe0000000) >> 29
}

// LP_ANA_PERI.LP_ANA_TOUCH_FILTER2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_OUTEN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg)&^(0x3fff8000)|value<<15)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_OUTEN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg) & 0x3fff8000) >> 15
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NOISE_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NOISE_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg) & 0x40000000) >> 30
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER2.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_TOUCH_FILTER3: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_BASELINE_SW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER3.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg)&^(0xffff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_BASELINE_SW() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg) & 0xffff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_UPDATE_BASELINE_SW(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FILTER3.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg)&^(0x10000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_UPDATE_BASELINE_SW() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FILTER3.Reg) & 0x10000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_SLP0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg)&^(0xffff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_TH0() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg) & 0xffff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_CHANNEL_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg)&^(0x10000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_CHANNEL_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg) & 0x10000) >> 16
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_PAD(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg)&^(0x1e0000)|value<<17)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_PAD() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP0.Reg) & 0x1e0000) >> 17
}

// LP_ANA_PERI.LP_ANA_TOUCH_SLP1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg)&^(0xffff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH2() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg) & 0xffff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_SLP1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_SLP1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_CLR: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_CHANNEL_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg)&^(0x7fff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_CHANNEL_CLR() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg) & 0x7fff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_STATUS_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_CLR.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_CLR_LP_ANA_TOUCH_STATUS_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_CLR.Reg) & 0x8000) >> 15
}

// LP_ANA_PERI.LP_ANA_TOUCH_APPROACH: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_PAD0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0xf)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_PAD0() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0xf
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_PAD1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0xf0)|value<<4)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_PAD1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0xf0) >> 4
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_PAD2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0xf00)|value<<8)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_PAD2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0xf00) >> 8
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_APPROACH_LP_ANA_TOUCH_SLP_APPROACH_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_APPROACH.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg)&^(0x1000)|value<<12)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_APPROACH_LP_ANA_TOUCH_SLP_APPROACH_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_APPROACH.Reg) & 0x1000) >> 12
}

// LP_ANA_PERI.LP_ANA_TOUCH_FREQ0_SCAN_PARA: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DCAP_LPF(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x7f)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DCAP_LPF() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x7f
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRES_LPF(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x180)|value<<7)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRES_LPF() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x180) >> 7
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_LS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x1e00)|value<<9)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_LS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x1e00) >> 9
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_HS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x3e000)|value<<13)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_HS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x3e000) >> 13
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DBIAS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg)&^(0x7c0000)|value<<18)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ0_SCAN_PARA.Reg) & 0x7c0000) >> 18
}

// LP_ANA_PERI.LP_ANA_TOUCH_FREQ1_SCAN_PARA: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DCAP_LPF(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x7f)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DCAP_LPF() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x7f
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRES_LPF(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x180)|value<<7)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRES_LPF() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x180) >> 7
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_LS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x1e00)|value<<9)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_LS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x1e00) >> 9
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_HS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x3e000)|value<<13)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_HS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x3e000) >> 13
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DBIAS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg)&^(0x7c0000)|value<<18)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ1_SCAN_PARA.Reg) & 0x7c0000) >> 18
}

// LP_ANA_PERI.LP_ANA_TOUCH_FREQ2_SCAN_PARA: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DCAP_LPF(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x7f)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DCAP_LPF() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x7f
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRES_LPF(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x180)|value<<7)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRES_LPF() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x180) >> 7
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_LS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x1e00)|value<<9)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_LS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x1e00) >> 9
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_HS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x3e000)|value<<13)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_HS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x3e000) >> 13
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DBIAS(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg)&^(0x7c0000)|value<<18)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_FREQ2_SCAN_PARA.Reg) & 0x7c0000) >> 18
}

// LP_ANA_PERI.LP_ANA_TOUCH_ANA_PARA: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_BUF_DRV(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg)&^(0x7)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_BUF_DRV() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg) & 0x7
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_EN_CAL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg)&^(0x8)|value<<3)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_EN_CAL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg) & 0x8) >> 3
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_DCAP_CAL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg)&^(0x7f0)|value<<4)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_DCAP_CAL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_ANA_PARA.Reg) & 0x7f0) >> 4
}

// LP_ANA_PERI.LP_ANA_TOUCH_MUX0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DATA_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x300)|value<<8)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DATA_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x300) >> 8
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FREQ_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0xc00)|value<<10)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FREQ_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0xc00) >> 10
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_BUFSEL(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x7fff000)|value<<12)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_BUFSEL() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x7fff000) >> 12
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x8000000) >> 27
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_FORCE(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_FORCE() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x10000000) >> 28
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FSM_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FSM_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x20000000) >> 29
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x40000000) >> 30
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_FORCE(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_FORCE() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX0.Reg) & 0x80000000) >> 31
}

// LP_ANA_PERI.LP_ANA_TOUCH_MUX1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_START(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg)&^(0x7fff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_START() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg) & 0x7fff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_XPD(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_MUX1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg)&^(0x3fff8000)|value<<15)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_XPD() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_MUX1.Reg) & 0x3fff8000) >> 15
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD0_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD0_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD0_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD0_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD0_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD0_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD0_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD0_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD0_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD0_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD0_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD0_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD0_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD1_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD1_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD1_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD1_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD1_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD1_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD1_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD1_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD1_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD1_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD1_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD1_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD1_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD2_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD2_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD2_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD2_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD2_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD2_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD2_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD2_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD2_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD2_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD2_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD2_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD2_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD3_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD3_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD3_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD3_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD3_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD3_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD3_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD3_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD3_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD3_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD3_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD3_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD3_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD4_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD4_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD4_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD4_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD4_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD4_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD4_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD4_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD4_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD4_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD4_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD4_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD4_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD5_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD5_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD5_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD5_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD5_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD5_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD5_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD5_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD5_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD5_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD5_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD5_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD5_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD6_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD6_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD6_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD6_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD6_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD6_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD6_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD6_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD6_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD6_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD6_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD6_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD6_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD7_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD7_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD7_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD7_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD7_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD7_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD7_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD7_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD7_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD7_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD7_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD7_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD7_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD8_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD8_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD8_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD8_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD8_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD8_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD8_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD8_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD8_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD8_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD8_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD8_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD8_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD9_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD9_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD9_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD9_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD9_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD9_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD9_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD9_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD9_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD9_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD9_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD9_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD9_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD10_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD10_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD10_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD10_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD10_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD10_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD10_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD10_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD10_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD10_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD10_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD10_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD10_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD11_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD11_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD11_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD11_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD11_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD11_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD11_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD11_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD11_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD11_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD11_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD11_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD11_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD12_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD12_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD12_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD12_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD12_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD12_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD12_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD12_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD12_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD12_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD12_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD12_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD12_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD13_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD13_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD13_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD13_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD13_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD13_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD13_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD13_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD13_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD13_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD13_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD13_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD13_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD14_TH0: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD14_TH0(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD14_TH0.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD14_TH0() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH0.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD14_TH1: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD14_TH1(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD14_TH1.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD14_TH1() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH1.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_TOUCH_PAD14_TH2: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_TOUCH_PAD14_TH2(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_TOUCH_PAD14_TH2.Reg, volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_TOUCH_PAD14_TH2() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_TOUCH_PAD14_TH2.Reg) & 0xffff0000) >> 16
}

// LP_ANA_PERI.LP_ANA_DATE: need_des
func (o *LP_ANA_PERI_Type) SetLP_ANA_DATE_LP_ANA_LP_ANA_DATE(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_DATE.Reg, volatile.LoadUint32(&o.LP_ANA_DATE.Reg)&^(0x7fffffff)|value)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_DATE_LP_ANA_LP_ANA_DATE() uint32 {
	return volatile.LoadUint32(&o.LP_ANA_DATE.Reg) & 0x7fffffff
}
func (o *LP_ANA_PERI_Type) SetLP_ANA_DATE_LP_ANA_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_ANA_DATE.Reg, volatile.LoadUint32(&o.LP_ANA_DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_ANA_PERI_Type) GetLP_ANA_DATE_LP_ANA_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_ANA_DATE.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST Peripheral
type LP_AON_CLKRST_Type struct {
	LP_AONCLKRST_LP_CLK_CONF            volatile.Register32 // 0x0
	LP_AONCLKRST_LP_CLK_PO_EN           volatile.Register32 // 0x4
	LP_AONCLKRST_LP_CLK_EN              volatile.Register32 // 0x8
	LP_AONCLKRST_LP_RST_EN              volatile.Register32 // 0xC
	LP_AONCLKRST_RESET_CAUSE            volatile.Register32 // 0x10
	LP_AONCLKRST_HPCPU_RESET_CTRL0      volatile.Register32 // 0x14
	LP_AONCLKRST_HPCPU_RESET_CTRL1      volatile.Register32 // 0x18
	LP_AONCLKRST_FOSC_CNTL              volatile.Register32 // 0x1C
	LP_AONCLKRST_RC32K_CNTL             volatile.Register32 // 0x20
	LP_AONCLKRST_SOSC_CNTL              volatile.Register32 // 0x24
	LP_AONCLKRST_CLK_TO_HP              volatile.Register32 // 0x28
	LP_AONCLKRST_LPMEM_FORCE            volatile.Register32 // 0x2C
	LP_AONCLKRST_XTAL32K                volatile.Register32 // 0x30
	LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS volatile.Register32 // 0x34
	LP_AONCLKRST_HPSYS_0_RESET_BYPASS   volatile.Register32 // 0x38
	LP_AONCLKRST_HPSYS_APM_RESET_BYPASS volatile.Register32 // 0x3C
	LP_AONCLKRST_HP_CLK_CTRL            volatile.Register32 // 0x40
	LP_AONCLKRST_HP_USB_CLKRST_CTRL0    volatile.Register32 // 0x44
	LP_AONCLKRST_HP_USB_CLKRST_CTRL1    volatile.Register32 // 0x48
	LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL volatile.Register32 // 0x4C
	_                                   [940]byte
	LP_AONCLKRST_DATE                   volatile.Register32 // 0x3FC
}

// LP_AON_CLKRST.LP_AONCLKRST_LP_CLK_CONF: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_SLOW_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0x3)|value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_SLOW_CLK_SEL() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0x3
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_FAST_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0xc)|value<<2)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_FAST_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0xc) >> 2
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_LP_PERI_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0x3f0)|value<<4)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_LP_PERI_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0x3f0) >> 4
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_ANA_SEL_REF_PLL8M(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg)&^(0x400)|value<<10)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_ANA_SEL_REF_PLL8M() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_CONF.Reg) & 0x400) >> 10
}

// LP_AON_CLKRST.LP_AONCLKRST_LP_CLK_PO_EN: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_CORE_EFUSE_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x1)|value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_CORE_EFUSE_OEN() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_LP_BUS_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x2)|value<<1)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_LP_BUS_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x2) >> 1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_SLOW_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x4)|value<<2)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_SLOW_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x4) >> 2
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_FAST_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x8)|value<<3)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_FAST_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x8) >> 3
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SLOW_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x10)|value<<4)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SLOW_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x10) >> 4
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FAST_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x20)|value<<5)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FAST_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x20) >> 5
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FOSC_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x40)|value<<6)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FOSC_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x40) >> 6
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_RC32K_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x80)|value<<7)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_RC32K_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x80) >> 7
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SXTAL_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x100)|value<<8)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SXTAL_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x100) >> 8
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SOSC_OEN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg)&^(0x200)|value<<9)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SOSC_OEN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_PO_EN.Reg) & 0x200) >> 9
}

// LP_AON_CLKRST.LP_AONCLKRST_LP_CLK_EN: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x4000000)|value<<26)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x4000000) >> 26
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_CK_EN_LP_RAM(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_CK_EN_LP_RAM() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x8000000) >> 27
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_ETM_EVENT_TICK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_ETM_EVENT_TICK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x10000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_PLL8M_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_PLL8M_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x20000000) >> 29
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_XTAL_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_XTAL_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x40000000) >> 30
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_FOSC_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_FOSC_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_CLK_EN.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_LP_RST_EN: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_HUK(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x1000000)|value<<24)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_HUK() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x1000000) >> 24
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_ANAPERI(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x2000000)|value<<25)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_ANAPERI() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x2000000) >> 25
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_WDT(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x4000000)|value<<26)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_WDT() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x4000000) >> 26
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_TIMER(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_TIMER() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x8000000) >> 27
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RTC(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RTC() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x10000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_MAILBOX(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_MAILBOX() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x20000000) >> 29
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_AONEFUSEREG(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_AONEFUSEREG() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x40000000) >> 30
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RAM(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RAM() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LP_RST_EN.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_RESET_CAUSE: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x3f)|value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x3f
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x40)|value<<6)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x40) >> 6
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x1f80)|value<<7)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x1f80) >> 7
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x2000)|value<<13)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x2000) >> 13
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0xfc000)|value<<14)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0xfc000) >> 14
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x100000)|value<<20)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x100000) >> 20
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x2000000)|value<<25)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x2000000) >> 25
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x4000000)|value<<26)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x4000000) >> 26
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x8000000) >> 27
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x10000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x20000000) >> 29
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x40000000) >> 30
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_RESET_CAUSE.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_HPCPU_RESET_CTRL0: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x1)|value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xe)|value<<1)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xe) >> 1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x10)|value<<4)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x10) >> 4
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_WAIT(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xfe0)|value<<5)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_WAIT() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xfe0) >> 5
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x1000)|value<<12)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x1000) >> 12
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_SW_RESET(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x2000)|value<<13)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_SW_RESET() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x2000) >> 13
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x4000)|value<<14)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x4000) >> 14
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x8000)|value<<15)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x8000) >> 15
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x10000)|value<<16)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x10000) >> 16
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xe0000)|value<<17)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xe0000) >> 17
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x100000)|value<<20)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x100000) >> 20
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_WAIT(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0xfe00000)|value<<21)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_WAIT() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0xfe00000) >> 21
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x10000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_SW_RESET(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_SW_RESET() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x20000000) >> 29
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x40000000) >> 30
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL0.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_HPCPU_RESET_CTRL1: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE0_SW_STALL_CODE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg)&^(0xff0000)|value<<16)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE0_SW_STALL_CODE() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg) & 0xff0000) >> 16
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE1_SW_STALL_CODE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg)&^(0xff000000)|value<<24)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE1_SW_STALL_CODE() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HPCPU_RESET_CTRL1.Reg) & 0xff000000) >> 24
}

// LP_AON_CLKRST.LP_AONCLKRST_FOSC_CNTL: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_FOSC_CNTL_LP_AONCLKRST_FOSC_DFREQ(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_FOSC_CNTL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_FOSC_CNTL.Reg)&^(0xffc00000)|value<<22)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_FOSC_CNTL_LP_AONCLKRST_FOSC_DFREQ() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_FOSC_CNTL.Reg) & 0xffc00000) >> 22
}

// LP_AON_CLKRST.LP_AONCLKRST_RC32K_CNTL: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_RC32K_CNTL(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_RC32K_CNTL.Reg, value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_RC32K_CNTL() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_RC32K_CNTL.Reg)
}

// LP_AON_CLKRST.LP_AONCLKRST_SOSC_CNTL: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_SOSC_CNTL_LP_AONCLKRST_SOSC_DFREQ(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_SOSC_CNTL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_SOSC_CNTL.Reg)&^(0xffc00000)|value<<22)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_SOSC_CNTL_LP_AONCLKRST_SOSC_DFREQ() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_SOSC_CNTL.Reg) & 0xffc00000) >> 22
}

// LP_AON_CLKRST.LP_AONCLKRST_CLK_TO_HP: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_XTAL32K(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_XTAL32K() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x10000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_SOSC(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_SOSC() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x20000000) >> 29
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_OSC32K(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_OSC32K() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x40000000) >> 30
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_FOSC(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_FOSC() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_CLK_TO_HP.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_LPMEM_FORCE: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_LPMEM_FORCE_LP_AONCLKRST_LPMEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_LPMEM_FORCE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_LPMEM_FORCE.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_LPMEM_FORCE_LP_AONCLKRST_LPMEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_LPMEM_FORCE.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_XTAL32K: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DRES_XTAL32K(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0x1c00000)|value<<22)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DRES_XTAL32K() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0x1c00000) >> 22
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DGM_XTAL32K(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0xe000000)|value<<25)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DGM_XTAL32K() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0xe000000) >> 25
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DBUF_XTAL32K(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DBUF_XTAL32K() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0x10000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DAC_XTAL32K(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_XTAL32K.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg)&^(0xe0000000)|value<<29)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_XTAL32K_LP_AONCLKRST_DAC_XTAL32K() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_XTAL32K.Reg) & 0xe0000000) >> 29
}

// LP_AON_CLKRST.LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_MUX_HPSYS_RESET_BYPASS(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS.Reg, value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_MUX_HPSYS_RESET_BYPASS() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS.Reg)
}

// LP_AON_CLKRST.LP_AONCLKRST_HPSYS_0_RESET_BYPASS: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPSYS_0_RESET_BYPASS(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPSYS_0_RESET_BYPASS.Reg, value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPSYS_0_RESET_BYPASS() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_HPSYS_0_RESET_BYPASS.Reg)
}

// LP_AON_CLKRST.LP_AONCLKRST_HPSYS_APM_RESET_BYPASS: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HPSYS_APM_RESET_BYPASS(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HPSYS_APM_RESET_BYPASS.Reg, value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HPSYS_APM_RESET_BYPASS() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_HPSYS_APM_RESET_BYPASS.Reg)
}

// LP_AON_CLKRST.LP_AONCLKRST_HP_CLK_CTRL: HP Clock Control Register.
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x3)|value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x3
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x4) >> 2
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x8) >> 3
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x10) >> 4
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x20) >> 5
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x40) >> 6
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x80) >> 7
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x100) >> 8
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x200) >> 9
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x400) >> 10
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x800) >> 11
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x1000) >> 12
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x2000) >> 13
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x4000) >> 14
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x8000) >> 15
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_32K_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_32K_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x10000) >> 16
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_RC_32K_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_RC_32K_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x20000) >> 17
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SOSC_150K_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SOSC_150K_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x40000) >> 18
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PLL_8M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x80000)|value<<19)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PLL_8M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x80000) >> 19
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x100000) >> 20
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x200000) >> 21
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x400000) >> 22
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x800000) >> 23
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_FOSC_20M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_FOSC_20M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x1000000) >> 24
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_40M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x2000000)|value<<25)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_40M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x2000000) >> 25
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_CPLL_400M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x4000000)|value<<26)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_CPLL_400M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x4000000) >> 26
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SPLL_480M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SPLL_480M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x8000000) >> 27
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_MPLL_500M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_MPLL_500M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_CLK_CTRL.Reg) & 0x10000000) >> 28
}

// LP_AON_CLKRST.LP_AONCLKRST_HP_USB_CLKRST_CTRL0: HP USB Clock Reset Control Register.
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_SLEEP_MODE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x1)|value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_SLEEP_MODE() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x2)|value<<1)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x2) >> 1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_SLEEP_MODE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x4)|value<<2)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_SLEEP_MODE() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x4) >> 2
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x8)|value<<3)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x8) >> 3
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_48M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x10)|value<<4)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_48M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x10) >> 4
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_DEVICE_48M_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x20)|value<<5)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_DEVICE_48M_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x20) >> 5
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_48M_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x3fc0)|value<<6)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_48M_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x3fc0) >> 6
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_25M_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x3fc000)|value<<14)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_25M_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x3fc000) >> 14
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_12M_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg)&^(0x3fc00000)|value<<22)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_12M_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL0.Reg) & 0x3fc00000) >> 22
}

// LP_AON_CLKRST.LP_AONCLKRST_HP_USB_CLKRST_CTRL1: HP USB Clock Reset Control Register.
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_ADP(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x1)|value)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_ADP() uint32 {
	return volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_PHY(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x2)|value<<1)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_PHY() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x2) >> 1
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x4)|value<<2)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x4) >> 2
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG11(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x8)|value<<3)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG11() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x8) >> 3
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_DEVICE(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x10)|value<<4)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_DEVICE() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x10) >> 4
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x30000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x30000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x40000000) >> 30
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_USB_CLKRST_CTRL1.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_SDMMC(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_SDMMC() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x10000000) >> 28
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_SDMMC(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_SDMMC() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x20000000) >> 29
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_EMAC(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_EMAC() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x40000000) >> 30
}
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_EMAC(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_EMAC() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL.Reg) & 0x80000000) >> 31
}

// LP_AON_CLKRST.LP_AONCLKRST_DATE: need_des
func (o *LP_AON_CLKRST_Type) SetLP_AONCLKRST_DATE_LP_AONCLKRST_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.LP_AONCLKRST_DATE.Reg, volatile.LoadUint32(&o.LP_AONCLKRST_DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_AON_CLKRST_Type) GetLP_AONCLKRST_DATE_LP_AONCLKRST_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_AONCLKRST_DATE.Reg) & 0x80000000) >> 31
}

// Low-power General Purpose Input/Output
type LP_GPIO_Type struct {
	CLK_EN             volatile.Register32 // 0x0
	VER_DATE           volatile.Register32 // 0x4
	OUT                volatile.Register32 // 0x8
	OUT_W1TS           volatile.Register32 // 0xC
	OUT_W1TC           volatile.Register32 // 0x10
	ENABLE             volatile.Register32 // 0x14
	ENABLE_W1TS        volatile.Register32 // 0x18
	ENABLE_W1TC        volatile.Register32 // 0x1C
	STATUS             volatile.Register32 // 0x20
	STATUS_W1TS        volatile.Register32 // 0x24
	STATUS_W1TC        volatile.Register32 // 0x28
	STATUS_NEXT        volatile.Register32 // 0x2C
	IN                 volatile.Register32 // 0x30
	PIN0               volatile.Register32 // 0x34
	PIN1               volatile.Register32 // 0x38
	PIN2               volatile.Register32 // 0x3C
	PIN3               volatile.Register32 // 0x40
	PIN4               volatile.Register32 // 0x44
	PIN5               volatile.Register32 // 0x48
	PIN6               volatile.Register32 // 0x4C
	PIN7               volatile.Register32 // 0x50
	PIN8               volatile.Register32 // 0x54
	PIN9               volatile.Register32 // 0x58
	PIN10              volatile.Register32 // 0x5C
	PIN11              volatile.Register32 // 0x60
	PIN12              volatile.Register32 // 0x64
	PIN13              volatile.Register32 // 0x68
	PIN14              volatile.Register32 // 0x6C
	PIN15              volatile.Register32 // 0x70
	FUNC0_IN_SEL_CFG   volatile.Register32 // 0x74
	FUNC1_IN_SEL_CFG   volatile.Register32 // 0x78
	FUNC2_IN_SEL_CFG   volatile.Register32 // 0x7C
	FUNC3_IN_SEL_CFG   volatile.Register32 // 0x80
	FUNC4_IN_SEL_CFG   volatile.Register32 // 0x84
	FUNC5_IN_SEL_CFG   volatile.Register32 // 0x88
	FUNC6_IN_SEL_CFG   volatile.Register32 // 0x8C
	FUNC7_IN_SEL_CFG   volatile.Register32 // 0x90
	FUNC8_IN_SEL_CFG   volatile.Register32 // 0x94
	FUNC9_IN_SEL_CFG   volatile.Register32 // 0x98
	FUNC10_IN_SEL_CFG  volatile.Register32 // 0x9C
	FUNC11_IN_SEL_CFG  volatile.Register32 // 0xA0
	FUNC12_IN_SEL_CFG  volatile.Register32 // 0xA4
	FUNC13_IN_SEL_CFG  volatile.Register32 // 0xA8
	_                  [72]byte
	FUNC0_OUT_SEL_CFG  volatile.Register32 // 0xF4
	FUNC1_OUT_SEL_CFG  volatile.Register32 // 0xF8
	FUNC2_OUT_SEL_CFG  volatile.Register32 // 0xFC
	FUNC3_OUT_SEL_CFG  volatile.Register32 // 0x100
	FUNC4_OUT_SEL_CFG  volatile.Register32 // 0x104
	FUNC5_OUT_SEL_CFG  volatile.Register32 // 0x108
	FUNC6_OUT_SEL_CFG  volatile.Register32 // 0x10C
	FUNC7_OUT_SEL_CFG  volatile.Register32 // 0x110
	FUNC8_OUT_SEL_CFG  volatile.Register32 // 0x114
	FUNC9_OUT_SEL_CFG  volatile.Register32 // 0x118
	FUNC10_OUT_SEL_CFG volatile.Register32 // 0x11C
	FUNC11_OUT_SEL_CFG volatile.Register32 // 0x120
	FUNC12_OUT_SEL_CFG volatile.Register32 // 0x124
	FUNC13_OUT_SEL_CFG volatile.Register32 // 0x128
	FUNC14_OUT_SEL_CFG volatile.Register32 // 0x12C
	FUNC15_OUT_SEL_CFG volatile.Register32 // 0x130
}

// LP_GPIO.CLK_EN: Reserved
func (o *LP_GPIO_Type) SetCLK_EN_REG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetCLK_EN_REG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1
}

// LP_GPIO.VER_DATE: Reserved
func (o *LP_GPIO_Type) SetVER_DATE_REG_VER_DATE(value uint32) {
	volatile.StoreUint32(&o.VER_DATE.Reg, volatile.LoadUint32(&o.VER_DATE.Reg)&^(0xfffffff)|value)
}
func (o *LP_GPIO_Type) GetVER_DATE_REG_VER_DATE() uint32 {
	return volatile.LoadUint32(&o.VER_DATE.Reg) & 0xfffffff
}

// LP_GPIO.OUT: Reserved
func (o *LP_GPIO_Type) SetOUT_REG_GPIO_OUT_DATA(value uint32) {
	volatile.StoreUint32(&o.OUT.Reg, volatile.LoadUint32(&o.OUT.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetOUT_REG_GPIO_OUT_DATA() uint32 {
	return volatile.LoadUint32(&o.OUT.Reg) & 0xffff
}

// LP_GPIO.OUT_W1TS: Reserved
func (o *LP_GPIO_Type) SetOUT_W1TS_REG_GPIO_OUT_DATA_W1TS(value uint32) {
	volatile.StoreUint32(&o.OUT_W1TS.Reg, volatile.LoadUint32(&o.OUT_W1TS.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetOUT_W1TS_REG_GPIO_OUT_DATA_W1TS() uint32 {
	return volatile.LoadUint32(&o.OUT_W1TS.Reg) & 0xffff
}

// LP_GPIO.OUT_W1TC: Reserved
func (o *LP_GPIO_Type) SetOUT_W1TC_REG_GPIO_OUT_DATA_W1TC(value uint32) {
	volatile.StoreUint32(&o.OUT_W1TC.Reg, volatile.LoadUint32(&o.OUT_W1TC.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetOUT_W1TC_REG_GPIO_OUT_DATA_W1TC() uint32 {
	return volatile.LoadUint32(&o.OUT_W1TC.Reg) & 0xffff
}

// LP_GPIO.ENABLE: Reserved
func (o *LP_GPIO_Type) SetENABLE_REG_GPIO_ENABLE_DATA(value uint32) {
	volatile.StoreUint32(&o.ENABLE.Reg, volatile.LoadUint32(&o.ENABLE.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetENABLE_REG_GPIO_ENABLE_DATA() uint32 {
	return volatile.LoadUint32(&o.ENABLE.Reg) & 0xffff
}

// LP_GPIO.ENABLE_W1TS: Reserved
func (o *LP_GPIO_Type) SetENABLE_W1TS_REG_GPIO_ENABLE_DATA_W1TS(value uint32) {
	volatile.StoreUint32(&o.ENABLE_W1TS.Reg, volatile.LoadUint32(&o.ENABLE_W1TS.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetENABLE_W1TS_REG_GPIO_ENABLE_DATA_W1TS() uint32 {
	return volatile.LoadUint32(&o.ENABLE_W1TS.Reg) & 0xffff
}

// LP_GPIO.ENABLE_W1TC: Reserved
func (o *LP_GPIO_Type) SetENABLE_W1TC_REG_GPIO_ENABLE_DATA_W1TC(value uint32) {
	volatile.StoreUint32(&o.ENABLE_W1TC.Reg, volatile.LoadUint32(&o.ENABLE_W1TC.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetENABLE_W1TC_REG_GPIO_ENABLE_DATA_W1TC() uint32 {
	return volatile.LoadUint32(&o.ENABLE_W1TC.Reg) & 0xffff
}

// LP_GPIO.STATUS: Reserved
func (o *LP_GPIO_Type) SetSTATUS_REG_GPIO_STATUS_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetSTATUS_REG_GPIO_STATUS_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg) & 0xffff
}

// LP_GPIO.STATUS_W1TS: Reserved
func (o *LP_GPIO_Type) SetSTATUS_W1TS_REG_GPIO_STATUS_DATA_W1TS(value uint32) {
	volatile.StoreUint32(&o.STATUS_W1TS.Reg, volatile.LoadUint32(&o.STATUS_W1TS.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetSTATUS_W1TS_REG_GPIO_STATUS_DATA_W1TS() uint32 {
	return volatile.LoadUint32(&o.STATUS_W1TS.Reg) & 0xffff
}

// LP_GPIO.STATUS_W1TC: Reserved
func (o *LP_GPIO_Type) SetSTATUS_W1TC_REG_GPIO_STATUS_DATA_W1TC(value uint32) {
	volatile.StoreUint32(&o.STATUS_W1TC.Reg, volatile.LoadUint32(&o.STATUS_W1TC.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetSTATUS_W1TC_REG_GPIO_STATUS_DATA_W1TC() uint32 {
	return volatile.LoadUint32(&o.STATUS_W1TC.Reg) & 0xffff
}

// LP_GPIO.STATUS_NEXT: Reserved
func (o *LP_GPIO_Type) SetSTATUS_NEXT_REG_GPIO_STATUS_INTERRUPT_NEXT(value uint32) {
	volatile.StoreUint32(&o.STATUS_NEXT.Reg, volatile.LoadUint32(&o.STATUS_NEXT.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetSTATUS_NEXT_REG_GPIO_STATUS_INTERRUPT_NEXT() uint32 {
	return volatile.LoadUint32(&o.STATUS_NEXT.Reg) & 0xffff
}

// LP_GPIO.IN: Reserved
func (o *LP_GPIO_Type) SetIN_REG_GPIO_IN_DATA_NEXT(value uint32) {
	volatile.StoreUint32(&o.IN.Reg, volatile.LoadUint32(&o.IN.Reg)&^(0xffff)|value)
}
func (o *LP_GPIO_Type) GetIN_REG_GPIO_IN_DATA_NEXT() uint32 {
	return volatile.LoadUint32(&o.IN.Reg) & 0xffff
}

// LP_GPIO.PIN0: Reserved
func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN0.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN0_REG_GPIO_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN0.Reg, volatile.LoadUint32(&o.PIN0.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN0_REG_GPIO_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN0.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN1: Reserved
func (o *LP_GPIO_Type) SetPIN1_REG_GPIO_PIN1_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN1_REG_GPIO_PIN1_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN1.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN1_REG_GPIO_PIN1_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN1_REG_GPIO_PIN1_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN1_REG_GPIO_PIN1_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN1_REG_GPIO_PIN1_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN1_REG_GPI1_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN1.Reg, volatile.LoadUint32(&o.PIN1.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN1_REG_GPI1_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN1.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN2: Reserved
func (o *LP_GPIO_Type) SetPIN2_REG_GPIO_PIN2_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN2_REG_GPIO_PIN2_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN2.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN2_REG_GPIO_PIN2_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN2_REG_GPIO_PIN2_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN2_REG_GPIO_PIN2_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN2_REG_GPIO_PIN2_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN2_REG_GPI2_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN2.Reg, volatile.LoadUint32(&o.PIN2.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN2_REG_GPI2_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN2.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN3: Reserved
func (o *LP_GPIO_Type) SetPIN3_REG_GPIO_PIN3_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN3_REG_GPIO_PIN3_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN3.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN3_REG_GPIO_PIN3_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN3_REG_GPIO_PIN3_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN3_REG_GPIO_PIN3_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN3_REG_GPIO_PIN3_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN3_REG_GPI3_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN3.Reg, volatile.LoadUint32(&o.PIN3.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN3_REG_GPI3_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN3.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN4: Reserved
func (o *LP_GPIO_Type) SetPIN4_REG_GPIO_PIN4_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN4_REG_GPIO_PIN4_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN4.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN4_REG_GPIO_PIN4_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN4_REG_GPIO_PIN4_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN4_REG_GPIO_PIN4_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN4_REG_GPIO_PIN4_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN4_REG_GPI4_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN4.Reg, volatile.LoadUint32(&o.PIN4.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN4_REG_GPI4_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN4.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN5: Reserved
func (o *LP_GPIO_Type) SetPIN5_REG_GPIO_PIN5_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN5_REG_GPIO_PIN5_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN5.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN5_REG_GPIO_PIN5_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN5_REG_GPIO_PIN5_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN5_REG_GPIO_PIN5_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN5_REG_GPIO_PIN5_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN5_REG_GPI5_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN5.Reg, volatile.LoadUint32(&o.PIN5.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN5_REG_GPI5_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN5.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN6: Reserved
func (o *LP_GPIO_Type) SetPIN6_REG_GPIO_PIN6_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN6_REG_GPIO_PIN6_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN6.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN6_REG_GPIO_PIN6_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN6_REG_GPIO_PIN6_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN6_REG_GPIO_PIN6_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN6_REG_GPIO_PIN6_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN6_REG_GPI6_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN6.Reg, volatile.LoadUint32(&o.PIN6.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN6_REG_GPI6_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN6.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN7: Reserved
func (o *LP_GPIO_Type) SetPIN7_REG_GPIO_PIN7_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN7_REG_GPIO_PIN7_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN7.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN7_REG_GPIO_PIN7_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN7_REG_GPIO_PIN7_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN7_REG_GPIO_PIN7_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN7_REG_GPIO_PIN7_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN7_REG_GPI7_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN7.Reg, volatile.LoadUint32(&o.PIN7.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN7_REG_GPI7_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN7.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN8: Reserved
func (o *LP_GPIO_Type) SetPIN8_REG_GPIO_PIN8_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN8_REG_GPIO_PIN8_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN8.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN8_REG_GPIO_PIN8_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN8_REG_GPIO_PIN8_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN8_REG_GPIO_PIN8_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN8_REG_GPIO_PIN8_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN8_REG_GPI8_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN8.Reg, volatile.LoadUint32(&o.PIN8.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN8_REG_GPI8_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN8.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN9: Reserved
func (o *LP_GPIO_Type) SetPIN9_REG_GPIO_PIN9_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN9_REG_GPIO_PIN9_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN9.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN9_REG_GPIO_PIN9_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN9_REG_GPIO_PIN9_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN9_REG_GPIO_PIN9_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN9_REG_GPIO_PIN9_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN9_REG_GPI9_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN9.Reg, volatile.LoadUint32(&o.PIN9.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN9_REG_GPI9_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN9.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN10: Reserved
func (o *LP_GPIO_Type) SetPIN10_REG_GPIO_PIN10_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN10_REG_GPIO_PIN10_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN10.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN10_REG_GPIO_PIN10_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN10_REG_GPIO_PIN10_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN10_REG_GPIO_PIN10_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN10_REG_GPIO_PIN10_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN10_REG_GPI10_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN10.Reg, volatile.LoadUint32(&o.PIN10.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN10_REG_GPI10_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN10.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN11: Reserved
func (o *LP_GPIO_Type) SetPIN11_REG_GPIO_PIN11_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN11_REG_GPIO_PIN11_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN11.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN11_REG_GPIO_PIN11_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN11_REG_GPIO_PIN11_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN11_REG_GPIO_PIN11_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN11_REG_GPIO_PIN11_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN11_REG_GPI11_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN11.Reg, volatile.LoadUint32(&o.PIN11.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN11_REG_GPI11_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN11.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN12: Reserved
func (o *LP_GPIO_Type) SetPIN12_REG_GPIO_PIN12_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN12_REG_GPIO_PIN12_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN12.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN12_REG_GPIO_PIN12_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN12_REG_GPIO_PIN12_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN12_REG_GPIO_PIN12_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN12_REG_GPIO_PIN12_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN12_REG_GPI12_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN12.Reg, volatile.LoadUint32(&o.PIN12.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN12_REG_GPI12_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN12.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN13: Reserved
func (o *LP_GPIO_Type) SetPIN13_REG_GPIO_PIN13_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN13_REG_GPIO_PIN13_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN13.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN13_REG_GPIO_PIN13_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN13_REG_GPIO_PIN13_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN13_REG_GPIO_PIN13_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN13_REG_GPIO_PIN13_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN13_REG_GPI13_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN13.Reg, volatile.LoadUint32(&o.PIN13.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN13_REG_GPI13_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN13.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN14: Reserved
func (o *LP_GPIO_Type) SetPIN14_REG_GPIO_PIN14_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN14_REG_GPIO_PIN14_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN14.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN14_REG_GPIO_PIN14_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN14_REG_GPIO_PIN14_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN14_REG_GPIO_PIN14_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN14_REG_GPIO_PIN14_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN14_REG_GPI14_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN14.Reg, volatile.LoadUint32(&o.PIN14.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN14_REG_GPI14_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN14.Reg) & 0x20) >> 5
}

// LP_GPIO.PIN15: Reserved
func (o *LP_GPIO_Type) SetPIN15_REG_GPIO_PIN15_WAKEUP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetPIN15_REG_GPIO_PIN15_WAKEUP_ENABLE() uint32 {
	return volatile.LoadUint32(&o.PIN15.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetPIN15_REG_GPIO_PIN15_INT_TYPE(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0xe)|value<<1)
}
func (o *LP_GPIO_Type) GetPIN15_REG_GPIO_PIN15_INT_TYPE() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0xe) >> 1
}
func (o *LP_GPIO_Type) SetPIN15_REG_GPIO_PIN15_PAD_DRIVER(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x10)|value<<4)
}
func (o *LP_GPIO_Type) GetPIN15_REG_GPIO_PIN15_PAD_DRIVER() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x10) >> 4
}
func (o *LP_GPIO_Type) SetPIN15_REG_GPI15_PIN0_EDGE_WAKEUP_CLR(value uint32) {
	volatile.StoreUint32(&o.PIN15.Reg, volatile.LoadUint32(&o.PIN15.Reg)&^(0x20)|value<<5)
}
func (o *LP_GPIO_Type) GetPIN15_REG_GPI15_PIN0_EDGE_WAKEUP_CLR() uint32 {
	return (volatile.LoadUint32(&o.PIN15.Reg) & 0x20) >> 5
}

// LP_GPIO.FUNC0_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC0_IN_SEL_CFG_REG_GPIO_SIG0_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC0_IN_SEL_CFG_REG_GPIO_SIG0_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC1_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC1_IN_SEL_CFG_REG_GPIO_SIG1_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC1_IN_SEL_CFG_REG_GPIO_SIG1_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC2_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC2_IN_SEL_CFG_REG_GPIO_SIG2_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC2_IN_SEL_CFG_REG_GPIO_SIG2_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC3_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC3_IN_SEL_CFG_REG_GPIO_SIG3_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC3_IN_SEL_CFG_REG_GPIO_SIG3_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC4_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC4_IN_SEL_CFG_REG_GPIO_SIG4_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC4_IN_SEL_CFG_REG_GPIO_SIG4_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC5_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC5_IN_SEL_CFG_REG_GPIO_SIG5_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC5_IN_SEL_CFG_REG_GPIO_SIG5_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC6_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC6_IN_SEL_CFG_REG_GPIO_SIG6_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC6_IN_SEL_CFG_REG_GPIO_SIG6_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC7_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC7_IN_SEL_CFG_REG_GPIO_SIG7_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC7_IN_SEL_CFG_REG_GPIO_SIG7_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC8_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC8_IN_SEL_CFG_REG_GPIO_SIG8_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC8_IN_SEL_CFG_REG_GPIO_SIG8_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC9_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC9_IN_SEL_CFG_REG_GPIO_SIG9_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC9_IN_SEL_CFG_REG_GPIO_SIG9_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC10_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC10_IN_SEL_CFG_REG_GPIO_SIG10_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC10_IN_SEL_CFG_REG_GPIO_SIG10_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC11_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC11_IN_SEL_CFG_REG_GPIO_SIG11_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC11_IN_SEL_CFG_REG_GPIO_SIG11_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC12_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC12_IN_SEL_CFG_REG_GPIO_SIG12_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC12_IN_SEL_CFG_REG_GPIO_SIG12_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC13_IN_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC13_IN_SEL_CFG_REG_GPIO_SIG13_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC13_IN_SEL_CFG_REG_GPIO_SIG13_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_IN_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg)&^(0xfc)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_IN_SEL_CFG.Reg) & 0xfc) >> 2
}

// LP_GPIO.FUNC0_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC0_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC0_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC1_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC1_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC1_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC2_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC2_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC2_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC3_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC3_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC3_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC4_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC4_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC4_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC5_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC5_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC5_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC6_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC6_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC6_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC7_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC7_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC7_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC8_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC8_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC8_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC9_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC9_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC9_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC10_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC10_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC10_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC11_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC11_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC11_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC12_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC12_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC12_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC13_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC13_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC13_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC14_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC14_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC14_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// LP_GPIO.FUNC15_OUT_SEL_CFG: Reserved
func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1)|value)
}
func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_INV_SEL() uint32 {
	return volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1
}
func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x2)|value<<1)
}
func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x2) >> 1
}
func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_INV_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x4)|value<<2)
}
func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_INV_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x4) >> 2
}
func (o *LP_GPIO_Type) SetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_SEL(value uint32) {
	volatile.StoreUint32(&o.FUNC15_OUT_SEL_CFG.Reg, volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg)&^(0x1f8)|value<<3)
}
func (o *LP_GPIO_Type) GetFUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_SEL() uint32 {
	return (volatile.LoadUint32(&o.FUNC15_OUT_SEL_CFG.Reg) & 0x1f8) >> 3
}

// Low-power I2C (Inter-Integrated Circuit) Controller 0
type LP_I2C_Type struct {
	SCL_LOW_PERIOD       volatile.Register32 // 0x0
	CTR                  volatile.Register32 // 0x4
	SR                   volatile.Register32 // 0x8
	TO                   volatile.Register32 // 0xC
	_                    [4]byte
	FIFO_ST              volatile.Register32 // 0x14
	FIFO_CONF            volatile.Register32 // 0x18
	DATA                 volatile.Register32 // 0x1C
	INT_RAW              volatile.Register32 // 0x20
	INT_CLR              volatile.Register32 // 0x24
	INT_ENA              volatile.Register32 // 0x28
	INT_STATUS           volatile.Register32 // 0x2C
	SDA_HOLD             volatile.Register32 // 0x30
	SDA_SAMPLE           volatile.Register32 // 0x34
	SCL_HIGH_PERIOD      volatile.Register32 // 0x38
	_                    [4]byte
	SCL_START_HOLD       volatile.Register32 // 0x40
	SCL_RSTART_SETUP     volatile.Register32 // 0x44
	SCL_STOP_HOLD        volatile.Register32 // 0x48
	SCL_STOP_SETUP       volatile.Register32 // 0x4C
	FILTER_CFG           volatile.Register32 // 0x50
	CLK_CONF             volatile.Register32 // 0x54
	COMD0                volatile.Register32 // 0x58
	COMD1                volatile.Register32 // 0x5C
	COMD2                volatile.Register32 // 0x60
	COMD3                volatile.Register32 // 0x64
	COMD4                volatile.Register32 // 0x68
	COMD5                volatile.Register32 // 0x6C
	COMD6                volatile.Register32 // 0x70
	COMD7                volatile.Register32 // 0x74
	SCL_ST_TIME_OUT      volatile.Register32 // 0x78
	SCL_MAIN_ST_TIME_OUT volatile.Register32 // 0x7C
	SCL_SP_CONF          volatile.Register32 // 0x80
	_                    [116]byte
	DATE                 volatile.Register32 // 0xF8
	_                    [4]byte
	TXFIFO_START_ADDR    volatile.Register32 // 0x100
	_                    [124]byte
	RXFIFO_START_ADDR    volatile.Register32 // 0x180
}

// LP_I2C.SCL_LOW_PERIOD: Configures the low level width of the SCL Clock
func (o *LP_I2C_Type) SetSCL_LOW_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_LOW_PERIOD.Reg, volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSCL_LOW_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_LOW_PERIOD.Reg) & 0x1ff
}

// LP_I2C.CTR: Transmission setting
func (o *LP_I2C_Type) SetCTR_SDA_FORCE_OUT(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x1)|value)
}
func (o *LP_I2C_Type) GetCTR_SDA_FORCE_OUT() uint32 {
	return volatile.LoadUint32(&o.CTR.Reg) & 0x1
}
func (o *LP_I2C_Type) SetCTR_SCL_FORCE_OUT(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2C_Type) GetCTR_SCL_FORCE_OUT() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x2) >> 1
}
func (o *LP_I2C_Type) SetCTR_SAMPLE_SCL_LEVEL(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2C_Type) GetCTR_SAMPLE_SCL_LEVEL() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x4) >> 2
}
func (o *LP_I2C_Type) SetCTR_RX_FULL_ACK_LEVEL(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2C_Type) GetCTR_RX_FULL_ACK_LEVEL() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x8) >> 3
}
func (o *LP_I2C_Type) SetCTR_TRANS_START(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2C_Type) GetCTR_TRANS_START() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x20) >> 5
}
func (o *LP_I2C_Type) SetCTR_TX_LSB_FIRST(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x40)|value<<6)
}
func (o *LP_I2C_Type) GetCTR_TX_LSB_FIRST() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x40) >> 6
}
func (o *LP_I2C_Type) SetCTR_RX_LSB_FIRST(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x80)|value<<7)
}
func (o *LP_I2C_Type) GetCTR_RX_LSB_FIRST() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x80) >> 7
}
func (o *LP_I2C_Type) SetCTR_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x100)|value<<8)
}
func (o *LP_I2C_Type) GetCTR_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x100) >> 8
}
func (o *LP_I2C_Type) SetCTR_ARBITRATION_EN(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x200)|value<<9)
}
func (o *LP_I2C_Type) GetCTR_ARBITRATION_EN() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x200) >> 9
}
func (o *LP_I2C_Type) SetCTR_FSM_RST(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x400)|value<<10)
}
func (o *LP_I2C_Type) GetCTR_FSM_RST() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x400) >> 10
}
func (o *LP_I2C_Type) SetCTR_CONF_UPGATE(value uint32) {
	volatile.StoreUint32(&o.CTR.Reg, volatile.LoadUint32(&o.CTR.Reg)&^(0x800)|value<<11)
}
func (o *LP_I2C_Type) GetCTR_CONF_UPGATE() uint32 {
	return (volatile.LoadUint32(&o.CTR.Reg) & 0x800) >> 11
}

// LP_I2C.SR: Describe I2C work status.
func (o *LP_I2C_Type) SetSR_RESP_REC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *LP_I2C_Type) GetSR_RESP_REC() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *LP_I2C_Type) SetSR_ARB_LOST(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2C_Type) GetSR_ARB_LOST() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *LP_I2C_Type) SetSR_BUS_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2C_Type) GetSR_BUS_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *LP_I2C_Type) SetSR_RXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1f00)|value<<8)
}
func (o *LP_I2C_Type) GetSR_RXFIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1f00) >> 8
}
func (o *LP_I2C_Type) SetSR_TXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7c0000)|value<<18)
}
func (o *LP_I2C_Type) GetSR_TXFIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x7c0000) >> 18
}
func (o *LP_I2C_Type) SetSR_SCL_MAIN_STATE_LAST(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x7000000)|value<<24)
}
func (o *LP_I2C_Type) GetSR_SCL_MAIN_STATE_LAST() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x7000000) >> 24
}
func (o *LP_I2C_Type) SetSR_SCL_STATE_LAST(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000000)|value<<28)
}
func (o *LP_I2C_Type) GetSR_SCL_STATE_LAST() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x70000000) >> 28
}

// LP_I2C.TO: Setting time out control for receiving data.
func (o *LP_I2C_Type) SetTO_TIME_OUT_VALUE(value uint32) {
	volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x1f)|value)
}
func (o *LP_I2C_Type) GetTO_TIME_OUT_VALUE() uint32 {
	return volatile.LoadUint32(&o.TO.Reg) & 0x1f
}
func (o *LP_I2C_Type) SetTO_TIME_OUT_EN(value uint32) {
	volatile.StoreUint32(&o.TO.Reg, volatile.LoadUint32(&o.TO.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2C_Type) GetTO_TIME_OUT_EN() uint32 {
	return (volatile.LoadUint32(&o.TO.Reg) & 0x20) >> 5
}

// LP_I2C.FIFO_ST: FIFO status register.
func (o *LP_I2C_Type) SetFIFO_ST_RXFIFO_RADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0xf)|value)
}
func (o *LP_I2C_Type) GetFIFO_ST_RXFIFO_RADDR() uint32 {
	return volatile.LoadUint32(&o.FIFO_ST.Reg) & 0xf
}
func (o *LP_I2C_Type) SetFIFO_ST_RXFIFO_WADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x1e0)|value<<5)
}
func (o *LP_I2C_Type) GetFIFO_ST_RXFIFO_WADDR() uint32 {
	return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x1e0) >> 5
}
func (o *LP_I2C_Type) SetFIFO_ST_TXFIFO_RADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x3c00)|value<<10)
}
func (o *LP_I2C_Type) GetFIFO_ST_TXFIFO_RADDR() uint32 {
	return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x3c00) >> 10
}
func (o *LP_I2C_Type) SetFIFO_ST_TXFIFO_WADDR(value uint32) {
	volatile.StoreUint32(&o.FIFO_ST.Reg, volatile.LoadUint32(&o.FIFO_ST.Reg)&^(0x78000)|value<<15)
}
func (o *LP_I2C_Type) GetFIFO_ST_TXFIFO_WADDR() uint32 {
	return (volatile.LoadUint32(&o.FIFO_ST.Reg) & 0x78000) >> 15
}

// LP_I2C.FIFO_CONF: FIFO configuration register.
func (o *LP_I2C_Type) SetFIFO_CONF_RXFIFO_WM_THRHD(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0xf)|value)
}
func (o *LP_I2C_Type) GetFIFO_CONF_RXFIFO_WM_THRHD() uint32 {
	return volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0xf
}
func (o *LP_I2C_Type) SetFIFO_CONF_TXFIFO_WM_THRHD(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1e0)|value<<5)
}
func (o *LP_I2C_Type) GetFIFO_CONF_TXFIFO_WM_THRHD() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1e0) >> 5
}
func (o *LP_I2C_Type) SetFIFO_CONF_NONFIFO_EN(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x400)|value<<10)
}
func (o *LP_I2C_Type) GetFIFO_CONF_NONFIFO_EN() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x400) >> 10
}
func (o *LP_I2C_Type) SetFIFO_CONF_RX_FIFO_RST(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *LP_I2C_Type) GetFIFO_CONF_RX_FIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x1000) >> 12
}
func (o *LP_I2C_Type) SetFIFO_CONF_TX_FIFO_RST(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *LP_I2C_Type) GetFIFO_CONF_TX_FIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x2000) >> 13
}
func (o *LP_I2C_Type) SetFIFO_CONF_FIFO_PRT_EN(value uint32) {
	volatile.StoreUint32(&o.FIFO_CONF.Reg, volatile.LoadUint32(&o.FIFO_CONF.Reg)&^(0x4000)|value<<14)
}
func (o *LP_I2C_Type) GetFIFO_CONF_FIFO_PRT_EN() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CONF.Reg) & 0x4000) >> 14
}

// LP_I2C.DATA: Rx FIFO read data.
func (o *LP_I2C_Type) SetDATA_FIFO_RDATA(value uint32) {
	volatile.StoreUint32(&o.DATA.Reg, volatile.LoadUint32(&o.DATA.Reg)&^(0xff)|value)
}
func (o *LP_I2C_Type) GetDATA_FIFO_RDATA() uint32 {
	return volatile.LoadUint32(&o.DATA.Reg) & 0xff
}

// LP_I2C.INT_RAW: Raw interrupt status
func (o *LP_I2C_Type) SetINT_RAW_RXFIFO_WM_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *LP_I2C_Type) GetINT_RAW_RXFIFO_WM_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *LP_I2C_Type) SetINT_RAW_TXFIFO_WM_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2C_Type) GetINT_RAW_TXFIFO_WM_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *LP_I2C_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2C_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *LP_I2C_Type) SetINT_RAW_END_DETECT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2C_Type) GetINT_RAW_END_DETECT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *LP_I2C_Type) SetINT_RAW_BYTE_TRANS_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2C_Type) GetINT_RAW_BYTE_TRANS_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *LP_I2C_Type) SetINT_RAW_ARBITRATION_LOST_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2C_Type) GetINT_RAW_ARBITRATION_LOST_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *LP_I2C_Type) SetINT_RAW_MST_TXFIFO_UDF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *LP_I2C_Type) GetINT_RAW_MST_TXFIFO_UDF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *LP_I2C_Type) SetINT_RAW_TRANS_COMPLETE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *LP_I2C_Type) GetINT_RAW_TRANS_COMPLETE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *LP_I2C_Type) SetINT_RAW_TIME_OUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *LP_I2C_Type) GetINT_RAW_TIME_OUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *LP_I2C_Type) SetINT_RAW_TRANS_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *LP_I2C_Type) GetINT_RAW_TRANS_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *LP_I2C_Type) SetINT_RAW_NACK_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *LP_I2C_Type) GetINT_RAW_NACK_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *LP_I2C_Type) SetINT_RAW_TXFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *LP_I2C_Type) GetINT_RAW_TXFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *LP_I2C_Type) SetINT_RAW_RXFIFO_UDF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *LP_I2C_Type) GetINT_RAW_RXFIFO_UDF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *LP_I2C_Type) SetINT_RAW_SCL_ST_TO_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *LP_I2C_Type) GetINT_RAW_SCL_ST_TO_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *LP_I2C_Type) SetINT_RAW_SCL_MAIN_ST_TO_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *LP_I2C_Type) GetINT_RAW_SCL_MAIN_ST_TO_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *LP_I2C_Type) SetINT_RAW_DET_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *LP_I2C_Type) GetINT_RAW_DET_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}

// LP_I2C.INT_CLR: Interrupt clear bits
func (o *LP_I2C_Type) SetINT_CLR_RXFIFO_WM_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *LP_I2C_Type) GetINT_CLR_RXFIFO_WM_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *LP_I2C_Type) SetINT_CLR_TXFIFO_WM_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2C_Type) GetINT_CLR_TXFIFO_WM_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *LP_I2C_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2C_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *LP_I2C_Type) SetINT_CLR_END_DETECT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2C_Type) GetINT_CLR_END_DETECT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *LP_I2C_Type) SetINT_CLR_BYTE_TRANS_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2C_Type) GetINT_CLR_BYTE_TRANS_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *LP_I2C_Type) SetINT_CLR_ARBITRATION_LOST_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2C_Type) GetINT_CLR_ARBITRATION_LOST_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *LP_I2C_Type) SetINT_CLR_MST_TXFIFO_UDF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *LP_I2C_Type) GetINT_CLR_MST_TXFIFO_UDF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *LP_I2C_Type) SetINT_CLR_TRANS_COMPLETE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *LP_I2C_Type) GetINT_CLR_TRANS_COMPLETE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *LP_I2C_Type) SetINT_CLR_TIME_OUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *LP_I2C_Type) GetINT_CLR_TIME_OUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *LP_I2C_Type) SetINT_CLR_TRANS_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *LP_I2C_Type) GetINT_CLR_TRANS_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *LP_I2C_Type) SetINT_CLR_NACK_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *LP_I2C_Type) GetINT_CLR_NACK_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *LP_I2C_Type) SetINT_CLR_TXFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *LP_I2C_Type) GetINT_CLR_TXFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *LP_I2C_Type) SetINT_CLR_RXFIFO_UDF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *LP_I2C_Type) GetINT_CLR_RXFIFO_UDF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *LP_I2C_Type) SetINT_CLR_SCL_ST_TO_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *LP_I2C_Type) GetINT_CLR_SCL_ST_TO_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *LP_I2C_Type) SetINT_CLR_SCL_MAIN_ST_TO_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *LP_I2C_Type) GetINT_CLR_SCL_MAIN_ST_TO_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *LP_I2C_Type) SetINT_CLR_DET_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *LP_I2C_Type) GetINT_CLR_DET_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}

// LP_I2C.INT_ENA: Interrupt enable bits
func (o *LP_I2C_Type) SetINT_ENA_RXFIFO_WM_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *LP_I2C_Type) GetINT_ENA_RXFIFO_WM_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *LP_I2C_Type) SetINT_ENA_TXFIFO_WM_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2C_Type) GetINT_ENA_TXFIFO_WM_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *LP_I2C_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2C_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *LP_I2C_Type) SetINT_ENA_END_DETECT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2C_Type) GetINT_ENA_END_DETECT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *LP_I2C_Type) SetINT_ENA_BYTE_TRANS_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2C_Type) GetINT_ENA_BYTE_TRANS_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *LP_I2C_Type) SetINT_ENA_ARBITRATION_LOST_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2C_Type) GetINT_ENA_ARBITRATION_LOST_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *LP_I2C_Type) SetINT_ENA_MST_TXFIFO_UDF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *LP_I2C_Type) GetINT_ENA_MST_TXFIFO_UDF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *LP_I2C_Type) SetINT_ENA_TRANS_COMPLETE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *LP_I2C_Type) GetINT_ENA_TRANS_COMPLETE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *LP_I2C_Type) SetINT_ENA_TIME_OUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *LP_I2C_Type) GetINT_ENA_TIME_OUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *LP_I2C_Type) SetINT_ENA_TRANS_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *LP_I2C_Type) GetINT_ENA_TRANS_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *LP_I2C_Type) SetINT_ENA_NACK_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *LP_I2C_Type) GetINT_ENA_NACK_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *LP_I2C_Type) SetINT_ENA_TXFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *LP_I2C_Type) GetINT_ENA_TXFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *LP_I2C_Type) SetINT_ENA_RXFIFO_UDF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *LP_I2C_Type) GetINT_ENA_RXFIFO_UDF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *LP_I2C_Type) SetINT_ENA_SCL_ST_TO_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *LP_I2C_Type) GetINT_ENA_SCL_ST_TO_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *LP_I2C_Type) SetINT_ENA_SCL_MAIN_ST_TO_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *LP_I2C_Type) GetINT_ENA_SCL_MAIN_ST_TO_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *LP_I2C_Type) SetINT_ENA_DET_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *LP_I2C_Type) GetINT_ENA_DET_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}

// LP_I2C.INT_STATUS: Status of captured I2C communication events
func (o *LP_I2C_Type) SetINT_STATUS_RXFIFO_WM_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1)|value)
}
func (o *LP_I2C_Type) GetINT_STATUS_RXFIFO_WM_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1
}
func (o *LP_I2C_Type) SetINT_STATUS_TXFIFO_WM_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2C_Type) GetINT_STATUS_TXFIFO_WM_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2) >> 1
}
func (o *LP_I2C_Type) SetINT_STATUS_RXFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2C_Type) GetINT_STATUS_RXFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4) >> 2
}
func (o *LP_I2C_Type) SetINT_STATUS_END_DETECT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2C_Type) GetINT_STATUS_END_DETECT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8) >> 3
}
func (o *LP_I2C_Type) SetINT_STATUS_BYTE_TRANS_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2C_Type) GetINT_STATUS_BYTE_TRANS_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x10) >> 4
}
func (o *LP_I2C_Type) SetINT_STATUS_ARBITRATION_LOST_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2C_Type) GetINT_STATUS_ARBITRATION_LOST_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x20) >> 5
}
func (o *LP_I2C_Type) SetINT_STATUS_MST_TXFIFO_UDF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *LP_I2C_Type) GetINT_STATUS_MST_TXFIFO_UDF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x40) >> 6
}
func (o *LP_I2C_Type) SetINT_STATUS_TRANS_COMPLETE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x80)|value<<7)
}
func (o *LP_I2C_Type) GetINT_STATUS_TRANS_COMPLETE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x80) >> 7
}
func (o *LP_I2C_Type) SetINT_STATUS_TIME_OUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x100)|value<<8)
}
func (o *LP_I2C_Type) GetINT_STATUS_TIME_OUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x100) >> 8
}
func (o *LP_I2C_Type) SetINT_STATUS_TRANS_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x200)|value<<9)
}
func (o *LP_I2C_Type) GetINT_STATUS_TRANS_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x200) >> 9
}
func (o *LP_I2C_Type) SetINT_STATUS_NACK_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x400)|value<<10)
}
func (o *LP_I2C_Type) GetINT_STATUS_NACK_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x400) >> 10
}
func (o *LP_I2C_Type) SetINT_STATUS_TXFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x800)|value<<11)
}
func (o *LP_I2C_Type) GetINT_STATUS_TXFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x800) >> 11
}
func (o *LP_I2C_Type) SetINT_STATUS_RXFIFO_UDF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x1000)|value<<12)
}
func (o *LP_I2C_Type) GetINT_STATUS_RXFIFO_UDF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x1000) >> 12
}
func (o *LP_I2C_Type) SetINT_STATUS_SCL_ST_TO_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x2000)|value<<13)
}
func (o *LP_I2C_Type) GetINT_STATUS_SCL_ST_TO_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x2000) >> 13
}
func (o *LP_I2C_Type) SetINT_STATUS_SCL_MAIN_ST_TO_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x4000)|value<<14)
}
func (o *LP_I2C_Type) GetINT_STATUS_SCL_MAIN_ST_TO_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x4000) >> 14
}
func (o *LP_I2C_Type) SetINT_STATUS_DET_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_STATUS.Reg, volatile.LoadUint32(&o.INT_STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *LP_I2C_Type) GetINT_STATUS_DET_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_STATUS.Reg) & 0x8000) >> 15
}

// LP_I2C.SDA_HOLD: Configures the hold time after a negative SCL edge.
func (o *LP_I2C_Type) SetSDA_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_HOLD.Reg, volatile.LoadUint32(&o.SDA_HOLD.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSDA_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SDA_HOLD.Reg) & 0x1ff
}

// LP_I2C.SDA_SAMPLE: Configures the sample time after a positive SCL edge.
func (o *LP_I2C_Type) SetSDA_SAMPLE_TIME(value uint32) {
	volatile.StoreUint32(&o.SDA_SAMPLE.Reg, volatile.LoadUint32(&o.SDA_SAMPLE.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSDA_SAMPLE_TIME() uint32 {
	return volatile.LoadUint32(&o.SDA_SAMPLE.Reg) & 0x1ff
}

// LP_I2C.SCL_HIGH_PERIOD: Configures the high level width of SCL
func (o *LP_I2C_Type) SetSCL_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSCL_HIGH_PERIOD() uint32 {
	return volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0x1ff
}
func (o *LP_I2C_Type) SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(value uint32) {
	volatile.StoreUint32(&o.SCL_HIGH_PERIOD.Reg, volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg)&^(0xfe00)|value<<9)
}
func (o *LP_I2C_Type) GetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.SCL_HIGH_PERIOD.Reg) & 0xfe00) >> 9
}

// LP_I2C.SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition
func (o *LP_I2C_Type) SetSCL_START_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_START_HOLD.Reg, volatile.LoadUint32(&o.SCL_START_HOLD.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSCL_START_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_START_HOLD.Reg) & 0x1ff
}

// LP_I2C.SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA
func (o *LP_I2C_Type) SetSCL_RSTART_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_RSTART_SETUP.Reg, volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSCL_RSTART_SETUP_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_RSTART_SETUP.Reg) & 0x1ff
}

// LP_I2C.SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition
func (o *LP_I2C_Type) SetSCL_STOP_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_STOP_HOLD.Reg, volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSCL_STOP_HOLD_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_STOP_HOLD.Reg) & 0x1ff
}

// LP_I2C.SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition
func (o *LP_I2C_Type) SetSCL_STOP_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SCL_STOP_SETUP.Reg, volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg)&^(0x1ff)|value)
}
func (o *LP_I2C_Type) GetSCL_STOP_SETUP_TIME() uint32 {
	return volatile.LoadUint32(&o.SCL_STOP_SETUP.Reg) & 0x1ff
}

// LP_I2C.FILTER_CFG: SCL and SDA filter configuration register
func (o *LP_I2C_Type) SetFILTER_CFG_SCL_FILTER_THRES(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf)|value)
}
func (o *LP_I2C_Type) GetFILTER_CFG_SCL_FILTER_THRES() uint32 {
	return volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf
}
func (o *LP_I2C_Type) SetFILTER_CFG_SDA_FILTER_THRES(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *LP_I2C_Type) GetFILTER_CFG_SDA_FILTER_THRES() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0xf0) >> 4
}
func (o *LP_I2C_Type) SetFILTER_CFG_SCL_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x100)|value<<8)
}
func (o *LP_I2C_Type) GetFILTER_CFG_SCL_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x100) >> 8
}
func (o *LP_I2C_Type) SetFILTER_CFG_SDA_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.FILTER_CFG.Reg, volatile.LoadUint32(&o.FILTER_CFG.Reg)&^(0x200)|value<<9)
}
func (o *LP_I2C_Type) GetFILTER_CFG_SDA_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CFG.Reg) & 0x200) >> 9
}

// LP_I2C.CLK_CONF: I2C CLK configuration register
func (o *LP_I2C_Type) SetCLK_CONF_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xff)|value)
}
func (o *LP_I2C_Type) GetCLK_CONF_SCLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xff
}
func (o *LP_I2C_Type) SetCLK_CONF_SCLK_DIV_A(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x3f00)|value<<8)
}
func (o *LP_I2C_Type) GetCLK_CONF_SCLK_DIV_A() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x3f00) >> 8
}
func (o *LP_I2C_Type) SetCLK_CONF_SCLK_DIV_B(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0xfc000)|value<<14)
}
func (o *LP_I2C_Type) GetCLK_CONF_SCLK_DIV_B() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0xfc000) >> 14
}
func (o *LP_I2C_Type) SetCLK_CONF_SCLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *LP_I2C_Type) GetCLK_CONF_SCLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x100000) >> 20
}
func (o *LP_I2C_Type) SetCLK_CONF_SCLK_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *LP_I2C_Type) GetCLK_CONF_SCLK_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x200000) >> 21
}

// LP_I2C.COMD0: I2C command register 0
func (o *LP_I2C_Type) SetCOMD0_COMMAND0(value uint32) {
	volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD0_COMMAND0() uint32 {
	return volatile.LoadUint32(&o.COMD0.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD0_COMMAND0_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD0.Reg, volatile.LoadUint32(&o.COMD0.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD0_COMMAND0_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD0.Reg) & 0x80000000) >> 31
}

// LP_I2C.COMD1: I2C command register 1
func (o *LP_I2C_Type) SetCOMD1_COMMAND1(value uint32) {
	volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD1_COMMAND1() uint32 {
	return volatile.LoadUint32(&o.COMD1.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD1_COMMAND1_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD1.Reg, volatile.LoadUint32(&o.COMD1.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD1_COMMAND1_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD1.Reg) & 0x80000000) >> 31
}

// LP_I2C.COMD2: I2C command register 2
func (o *LP_I2C_Type) SetCOMD2_COMMAND2(value uint32) {
	volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD2_COMMAND2() uint32 {
	return volatile.LoadUint32(&o.COMD2.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD2_COMMAND2_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD2.Reg, volatile.LoadUint32(&o.COMD2.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD2_COMMAND2_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD2.Reg) & 0x80000000) >> 31
}

// LP_I2C.COMD3: I2C command register 3
func (o *LP_I2C_Type) SetCOMD3_COMMAND3(value uint32) {
	volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD3_COMMAND3() uint32 {
	return volatile.LoadUint32(&o.COMD3.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD3_COMMAND3_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD3.Reg, volatile.LoadUint32(&o.COMD3.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD3_COMMAND3_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD3.Reg) & 0x80000000) >> 31
}

// LP_I2C.COMD4: I2C command register 4
func (o *LP_I2C_Type) SetCOMD4_COMMAND4(value uint32) {
	volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD4_COMMAND4() uint32 {
	return volatile.LoadUint32(&o.COMD4.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD4_COMMAND4_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD4.Reg, volatile.LoadUint32(&o.COMD4.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD4_COMMAND4_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD4.Reg) & 0x80000000) >> 31
}

// LP_I2C.COMD5: I2C command register 5
func (o *LP_I2C_Type) SetCOMD5_COMMAND5(value uint32) {
	volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD5_COMMAND5() uint32 {
	return volatile.LoadUint32(&o.COMD5.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD5_COMMAND5_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD5.Reg, volatile.LoadUint32(&o.COMD5.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD5_COMMAND5_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD5.Reg) & 0x80000000) >> 31
}

// LP_I2C.COMD6: I2C command register 6
func (o *LP_I2C_Type) SetCOMD6_COMMAND6(value uint32) {
	volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD6_COMMAND6() uint32 {
	return volatile.LoadUint32(&o.COMD6.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD6_COMMAND6_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD6.Reg, volatile.LoadUint32(&o.COMD6.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD6_COMMAND6_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD6.Reg) & 0x80000000) >> 31
}

// LP_I2C.COMD7: I2C command register 7
func (o *LP_I2C_Type) SetCOMD7_COMMAND7(value uint32) {
	volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x3fff)|value)
}
func (o *LP_I2C_Type) GetCOMD7_COMMAND7() uint32 {
	return volatile.LoadUint32(&o.COMD7.Reg) & 0x3fff
}
func (o *LP_I2C_Type) SetCOMD7_COMMAND7_DONE(value uint32) {
	volatile.StoreUint32(&o.COMD7.Reg, volatile.LoadUint32(&o.COMD7.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2C_Type) GetCOMD7_COMMAND7_DONE() uint32 {
	return (volatile.LoadUint32(&o.COMD7.Reg) & 0x80000000) >> 31
}

// LP_I2C.SCL_ST_TIME_OUT: SCL status time out register
func (o *LP_I2C_Type) SetSCL_ST_TIME_OUT_SCL_ST_TO_I2C(value uint32) {
	volatile.StoreUint32(&o.SCL_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg)&^(0x1f)|value)
}
func (o *LP_I2C_Type) GetSCL_ST_TIME_OUT_SCL_ST_TO_I2C() uint32 {
	return volatile.LoadUint32(&o.SCL_ST_TIME_OUT.Reg) & 0x1f
}

// LP_I2C.SCL_MAIN_ST_TIME_OUT: SCL main status time out register
func (o *LP_I2C_Type) SetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C(value uint32) {
	volatile.StoreUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg, volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg)&^(0x1f)|value)
}
func (o *LP_I2C_Type) GetSCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C() uint32 {
	return volatile.LoadUint32(&o.SCL_MAIN_ST_TIME_OUT.Reg) & 0x1f
}

// LP_I2C.SCL_SP_CONF: Power configuration register
func (o *LP_I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x1)|value)
}
func (o *LP_I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_EN() uint32 {
	return volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x1
}
func (o *LP_I2C_Type) SetSCL_SP_CONF_SCL_RST_SLV_NUM(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x3e)|value<<1)
}
func (o *LP_I2C_Type) GetSCL_SP_CONF_SCL_RST_SLV_NUM() uint32 {
	return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x3e) >> 1
}
func (o *LP_I2C_Type) SetSCL_SP_CONF_SCL_PD_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x40)|value<<6)
}
func (o *LP_I2C_Type) GetSCL_SP_CONF_SCL_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x40) >> 6
}
func (o *LP_I2C_Type) SetSCL_SP_CONF_SDA_PD_EN(value uint32) {
	volatile.StoreUint32(&o.SCL_SP_CONF.Reg, volatile.LoadUint32(&o.SCL_SP_CONF.Reg)&^(0x80)|value<<7)
}
func (o *LP_I2C_Type) GetSCL_SP_CONF_SDA_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.SCL_SP_CONF.Reg) & 0x80) >> 7
}

// LP_I2C.DATE: Version register
func (o *LP_I2C_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *LP_I2C_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// LP_I2C.TXFIFO_START_ADDR: I2C TXFIFO base address register
func (o *LP_I2C_Type) SetTXFIFO_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.TXFIFO_START_ADDR.Reg, value)
}
func (o *LP_I2C_Type) GetTXFIFO_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.TXFIFO_START_ADDR.Reg)
}

// LP_I2C.RXFIFO_START_ADDR: I2C RXFIFO base address register
func (o *LP_I2C_Type) SetRXFIFO_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.RXFIFO_START_ADDR.Reg, value)
}
func (o *LP_I2C_Type) GetRXFIFO_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.RXFIFO_START_ADDR.Reg)
}

// Low-power I2S (Inter-IC Sound) Controller 0
type LP_I2S_Type struct {
	VAD_CONF        volatile.Register32 // 0x0
	VAD_RESULT      volatile.Register32 // 0x4
	RX_MEM_CONF     volatile.Register32 // 0x8
	INT_RAW         volatile.Register32 // 0xC
	INT_ST          volatile.Register32 // 0x10
	INT_ENA         volatile.Register32 // 0x14
	INT_CLR         volatile.Register32 // 0x18
	_               [4]byte
	RX_CONF         volatile.Register32 // 0x20
	_               [4]byte
	RX_CONF1        volatile.Register32 // 0x28
	_               [36]byte
	RX_TDM_CTRL     volatile.Register32 // 0x50
	_               [4]byte
	RX_TIMING       volatile.Register32 // 0x58
	_               [4]byte
	LC_HUNG_CONF    volatile.Register32 // 0x60
	RXEOF_NUM       volatile.Register32 // 0x64
	CONF_SIGLE_DATA volatile.Register32 // 0x68
	_               [4]byte
	RX_PDM_CONF     volatile.Register32 // 0x70
	ECO_LOW         volatile.Register32 // 0x74
	ECO_HIGH        volatile.Register32 // 0x78
	ECO_CONF        volatile.Register32 // 0x7C
	VAD_PARAM0      volatile.Register32 // 0x80
	VAD_PARAM1      volatile.Register32 // 0x84
	VAD_PARAM2      volatile.Register32 // 0x88
	VAD_PARAM3      volatile.Register32 // 0x8C
	VAD_PARAM4      volatile.Register32 // 0x90
	VAD_PARAM5      volatile.Register32 // 0x94
	VAD_PARAM6      volatile.Register32 // 0x98
	VAD_PARAM7      volatile.Register32 // 0x9C
	VAD_PARAM8      volatile.Register32 // 0xA0
	_               [12]byte
	VAD_OB0         volatile.Register32 // 0xB0
	VAD_OB1         volatile.Register32 // 0xB4
	VAD_OB2         volatile.Register32 // 0xB8
	VAD_OB3         volatile.Register32 // 0xBC
	VAD_OB4         volatile.Register32 // 0xC0
	VAD_OB5         volatile.Register32 // 0xC4
	VAD_OB6         volatile.Register32 // 0xC8
	VAD_OB7         volatile.Register32 // 0xCC
	VAD_OB8         volatile.Register32 // 0xD0
	_               [36]byte
	CLK_GATE        volatile.Register32 // 0xF8
	DATE            volatile.Register32 // 0xFC
}

// LP_I2S.VAD_CONF: I2S VAD Configure register
func (o *LP_I2S_Type) SetVAD_CONF_VAD_EN(value uint32) {
	volatile.StoreUint32(&o.VAD_CONF.Reg, volatile.LoadUint32(&o.VAD_CONF.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetVAD_CONF_VAD_EN() uint32 {
	return volatile.LoadUint32(&o.VAD_CONF.Reg) & 0x1
}
func (o *LP_I2S_Type) SetVAD_CONF_VAD_RESET(value uint32) {
	volatile.StoreUint32(&o.VAD_CONF.Reg, volatile.LoadUint32(&o.VAD_CONF.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetVAD_CONF_VAD_RESET() uint32 {
	return (volatile.LoadUint32(&o.VAD_CONF.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetVAD_CONF_VAD_FORCE_START(value uint32) {
	volatile.StoreUint32(&o.VAD_CONF.Reg, volatile.LoadUint32(&o.VAD_CONF.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2S_Type) GetVAD_CONF_VAD_FORCE_START() uint32 {
	return (volatile.LoadUint32(&o.VAD_CONF.Reg) & 0x4) >> 2
}

// LP_I2S.VAD_RESULT: I2S VAD Result register
func (o *LP_I2S_Type) SetVAD_RESULT_VAD_FLAG(value uint32) {
	volatile.StoreUint32(&o.VAD_RESULT.Reg, volatile.LoadUint32(&o.VAD_RESULT.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetVAD_RESULT_VAD_FLAG() uint32 {
	return volatile.LoadUint32(&o.VAD_RESULT.Reg) & 0x1
}
func (o *LP_I2S_Type) SetVAD_RESULT_ENERGY_ENOUGH(value uint32) {
	volatile.StoreUint32(&o.VAD_RESULT.Reg, volatile.LoadUint32(&o.VAD_RESULT.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetVAD_RESULT_ENERGY_ENOUGH() uint32 {
	return (volatile.LoadUint32(&o.VAD_RESULT.Reg) & 0x2) >> 1
}

// LP_I2S.RX_MEM_CONF: I2S VAD Observe register
func (o *LP_I2S_Type) SetRX_MEM_CONF_RX_MEM_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_MEM_CONF.Reg, volatile.LoadUint32(&o.RX_MEM_CONF.Reg)&^(0x1ff)|value)
}
func (o *LP_I2S_Type) GetRX_MEM_CONF_RX_MEM_FIFO_CNT() uint32 {
	return volatile.LoadUint32(&o.RX_MEM_CONF.Reg) & 0x1ff
}
func (o *LP_I2S_Type) SetRX_MEM_CONF_RX_MEM_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.RX_MEM_CONF.Reg, volatile.LoadUint32(&o.RX_MEM_CONF.Reg)&^(0x1fe00)|value<<9)
}
func (o *LP_I2S_Type) GetRX_MEM_CONF_RX_MEM_THRESHOLD() uint32 {
	return (volatile.LoadUint32(&o.RX_MEM_CONF.Reg) & 0x1fe00) >> 9
}

// LP_I2S.INT_RAW: I2S interrupt raw register, valid in level.
func (o *LP_I2S_Type) SetINT_RAW_RX_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetINT_RAW_RX_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *LP_I2S_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetINT_RAW_RX_FIFOMEM_UDF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2S_Type) GetINT_RAW_RX_FIFOMEM_UDF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *LP_I2S_Type) SetINT_RAW_VAD_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2S_Type) GetINT_RAW_VAD_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *LP_I2S_Type) SetINT_RAW_VAD_RESET_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2S_Type) GetINT_RAW_VAD_RESET_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *LP_I2S_Type) SetINT_RAW_RX_MEM_THRESHOLD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2S_Type) GetINT_RAW_RX_MEM_THRESHOLD_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}

// LP_I2S.INT_ST: I2S interrupt status register.
func (o *LP_I2S_Type) SetINT_ST_RX_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetINT_ST_RX_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *LP_I2S_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetINT_ST_RX_FIFOMEM_UDF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2S_Type) GetINT_ST_RX_FIFOMEM_UDF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *LP_I2S_Type) SetINT_ST_LP_VAD_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2S_Type) GetINT_ST_LP_VAD_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *LP_I2S_Type) SetINT_ST_LP_VAD_RESET_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2S_Type) GetINT_ST_LP_VAD_RESET_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *LP_I2S_Type) SetINT_ST_RX_MEM_THRESHOLD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2S_Type) GetINT_ST_RX_MEM_THRESHOLD_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}

// LP_I2S.INT_ENA: I2S interrupt enable register.
func (o *LP_I2S_Type) SetINT_ENA_RX_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetINT_ENA_RX_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *LP_I2S_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetINT_ENA_RX_FIFOMEM_UDF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2S_Type) GetINT_ENA_RX_FIFOMEM_UDF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *LP_I2S_Type) SetINT_ENA_LP_VAD_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2S_Type) GetINT_ENA_LP_VAD_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *LP_I2S_Type) SetINT_ENA_LP_VAD_RESET_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2S_Type) GetINT_ENA_LP_VAD_RESET_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *LP_I2S_Type) SetINT_ENA_RX_MEM_THRESHOLD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2S_Type) GetINT_ENA_RX_MEM_THRESHOLD_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}

// LP_I2S.INT_CLR: I2S interrupt clear register.
func (o *LP_I2S_Type) SetINT_CLR_RX_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetINT_CLR_RX_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *LP_I2S_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetINT_CLR_RX_FIFOMEM_UDF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2S_Type) GetINT_CLR_RX_FIFOMEM_UDF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *LP_I2S_Type) SetINT_CLR_LP_VAD_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2S_Type) GetINT_CLR_LP_VAD_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *LP_I2S_Type) SetINT_CLR_LP_VAD_RESET_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2S_Type) GetINT_CLR_LP_VAD_RESET_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *LP_I2S_Type) SetINT_CLR_RX_MEM_THRESHOLD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2S_Type) GetINT_CLR_RX_MEM_THRESHOLD_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}

// LP_I2S.RX_CONF: I2S RX configure register
func (o *LP_I2S_Type) SetRX_CONF_RX_RESET(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_RESET() uint32 {
	return volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1
}
func (o *LP_I2S_Type) SetRX_CONF_RX_FIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_FIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetRX_CONF_RX_START(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_START() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x4) >> 2
}
func (o *LP_I2S_Type) SetRX_CONF_RX_SLAVE_MOD(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_SLAVE_MOD() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8) >> 3
}
func (o *LP_I2S_Type) SetRX_CONF_RX_FIFOMEM_RESET(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10)|value<<4)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_FIFOMEM_RESET() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10) >> 4
}
func (o *LP_I2S_Type) SetRX_CONF_RX_MONO(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20)|value<<5)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_MONO() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20) >> 5
}
func (o *LP_I2S_Type) SetRX_CONF_RX_BIG_ENDIAN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80)|value<<7)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_BIG_ENDIAN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80) >> 7
}
func (o *LP_I2S_Type) SetRX_CONF_RX_UPDATE(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100)|value<<8)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100) >> 8
}
func (o *LP_I2S_Type) SetRX_CONF_RX_MONO_FST_VLD(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x200)|value<<9)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_MONO_FST_VLD() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x200) >> 9
}
func (o *LP_I2S_Type) SetRX_CONF_RX_PCM_CONF(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0xc00)|value<<10)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_PCM_CONF() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0xc00) >> 10
}
func (o *LP_I2S_Type) SetRX_CONF_RX_PCM_BYPASS(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_PCM_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x1000) >> 12
}
func (o *LP_I2S_Type) SetRX_CONF_RX_STOP_MODE(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x6000)|value<<13)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_STOP_MODE() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x6000) >> 13
}
func (o *LP_I2S_Type) SetRX_CONF_RX_LEFT_ALIGN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x8000)|value<<15)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_LEFT_ALIGN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x8000) >> 15
}
func (o *LP_I2S_Type) SetRX_CONF_RX_24_FILL_EN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x10000)|value<<16)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_24_FILL_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x10000) >> 16
}
func (o *LP_I2S_Type) SetRX_CONF_RX_WS_IDLE_POL(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x20000)|value<<17)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_WS_IDLE_POL() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x20000) >> 17
}
func (o *LP_I2S_Type) SetRX_CONF_RX_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x40000)|value<<18)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x40000) >> 18
}
func (o *LP_I2S_Type) SetRX_CONF_RX_TDM_EN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_TDM_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x80000) >> 19
}
func (o *LP_I2S_Type) SetRX_CONF_RX_PDM_EN(value uint32) {
	volatile.StoreUint32(&o.RX_CONF.Reg, volatile.LoadUint32(&o.RX_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *LP_I2S_Type) GetRX_CONF_RX_PDM_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF.Reg) & 0x100000) >> 20
}

// LP_I2S.RX_CONF1: I2S RX configure register 1
func (o *LP_I2S_Type) SetRX_CONF1_RX_TDM_WS_WIDTH(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x7f)|value)
}
func (o *LP_I2S_Type) GetRX_CONF1_RX_TDM_WS_WIDTH() uint32 {
	return volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x7f
}
func (o *LP_I2S_Type) SetRX_CONF1_RX_BCK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f80)|value<<7)
}
func (o *LP_I2S_Type) GetRX_CONF1_RX_BCK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f80) >> 7
}
func (o *LP_I2S_Type) SetRX_CONF1_RX_BITS_MOD(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x3e000)|value<<13)
}
func (o *LP_I2S_Type) GetRX_CONF1_RX_BITS_MOD() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x3e000) >> 13
}
func (o *LP_I2S_Type) SetRX_CONF1_RX_HALF_SAMPLE_BITS(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0xfc0000)|value<<18)
}
func (o *LP_I2S_Type) GetRX_CONF1_RX_HALF_SAMPLE_BITS() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0xfc0000) >> 18
}
func (o *LP_I2S_Type) SetRX_CONF1_RX_TDM_CHAN_BITS(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x1f000000)|value<<24)
}
func (o *LP_I2S_Type) GetRX_CONF1_RX_TDM_CHAN_BITS() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x1f000000) >> 24
}
func (o *LP_I2S_Type) SetRX_CONF1_RX_MSB_SHIFT(value uint32) {
	volatile.StoreUint32(&o.RX_CONF1.Reg, volatile.LoadUint32(&o.RX_CONF1.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_I2S_Type) GetRX_CONF1_RX_MSB_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.RX_CONF1.Reg) & 0x20000000) >> 29
}

// LP_I2S.RX_TDM_CTRL: I2S TX TDM mode control register
func (o *LP_I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN() uint32 {
	return volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x1
}
func (o *LP_I2S_Type) SetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetRX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM(value uint32) {
	volatile.StoreUint32(&o.RX_TDM_CTRL.Reg, volatile.LoadUint32(&o.RX_TDM_CTRL.Reg)&^(0xf0000)|value<<16)
}
func (o *LP_I2S_Type) GetRX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM() uint32 {
	return (volatile.LoadUint32(&o.RX_TDM_CTRL.Reg) & 0xf0000) >> 16
}

// LP_I2S.RX_TIMING: I2S RX timing control register
func (o *LP_I2S_Type) SetRX_TIMING_RX_SD_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3)|value)
}
func (o *LP_I2S_Type) GetRX_TIMING_RX_SD_IN_DM() uint32 {
	return volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3
}
func (o *LP_I2S_Type) SetRX_TIMING_RX_WS_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000)|value<<16)
}
func (o *LP_I2S_Type) GetRX_TIMING_RX_WS_OUT_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000) >> 16
}
func (o *LP_I2S_Type) SetRX_TIMING_RX_BCK_OUT_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x300000)|value<<20)
}
func (o *LP_I2S_Type) GetRX_TIMING_RX_BCK_OUT_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x300000) >> 20
}
func (o *LP_I2S_Type) SetRX_TIMING_RX_WS_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x3000000)|value<<24)
}
func (o *LP_I2S_Type) GetRX_TIMING_RX_WS_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x3000000) >> 24
}
func (o *LP_I2S_Type) SetRX_TIMING_RX_BCK_IN_DM(value uint32) {
	volatile.StoreUint32(&o.RX_TIMING.Reg, volatile.LoadUint32(&o.RX_TIMING.Reg)&^(0x30000000)|value<<28)
}
func (o *LP_I2S_Type) GetRX_TIMING_RX_BCK_IN_DM() uint32 {
	return (volatile.LoadUint32(&o.RX_TIMING.Reg) & 0x30000000) >> 28
}

// LP_I2S.LC_HUNG_CONF: I2S HUNG configure register.
func (o *LP_I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0xff)|value)
}
func (o *LP_I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT() uint32 {
	return volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0xff
}
func (o *LP_I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT(value uint32) {
	volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x700)|value<<8)
}
func (o *LP_I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x700) >> 8
}
func (o *LP_I2S_Type) SetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA(value uint32) {
	volatile.StoreUint32(&o.LC_HUNG_CONF.Reg, volatile.LoadUint32(&o.LC_HUNG_CONF.Reg)&^(0x800)|value<<11)
}
func (o *LP_I2S_Type) GetLC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LC_HUNG_CONF.Reg) & 0x800) >> 11
}

// LP_I2S.RXEOF_NUM: I2S RX data number control register.
func (o *LP_I2S_Type) SetRXEOF_NUM_RX_EOF_NUM(value uint32) {
	volatile.StoreUint32(&o.RXEOF_NUM.Reg, volatile.LoadUint32(&o.RXEOF_NUM.Reg)&^(0xfff)|value)
}
func (o *LP_I2S_Type) GetRXEOF_NUM_RX_EOF_NUM() uint32 {
	return volatile.LoadUint32(&o.RXEOF_NUM.Reg) & 0xfff
}

// LP_I2S.CONF_SIGLE_DATA: I2S signal data register
func (o *LP_I2S_Type) SetCONF_SIGLE_DATA(value uint32) {
	volatile.StoreUint32(&o.CONF_SIGLE_DATA.Reg, value)
}
func (o *LP_I2S_Type) GetCONF_SIGLE_DATA() uint32 {
	return volatile.LoadUint32(&o.CONF_SIGLE_DATA.Reg)
}

// LP_I2S.RX_PDM_CONF: I2S RX configure register
func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM2PCM_EN(value uint32) {
	volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM2PCM_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x80000) >> 19
}
func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM_SINC_DSR_16_EN(value uint32) {
	volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM_SINC_DSR_16_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x100000) >> 20
}
func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM2PCM_AMPLIFY_NUM(value uint32) {
	volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x1e00000)|value<<21)
}
func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM2PCM_AMPLIFY_NUM() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x1e00000) >> 21
}
func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_PDM_HP_BYPASS(value uint32) {
	volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_PDM_HP_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x2000000) >> 25
}
func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_IIR_HP_MULT12_5(value uint32) {
	volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0x1c000000)|value<<26)
}
func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_IIR_HP_MULT12_5() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0x1c000000) >> 26
}
func (o *LP_I2S_Type) SetRX_PDM_CONF_RX_IIR_HP_MULT12_0(value uint32) {
	volatile.StoreUint32(&o.RX_PDM_CONF.Reg, volatile.LoadUint32(&o.RX_PDM_CONF.Reg)&^(0xe0000000)|value<<29)
}
func (o *LP_I2S_Type) GetRX_PDM_CONF_RX_IIR_HP_MULT12_0() uint32 {
	return (volatile.LoadUint32(&o.RX_PDM_CONF.Reg) & 0xe0000000) >> 29
}

// LP_I2S.ECO_LOW: I2S ECO register
func (o *LP_I2S_Type) SetECO_LOW(value uint32) {
	volatile.StoreUint32(&o.ECO_LOW.Reg, value)
}
func (o *LP_I2S_Type) GetECO_LOW() uint32 {
	return volatile.LoadUint32(&o.ECO_LOW.Reg)
}

// LP_I2S.ECO_HIGH: I2S ECO register
func (o *LP_I2S_Type) SetECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.ECO_HIGH.Reg, value)
}
func (o *LP_I2S_Type) GetECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.ECO_HIGH.Reg)
}

// LP_I2S.ECO_CONF: I2S ECO register
func (o *LP_I2S_Type) SetECO_CONF_RDN_ENA(value uint32) {
	volatile.StoreUint32(&o.ECO_CONF.Reg, volatile.LoadUint32(&o.ECO_CONF.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetECO_CONF_RDN_ENA() uint32 {
	return volatile.LoadUint32(&o.ECO_CONF.Reg) & 0x1
}
func (o *LP_I2S_Type) SetECO_CONF_RDN_RESULT(value uint32) {
	volatile.StoreUint32(&o.ECO_CONF.Reg, volatile.LoadUint32(&o.ECO_CONF.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetECO_CONF_RDN_RESULT() uint32 {
	return (volatile.LoadUint32(&o.ECO_CONF.Reg) & 0x2) >> 1
}

// LP_I2S.VAD_PARAM0: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM0_PARAM_MIN_ENERGY(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM0.Reg, volatile.LoadUint32(&o.VAD_PARAM0.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM0_PARAM_MIN_ENERGY() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM0.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_PARAM0_PARAM_INIT_FRAME_NUM(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM0.Reg, volatile.LoadUint32(&o.VAD_PARAM0.Reg)&^(0x1ff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM0_PARAM_INIT_FRAME_NUM() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM0.Reg) & 0x1ff0000) >> 16
}

// LP_I2S.VAD_PARAM1: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_MIN_SPEECH_COUNT(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0xf)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_MIN_SPEECH_COUNT() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0xf
}
func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_MAX_SPEECH_COUNT(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0x7f0)|value<<4)
}
func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_MAX_SPEECH_COUNT() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0x7f0) >> 4
}
func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_HANGOVER_SPEECH(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0xf800)|value<<11)
}
func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_HANGOVER_SPEECH() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0xf800) >> 11
}
func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_HANGOVER_SILENT(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0xff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_HANGOVER_SILENT() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0xff0000) >> 16
}
func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_MAX_OFFSET(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0x7f000000)|value<<24)
}
func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_MAX_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0x7f000000) >> 24
}
func (o *LP_I2S_Type) SetVAD_PARAM1_PARAM_SKIP_BAND_ENERGY(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM1.Reg, volatile.LoadUint32(&o.VAD_PARAM1.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_I2S_Type) GetVAD_PARAM1_PARAM_SKIP_BAND_ENERGY() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM1.Reg) & 0x80000000) >> 31
}

// LP_I2S.VAD_PARAM2: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM2_PARAM_NOISE_AMP_DOWN(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM2.Reg, volatile.LoadUint32(&o.VAD_PARAM2.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM2_PARAM_NOISE_AMP_DOWN() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM2.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_PARAM2_PARAM_NOISE_AMP_UP(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM2.Reg, volatile.LoadUint32(&o.VAD_PARAM2.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM2_PARAM_NOISE_AMP_UP() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM2.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_PARAM3: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM3_PARAM_NOISE_SPE_UP0(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM3.Reg, volatile.LoadUint32(&o.VAD_PARAM3.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM3_PARAM_NOISE_SPE_UP0() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM3.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_PARAM3_PARAM_NOISE_SPE_UP1(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM3.Reg, volatile.LoadUint32(&o.VAD_PARAM3.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM3_PARAM_NOISE_SPE_UP1() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM3.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_PARAM4: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM4_PARAM_NOISE_SPE_DOWN(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM4.Reg, volatile.LoadUint32(&o.VAD_PARAM4.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM4_PARAM_NOISE_SPE_DOWN() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM4.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_PARAM4_PARAM_NOISE_MEAN_DOWN(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM4.Reg, volatile.LoadUint32(&o.VAD_PARAM4.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM4_PARAM_NOISE_MEAN_DOWN() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM4.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_PARAM5: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM5_PARAM_NOISE_MEAN_UP0(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM5.Reg, volatile.LoadUint32(&o.VAD_PARAM5.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM5_PARAM_NOISE_MEAN_UP0() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM5.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_PARAM5_PARAM_NOISE_MEAN_UP1(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM5.Reg, volatile.LoadUint32(&o.VAD_PARAM5.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM5_PARAM_NOISE_MEAN_UP1() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM5.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_PARAM6: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM6_PARAM_NOISE_STD_FS_THSL(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM6.Reg, volatile.LoadUint32(&o.VAD_PARAM6.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM6_PARAM_NOISE_STD_FS_THSL() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM6.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_PARAM6_PARAM_NOISE_STD_FS_THSH(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM6.Reg, volatile.LoadUint32(&o.VAD_PARAM6.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM6_PARAM_NOISE_STD_FS_THSH() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM6.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_PARAM7: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM7_PARAM_THRES_UPD_BASE(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM7.Reg, volatile.LoadUint32(&o.VAD_PARAM7.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM7_PARAM_THRES_UPD_BASE() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM7.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_PARAM7_PARAM_THRES_UPD_VARY(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM7.Reg, volatile.LoadUint32(&o.VAD_PARAM7.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM7_PARAM_THRES_UPD_VARY() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM7.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_PARAM8: I2S VAD Parameter register
func (o *LP_I2S_Type) SetVAD_PARAM8_PARAM_THRES_UPD_BDL(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM8.Reg, volatile.LoadUint32(&o.VAD_PARAM8.Reg)&^(0xff)|value)
}
func (o *LP_I2S_Type) GetVAD_PARAM8_PARAM_THRES_UPD_BDL() uint32 {
	return volatile.LoadUint32(&o.VAD_PARAM8.Reg) & 0xff
}
func (o *LP_I2S_Type) SetVAD_PARAM8_PARAM_THRES_UPD_BDH(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM8.Reg, volatile.LoadUint32(&o.VAD_PARAM8.Reg)&^(0xff00)|value<<8)
}
func (o *LP_I2S_Type) GetVAD_PARAM8_PARAM_THRES_UPD_BDH() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM8.Reg) & 0xff00) >> 8
}
func (o *LP_I2S_Type) SetVAD_PARAM8_PARAM_FEATURE_BURST(value uint32) {
	volatile.StoreUint32(&o.VAD_PARAM8.Reg, volatile.LoadUint32(&o.VAD_PARAM8.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_PARAM8_PARAM_FEATURE_BURST() uint32 {
	return (volatile.LoadUint32(&o.VAD_PARAM8.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_OB0: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB0_SPEECH_COUNT_OB(value uint32) {
	volatile.StoreUint32(&o.VAD_OB0.Reg, volatile.LoadUint32(&o.VAD_OB0.Reg)&^(0xff)|value)
}
func (o *LP_I2S_Type) GetVAD_OB0_SPEECH_COUNT_OB() uint32 {
	return volatile.LoadUint32(&o.VAD_OB0.Reg) & 0xff
}
func (o *LP_I2S_Type) SetVAD_OB0_SILENT_COUNT_OB(value uint32) {
	volatile.StoreUint32(&o.VAD_OB0.Reg, volatile.LoadUint32(&o.VAD_OB0.Reg)&^(0xff00)|value<<8)
}
func (o *LP_I2S_Type) GetVAD_OB0_SILENT_COUNT_OB() uint32 {
	return (volatile.LoadUint32(&o.VAD_OB0.Reg) & 0xff00) >> 8
}
func (o *LP_I2S_Type) SetVAD_OB0_MAX_SIGNAL0_OB(value uint32) {
	volatile.StoreUint32(&o.VAD_OB0.Reg, volatile.LoadUint32(&o.VAD_OB0.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_OB0_MAX_SIGNAL0_OB() uint32 {
	return (volatile.LoadUint32(&o.VAD_OB0.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_OB1: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB1_MAX_SIGNAL1_OB(value uint32) {
	volatile.StoreUint32(&o.VAD_OB1.Reg, volatile.LoadUint32(&o.VAD_OB1.Reg)&^(0xffff)|value)
}
func (o *LP_I2S_Type) GetVAD_OB1_MAX_SIGNAL1_OB() uint32 {
	return volatile.LoadUint32(&o.VAD_OB1.Reg) & 0xffff
}
func (o *LP_I2S_Type) SetVAD_OB1_MAX_SIGNAL2_OB(value uint32) {
	volatile.StoreUint32(&o.VAD_OB1.Reg, volatile.LoadUint32(&o.VAD_OB1.Reg)&^(0xffff0000)|value<<16)
}
func (o *LP_I2S_Type) GetVAD_OB1_MAX_SIGNAL2_OB() uint32 {
	return (volatile.LoadUint32(&o.VAD_OB1.Reg) & 0xffff0000) >> 16
}

// LP_I2S.VAD_OB2: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB2(value uint32) {
	volatile.StoreUint32(&o.VAD_OB2.Reg, value)
}
func (o *LP_I2S_Type) GetVAD_OB2() uint32 {
	return volatile.LoadUint32(&o.VAD_OB2.Reg)
}

// LP_I2S.VAD_OB3: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB3(value uint32) {
	volatile.StoreUint32(&o.VAD_OB3.Reg, value)
}
func (o *LP_I2S_Type) GetVAD_OB3() uint32 {
	return volatile.LoadUint32(&o.VAD_OB3.Reg)
}

// LP_I2S.VAD_OB4: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB4(value uint32) {
	volatile.StoreUint32(&o.VAD_OB4.Reg, value)
}
func (o *LP_I2S_Type) GetVAD_OB4() uint32 {
	return volatile.LoadUint32(&o.VAD_OB4.Reg)
}

// LP_I2S.VAD_OB5: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB5(value uint32) {
	volatile.StoreUint32(&o.VAD_OB5.Reg, value)
}
func (o *LP_I2S_Type) GetVAD_OB5() uint32 {
	return volatile.LoadUint32(&o.VAD_OB5.Reg)
}

// LP_I2S.VAD_OB6: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB6(value uint32) {
	volatile.StoreUint32(&o.VAD_OB6.Reg, value)
}
func (o *LP_I2S_Type) GetVAD_OB6() uint32 {
	return volatile.LoadUint32(&o.VAD_OB6.Reg)
}

// LP_I2S.VAD_OB7: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB7(value uint32) {
	volatile.StoreUint32(&o.VAD_OB7.Reg, value)
}
func (o *LP_I2S_Type) GetVAD_OB7() uint32 {
	return volatile.LoadUint32(&o.VAD_OB7.Reg)
}

// LP_I2S.VAD_OB8: I2S VAD Observe register
func (o *LP_I2S_Type) SetVAD_OB8(value uint32) {
	volatile.StoreUint32(&o.VAD_OB8.Reg, value)
}
func (o *LP_I2S_Type) GetVAD_OB8() uint32 {
	return volatile.LoadUint32(&o.VAD_OB8.Reg)
}

// LP_I2S.CLK_GATE: Clock gate register
func (o *LP_I2S_Type) SetCLK_GATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x1)|value)
}
func (o *LP_I2S_Type) GetCLK_GATE_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x1
}
func (o *LP_I2S_Type) SetCLK_GATE_VAD_CG_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x2)|value<<1)
}
func (o *LP_I2S_Type) GetCLK_GATE_VAD_CG_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x2) >> 1
}
func (o *LP_I2S_Type) SetCLK_GATE_RX_MEM_CG_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x4)|value<<2)
}
func (o *LP_I2S_Type) GetCLK_GATE_RX_MEM_CG_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x4) >> 2
}
func (o *LP_I2S_Type) SetCLK_GATE_RX_REG_CG_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.CLK_GATE.Reg, volatile.LoadUint32(&o.CLK_GATE.Reg)&^(0x8)|value<<3)
}
func (o *LP_I2S_Type) GetCLK_GATE_RX_REG_CG_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.CLK_GATE.Reg) & 0x8) >> 3
}

// LP_I2S.DATE: Version control register
func (o *LP_I2S_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *LP_I2S_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// Low-power Input/Output Multiplexer
type LP_IOMUX_Type struct {
	CLK_EN          volatile.Register32 // 0x0
	VER_DATE        volatile.Register32 // 0x4
	PAD0            volatile.Register32 // 0x8
	PAD1            volatile.Register32 // 0xC
	PAD2            volatile.Register32 // 0x10
	PAD3            volatile.Register32 // 0x14
	PAD4            volatile.Register32 // 0x18
	PAD5            volatile.Register32 // 0x1C
	PAD6            volatile.Register32 // 0x20
	PAD7            volatile.Register32 // 0x24
	PAD8            volatile.Register32 // 0x28
	PAD9            volatile.Register32 // 0x2C
	PAD10           volatile.Register32 // 0x30
	PAD11           volatile.Register32 // 0x34
	PAD120          volatile.Register32 // 0x38
	PAD13           volatile.Register32 // 0x3C
	PAD14           volatile.Register32 // 0x40
	PAD15           volatile.Register32 // 0x44
	EXT_WAKEUP0_SEL volatile.Register32 // 0x48
	LP_PAD_HOLD     volatile.Register32 // 0x4C
	LP_PAD_HYS      volatile.Register32 // 0x50
}

// LP_IOMUX.CLK_EN: Reserved
func (o *LP_IOMUX_Type) SetCLK_EN_REG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value)
}
func (o *LP_IOMUX_Type) GetCLK_EN_REG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1
}

// LP_IOMUX.VER_DATE: Reserved
func (o *LP_IOMUX_Type) SetVER_DATE_REG_VER_DATE(value uint32) {
	volatile.StoreUint32(&o.VER_DATE.Reg, volatile.LoadUint32(&o.VER_DATE.Reg)&^(0xfffffff)|value)
}
func (o *LP_IOMUX_Type) GetVER_DATE_REG_VER_DATE() uint32 {
	return volatile.LoadUint32(&o.VER_DATE.Reg) & 0xfffffff
}

// LP_IOMUX.PAD0: Reserved
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD0.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD0_REG_PAD0_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD0.Reg, volatile.LoadUint32(&o.PAD0.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD0_REG_PAD0_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD0.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD1: Reserved
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD1.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD1_REG_PAD1_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD1.Reg, volatile.LoadUint32(&o.PAD1.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD1_REG_PAD1_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD1.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD2: Reserved
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD2.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD2_REG_PAD2_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD2.Reg, volatile.LoadUint32(&o.PAD2.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD2_REG_PAD2_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD2.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD3: Reserved
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD3.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD3_REG_PAD3_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD3.Reg, volatile.LoadUint32(&o.PAD3.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD3_REG_PAD3_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD3.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD4: Reserved
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD4.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD4_REG_PAD4_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD4.Reg, volatile.LoadUint32(&o.PAD4.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD4_REG_PAD4_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD4.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD5: Reserved
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD5.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD5_REG_PAD5_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD5.Reg, volatile.LoadUint32(&o.PAD5.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD5_REG_PAD5_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD5.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD6: Reserved
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD6.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD6_REG_PAD6_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD6.Reg, volatile.LoadUint32(&o.PAD6.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD6_REG_PAD6_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD6.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD7: Reserved
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD7.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD7_REG_PAD7_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD7.Reg, volatile.LoadUint32(&o.PAD7.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD7_REG_PAD7_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD7.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD8: Reserved
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD8.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD8_REG_PAD8_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD8.Reg, volatile.LoadUint32(&o.PAD8.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD8_REG_PAD8_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD8.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD9: Reserved
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD9.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD9_REG_PAD9_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD9.Reg, volatile.LoadUint32(&o.PAD9.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD9_REG_PAD9_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD9.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD10: Reserved
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD10.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD10_REG_PAD10_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD10.Reg, volatile.LoadUint32(&o.PAD10.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD10_REG_PAD10_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD10.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD11: Reserved
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD11.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD11_REG_PAD11_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD11.Reg, volatile.LoadUint32(&o.PAD11.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD11_REG_PAD11_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD11.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD120: Reserved
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD120.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD120_REG_PAD12_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD120.Reg, volatile.LoadUint32(&o.PAD120.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD120_REG_PAD12_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD120.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD13: Reserved
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD13.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD13_REG_PAD13_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD13.Reg, volatile.LoadUint32(&o.PAD13.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD13_REG_PAD13_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD13.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD14: Reserved
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD14.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD14_REG_PAD14_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD14.Reg, volatile.LoadUint32(&o.PAD14.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD14_REG_PAD14_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD14.Reg) & 0x800) >> 11
}

// LP_IOMUX.PAD15: Reserved
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_DRV(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x3)|value)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_DRV() uint32 {
	return volatile.LoadUint32(&o.PAD15.Reg) & 0x3
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_RDE(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x4)|value<<2)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_RDE() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x4) >> 2
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_RUE(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x8)|value<<3)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_RUE() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x8) >> 3
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_MUX_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x10)|value<<4)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_MUX_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x10) >> 4
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_FUN_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x60)|value<<5)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_FUN_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x60) >> 5
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x80)|value<<7)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x80) >> 7
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_SLP_IE(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x100)|value<<8)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_SLP_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x100) >> 8
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_SLP_OE(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x200)|value<<9)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_SLP_OE() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x200) >> 9
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_FUN_IE(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x400)|value<<10)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_FUN_IE() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x400) >> 10
}
func (o *LP_IOMUX_Type) SetPAD15_REG_PAD15_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.PAD15.Reg, volatile.LoadUint32(&o.PAD15.Reg)&^(0x800)|value<<11)
}
func (o *LP_IOMUX_Type) GetPAD15_REG_PAD15_FILTER_EN() uint32 {
	return (volatile.LoadUint32(&o.PAD15.Reg) & 0x800) >> 11
}

// LP_IOMUX.EXT_WAKEUP0_SEL: Reserved
func (o *LP_IOMUX_Type) SetEXT_WAKEUP0_SEL_REG_XTL_EXT_CTR_SEL(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP0_SEL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg)&^(0x1f)|value)
}
func (o *LP_IOMUX_Type) GetEXT_WAKEUP0_SEL_REG_XTL_EXT_CTR_SEL() uint32 {
	return volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg) & 0x1f
}
func (o *LP_IOMUX_Type) SetEXT_WAKEUP0_SEL_REG_EXT_WAKEUP0_SEL(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP0_SEL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg)&^(0x3e0)|value<<5)
}
func (o *LP_IOMUX_Type) GetEXT_WAKEUP0_SEL_REG_EXT_WAKEUP0_SEL() uint32 {
	return (volatile.LoadUint32(&o.EXT_WAKEUP0_SEL.Reg) & 0x3e0) >> 5
}

// LP_IOMUX.LP_PAD_HOLD: Reserved
func (o *LP_IOMUX_Type) SetLP_PAD_HOLD_REG_LP_GPIO_HOLD(value uint32) {
	volatile.StoreUint32(&o.LP_PAD_HOLD.Reg, volatile.LoadUint32(&o.LP_PAD_HOLD.Reg)&^(0xffff)|value)
}
func (o *LP_IOMUX_Type) GetLP_PAD_HOLD_REG_LP_GPIO_HOLD() uint32 {
	return volatile.LoadUint32(&o.LP_PAD_HOLD.Reg) & 0xffff
}

// LP_IOMUX.LP_PAD_HYS: Reserved
func (o *LP_IOMUX_Type) SetLP_PAD_HYS_REG_LP_GPIO_HYS(value uint32) {
	volatile.StoreUint32(&o.LP_PAD_HYS.Reg, volatile.LoadUint32(&o.LP_PAD_HYS.Reg)&^(0xffff)|value)
}
func (o *LP_IOMUX_Type) GetLP_PAD_HYS_REG_LP_GPIO_HYS() uint32 {
	return volatile.LoadUint32(&o.LP_PAD_HYS.Reg) & 0xffff
}

// Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller
type LP_UART_Type struct {
	FIFO                volatile.Register32 // 0x0
	INT_RAW             volatile.Register32 // 0x4
	INT_ST              volatile.Register32 // 0x8
	INT_ENA             volatile.Register32 // 0xC
	INT_CLR             volatile.Register32 // 0x10
	CLKDIV_SYNC         volatile.Register32 // 0x14
	RX_FILT             volatile.Register32 // 0x18
	STATUS              volatile.Register32 // 0x1C
	CONF0_SYNC          volatile.Register32 // 0x20
	CONF1               volatile.Register32 // 0x24
	_                   [4]byte
	HWFC_CONF_SYNC      volatile.Register32 // 0x2C
	SLEEP_CONF0         volatile.Register32 // 0x30
	SLEEP_CONF1         volatile.Register32 // 0x34
	SLEEP_CONF2         volatile.Register32 // 0x38
	SWFC_CONF0_SYNC     volatile.Register32 // 0x3C
	SWFC_CONF1          volatile.Register32 // 0x40
	TXBRK_CONF_SYNC     volatile.Register32 // 0x44
	IDLE_CONF_SYNC      volatile.Register32 // 0x48
	RS485_CONF_SYNC     volatile.Register32 // 0x4C
	AT_CMD_PRECNT_SYNC  volatile.Register32 // 0x50
	AT_CMD_POSTCNT_SYNC volatile.Register32 // 0x54
	AT_CMD_GAPTOUT_SYNC volatile.Register32 // 0x58
	AT_CMD_CHAR_SYNC    volatile.Register32 // 0x5C
	MEM_CONF            volatile.Register32 // 0x60
	TOUT_CONF_SYNC      volatile.Register32 // 0x64
	MEM_TX_STATUS       volatile.Register32 // 0x68
	MEM_RX_STATUS       volatile.Register32 // 0x6C
	FSM_STATUS          volatile.Register32 // 0x70
	_                   [20]byte
	CLK_CONF            volatile.Register32 // 0x88
	DATE                volatile.Register32 // 0x8C
	AFIFO_STATUS        volatile.Register32 // 0x90
	_                   [4]byte
	REG_UPDATE          volatile.Register32 // 0x98
	ID                  volatile.Register32 // 0x9C
}

// LP_UART.FIFO: FIFO data register
func (o *LP_UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) {
	volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value)
}
func (o *LP_UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 {
	return volatile.LoadUint32(&o.FIFO.Reg) & 0xff
}

// LP_UART.INT_RAW: Raw interrupt status
func (o *LP_UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *LP_UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *LP_UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *LP_UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *LP_UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *LP_UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *LP_UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *LP_UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *LP_UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *LP_UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *LP_UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *LP_UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *LP_UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *LP_UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *LP_UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *LP_UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *LP_UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *LP_UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *LP_UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *LP_UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *LP_UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *LP_UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *LP_UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *LP_UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *LP_UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *LP_UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *LP_UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *LP_UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *LP_UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *LP_UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *LP_UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}

// LP_UART.INT_ST: Masked interrupt status
func (o *LP_UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *LP_UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *LP_UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *LP_UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *LP_UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *LP_UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *LP_UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *LP_UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *LP_UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *LP_UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *LP_UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *LP_UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *LP_UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *LP_UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *LP_UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *LP_UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *LP_UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *LP_UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *LP_UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *LP_UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *LP_UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *LP_UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *LP_UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *LP_UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *LP_UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *LP_UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *LP_UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *LP_UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *LP_UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18
}
func (o *LP_UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *LP_UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19
}

// LP_UART.INT_ENA: Interrupt enable bits
func (o *LP_UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *LP_UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *LP_UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *LP_UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *LP_UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *LP_UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *LP_UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *LP_UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *LP_UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *LP_UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *LP_UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *LP_UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *LP_UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *LP_UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *LP_UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *LP_UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *LP_UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *LP_UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *LP_UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *LP_UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *LP_UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *LP_UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *LP_UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *LP_UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *LP_UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *LP_UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *LP_UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *LP_UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *LP_UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}
func (o *LP_UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *LP_UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19
}

// LP_UART.INT_CLR: Interrupt clear bits
func (o *LP_UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *LP_UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *LP_UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *LP_UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *LP_UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *LP_UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *LP_UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *LP_UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *LP_UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *LP_UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *LP_UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *LP_UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *LP_UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *LP_UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *LP_UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *LP_UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *LP_UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *LP_UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *LP_UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *LP_UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *LP_UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *LP_UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *LP_UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *LP_UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *LP_UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *LP_UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *LP_UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *LP_UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *LP_UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}
func (o *LP_UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *LP_UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19
}

// LP_UART.CLKDIV_SYNC: Clock divider configuration
func (o *LP_UART_Type) SetCLKDIV_SYNC_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xfff)|value)
}
func (o *LP_UART_Type) GetCLKDIV_SYNC_CLKDIV() uint32 {
	return volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xfff
}
func (o *LP_UART_Type) SetCLKDIV_SYNC_CLKDIV_FRAG(value uint32) {
	volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xf00000)|value<<20)
}
func (o *LP_UART_Type) GetCLKDIV_SYNC_CLKDIV_FRAG() uint32 {
	return (volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xf00000) >> 20
}

// LP_UART.RX_FILT: Rx Filter configuration
func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) {
	volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value)
}
func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT() uint32 {
	return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff
}
func (o *LP_UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) {
	volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8)
}
func (o *LP_UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8
}

// LP_UART.STATUS: UART status register
func (o *LP_UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf8)|value<<3)
}
func (o *LP_UART_Type) GetSTATUS_RXFIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf8) >> 3
}
func (o *LP_UART_Type) SetSTATUS_DSRN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13)
}
func (o *LP_UART_Type) GetSTATUS_DSRN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13
}
func (o *LP_UART_Type) SetSTATUS_CTSN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14)
}
func (o *LP_UART_Type) GetSTATUS_CTSN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14
}
func (o *LP_UART_Type) SetSTATUS_RXD(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *LP_UART_Type) GetSTATUS_RXD() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15
}
func (o *LP_UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf80000)|value<<19)
}
func (o *LP_UART_Type) GetSTATUS_TXFIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf80000) >> 19
}
func (o *LP_UART_Type) SetSTATUS_DTRN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29)
}
func (o *LP_UART_Type) GetSTATUS_DTRN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29
}
func (o *LP_UART_Type) SetSTATUS_RTSN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30)
}
func (o *LP_UART_Type) GetSTATUS_RTSN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30
}
func (o *LP_UART_Type) SetSTATUS_TXD(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31)
}
func (o *LP_UART_Type) GetSTATUS_TXD() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31
}

// LP_UART.CONF0_SYNC: Configuration register 0
func (o *LP_UART_Type) SetCONF0_SYNC_PARITY(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetCONF0_SYNC_PARITY() uint32 {
	return volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1
}
func (o *LP_UART_Type) SetCONF0_SYNC_PARITY_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetCONF0_SYNC_PARITY_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetCONF0_SYNC_BIT_NUM(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0xc)|value<<2)
}
func (o *LP_UART_Type) GetCONF0_SYNC_BIT_NUM() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0xc) >> 2
}
func (o *LP_UART_Type) SetCONF0_SYNC_STOP_BIT_NUM(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x30)|value<<4)
}
func (o *LP_UART_Type) GetCONF0_SYNC_STOP_BIT_NUM() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x30) >> 4
}
func (o *LP_UART_Type) SetCONF0_SYNC_TXD_BRK(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40)|value<<6)
}
func (o *LP_UART_Type) GetCONF0_SYNC_TXD_BRK() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40) >> 6
}
func (o *LP_UART_Type) SetCONF0_SYNC_LOOPBACK(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1000)|value<<12)
}
func (o *LP_UART_Type) GetCONF0_SYNC_LOOPBACK() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1000) >> 12
}
func (o *LP_UART_Type) SetCONF0_SYNC_TX_FLOW_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2000)|value<<13)
}
func (o *LP_UART_Type) GetCONF0_SYNC_TX_FLOW_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2000) >> 13
}
func (o *LP_UART_Type) SetCONF0_SYNC_RXD_INV(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x8000)|value<<15)
}
func (o *LP_UART_Type) GetCONF0_SYNC_RXD_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x8000) >> 15
}
func (o *LP_UART_Type) SetCONF0_SYNC_TXD_INV(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x10000)|value<<16)
}
func (o *LP_UART_Type) GetCONF0_SYNC_TXD_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x10000) >> 16
}
func (o *LP_UART_Type) SetCONF0_SYNC_DIS_RX_DAT_OVF(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x20000)|value<<17)
}
func (o *LP_UART_Type) GetCONF0_SYNC_DIS_RX_DAT_OVF() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x20000) >> 17
}
func (o *LP_UART_Type) SetCONF0_SYNC_ERR_WR_MASK(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40000)|value<<18)
}
func (o *LP_UART_Type) GetCONF0_SYNC_ERR_WR_MASK() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40000) >> 18
}
func (o *LP_UART_Type) SetCONF0_SYNC_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x100000)|value<<20)
}
func (o *LP_UART_Type) GetCONF0_SYNC_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x100000) >> 20
}
func (o *LP_UART_Type) SetCONF0_SYNC_SW_RTS(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x200000)|value<<21)
}
func (o *LP_UART_Type) GetCONF0_SYNC_SW_RTS() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x200000) >> 21
}
func (o *LP_UART_Type) SetCONF0_SYNC_RXFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x400000)|value<<22)
}
func (o *LP_UART_Type) GetCONF0_SYNC_RXFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x400000) >> 22
}
func (o *LP_UART_Type) SetCONF0_SYNC_TXFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x800000)|value<<23)
}
func (o *LP_UART_Type) GetCONF0_SYNC_TXFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x800000) >> 23
}

// LP_UART.CONF1: Configuration register 1
func (o *LP_UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf8)|value<<3)
}
func (o *LP_UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf8) >> 3
}
func (o *LP_UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xf800)|value<<11)
}
func (o *LP_UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0xf800) >> 11
}
func (o *LP_UART_Type) SetCONF1_CTS_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16)
}
func (o *LP_UART_Type) GetCONF1_CTS_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16
}
func (o *LP_UART_Type) SetCONF1_DSR_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17)
}
func (o *LP_UART_Type) GetCONF1_DSR_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17
}
func (o *LP_UART_Type) SetCONF1_RTS_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18)
}
func (o *LP_UART_Type) GetCONF1_RTS_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18
}
func (o *LP_UART_Type) SetCONF1_DTR_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19)
}
func (o *LP_UART_Type) GetCONF1_DTR_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19
}
func (o *LP_UART_Type) SetCONF1_SW_DTR(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20)
}
func (o *LP_UART_Type) GetCONF1_SW_DTR() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20
}
func (o *LP_UART_Type) SetCONF1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21)
}
func (o *LP_UART_Type) GetCONF1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21
}

// LP_UART.HWFC_CONF_SYNC: Hardware flow-control configuration
func (o *LP_UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_THRHD(value uint32) {
	volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0xf8)|value<<3)
}
func (o *LP_UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_THRHD() uint32 {
	return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0xf8) >> 3
}
func (o *LP_UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_EN(value uint32) {
	volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0x100)|value<<8)
}
func (o *LP_UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_EN() uint32 {
	return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0x100) >> 8
}

// LP_UART.SLEEP_CONF0: UART sleep configure register 0
func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value)
}
func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 {
	return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff
}
func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8)
}
func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8
}
func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16)
}
func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16
}
func (o *LP_UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24)
}
func (o *LP_UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24
}

// LP_UART.SLEEP_CONF1: UART sleep configure register 1
func (o *LP_UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value)
}
func (o *LP_UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 {
	return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff
}

// LP_UART.SLEEP_CONF2: UART sleep configure register 2
func (o *LP_UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value)
}
func (o *LP_UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 {
	return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff
}
func (o *LP_UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e000)|value<<13)
}
func (o *LP_UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e000) >> 13
}
func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18)
}
func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18
}
func (o *LP_UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21)
}
func (o *LP_UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21
}
func (o *LP_UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26)
}
func (o *LP_UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26
}

// LP_UART.SWFC_CONF0_SYNC: Software flow-control character configuration
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XON_CHAR(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff)|value)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XON_CHAR() uint32 {
	return volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XOFF_CHAR(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff00)|value<<8)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XOFF_CHAR() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff00) >> 8
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x10000)|value<<16)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x10000) >> 16
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SW_FLOW_CON_EN(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x20000)|value<<17)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SW_FLOW_CON_EN() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x20000) >> 17
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_XONOFF_DEL(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x40000)|value<<18)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_XONOFF_DEL() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x40000) >> 18
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_FORCE_XON(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x80000)|value<<19)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_FORCE_XON() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x80000) >> 19
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_FORCE_XOFF(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x100000)|value<<20)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_FORCE_XOFF() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x100000) >> 20
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SEND_XON(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x200000)|value<<21)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SEND_XON() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x200000) >> 21
}
func (o *LP_UART_Type) SetSWFC_CONF0_SYNC_SEND_XOFF(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x400000)|value<<22)
}
func (o *LP_UART_Type) GetSWFC_CONF0_SYNC_SEND_XOFF() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x400000) >> 22
}

// LP_UART.SWFC_CONF1: Software flow-control character configuration
func (o *LP_UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf8)|value<<3)
}
func (o *LP_UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf8) >> 3
}
func (o *LP_UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xf800)|value<<11)
}
func (o *LP_UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xf800) >> 11
}

// LP_UART.TXBRK_CONF_SYNC: Tx Break character configuration
func (o *LP_UART_Type) SetTXBRK_CONF_SYNC_TX_BRK_NUM(value uint32) {
	volatile.StoreUint32(&o.TXBRK_CONF_SYNC.Reg, volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg)&^(0xff)|value)
}
func (o *LP_UART_Type) GetTXBRK_CONF_SYNC_TX_BRK_NUM() uint32 {
	return volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg) & 0xff
}

// LP_UART.IDLE_CONF_SYNC: Frame-end idle configuration
func (o *LP_UART_Type) SetIDLE_CONF_SYNC_RX_IDLE_THRHD(value uint32) {
	volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0x3ff)|value)
}
func (o *LP_UART_Type) GetIDLE_CONF_SYNC_RX_IDLE_THRHD() uint32 {
	return volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0x3ff
}
func (o *LP_UART_Type) SetIDLE_CONF_SYNC_TX_IDLE_NUM(value uint32) {
	volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0xffc00)|value<<10)
}
func (o *LP_UART_Type) GetIDLE_CONF_SYNC_TX_IDLE_NUM() uint32 {
	return (volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0xffc00) >> 10
}

// LP_UART.RS485_CONF_SYNC: RS485 mode configuration
func (o *LP_UART_Type) SetRS485_CONF_SYNC_DL0_EN(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetRS485_CONF_SYNC_DL0_EN() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetRS485_CONF_SYNC_DL1_EN(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x4)|value<<2)
}
func (o *LP_UART_Type) GetRS485_CONF_SYNC_DL1_EN() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x4) >> 2
}

// LP_UART.AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration
func (o *LP_UART_Type) SetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_PRECNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg)&^(0xffff)|value)
}
func (o *LP_UART_Type) GetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg) & 0xffff
}

// LP_UART.AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration
func (o *LP_UART_Type) SetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_POSTCNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg)&^(0xffff)|value)
}
func (o *LP_UART_Type) GetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg) & 0xffff
}

// LP_UART.AT_CMD_GAPTOUT_SYNC: Timeout configuration
func (o *LP_UART_Type) SetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg)&^(0xffff)|value)
}
func (o *LP_UART_Type) GetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg) & 0xffff
}

// LP_UART.AT_CMD_CHAR_SYNC: AT escape sequence detection configuration
func (o *LP_UART_Type) SetAT_CMD_CHAR_SYNC_AT_CMD_CHAR(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff)|value)
}
func (o *LP_UART_Type) GetAT_CMD_CHAR_SYNC_AT_CMD_CHAR() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff
}
func (o *LP_UART_Type) SetAT_CMD_CHAR_SYNC_CHAR_NUM(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff00)|value<<8)
}
func (o *LP_UART_Type) GetAT_CMD_CHAR_SYNC_CHAR_NUM() uint32 {
	return (volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff00) >> 8
}

// LP_UART.MEM_CONF: UART memory power configuration
func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25
}
func (o *LP_UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *LP_UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26
}

// LP_UART.TOUT_CONF_SYNC: UART threshold and allocation configuration
func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_EN(value uint32) {
	volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_EN() uint32 {
	return volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x1
}
func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS(value uint32) {
	volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS() uint32 {
	return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_THRHD(value uint32) {
	volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0xffc)|value<<2)
}
func (o *LP_UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_THRHD() uint32 {
	return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0xffc) >> 2
}

// LP_UART.MEM_TX_STATUS: Tx-SRAM write and read offset address.
func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xf8)|value<<3)
}
func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 {
	return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xf8) >> 3
}
func (o *LP_UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1f000)|value<<12)
}
func (o *LP_UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 {
	return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1f000) >> 12
}

// LP_UART.MEM_RX_STATUS: Rx-SRAM write and read offset address.
func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xf8)|value<<3)
}
func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 {
	return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xf8) >> 3
}
func (o *LP_UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1f000)|value<<12)
}
func (o *LP_UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 {
	return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1f000) >> 12
}

// LP_UART.FSM_STATUS: UART transmit and receive status.
func (o *LP_UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) {
	volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value)
}
func (o *LP_UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 {
	return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf
}
func (o *LP_UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) {
	volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4)
}
func (o *LP_UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 {
	return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4
}

// LP_UART.CLK_CONF: UART core clock configuration
func (o *LP_UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *LP_UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24
}
func (o *LP_UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *LP_UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25
}
func (o *LP_UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *LP_UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26
}
func (o *LP_UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27)
}
func (o *LP_UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27
}

// LP_UART.DATE: UART Version register
func (o *LP_UART_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *LP_UART_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// LP_UART.AFIFO_STATUS: UART AFIFO Status
func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 {
	return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1
}
func (o *LP_UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *LP_UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1
}
func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2
}
func (o *LP_UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *LP_UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3
}

// LP_UART.REG_UPDATE: UART Registers Configuration Update register
func (o *LP_UART_Type) SetREG_UPDATE(value uint32) {
	volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value)
}
func (o *LP_UART_Type) GetREG_UPDATE() uint32 {
	return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1
}

// LP_UART.ID: UART ID register
func (o *LP_UART_Type) SetID(value uint32) {
	volatile.StoreUint32(&o.ID.Reg, value)
}
func (o *LP_UART_Type) GetID() uint32 {
	return volatile.LoadUint32(&o.ID.Reg)
}

// Motor Control Pulse-Width Modulation 0
type MCPWM_Type struct {
	CLK_CFG           volatile.Register32 // 0x0
	TIMER0_CFG0       volatile.Register32 // 0x4
	TIMER0_CFG1       volatile.Register32 // 0x8
	TIMER0_SYNC       volatile.Register32 // 0xC
	TIMER0_STATUS     volatile.Register32 // 0x10
	TIMER1_CFG0       volatile.Register32 // 0x14
	TIMER1_CFG1       volatile.Register32 // 0x18
	TIMER1_SYNC       volatile.Register32 // 0x1C
	TIMER1_STATUS     volatile.Register32 // 0x20
	TIMER2_CFG0       volatile.Register32 // 0x24
	TIMER2_CFG1       volatile.Register32 // 0x28
	TIMER2_SYNC       volatile.Register32 // 0x2C
	TIMER2_STATUS     volatile.Register32 // 0x30
	TIMER_SYNCI_CFG   volatile.Register32 // 0x34
	OPERATOR_TIMERSEL volatile.Register32 // 0x38
	GEN0_STMP_CFG     volatile.Register32 // 0x3C
	GEN0_TSTMP_A      volatile.Register32 // 0x40
	GEN0_TSTMP_B      volatile.Register32 // 0x44
	GEN0_CFG0         volatile.Register32 // 0x48
	GEN0_FORCE        volatile.Register32 // 0x4C
	GEN0_A            volatile.Register32 // 0x50
	GEN0_B            volatile.Register32 // 0x54
	DT0_CFG           volatile.Register32 // 0x58
	DT0_FED_CFG       volatile.Register32 // 0x5C
	DT0_RED_CFG       volatile.Register32 // 0x60
	CARRIER0_CFG      volatile.Register32 // 0x64
	FH0_CFG0          volatile.Register32 // 0x68
	FH0_CFG1          volatile.Register32 // 0x6C
	FH0_STATUS        volatile.Register32 // 0x70
	GEN1_STMP_CFG     volatile.Register32 // 0x74
	GEN1_TSTMP_A      volatile.Register32 // 0x78
	GEN1_TSTMP_B      volatile.Register32 // 0x7C
	GEN1_CFG0         volatile.Register32 // 0x80
	GEN1_FORCE        volatile.Register32 // 0x84
	GEN1_A            volatile.Register32 // 0x88
	GEN1_B            volatile.Register32 // 0x8C
	DT1_CFG           volatile.Register32 // 0x90
	DT1_FED_CFG       volatile.Register32 // 0x94
	DT1_RED_CFG       volatile.Register32 // 0x98
	CARRIER1_CFG      volatile.Register32 // 0x9C
	FH1_CFG0          volatile.Register32 // 0xA0
	FH1_CFG1          volatile.Register32 // 0xA4
	FH1_STATUS        volatile.Register32 // 0xA8
	GEN2_STMP_CFG     volatile.Register32 // 0xAC
	GEN2_TSTMP_A      volatile.Register32 // 0xB0
	GEN2_TSTMP_B      volatile.Register32 // 0xB4
	GEN2_CFG0         volatile.Register32 // 0xB8
	GEN2_FORCE        volatile.Register32 // 0xBC
	GEN2_A            volatile.Register32 // 0xC0
	GEN2_B            volatile.Register32 // 0xC4
	DT2_CFG           volatile.Register32 // 0xC8
	DT2_FED_CFG       volatile.Register32 // 0xCC
	DT2_RED_CFG       volatile.Register32 // 0xD0
	CARRIER2_CFG      volatile.Register32 // 0xD4
	FH2_CFG0          volatile.Register32 // 0xD8
	FH2_CFG1          volatile.Register32 // 0xDC
	FH2_STATUS        volatile.Register32 // 0xE0
	FAULT_DETECT      volatile.Register32 // 0xE4
	CAP_TIMER_CFG     volatile.Register32 // 0xE8
	CAP_TIMER_PHASE   volatile.Register32 // 0xEC
	CAP_CH0_CFG       volatile.Register32 // 0xF0
	CAP_CH1_CFG       volatile.Register32 // 0xF4
	CAP_CH2_CFG       volatile.Register32 // 0xF8
	CAP_CH0           volatile.Register32 // 0xFC
	CAP_CH1           volatile.Register32 // 0x100
	CAP_CH2           volatile.Register32 // 0x104
	CAP_STATUS        volatile.Register32 // 0x108
	UPDATE_CFG        volatile.Register32 // 0x10C
	INT_ENA           volatile.Register32 // 0x110
	INT_RAW           volatile.Register32 // 0x114
	INT_ST            volatile.Register32 // 0x118
	INT_CLR           volatile.Register32 // 0x11C
	EVT_EN            volatile.Register32 // 0x120
	TASK_EN           volatile.Register32 // 0x124
	EVT_EN2           volatile.Register32 // 0x128
	OP0_TSTMP_E1      volatile.Register32 // 0x12C
	OP0_TSTMP_E2      volatile.Register32 // 0x130
	OP1_TSTMP_E1      volatile.Register32 // 0x134
	OP1_TSTMP_E2      volatile.Register32 // 0x138
	OP2_TSTMP_E1      volatile.Register32 // 0x13C
	OP2_TSTMP_E2      volatile.Register32 // 0x140
	CLK               volatile.Register32 // 0x144
	VERSION           volatile.Register32 // 0x148
}

// MCPWM.CLK_CFG: PWM clock prescaler register.
func (o *MCPWM_Type) SetCLK_CFG_CLK_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value)
}
func (o *MCPWM_Type) GetCLK_CFG_CLK_PRESCALE() uint32 {
	return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff
}

// MCPWM.TIMER0_CFG0: PWM timer%s period and update method configuration register.
func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xff)|value)
}
func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER_PRESCALE() uint32 {
	return volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xff
}
func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER_PERIOD(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0xffff00)|value<<8)
}
func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0xffff00) >> 8
}
func (o *MCPWM_Type) SetTIMER0_CFG0_TIMER_PERIOD_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CFG0.Reg, volatile.LoadUint32(&o.TIMER0_CFG0.Reg)&^(0x3000000)|value<<24)
}
func (o *MCPWM_Type) GetTIMER0_CFG0_TIMER_PERIOD_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CFG0.Reg) & 0x3000000) >> 24
}

// MCPWM.TIMER0_CFG1: PWM timer%s working mode and start/stop control register.
func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER_START(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x7)|value)
}
func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER_START() uint32 {
	return volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x7
}
func (o *MCPWM_Type) SetTIMER0_CFG1_TIMER_MOD(value uint32) {
	volatile.StoreUint32(&o.TIMER0_CFG1.Reg, volatile.LoadUint32(&o.TIMER0_CFG1.Reg)&^(0x18)|value<<3)
}
func (o *MCPWM_Type) GetTIMER0_CFG1_TIMER_MOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_CFG1.Reg) & 0x18) >> 3
}

// MCPWM.TIMER0_SYNC: PWM timer%s sync function configuration register.
func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_SYNCI_EN(value uint32) {
	volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_SYNCI_EN() uint32 {
	return volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x1
}
func (o *MCPWM_Type) SetTIMER0_SYNC_SW(value uint32) {
	volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetTIMER0_SYNC_SW() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_SYNCO_SEL(value uint32) {
	volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_SYNCO_SEL() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_PHASE(value uint32) {
	volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0xffff0)|value<<4)
}
func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_PHASE() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0xffff0) >> 4
}
func (o *MCPWM_Type) SetTIMER0_SYNC_TIMER_PHASE_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.TIMER0_SYNC.Reg, volatile.LoadUint32(&o.TIMER0_SYNC.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetTIMER0_SYNC_TIMER_PHASE_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_SYNC.Reg) & 0x100000) >> 20
}

// MCPWM.TIMER0_STATUS: PWM timer%s status register.
func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER_VALUE(value uint32) {
	volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER_VALUE() uint32 {
	return volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0xffff
}
func (o *MCPWM_Type) SetTIMER0_STATUS_TIMER_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.TIMER0_STATUS.Reg, volatile.LoadUint32(&o.TIMER0_STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetTIMER0_STATUS_TIMER_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.TIMER0_STATUS.Reg) & 0x10000) >> 16
}

// MCPWM.TIMER1_CFG0: PWM timer%s period and update method configuration register.
func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xff)|value)
}
func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER_PRESCALE() uint32 {
	return volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xff
}
func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER_PERIOD(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0xffff00)|value<<8)
}
func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0xffff00) >> 8
}
func (o *MCPWM_Type) SetTIMER1_CFG0_TIMER_PERIOD_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CFG0.Reg, volatile.LoadUint32(&o.TIMER1_CFG0.Reg)&^(0x3000000)|value<<24)
}
func (o *MCPWM_Type) GetTIMER1_CFG0_TIMER_PERIOD_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CFG0.Reg) & 0x3000000) >> 24
}

// MCPWM.TIMER1_CFG1: PWM timer%s working mode and start/stop control register.
func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER_START(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x7)|value)
}
func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER_START() uint32 {
	return volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x7
}
func (o *MCPWM_Type) SetTIMER1_CFG1_TIMER_MOD(value uint32) {
	volatile.StoreUint32(&o.TIMER1_CFG1.Reg, volatile.LoadUint32(&o.TIMER1_CFG1.Reg)&^(0x18)|value<<3)
}
func (o *MCPWM_Type) GetTIMER1_CFG1_TIMER_MOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_CFG1.Reg) & 0x18) >> 3
}

// MCPWM.TIMER1_SYNC: PWM timer%s sync function configuration register.
func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_SYNCI_EN(value uint32) {
	volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_SYNCI_EN() uint32 {
	return volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x1
}
func (o *MCPWM_Type) SetTIMER1_SYNC_SW(value uint32) {
	volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetTIMER1_SYNC_SW() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_SYNCO_SEL(value uint32) {
	volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_SYNCO_SEL() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_PHASE(value uint32) {
	volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0xffff0)|value<<4)
}
func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_PHASE() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0xffff0) >> 4
}
func (o *MCPWM_Type) SetTIMER1_SYNC_TIMER_PHASE_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.TIMER1_SYNC.Reg, volatile.LoadUint32(&o.TIMER1_SYNC.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetTIMER1_SYNC_TIMER_PHASE_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_SYNC.Reg) & 0x100000) >> 20
}

// MCPWM.TIMER1_STATUS: PWM timer%s status register.
func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER_VALUE(value uint32) {
	volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER_VALUE() uint32 {
	return volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0xffff
}
func (o *MCPWM_Type) SetTIMER1_STATUS_TIMER_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.TIMER1_STATUS.Reg, volatile.LoadUint32(&o.TIMER1_STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetTIMER1_STATUS_TIMER_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.TIMER1_STATUS.Reg) & 0x10000) >> 16
}

// MCPWM.TIMER2_CFG0: PWM timer%s period and update method configuration register.
func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xff)|value)
}
func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER_PRESCALE() uint32 {
	return volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xff
}
func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER_PERIOD(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0xffff00)|value<<8)
}
func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER_PERIOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0xffff00) >> 8
}
func (o *MCPWM_Type) SetTIMER2_CFG0_TIMER_PERIOD_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CFG0.Reg, volatile.LoadUint32(&o.TIMER2_CFG0.Reg)&^(0x3000000)|value<<24)
}
func (o *MCPWM_Type) GetTIMER2_CFG0_TIMER_PERIOD_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CFG0.Reg) & 0x3000000) >> 24
}

// MCPWM.TIMER2_CFG1: PWM timer%s working mode and start/stop control register.
func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER_START(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x7)|value)
}
func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER_START() uint32 {
	return volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x7
}
func (o *MCPWM_Type) SetTIMER2_CFG1_TIMER_MOD(value uint32) {
	volatile.StoreUint32(&o.TIMER2_CFG1.Reg, volatile.LoadUint32(&o.TIMER2_CFG1.Reg)&^(0x18)|value<<3)
}
func (o *MCPWM_Type) GetTIMER2_CFG1_TIMER_MOD() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_CFG1.Reg) & 0x18) >> 3
}

// MCPWM.TIMER2_SYNC: PWM timer%s sync function configuration register.
func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_SYNCI_EN(value uint32) {
	volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_SYNCI_EN() uint32 {
	return volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x1
}
func (o *MCPWM_Type) SetTIMER2_SYNC_SW(value uint32) {
	volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetTIMER2_SYNC_SW() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_SYNCO_SEL(value uint32) {
	volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_SYNCO_SEL() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_PHASE(value uint32) {
	volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0xffff0)|value<<4)
}
func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_PHASE() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0xffff0) >> 4
}
func (o *MCPWM_Type) SetTIMER2_SYNC_TIMER_PHASE_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.TIMER2_SYNC.Reg, volatile.LoadUint32(&o.TIMER2_SYNC.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetTIMER2_SYNC_TIMER_PHASE_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_SYNC.Reg) & 0x100000) >> 20
}

// MCPWM.TIMER2_STATUS: PWM timer%s status register.
func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER_VALUE(value uint32) {
	volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER_VALUE() uint32 {
	return volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0xffff
}
func (o *MCPWM_Type) SetTIMER2_STATUS_TIMER_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.TIMER2_STATUS.Reg, volatile.LoadUint32(&o.TIMER2_STATUS.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetTIMER2_STATUS_TIMER_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.TIMER2_STATUS.Reg) & 0x10000) >> 16
}

// MCPWM.TIMER_SYNCI_CFG: Synchronization input selection register for PWM timers.
func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER0_SYNCISEL(value uint32) {
	volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x7)|value)
}
func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER0_SYNCISEL() uint32 {
	return volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x7
}
func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER1_SYNCISEL(value uint32) {
	volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x38)|value<<3)
}
func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER1_SYNCISEL() uint32 {
	return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x38) >> 3
}
func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_TIMER2_SYNCISEL(value uint32) {
	volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x1c0)|value<<6)
}
func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_TIMER2_SYNCISEL() uint32 {
	return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x1c0) >> 6
}
func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT(value uint32) {
	volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT() uint32 {
	return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT(value uint32) {
	volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT() uint32 {
	return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT(value uint32) {
	volatile.StoreUint32(&o.TIMER_SYNCI_CFG.Reg, volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetTIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT() uint32 {
	return (volatile.LoadUint32(&o.TIMER_SYNCI_CFG.Reg) & 0x800) >> 11
}

// MCPWM.OPERATOR_TIMERSEL: PWM operator's timer select register
func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL(value uint32) {
	volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x3)|value)
}
func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR0_TIMERSEL() uint32 {
	return volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x3
}
func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL(value uint32) {
	volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR1_TIMERSEL() uint32 {
	return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL(value uint32) {
	volatile.StoreUint32(&o.OPERATOR_TIMERSEL.Reg, volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg)&^(0x30)|value<<4)
}
func (o *MCPWM_Type) GetOPERATOR_TIMERSEL_OPERATOR2_TIMERSEL() uint32 {
	return (volatile.LoadUint32(&o.OPERATOR_TIMERSEL.Reg) & 0x30) >> 4
}

// MCPWM.GEN0_STMP_CFG: Generator%s time stamp registers A and B transfer status and update method register
func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_A_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_A_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf
}
func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_B_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_B_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0xf0) >> 4
}
func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_A_SHDW_FULL(value uint32) {
	volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_A_SHDW_FULL() uint32 {
	return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetGEN0_STMP_CFG_CMPR_B_SHDW_FULL(value uint32) {
	volatile.StoreUint32(&o.GEN0_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetGEN0_STMP_CFG_CMPR_B_SHDW_FULL() uint32 {
	return (volatile.LoadUint32(&o.GEN0_STMP_CFG.Reg) & 0x200) >> 9
}

// MCPWM.GEN0_TSTMP_A: Generator%s time stamp A's shadow register
func (o *MCPWM_Type) SetGEN0_TSTMP_A_CMPR_A(value uint32) {
	volatile.StoreUint32(&o.GEN0_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetGEN0_TSTMP_A_CMPR_A() uint32 {
	return volatile.LoadUint32(&o.GEN0_TSTMP_A.Reg) & 0xffff
}

// MCPWM.GEN0_TSTMP_B: Generator%s time stamp B's shadow register
func (o *MCPWM_Type) SetGEN0_TSTMP_B_CMPR_B(value uint32) {
	volatile.StoreUint32(&o.GEN0_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetGEN0_TSTMP_B_CMPR_B() uint32 {
	return volatile.LoadUint32(&o.GEN0_TSTMP_B.Reg) & 0xffff
}

// MCPWM.GEN0_CFG0: Generator%s fault event T0 and T1 configuration register
func (o *MCPWM_Type) SetGEN0_CFG0_GEN_CFG_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetGEN0_CFG0_GEN_CFG_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0xf
}
func (o *MCPWM_Type) SetGEN0_CFG0_GEN_T0_SEL(value uint32) {
	volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x70)|value<<4)
}
func (o *MCPWM_Type) GetGEN0_CFG0_GEN_T0_SEL() uint32 {
	return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x70) >> 4
}
func (o *MCPWM_Type) SetGEN0_CFG0_GEN_T1_SEL(value uint32) {
	volatile.StoreUint32(&o.GEN0_CFG0.Reg, volatile.LoadUint32(&o.GEN0_CFG0.Reg)&^(0x380)|value<<7)
}
func (o *MCPWM_Type) GetGEN0_CFG0_GEN_T1_SEL() uint32 {
	return (volatile.LoadUint32(&o.GEN0_CFG0.Reg) & 0x380) >> 7
}

// MCPWM.GEN0_FORCE: Generator%s output signal force mode register.
func (o *MCPWM_Type) SetGEN0_FORCE_GEN_CNTUFORCE_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x3f)|value)
}
func (o *MCPWM_Type) GetGEN0_FORCE_GEN_CNTUFORCE_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x3f
}
func (o *MCPWM_Type) SetGEN0_FORCE_GEN_A_CNTUFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN0_FORCE_GEN_A_CNTUFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN0_FORCE_GEN_B_CNTUFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN0_FORCE_GEN_B_CNTUFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN0_FORCE_GEN_A_NCIFORCE(value uint32) {
	volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetGEN0_FORCE_GEN_A_NCIFORCE() uint32 {
	return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetGEN0_FORCE_GEN_A_NCIFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x1800)|value<<11)
}
func (o *MCPWM_Type) GetGEN0_FORCE_GEN_A_NCIFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x1800) >> 11
}
func (o *MCPWM_Type) SetGEN0_FORCE_GEN_B_NCIFORCE(value uint32) {
	volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetGEN0_FORCE_GEN_B_NCIFORCE() uint32 {
	return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetGEN0_FORCE_GEN_B_NCIFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN0_FORCE.Reg, volatile.LoadUint32(&o.GEN0_FORCE.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN0_FORCE_GEN_B_NCIFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN0_FORCE.Reg) & 0xc000) >> 14
}

// MCPWM.GEN0_A: PWM%s output signal A actions configuration register
func (o *MCPWM_Type) SetGEN0_A_UTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3)|value)
}
func (o *MCPWM_Type) GetGEN0_A_UTEZ() uint32 {
	return volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3
}
func (o *MCPWM_Type) SetGEN0_A_UTEP(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetGEN0_A_UTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetGEN0_A_UTEA(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30)|value<<4)
}
func (o *MCPWM_Type) GetGEN0_A_UTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30) >> 4
}
func (o *MCPWM_Type) SetGEN0_A_UTEB(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN0_A_UTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN0_A_UT0(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN0_A_UT0() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN0_A_UT1(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetGEN0_A_UT1() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetGEN0_A_DTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetGEN0_A_DTEZ() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetGEN0_A_DTEP(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN0_A_DTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetGEN0_A_DTEA(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetGEN0_A_DTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetGEN0_A_DTEB(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetGEN0_A_DTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetGEN0_A_DT0(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetGEN0_A_DT0() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetGEN0_A_DT1(value uint32) {
	volatile.StoreUint32(&o.GEN0_A.Reg, volatile.LoadUint32(&o.GEN0_A.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetGEN0_A_DT1() uint32 {
	return (volatile.LoadUint32(&o.GEN0_A.Reg) & 0xc00000) >> 22
}

// MCPWM.GEN0_B: PWM%s output signal B actions configuration register
func (o *MCPWM_Type) SetGEN0_B_UTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3)|value)
}
func (o *MCPWM_Type) GetGEN0_B_UTEZ() uint32 {
	return volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3
}
func (o *MCPWM_Type) SetGEN0_B_UTEP(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetGEN0_B_UTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetGEN0_B_UTEA(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30)|value<<4)
}
func (o *MCPWM_Type) GetGEN0_B_UTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30) >> 4
}
func (o *MCPWM_Type) SetGEN0_B_UTEB(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN0_B_UTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN0_B_UT0(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN0_B_UT0() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN0_B_UT1(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetGEN0_B_UT1() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetGEN0_B_DTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetGEN0_B_DTEZ() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetGEN0_B_DTEP(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN0_B_DTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetGEN0_B_DTEA(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetGEN0_B_DTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetGEN0_B_DTEB(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetGEN0_B_DTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetGEN0_B_DT0(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetGEN0_B_DT0() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetGEN0_B_DT1(value uint32) {
	volatile.StoreUint32(&o.GEN0_B.Reg, volatile.LoadUint32(&o.GEN0_B.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetGEN0_B_DT1() uint32 {
	return (volatile.LoadUint32(&o.GEN0_B.Reg) & 0xc00000) >> 22
}

// MCPWM.DT0_CFG: Dead time configuration register
func (o *MCPWM_Type) SetDT0_CFG_DB_FED_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_FED_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf
}
func (o *MCPWM_Type) SetDT0_CFG_DB_RED_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_RED_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0xf0) >> 4
}
func (o *MCPWM_Type) SetDT0_CFG_DB_DEB_MODE(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_DEB_MODE() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetDT0_CFG_DB_A_OUTSWAP(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_A_OUTSWAP() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetDT0_CFG_DB_B_OUTSWAP(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_B_OUTSWAP() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetDT0_CFG_DB_RED_INSEL(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_RED_INSEL() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetDT0_CFG_DB_FED_INSEL(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_FED_INSEL() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetDT0_CFG_DB_RED_OUTINVERT(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_RED_OUTINVERT() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetDT0_CFG_DB_FED_OUTINVERT(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_FED_OUTINVERT() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetDT0_CFG_DB_A_OUTBYPASS(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_A_OUTBYPASS() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetDT0_CFG_DB_B_OUTBYPASS(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_B_OUTBYPASS() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetDT0_CFG_DB_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.DT0_CFG.Reg, volatile.LoadUint32(&o.DT0_CFG.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetDT0_CFG_DB_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.DT0_CFG.Reg) & 0x20000) >> 17
}

// MCPWM.DT0_FED_CFG: Falling edge delay (FED) shadow register
func (o *MCPWM_Type) SetDT0_FED_CFG_DB_FED(value uint32) {
	volatile.StoreUint32(&o.DT0_FED_CFG.Reg, volatile.LoadUint32(&o.DT0_FED_CFG.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetDT0_FED_CFG_DB_FED() uint32 {
	return volatile.LoadUint32(&o.DT0_FED_CFG.Reg) & 0xffff
}

// MCPWM.DT0_RED_CFG: Rising edge delay (RED) shadow register
func (o *MCPWM_Type) SetDT0_RED_CFG_DB_RED(value uint32) {
	volatile.StoreUint32(&o.DT0_RED_CFG.Reg, volatile.LoadUint32(&o.DT0_RED_CFG.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetDT0_RED_CFG_DB_RED() uint32 {
	return volatile.LoadUint32(&o.DT0_RED_CFG.Reg) & 0xffff
}

// MCPWM.CARRIER0_CFG: Carrier%s configuration register
func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_EN(value uint32) {
	volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_EN() uint32 {
	return volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1e)|value<<1)
}
func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1e) >> 1
}
func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_DUTY(value uint32) {
	volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xe0)|value<<5)
}
func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_DUTY() uint32 {
	return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xe0) >> 5
}
func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_OSHTWTH(value uint32) {
	volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0xf00)|value<<8)
}
func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_OSHTWTH() uint32 {
	return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0xf00) >> 8
}
func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_OUT_INVERT(value uint32) {
	volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_OUT_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetCARRIER0_CFG_CHOPPER_IN_INVERT(value uint32) {
	volatile.StoreUint32(&o.CARRIER0_CFG.Reg, volatile.LoadUint32(&o.CARRIER0_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetCARRIER0_CFG_CHOPPER_IN_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CARRIER0_CFG.Reg) & 0x2000) >> 13
}

// MCPWM.FH0_CFG0: PWM%s A and PWM%s B trip events actions configuration register
func (o *MCPWM_Type) SetFH0_CFG0_TZ_SW_CBC(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_SW_CBC() uint32 {
	return volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_F2_CBC(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_F2_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_F1_CBC(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_F1_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_F0_CBC(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_F0_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_SW_OST(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_SW_OST() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_F2_OST(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_F2_OST() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_F1_OST(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_F1_OST() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_F0_OST(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_F0_OST() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_CBC_D(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_CBC_D() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_CBC_U(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_CBC_U() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_OST_D(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_OST_D() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_A_OST_U(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_A_OST_U() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_CBC_D(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_CBC_D() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_CBC_U(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_CBC_U() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_OST_D(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_OST_D() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetFH0_CFG0_TZ_B_OST_U(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG0.Reg, volatile.LoadUint32(&o.FH0_CFG0.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetFH0_CFG0_TZ_B_OST_U() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG0.Reg) & 0xc00000) >> 22
}

// MCPWM.FH0_CFG1: Software triggers for fault handler actions configuration register
func (o *MCPWM_Type) SetFH0_CFG1_TZ_CLR_OST(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH0_CFG1_TZ_CLR_OST() uint32 {
	return volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH0_CFG1_TZ_CBCPULSE(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x6)|value<<1)
}
func (o *MCPWM_Type) GetFH0_CFG1_TZ_CBCPULSE() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x6) >> 1
}
func (o *MCPWM_Type) SetFH0_CFG1_TZ_FORCE_CBC(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetFH0_CFG1_TZ_FORCE_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetFH0_CFG1_TZ_FORCE_OST(value uint32) {
	volatile.StoreUint32(&o.FH0_CFG1.Reg, volatile.LoadUint32(&o.FH0_CFG1.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetFH0_CFG1_TZ_FORCE_OST() uint32 {
	return (volatile.LoadUint32(&o.FH0_CFG1.Reg) & 0x10) >> 4
}

// MCPWM.FH0_STATUS: Fault events status register
func (o *MCPWM_Type) SetFH0_STATUS_TZ_CBC_ON(value uint32) {
	volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH0_STATUS_TZ_CBC_ON() uint32 {
	return volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH0_STATUS_TZ_OST_ON(value uint32) {
	volatile.StoreUint32(&o.FH0_STATUS.Reg, volatile.LoadUint32(&o.FH0_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetFH0_STATUS_TZ_OST_ON() uint32 {
	return (volatile.LoadUint32(&o.FH0_STATUS.Reg) & 0x2) >> 1
}

// MCPWM.GEN1_STMP_CFG: Generator%s time stamp registers A and B transfer status and update method register
func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_A_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_A_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf
}
func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_B_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_B_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0xf0) >> 4
}
func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_A_SHDW_FULL(value uint32) {
	volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_A_SHDW_FULL() uint32 {
	return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetGEN1_STMP_CFG_CMPR_B_SHDW_FULL(value uint32) {
	volatile.StoreUint32(&o.GEN1_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetGEN1_STMP_CFG_CMPR_B_SHDW_FULL() uint32 {
	return (volatile.LoadUint32(&o.GEN1_STMP_CFG.Reg) & 0x200) >> 9
}

// MCPWM.GEN1_TSTMP_A: Generator%s time stamp A's shadow register
func (o *MCPWM_Type) SetGEN1_TSTMP_A_CMPR_A(value uint32) {
	volatile.StoreUint32(&o.GEN1_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetGEN1_TSTMP_A_CMPR_A() uint32 {
	return volatile.LoadUint32(&o.GEN1_TSTMP_A.Reg) & 0xffff
}

// MCPWM.GEN1_TSTMP_B: Generator%s time stamp B's shadow register
func (o *MCPWM_Type) SetGEN1_TSTMP_B_CMPR_B(value uint32) {
	volatile.StoreUint32(&o.GEN1_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetGEN1_TSTMP_B_CMPR_B() uint32 {
	return volatile.LoadUint32(&o.GEN1_TSTMP_B.Reg) & 0xffff
}

// MCPWM.GEN1_CFG0: Generator%s fault event T0 and T1 configuration register
func (o *MCPWM_Type) SetGEN1_CFG0_GEN_CFG_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetGEN1_CFG0_GEN_CFG_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0xf
}
func (o *MCPWM_Type) SetGEN1_CFG0_GEN_T0_SEL(value uint32) {
	volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x70)|value<<4)
}
func (o *MCPWM_Type) GetGEN1_CFG0_GEN_T0_SEL() uint32 {
	return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x70) >> 4
}
func (o *MCPWM_Type) SetGEN1_CFG0_GEN_T1_SEL(value uint32) {
	volatile.StoreUint32(&o.GEN1_CFG0.Reg, volatile.LoadUint32(&o.GEN1_CFG0.Reg)&^(0x380)|value<<7)
}
func (o *MCPWM_Type) GetGEN1_CFG0_GEN_T1_SEL() uint32 {
	return (volatile.LoadUint32(&o.GEN1_CFG0.Reg) & 0x380) >> 7
}

// MCPWM.GEN1_FORCE: Generator%s output signal force mode register.
func (o *MCPWM_Type) SetGEN1_FORCE_GEN_CNTUFORCE_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x3f)|value)
}
func (o *MCPWM_Type) GetGEN1_FORCE_GEN_CNTUFORCE_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x3f
}
func (o *MCPWM_Type) SetGEN1_FORCE_GEN_A_CNTUFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN1_FORCE_GEN_A_CNTUFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN1_FORCE_GEN_B_CNTUFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN1_FORCE_GEN_B_CNTUFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN1_FORCE_GEN_A_NCIFORCE(value uint32) {
	volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetGEN1_FORCE_GEN_A_NCIFORCE() uint32 {
	return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetGEN1_FORCE_GEN_A_NCIFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x1800)|value<<11)
}
func (o *MCPWM_Type) GetGEN1_FORCE_GEN_A_NCIFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x1800) >> 11
}
func (o *MCPWM_Type) SetGEN1_FORCE_GEN_B_NCIFORCE(value uint32) {
	volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetGEN1_FORCE_GEN_B_NCIFORCE() uint32 {
	return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetGEN1_FORCE_GEN_B_NCIFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN1_FORCE.Reg, volatile.LoadUint32(&o.GEN1_FORCE.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN1_FORCE_GEN_B_NCIFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN1_FORCE.Reg) & 0xc000) >> 14
}

// MCPWM.GEN1_A: PWM%s output signal A actions configuration register
func (o *MCPWM_Type) SetGEN1_A_UTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3)|value)
}
func (o *MCPWM_Type) GetGEN1_A_UTEZ() uint32 {
	return volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3
}
func (o *MCPWM_Type) SetGEN1_A_UTEP(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetGEN1_A_UTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetGEN1_A_UTEA(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30)|value<<4)
}
func (o *MCPWM_Type) GetGEN1_A_UTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30) >> 4
}
func (o *MCPWM_Type) SetGEN1_A_UTEB(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN1_A_UTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN1_A_UT0(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN1_A_UT0() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN1_A_UT1(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetGEN1_A_UT1() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetGEN1_A_DTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetGEN1_A_DTEZ() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetGEN1_A_DTEP(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN1_A_DTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetGEN1_A_DTEA(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetGEN1_A_DTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetGEN1_A_DTEB(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetGEN1_A_DTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetGEN1_A_DT0(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetGEN1_A_DT0() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetGEN1_A_DT1(value uint32) {
	volatile.StoreUint32(&o.GEN1_A.Reg, volatile.LoadUint32(&o.GEN1_A.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetGEN1_A_DT1() uint32 {
	return (volatile.LoadUint32(&o.GEN1_A.Reg) & 0xc00000) >> 22
}

// MCPWM.GEN1_B: PWM%s output signal B actions configuration register
func (o *MCPWM_Type) SetGEN1_B_UTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3)|value)
}
func (o *MCPWM_Type) GetGEN1_B_UTEZ() uint32 {
	return volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3
}
func (o *MCPWM_Type) SetGEN1_B_UTEP(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetGEN1_B_UTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetGEN1_B_UTEA(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30)|value<<4)
}
func (o *MCPWM_Type) GetGEN1_B_UTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30) >> 4
}
func (o *MCPWM_Type) SetGEN1_B_UTEB(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN1_B_UTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN1_B_UT0(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN1_B_UT0() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN1_B_UT1(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetGEN1_B_UT1() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetGEN1_B_DTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetGEN1_B_DTEZ() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetGEN1_B_DTEP(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN1_B_DTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetGEN1_B_DTEA(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetGEN1_B_DTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetGEN1_B_DTEB(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetGEN1_B_DTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetGEN1_B_DT0(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetGEN1_B_DT0() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetGEN1_B_DT1(value uint32) {
	volatile.StoreUint32(&o.GEN1_B.Reg, volatile.LoadUint32(&o.GEN1_B.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetGEN1_B_DT1() uint32 {
	return (volatile.LoadUint32(&o.GEN1_B.Reg) & 0xc00000) >> 22
}

// MCPWM.DT1_CFG: Dead time configuration register
func (o *MCPWM_Type) SetDT1_CFG_DB_FED_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_FED_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf
}
func (o *MCPWM_Type) SetDT1_CFG_DB_RED_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_RED_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0xf0) >> 4
}
func (o *MCPWM_Type) SetDT1_CFG_DB_DEB_MODE(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_DEB_MODE() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetDT1_CFG_DB_A_OUTSWAP(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_A_OUTSWAP() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetDT1_CFG_DB_B_OUTSWAP(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_B_OUTSWAP() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetDT1_CFG_DB_RED_INSEL(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_RED_INSEL() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetDT1_CFG_DB_FED_INSEL(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_FED_INSEL() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetDT1_CFG_DB_RED_OUTINVERT(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_RED_OUTINVERT() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetDT1_CFG_DB_FED_OUTINVERT(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_FED_OUTINVERT() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetDT1_CFG_DB_A_OUTBYPASS(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_A_OUTBYPASS() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetDT1_CFG_DB_B_OUTBYPASS(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_B_OUTBYPASS() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetDT1_CFG_DB_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.DT1_CFG.Reg, volatile.LoadUint32(&o.DT1_CFG.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetDT1_CFG_DB_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.DT1_CFG.Reg) & 0x20000) >> 17
}

// MCPWM.DT1_FED_CFG: Falling edge delay (FED) shadow register
func (o *MCPWM_Type) SetDT1_FED_CFG_DB_FED(value uint32) {
	volatile.StoreUint32(&o.DT1_FED_CFG.Reg, volatile.LoadUint32(&o.DT1_FED_CFG.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetDT1_FED_CFG_DB_FED() uint32 {
	return volatile.LoadUint32(&o.DT1_FED_CFG.Reg) & 0xffff
}

// MCPWM.DT1_RED_CFG: Rising edge delay (RED) shadow register
func (o *MCPWM_Type) SetDT1_RED_CFG_DB_RED(value uint32) {
	volatile.StoreUint32(&o.DT1_RED_CFG.Reg, volatile.LoadUint32(&o.DT1_RED_CFG.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetDT1_RED_CFG_DB_RED() uint32 {
	return volatile.LoadUint32(&o.DT1_RED_CFG.Reg) & 0xffff
}

// MCPWM.CARRIER1_CFG: Carrier%s configuration register
func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_EN(value uint32) {
	volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_EN() uint32 {
	return volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1e)|value<<1)
}
func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1e) >> 1
}
func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_DUTY(value uint32) {
	volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xe0)|value<<5)
}
func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_DUTY() uint32 {
	return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xe0) >> 5
}
func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_OSHTWTH(value uint32) {
	volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0xf00)|value<<8)
}
func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_OSHTWTH() uint32 {
	return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0xf00) >> 8
}
func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_OUT_INVERT(value uint32) {
	volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_OUT_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetCARRIER1_CFG_CHOPPER_IN_INVERT(value uint32) {
	volatile.StoreUint32(&o.CARRIER1_CFG.Reg, volatile.LoadUint32(&o.CARRIER1_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetCARRIER1_CFG_CHOPPER_IN_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CARRIER1_CFG.Reg) & 0x2000) >> 13
}

// MCPWM.FH1_CFG0: PWM%s A and PWM%s B trip events actions configuration register
func (o *MCPWM_Type) SetFH1_CFG0_TZ_SW_CBC(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_SW_CBC() uint32 {
	return volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_F2_CBC(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_F2_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_F1_CBC(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_F1_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_F0_CBC(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_F0_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_SW_OST(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_SW_OST() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_F2_OST(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_F2_OST() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_F1_OST(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_F1_OST() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_F0_OST(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_F0_OST() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_CBC_D(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_CBC_D() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_CBC_U(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_CBC_U() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_OST_D(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_OST_D() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_A_OST_U(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_A_OST_U() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_CBC_D(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_CBC_D() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_CBC_U(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_CBC_U() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_OST_D(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_OST_D() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetFH1_CFG0_TZ_B_OST_U(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG0.Reg, volatile.LoadUint32(&o.FH1_CFG0.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetFH1_CFG0_TZ_B_OST_U() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG0.Reg) & 0xc00000) >> 22
}

// MCPWM.FH1_CFG1: Software triggers for fault handler actions configuration register
func (o *MCPWM_Type) SetFH1_CFG1_TZ_CLR_OST(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH1_CFG1_TZ_CLR_OST() uint32 {
	return volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH1_CFG1_TZ_CBCPULSE(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x6)|value<<1)
}
func (o *MCPWM_Type) GetFH1_CFG1_TZ_CBCPULSE() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x6) >> 1
}
func (o *MCPWM_Type) SetFH1_CFG1_TZ_FORCE_CBC(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetFH1_CFG1_TZ_FORCE_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetFH1_CFG1_TZ_FORCE_OST(value uint32) {
	volatile.StoreUint32(&o.FH1_CFG1.Reg, volatile.LoadUint32(&o.FH1_CFG1.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetFH1_CFG1_TZ_FORCE_OST() uint32 {
	return (volatile.LoadUint32(&o.FH1_CFG1.Reg) & 0x10) >> 4
}

// MCPWM.FH1_STATUS: Fault events status register
func (o *MCPWM_Type) SetFH1_STATUS_TZ_CBC_ON(value uint32) {
	volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH1_STATUS_TZ_CBC_ON() uint32 {
	return volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH1_STATUS_TZ_OST_ON(value uint32) {
	volatile.StoreUint32(&o.FH1_STATUS.Reg, volatile.LoadUint32(&o.FH1_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetFH1_STATUS_TZ_OST_ON() uint32 {
	return (volatile.LoadUint32(&o.FH1_STATUS.Reg) & 0x2) >> 1
}

// MCPWM.GEN2_STMP_CFG: Generator%s time stamp registers A and B transfer status and update method register
func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_A_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_A_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf
}
func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_B_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_B_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0xf0) >> 4
}
func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_A_SHDW_FULL(value uint32) {
	volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_A_SHDW_FULL() uint32 {
	return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetGEN2_STMP_CFG_CMPR_B_SHDW_FULL(value uint32) {
	volatile.StoreUint32(&o.GEN2_STMP_CFG.Reg, volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetGEN2_STMP_CFG_CMPR_B_SHDW_FULL() uint32 {
	return (volatile.LoadUint32(&o.GEN2_STMP_CFG.Reg) & 0x200) >> 9
}

// MCPWM.GEN2_TSTMP_A: Generator%s time stamp A's shadow register
func (o *MCPWM_Type) SetGEN2_TSTMP_A_CMPR_A(value uint32) {
	volatile.StoreUint32(&o.GEN2_TSTMP_A.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetGEN2_TSTMP_A_CMPR_A() uint32 {
	return volatile.LoadUint32(&o.GEN2_TSTMP_A.Reg) & 0xffff
}

// MCPWM.GEN2_TSTMP_B: Generator%s time stamp B's shadow register
func (o *MCPWM_Type) SetGEN2_TSTMP_B_CMPR_B(value uint32) {
	volatile.StoreUint32(&o.GEN2_TSTMP_B.Reg, volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetGEN2_TSTMP_B_CMPR_B() uint32 {
	return volatile.LoadUint32(&o.GEN2_TSTMP_B.Reg) & 0xffff
}

// MCPWM.GEN2_CFG0: Generator%s fault event T0 and T1 configuration register
func (o *MCPWM_Type) SetGEN2_CFG0_GEN_CFG_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetGEN2_CFG0_GEN_CFG_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0xf
}
func (o *MCPWM_Type) SetGEN2_CFG0_GEN_T0_SEL(value uint32) {
	volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x70)|value<<4)
}
func (o *MCPWM_Type) GetGEN2_CFG0_GEN_T0_SEL() uint32 {
	return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x70) >> 4
}
func (o *MCPWM_Type) SetGEN2_CFG0_GEN_T1_SEL(value uint32) {
	volatile.StoreUint32(&o.GEN2_CFG0.Reg, volatile.LoadUint32(&o.GEN2_CFG0.Reg)&^(0x380)|value<<7)
}
func (o *MCPWM_Type) GetGEN2_CFG0_GEN_T1_SEL() uint32 {
	return (volatile.LoadUint32(&o.GEN2_CFG0.Reg) & 0x380) >> 7
}

// MCPWM.GEN2_FORCE: Generator%s output signal force mode register.
func (o *MCPWM_Type) SetGEN2_FORCE_GEN_CNTUFORCE_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x3f)|value)
}
func (o *MCPWM_Type) GetGEN2_FORCE_GEN_CNTUFORCE_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x3f
}
func (o *MCPWM_Type) SetGEN2_FORCE_GEN_A_CNTUFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN2_FORCE_GEN_A_CNTUFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN2_FORCE_GEN_B_CNTUFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN2_FORCE_GEN_B_CNTUFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN2_FORCE_GEN_A_NCIFORCE(value uint32) {
	volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetGEN2_FORCE_GEN_A_NCIFORCE() uint32 {
	return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetGEN2_FORCE_GEN_A_NCIFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x1800)|value<<11)
}
func (o *MCPWM_Type) GetGEN2_FORCE_GEN_A_NCIFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x1800) >> 11
}
func (o *MCPWM_Type) SetGEN2_FORCE_GEN_B_NCIFORCE(value uint32) {
	volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetGEN2_FORCE_GEN_B_NCIFORCE() uint32 {
	return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetGEN2_FORCE_GEN_B_NCIFORCE_MODE(value uint32) {
	volatile.StoreUint32(&o.GEN2_FORCE.Reg, volatile.LoadUint32(&o.GEN2_FORCE.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN2_FORCE_GEN_B_NCIFORCE_MODE() uint32 {
	return (volatile.LoadUint32(&o.GEN2_FORCE.Reg) & 0xc000) >> 14
}

// MCPWM.GEN2_A: PWM%s output signal A actions configuration register
func (o *MCPWM_Type) SetGEN2_A_UTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3)|value)
}
func (o *MCPWM_Type) GetGEN2_A_UTEZ() uint32 {
	return volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3
}
func (o *MCPWM_Type) SetGEN2_A_UTEP(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetGEN2_A_UTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetGEN2_A_UTEA(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30)|value<<4)
}
func (o *MCPWM_Type) GetGEN2_A_UTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30) >> 4
}
func (o *MCPWM_Type) SetGEN2_A_UTEB(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN2_A_UTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN2_A_UT0(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN2_A_UT0() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN2_A_UT1(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetGEN2_A_UT1() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetGEN2_A_DTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetGEN2_A_DTEZ() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetGEN2_A_DTEP(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN2_A_DTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetGEN2_A_DTEA(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetGEN2_A_DTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetGEN2_A_DTEB(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetGEN2_A_DTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetGEN2_A_DT0(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetGEN2_A_DT0() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetGEN2_A_DT1(value uint32) {
	volatile.StoreUint32(&o.GEN2_A.Reg, volatile.LoadUint32(&o.GEN2_A.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetGEN2_A_DT1() uint32 {
	return (volatile.LoadUint32(&o.GEN2_A.Reg) & 0xc00000) >> 22
}

// MCPWM.GEN2_B: PWM%s output signal B actions configuration register
func (o *MCPWM_Type) SetGEN2_B_UTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3)|value)
}
func (o *MCPWM_Type) GetGEN2_B_UTEZ() uint32 {
	return volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3
}
func (o *MCPWM_Type) SetGEN2_B_UTEP(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc)|value<<2)
}
func (o *MCPWM_Type) GetGEN2_B_UTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc) >> 2
}
func (o *MCPWM_Type) SetGEN2_B_UTEA(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30)|value<<4)
}
func (o *MCPWM_Type) GetGEN2_B_UTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30) >> 4
}
func (o *MCPWM_Type) SetGEN2_B_UTEB(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0)|value<<6)
}
func (o *MCPWM_Type) GetGEN2_B_UTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0) >> 6
}
func (o *MCPWM_Type) SetGEN2_B_UT0(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetGEN2_B_UT0() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetGEN2_B_UT1(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetGEN2_B_UT1() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetGEN2_B_DTEZ(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetGEN2_B_DTEZ() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetGEN2_B_DTEP(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetGEN2_B_DTEP() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetGEN2_B_DTEA(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetGEN2_B_DTEA() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetGEN2_B_DTEB(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetGEN2_B_DTEB() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetGEN2_B_DT0(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetGEN2_B_DT0() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetGEN2_B_DT1(value uint32) {
	volatile.StoreUint32(&o.GEN2_B.Reg, volatile.LoadUint32(&o.GEN2_B.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetGEN2_B_DT1() uint32 {
	return (volatile.LoadUint32(&o.GEN2_B.Reg) & 0xc00000) >> 22
}

// MCPWM.DT2_CFG: Dead time configuration register
func (o *MCPWM_Type) SetDT2_CFG_DB_FED_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf)|value)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_FED_UPMETHOD() uint32 {
	return volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf
}
func (o *MCPWM_Type) SetDT2_CFG_DB_RED_UPMETHOD(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0xf0)|value<<4)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_RED_UPMETHOD() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0xf0) >> 4
}
func (o *MCPWM_Type) SetDT2_CFG_DB_DEB_MODE(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_DEB_MODE() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetDT2_CFG_DB_A_OUTSWAP(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_A_OUTSWAP() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetDT2_CFG_DB_B_OUTSWAP(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_B_OUTSWAP() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetDT2_CFG_DB_RED_INSEL(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_RED_INSEL() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetDT2_CFG_DB_FED_INSEL(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_FED_INSEL() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetDT2_CFG_DB_RED_OUTINVERT(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_RED_OUTINVERT() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetDT2_CFG_DB_FED_OUTINVERT(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_FED_OUTINVERT() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetDT2_CFG_DB_A_OUTBYPASS(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_A_OUTBYPASS() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetDT2_CFG_DB_B_OUTBYPASS(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_B_OUTBYPASS() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetDT2_CFG_DB_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.DT2_CFG.Reg, volatile.LoadUint32(&o.DT2_CFG.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetDT2_CFG_DB_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.DT2_CFG.Reg) & 0x20000) >> 17
}

// MCPWM.DT2_FED_CFG: Falling edge delay (FED) shadow register
func (o *MCPWM_Type) SetDT2_FED_CFG_DB_FED(value uint32) {
	volatile.StoreUint32(&o.DT2_FED_CFG.Reg, volatile.LoadUint32(&o.DT2_FED_CFG.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetDT2_FED_CFG_DB_FED() uint32 {
	return volatile.LoadUint32(&o.DT2_FED_CFG.Reg) & 0xffff
}

// MCPWM.DT2_RED_CFG: Rising edge delay (RED) shadow register
func (o *MCPWM_Type) SetDT2_RED_CFG_DB_RED(value uint32) {
	volatile.StoreUint32(&o.DT2_RED_CFG.Reg, volatile.LoadUint32(&o.DT2_RED_CFG.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetDT2_RED_CFG_DB_RED() uint32 {
	return volatile.LoadUint32(&o.DT2_RED_CFG.Reg) & 0xffff
}

// MCPWM.CARRIER2_CFG: Carrier%s configuration register
func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_EN(value uint32) {
	volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_EN() uint32 {
	return volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1e)|value<<1)
}
func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1e) >> 1
}
func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_DUTY(value uint32) {
	volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xe0)|value<<5)
}
func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_DUTY() uint32 {
	return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xe0) >> 5
}
func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_OSHTWTH(value uint32) {
	volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0xf00)|value<<8)
}
func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_OSHTWTH() uint32 {
	return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0xf00) >> 8
}
func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_OUT_INVERT(value uint32) {
	volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_OUT_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetCARRIER2_CFG_CHOPPER_IN_INVERT(value uint32) {
	volatile.StoreUint32(&o.CARRIER2_CFG.Reg, volatile.LoadUint32(&o.CARRIER2_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetCARRIER2_CFG_CHOPPER_IN_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CARRIER2_CFG.Reg) & 0x2000) >> 13
}

// MCPWM.FH2_CFG0: PWM%s A and PWM%s B trip events actions configuration register
func (o *MCPWM_Type) SetFH2_CFG0_TZ_SW_CBC(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_SW_CBC() uint32 {
	return volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_F2_CBC(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_F2_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_F1_CBC(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_F1_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_F0_CBC(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_F0_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_SW_OST(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_SW_OST() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_F2_OST(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_F2_OST() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_F1_OST(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_F1_OST() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_F0_OST(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_F0_OST() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_CBC_D(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300)|value<<8)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_CBC_D() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300) >> 8
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_CBC_U(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00)|value<<10)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_CBC_U() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00) >> 10
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_OST_D(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x3000)|value<<12)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_OST_D() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x3000) >> 12
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_A_OST_U(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc000)|value<<14)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_A_OST_U() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc000) >> 14
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_CBC_D(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x30000)|value<<16)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_CBC_D() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x30000) >> 16
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_CBC_U(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc0000)|value<<18)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_CBC_U() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc0000) >> 18
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_OST_D(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0x300000)|value<<20)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_OST_D() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0x300000) >> 20
}
func (o *MCPWM_Type) SetFH2_CFG0_TZ_B_OST_U(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG0.Reg, volatile.LoadUint32(&o.FH2_CFG0.Reg)&^(0xc00000)|value<<22)
}
func (o *MCPWM_Type) GetFH2_CFG0_TZ_B_OST_U() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG0.Reg) & 0xc00000) >> 22
}

// MCPWM.FH2_CFG1: Software triggers for fault handler actions configuration register
func (o *MCPWM_Type) SetFH2_CFG1_TZ_CLR_OST(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH2_CFG1_TZ_CLR_OST() uint32 {
	return volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH2_CFG1_TZ_CBCPULSE(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x6)|value<<1)
}
func (o *MCPWM_Type) GetFH2_CFG1_TZ_CBCPULSE() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x6) >> 1
}
func (o *MCPWM_Type) SetFH2_CFG1_TZ_FORCE_CBC(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetFH2_CFG1_TZ_FORCE_CBC() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetFH2_CFG1_TZ_FORCE_OST(value uint32) {
	volatile.StoreUint32(&o.FH2_CFG1.Reg, volatile.LoadUint32(&o.FH2_CFG1.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetFH2_CFG1_TZ_FORCE_OST() uint32 {
	return (volatile.LoadUint32(&o.FH2_CFG1.Reg) & 0x10) >> 4
}

// MCPWM.FH2_STATUS: Fault events status register
func (o *MCPWM_Type) SetFH2_STATUS_TZ_CBC_ON(value uint32) {
	volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFH2_STATUS_TZ_CBC_ON() uint32 {
	return volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x1
}
func (o *MCPWM_Type) SetFH2_STATUS_TZ_OST_ON(value uint32) {
	volatile.StoreUint32(&o.FH2_STATUS.Reg, volatile.LoadUint32(&o.FH2_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetFH2_STATUS_TZ_OST_ON() uint32 {
	return (volatile.LoadUint32(&o.FH2_STATUS.Reg) & 0x2) >> 1
}

// MCPWM.FAULT_DETECT: Fault detection configuration and status register
func (o *MCPWM_Type) SetFAULT_DETECT_F0_EN(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetFAULT_DETECT_F0_EN() uint32 {
	return volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x1
}
func (o *MCPWM_Type) SetFAULT_DETECT_F1_EN(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetFAULT_DETECT_F1_EN() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetFAULT_DETECT_F2_EN(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetFAULT_DETECT_F2_EN() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetFAULT_DETECT_F0_POLE(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetFAULT_DETECT_F0_POLE() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetFAULT_DETECT_F1_POLE(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetFAULT_DETECT_F1_POLE() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetFAULT_DETECT_F2_POLE(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetFAULT_DETECT_F2_POLE() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F0(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F0() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F1(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F1() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetFAULT_DETECT_EVENT_F2(value uint32) {
	volatile.StoreUint32(&o.FAULT_DETECT.Reg, volatile.LoadUint32(&o.FAULT_DETECT.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetFAULT_DETECT_EVENT_F2() uint32 {
	return (volatile.LoadUint32(&o.FAULT_DETECT.Reg) & 0x100) >> 8
}

// MCPWM.CAP_TIMER_CFG: Capture timer configuration register
func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_TIMER_EN(value uint32) {
	volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_TIMER_EN() uint32 {
	return volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_EN(value uint32) {
	volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_EN() uint32 {
	return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNCI_SEL(value uint32) {
	volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x1c)|value<<2)
}
func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNCI_SEL() uint32 {
	return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x1c) >> 2
}
func (o *MCPWM_Type) SetCAP_TIMER_CFG_CAP_SYNC_SW(value uint32) {
	volatile.StoreUint32(&o.CAP_TIMER_CFG.Reg, volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetCAP_TIMER_CFG_CAP_SYNC_SW() uint32 {
	return (volatile.LoadUint32(&o.CAP_TIMER_CFG.Reg) & 0x20) >> 5
}

// MCPWM.CAP_TIMER_PHASE: Capture timer sync phase register
func (o *MCPWM_Type) SetCAP_TIMER_PHASE(value uint32) {
	volatile.StoreUint32(&o.CAP_TIMER_PHASE.Reg, value)
}
func (o *MCPWM_Type) GetCAP_TIMER_PHASE() uint32 {
	return volatile.LoadUint32(&o.CAP_TIMER_PHASE.Reg)
}

// MCPWM.CAP_CH0_CFG: Capture channel %s configuration register
func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_EN(value uint32) {
	volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_EN() uint32 {
	return volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_MODE(value uint32) {
	volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x6)|value<<1)
}
func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x6) >> 1
}
func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x7f8)|value<<3)
}
func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x7f8) >> 3
}
func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_IN_INVERT(value uint32) {
	volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_IN_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetCAP_CH0_CFG_CAP_SW(value uint32) {
	volatile.StoreUint32(&o.CAP_CH0_CFG.Reg, volatile.LoadUint32(&o.CAP_CH0_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetCAP_CH0_CFG_CAP_SW() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH0_CFG.Reg) & 0x1000) >> 12
}

// MCPWM.CAP_CH1_CFG: Capture channel %s configuration register
func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_EN(value uint32) {
	volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_EN() uint32 {
	return volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_MODE(value uint32) {
	volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x6)|value<<1)
}
func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x6) >> 1
}
func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x7f8)|value<<3)
}
func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x7f8) >> 3
}
func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_IN_INVERT(value uint32) {
	volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_IN_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetCAP_CH1_CFG_CAP_SW(value uint32) {
	volatile.StoreUint32(&o.CAP_CH1_CFG.Reg, volatile.LoadUint32(&o.CAP_CH1_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetCAP_CH1_CFG_CAP_SW() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH1_CFG.Reg) & 0x1000) >> 12
}

// MCPWM.CAP_CH2_CFG: Capture channel %s configuration register
func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_EN(value uint32) {
	volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_EN() uint32 {
	return volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_MODE(value uint32) {
	volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x6)|value<<1)
}
func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_MODE() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x6) >> 1
}
func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x7f8)|value<<3)
}
func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x7f8) >> 3
}
func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_IN_INVERT(value uint32) {
	volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_IN_INVERT() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetCAP_CH2_CFG_CAP_SW(value uint32) {
	volatile.StoreUint32(&o.CAP_CH2_CFG.Reg, volatile.LoadUint32(&o.CAP_CH2_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetCAP_CH2_CFG_CAP_SW() uint32 {
	return (volatile.LoadUint32(&o.CAP_CH2_CFG.Reg) & 0x1000) >> 12
}

// MCPWM.CAP_CH0: CAP%s capture value register
func (o *MCPWM_Type) SetCAP_CH0(value uint32) {
	volatile.StoreUint32(&o.CAP_CH0.Reg, value)
}
func (o *MCPWM_Type) GetCAP_CH0() uint32 {
	return volatile.LoadUint32(&o.CAP_CH0.Reg)
}

// MCPWM.CAP_CH1: CAP%s capture value register
func (o *MCPWM_Type) SetCAP_CH1(value uint32) {
	volatile.StoreUint32(&o.CAP_CH1.Reg, value)
}
func (o *MCPWM_Type) GetCAP_CH1() uint32 {
	return volatile.LoadUint32(&o.CAP_CH1.Reg)
}

// MCPWM.CAP_CH2: CAP%s capture value register
func (o *MCPWM_Type) SetCAP_CH2(value uint32) {
	volatile.StoreUint32(&o.CAP_CH2.Reg, value)
}
func (o *MCPWM_Type) GetCAP_CH2() uint32 {
	return volatile.LoadUint32(&o.CAP_CH2.Reg)
}

// MCPWM.CAP_STATUS: Last capture trigger edge information register
func (o *MCPWM_Type) SetCAP_STATUS_CAP0_EDGE(value uint32) {
	volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCAP_STATUS_CAP0_EDGE() uint32 {
	return volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x1
}
func (o *MCPWM_Type) SetCAP_STATUS_CAP1_EDGE(value uint32) {
	volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetCAP_STATUS_CAP1_EDGE() uint32 {
	return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetCAP_STATUS_CAP2_EDGE(value uint32) {
	volatile.StoreUint32(&o.CAP_STATUS.Reg, volatile.LoadUint32(&o.CAP_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetCAP_STATUS_CAP2_EDGE() uint32 {
	return (volatile.LoadUint32(&o.CAP_STATUS.Reg) & 0x4) >> 2
}

// MCPWM.UPDATE_CFG: Generator Update configuration register
func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_UP_EN(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_UP_EN() uint32 {
	return volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x1
}
func (o *MCPWM_Type) SetUPDATE_CFG_GLOBAL_FORCE_UP(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetUPDATE_CFG_GLOBAL_FORCE_UP() uint32 {
	return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetUPDATE_CFG_OP0_UP_EN(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetUPDATE_CFG_OP0_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetUPDATE_CFG_OP0_FORCE_UP(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetUPDATE_CFG_OP0_FORCE_UP() uint32 {
	return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetUPDATE_CFG_OP1_UP_EN(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetUPDATE_CFG_OP1_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetUPDATE_CFG_OP1_FORCE_UP(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetUPDATE_CFG_OP1_FORCE_UP() uint32 {
	return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetUPDATE_CFG_OP2_UP_EN(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetUPDATE_CFG_OP2_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetUPDATE_CFG_OP2_FORCE_UP(value uint32) {
	volatile.StoreUint32(&o.UPDATE_CFG.Reg, volatile.LoadUint32(&o.UPDATE_CFG.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetUPDATE_CFG_OP2_FORCE_UP() uint32 {
	return (volatile.LoadUint32(&o.UPDATE_CFG.Reg) & 0x80) >> 7
}

// MCPWM.INT_ENA: Interrupt enable register
func (o *MCPWM_Type) SetINT_ENA_TIMER0_STOP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER0_STOP_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *MCPWM_Type) SetINT_ENA_TIMER1_STOP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER1_STOP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetINT_ENA_TIMER2_STOP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER2_STOP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEZ_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEZ_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEZ_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEZ_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEZ_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEZ_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetINT_ENA_TIMER0_TEP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER0_TEP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetINT_ENA_TIMER1_TEP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER1_TEP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetINT_ENA_TIMER2_TEP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetINT_ENA_TIMER2_TEP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetINT_ENA_FAULT0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetINT_ENA_FAULT0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetINT_ENA_FAULT1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetINT_ENA_FAULT1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetINT_ENA_FAULT2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetINT_ENA_FAULT2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetINT_ENA_FAULT0_CLR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetINT_ENA_FAULT0_CLR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetINT_ENA_FAULT1_CLR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetINT_ENA_FAULT1_CLR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetINT_ENA_FAULT2_CLR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetINT_ENA_FAULT2_CLR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEA_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEA_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEA_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEA_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEA_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEA_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17
}
func (o *MCPWM_Type) SetINT_ENA_CMPR0_TEB_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *MCPWM_Type) GetINT_ENA_CMPR0_TEB_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}
func (o *MCPWM_Type) SetINT_ENA_CMPR1_TEB_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *MCPWM_Type) GetINT_ENA_CMPR1_TEB_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19
}
func (o *MCPWM_Type) SetINT_ENA_CMPR2_TEB_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetINT_ENA_CMPR2_TEB_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20
}
func (o *MCPWM_Type) SetINT_ENA_TZ0_CBC_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21)
}
func (o *MCPWM_Type) GetINT_ENA_TZ0_CBC_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21
}
func (o *MCPWM_Type) SetINT_ENA_TZ1_CBC_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22)
}
func (o *MCPWM_Type) GetINT_ENA_TZ1_CBC_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22
}
func (o *MCPWM_Type) SetINT_ENA_TZ2_CBC_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23)
}
func (o *MCPWM_Type) GetINT_ENA_TZ2_CBC_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23
}
func (o *MCPWM_Type) SetINT_ENA_TZ0_OST_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24)
}
func (o *MCPWM_Type) GetINT_ENA_TZ0_OST_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24
}
func (o *MCPWM_Type) SetINT_ENA_TZ1_OST_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25)
}
func (o *MCPWM_Type) GetINT_ENA_TZ1_OST_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25
}
func (o *MCPWM_Type) SetINT_ENA_TZ2_OST_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26)
}
func (o *MCPWM_Type) GetINT_ENA_TZ2_OST_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26
}
func (o *MCPWM_Type) SetINT_ENA_CAP0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27)
}
func (o *MCPWM_Type) GetINT_ENA_CAP0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27
}
func (o *MCPWM_Type) SetINT_ENA_CAP1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *MCPWM_Type) GetINT_ENA_CAP1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28
}
func (o *MCPWM_Type) SetINT_ENA_CAP2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29)
}
func (o *MCPWM_Type) GetINT_ENA_CAP2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29
}

// MCPWM.INT_RAW: Interrupt raw status register
func (o *MCPWM_Type) SetINT_RAW_TIMER0_STOP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER0_STOP_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *MCPWM_Type) SetINT_RAW_TIMER1_STOP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER1_STOP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetINT_RAW_TIMER2_STOP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER2_STOP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEZ_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEZ_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEZ_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEZ_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEZ_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEZ_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetINT_RAW_TIMER0_TEP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER0_TEP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetINT_RAW_TIMER1_TEP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER1_TEP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetINT_RAW_TIMER2_TEP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetINT_RAW_TIMER2_TEP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetINT_RAW_FAULT0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetINT_RAW_FAULT0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetINT_RAW_FAULT1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetINT_RAW_FAULT1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetINT_RAW_FAULT2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetINT_RAW_FAULT2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetINT_RAW_FAULT0_CLR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetINT_RAW_FAULT0_CLR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetINT_RAW_FAULT1_CLR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetINT_RAW_FAULT1_CLR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetINT_RAW_FAULT2_CLR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetINT_RAW_FAULT2_CLR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEA_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEA_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEA_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEA_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEA_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEA_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *MCPWM_Type) SetINT_RAW_CMPR0_TEB_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *MCPWM_Type) GetINT_RAW_CMPR0_TEB_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *MCPWM_Type) SetINT_RAW_CMPR1_TEB_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *MCPWM_Type) GetINT_RAW_CMPR1_TEB_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}
func (o *MCPWM_Type) SetINT_RAW_CMPR2_TEB_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetINT_RAW_CMPR2_TEB_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20
}
func (o *MCPWM_Type) SetINT_RAW_TZ0_CBC_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21)
}
func (o *MCPWM_Type) GetINT_RAW_TZ0_CBC_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21
}
func (o *MCPWM_Type) SetINT_RAW_TZ1_CBC_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22)
}
func (o *MCPWM_Type) GetINT_RAW_TZ1_CBC_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22
}
func (o *MCPWM_Type) SetINT_RAW_TZ2_CBC_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23)
}
func (o *MCPWM_Type) GetINT_RAW_TZ2_CBC_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23
}
func (o *MCPWM_Type) SetINT_RAW_TZ0_OST_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24)
}
func (o *MCPWM_Type) GetINT_RAW_TZ0_OST_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24
}
func (o *MCPWM_Type) SetINT_RAW_TZ1_OST_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25)
}
func (o *MCPWM_Type) GetINT_RAW_TZ1_OST_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25
}
func (o *MCPWM_Type) SetINT_RAW_TZ2_OST_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26)
}
func (o *MCPWM_Type) GetINT_RAW_TZ2_OST_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26
}
func (o *MCPWM_Type) SetINT_RAW_CAP0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27)
}
func (o *MCPWM_Type) GetINT_RAW_CAP0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27
}
func (o *MCPWM_Type) SetINT_RAW_CAP1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *MCPWM_Type) GetINT_RAW_CAP1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28
}
func (o *MCPWM_Type) SetINT_RAW_CAP2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29)
}
func (o *MCPWM_Type) GetINT_RAW_CAP2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29
}

// MCPWM.INT_ST: Interrupt masked status register
func (o *MCPWM_Type) SetINT_ST_TIMER0_STOP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetINT_ST_TIMER0_STOP_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *MCPWM_Type) SetINT_ST_TIMER1_STOP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetINT_ST_TIMER1_STOP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetINT_ST_TIMER2_STOP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetINT_ST_TIMER2_STOP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetINT_ST_TIMER0_TEZ_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetINT_ST_TIMER0_TEZ_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetINT_ST_TIMER1_TEZ_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetINT_ST_TIMER1_TEZ_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetINT_ST_TIMER2_TEZ_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetINT_ST_TIMER2_TEZ_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetINT_ST_TIMER0_TEP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetINT_ST_TIMER0_TEP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetINT_ST_TIMER1_TEP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetINT_ST_TIMER1_TEP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetINT_ST_TIMER2_TEP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetINT_ST_TIMER2_TEP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetINT_ST_FAULT0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetINT_ST_FAULT0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetINT_ST_FAULT1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetINT_ST_FAULT1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetINT_ST_FAULT2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetINT_ST_FAULT2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetINT_ST_FAULT0_CLR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetINT_ST_FAULT0_CLR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetINT_ST_FAULT1_CLR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetINT_ST_FAULT1_CLR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetINT_ST_FAULT2_CLR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetINT_ST_FAULT2_CLR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetINT_ST_CMPR0_TEA_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetINT_ST_CMPR0_TEA_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetINT_ST_CMPR1_TEA_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetINT_ST_CMPR1_TEA_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetINT_ST_CMPR2_TEA_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetINT_ST_CMPR2_TEA_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17
}
func (o *MCPWM_Type) SetINT_ST_CMPR0_TEB_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *MCPWM_Type) GetINT_ST_CMPR0_TEB_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18
}
func (o *MCPWM_Type) SetINT_ST_CMPR1_TEB_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *MCPWM_Type) GetINT_ST_CMPR1_TEB_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19
}
func (o *MCPWM_Type) SetINT_ST_CMPR2_TEB_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetINT_ST_CMPR2_TEB_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20
}
func (o *MCPWM_Type) SetINT_ST_TZ0_CBC_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21)
}
func (o *MCPWM_Type) GetINT_ST_TZ0_CBC_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21
}
func (o *MCPWM_Type) SetINT_ST_TZ1_CBC_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22)
}
func (o *MCPWM_Type) GetINT_ST_TZ1_CBC_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22
}
func (o *MCPWM_Type) SetINT_ST_TZ2_CBC_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23)
}
func (o *MCPWM_Type) GetINT_ST_TZ2_CBC_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23
}
func (o *MCPWM_Type) SetINT_ST_TZ0_OST_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24)
}
func (o *MCPWM_Type) GetINT_ST_TZ0_OST_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24
}
func (o *MCPWM_Type) SetINT_ST_TZ1_OST_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25)
}
func (o *MCPWM_Type) GetINT_ST_TZ1_OST_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25
}
func (o *MCPWM_Type) SetINT_ST_TZ2_OST_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26)
}
func (o *MCPWM_Type) GetINT_ST_TZ2_OST_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26
}
func (o *MCPWM_Type) SetINT_ST_CAP0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27)
}
func (o *MCPWM_Type) GetINT_ST_CAP0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27
}
func (o *MCPWM_Type) SetINT_ST_CAP1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *MCPWM_Type) GetINT_ST_CAP1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28
}
func (o *MCPWM_Type) SetINT_ST_CAP2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29)
}
func (o *MCPWM_Type) GetINT_ST_CAP2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29
}

// MCPWM.INT_CLR: Interrupt clear register
func (o *MCPWM_Type) SetINT_CLR_TIMER0_STOP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER0_STOP_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *MCPWM_Type) SetINT_CLR_TIMER1_STOP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER1_STOP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetINT_CLR_TIMER2_STOP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER2_STOP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEZ_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEZ_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEZ_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEZ_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEZ_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEZ_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetINT_CLR_TIMER0_TEP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER0_TEP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetINT_CLR_TIMER1_TEP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER1_TEP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetINT_CLR_TIMER2_TEP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetINT_CLR_TIMER2_TEP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetINT_CLR_FAULT0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetINT_CLR_FAULT0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetINT_CLR_FAULT1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetINT_CLR_FAULT1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetINT_CLR_FAULT2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetINT_CLR_FAULT2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetINT_CLR_FAULT0_CLR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetINT_CLR_FAULT0_CLR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetINT_CLR_FAULT1_CLR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetINT_CLR_FAULT1_CLR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetINT_CLR_FAULT2_CLR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetINT_CLR_FAULT2_CLR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEA_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEA_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEA_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEA_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEA_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEA_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17
}
func (o *MCPWM_Type) SetINT_CLR_CMPR0_TEB_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *MCPWM_Type) GetINT_CLR_CMPR0_TEB_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}
func (o *MCPWM_Type) SetINT_CLR_CMPR1_TEB_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *MCPWM_Type) GetINT_CLR_CMPR1_TEB_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19
}
func (o *MCPWM_Type) SetINT_CLR_CMPR2_TEB_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetINT_CLR_CMPR2_TEB_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20
}
func (o *MCPWM_Type) SetINT_CLR_TZ0_CBC_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *MCPWM_Type) GetINT_CLR_TZ0_CBC_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21
}
func (o *MCPWM_Type) SetINT_CLR_TZ1_CBC_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *MCPWM_Type) GetINT_CLR_TZ1_CBC_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22
}
func (o *MCPWM_Type) SetINT_CLR_TZ2_CBC_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *MCPWM_Type) GetINT_CLR_TZ2_CBC_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23
}
func (o *MCPWM_Type) SetINT_CLR_TZ0_OST_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *MCPWM_Type) GetINT_CLR_TZ0_OST_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24
}
func (o *MCPWM_Type) SetINT_CLR_TZ1_OST_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *MCPWM_Type) GetINT_CLR_TZ1_OST_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25
}
func (o *MCPWM_Type) SetINT_CLR_TZ2_OST_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *MCPWM_Type) GetINT_CLR_TZ2_OST_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26
}
func (o *MCPWM_Type) SetINT_CLR_CAP0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *MCPWM_Type) GetINT_CLR_CAP0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27
}
func (o *MCPWM_Type) SetINT_CLR_CAP1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *MCPWM_Type) GetINT_CLR_CAP1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28
}
func (o *MCPWM_Type) SetINT_CLR_CAP2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *MCPWM_Type) GetINT_CLR_CAP2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29
}

// MCPWM.EVT_EN: Event enable register
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_STOP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_STOP_EN() uint32 {
	return volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_STOP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_STOP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_STOP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_STOP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEZ_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEZ_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEZ_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEZ_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEZ_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEZ_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER0_TEP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER0_TEP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER1_TEP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER1_TEP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TIMER2_TEP_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TIMER2_TEP_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEA_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEA_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEA_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEA_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEA_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEA_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetEVT_EN_EVT_OP0_TEB_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_OP0_TEB_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetEVT_EN_EVT_OP1_TEB_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_OP1_TEB_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetEVT_EN_EVT_OP2_TEB_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_OP2_TEB_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetEVT_EN_EVT_F0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_F0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetEVT_EN_EVT_F1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_F1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetEVT_EN_EVT_F2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_F2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000) >> 17
}
func (o *MCPWM_Type) SetEVT_EN_EVT_F0_CLR_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x40000)|value<<18)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_F0_CLR_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x40000) >> 18
}
func (o *MCPWM_Type) SetEVT_EN_EVT_F1_CLR_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x80000)|value<<19)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_F1_CLR_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x80000) >> 19
}
func (o *MCPWM_Type) SetEVT_EN_EVT_F2_CLR_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_F2_CLR_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x100000) >> 20
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_CBC_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x200000)|value<<21)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_CBC_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x200000) >> 21
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_CBC_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x400000)|value<<22)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_CBC_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x400000) >> 22
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_CBC_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x800000)|value<<23)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_CBC_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x800000) >> 23
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TZ0_OST_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x1000000)|value<<24)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TZ0_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x1000000) >> 24
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TZ1_OST_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x2000000)|value<<25)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TZ1_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x2000000) >> 25
}
func (o *MCPWM_Type) SetEVT_EN_EVT_TZ2_OST_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x4000000)|value<<26)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_TZ2_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x4000000) >> 26
}
func (o *MCPWM_Type) SetEVT_EN_EVT_CAP0_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x8000000)|value<<27)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_CAP0_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x8000000) >> 27
}
func (o *MCPWM_Type) SetEVT_EN_EVT_CAP1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x10000000)|value<<28)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_CAP1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x10000000) >> 28
}
func (o *MCPWM_Type) SetEVT_EN_EVT_CAP2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN.Reg, volatile.LoadUint32(&o.EVT_EN.Reg)&^(0x20000000)|value<<29)
}
func (o *MCPWM_Type) GetEVT_EN_EVT_CAP2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN.Reg) & 0x20000000) >> 29
}

// MCPWM.TASK_EN: Task enable register
func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_A_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_A_UP_EN() uint32 {
	return volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_A_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_A_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_A_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_A_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR0_B_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR0_B_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR1_B_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR1_B_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CMPR2_B_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CMPR2_B_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20) >> 5
}
func (o *MCPWM_Type) SetTASK_EN_TASK_GEN_STOP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40)|value<<6)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_GEN_STOP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40) >> 6
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_SYNC_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80)|value<<7)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_SYNC_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80) >> 7
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_SYNC_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100)|value<<8)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_SYNC_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100) >> 8
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_SYNC_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200)|value<<9)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_SYNC_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200) >> 9
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER0_PERIOD_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x400)|value<<10)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER0_PERIOD_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x400) >> 10
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER1_PERIOD_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x800)|value<<11)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER1_PERIOD_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x800) >> 11
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TIMER2_PERIOD_UP_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x1000)|value<<12)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TIMER2_PERIOD_UP_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x1000) >> 12
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TZ0_OST_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x2000)|value<<13)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TZ0_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x2000) >> 13
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TZ1_OST_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x4000)|value<<14)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TZ1_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x4000) >> 14
}
func (o *MCPWM_Type) SetTASK_EN_TASK_TZ2_OST_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x8000)|value<<15)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_TZ2_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x8000) >> 15
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CLR0_OST_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x10000)|value<<16)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CLR0_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x10000) >> 16
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CLR1_OST_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x20000)|value<<17)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CLR1_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x20000) >> 17
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CLR2_OST_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x40000)|value<<18)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CLR2_OST_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x40000) >> 18
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CAP0_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x80000)|value<<19)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CAP0_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x80000) >> 19
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CAP1_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x100000)|value<<20)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CAP1_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x100000) >> 20
}
func (o *MCPWM_Type) SetTASK_EN_TASK_CAP2_EN(value uint32) {
	volatile.StoreUint32(&o.TASK_EN.Reg, volatile.LoadUint32(&o.TASK_EN.Reg)&^(0x200000)|value<<21)
}
func (o *MCPWM_Type) GetTASK_EN_TASK_CAP2_EN() uint32 {
	return (volatile.LoadUint32(&o.TASK_EN.Reg) & 0x200000) >> 21
}

// MCPWM.EVT_EN2: Event enable register2
func (o *MCPWM_Type) SetEVT_EN2_EVT_OP0_TEE1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetEVT_EN2_EVT_OP0_TEE1_EN() uint32 {
	return volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x1
}
func (o *MCPWM_Type) SetEVT_EN2_EVT_OP1_TEE1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x2)|value<<1)
}
func (o *MCPWM_Type) GetEVT_EN2_EVT_OP1_TEE1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x2) >> 1
}
func (o *MCPWM_Type) SetEVT_EN2_EVT_OP2_TEE1_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x4)|value<<2)
}
func (o *MCPWM_Type) GetEVT_EN2_EVT_OP2_TEE1_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x4) >> 2
}
func (o *MCPWM_Type) SetEVT_EN2_EVT_OP0_TEE2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x8)|value<<3)
}
func (o *MCPWM_Type) GetEVT_EN2_EVT_OP0_TEE2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x8) >> 3
}
func (o *MCPWM_Type) SetEVT_EN2_EVT_OP1_TEE2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x10)|value<<4)
}
func (o *MCPWM_Type) GetEVT_EN2_EVT_OP1_TEE2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x10) >> 4
}
func (o *MCPWM_Type) SetEVT_EN2_EVT_OP2_TEE2_EN(value uint32) {
	volatile.StoreUint32(&o.EVT_EN2.Reg, volatile.LoadUint32(&o.EVT_EN2.Reg)&^(0x20)|value<<5)
}
func (o *MCPWM_Type) GetEVT_EN2_EVT_OP2_TEE2_EN() uint32 {
	return (volatile.LoadUint32(&o.EVT_EN2.Reg) & 0x20) >> 5
}

// MCPWM.OP0_TSTMP_E1: Generator%s timer stamp E1 value register
func (o *MCPWM_Type) SetOP0_TSTMP_E1_OP_TSTMP_E1(value uint32) {
	volatile.StoreUint32(&o.OP0_TSTMP_E1.Reg, volatile.LoadUint32(&o.OP0_TSTMP_E1.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetOP0_TSTMP_E1_OP_TSTMP_E1() uint32 {
	return volatile.LoadUint32(&o.OP0_TSTMP_E1.Reg) & 0xffff
}

// MCPWM.OP0_TSTMP_E2: Generator%s timer stamp E2 value register
func (o *MCPWM_Type) SetOP0_TSTMP_E2_OP_TSTMP_E2(value uint32) {
	volatile.StoreUint32(&o.OP0_TSTMP_E2.Reg, volatile.LoadUint32(&o.OP0_TSTMP_E2.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetOP0_TSTMP_E2_OP_TSTMP_E2() uint32 {
	return volatile.LoadUint32(&o.OP0_TSTMP_E2.Reg) & 0xffff
}

// MCPWM.OP1_TSTMP_E1: Generator%s timer stamp E1 value register
func (o *MCPWM_Type) SetOP1_TSTMP_E1_OP_TSTMP_E1(value uint32) {
	volatile.StoreUint32(&o.OP1_TSTMP_E1.Reg, volatile.LoadUint32(&o.OP1_TSTMP_E1.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetOP1_TSTMP_E1_OP_TSTMP_E1() uint32 {
	return volatile.LoadUint32(&o.OP1_TSTMP_E1.Reg) & 0xffff
}

// MCPWM.OP1_TSTMP_E2: Generator%s timer stamp E2 value register
func (o *MCPWM_Type) SetOP1_TSTMP_E2_OP_TSTMP_E2(value uint32) {
	volatile.StoreUint32(&o.OP1_TSTMP_E2.Reg, volatile.LoadUint32(&o.OP1_TSTMP_E2.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetOP1_TSTMP_E2_OP_TSTMP_E2() uint32 {
	return volatile.LoadUint32(&o.OP1_TSTMP_E2.Reg) & 0xffff
}

// MCPWM.OP2_TSTMP_E1: Generator%s timer stamp E1 value register
func (o *MCPWM_Type) SetOP2_TSTMP_E1_OP_TSTMP_E1(value uint32) {
	volatile.StoreUint32(&o.OP2_TSTMP_E1.Reg, volatile.LoadUint32(&o.OP2_TSTMP_E1.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetOP2_TSTMP_E1_OP_TSTMP_E1() uint32 {
	return volatile.LoadUint32(&o.OP2_TSTMP_E1.Reg) & 0xffff
}

// MCPWM.OP2_TSTMP_E2: Generator%s timer stamp E2 value register
func (o *MCPWM_Type) SetOP2_TSTMP_E2_OP_TSTMP_E2(value uint32) {
	volatile.StoreUint32(&o.OP2_TSTMP_E2.Reg, volatile.LoadUint32(&o.OP2_TSTMP_E2.Reg)&^(0xffff)|value)
}
func (o *MCPWM_Type) GetOP2_TSTMP_E2_OP_TSTMP_E2() uint32 {
	return volatile.LoadUint32(&o.OP2_TSTMP_E2.Reg) & 0xffff
}

// MCPWM.CLK: Global configuration register
func (o *MCPWM_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x1)|value)
}
func (o *MCPWM_Type) GetCLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK.Reg) & 0x1
}

// MCPWM.VERSION: Version register.
func (o *MCPWM_Type) SetVERSION_DATE(value uint32) {
	volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value)
}
func (o *MCPWM_Type) GetVERSION_DATE() uint32 {
	return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff
}

// Parallel IO Controller
type PARL_IO_Type struct {
	RX_MODE_CFG  volatile.Register32 // 0x0
	RX_DATA_CFG  volatile.Register32 // 0x4
	RX_GENRL_CFG volatile.Register32 // 0x8
	RX_START_CFG volatile.Register32 // 0xC
	TX_DATA_CFG  volatile.Register32 // 0x10
	TX_START_CFG volatile.Register32 // 0x14
	TX_GENRL_CFG volatile.Register32 // 0x18
	FIFO_CFG     volatile.Register32 // 0x1C
	REG_UPDATE   volatile.Register32 // 0x20
	ST           volatile.Register32 // 0x24
	INT_ENA      volatile.Register32 // 0x28
	INT_RAW      volatile.Register32 // 0x2C
	INT_ST       volatile.Register32 // 0x30
	INT_CLR      volatile.Register32 // 0x34
	RX_ST0       volatile.Register32 // 0x38
	RX_ST1       volatile.Register32 // 0x3C
	TX_ST0       volatile.Register32 // 0x40
	RX_CLK_CFG   volatile.Register32 // 0x44
	TX_CLK_CFG   volatile.Register32 // 0x48
	_            [212]byte
	CLK          volatile.Register32 // 0x120
	_            [728]byte
	VERSION      volatile.Register32 // 0x3FC
}

// PARL_IO.RX_MODE_CFG: Parallel RX Sampling mode configuration register.
func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_EXT_EN_SEL(value uint32) {
	volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x1e00000)|value<<21)
}
func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_EXT_EN_SEL() uint32 {
	return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x1e00000) >> 21
}
func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_SW_EN(value uint32) {
	volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x2000000)|value<<25)
}
func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_SW_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x2000000) >> 25
}
func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_EXT_EN_INV(value uint32) {
	volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x4000000)|value<<26)
}
func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_EXT_EN_INV() uint32 {
	return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x4000000) >> 26
}
func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_PULSE_SUBMODE_SEL(value uint32) {
	volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0x38000000)|value<<27)
}
func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_PULSE_SUBMODE_SEL() uint32 {
	return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0x38000000) >> 27
}
func (o *PARL_IO_Type) SetRX_MODE_CFG_RX_SMP_MODE_SEL(value uint32) {
	volatile.StoreUint32(&o.RX_MODE_CFG.Reg, volatile.LoadUint32(&o.RX_MODE_CFG.Reg)&^(0xc0000000)|value<<30)
}
func (o *PARL_IO_Type) GetRX_MODE_CFG_RX_SMP_MODE_SEL() uint32 {
	return (volatile.LoadUint32(&o.RX_MODE_CFG.Reg) & 0xc0000000) >> 30
}

// PARL_IO.RX_DATA_CFG: Parallel RX data configuration register.
func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_BITLEN(value uint32) {
	volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0xffffe00)|value<<9)
}
func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0xffffe00) >> 9
}
func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_DATA_ORDER_INV(value uint32) {
	volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0x10000000)|value<<28)
}
func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_DATA_ORDER_INV() uint32 {
	return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0x10000000) >> 28
}
func (o *PARL_IO_Type) SetRX_DATA_CFG_RX_BUS_WID_SEL(value uint32) {
	volatile.StoreUint32(&o.RX_DATA_CFG.Reg, volatile.LoadUint32(&o.RX_DATA_CFG.Reg)&^(0xe0000000)|value<<29)
}
func (o *PARL_IO_Type) GetRX_DATA_CFG_RX_BUS_WID_SEL() uint32 {
	return (volatile.LoadUint32(&o.RX_DATA_CFG.Reg) & 0xe0000000) >> 29
}

// PARL_IO.RX_GENRL_CFG: Parallel RX general configuration register.
func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_GATING_EN(value uint32) {
	volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x1000)|value<<12)
}
func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_GATING_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x1000) >> 12
}
func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x1fffe000)|value<<13)
}
func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x1fffe000) >> 13
}
func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_TIMEOUT_EN(value uint32) {
	volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x20000000)|value<<29)
}
func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_TIMEOUT_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x20000000) >> 29
}
func (o *PARL_IO_Type) SetRX_GENRL_CFG_RX_EOF_GEN_SEL(value uint32) {
	volatile.StoreUint32(&o.RX_GENRL_CFG.Reg, volatile.LoadUint32(&o.RX_GENRL_CFG.Reg)&^(0x40000000)|value<<30)
}
func (o *PARL_IO_Type) GetRX_GENRL_CFG_RX_EOF_GEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.RX_GENRL_CFG.Reg) & 0x40000000) >> 30
}

// PARL_IO.RX_START_CFG: Parallel RX Start configuration register.
func (o *PARL_IO_Type) SetRX_START_CFG_RX_START(value uint32) {
	volatile.StoreUint32(&o.RX_START_CFG.Reg, volatile.LoadUint32(&o.RX_START_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetRX_START_CFG_RX_START() uint32 {
	return (volatile.LoadUint32(&o.RX_START_CFG.Reg) & 0x80000000) >> 31
}

// PARL_IO.TX_DATA_CFG: Parallel TX data configuration register.
func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_BITLEN(value uint32) {
	volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0xffffe00)|value<<9)
}
func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0xffffe00) >> 9
}
func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_DATA_ORDER_INV(value uint32) {
	volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0x10000000)|value<<28)
}
func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_DATA_ORDER_INV() uint32 {
	return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0x10000000) >> 28
}
func (o *PARL_IO_Type) SetTX_DATA_CFG_TX_BUS_WID_SEL(value uint32) {
	volatile.StoreUint32(&o.TX_DATA_CFG.Reg, volatile.LoadUint32(&o.TX_DATA_CFG.Reg)&^(0xe0000000)|value<<29)
}
func (o *PARL_IO_Type) GetTX_DATA_CFG_TX_BUS_WID_SEL() uint32 {
	return (volatile.LoadUint32(&o.TX_DATA_CFG.Reg) & 0xe0000000) >> 29
}

// PARL_IO.TX_START_CFG: Parallel TX Start configuration register.
func (o *PARL_IO_Type) SetTX_START_CFG_TX_START(value uint32) {
	volatile.StoreUint32(&o.TX_START_CFG.Reg, volatile.LoadUint32(&o.TX_START_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetTX_START_CFG_TX_START() uint32 {
	return (volatile.LoadUint32(&o.TX_START_CFG.Reg) & 0x80000000) >> 31
}

// PARL_IO.TX_GENRL_CFG: Parallel TX general configuration register.
func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_EOF_GEN_SEL(value uint32) {
	volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x2000)|value<<13)
}
func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_EOF_GEN_SEL() uint32 {
	return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x2000) >> 13
}
func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_IDLE_VALUE(value uint32) {
	volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x3fffc000)|value<<14)
}
func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_IDLE_VALUE() uint32 {
	return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x3fffc000) >> 14
}
func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_GATING_EN(value uint32) {
	volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x40000000)|value<<30)
}
func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_GATING_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x40000000) >> 30
}
func (o *PARL_IO_Type) SetTX_GENRL_CFG_TX_VALID_OUTPUT_EN(value uint32) {
	volatile.StoreUint32(&o.TX_GENRL_CFG.Reg, volatile.LoadUint32(&o.TX_GENRL_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetTX_GENRL_CFG_TX_VALID_OUTPUT_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_GENRL_CFG.Reg) & 0x80000000) >> 31
}

// PARL_IO.FIFO_CFG: Parallel IO FIFO configuration register.
func (o *PARL_IO_Type) SetFIFO_CFG_TX_FIFO_SRST(value uint32) {
	volatile.StoreUint32(&o.FIFO_CFG.Reg, volatile.LoadUint32(&o.FIFO_CFG.Reg)&^(0x40000000)|value<<30)
}
func (o *PARL_IO_Type) GetFIFO_CFG_TX_FIFO_SRST() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CFG.Reg) & 0x40000000) >> 30
}
func (o *PARL_IO_Type) SetFIFO_CFG_RX_FIFO_SRST(value uint32) {
	volatile.StoreUint32(&o.FIFO_CFG.Reg, volatile.LoadUint32(&o.FIFO_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetFIFO_CFG_RX_FIFO_SRST() uint32 {
	return (volatile.LoadUint32(&o.FIFO_CFG.Reg) & 0x80000000) >> 31
}

// PARL_IO.REG_UPDATE: Parallel IO FIFO configuration register.
func (o *PARL_IO_Type) SetREG_UPDATE_RX_REG_UPDATE(value uint32) {
	volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetREG_UPDATE_RX_REG_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x80000000) >> 31
}

// PARL_IO.ST: Parallel IO module status register0.
func (o *PARL_IO_Type) SetST_TX_READY(value uint32) {
	volatile.StoreUint32(&o.ST.Reg, volatile.LoadUint32(&o.ST.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetST_TX_READY() uint32 {
	return (volatile.LoadUint32(&o.ST.Reg) & 0x80000000) >> 31
}

// PARL_IO.INT_ENA: Parallel IO interrupt enable singal configuration register.
func (o *PARL_IO_Type) SetINT_ENA_TX_FIFO_REMPTY_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *PARL_IO_Type) GetINT_ENA_TX_FIFO_REMPTY_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *PARL_IO_Type) SetINT_ENA_RX_FIFO_WOVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *PARL_IO_Type) GetINT_ENA_RX_FIFO_WOVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *PARL_IO_Type) SetINT_ENA_TX_EOF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *PARL_IO_Type) GetINT_ENA_TX_EOF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}

// PARL_IO.INT_RAW: Parallel IO interrupt raw singal status register.
func (o *PARL_IO_Type) SetINT_RAW_TX_FIFO_REMPTY_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *PARL_IO_Type) GetINT_RAW_TX_FIFO_REMPTY_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *PARL_IO_Type) SetINT_RAW_RX_FIFO_WOVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *PARL_IO_Type) GetINT_RAW_RX_FIFO_WOVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *PARL_IO_Type) SetINT_RAW_TX_EOF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *PARL_IO_Type) GetINT_RAW_TX_EOF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}

// PARL_IO.INT_ST: Parallel IO interrupt singal status register.
func (o *PARL_IO_Type) SetINT_ST_TX_FIFO_REMPTY_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *PARL_IO_Type) GetINT_ST_TX_FIFO_REMPTY_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *PARL_IO_Type) SetINT_ST_RX_FIFO_WOVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *PARL_IO_Type) GetINT_ST_RX_FIFO_WOVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *PARL_IO_Type) SetINT_ST_TX_EOF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *PARL_IO_Type) GetINT_ST_TX_EOF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}

// PARL_IO.INT_CLR: Parallel IO interrupt clear singal configuration register.
func (o *PARL_IO_Type) SetINT_CLR_TX_FIFO_REMPTY_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *PARL_IO_Type) GetINT_CLR_TX_FIFO_REMPTY_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *PARL_IO_Type) SetINT_CLR_RX_FIFO_WOVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *PARL_IO_Type) GetINT_CLR_RX_FIFO_WOVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *PARL_IO_Type) SetINT_CLR_TX_EOF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *PARL_IO_Type) GetINT_CLR_TX_EOF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}

// PARL_IO.RX_ST0: Parallel IO RX status register0
func (o *PARL_IO_Type) SetRX_ST0_RX_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_ST0.Reg, volatile.LoadUint32(&o.RX_ST0.Reg)&^(0x1f00)|value<<8)
}
func (o *PARL_IO_Type) GetRX_ST0_RX_CNT() uint32 {
	return (volatile.LoadUint32(&o.RX_ST0.Reg) & 0x1f00) >> 8
}
func (o *PARL_IO_Type) SetRX_ST0_RX_FIFO_WR_BIT_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_ST0.Reg, volatile.LoadUint32(&o.RX_ST0.Reg)&^(0xffffe000)|value<<13)
}
func (o *PARL_IO_Type) GetRX_ST0_RX_FIFO_WR_BIT_CNT() uint32 {
	return (volatile.LoadUint32(&o.RX_ST0.Reg) & 0xffffe000) >> 13
}

// PARL_IO.RX_ST1: Parallel IO RX status register1
func (o *PARL_IO_Type) SetRX_ST1_RX_FIFO_RD_BIT_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_ST1.Reg, volatile.LoadUint32(&o.RX_ST1.Reg)&^(0xffffe000)|value<<13)
}
func (o *PARL_IO_Type) GetRX_ST1_RX_FIFO_RD_BIT_CNT() uint32 {
	return (volatile.LoadUint32(&o.RX_ST1.Reg) & 0xffffe000) >> 13
}

// PARL_IO.TX_ST0: Parallel IO TX status register0
func (o *PARL_IO_Type) SetTX_ST0_TX_CNT(value uint32) {
	volatile.StoreUint32(&o.TX_ST0.Reg, volatile.LoadUint32(&o.TX_ST0.Reg)&^(0x1fc0)|value<<6)
}
func (o *PARL_IO_Type) GetTX_ST0_TX_CNT() uint32 {
	return (volatile.LoadUint32(&o.TX_ST0.Reg) & 0x1fc0) >> 6
}
func (o *PARL_IO_Type) SetTX_ST0_TX_FIFO_RD_BIT_CNT(value uint32) {
	volatile.StoreUint32(&o.TX_ST0.Reg, volatile.LoadUint32(&o.TX_ST0.Reg)&^(0xffffe000)|value<<13)
}
func (o *PARL_IO_Type) GetTX_ST0_TX_FIFO_RD_BIT_CNT() uint32 {
	return (volatile.LoadUint32(&o.TX_ST0.Reg) & 0xffffe000) >> 13
}

// PARL_IO.RX_CLK_CFG: Parallel IO RX clk configuration register
func (o *PARL_IO_Type) SetRX_CLK_CFG_RX_CLK_I_INV(value uint32) {
	volatile.StoreUint32(&o.RX_CLK_CFG.Reg, volatile.LoadUint32(&o.RX_CLK_CFG.Reg)&^(0x40000000)|value<<30)
}
func (o *PARL_IO_Type) GetRX_CLK_CFG_RX_CLK_I_INV() uint32 {
	return (volatile.LoadUint32(&o.RX_CLK_CFG.Reg) & 0x40000000) >> 30
}
func (o *PARL_IO_Type) SetRX_CLK_CFG_RX_CLK_O_INV(value uint32) {
	volatile.StoreUint32(&o.RX_CLK_CFG.Reg, volatile.LoadUint32(&o.RX_CLK_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetRX_CLK_CFG_RX_CLK_O_INV() uint32 {
	return (volatile.LoadUint32(&o.RX_CLK_CFG.Reg) & 0x80000000) >> 31
}

// PARL_IO.TX_CLK_CFG: Parallel IO TX clk configuration register
func (o *PARL_IO_Type) SetTX_CLK_CFG_TX_CLK_I_INV(value uint32) {
	volatile.StoreUint32(&o.TX_CLK_CFG.Reg, volatile.LoadUint32(&o.TX_CLK_CFG.Reg)&^(0x40000000)|value<<30)
}
func (o *PARL_IO_Type) GetTX_CLK_CFG_TX_CLK_I_INV() uint32 {
	return (volatile.LoadUint32(&o.TX_CLK_CFG.Reg) & 0x40000000) >> 30
}
func (o *PARL_IO_Type) SetTX_CLK_CFG_TX_CLK_O_INV(value uint32) {
	volatile.StoreUint32(&o.TX_CLK_CFG.Reg, volatile.LoadUint32(&o.TX_CLK_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetTX_CLK_CFG_TX_CLK_O_INV() uint32 {
	return (volatile.LoadUint32(&o.TX_CLK_CFG.Reg) & 0x80000000) >> 31
}

// PARL_IO.CLK: Parallel IO clk configuration register
func (o *PARL_IO_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK.Reg, volatile.LoadUint32(&o.CLK.Reg)&^(0x80000000)|value<<31)
}
func (o *PARL_IO_Type) GetCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK.Reg) & 0x80000000) >> 31
}

// PARL_IO.VERSION: Version register.
func (o *PARL_IO_Type) SetVERSION_DATE(value uint32) {
	volatile.StoreUint32(&o.VERSION.Reg, volatile.LoadUint32(&o.VERSION.Reg)&^(0xfffffff)|value)
}
func (o *PARL_IO_Type) GetVERSION_DATE() uint32 {
	return volatile.LoadUint32(&o.VERSION.Reg) & 0xfffffff
}

// PAU Peripheral
type PAU_Type struct {
	REGDMA_CONF              volatile.Register32 // 0x0
	REGDMA_CLK_CONF          volatile.Register32 // 0x4
	REGDMA_ETM_CTRL          volatile.Register32 // 0x8
	REGDMA_LINK_0_ADDR       volatile.Register32 // 0xC
	REGDMA_LINK_1_ADDR       volatile.Register32 // 0x10
	REGDMA_LINK_2_ADDR       volatile.Register32 // 0x14
	REGDMA_LINK_3_ADDR       volatile.Register32 // 0x18
	REGDMA_LINK_MAC_ADDR     volatile.Register32 // 0x1C
	REGDMA_CURRENT_LINK_ADDR volatile.Register32 // 0x20
	REGDMA_BACKUP_ADDR       volatile.Register32 // 0x24
	REGDMA_MEM_ADDR          volatile.Register32 // 0x28
	REGDMA_BKP_CONF          volatile.Register32 // 0x2C
	INT_ENA                  volatile.Register32 // 0x30
	INT_RAW                  volatile.Register32 // 0x34
	INT_CLR                  volatile.Register32 // 0x38
	INT_ST                   volatile.Register32 // 0x3C
	_                        [956]byte
	DATE                     volatile.Register32 // 0x3FC
}

// PAU.REGDMA_CONF: Peri backup control register
func (o *PAU_Type) SetREGDMA_CONF_FLOW_ERR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x7)|value)
}
func (o *PAU_Type) GetREGDMA_CONF_FLOW_ERR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x7
}
func (o *PAU_Type) SetREGDMA_CONF_START(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x8)|value<<3)
}
func (o *PAU_Type) GetREGDMA_CONF_START() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x8) >> 3
}
func (o *PAU_Type) SetREGDMA_CONF_TO_MEM(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x10)|value<<4)
}
func (o *PAU_Type) GetREGDMA_CONF_TO_MEM() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x10) >> 4
}
func (o *PAU_Type) SetREGDMA_CONF_LINK_SEL(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x60)|value<<5)
}
func (o *PAU_Type) GetREGDMA_CONF_LINK_SEL() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x60) >> 5
}
func (o *PAU_Type) SetREGDMA_CONF_START_MAC(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x80)|value<<7)
}
func (o *PAU_Type) GetREGDMA_CONF_START_MAC() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x80) >> 7
}
func (o *PAU_Type) SetREGDMA_CONF_TO_MEM_MAC(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x100)|value<<8)
}
func (o *PAU_Type) GetREGDMA_CONF_TO_MEM_MAC() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x100) >> 8
}
func (o *PAU_Type) SetREGDMA_CONF_SEL_MAC(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CONF.Reg)&^(0x200)|value<<9)
}
func (o *PAU_Type) GetREGDMA_CONF_SEL_MAC() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_CONF.Reg) & 0x200) >> 9
}

// PAU.REGDMA_CLK_CONF: Clock control register
func (o *PAU_Type) SetREGDMA_CLK_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CLK_CONF.Reg, volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg)&^(0x1)|value)
}
func (o *PAU_Type) GetREGDMA_CLK_CONF_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.REGDMA_CLK_CONF.Reg) & 0x1
}

// PAU.REGDMA_ETM_CTRL: ETM start ctrl reg
func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_0(value uint32) {
	volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x1)|value)
}
func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_0() uint32 {
	return volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x1
}
func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_1(value uint32) {
	volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_1() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x2) >> 1
}
func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_2(value uint32) {
	volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_2() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x4) >> 2
}
func (o *PAU_Type) SetREGDMA_ETM_CTRL_ETM_START_3(value uint32) {
	volatile.StoreUint32(&o.REGDMA_ETM_CTRL.Reg, volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *PAU_Type) GetREGDMA_ETM_CTRL_ETM_START_3() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_ETM_CTRL.Reg) & 0x8) >> 3
}

// PAU.REGDMA_LINK_0_ADDR: link_0_addr
func (o *PAU_Type) SetREGDMA_LINK_0_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_LINK_0_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_LINK_0_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_LINK_0_ADDR.Reg)
}

// PAU.REGDMA_LINK_1_ADDR: Link_1_addr
func (o *PAU_Type) SetREGDMA_LINK_1_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_LINK_1_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_LINK_1_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_LINK_1_ADDR.Reg)
}

// PAU.REGDMA_LINK_2_ADDR: Link_2_addr
func (o *PAU_Type) SetREGDMA_LINK_2_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_LINK_2_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_LINK_2_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_LINK_2_ADDR.Reg)
}

// PAU.REGDMA_LINK_3_ADDR: Link_3_addr
func (o *PAU_Type) SetREGDMA_LINK_3_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_LINK_3_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_LINK_3_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_LINK_3_ADDR.Reg)
}

// PAU.REGDMA_LINK_MAC_ADDR: Link_mac_addr
func (o *PAU_Type) SetREGDMA_LINK_MAC_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_LINK_MAC_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_LINK_MAC_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_LINK_MAC_ADDR.Reg)
}

// PAU.REGDMA_CURRENT_LINK_ADDR: current link addr
func (o *PAU_Type) SetREGDMA_CURRENT_LINK_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_CURRENT_LINK_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_CURRENT_LINK_ADDR.Reg)
}

// PAU.REGDMA_BACKUP_ADDR: Backup addr
func (o *PAU_Type) SetREGDMA_BACKUP_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_BACKUP_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_BACKUP_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_BACKUP_ADDR.Reg)
}

// PAU.REGDMA_MEM_ADDR: mem addr
func (o *PAU_Type) SetREGDMA_MEM_ADDR(value uint32) {
	volatile.StoreUint32(&o.REGDMA_MEM_ADDR.Reg, value)
}
func (o *PAU_Type) GetREGDMA_MEM_ADDR() uint32 {
	return volatile.LoadUint32(&o.REGDMA_MEM_ADDR.Reg)
}

// PAU.REGDMA_BKP_CONF: backup config
func (o *PAU_Type) SetREGDMA_BKP_CONF_READ_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x7f)|value)
}
func (o *PAU_Type) GetREGDMA_BKP_CONF_READ_INTERVAL() uint32 {
	return volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x7f
}
func (o *PAU_Type) SetREGDMA_BKP_CONF_LINK_TOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x1ff80)|value<<7)
}
func (o *PAU_Type) GetREGDMA_BKP_CONF_LINK_TOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x1ff80) >> 7
}
func (o *PAU_Type) SetREGDMA_BKP_CONF_BURST_LIMIT(value uint32) {
	volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0x3e0000)|value<<17)
}
func (o *PAU_Type) GetREGDMA_BKP_CONF_BURST_LIMIT() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0x3e0000) >> 17
}
func (o *PAU_Type) SetREGDMA_BKP_CONF_BACKUP_TOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.REGDMA_BKP_CONF.Reg, volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg)&^(0xffc00000)|value<<22)
}
func (o *PAU_Type) GetREGDMA_BKP_CONF_BACKUP_TOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.REGDMA_BKP_CONF.Reg) & 0xffc00000) >> 22
}

// PAU.INT_ENA: Read only register for error and done
func (o *PAU_Type) SetINT_ENA_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *PAU_Type) GetINT_ENA_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *PAU_Type) SetINT_ENA_ERROR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *PAU_Type) GetINT_ENA_ERROR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}

// PAU.INT_RAW: Read only register for error and done
func (o *PAU_Type) SetINT_RAW_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *PAU_Type) GetINT_RAW_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *PAU_Type) SetINT_RAW_ERROR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *PAU_Type) GetINT_RAW_ERROR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}

// PAU.INT_CLR: Read only register for error and done
func (o *PAU_Type) SetINT_CLR_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *PAU_Type) GetINT_CLR_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *PAU_Type) SetINT_CLR_ERROR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *PAU_Type) GetINT_CLR_ERROR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}

// PAU.INT_ST: Read only register for error and done
func (o *PAU_Type) SetINT_ST_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *PAU_Type) GetINT_ST_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *PAU_Type) SetINT_ST_ERROR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *PAU_Type) GetINT_ST_ERROR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}

// PAU.DATE: Date register.
func (o *PAU_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *PAU_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// Pulse Count Controller
type PCNT_Type struct {
	U0_CONF0       volatile.Register32 // 0x0
	U0_CONF1       volatile.Register32 // 0x4
	U0_CONF2       volatile.Register32 // 0x8
	U1_CONF0       volatile.Register32 // 0xC
	U1_CONF1       volatile.Register32 // 0x10
	U1_CONF2       volatile.Register32 // 0x14
	U2_CONF0       volatile.Register32 // 0x18
	U2_CONF1       volatile.Register32 // 0x1C
	U2_CONF2       volatile.Register32 // 0x20
	U3_CONF0       volatile.Register32 // 0x24
	U3_CONF1       volatile.Register32 // 0x28
	U3_CONF2       volatile.Register32 // 0x2C
	U0_CNT         volatile.Register32 // 0x30
	U1_CNT         volatile.Register32 // 0x34
	U2_CNT         volatile.Register32 // 0x38
	U3_CNT         volatile.Register32 // 0x3C
	INT_RAW        volatile.Register32 // 0x40
	INT_ST         volatile.Register32 // 0x44
	INT_ENA        volatile.Register32 // 0x48
	INT_CLR        volatile.Register32 // 0x4C
	U0_STATUS      volatile.Register32 // 0x50
	U1_STATUS      volatile.Register32 // 0x54
	U2_STATUS      volatile.Register32 // 0x58
	U3_STATUS      volatile.Register32 // 0x5C
	CTRL           volatile.Register32 // 0x60
	U3_CHANGE_CONF volatile.Register32 // 0x64
	U2_CHANGE_CONF volatile.Register32 // 0x68
	U1_CHANGE_CONF volatile.Register32 // 0x6C
	U0_CHANGE_CONF volatile.Register32 // 0x70
	_              [136]byte
	DATE           volatile.Register32 // 0xFC
}

// PCNT.U0_CONF0: Configuration register 0 for unit %s
func (o *PCNT_Type) SetU0_CONF0_FILTER_THRES_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3ff)|value)
}
func (o *PCNT_Type) GetU0_CONF0_FILTER_THRES_U() uint32 {
	return volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3ff
}
func (o *PCNT_Type) SetU0_CONF0_FILTER_EN_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x400)|value<<10)
}
func (o *PCNT_Type) GetU0_CONF0_FILTER_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x400) >> 10
}
func (o *PCNT_Type) SetU0_CONF0_THR_ZERO_EN_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x800)|value<<11)
}
func (o *PCNT_Type) GetU0_CONF0_THR_ZERO_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x800) >> 11
}
func (o *PCNT_Type) SetU0_CONF0_THR_H_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x1000)|value<<12)
}
func (o *PCNT_Type) GetU0_CONF0_THR_H_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x1000) >> 12
}
func (o *PCNT_Type) SetU0_CONF0_THR_L_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x2000)|value<<13)
}
func (o *PCNT_Type) GetU0_CONF0_THR_L_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x2000) >> 13
}
func (o *PCNT_Type) SetU0_CONF0_THR_THRES0_EN_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x4000)|value<<14)
}
func (o *PCNT_Type) GetU0_CONF0_THR_THRES0_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x4000) >> 14
}
func (o *PCNT_Type) SetU0_CONF0_THR_THRES1_EN_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *PCNT_Type) GetU0_CONF0_THR_THRES1_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x8000) >> 15
}
func (o *PCNT_Type) SetU0_CONF0_CH0_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000)|value<<16)
}
func (o *PCNT_Type) GetU0_CONF0_CH0_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000) >> 16
}
func (o *PCNT_Type) SetU0_CONF0_CH0_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000)|value<<18)
}
func (o *PCNT_Type) GetU0_CONF0_CH0_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000) >> 18
}
func (o *PCNT_Type) SetU0_CONF0_CH0_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x300000)|value<<20)
}
func (o *PCNT_Type) GetU0_CONF0_CH0_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x300000) >> 20
}
func (o *PCNT_Type) SetU0_CONF0_CH0_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc00000)|value<<22)
}
func (o *PCNT_Type) GetU0_CONF0_CH0_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc00000) >> 22
}
func (o *PCNT_Type) SetU0_CONF0_CH1_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x3000000)|value<<24)
}
func (o *PCNT_Type) GetU0_CONF0_CH1_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x3000000) >> 24
}
func (o *PCNT_Type) SetU0_CONF0_CH1_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc000000)|value<<26)
}
func (o *PCNT_Type) GetU0_CONF0_CH1_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc000000) >> 26
}
func (o *PCNT_Type) SetU0_CONF0_CH1_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0x30000000)|value<<28)
}
func (o *PCNT_Type) GetU0_CONF0_CH1_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0x30000000) >> 28
}
func (o *PCNT_Type) SetU0_CONF0_CH1_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF0.Reg, volatile.LoadUint32(&o.U0_CONF0.Reg)&^(0xc0000000)|value<<30)
}
func (o *PCNT_Type) GetU0_CONF0_CH1_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF0.Reg) & 0xc0000000) >> 30
}

// PCNT.U0_CONF1: Configuration register 1 for unit %s
func (o *PCNT_Type) SetU0_CONF1_CNT_THRES0_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU0_CONF1_CNT_THRES0_U() uint32 {
	return volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff
}
func (o *PCNT_Type) SetU0_CONF1_CNT_THRES1_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF1.Reg, volatile.LoadUint32(&o.U0_CONF1.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU0_CONF1_CNT_THRES1_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF1.Reg) & 0xffff0000) >> 16
}

// PCNT.U0_CONF2: Configuration register 2 for unit %s
func (o *PCNT_Type) SetU0_CONF2_CNT_H_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU0_CONF2_CNT_H_LIM_U() uint32 {
	return volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff
}
func (o *PCNT_Type) SetU0_CONF2_CNT_L_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U0_CONF2.Reg, volatile.LoadUint32(&o.U0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU0_CONF2_CNT_L_LIM_U() uint32 {
	return (volatile.LoadUint32(&o.U0_CONF2.Reg) & 0xffff0000) >> 16
}

// PCNT.U1_CONF0: Configuration register 0 for unit %s
func (o *PCNT_Type) SetU1_CONF0_FILTER_THRES_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3ff)|value)
}
func (o *PCNT_Type) GetU1_CONF0_FILTER_THRES_U() uint32 {
	return volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3ff
}
func (o *PCNT_Type) SetU1_CONF0_FILTER_EN_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x400)|value<<10)
}
func (o *PCNT_Type) GetU1_CONF0_FILTER_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x400) >> 10
}
func (o *PCNT_Type) SetU1_CONF0_THR_ZERO_EN_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x800)|value<<11)
}
func (o *PCNT_Type) GetU1_CONF0_THR_ZERO_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x800) >> 11
}
func (o *PCNT_Type) SetU1_CONF0_THR_H_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x1000)|value<<12)
}
func (o *PCNT_Type) GetU1_CONF0_THR_H_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x1000) >> 12
}
func (o *PCNT_Type) SetU1_CONF0_THR_L_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x2000)|value<<13)
}
func (o *PCNT_Type) GetU1_CONF0_THR_L_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x2000) >> 13
}
func (o *PCNT_Type) SetU1_CONF0_THR_THRES0_EN_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x4000)|value<<14)
}
func (o *PCNT_Type) GetU1_CONF0_THR_THRES0_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x4000) >> 14
}
func (o *PCNT_Type) SetU1_CONF0_THR_THRES1_EN_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *PCNT_Type) GetU1_CONF0_THR_THRES1_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x8000) >> 15
}
func (o *PCNT_Type) SetU1_CONF0_CH0_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000)|value<<16)
}
func (o *PCNT_Type) GetU1_CONF0_CH0_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000) >> 16
}
func (o *PCNT_Type) SetU1_CONF0_CH0_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000)|value<<18)
}
func (o *PCNT_Type) GetU1_CONF0_CH0_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000) >> 18
}
func (o *PCNT_Type) SetU1_CONF0_CH0_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x300000)|value<<20)
}
func (o *PCNT_Type) GetU1_CONF0_CH0_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x300000) >> 20
}
func (o *PCNT_Type) SetU1_CONF0_CH0_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc00000)|value<<22)
}
func (o *PCNT_Type) GetU1_CONF0_CH0_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc00000) >> 22
}
func (o *PCNT_Type) SetU1_CONF0_CH1_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x3000000)|value<<24)
}
func (o *PCNT_Type) GetU1_CONF0_CH1_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x3000000) >> 24
}
func (o *PCNT_Type) SetU1_CONF0_CH1_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc000000)|value<<26)
}
func (o *PCNT_Type) GetU1_CONF0_CH1_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc000000) >> 26
}
func (o *PCNT_Type) SetU1_CONF0_CH1_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0x30000000)|value<<28)
}
func (o *PCNT_Type) GetU1_CONF0_CH1_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0x30000000) >> 28
}
func (o *PCNT_Type) SetU1_CONF0_CH1_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF0.Reg, volatile.LoadUint32(&o.U1_CONF0.Reg)&^(0xc0000000)|value<<30)
}
func (o *PCNT_Type) GetU1_CONF0_CH1_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF0.Reg) & 0xc0000000) >> 30
}

// PCNT.U1_CONF1: Configuration register 1 for unit %s
func (o *PCNT_Type) SetU1_CONF1_CNT_THRES0_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU1_CONF1_CNT_THRES0_U() uint32 {
	return volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff
}
func (o *PCNT_Type) SetU1_CONF1_CNT_THRES1_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF1.Reg, volatile.LoadUint32(&o.U1_CONF1.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU1_CONF1_CNT_THRES1_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF1.Reg) & 0xffff0000) >> 16
}

// PCNT.U1_CONF2: Configuration register 2 for unit %s
func (o *PCNT_Type) SetU1_CONF2_CNT_H_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU1_CONF2_CNT_H_LIM_U() uint32 {
	return volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff
}
func (o *PCNT_Type) SetU1_CONF2_CNT_L_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U1_CONF2.Reg, volatile.LoadUint32(&o.U1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU1_CONF2_CNT_L_LIM_U() uint32 {
	return (volatile.LoadUint32(&o.U1_CONF2.Reg) & 0xffff0000) >> 16
}

// PCNT.U2_CONF0: Configuration register 0 for unit %s
func (o *PCNT_Type) SetU2_CONF0_FILTER_THRES_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3ff)|value)
}
func (o *PCNT_Type) GetU2_CONF0_FILTER_THRES_U() uint32 {
	return volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3ff
}
func (o *PCNT_Type) SetU2_CONF0_FILTER_EN_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x400)|value<<10)
}
func (o *PCNT_Type) GetU2_CONF0_FILTER_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x400) >> 10
}
func (o *PCNT_Type) SetU2_CONF0_THR_ZERO_EN_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x800)|value<<11)
}
func (o *PCNT_Type) GetU2_CONF0_THR_ZERO_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x800) >> 11
}
func (o *PCNT_Type) SetU2_CONF0_THR_H_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x1000)|value<<12)
}
func (o *PCNT_Type) GetU2_CONF0_THR_H_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x1000) >> 12
}
func (o *PCNT_Type) SetU2_CONF0_THR_L_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x2000)|value<<13)
}
func (o *PCNT_Type) GetU2_CONF0_THR_L_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x2000) >> 13
}
func (o *PCNT_Type) SetU2_CONF0_THR_THRES0_EN_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x4000)|value<<14)
}
func (o *PCNT_Type) GetU2_CONF0_THR_THRES0_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x4000) >> 14
}
func (o *PCNT_Type) SetU2_CONF0_THR_THRES1_EN_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *PCNT_Type) GetU2_CONF0_THR_THRES1_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x8000) >> 15
}
func (o *PCNT_Type) SetU2_CONF0_CH0_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000)|value<<16)
}
func (o *PCNT_Type) GetU2_CONF0_CH0_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000) >> 16
}
func (o *PCNT_Type) SetU2_CONF0_CH0_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000)|value<<18)
}
func (o *PCNT_Type) GetU2_CONF0_CH0_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000) >> 18
}
func (o *PCNT_Type) SetU2_CONF0_CH0_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x300000)|value<<20)
}
func (o *PCNT_Type) GetU2_CONF0_CH0_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x300000) >> 20
}
func (o *PCNT_Type) SetU2_CONF0_CH0_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc00000)|value<<22)
}
func (o *PCNT_Type) GetU2_CONF0_CH0_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc00000) >> 22
}
func (o *PCNT_Type) SetU2_CONF0_CH1_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x3000000)|value<<24)
}
func (o *PCNT_Type) GetU2_CONF0_CH1_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x3000000) >> 24
}
func (o *PCNT_Type) SetU2_CONF0_CH1_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc000000)|value<<26)
}
func (o *PCNT_Type) GetU2_CONF0_CH1_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc000000) >> 26
}
func (o *PCNT_Type) SetU2_CONF0_CH1_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0x30000000)|value<<28)
}
func (o *PCNT_Type) GetU2_CONF0_CH1_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0x30000000) >> 28
}
func (o *PCNT_Type) SetU2_CONF0_CH1_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF0.Reg, volatile.LoadUint32(&o.U2_CONF0.Reg)&^(0xc0000000)|value<<30)
}
func (o *PCNT_Type) GetU2_CONF0_CH1_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF0.Reg) & 0xc0000000) >> 30
}

// PCNT.U2_CONF1: Configuration register 1 for unit %s
func (o *PCNT_Type) SetU2_CONF1_CNT_THRES0_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU2_CONF1_CNT_THRES0_U() uint32 {
	return volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff
}
func (o *PCNT_Type) SetU2_CONF1_CNT_THRES1_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF1.Reg, volatile.LoadUint32(&o.U2_CONF1.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU2_CONF1_CNT_THRES1_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF1.Reg) & 0xffff0000) >> 16
}

// PCNT.U2_CONF2: Configuration register 2 for unit %s
func (o *PCNT_Type) SetU2_CONF2_CNT_H_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU2_CONF2_CNT_H_LIM_U() uint32 {
	return volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff
}
func (o *PCNT_Type) SetU2_CONF2_CNT_L_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U2_CONF2.Reg, volatile.LoadUint32(&o.U2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU2_CONF2_CNT_L_LIM_U() uint32 {
	return (volatile.LoadUint32(&o.U2_CONF2.Reg) & 0xffff0000) >> 16
}

// PCNT.U3_CONF0: Configuration register 0 for unit %s
func (o *PCNT_Type) SetU3_CONF0_FILTER_THRES_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3ff)|value)
}
func (o *PCNT_Type) GetU3_CONF0_FILTER_THRES_U() uint32 {
	return volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3ff
}
func (o *PCNT_Type) SetU3_CONF0_FILTER_EN_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x400)|value<<10)
}
func (o *PCNT_Type) GetU3_CONF0_FILTER_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x400) >> 10
}
func (o *PCNT_Type) SetU3_CONF0_THR_ZERO_EN_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x800)|value<<11)
}
func (o *PCNT_Type) GetU3_CONF0_THR_ZERO_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x800) >> 11
}
func (o *PCNT_Type) SetU3_CONF0_THR_H_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x1000)|value<<12)
}
func (o *PCNT_Type) GetU3_CONF0_THR_H_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x1000) >> 12
}
func (o *PCNT_Type) SetU3_CONF0_THR_L_LIM_EN_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x2000)|value<<13)
}
func (o *PCNT_Type) GetU3_CONF0_THR_L_LIM_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x2000) >> 13
}
func (o *PCNT_Type) SetU3_CONF0_THR_THRES0_EN_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x4000)|value<<14)
}
func (o *PCNT_Type) GetU3_CONF0_THR_THRES0_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x4000) >> 14
}
func (o *PCNT_Type) SetU3_CONF0_THR_THRES1_EN_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *PCNT_Type) GetU3_CONF0_THR_THRES1_EN_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x8000) >> 15
}
func (o *PCNT_Type) SetU3_CONF0_CH0_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000)|value<<16)
}
func (o *PCNT_Type) GetU3_CONF0_CH0_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000) >> 16
}
func (o *PCNT_Type) SetU3_CONF0_CH0_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000)|value<<18)
}
func (o *PCNT_Type) GetU3_CONF0_CH0_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000) >> 18
}
func (o *PCNT_Type) SetU3_CONF0_CH0_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x300000)|value<<20)
}
func (o *PCNT_Type) GetU3_CONF0_CH0_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x300000) >> 20
}
func (o *PCNT_Type) SetU3_CONF0_CH0_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc00000)|value<<22)
}
func (o *PCNT_Type) GetU3_CONF0_CH0_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc00000) >> 22
}
func (o *PCNT_Type) SetU3_CONF0_CH1_NEG_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x3000000)|value<<24)
}
func (o *PCNT_Type) GetU3_CONF0_CH1_NEG_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x3000000) >> 24
}
func (o *PCNT_Type) SetU3_CONF0_CH1_POS_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc000000)|value<<26)
}
func (o *PCNT_Type) GetU3_CONF0_CH1_POS_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc000000) >> 26
}
func (o *PCNT_Type) SetU3_CONF0_CH1_HCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0x30000000)|value<<28)
}
func (o *PCNT_Type) GetU3_CONF0_CH1_HCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0x30000000) >> 28
}
func (o *PCNT_Type) SetU3_CONF0_CH1_LCTRL_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF0.Reg, volatile.LoadUint32(&o.U3_CONF0.Reg)&^(0xc0000000)|value<<30)
}
func (o *PCNT_Type) GetU3_CONF0_CH1_LCTRL_MODE_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF0.Reg) & 0xc0000000) >> 30
}

// PCNT.U3_CONF1: Configuration register 1 for unit %s
func (o *PCNT_Type) SetU3_CONF1_CNT_THRES0_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU3_CONF1_CNT_THRES0_U() uint32 {
	return volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff
}
func (o *PCNT_Type) SetU3_CONF1_CNT_THRES1_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF1.Reg, volatile.LoadUint32(&o.U3_CONF1.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU3_CONF1_CNT_THRES1_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF1.Reg) & 0xffff0000) >> 16
}

// PCNT.U3_CONF2: Configuration register 2 for unit %s
func (o *PCNT_Type) SetU3_CONF2_CNT_H_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU3_CONF2_CNT_H_LIM_U() uint32 {
	return volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff
}
func (o *PCNT_Type) SetU3_CONF2_CNT_L_LIM_U(value uint32) {
	volatile.StoreUint32(&o.U3_CONF2.Reg, volatile.LoadUint32(&o.U3_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU3_CONF2_CNT_L_LIM_U() uint32 {
	return (volatile.LoadUint32(&o.U3_CONF2.Reg) & 0xffff0000) >> 16
}

// PCNT.U0_CNT: Counter value for unit %s
func (o *PCNT_Type) SetU0_CNT_PULSE_CNT_U(value uint32) {
	volatile.StoreUint32(&o.U0_CNT.Reg, volatile.LoadUint32(&o.U0_CNT.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU0_CNT_PULSE_CNT_U() uint32 {
	return volatile.LoadUint32(&o.U0_CNT.Reg) & 0xffff
}

// PCNT.U1_CNT: Counter value for unit %s
func (o *PCNT_Type) SetU1_CNT_PULSE_CNT_U(value uint32) {
	volatile.StoreUint32(&o.U1_CNT.Reg, volatile.LoadUint32(&o.U1_CNT.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU1_CNT_PULSE_CNT_U() uint32 {
	return volatile.LoadUint32(&o.U1_CNT.Reg) & 0xffff
}

// PCNT.U2_CNT: Counter value for unit %s
func (o *PCNT_Type) SetU2_CNT_PULSE_CNT_U(value uint32) {
	volatile.StoreUint32(&o.U2_CNT.Reg, volatile.LoadUint32(&o.U2_CNT.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU2_CNT_PULSE_CNT_U() uint32 {
	return volatile.LoadUint32(&o.U2_CNT.Reg) & 0xffff
}

// PCNT.U3_CNT: Counter value for unit %s
func (o *PCNT_Type) SetU3_CNT_PULSE_CNT_U(value uint32) {
	volatile.StoreUint32(&o.U3_CNT.Reg, volatile.LoadUint32(&o.U3_CNT.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU3_CNT_PULSE_CNT_U() uint32 {
	return volatile.LoadUint32(&o.U3_CNT.Reg) & 0xffff
}

// PCNT.INT_RAW: Interrupt raw status register
func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U0_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetINT_RAW_CNT_THR_EVENT_U3_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetINT_RAW_CNT_THR_EVENT_U3_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}

// PCNT.INT_ST: Interrupt status register
func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U0_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetINT_ST_CNT_THR_EVENT_U3_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetINT_ST_CNT_THR_EVENT_U3_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}

// PCNT.INT_ENA: Interrupt enable register
func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U0_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetINT_ENA_CNT_THR_EVENT_U3_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetINT_ENA_CNT_THR_EVENT_U3_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}

// PCNT.INT_CLR: Interrupt clear register
func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U0_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetINT_CLR_CNT_THR_EVENT_U3_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetINT_CLR_CNT_THR_EVENT_U3_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}

// PCNT.U0_STATUS: PNCT UNIT%s status register
func (o *PCNT_Type) SetU0_STATUS_CNT_THR_ZERO_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x3)|value)
}
func (o *PCNT_Type) GetU0_STATUS_CNT_THR_ZERO_MODE_U() uint32 {
	return volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x3
}
func (o *PCNT_Type) SetU0_STATUS_CNT_THR_THRES1_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetU0_STATUS_CNT_THR_THRES1_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetU0_STATUS_CNT_THR_THRES0_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetU0_STATUS_CNT_THR_THRES0_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x8) >> 3
}
func (o *PCNT_Type) SetU0_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *PCNT_Type) GetU0_STATUS_CNT_THR_L_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x10) >> 4
}
func (o *PCNT_Type) SetU0_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *PCNT_Type) GetU0_STATUS_CNT_THR_H_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x20) >> 5
}
func (o *PCNT_Type) SetU0_STATUS_CNT_THR_ZERO_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U0_STATUS.Reg, volatile.LoadUint32(&o.U0_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *PCNT_Type) GetU0_STATUS_CNT_THR_ZERO_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U0_STATUS.Reg) & 0x40) >> 6
}

// PCNT.U1_STATUS: PNCT UNIT%s status register
func (o *PCNT_Type) SetU1_STATUS_CNT_THR_ZERO_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x3)|value)
}
func (o *PCNT_Type) GetU1_STATUS_CNT_THR_ZERO_MODE_U() uint32 {
	return volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x3
}
func (o *PCNT_Type) SetU1_STATUS_CNT_THR_THRES1_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetU1_STATUS_CNT_THR_THRES1_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetU1_STATUS_CNT_THR_THRES0_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetU1_STATUS_CNT_THR_THRES0_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x8) >> 3
}
func (o *PCNT_Type) SetU1_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *PCNT_Type) GetU1_STATUS_CNT_THR_L_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x10) >> 4
}
func (o *PCNT_Type) SetU1_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *PCNT_Type) GetU1_STATUS_CNT_THR_H_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x20) >> 5
}
func (o *PCNT_Type) SetU1_STATUS_CNT_THR_ZERO_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U1_STATUS.Reg, volatile.LoadUint32(&o.U1_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *PCNT_Type) GetU1_STATUS_CNT_THR_ZERO_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U1_STATUS.Reg) & 0x40) >> 6
}

// PCNT.U2_STATUS: PNCT UNIT%s status register
func (o *PCNT_Type) SetU2_STATUS_CNT_THR_ZERO_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x3)|value)
}
func (o *PCNT_Type) GetU2_STATUS_CNT_THR_ZERO_MODE_U() uint32 {
	return volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x3
}
func (o *PCNT_Type) SetU2_STATUS_CNT_THR_THRES1_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetU2_STATUS_CNT_THR_THRES1_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetU2_STATUS_CNT_THR_THRES0_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetU2_STATUS_CNT_THR_THRES0_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x8) >> 3
}
func (o *PCNT_Type) SetU2_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *PCNT_Type) GetU2_STATUS_CNT_THR_L_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x10) >> 4
}
func (o *PCNT_Type) SetU2_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *PCNT_Type) GetU2_STATUS_CNT_THR_H_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x20) >> 5
}
func (o *PCNT_Type) SetU2_STATUS_CNT_THR_ZERO_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U2_STATUS.Reg, volatile.LoadUint32(&o.U2_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *PCNT_Type) GetU2_STATUS_CNT_THR_ZERO_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U2_STATUS.Reg) & 0x40) >> 6
}

// PCNT.U3_STATUS: PNCT UNIT%s status register
func (o *PCNT_Type) SetU3_STATUS_CNT_THR_ZERO_MODE_U(value uint32) {
	volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x3)|value)
}
func (o *PCNT_Type) GetU3_STATUS_CNT_THR_ZERO_MODE_U() uint32 {
	return volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x3
}
func (o *PCNT_Type) SetU3_STATUS_CNT_THR_THRES1_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetU3_STATUS_CNT_THR_THRES1_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetU3_STATUS_CNT_THR_THRES0_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetU3_STATUS_CNT_THR_THRES0_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x8) >> 3
}
func (o *PCNT_Type) SetU3_STATUS_CNT_THR_L_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *PCNT_Type) GetU3_STATUS_CNT_THR_L_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x10) >> 4
}
func (o *PCNT_Type) SetU3_STATUS_CNT_THR_H_LIM_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *PCNT_Type) GetU3_STATUS_CNT_THR_H_LIM_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x20) >> 5
}
func (o *PCNT_Type) SetU3_STATUS_CNT_THR_ZERO_LAT_U(value uint32) {
	volatile.StoreUint32(&o.U3_STATUS.Reg, volatile.LoadUint32(&o.U3_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *PCNT_Type) GetU3_STATUS_CNT_THR_ZERO_LAT_U() uint32 {
	return (volatile.LoadUint32(&o.U3_STATUS.Reg) & 0x40) >> 6
}

// PCNT.CTRL: Control register for all counters
func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U0(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value)
}
func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U0() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0x1
}
func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U0(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1)
}
func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U0() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1
}
func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U1(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2)
}
func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U1() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2
}
func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U1(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x8)|value<<3)
}
func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U1() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x8) >> 3
}
func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U2(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4)
}
func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U2() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4
}
func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U2(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5)
}
func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U2() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5
}
func (o *PCNT_Type) SetCTRL_PULSE_CNT_RST_U3(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6)
}
func (o *PCNT_Type) GetCTRL_PULSE_CNT_RST_U3() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6
}
func (o *PCNT_Type) SetCTRL_CNT_PAUSE_U3(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7)
}
func (o *PCNT_Type) GetCTRL_CNT_PAUSE_U3() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7
}
func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U0(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8)
}
func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U0() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8
}
func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U1(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9)
}
func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U1() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9
}
func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U2(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10)
}
func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U2() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10
}
func (o *PCNT_Type) SetCTRL_DALTA_CHANGE_EN_U3(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11)
}
func (o *PCNT_Type) GetCTRL_DALTA_CHANGE_EN_U3() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11
}
func (o *PCNT_Type) SetCTRL_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *PCNT_Type) GetCTRL_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10000) >> 16
}

// PCNT.U3_CHANGE_CONF: Configuration register for unit $n's step value.
func (o *PCNT_Type) SetU3_CHANGE_CONF_CNT_STEP_U3(value uint32) {
	volatile.StoreUint32(&o.U3_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU3_CHANGE_CONF_CNT_STEP_U3() uint32 {
	return volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg) & 0xffff
}
func (o *PCNT_Type) SetU3_CHANGE_CONF_CNT_STEP_LIM_U3(value uint32) {
	volatile.StoreUint32(&o.U3_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU3_CHANGE_CONF_CNT_STEP_LIM_U3() uint32 {
	return (volatile.LoadUint32(&o.U3_CHANGE_CONF.Reg) & 0xffff0000) >> 16
}

// PCNT.U2_CHANGE_CONF: Configuration register for unit $n's step value.
func (o *PCNT_Type) SetU2_CHANGE_CONF_CNT_STEP_U2(value uint32) {
	volatile.StoreUint32(&o.U2_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU2_CHANGE_CONF_CNT_STEP_U2() uint32 {
	return volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg) & 0xffff
}
func (o *PCNT_Type) SetU2_CHANGE_CONF_CNT_STEP_LIM_U2(value uint32) {
	volatile.StoreUint32(&o.U2_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU2_CHANGE_CONF_CNT_STEP_LIM_U2() uint32 {
	return (volatile.LoadUint32(&o.U2_CHANGE_CONF.Reg) & 0xffff0000) >> 16
}

// PCNT.U1_CHANGE_CONF: Configuration register for unit $n's step value.
func (o *PCNT_Type) SetU1_CHANGE_CONF_CNT_STEP_U1(value uint32) {
	volatile.StoreUint32(&o.U1_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU1_CHANGE_CONF_CNT_STEP_U1() uint32 {
	return volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg) & 0xffff
}
func (o *PCNT_Type) SetU1_CHANGE_CONF_CNT_STEP_LIM_U1(value uint32) {
	volatile.StoreUint32(&o.U1_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU1_CHANGE_CONF_CNT_STEP_LIM_U1() uint32 {
	return (volatile.LoadUint32(&o.U1_CHANGE_CONF.Reg) & 0xffff0000) >> 16
}

// PCNT.U0_CHANGE_CONF: Configuration register for unit $n's step value.
func (o *PCNT_Type) SetU0_CHANGE_CONF_CNT_STEP_U0(value uint32) {
	volatile.StoreUint32(&o.U0_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg)&^(0xffff)|value)
}
func (o *PCNT_Type) GetU0_CHANGE_CONF_CNT_STEP_U0() uint32 {
	return volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg) & 0xffff
}
func (o *PCNT_Type) SetU0_CHANGE_CONF_CNT_STEP_LIM_U0(value uint32) {
	volatile.StoreUint32(&o.U0_CHANGE_CONF.Reg, volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg)&^(0xffff0000)|value<<16)
}
func (o *PCNT_Type) GetU0_CHANGE_CONF_CNT_STEP_LIM_U0() uint32 {
	return (volatile.LoadUint32(&o.U0_CHANGE_CONF.Reg) & 0xffff0000) >> 16
}

// PCNT.DATE: PCNT version control register
func (o *PCNT_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *PCNT_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// PMU Peripheral
type PMU_Type struct {
	HP_ACTIVE_DIG_POWER      volatile.Register32 // 0x0
	HP_ACTIVE_ICG_HP_FUNC    volatile.Register32 // 0x4
	HP_ACTIVE_ICG_HP_APB     volatile.Register32 // 0x8
	HP_ACTIVE_ICG_MODEM      volatile.Register32 // 0xC
	HP_ACTIVE_HP_SYS_CNTL    volatile.Register32 // 0x10
	HP_ACTIVE_HP_CK_POWER    volatile.Register32 // 0x14
	HP_ACTIVE_BIAS           volatile.Register32 // 0x18
	HP_ACTIVE_BACKUP         volatile.Register32 // 0x1C
	HP_ACTIVE_BACKUP_CLK     volatile.Register32 // 0x20
	HP_ACTIVE_SYSCLK         volatile.Register32 // 0x24
	HP_ACTIVE_HP_REGULATOR0  volatile.Register32 // 0x28
	HP_ACTIVE_HP_REGULATOR1  volatile.Register32 // 0x2C
	HP_ACTIVE_XTAL           volatile.Register32 // 0x30
	HP_MODEM_DIG_POWER       volatile.Register32 // 0x34
	HP_MODEM_ICG_HP_FUNC     volatile.Register32 // 0x38
	HP_MODEM_ICG_HP_APB      volatile.Register32 // 0x3C
	HP_MODEM_ICG_MODEM       volatile.Register32 // 0x40
	HP_MODEM_HP_SYS_CNTL     volatile.Register32 // 0x44
	HP_MODEM_HP_CK_POWER     volatile.Register32 // 0x48
	HP_MODEM_BIAS            volatile.Register32 // 0x4C
	HP_MODEM_BACKUP          volatile.Register32 // 0x50
	HP_MODEM_BACKUP_CLK      volatile.Register32 // 0x54
	HP_MODEM_SYSCLK          volatile.Register32 // 0x58
	HP_MODEM_HP_REGULATOR0   volatile.Register32 // 0x5C
	HP_MODEM_HP_REGULATOR1   volatile.Register32 // 0x60
	HP_MODEM_XTAL            volatile.Register32 // 0x64
	HP_SLEEP_DIG_POWER       volatile.Register32 // 0x68
	HP_SLEEP_ICG_HP_FUNC     volatile.Register32 // 0x6C
	HP_SLEEP_ICG_HP_APB      volatile.Register32 // 0x70
	HP_SLEEP_ICG_MODEM       volatile.Register32 // 0x74
	HP_SLEEP_HP_SYS_CNTL     volatile.Register32 // 0x78
	HP_SLEEP_HP_CK_POWER     volatile.Register32 // 0x7C
	HP_SLEEP_BIAS            volatile.Register32 // 0x80
	HP_SLEEP_BACKUP          volatile.Register32 // 0x84
	HP_SLEEP_BACKUP_CLK      volatile.Register32 // 0x88
	HP_SLEEP_SYSCLK          volatile.Register32 // 0x8C
	HP_SLEEP_HP_REGULATOR0   volatile.Register32 // 0x90
	HP_SLEEP_HP_REGULATOR1   volatile.Register32 // 0x94
	HP_SLEEP_XTAL            volatile.Register32 // 0x98
	HP_SLEEP_LP_REGULATOR0   volatile.Register32 // 0x9C
	HP_SLEEP_LP_REGULATOR1   volatile.Register32 // 0xA0
	HP_SLEEP_LP_DCDC_RESERVE volatile.Register32 // 0xA4
	HP_SLEEP_LP_DIG_POWER    volatile.Register32 // 0xA8
	HP_SLEEP_LP_CK_POWER     volatile.Register32 // 0xAC
	LP_SLEEP_LP_BIAS_RESERVE volatile.Register32 // 0xB0
	LP_SLEEP_LP_REGULATOR0   volatile.Register32 // 0xB4
	LP_SLEEP_LP_REGULATOR1   volatile.Register32 // 0xB8
	LP_SLEEP_XTAL            volatile.Register32 // 0xBC
	LP_SLEEP_LP_DIG_POWER    volatile.Register32 // 0xC0
	LP_SLEEP_LP_CK_POWER     volatile.Register32 // 0xC4
	LP_SLEEP_BIAS            volatile.Register32 // 0xC8
	IMM_HP_CK_POWER          volatile.Register32 // 0xCC
	IMM_SLEEP_SYSCLK         volatile.Register32 // 0xD0
	IMM_HP_FUNC_ICG          volatile.Register32 // 0xD4
	IMM_HP_APB_ICG           volatile.Register32 // 0xD8
	IMM_MODEM_ICG            volatile.Register32 // 0xDC
	IMM_LP_ICG               volatile.Register32 // 0xE0
	IMM_PAD_HOLD_ALL         volatile.Register32 // 0xE4
	IMM_I2C_ISO              volatile.Register32 // 0xE8
	POWER_WAIT_TIMER0        volatile.Register32 // 0xEC
	POWER_WAIT_TIMER1        volatile.Register32 // 0xF0
	POWER_PD_TOP_CNTL        volatile.Register32 // 0xF4
	POWER_PD_CNNT_CNTL       volatile.Register32 // 0xF8
	POWER_PD_HPMEM_CNTL      volatile.Register32 // 0xFC
	POWER_PD_TOP_MASK        volatile.Register32 // 0x100
	POWER_PD_CNNT_MASK       volatile.Register32 // 0x104
	POWER_PD_HPMEM_MASK      volatile.Register32 // 0x108
	POWER_DCDC_SWITCH        volatile.Register32 // 0x10C
	POWER_PD_LPPERI_CNTL     volatile.Register32 // 0x110
	POWER_PD_LPPERI_MASK     volatile.Register32 // 0x114
	POWER_HP_PAD             volatile.Register32 // 0x118
	POWER_CK_WAIT_CNTL       volatile.Register32 // 0x11C
	SLP_WAKEUP_CNTL0         volatile.Register32 // 0x120
	SLP_WAKEUP_CNTL1         volatile.Register32 // 0x124
	SLP_WAKEUP_CNTL2         volatile.Register32 // 0x128
	SLP_WAKEUP_CNTL3         volatile.Register32 // 0x12C
	SLP_WAKEUP_CNTL4         volatile.Register32 // 0x130
	SLP_WAKEUP_CNTL5         volatile.Register32 // 0x134
	SLP_WAKEUP_CNTL6         volatile.Register32 // 0x138
	SLP_WAKEUP_CNTL7         volatile.Register32 // 0x13C
	SLP_WAKEUP_CNTL8         volatile.Register32 // 0x140
	SLP_WAKEUP_STATUS0       volatile.Register32 // 0x144
	SLP_WAKEUP_STATUS1       volatile.Register32 // 0x148
	SLP_WAKEUP_STATUS2       volatile.Register32 // 0x14C
	HP_CK_POWERON            volatile.Register32 // 0x150
	HP_CK_CNTL               volatile.Register32 // 0x154
	POR_STATUS               volatile.Register32 // 0x158
	RF_PWC                   volatile.Register32 // 0x15C
	BACKUP_CFG               volatile.Register32 // 0x160
	INT_RAW                  volatile.Register32 // 0x164
	HP_INT_ST                volatile.Register32 // 0x168
	HP_INT_ENA               volatile.Register32 // 0x16C
	HP_INT_CLR               volatile.Register32 // 0x170
	LP_INT_RAW               volatile.Register32 // 0x174
	LP_INT_ST                volatile.Register32 // 0x178
	LP_INT_ENA               volatile.Register32 // 0x17C
	LP_INT_CLR               volatile.Register32 // 0x180
	LP_CPU_PWR0              volatile.Register32 // 0x184
	LP_CPU_PWR1              volatile.Register32 // 0x188
	LP_CPU_PWR2              volatile.Register32 // 0x18C
	LP_CPU_PWR3              volatile.Register32 // 0x190
	LP_CPU_PWR4              volatile.Register32 // 0x194
	LP_CPU_PWR5              volatile.Register32 // 0x198
	HP_LP_CPU_COMM           volatile.Register32 // 0x19C
	HP_REGULATOR_CFG         volatile.Register32 // 0x1A0
	MAIN_STATE               volatile.Register32 // 0x1A4
	PWR_STATE                volatile.Register32 // 0x1A8
	CLK_STATE0               volatile.Register32 // 0x1AC
	CLK_STATE1               volatile.Register32 // 0x1B0
	CLK_STATE2               volatile.Register32 // 0x1B4
	EXT_LDO_P0_0P1A          volatile.Register32 // 0x1B8
	EXT_LDO_P0_0P1A_ANA      volatile.Register32 // 0x1BC
	EXT_LDO_P0_0P2A          volatile.Register32 // 0x1C0
	EXT_LDO_P0_0P2A_ANA      volatile.Register32 // 0x1C4
	EXT_LDO_P0_0P3A          volatile.Register32 // 0x1C8
	EXT_LDO_P0_0P3A_ANA      volatile.Register32 // 0x1CC
	EXT_LDO_P1_0P1A          volatile.Register32 // 0x1D0
	EXT_LDO_P1_0P1A_ANA      volatile.Register32 // 0x1D4
	EXT_LDO_P1_0P2A          volatile.Register32 // 0x1D8
	EXT_LDO_P1_0P2A_ANA      volatile.Register32 // 0x1DC
	EXT_LDO_P1_0P3A          volatile.Register32 // 0x1E0
	EXT_LDO_P1_0P3A_ANA      volatile.Register32 // 0x1E4
	EXT_WAKEUP_LV            volatile.Register32 // 0x1E8
	EXT_WAKEUP_SEL           volatile.Register32 // 0x1EC
	EXT_WAKEUP_ST            volatile.Register32 // 0x1F0
	EXT_WAKEUP_CNTL          volatile.Register32 // 0x1F4
	SDIO_WAKEUP_CNTL         volatile.Register32 // 0x1F8
	XTAL_SLP                 volatile.Register32 // 0x1FC
	CPU_SW_STALL             volatile.Register32 // 0x200
	DCM_CTRL                 volatile.Register32 // 0x204
	DCM_WAIT_DELAY           volatile.Register32 // 0x208
	VDDBAT_CFG               volatile.Register32 // 0x20C
	TOUCH_PWR_CNTL           volatile.Register32 // 0x210
	RDN_ECO                  volatile.Register32 // 0x214
	_                        [484]byte
	DATE                     volatile.Register32 // 0x3FC
}

// PMU.HP_ACTIVE_DIG_POWER: need_des
func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_DCDC_SWITCH_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_DCDC_SWITCH_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_CNNT_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_CNNT_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_DIG_POWER.Reg) & 0x80000000) >> 31
}

// PMU.HP_ACTIVE_ICG_HP_FUNC: need_des
func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_FUNC(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg, value)
}
func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_FUNC() uint32 {
	return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_FUNC.Reg)
}

// PMU.HP_ACTIVE_ICG_HP_APB: need_des
func (o *PMU_Type) SetHP_ACTIVE_ICG_HP_APB(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg, value)
}
func (o *PMU_Type) GetHP_ACTIVE_ICG_HP_APB() uint32 {
	return volatile.LoadUint32(&o.HP_ACTIVE_ICG_HP_APB.Reg)
}

// PMU.HP_ACTIVE_ICG_MODEM: need_des
func (o *PMU_Type) SetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg)&^(0xc0000000)|value<<30)
}
func (o *PMU_Type) GetHP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_ICG_MODEM.Reg) & 0xc0000000) >> 30
}

// PMU.HP_ACTIVE_HP_SYS_CNTL: need_des
func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_POWER_DET_BYPASS(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_POWER_DET_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_SYS_CNTL.Reg) & 0x20000000) >> 29
}

// PMU.HP_ACTIVE_HP_CK_POWER: need_des
func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_I2C(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_I2C() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg)&^(0x78000000)|value<<27)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_CK_POWER.Reg) & 0x78000000) >> 27
}

// PMU.HP_ACTIVE_BIAS: need_des
func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_VSET(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x7c0000)|value<<18)
}
func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_VSET() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x7c0000) >> 18
}
func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x1800000)|value<<23)
}
func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_DCM_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x1800000) >> 23
}
func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x3c000000)|value<<26)
}
func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x3c000000) >> 26
}
func (o *PMU_Type) SetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_ACTIVE_BIAS_SLEEP(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BIAS.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_ACTIVE_BIAS_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BIAS.Reg) & 0x80000000) >> 31
}

// PMU.HP_ACTIVE_BACKUP: need_des
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30)|value<<4)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30) >> 4
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc0)|value<<6)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc0) >> 6
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x400)|value<<10)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x400) >> 10
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x800)|value<<11)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x800) >> 11
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0xc000)|value<<14)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0xc000) >> 14
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x30000)|value<<16)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x30000) >> 16
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x700000)|value<<20)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x700000) >> 20
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP.Reg, volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_BACKUP.Reg) & 0x40000000) >> 30
}

// PMU.HP_ACTIVE_BACKUP_CLK: need_des
func (o *PMU_Type) SetHP_ACTIVE_BACKUP_CLK(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg, value)
}
func (o *PMU_Type) GetHP_ACTIVE_BACKUP_CLK() uint32 {
	return volatile.LoadUint32(&o.HP_ACTIVE_BACKUP_CLK.Reg)
}

// PMU.HP_ACTIVE_SYSCLK: need_des
func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_SYSCLK.Reg, volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg)&^(0xc0000000)|value<<30)
}
func (o *PMU_Type) GetHP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_SYSCLK.Reg) & 0xc0000000) >> 30
}

// PMU.HP_ACTIVE_HP_REGULATOR0: need_des
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x1f0)|value<<4)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x1f0) >> 4
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x3e00)|value<<9)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x3e00) >> 9
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x780000)|value<<19)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x780000) >> 19
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR0.Reg) & 0xf8000000) >> 27
}

// PMU.HP_ACTIVE_HP_REGULATOR1: need_des
func (o *PMU_Type) SetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg)&^(0xfc000000)|value<<26)
}
func (o *PMU_Type) GetHP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_HP_REGULATOR1.Reg) & 0xfc000000) >> 26
}

// PMU.HP_ACTIVE_XTAL: need_des
func (o *PMU_Type) SetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL(value uint32) {
	volatile.StoreUint32(&o.HP_ACTIVE_XTAL.Reg, volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL() uint32 {
	return (volatile.LoadUint32(&o.HP_ACTIVE_XTAL.Reg) & 0x80000000) >> 31
}

// PMU.HP_MODEM_DIG_POWER: need_des
func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_DCDC_SWITCH_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_DCDC_SWITCH_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_CNNT_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_CNNT_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_DIG_POWER.Reg) & 0x80000000) >> 31
}

// PMU.HP_MODEM_ICG_HP_FUNC: need_des
func (o *PMU_Type) SetHP_MODEM_ICG_HP_FUNC(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg, value)
}
func (o *PMU_Type) GetHP_MODEM_ICG_HP_FUNC() uint32 {
	return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_FUNC.Reg)
}

// PMU.HP_MODEM_ICG_HP_APB: need_des
func (o *PMU_Type) SetHP_MODEM_ICG_HP_APB(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_ICG_HP_APB.Reg, value)
}
func (o *PMU_Type) GetHP_MODEM_ICG_HP_APB() uint32 {
	return volatile.LoadUint32(&o.HP_MODEM_ICG_HP_APB.Reg)
}

// PMU.HP_MODEM_ICG_MODEM: need_des
func (o *PMU_Type) SetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg)&^(0xc0000000)|value<<30)
}
func (o *PMU_Type) GetHP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_ICG_MODEM.Reg) & 0xc0000000) >> 30
}

// PMU.HP_MODEM_HP_SYS_CNTL: need_des
func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_POWER_DET_BYPASS(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_POWER_DET_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_SYS_CNTL.Reg) & 0x20000000) >> 29
}

// PMU.HP_MODEM_HP_CK_POWER: need_des
func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_I2C(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_I2C() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg)&^(0x78000000)|value<<27)
}
func (o *PMU_Type) GetHP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_CK_POWER.Reg) & 0x78000000) >> 27
}

// PMU.HP_MODEM_BIAS: need_des
func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_DCM_VSET(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x7c0000)|value<<18)
}
func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_DCM_VSET() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x7c0000) >> 18
}
func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_DCM_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x1800000)|value<<23)
}
func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_DCM_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x1800000) >> 23
}
func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_XPD_BIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_DBG_ATTEN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x3c000000)|value<<26)
}
func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_DBG_ATTEN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x3c000000) >> 26
}
func (o *PMU_Type) SetHP_MODEM_BIAS_HP_MODEM_PD_CUR(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_MODEM_BIAS_HP_MODEM_PD_CUR() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_MODEM_BIAS_SLEEP(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BIAS.Reg, volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_MODEM_BIAS_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BIAS.Reg) & 0x80000000) >> 31
}

// PMU.HP_MODEM_BACKUP: need_des
func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x30)|value<<4)
}
func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x30) >> 4
}
func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x400)|value<<10)
}
func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x400) >> 10
}
func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x800)|value<<11)
}
func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x800) >> 11
}
func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0xc000)|value<<14)
}
func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0xc000) >> 14
}
func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x700000)|value<<20)
}
func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x700000) >> 20
}
func (o *PMU_Type) SetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BACKUP.Reg, volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_BACKUP.Reg) & 0x20000000) >> 29
}

// PMU.HP_MODEM_BACKUP_CLK: need_des
func (o *PMU_Type) SetHP_MODEM_BACKUP_CLK(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_BACKUP_CLK.Reg, value)
}
func (o *PMU_Type) GetHP_MODEM_BACKUP_CLK() uint32 {
	return volatile.LoadUint32(&o.HP_MODEM_BACKUP_CLK.Reg)
}

// PMU.HP_MODEM_SYSCLK: need_des
func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_SYSCLK.Reg, volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg)&^(0xc0000000)|value<<30)
}
func (o *PMU_Type) GetHP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_SYSCLK.Reg) & 0xc0000000) >> 30
}

// PMU.HP_MODEM_HP_REGULATOR0: need_des
func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x780000)|value<<19)
}
func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x780000) >> 19
}
func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR0.Reg) & 0xf8000000) >> 27
}

// PMU.HP_MODEM_HP_REGULATOR1: need_des
func (o *PMU_Type) SetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg)&^(0xffffff00)|value<<8)
}
func (o *PMU_Type) GetHP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_HP_REGULATOR1.Reg) & 0xffffff00) >> 8
}

// PMU.HP_MODEM_XTAL: need_des
func (o *PMU_Type) SetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL(value uint32) {
	volatile.StoreUint32(&o.HP_MODEM_XTAL.Reg, volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_MODEM_XTAL_HP_MODEM_XPD_XTAL() uint32 {
	return (volatile.LoadUint32(&o.HP_MODEM_XTAL.Reg) & 0x80000000) >> 31
}

// PMU.HP_SLEEP_DIG_POWER: need_des
func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_DCDC_SWITCH_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_DCDC_SWITCH_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_CNNT_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_CNNT_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_DIG_POWER.Reg) & 0x80000000) >> 31
}

// PMU.HP_SLEEP_ICG_HP_FUNC: need_des
func (o *PMU_Type) SetHP_SLEEP_ICG_HP_FUNC(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg, value)
}
func (o *PMU_Type) GetHP_SLEEP_ICG_HP_FUNC() uint32 {
	return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_FUNC.Reg)
}

// PMU.HP_SLEEP_ICG_HP_APB: need_des
func (o *PMU_Type) SetHP_SLEEP_ICG_HP_APB(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_ICG_HP_APB.Reg, value)
}
func (o *PMU_Type) GetHP_SLEEP_ICG_HP_APB() uint32 {
	return volatile.LoadUint32(&o.HP_SLEEP_ICG_HP_APB.Reg)
}

// PMU.HP_SLEEP_ICG_MODEM: need_des
func (o *PMU_Type) SetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_ICG_MODEM.Reg, volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg)&^(0xc0000000)|value<<30)
}
func (o *PMU_Type) GetHP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_ICG_MODEM.Reg) & 0xc0000000) >> 30
}

// PMU.HP_SLEEP_HP_SYS_CNTL: need_des
func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_POWER_DET_BYPASS(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_POWER_DET_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_SYS_CNTL.Reg) & 0x20000000) >> 29
}

// PMU.HP_SLEEP_HP_CK_POWER: need_des
func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_I2C(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_I2C() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg)&^(0x78000000)|value<<27)
}
func (o *PMU_Type) GetHP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_CK_POWER.Reg) & 0x78000000) >> 27
}

// PMU.HP_SLEEP_BIAS: need_des
func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_DCM_VSET(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x7c0000)|value<<18)
}
func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_DCM_VSET() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x7c0000) >> 18
}
func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_DCM_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x1800000)|value<<23)
}
func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_DCM_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x1800000) >> 23
}
func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x3c000000)|value<<26)
}
func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x3c000000) >> 26
}
func (o *PMU_Type) SetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_SLEEP_BIAS_HP_SLEEP_PD_CUR() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_SLEEP_BIAS_SLEEP(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_SLEEP_BIAS_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BIAS.Reg) & 0x80000000) >> 31
}

// PMU.HP_SLEEP_BACKUP: need_des
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0)|value<<6)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0) >> 6
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x300)|value<<8)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x300) >> 8
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x400)|value<<10)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x400) >> 10
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x30000)|value<<16)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x30000) >> 16
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0xc0000)|value<<18)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0xc0000) >> 18
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x1c000000)|value<<26)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x1c000000) >> 26
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP.Reg, volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_BACKUP.Reg) & 0x80000000) >> 31
}

// PMU.HP_SLEEP_BACKUP_CLK: need_des
func (o *PMU_Type) SetHP_SLEEP_BACKUP_CLK(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_BACKUP_CLK.Reg, value)
}
func (o *PMU_Type) GetHP_SLEEP_BACKUP_CLK() uint32 {
	return volatile.LoadUint32(&o.HP_SLEEP_BACKUP_CLK.Reg)
}

// PMU.HP_SLEEP_SYSCLK: need_des
func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg)&^(0xc0000000)|value<<30)
}
func (o *PMU_Type) GetHP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_SYSCLK.Reg) & 0xc0000000) >> 30
}

// PMU.HP_SLEEP_HP_REGULATOR0: need_des
func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x780000)|value<<19)
}
func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x780000) >> 19
}
func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR0.Reg) & 0xf8000000) >> 27
}

// PMU.HP_SLEEP_HP_REGULATOR1: need_des
func (o *PMU_Type) SetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg)&^(0xfc000000)|value<<26)
}
func (o *PMU_Type) GetHP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_HP_REGULATOR1.Reg) & 0xfc000000) >> 26
}

// PMU.HP_SLEEP_XTAL: need_des
func (o *PMU_Type) SetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_XTAL.Reg) & 0x80000000) >> 31
}

// PMU.HP_SLEEP_LP_REGULATOR0: need_des
func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27
}

// PMU.HP_SLEEP_LP_REGULATOR1: need_des
func (o *PMU_Type) SetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg)&^(0xfc000000)|value<<26)
}
func (o *PMU_Type) GetHP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_REGULATOR1.Reg) & 0xfc000000) >> 26
}

// PMU.HP_SLEEP_LP_DCDC_RESERVE: need_des
func (o *PMU_Type) SetHP_SLEEP_LP_DCDC_RESERVE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg, value)
}
func (o *PMU_Type) GetHP_SLEEP_LP_DCDC_RESERVE() uint32 {
	return volatile.LoadUint32(&o.HP_SLEEP_LP_DCDC_RESERVE.Reg)
}

// PMU.HP_SLEEP_LP_DIG_POWER: need_des
func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_PAD_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x30000000)|value<<28)
}
func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x30000000) >> 28
}
func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31
}

// PMU.HP_SLEEP_LP_CK_POWER: need_des
func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK(value uint32) {
	volatile.StoreUint32(&o.HP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK() uint32 {
	return (volatile.LoadUint32(&o.HP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31
}

// PMU.LP_SLEEP_LP_BIAS_RESERVE: need_des
func (o *PMU_Type) SetLP_SLEEP_LP_BIAS_RESERVE(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg, value)
}
func (o *PMU_Type) GetLP_SLEEP_LP_BIAS_RESERVE() uint32 {
	return volatile.LoadUint32(&o.LP_SLEEP_LP_BIAS_RESERVE.Reg)
}

// PMU.LP_SLEEP_LP_REGULATOR0: need_des
func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR0.Reg) & 0xf8000000) >> 27
}

// PMU.LP_SLEEP_LP_REGULATOR1: need_des
func (o *PMU_Type) SetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg)&^(0xfc000000)|value<<26)
}
func (o *PMU_Type) GetLP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_REGULATOR1.Reg) & 0xfc000000) >> 26
}

// PMU.LP_SLEEP_XTAL: need_des
func (o *PMU_Type) SetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_XTAL.Reg, volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_XTAL.Reg) & 0x80000000) >> 31
}

// PMU.LP_SLEEP_LP_DIG_POWER: need_des
func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_PAD_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x30000000)|value<<28)
}
func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x30000000) >> 28
}
func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_DIG_POWER.Reg) & 0x80000000) >> 31
}

// PMU.LP_SLEEP_LP_CK_POWER: need_des
func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_LP_CK_POWER.Reg, volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_LP_CK_POWER.Reg) & 0x80000000) >> 31
}

// PMU.LP_SLEEP_BIAS: need_des
func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x3c000000)|value<<26)
}
func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x3c000000) >> 26
}
func (o *PMU_Type) SetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_SLEEP_BIAS_LP_SLEEP_PD_CUR() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_SLEEP_BIAS_SLEEP(value uint32) {
	volatile.StoreUint32(&o.LP_SLEEP_BIAS.Reg, volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_SLEEP_BIAS_SLEEP() uint32 {
	return (volatile.LoadUint32(&o.LP_SLEEP_BIAS.Reg) & 0x80000000) >> 31
}

// PMU.IMM_HP_CK_POWER: need_des
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_CALI_XTAL_ICG(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_CALI_XTAL_ICG() uint32 {
	return volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_PLL_ICG(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1e)|value<<1)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_PLL_ICG() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1e) >> 1
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x20)|value<<5)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x20) >> 5
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x40)|value<<6)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x40) >> 6
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL_I2C(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x780)|value<<7)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL_I2C() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x780) >> 7
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x7800)|value<<11)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_PLL() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x7800) >> 11
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_LOW_XPD_XTAL() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_CALI_XTAL_ICG(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_CALI_XTAL_ICG() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_PLL_ICG(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x1e0000)|value<<17)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_PLL_ICG() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x1e0000) >> 17
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_I2C(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x7800000)|value<<23)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_I2C() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x7800000) >> 23
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x78000000)|value<<27)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_PLL() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x78000000) >> 27
}
func (o *PMU_Type) SetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_CK_POWER.Reg, volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_CK_POWER.Reg) & 0x80000000) >> 31
}

// PMU.IMM_SLEEP_SYSCLK: need_des
func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH(value uint32) {
	volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH() uint32 {
	return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_SLEEP_SYSCLK.Reg, volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.IMM_SLEEP_SYSCLK.Reg) & 0x80000000) >> 31
}

// PMU.IMM_HP_FUNC_ICG: need_des
func (o *PMU_Type) SetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_FUNC_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_FUNC_ICG.Reg) & 0x80000000) >> 31
}

// PMU.IMM_HP_APB_ICG: need_des
func (o *PMU_Type) SetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN(value uint32) {
	volatile.StoreUint32(&o.IMM_HP_APB_ICG.Reg, volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN() uint32 {
	return (volatile.LoadUint32(&o.IMM_HP_APB_ICG.Reg) & 0x80000000) >> 31
}

// PMU.IMM_MODEM_ICG: need_des
func (o *PMU_Type) SetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN(value uint32) {
	volatile.StoreUint32(&o.IMM_MODEM_ICG.Reg, volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN() uint32 {
	return (volatile.LoadUint32(&o.IMM_MODEM_ICG.Reg) & 0x80000000) >> 31
}

// PMU.IMM_LP_ICG: need_des
func (o *PMU_Type) SetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetIMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_LP_ICG.Reg, volatile.LoadUint32(&o.IMM_LP_ICG.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.IMM_LP_ICG.Reg) & 0x80000000) >> 31
}

// PMU.IMM_PAD_HOLD_ALL: need_des
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_PAD_SLP_SEL() uint32 {
	return volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x1
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_LP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_LP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x2) >> 1
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_HP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x4)|value<<2)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_HP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x4) >> 2
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_PAD_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_PAD_SLP_SEL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_PAD_SLP_SEL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL(value uint32) {
	volatile.StoreUint32(&o.IMM_PAD_HOLD_ALL.Reg, volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL() uint32 {
	return (volatile.LoadUint32(&o.IMM_PAD_HOLD_ALL.Reg) & 0x80000000) >> 31
}

// PMU.IMM_I2C_ISO: need_des
func (o *PMU_Type) SetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN(value uint32) {
	volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetIMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN() uint32 {
	return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN(value uint32) {
	volatile.StoreUint32(&o.IMM_I2C_ISO.Reg, volatile.LoadUint32(&o.IMM_I2C_ISO.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetIMM_I2C_ISO_TIE_LOW_I2C_ISO_EN() uint32 {
	return (volatile.LoadUint32(&o.IMM_I2C_ISO.Reg) & 0x80000000) >> 31
}

// PMU.POWER_WAIT_TIMER0: need_des
func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER(value uint32) {
	volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x3fe0)|value<<5)
}
func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER() uint32 {
	return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x3fe0) >> 5
}
func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER(value uint32) {
	volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0x7fc000)|value<<14)
}
func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER() uint32 {
	return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0x7fc000) >> 14
}
func (o *PMU_Type) SetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER(value uint32) {
	volatile.StoreUint32(&o.POWER_WAIT_TIMER0.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg)&^(0xff800000)|value<<23)
}
func (o *PMU_Type) GetPOWER_WAIT_TIMER0_DG_HP_WAIT_TIMER() uint32 {
	return (volatile.LoadUint32(&o.POWER_WAIT_TIMER0.Reg) & 0xff800000) >> 23
}

// PMU.POWER_WAIT_TIMER1: need_des
func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER(value uint32) {
	volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0x3fe0)|value<<5)
}
func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER() uint32 {
	return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0x3fe0) >> 5
}
func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER(value uint32) {
	volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0x7fc000)|value<<14)
}
func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER() uint32 {
	return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0x7fc000) >> 14
}
func (o *PMU_Type) SetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER(value uint32) {
	volatile.StoreUint32(&o.POWER_WAIT_TIMER1.Reg, volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg)&^(0xff800000)|value<<23)
}
func (o *PMU_Type) GetPOWER_WAIT_TIMER1_DG_LP_WAIT_TIMER() uint32 {
	return (volatile.LoadUint32(&o.POWER_WAIT_TIMER1.Reg) & 0xff800000) >> 23
}

// PMU.POWER_PD_TOP_CNTL: need_des
func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_RESET() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x1
}
func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x2) >> 1
}
func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PU(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x4)|value<<2)
}
func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PU() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x4) >> 2
}
func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x8)|value<<3)
}
func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x8) >> 3
}
func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x10)|value<<4)
}
func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x10) >> 4
}
func (o *PMU_Type) SetPOWER_PD_TOP_CNTL_FORCE_TOP_PD(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg)&^(0x20)|value<<5)
}
func (o *PMU_Type) GetPOWER_PD_TOP_CNTL_FORCE_TOP_PD() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_TOP_CNTL.Reg) & 0x20) >> 5
}

// PMU.POWER_PD_CNNT_CNTL: need_des
func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_RESET() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x1
}
func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x2) >> 1
}
func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PU(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x4)|value<<2)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PU() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x4) >> 2
}
func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x8)|value<<3)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_RESET() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x8) >> 3
}
func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x10)|value<<4)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_NO_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x10) >> 4
}
func (o *PMU_Type) SetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PD(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg)&^(0x20)|value<<5)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_CNTL_FORCE_CNNT_PD() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_CNNT_CNTL.Reg) & 0x20) >> 5
}

// PMU.POWER_PD_HPMEM_CNTL: need_des
func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_RESET() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x1
}
func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x2) >> 1
}
func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PU(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x4)|value<<2)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PU() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x4) >> 2
}
func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x8)|value<<3)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_RESET() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x8) >> 3
}
func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x10)|value<<4)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x10) >> 4
}
func (o *PMU_Type) SetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg)&^(0x20)|value<<5)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PD() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_HPMEM_CNTL.Reg) & 0x20) >> 5
}

// PMU.POWER_PD_TOP_MASK: need_des
func (o *PMU_Type) SetPOWER_PD_TOP_MASK_XPD_TOP_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg)&^(0x1f)|value)
}
func (o *PMU_Type) GetPOWER_PD_TOP_MASK_XPD_TOP_MASK() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg) & 0x1f
}
func (o *PMU_Type) SetPOWER_PD_TOP_MASK_PD_TOP_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_TOP_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetPOWER_PD_TOP_MASK_PD_TOP_MASK() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_TOP_MASK.Reg) & 0xf8000000) >> 27
}

// PMU.POWER_PD_CNNT_MASK: need_des
func (o *PMU_Type) SetPOWER_PD_CNNT_MASK_XPD_CNNT_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg)&^(0x1f)|value)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_MASK_XPD_CNNT_MASK() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg) & 0x1f
}
func (o *PMU_Type) SetPOWER_PD_CNNT_MASK_PD_CNNT_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_CNNT_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetPOWER_PD_CNNT_MASK_PD_CNNT_MASK() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_CNNT_MASK.Reg) & 0xf8000000) >> 27
}

// PMU.POWER_PD_HPMEM_MASK: need_des
func (o *PMU_Type) SetPOWER_PD_HPMEM_MASK_XPD_HP_MEM_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg)&^(0x3f)|value)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_MASK_XPD_HP_MEM_MASK() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg) & 0x3f
}
func (o *PMU_Type) SetPOWER_PD_HPMEM_MASK_PD_HP_MEM_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_HPMEM_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg)&^(0xfc000000)|value<<26)
}
func (o *PMU_Type) GetPOWER_PD_HPMEM_MASK_PD_HP_MEM_MASK() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_HPMEM_MASK.Reg) & 0xfc000000) >> 26
}

// PMU.POWER_DCDC_SWITCH: need_des
func (o *PMU_Type) SetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PU(value uint32) {
	volatile.StoreUint32(&o.POWER_DCDC_SWITCH.Reg, volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PU() uint32 {
	return volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg) & 0x1
}
func (o *PMU_Type) SetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PD(value uint32) {
	volatile.StoreUint32(&o.POWER_DCDC_SWITCH.Reg, volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetPOWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PD() uint32 {
	return (volatile.LoadUint32(&o.POWER_DCDC_SWITCH.Reg) & 0x2) >> 1
}

// PMU.POWER_PD_LPPERI_CNTL: need_des
func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x1
}
func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x2) >> 1
}
func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x4)|value<<2)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x4) >> 2
}
func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x8)|value<<3)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x8) >> 3
}
func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x10)|value<<4)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x10) >> 4
}
func (o *PMU_Type) SetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_CNTL.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg)&^(0x20)|value<<5)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_LPPERI_CNTL.Reg) & 0x20) >> 5
}

// PMU.POWER_PD_LPPERI_MASK: need_des
func (o *PMU_Type) SetPOWER_PD_LPPERI_MASK_XPD_LP_PERI_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg)&^(0x1f)|value)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_MASK_XPD_LP_PERI_MASK() uint32 {
	return volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg) & 0x1f
}
func (o *PMU_Type) SetPOWER_PD_LPPERI_MASK_PD_LP_PERI_MASK(value uint32) {
	volatile.StoreUint32(&o.POWER_PD_LPPERI_MASK.Reg, volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg)&^(0xf8000000)|value<<27)
}
func (o *PMU_Type) GetPOWER_PD_LPPERI_MASK_PD_LP_PERI_MASK() uint32 {
	return (volatile.LoadUint32(&o.POWER_PD_LPPERI_MASK.Reg) & 0xf8000000) >> 27
}

// PMU.POWER_HP_PAD: need_des
func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL(value uint32) {
	volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL() uint32 {
	return volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x1
}
func (o *PMU_Type) SetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL(value uint32) {
	volatile.StoreUint32(&o.POWER_HP_PAD.Reg, volatile.LoadUint32(&o.POWER_HP_PAD.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetPOWER_HP_PAD_FORCE_HP_PAD_ISO_ALL() uint32 {
	return (volatile.LoadUint32(&o.POWER_HP_PAD.Reg) & 0x2) >> 1
}

// PMU.POWER_CK_WAIT_CNTL: need_des
func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_PMU_WAIT_XTL_STABLE(value uint32) {
	volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff)|value)
}
func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_PMU_WAIT_XTL_STABLE() uint32 {
	return volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff
}
func (o *PMU_Type) SetPOWER_CK_WAIT_CNTL_PMU_WAIT_PLL_STABLE(value uint32) {
	volatile.StoreUint32(&o.POWER_CK_WAIT_CNTL.Reg, volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg)&^(0xffff0000)|value<<16)
}
func (o *PMU_Type) GetPOWER_CK_WAIT_CNTL_PMU_WAIT_PLL_STABLE() uint32 {
	return (volatile.LoadUint32(&o.POWER_CK_WAIT_CNTL.Reg) & 0xffff0000) >> 16
}

// PMU.SLP_WAKEUP_CNTL0: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL0_SLEEP_REQ(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL0.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL0_SLEEP_REQ() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL0.Reg) & 0x80000000) >> 31
}

// PMU.SLP_WAKEUP_CNTL1: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA() uint32 {
	return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x7fffffff
}
func (o *PMU_Type) SetSLP_WAKEUP_CNTL1_SLP_REJECT_EN(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL1_SLP_REJECT_EN() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL1.Reg) & 0x80000000) >> 31
}

// PMU.SLP_WAKEUP_CNTL2: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL2_WAKEUP_ENA(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL2.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL2.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL2_WAKEUP_ENA() uint32 {
	return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL2.Reg) & 0x7fffffff
}

// PMU.SLP_WAKEUP_CNTL3: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff)|value)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL() uint32 {
	return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff
}
func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0xff00)|value<<8)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0xff00) >> 8
}
func (o *PMU_Type) SetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL3.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg)&^(0x30000)|value<<16)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL3_SLEEP_PRT_SEL() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL3.Reg) & 0x30000) >> 16
}

// PMU.SLP_WAKEUP_CNTL4: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL4.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL4.Reg) & 0x80000000) >> 31
}

// PMU.SLP_WAKEUP_CNTL5: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xfffff)|value)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET() uint32 {
	return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xfffff
}
func (o *PMU_Type) SetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL5.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg)&^(0xff000000)|value<<24)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL5.Reg) & 0xff000000) >> 24
}

// PMU.SLP_WAKEUP_CNTL6: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xfffff)|value)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT() uint32 {
	return volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xfffff
}
func (o *PMU_Type) SetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL6.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg)&^(0xc0000000)|value<<30)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL6.Reg) & 0xc0000000) >> 30
}

// PMU.SLP_WAKEUP_CNTL7: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL7.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg)&^(0xffff0000)|value<<16)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL7_ANA_WAIT_TARGET() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL7.Reg) & 0xffff0000) >> 16
}

// PMU.SLP_WAKEUP_CNTL8: need_des
func (o *PMU_Type) SetSLP_WAKEUP_CNTL8_LP_LITE_WAKEUP_ENA(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_CNTL8.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_CNTL8.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetSLP_WAKEUP_CNTL8_LP_LITE_WAKEUP_ENA() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_CNTL8.Reg) & 0x80000000) >> 31
}

// PMU.SLP_WAKEUP_STATUS0: need_des
func (o *PMU_Type) SetSLP_WAKEUP_STATUS0_WAKEUP_CAUSE(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_STATUS0.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_STATUS0.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetSLP_WAKEUP_STATUS0_WAKEUP_CAUSE() uint32 {
	return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS0.Reg) & 0x7fffffff
}

// PMU.SLP_WAKEUP_STATUS1: need_des
func (o *PMU_Type) SetSLP_WAKEUP_STATUS1_REJECT_CAUSE(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_STATUS1.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_STATUS1.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetSLP_WAKEUP_STATUS1_REJECT_CAUSE() uint32 {
	return volatile.LoadUint32(&o.SLP_WAKEUP_STATUS1.Reg) & 0x7fffffff
}

// PMU.SLP_WAKEUP_STATUS2: need_des
func (o *PMU_Type) SetSLP_WAKEUP_STATUS2_LP_LITE_WAKEUP_CAUSE(value uint32) {
	volatile.StoreUint32(&o.SLP_WAKEUP_STATUS2.Reg, volatile.LoadUint32(&o.SLP_WAKEUP_STATUS2.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetSLP_WAKEUP_STATUS2_LP_LITE_WAKEUP_CAUSE() uint32 {
	return (volatile.LoadUint32(&o.SLP_WAKEUP_STATUS2.Reg) & 0x80000000) >> 31
}

// PMU.HP_CK_POWERON: need_des
func (o *PMU_Type) SetHP_CK_POWERON_I2C_POR_WAIT_TARGET(value uint32) {
	volatile.StoreUint32(&o.HP_CK_POWERON.Reg, volatile.LoadUint32(&o.HP_CK_POWERON.Reg)&^(0xff)|value)
}
func (o *PMU_Type) GetHP_CK_POWERON_I2C_POR_WAIT_TARGET() uint32 {
	return volatile.LoadUint32(&o.HP_CK_POWERON.Reg) & 0xff
}

// PMU.HP_CK_CNTL: need_des
func (o *PMU_Type) SetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT(value uint32) {
	volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff)|value)
}
func (o *PMU_Type) GetHP_CK_CNTL_MODIFY_ICG_CNTL_WAIT() uint32 {
	return volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff
}
func (o *PMU_Type) SetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT(value uint32) {
	volatile.StoreUint32(&o.HP_CK_CNTL.Reg, volatile.LoadUint32(&o.HP_CK_CNTL.Reg)&^(0xff00)|value<<8)
}
func (o *PMU_Type) GetHP_CK_CNTL_SWITCH_ICG_CNTL_WAIT() uint32 {
	return (volatile.LoadUint32(&o.HP_CK_CNTL.Reg) & 0xff00) >> 8
}

// PMU.POR_STATUS: need_des
func (o *PMU_Type) SetPOR_STATUS_POR_DONE(value uint32) {
	volatile.StoreUint32(&o.POR_STATUS.Reg, volatile.LoadUint32(&o.POR_STATUS.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetPOR_STATUS_POR_DONE() uint32 {
	return (volatile.LoadUint32(&o.POR_STATUS.Reg) & 0x80000000) >> 31
}

// PMU.RF_PWC: need_des
func (o *PMU_Type) SetRF_PWC_MSPI_PHY_XPD(value uint32) {
	volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetRF_PWC_MSPI_PHY_XPD() uint32 {
	return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetRF_PWC_SDIO_PLL_XPD(value uint32) {
	volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetRF_PWC_SDIO_PLL_XPD() uint32 {
	return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetRF_PWC_PERIF_I2C_RSTB(value uint32) {
	volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetRF_PWC_PERIF_I2C_RSTB() uint32 {
	return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetRF_PWC_XPD_PERIF_I2C(value uint32) {
	volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetRF_PWC_XPD_PERIF_I2C() uint32 {
	return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetRF_PWC_XPD_TXRF_I2C(value uint32) {
	volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetRF_PWC_XPD_TXRF_I2C() uint32 {
	return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetRF_PWC_XPD_RFRX_PBUS(value uint32) {
	volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetRF_PWC_XPD_RFRX_PBUS() uint32 {
	return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetRF_PWC_XPD_CKGEN_I2C(value uint32) {
	volatile.StoreUint32(&o.RF_PWC.Reg, volatile.LoadUint32(&o.RF_PWC.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetRF_PWC_XPD_CKGEN_I2C() uint32 {
	return (volatile.LoadUint32(&o.RF_PWC.Reg) & 0x40000000) >> 30
}

// PMU.BACKUP_CFG: need_des
func (o *PMU_Type) SetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV(value uint32) {
	volatile.StoreUint32(&o.BACKUP_CFG.Reg, volatile.LoadUint32(&o.BACKUP_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetBACKUP_CFG_BACKUP_SYS_CLK_NO_DIV() uint32 {
	return (volatile.LoadUint32(&o.BACKUP_CFG.Reg) & 0x80000000) >> 31
}

// PMU.INT_RAW: need_des
func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetINT_RAW__0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetINT_RAW__0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetINT_RAW__0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetINT_RAW__0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetINT_RAW__0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetINT_RAW__0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetINT_RAW_LP_CPU_EXC_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetINT_RAW_LP_CPU_EXC_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetINT_RAW_SDIO_IDLE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetINT_RAW_SDIO_IDLE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetINT_RAW_SW_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetINT_RAW_SW_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetINT_RAW_SOC_SLEEP_REJECT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetINT_RAW_SOC_SLEEP_REJECT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31
}

// PMU.HP_INT_ST: need_des
func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET0_REACH_0_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET0_REACH_0_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET1_REACH_0_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET1_REACH_0_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET0_REACH_1_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET0_REACH_1_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetHP_INT_ST__0P1A_CNT_TARGET1_REACH_1_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetHP_INT_ST__0P1A_CNT_TARGET1_REACH_1_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET0_REACH_0_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET0_REACH_0_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET1_REACH_0_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET1_REACH_0_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET0_REACH_1_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET0_REACH_1_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetHP_INT_ST__0P2A_CNT_TARGET1_REACH_1_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_INT_ST__0P2A_CNT_TARGET1_REACH_1_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET0_REACH_0_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET0_REACH_0_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET1_REACH_0_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET1_REACH_0_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET0_REACH_1_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET0_REACH_1_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetHP_INT_ST__0P3A_CNT_TARGET1_REACH_1_HP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_INT_ST__0P3A_CNT_TARGET1_REACH_1_HP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_INT_ST_LP_CPU_EXC_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_INT_ST_LP_CPU_EXC_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_INT_ST_SDIO_IDLE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_INT_ST_SDIO_IDLE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_INT_ST_SW_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_INT_ST_SW_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_INT_ST_SOC_SLEEP_REJECT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_INT_ST_SOC_WAKEUP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ST.Reg, volatile.LoadUint32(&o.HP_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_INT_ST_SOC_WAKEUP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ST.Reg) & 0x80000000) >> 31
}

// PMU.HP_INT_ENA: need_des
func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetHP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_INT_ENA_LP_CPU_EXC_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_INT_ENA_LP_CPU_EXC_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_INT_ENA_SDIO_IDLE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_INT_ENA_SDIO_IDLE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_INT_ENA_SW_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_INT_ENA_SW_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_INT_ENA_SOC_WAKEUP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.HP_INT_ENA.Reg, volatile.LoadUint32(&o.HP_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_INT_ENA_SOC_WAKEUP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_ENA.Reg) & 0x80000000) >> 31
}

// PMU.HP_INT_CLR: need_des
func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetHP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetHP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetHP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetHP_INT_CLR_LP_CPU_EXC_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetHP_INT_CLR_LP_CPU_EXC_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetHP_INT_CLR_SDIO_IDLE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetHP_INT_CLR_SDIO_IDLE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetHP_INT_CLR_SW_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetHP_INT_CLR_SW_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_INT_CLR_SOC_WAKEUP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.HP_INT_CLR.Reg, volatile.LoadUint32(&o.HP_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_INT_CLR_SOC_WAKEUP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.HP_INT_CLR.Reg) & 0x80000000) >> 31
}

// PMU.LP_INT_RAW: need_des
func (o *PMU_Type) SetLP_INT_RAW_LP_CPU_SLEEP_REJECT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetLP_INT_RAW_LP_CPU_SLEEP_REJECT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetLP_INT_RAW__0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetLP_INT_RAW__0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetLP_INT_RAW__0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetLP_INT_RAW_LP_CPU_WAKEUP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetLP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_INT_RAW_HP_SW_TRIGGER_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31
}

// PMU.LP_INT_ST: need_des
func (o *PMU_Type) SetLP_INT_ST_LP_CPU_SLEEP_REJECT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetLP_INT_ST_LP_CPU_SLEEP_REJECT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET0_REACH_0_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET0_REACH_0_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET1_REACH_0_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET1_REACH_0_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET0_REACH_1_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET0_REACH_1_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetLP_INT_ST__0P1A_CNT_TARGET1_REACH_1_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetLP_INT_ST__0P1A_CNT_TARGET1_REACH_1_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET0_REACH_0_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET0_REACH_0_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET1_REACH_0_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET1_REACH_0_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET0_REACH_1_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET0_REACH_1_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetLP_INT_ST__0P2A_CNT_TARGET1_REACH_1_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetLP_INT_ST__0P2A_CNT_TARGET1_REACH_1_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET0_REACH_0_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET0_REACH_0_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET1_REACH_0_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET1_REACH_0_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET0_REACH_1_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET0_REACH_1_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetLP_INT_ST__0P3A_CNT_TARGET1_REACH_1_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetLP_INT_ST__0P3A_CNT_TARGET1_REACH_1_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetLP_INT_ST_LP_CPU_WAKEUP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetLP_INT_ST_LP_CPU_WAKEUP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetLP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_INT_ST_HP_SW_TRIGGER_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_INT_ST_HP_SW_TRIGGER_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31
}

// PMU.LP_INT_ENA: need_des
func (o *PMU_Type) SetLP_INT_ENA_LP_CPU_SLEEP_REJECT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetLP_INT_ENA_LP_CPU_SLEEP_REJECT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetLP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetLP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetLP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetLP_INT_ENA_LP_CPU_WAKEUP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetLP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_INT_ENA_HP_SW_TRIGGER_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31
}

// PMU.LP_INT_CLR: need_des
func (o *PMU_Type) SetLP_INT_CLR_LP_CPU_SLEEP_REJECT_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetLP_INT_CLR_LP_CPU_SLEEP_REJECT_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x10000) >> 16
}
func (o *PMU_Type) SetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *PMU_Type) GetLP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x20000) >> 17
}
func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *PMU_Type) GetLP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x200000) >> 21
}
func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x400000) >> 22
}
func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x800000) >> 23
}
func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetLP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetLP_INT_CLR_LP_CPU_WAKEUP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x10000000) >> 28
}
func (o *PMU_Type) SetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetLP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_INT_CLR_HP_SW_TRIGGER_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31
}

// PMU.LP_CPU_PWR0: need_des
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_WAITI_RDY(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_WAITI_RDY() uint32 {
	return volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_STALL_RDY(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_STALL_RDY() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x2) >> 1
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_FORCE_STALL(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_FORCE_STALL() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x100000)|value<<20)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x100000) >> 20
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x1fe00000)|value<<21)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x1fe00000) >> 21
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_STALL_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x20000000) >> 29
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR0.Reg, volatile.LoadUint32(&o.LP_CPU_PWR0.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR0.Reg) & 0x80000000) >> 31
}

// PMU.LP_CPU_PWR1: need_des
func (o *PMU_Type) SetLP_CPU_PWR1_LP_CPU_SLEEP_REQ(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR1.Reg, volatile.LoadUint32(&o.LP_CPU_PWR1.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetLP_CPU_PWR1_LP_CPU_SLEEP_REQ() uint32 {
	return (volatile.LoadUint32(&o.LP_CPU_PWR1.Reg) & 0x80000000) >> 31
}

// PMU.LP_CPU_PWR2: need_des
func (o *PMU_Type) SetLP_CPU_PWR2_LP_CPU_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR2.Reg, volatile.LoadUint32(&o.LP_CPU_PWR2.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetLP_CPU_PWR2_LP_CPU_WAKEUP_EN() uint32 {
	return volatile.LoadUint32(&o.LP_CPU_PWR2.Reg) & 0x7fffffff
}

// PMU.LP_CPU_PWR3: need_des
func (o *PMU_Type) SetLP_CPU_PWR3_LP_CPU_WAKEUP_CAUSE(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR3.Reg, volatile.LoadUint32(&o.LP_CPU_PWR3.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetLP_CPU_PWR3_LP_CPU_WAKEUP_CAUSE() uint32 {
	return volatile.LoadUint32(&o.LP_CPU_PWR3.Reg) & 0x7fffffff
}

// PMU.LP_CPU_PWR4: need_des
func (o *PMU_Type) SetLP_CPU_PWR4_LP_CPU_REJECT_EN(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR4.Reg, volatile.LoadUint32(&o.LP_CPU_PWR4.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetLP_CPU_PWR4_LP_CPU_REJECT_EN() uint32 {
	return volatile.LoadUint32(&o.LP_CPU_PWR4.Reg) & 0x7fffffff
}

// PMU.LP_CPU_PWR5: need_des
func (o *PMU_Type) SetLP_CPU_PWR5_LP_CPU_REJECT_CAUSE(value uint32) {
	volatile.StoreUint32(&o.LP_CPU_PWR5.Reg, volatile.LoadUint32(&o.LP_CPU_PWR5.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetLP_CPU_PWR5_LP_CPU_REJECT_CAUSE() uint32 {
	return volatile.LoadUint32(&o.LP_CPU_PWR5.Reg) & 0x7fffffff
}

// PMU.HP_LP_CPU_COMM: need_des
func (o *PMU_Type) SetHP_LP_CPU_COMM_LP_TRIGGER_HP(value uint32) {
	volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetHP_LP_CPU_COMM_LP_TRIGGER_HP() uint32 {
	return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetHP_LP_CPU_COMM_HP_TRIGGER_LP(value uint32) {
	volatile.StoreUint32(&o.HP_LP_CPU_COMM.Reg, volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_LP_CPU_COMM_HP_TRIGGER_LP() uint32 {
	return (volatile.LoadUint32(&o.HP_LP_CPU_COMM.Reg) & 0x80000000) >> 31
}

// PMU.HP_REGULATOR_CFG: need_des
func (o *PMU_Type) SetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL(value uint32) {
	volatile.StoreUint32(&o.HP_REGULATOR_CFG.Reg, volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetHP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL() uint32 {
	return (volatile.LoadUint32(&o.HP_REGULATOR_CFG.Reg) & 0x80000000) >> 31
}

// PMU.MAIN_STATE: need_des
func (o *PMU_Type) SetMAIN_STATE_ENABLE_CALI_PMU_CNTL(value uint32) {
	volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetMAIN_STATE_ENABLE_CALI_PMU_CNTL() uint32 {
	return volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x1
}
func (o *PMU_Type) SetMAIN_STATE_PMU_MAIN_LAST_ST_STATE(value uint32) {
	volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x3f800)|value<<11)
}
func (o *PMU_Type) GetMAIN_STATE_PMU_MAIN_LAST_ST_STATE() uint32 {
	return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x3f800) >> 11
}
func (o *PMU_Type) SetMAIN_STATE_PMU_MAIN_TAR_ST_STATE(value uint32) {
	volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0x1fc0000)|value<<18)
}
func (o *PMU_Type) GetMAIN_STATE_PMU_MAIN_TAR_ST_STATE() uint32 {
	return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0x1fc0000) >> 18
}
func (o *PMU_Type) SetMAIN_STATE_PMU_MAIN_CUR_ST_STATE(value uint32) {
	volatile.StoreUint32(&o.MAIN_STATE.Reg, volatile.LoadUint32(&o.MAIN_STATE.Reg)&^(0xfe000000)|value<<25)
}
func (o *PMU_Type) GetMAIN_STATE_PMU_MAIN_CUR_ST_STATE() uint32 {
	return (volatile.LoadUint32(&o.MAIN_STATE.Reg) & 0xfe000000) >> 25
}

// PMU.PWR_STATE: need_des
func (o *PMU_Type) SetPWR_STATE_PMU_BACKUP_ST_STATE(value uint32) {
	volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x3e000)|value<<13)
}
func (o *PMU_Type) GetPWR_STATE_PMU_BACKUP_ST_STATE() uint32 {
	return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x3e000) >> 13
}
func (o *PMU_Type) SetPWR_STATE_PMU_LP_PWR_ST_STATE(value uint32) {
	volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0x7c0000)|value<<18)
}
func (o *PMU_Type) GetPWR_STATE_PMU_LP_PWR_ST_STATE() uint32 {
	return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0x7c0000) >> 18
}
func (o *PMU_Type) SetPWR_STATE_PMU_HP_PWR_ST_STATE(value uint32) {
	volatile.StoreUint32(&o.PWR_STATE.Reg, volatile.LoadUint32(&o.PWR_STATE.Reg)&^(0xff800000)|value<<23)
}
func (o *PMU_Type) GetPWR_STATE_PMU_HP_PWR_ST_STATE() uint32 {
	return (volatile.LoadUint32(&o.PWR_STATE.Reg) & 0xff800000) >> 23
}

// PMU.CLK_STATE0: need_des
func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_PLL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x7)|value)
}
func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_PLL_STATE() uint32 {
	return volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x7
}
func (o *PMU_Type) SetCLK_STATE0_STABLE_XPD_XTAL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8)|value<<3)
}
func (o *PMU_Type) GetCLK_STATE0_STABLE_XPD_XTAL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8) >> 3
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_XPD_PLL_I2C_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x70)|value<<4)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_XPD_PLL_I2C_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x70) >> 4
}
func (o *PMU_Type) SetCLK_STATE0_PMU_SYS_CLK_SLP_SEL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x400)|value<<10)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_SYS_CLK_SLP_SEL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x400) >> 10
}
func (o *PMU_Type) SetCLK_STATE0_PMU_SYS_CLK_SEL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1800)|value<<11)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_SYS_CLK_SEL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1800) >> 11
}
func (o *PMU_Type) SetCLK_STATE0_PMU_SYS_CLK_NO_DIV_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_SYS_CLK_NO_DIV_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_SYS_CLK_EN_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_SYS_CLK_EN_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_MODEM_SWITCH_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_MODEM_SWITCH_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_MODEM_CODE_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x30000)|value<<16)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_MODEM_CODE_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x30000) >> 16
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_SLP_SEL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x40000)|value<<18)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_SLP_SEL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x40000) >> 18
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_GLOBAL_XTAL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000)|value<<19)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_GLOBAL_XTAL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000) >> 19
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ICG_GLOBAL_PLL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0xf00000)|value<<20)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ICG_GLOBAL_PLL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0xf00000) >> 20
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_I2C_ISO_EN_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x1000000)|value<<24)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_I2C_ISO_EN_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x1000000) >> 24
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_I2C_RETENTION_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x2000000)|value<<25)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_I2C_RETENTION_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x2000000) >> 25
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_XPD_PLL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x78000000)|value<<27)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_XPD_PLL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x78000000) >> 27
}
func (o *PMU_Type) SetCLK_STATE0_PMU_ANA_XPD_XTAL_STATE(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE0.Reg, volatile.LoadUint32(&o.CLK_STATE0.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetCLK_STATE0_PMU_ANA_XPD_XTAL_STATE() uint32 {
	return (volatile.LoadUint32(&o.CLK_STATE0.Reg) & 0x80000000) >> 31
}

// PMU.CLK_STATE1: need_des
func (o *PMU_Type) SetCLK_STATE1(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE1.Reg, value)
}
func (o *PMU_Type) GetCLK_STATE1() uint32 {
	return volatile.LoadUint32(&o.CLK_STATE1.Reg)
}

// PMU.CLK_STATE2: need_des
func (o *PMU_Type) SetCLK_STATE2(value uint32) {
	volatile.StoreUint32(&o.CLK_STATE2.Reg, value)
}
func (o *PMU_Type) GetCLK_STATE2() uint32 {
	return volatile.LoadUint32(&o.CLK_STATE2.Reg)
}

// PMU.EXT_LDO_P0_0P1A: need_des
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_FORCE_TIEH_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x80)|value<<7)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_FORCE_TIEH_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x80) >> 7
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_XPD_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x100)|value<<8)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_XPD_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x100) >> 8
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0xe00)|value<<9)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0xe00) >> 9
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_POS_EN_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_POS_EN_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_NEG_EN_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_NEG_EN_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TIEH_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TIEH_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TARGET1_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x7f8000)|value<<15)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TARGET1_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x7f8000) >> 15
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_TARGET0_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x7f800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_TARGET0_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x7f800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A.Reg) & 0x80000000) >> 31
}

// PMU.EXT_LDO_P0_0P1A_ANA: need_des
func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_MUL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_MUL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_VDET_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_VDET_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_DREF_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg)&^(0xf0000000)|value<<28)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P1A_ANA_ANA_0P1A_DREF_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P1A_ANA.Reg) & 0xf0000000) >> 28
}

// PMU.EXT_LDO_P0_0P2A: need_des
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_FORCE_TIEH_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x80)|value<<7)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_FORCE_TIEH_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x80) >> 7
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_XPD_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x100)|value<<8)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_XPD_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x100) >> 8
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0xe00)|value<<9)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0xe00) >> 9
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_POS_EN_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_POS_EN_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_NEG_EN_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_NEG_EN_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TIEH_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TIEH_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TARGET1_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x7f8000)|value<<15)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TARGET1_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x7f8000) >> 15
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_TARGET0_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x7f800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_TARGET0_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x7f800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A.Reg) & 0x80000000) >> 31
}

// PMU.EXT_LDO_P0_0P2A_ANA: need_des
func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_MUL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_MUL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_VDET_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_VDET_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_DREF_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg)&^(0xf0000000)|value<<28)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P2A_ANA_ANA_0P2A_DREF_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P2A_ANA.Reg) & 0xf0000000) >> 28
}

// PMU.EXT_LDO_P0_0P3A: need_des
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_FORCE_TIEH_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x80)|value<<7)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_FORCE_TIEH_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x80) >> 7
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_XPD_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x100)|value<<8)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_XPD_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x100) >> 8
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0xe00)|value<<9)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0xe00) >> 9
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_POS_EN_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_POS_EN_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_NEG_EN_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_NEG_EN_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TIEH_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TIEH_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TARGET1_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x7f8000)|value<<15)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TARGET1_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x7f8000) >> 15
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_TARGET0_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x7f800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_TARGET0_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x7f800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A.Reg) & 0x80000000) >> 31
}

// PMU.EXT_LDO_P0_0P3A_ANA: need_des
func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_MUL_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_MUL_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_VDET_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_VDET_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_DREF_0(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg)&^(0xf0000000)|value<<28)
}
func (o *PMU_Type) GetEXT_LDO_P0_0P3A_ANA_ANA_0P3A_DREF_0() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P0_0P3A_ANA.Reg) & 0xf0000000) >> 28
}

// PMU.EXT_LDO_P1_0P1A: need_des
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_FORCE_TIEH_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x80)|value<<7)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_FORCE_TIEH_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x80) >> 7
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_XPD_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x100)|value<<8)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_XPD_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x100) >> 8
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0xe00)|value<<9)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0xe00) >> 9
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_POS_EN_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_POS_EN_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_NEG_EN_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_NEG_EN_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TIEH_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TIEH_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TARGET1_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x7f8000)|value<<15)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TARGET1_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x7f8000) >> 15
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_TARGET0_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x7f800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_TARGET0_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x7f800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A.Reg) & 0x80000000) >> 31
}

// PMU.EXT_LDO_P1_0P1A_ANA: need_des
func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_MUL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_MUL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_VDET_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_VDET_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_DREF_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg)&^(0xf0000000)|value<<28)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P1A_ANA_ANA_0P1A_DREF_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P1A_ANA.Reg) & 0xf0000000) >> 28
}

// PMU.EXT_LDO_P1_0P2A: need_des
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_FORCE_TIEH_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x80)|value<<7)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_FORCE_TIEH_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x80) >> 7
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_XPD_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x100)|value<<8)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_XPD_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x100) >> 8
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0xe00)|value<<9)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0xe00) >> 9
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_POS_EN_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_POS_EN_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_NEG_EN_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_NEG_EN_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TIEH_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TIEH_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TARGET1_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x7f8000)|value<<15)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TARGET1_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x7f8000) >> 15
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_TARGET0_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x7f800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_TARGET0_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x7f800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A.Reg) & 0x80000000) >> 31
}

// PMU.EXT_LDO_P1_0P2A_ANA: need_des
func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_MUL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_MUL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_VDET_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_VDET_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_DREF_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg)&^(0xf0000000)|value<<28)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P2A_ANA_ANA_0P2A_DREF_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P2A_ANA.Reg) & 0xf0000000) >> 28
}

// PMU.EXT_LDO_P1_0P3A: need_des
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_FORCE_TIEH_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x80)|value<<7)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_FORCE_TIEH_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x80) >> 7
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_XPD_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x100)|value<<8)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_XPD_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x100) >> 8
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0xe00)|value<<9)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0xe00) >> 9
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_POS_EN_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_POS_EN_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_NEG_EN_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_NEG_EN_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TIEH_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TIEH_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TARGET1_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x7f8000)|value<<15)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TARGET1_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x7f8000) >> 15
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_TARGET0_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x7f800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_TARGET0_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x7f800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A.Reg) & 0x80000000) >> 31
}

// PMU.EXT_LDO_P1_0P3A_ANA: need_des
func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_MUL_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0x3800000)|value<<23)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_MUL_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0x3800000) >> 23
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_VDET_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0x4000000)|value<<26)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_VDET_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0x4000000) >> 26
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0x8000000)|value<<27)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0x8000000) >> 27
}
func (o *PMU_Type) SetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_DREF_1(value uint32) {
	volatile.StoreUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg, volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg)&^(0xf0000000)|value<<28)
}
func (o *PMU_Type) GetEXT_LDO_P1_0P3A_ANA_ANA_0P3A_DREF_1() uint32 {
	return (volatile.LoadUint32(&o.EXT_LDO_P1_0P3A_ANA.Reg) & 0xf0000000) >> 28
}

// PMU.EXT_WAKEUP_LV: need_des
func (o *PMU_Type) SetEXT_WAKEUP_LV(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP_LV.Reg, value)
}
func (o *PMU_Type) GetEXT_WAKEUP_LV() uint32 {
	return volatile.LoadUint32(&o.EXT_WAKEUP_LV.Reg)
}

// PMU.EXT_WAKEUP_SEL: need_des
func (o *PMU_Type) SetEXT_WAKEUP_SEL(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP_SEL.Reg, value)
}
func (o *PMU_Type) GetEXT_WAKEUP_SEL() uint32 {
	return volatile.LoadUint32(&o.EXT_WAKEUP_SEL.Reg)
}

// PMU.EXT_WAKEUP_ST: need_des
func (o *PMU_Type) SetEXT_WAKEUP_ST(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP_ST.Reg, value)
}
func (o *PMU_Type) GetEXT_WAKEUP_ST() uint32 {
	return volatile.LoadUint32(&o.EXT_WAKEUP_ST.Reg)
}

// PMU.EXT_WAKEUP_CNTL: need_des
func (o *PMU_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR() uint32 {
	return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER(value uint32) {
	volatile.StoreUint32(&o.EXT_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetEXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER() uint32 {
	return (volatile.LoadUint32(&o.EXT_WAKEUP_CNTL.Reg) & 0x80000000) >> 31
}

// PMU.SDIO_WAKEUP_CNTL: need_des
func (o *PMU_Type) SetSDIO_WAKEUP_CNTL_SDIO_ACT_DNUM(value uint32) {
	volatile.StoreUint32(&o.SDIO_WAKEUP_CNTL.Reg, volatile.LoadUint32(&o.SDIO_WAKEUP_CNTL.Reg)&^(0x3ff)|value)
}
func (o *PMU_Type) GetSDIO_WAKEUP_CNTL_SDIO_ACT_DNUM() uint32 {
	return volatile.LoadUint32(&o.SDIO_WAKEUP_CNTL.Reg) & 0x3ff
}

// PMU.XTAL_SLP: need_des
func (o *PMU_Type) SetXTAL_SLP_CNT_TARGET(value uint32) {
	volatile.StoreUint32(&o.XTAL_SLP.Reg, volatile.LoadUint32(&o.XTAL_SLP.Reg)&^(0xffff0000)|value<<16)
}
func (o *PMU_Type) GetXTAL_SLP_CNT_TARGET() uint32 {
	return (volatile.LoadUint32(&o.XTAL_SLP.Reg) & 0xffff0000) >> 16
}

// PMU.CPU_SW_STALL: need_des
func (o *PMU_Type) SetCPU_SW_STALL_HPCORE1_SW_STALL_CODE(value uint32) {
	volatile.StoreUint32(&o.CPU_SW_STALL.Reg, volatile.LoadUint32(&o.CPU_SW_STALL.Reg)&^(0xff0000)|value<<16)
}
func (o *PMU_Type) GetCPU_SW_STALL_HPCORE1_SW_STALL_CODE() uint32 {
	return (volatile.LoadUint32(&o.CPU_SW_STALL.Reg) & 0xff0000) >> 16
}
func (o *PMU_Type) SetCPU_SW_STALL_HPCORE0_SW_STALL_CODE(value uint32) {
	volatile.StoreUint32(&o.CPU_SW_STALL.Reg, volatile.LoadUint32(&o.CPU_SW_STALL.Reg)&^(0xff000000)|value<<24)
}
func (o *PMU_Type) GetCPU_SW_STALL_HPCORE0_SW_STALL_CODE() uint32 {
	return (volatile.LoadUint32(&o.CPU_SW_STALL.Reg) & 0xff000000) >> 24
}

// PMU.DCM_CTRL: need_des
func (o *PMU_Type) SetDCM_CTRL_DCDC_ON_REQ(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_ON_REQ() uint32 {
	return volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x1
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_OFF_REQ(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_OFF_REQ() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x2) >> 1
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_LIGHTSLP_REQ(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_LIGHTSLP_REQ() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x4) >> 2
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_DEEPSLP_REQ(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_DEEPSLP_REQ() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x8) >> 3
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_DONE_FORCE(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_DONE_FORCE() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x80) >> 7
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_ON_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_ON_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x100) >> 8
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_ON_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_ON_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x200) >> 9
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_FB_RES_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_FB_RES_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x400) >> 10
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_FB_RES_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_FB_RES_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x800) >> 11
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_LS_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_LS_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x1000) >> 12
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_LS_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_LS_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x2000) >> 13
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_DS_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_DS_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x4000) >> 14
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_DS_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_DS_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x8000) >> 15
}
func (o *PMU_Type) SetDCM_CTRL_DCM_CUR_ST(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0xff0000)|value<<16)
}
func (o *PMU_Type) GetDCM_CTRL_DCM_CUR_ST() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0xff0000) >> 16
}
func (o *PMU_Type) SetDCM_CTRL_DCDC_EN_AMUX_TEST(value uint32) {
	volatile.StoreUint32(&o.DCM_CTRL.Reg, volatile.LoadUint32(&o.DCM_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *PMU_Type) GetDCM_CTRL_DCDC_EN_AMUX_TEST() uint32 {
	return (volatile.LoadUint32(&o.DCM_CTRL.Reg) & 0x20000000) >> 29
}

// PMU.DCM_WAIT_DELAY: need_des
func (o *PMU_Type) SetDCM_WAIT_DELAY_DCDC_PRE_DELAY(value uint32) {
	volatile.StoreUint32(&o.DCM_WAIT_DELAY.Reg, volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg)&^(0xff)|value)
}
func (o *PMU_Type) GetDCM_WAIT_DELAY_DCDC_PRE_DELAY() uint32 {
	return volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg) & 0xff
}
func (o *PMU_Type) SetDCM_WAIT_DELAY_DCDC_RES_OFF_DELAY(value uint32) {
	volatile.StoreUint32(&o.DCM_WAIT_DELAY.Reg, volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg)&^(0xff00)|value<<8)
}
func (o *PMU_Type) GetDCM_WAIT_DELAY_DCDC_RES_OFF_DELAY() uint32 {
	return (volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg) & 0xff00) >> 8
}
func (o *PMU_Type) SetDCM_WAIT_DELAY_DCDC_STABLE_DELAY(value uint32) {
	volatile.StoreUint32(&o.DCM_WAIT_DELAY.Reg, volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg)&^(0x3ff0000)|value<<16)
}
func (o *PMU_Type) GetDCM_WAIT_DELAY_DCDC_STABLE_DELAY() uint32 {
	return (volatile.LoadUint32(&o.DCM_WAIT_DELAY.Reg) & 0x3ff0000) >> 16
}

// PMU.VDDBAT_CFG: need_des
func (o *PMU_Type) SetVDDBAT_CFG_ANA_VDDBAT_MODE(value uint32) {
	volatile.StoreUint32(&o.VDDBAT_CFG.Reg, volatile.LoadUint32(&o.VDDBAT_CFG.Reg)&^(0x3)|value)
}
func (o *PMU_Type) GetVDDBAT_CFG_ANA_VDDBAT_MODE() uint32 {
	return volatile.LoadUint32(&o.VDDBAT_CFG.Reg) & 0x3
}
func (o *PMU_Type) SetVDDBAT_CFG_VDDBAT_SW_UPDATE(value uint32) {
	volatile.StoreUint32(&o.VDDBAT_CFG.Reg, volatile.LoadUint32(&o.VDDBAT_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetVDDBAT_CFG_VDDBAT_SW_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.VDDBAT_CFG.Reg) & 0x80000000) >> 31
}

// PMU.TOUCH_PWR_CNTL: need_des
func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_WAIT_CYCLES(value uint32) {
	volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x3fe0)|value<<5)
}
func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_WAIT_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x3fe0) >> 5
}
func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_SLEEP_CYCLES(value uint32) {
	volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x3fffc000)|value<<14)
}
func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_SLEEP_CYCLES() uint32 {
	return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x3fffc000) >> 14
}
func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_FORCE_DONE(value uint32) {
	volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x40000000)|value<<30)
}
func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_FORCE_DONE() uint32 {
	return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x40000000) >> 30
}
func (o *PMU_Type) SetTOUCH_PWR_CNTL_TOUCH_SLEEP_TIMER_EN(value uint32) {
	volatile.StoreUint32(&o.TOUCH_PWR_CNTL.Reg, volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetTOUCH_PWR_CNTL_TOUCH_SLEEP_TIMER_EN() uint32 {
	return (volatile.LoadUint32(&o.TOUCH_PWR_CNTL.Reg) & 0x80000000) >> 31
}

// PMU.RDN_ECO: need_des
func (o *PMU_Type) SetRDN_ECO_PMU_RDN_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO.Reg, volatile.LoadUint32(&o.RDN_ECO.Reg)&^(0x1)|value)
}
func (o *PMU_Type) GetRDN_ECO_PMU_RDN_ECO_RESULT() uint32 {
	return volatile.LoadUint32(&o.RDN_ECO.Reg) & 0x1
}
func (o *PMU_Type) SetRDN_ECO_PMU_RDN_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RDN_ECO.Reg, volatile.LoadUint32(&o.RDN_ECO.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetRDN_ECO_PMU_RDN_ECO_EN() uint32 {
	return (volatile.LoadUint32(&o.RDN_ECO.Reg) & 0x80000000) >> 31
}

// PMU.DATE: need_des
func (o *PMU_Type) SetDATE_PMU_DATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value)
}
func (o *PMU_Type) GetDATE_PMU_DATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff
}
func (o *PMU_Type) SetDATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *PMU_Type) GetDATE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31
}

// PPA Peripheral
type PPA_Type struct {
	BLEND0_CLUT_DATA volatile.Register32 // 0x0
	BLEND1_CLUT_DATA volatile.Register32 // 0x4
	_                [4]byte
	CLUT_CONF        volatile.Register32 // 0xC
	INT_RAW          volatile.Register32 // 0x10
	INT_ST           volatile.Register32 // 0x14
	INT_ENA          volatile.Register32 // 0x18
	INT_CLR          volatile.Register32 // 0x1C
	SR_COLOR_MODE    volatile.Register32 // 0x20
	BLEND_COLOR_MODE volatile.Register32 // 0x24
	SR_BYTE_ORDER    volatile.Register32 // 0x28
	BLEND_BYTE_ORDER volatile.Register32 // 0x2C
	_                [4]byte
	BLEND_TRANS_MODE volatile.Register32 // 0x34
	SR_FIX_ALPHA     volatile.Register32 // 0x38
	BLEND_TX_SIZE    volatile.Register32 // 0x3C
	BLEND_FIX_ALPHA  volatile.Register32 // 0x40
	_                [4]byte
	BLEND_RGB        volatile.Register32 // 0x48
	BLEND_FIX_PIXEL  volatile.Register32 // 0x4C
	CK_FG_LOW        volatile.Register32 // 0x50
	CK_FG_HIGH       volatile.Register32 // 0x54
	CK_BG_LOW        volatile.Register32 // 0x58
	CK_BG_HIGH       volatile.Register32 // 0x5C
	CK_DEFAULT       volatile.Register32 // 0x60
	SR_SCAL_ROTATE   volatile.Register32 // 0x64
	SR_MEM_PD        volatile.Register32 // 0x68
	REG_CONF         volatile.Register32 // 0x6C
	CLUT_CNT         volatile.Register32 // 0x70
	BLEND_ST         volatile.Register32 // 0x74
	SR_PARAM_ERR_ST  volatile.Register32 // 0x78
	SR_STATUS        volatile.Register32 // 0x7C
	ECO_LOW          volatile.Register32 // 0x80
	ECO_HIGH         volatile.Register32 // 0x84
	ECO_CELL_CTRL    volatile.Register32 // 0x88
	SRAM_CTRL        volatile.Register32 // 0x8C
	_                [112]byte
	DATE             volatile.Register32 // 0x100
}

// PPA.BLEND0_CLUT_DATA: CLUT sram data read/write register in background plane of blender
func (o *PPA_Type) SetBLEND0_CLUT_DATA(value uint32) {
	volatile.StoreUint32(&o.BLEND0_CLUT_DATA.Reg, value)
}
func (o *PPA_Type) GetBLEND0_CLUT_DATA() uint32 {
	return volatile.LoadUint32(&o.BLEND0_CLUT_DATA.Reg)
}

// PPA.BLEND1_CLUT_DATA: CLUT sram data read/write register in foreground plane of blender
func (o *PPA_Type) SetBLEND1_CLUT_DATA(value uint32) {
	volatile.StoreUint32(&o.BLEND1_CLUT_DATA.Reg, value)
}
func (o *PPA_Type) GetBLEND1_CLUT_DATA() uint32 {
	return volatile.LoadUint32(&o.BLEND1_CLUT_DATA.Reg)
}

// PPA.CLUT_CONF: CLUT configure register
func (o *PPA_Type) SetCLUT_CONF_APB_FIFO_MASK(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetCLUT_CONF_APB_FIFO_MASK() uint32 {
	return volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x1
}
func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_RST(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_RST() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetCLUT_CONF_BLEND1_CLUT_MEM_RST(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetCLUT_CONF_BLEND1_CLUT_MEM_RST() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x4) >> 2
}
func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_RDADDR_RST(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x8)|value<<3)
}
func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_RDADDR_RST() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x8) >> 3
}
func (o *PPA_Type) SetCLUT_CONF_BLEND1_CLUT_MEM_RDADDR_RST(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x10)|value<<4)
}
func (o *PPA_Type) GetCLUT_CONF_BLEND1_CLUT_MEM_RDADDR_RST() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x10) >> 4
}
func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x20)|value<<5)
}
func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x20) >> 5
}
func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x40)|value<<6)
}
func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x40) >> 6
}
func (o *PPA_Type) SetCLUT_CONF_BLEND0_CLUT_MEM_CLK_ENA(value uint32) {
	volatile.StoreUint32(&o.CLUT_CONF.Reg, volatile.LoadUint32(&o.CLUT_CONF.Reg)&^(0x80)|value<<7)
}
func (o *PPA_Type) GetCLUT_CONF_BLEND0_CLUT_MEM_CLK_ENA() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CONF.Reg) & 0x80) >> 7
}

// PPA.INT_RAW: Raw status interrupt
func (o *PPA_Type) SetINT_RAW_SR_EOF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetINT_RAW_SR_EOF_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *PPA_Type) SetINT_RAW_BLEND_EOF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetINT_RAW_BLEND_EOF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetINT_RAW_SR_PARAM_CFG_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetINT_RAW_SR_PARAM_CFG_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}

// PPA.INT_ST: Masked interrupt
func (o *PPA_Type) SetINT_ST_SR_EOF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetINT_ST_SR_EOF_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *PPA_Type) SetINT_ST_BLEND_EOF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetINT_ST_BLEND_EOF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetINT_ST_SR_PARAM_CFG_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetINT_ST_SR_PARAM_CFG_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}

// PPA.INT_ENA: Interrupt enable bits
func (o *PPA_Type) SetINT_ENA_SR_EOF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetINT_ENA_SR_EOF_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *PPA_Type) SetINT_ENA_BLEND_EOF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetINT_ENA_BLEND_EOF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetINT_ENA_SR_PARAM_CFG_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetINT_ENA_SR_PARAM_CFG_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}

// PPA.INT_CLR: Interrupt clear bits
func (o *PPA_Type) SetINT_CLR_SR_EOF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetINT_CLR_SR_EOF_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *PPA_Type) SetINT_CLR_BLEND_EOF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetINT_CLR_BLEND_EOF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetINT_CLR_SR_PARAM_CFG_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetINT_CLR_SR_PARAM_CFG_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}

// PPA.SR_COLOR_MODE: Scaling and rotating engine color mode register
func (o *PPA_Type) SetSR_COLOR_MODE_SR_RX_CM(value uint32) {
	volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0xf)|value)
}
func (o *PPA_Type) GetSR_COLOR_MODE_SR_RX_CM() uint32 {
	return volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0xf
}
func (o *PPA_Type) SetSR_COLOR_MODE_SR_TX_CM(value uint32) {
	volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0xf0)|value<<4)
}
func (o *PPA_Type) GetSR_COLOR_MODE_SR_TX_CM() uint32 {
	return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0xf0) >> 4
}
func (o *PPA_Type) SetSR_COLOR_MODE_YUV_RX_RANGE(value uint32) {
	volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x100)|value<<8)
}
func (o *PPA_Type) GetSR_COLOR_MODE_YUV_RX_RANGE() uint32 {
	return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x100) >> 8
}
func (o *PPA_Type) SetSR_COLOR_MODE_YUV_TX_RANGE(value uint32) {
	volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x200)|value<<9)
}
func (o *PPA_Type) GetSR_COLOR_MODE_YUV_TX_RANGE() uint32 {
	return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x200) >> 9
}
func (o *PPA_Type) SetSR_COLOR_MODE_YUV2RGB_PROTOCAL(value uint32) {
	volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x400)|value<<10)
}
func (o *PPA_Type) GetSR_COLOR_MODE_YUV2RGB_PROTOCAL() uint32 {
	return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x400) >> 10
}
func (o *PPA_Type) SetSR_COLOR_MODE_RGB2YUV_PROTOCAL(value uint32) {
	volatile.StoreUint32(&o.SR_COLOR_MODE.Reg, volatile.LoadUint32(&o.SR_COLOR_MODE.Reg)&^(0x800)|value<<11)
}
func (o *PPA_Type) GetSR_COLOR_MODE_RGB2YUV_PROTOCAL() uint32 {
	return (volatile.LoadUint32(&o.SR_COLOR_MODE.Reg) & 0x800) >> 11
}

// PPA.BLEND_COLOR_MODE: blending engine color mode register
func (o *PPA_Type) SetBLEND_COLOR_MODE_BLEND0_RX_CM(value uint32) {
	volatile.StoreUint32(&o.BLEND_COLOR_MODE.Reg, volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg)&^(0xf)|value)
}
func (o *PPA_Type) GetBLEND_COLOR_MODE_BLEND0_RX_CM() uint32 {
	return volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg) & 0xf
}
func (o *PPA_Type) SetBLEND_COLOR_MODE_BLEND1_RX_CM(value uint32) {
	volatile.StoreUint32(&o.BLEND_COLOR_MODE.Reg, volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg)&^(0xf0)|value<<4)
}
func (o *PPA_Type) GetBLEND_COLOR_MODE_BLEND1_RX_CM() uint32 {
	return (volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg) & 0xf0) >> 4
}
func (o *PPA_Type) SetBLEND_COLOR_MODE_BLEND_TX_CM(value uint32) {
	volatile.StoreUint32(&o.BLEND_COLOR_MODE.Reg, volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg)&^(0xf00)|value<<8)
}
func (o *PPA_Type) GetBLEND_COLOR_MODE_BLEND_TX_CM() uint32 {
	return (volatile.LoadUint32(&o.BLEND_COLOR_MODE.Reg) & 0xf00) >> 8
}

// PPA.SR_BYTE_ORDER: Scaling and rotating engine byte order register
func (o *PPA_Type) SetSR_BYTE_ORDER_SR_RX_BYTE_SWAP_EN(value uint32) {
	volatile.StoreUint32(&o.SR_BYTE_ORDER.Reg, volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetSR_BYTE_ORDER_SR_RX_BYTE_SWAP_EN() uint32 {
	return volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg) & 0x1
}
func (o *PPA_Type) SetSR_BYTE_ORDER_SR_RX_RGB_SWAP_EN(value uint32) {
	volatile.StoreUint32(&o.SR_BYTE_ORDER.Reg, volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetSR_BYTE_ORDER_SR_RX_RGB_SWAP_EN() uint32 {
	return (volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetSR_BYTE_ORDER_SR_MACRO_BK_RO_BYPASS(value uint32) {
	volatile.StoreUint32(&o.SR_BYTE_ORDER.Reg, volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetSR_BYTE_ORDER_SR_MACRO_BK_RO_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.SR_BYTE_ORDER.Reg) & 0x4) >> 2
}

// PPA.BLEND_BYTE_ORDER: Blending engine byte order register
func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND0_RX_BYTE_SWAP_EN(value uint32) {
	volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND0_RX_BYTE_SWAP_EN() uint32 {
	return volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x1
}
func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND1_RX_BYTE_SWAP_EN(value uint32) {
	volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND1_RX_BYTE_SWAP_EN() uint32 {
	return (volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND0_RX_RGB_SWAP_EN(value uint32) {
	volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND0_RX_RGB_SWAP_EN() uint32 {
	return (volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x4) >> 2
}
func (o *PPA_Type) SetBLEND_BYTE_ORDER_BLEND1_RX_RGB_SWAP_EN(value uint32) {
	volatile.StoreUint32(&o.BLEND_BYTE_ORDER.Reg, volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg)&^(0x8)|value<<3)
}
func (o *PPA_Type) GetBLEND_BYTE_ORDER_BLEND1_RX_RGB_SWAP_EN() uint32 {
	return (volatile.LoadUint32(&o.BLEND_BYTE_ORDER.Reg) & 0x8) >> 3
}

// PPA.BLEND_TRANS_MODE: Blending engine mode configure register
func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_EN(value uint32) {
	volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_EN() uint32 {
	return volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x1
}
func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_BYPASS(value uint32) {
	volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_FIX_PIXEL_FILL_EN(value uint32) {
	volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_FIX_PIXEL_FILL_EN() uint32 {
	return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x4) >> 2
}
func (o *PPA_Type) SetBLEND_TRANS_MODE_UPDATE(value uint32) {
	volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x8)|value<<3)
}
func (o *PPA_Type) GetBLEND_TRANS_MODE_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x8) >> 3
}
func (o *PPA_Type) SetBLEND_TRANS_MODE_BLEND_RST(value uint32) {
	volatile.StoreUint32(&o.BLEND_TRANS_MODE.Reg, volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg)&^(0x10)|value<<4)
}
func (o *PPA_Type) GetBLEND_TRANS_MODE_BLEND_RST() uint32 {
	return (volatile.LoadUint32(&o.BLEND_TRANS_MODE.Reg) & 0x10) >> 4
}

// PPA.SR_FIX_ALPHA: Scaling and rotating engine alpha override register
func (o *PPA_Type) SetSR_FIX_ALPHA_SR_RX_FIX_ALPHA(value uint32) {
	volatile.StoreUint32(&o.SR_FIX_ALPHA.Reg, volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetSR_FIX_ALPHA_SR_RX_FIX_ALPHA() uint32 {
	return volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg) & 0xff
}
func (o *PPA_Type) SetSR_FIX_ALPHA_SR_RX_ALPHA_MOD(value uint32) {
	volatile.StoreUint32(&o.SR_FIX_ALPHA.Reg, volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg)&^(0x300)|value<<8)
}
func (o *PPA_Type) GetSR_FIX_ALPHA_SR_RX_ALPHA_MOD() uint32 {
	return (volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg) & 0x300) >> 8
}
func (o *PPA_Type) SetSR_FIX_ALPHA_SR_RX_ALPHA_INV(value uint32) {
	volatile.StoreUint32(&o.SR_FIX_ALPHA.Reg, volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg)&^(0x400)|value<<10)
}
func (o *PPA_Type) GetSR_FIX_ALPHA_SR_RX_ALPHA_INV() uint32 {
	return (volatile.LoadUint32(&o.SR_FIX_ALPHA.Reg) & 0x400) >> 10
}

// PPA.BLEND_TX_SIZE: Fix pixel filling mode image size register
func (o *PPA_Type) SetBLEND_TX_SIZE_BLEND_HB(value uint32) {
	volatile.StoreUint32(&o.BLEND_TX_SIZE.Reg, volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg)&^(0x3fff)|value)
}
func (o *PPA_Type) GetBLEND_TX_SIZE_BLEND_HB() uint32 {
	return volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg) & 0x3fff
}
func (o *PPA_Type) SetBLEND_TX_SIZE_BLEND_VB(value uint32) {
	volatile.StoreUint32(&o.BLEND_TX_SIZE.Reg, volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg)&^(0xfffc000)|value<<14)
}
func (o *PPA_Type) GetBLEND_TX_SIZE_BLEND_VB() uint32 {
	return (volatile.LoadUint32(&o.BLEND_TX_SIZE.Reg) & 0xfffc000) >> 14
}

// PPA.BLEND_FIX_ALPHA: Blending engine alpha override register
func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND0_RX_FIX_ALPHA(value uint32) {
	volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND0_RX_FIX_ALPHA() uint32 {
	return volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0xff
}
func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND1_RX_FIX_ALPHA(value uint32) {
	volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0xff00)|value<<8)
}
func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND1_RX_FIX_ALPHA() uint32 {
	return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0xff00) >> 8
}
func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_MOD(value uint32) {
	volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0x30000)|value<<16)
}
func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_MOD() uint32 {
	return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0x30000) >> 16
}
func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_MOD(value uint32) {
	volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0xc0000)|value<<18)
}
func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_MOD() uint32 {
	return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0xc0000) >> 18
}
func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_INV(value uint32) {
	volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0x100000)|value<<20)
}
func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND0_RX_ALPHA_INV() uint32 {
	return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0x100000) >> 20
}
func (o *PPA_Type) SetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_INV(value uint32) {
	volatile.StoreUint32(&o.BLEND_FIX_ALPHA.Reg, volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg)&^(0x200000)|value<<21)
}
func (o *PPA_Type) GetBLEND_FIX_ALPHA_BLEND1_RX_ALPHA_INV() uint32 {
	return (volatile.LoadUint32(&o.BLEND_FIX_ALPHA.Reg) & 0x200000) >> 21
}

// PPA.BLEND_RGB: RGB color register
func (o *PPA_Type) SetBLEND_RGB_BLEND1_RX_B(value uint32) {
	volatile.StoreUint32(&o.BLEND_RGB.Reg, volatile.LoadUint32(&o.BLEND_RGB.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetBLEND_RGB_BLEND1_RX_B() uint32 {
	return volatile.LoadUint32(&o.BLEND_RGB.Reg) & 0xff
}
func (o *PPA_Type) SetBLEND_RGB_BLEND1_RX_G(value uint32) {
	volatile.StoreUint32(&o.BLEND_RGB.Reg, volatile.LoadUint32(&o.BLEND_RGB.Reg)&^(0xff00)|value<<8)
}
func (o *PPA_Type) GetBLEND_RGB_BLEND1_RX_G() uint32 {
	return (volatile.LoadUint32(&o.BLEND_RGB.Reg) & 0xff00) >> 8
}
func (o *PPA_Type) SetBLEND_RGB_BLEND1_RX_R(value uint32) {
	volatile.StoreUint32(&o.BLEND_RGB.Reg, volatile.LoadUint32(&o.BLEND_RGB.Reg)&^(0xff0000)|value<<16)
}
func (o *PPA_Type) GetBLEND_RGB_BLEND1_RX_R() uint32 {
	return (volatile.LoadUint32(&o.BLEND_RGB.Reg) & 0xff0000) >> 16
}

// PPA.BLEND_FIX_PIXEL: Blending engine fix pixel register
func (o *PPA_Type) SetBLEND_FIX_PIXEL(value uint32) {
	volatile.StoreUint32(&o.BLEND_FIX_PIXEL.Reg, value)
}
func (o *PPA_Type) GetBLEND_FIX_PIXEL() uint32 {
	return volatile.LoadUint32(&o.BLEND_FIX_PIXEL.Reg)
}

// PPA.CK_FG_LOW: foreground color key lower threshold
func (o *PPA_Type) SetCK_FG_LOW_COLORKEY_FG_B_LOW(value uint32) {
	volatile.StoreUint32(&o.CK_FG_LOW.Reg, volatile.LoadUint32(&o.CK_FG_LOW.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetCK_FG_LOW_COLORKEY_FG_B_LOW() uint32 {
	return volatile.LoadUint32(&o.CK_FG_LOW.Reg) & 0xff
}
func (o *PPA_Type) SetCK_FG_LOW_COLORKEY_FG_G_LOW(value uint32) {
	volatile.StoreUint32(&o.CK_FG_LOW.Reg, volatile.LoadUint32(&o.CK_FG_LOW.Reg)&^(0xff00)|value<<8)
}
func (o *PPA_Type) GetCK_FG_LOW_COLORKEY_FG_G_LOW() uint32 {
	return (volatile.LoadUint32(&o.CK_FG_LOW.Reg) & 0xff00) >> 8
}
func (o *PPA_Type) SetCK_FG_LOW_COLORKEY_FG_R_LOW(value uint32) {
	volatile.StoreUint32(&o.CK_FG_LOW.Reg, volatile.LoadUint32(&o.CK_FG_LOW.Reg)&^(0xff0000)|value<<16)
}
func (o *PPA_Type) GetCK_FG_LOW_COLORKEY_FG_R_LOW() uint32 {
	return (volatile.LoadUint32(&o.CK_FG_LOW.Reg) & 0xff0000) >> 16
}

// PPA.CK_FG_HIGH: foreground color key higher threshold
func (o *PPA_Type) SetCK_FG_HIGH_COLORKEY_FG_B_HIGH(value uint32) {
	volatile.StoreUint32(&o.CK_FG_HIGH.Reg, volatile.LoadUint32(&o.CK_FG_HIGH.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetCK_FG_HIGH_COLORKEY_FG_B_HIGH() uint32 {
	return volatile.LoadUint32(&o.CK_FG_HIGH.Reg) & 0xff
}
func (o *PPA_Type) SetCK_FG_HIGH_COLORKEY_FG_G_HIGH(value uint32) {
	volatile.StoreUint32(&o.CK_FG_HIGH.Reg, volatile.LoadUint32(&o.CK_FG_HIGH.Reg)&^(0xff00)|value<<8)
}
func (o *PPA_Type) GetCK_FG_HIGH_COLORKEY_FG_G_HIGH() uint32 {
	return (volatile.LoadUint32(&o.CK_FG_HIGH.Reg) & 0xff00) >> 8
}
func (o *PPA_Type) SetCK_FG_HIGH_COLORKEY_FG_R_HIGH(value uint32) {
	volatile.StoreUint32(&o.CK_FG_HIGH.Reg, volatile.LoadUint32(&o.CK_FG_HIGH.Reg)&^(0xff0000)|value<<16)
}
func (o *PPA_Type) GetCK_FG_HIGH_COLORKEY_FG_R_HIGH() uint32 {
	return (volatile.LoadUint32(&o.CK_FG_HIGH.Reg) & 0xff0000) >> 16
}

// PPA.CK_BG_LOW: background color key lower threshold
func (o *PPA_Type) SetCK_BG_LOW_COLORKEY_BG_B_LOW(value uint32) {
	volatile.StoreUint32(&o.CK_BG_LOW.Reg, volatile.LoadUint32(&o.CK_BG_LOW.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetCK_BG_LOW_COLORKEY_BG_B_LOW() uint32 {
	return volatile.LoadUint32(&o.CK_BG_LOW.Reg) & 0xff
}
func (o *PPA_Type) SetCK_BG_LOW_COLORKEY_BG_G_LOW(value uint32) {
	volatile.StoreUint32(&o.CK_BG_LOW.Reg, volatile.LoadUint32(&o.CK_BG_LOW.Reg)&^(0xff00)|value<<8)
}
func (o *PPA_Type) GetCK_BG_LOW_COLORKEY_BG_G_LOW() uint32 {
	return (volatile.LoadUint32(&o.CK_BG_LOW.Reg) & 0xff00) >> 8
}
func (o *PPA_Type) SetCK_BG_LOW_COLORKEY_BG_R_LOW(value uint32) {
	volatile.StoreUint32(&o.CK_BG_LOW.Reg, volatile.LoadUint32(&o.CK_BG_LOW.Reg)&^(0xff0000)|value<<16)
}
func (o *PPA_Type) GetCK_BG_LOW_COLORKEY_BG_R_LOW() uint32 {
	return (volatile.LoadUint32(&o.CK_BG_LOW.Reg) & 0xff0000) >> 16
}

// PPA.CK_BG_HIGH: background color key higher threshold
func (o *PPA_Type) SetCK_BG_HIGH_COLORKEY_BG_B_HIGH(value uint32) {
	volatile.StoreUint32(&o.CK_BG_HIGH.Reg, volatile.LoadUint32(&o.CK_BG_HIGH.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetCK_BG_HIGH_COLORKEY_BG_B_HIGH() uint32 {
	return volatile.LoadUint32(&o.CK_BG_HIGH.Reg) & 0xff
}
func (o *PPA_Type) SetCK_BG_HIGH_COLORKEY_BG_G_HIGH(value uint32) {
	volatile.StoreUint32(&o.CK_BG_HIGH.Reg, volatile.LoadUint32(&o.CK_BG_HIGH.Reg)&^(0xff00)|value<<8)
}
func (o *PPA_Type) GetCK_BG_HIGH_COLORKEY_BG_G_HIGH() uint32 {
	return (volatile.LoadUint32(&o.CK_BG_HIGH.Reg) & 0xff00) >> 8
}
func (o *PPA_Type) SetCK_BG_HIGH_COLORKEY_BG_R_HIGH(value uint32) {
	volatile.StoreUint32(&o.CK_BG_HIGH.Reg, volatile.LoadUint32(&o.CK_BG_HIGH.Reg)&^(0xff0000)|value<<16)
}
func (o *PPA_Type) GetCK_BG_HIGH_COLORKEY_BG_R_HIGH() uint32 {
	return (volatile.LoadUint32(&o.CK_BG_HIGH.Reg) & 0xff0000) >> 16
}

// PPA.CK_DEFAULT: default value when foreground and background both in color key range
func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_DEFAULT_B(value uint32) {
	volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_DEFAULT_B() uint32 {
	return volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0xff
}
func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_DEFAULT_G(value uint32) {
	volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0xff00)|value<<8)
}
func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_DEFAULT_G() uint32 {
	return (volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0xff00) >> 8
}
func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_DEFAULT_R(value uint32) {
	volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0xff0000)|value<<16)
}
func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_DEFAULT_R() uint32 {
	return (volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0xff0000) >> 16
}
func (o *PPA_Type) SetCK_DEFAULT_COLORKEY_FG_BG_REVERSE(value uint32) {
	volatile.StoreUint32(&o.CK_DEFAULT.Reg, volatile.LoadUint32(&o.CK_DEFAULT.Reg)&^(0x1000000)|value<<24)
}
func (o *PPA_Type) GetCK_DEFAULT_COLORKEY_FG_BG_REVERSE() uint32 {
	return (volatile.LoadUint32(&o.CK_DEFAULT.Reg) & 0x1000000) >> 24
}

// PPA.SR_SCAL_ROTATE: Scaling and rotating coefficient register
func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_X_INT(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xff)|value)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_X_INT() uint32 {
	return volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xff
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_X_FRAG(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xf00)|value<<8)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_X_FRAG() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xf00) >> 8
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_Y_INT(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xff000)|value<<12)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_Y_INT() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xff000) >> 12
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_SCAL_Y_FRAG(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0xf00000)|value<<20)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_SCAL_Y_FRAG() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0xf00000) >> 20
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_ROTATE_ANGLE(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x3000000)|value<<24)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_ROTATE_ANGLE() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x3000000) >> 24
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SCAL_ROTATE_RST(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x4000000)|value<<26)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SCAL_ROTATE_RST() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x4000000) >> 26
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SCAL_ROTATE_START(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x8000000)|value<<27)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SCAL_ROTATE_START() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x8000000) >> 27
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_MIRROR_X(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x10000000)|value<<28)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_MIRROR_X() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x10000000) >> 28
}
func (o *PPA_Type) SetSR_SCAL_ROTATE_SR_MIRROR_Y(value uint32) {
	volatile.StoreUint32(&o.SR_SCAL_ROTATE.Reg, volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg)&^(0x20000000)|value<<29)
}
func (o *PPA_Type) GetSR_SCAL_ROTATE_SR_MIRROR_Y() uint32 {
	return (volatile.LoadUint32(&o.SR_SCAL_ROTATE.Reg) & 0x20000000) >> 29
}

// PPA.SR_MEM_PD: SR memory power done register
func (o *PPA_Type) SetSR_MEM_PD_SR_MEM_CLK_ENA(value uint32) {
	volatile.StoreUint32(&o.SR_MEM_PD.Reg, volatile.LoadUint32(&o.SR_MEM_PD.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetSR_MEM_PD_SR_MEM_CLK_ENA() uint32 {
	return volatile.LoadUint32(&o.SR_MEM_PD.Reg) & 0x1
}
func (o *PPA_Type) SetSR_MEM_PD_SR_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.SR_MEM_PD.Reg, volatile.LoadUint32(&o.SR_MEM_PD.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetSR_MEM_PD_SR_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.SR_MEM_PD.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetSR_MEM_PD_SR_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.SR_MEM_PD.Reg, volatile.LoadUint32(&o.SR_MEM_PD.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetSR_MEM_PD_SR_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.SR_MEM_PD.Reg) & 0x4) >> 2
}

// PPA.REG_CONF: Register clock enable register
func (o *PPA_Type) SetREG_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REG_CONF.Reg, volatile.LoadUint32(&o.REG_CONF.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetREG_CONF_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.REG_CONF.Reg) & 0x1
}

// PPA.CLUT_CNT: BLEND CLUT write counter register
func (o *PPA_Type) SetCLUT_CNT_BLEND0_CLUT_CNT(value uint32) {
	volatile.StoreUint32(&o.CLUT_CNT.Reg, volatile.LoadUint32(&o.CLUT_CNT.Reg)&^(0x1ff)|value)
}
func (o *PPA_Type) GetCLUT_CNT_BLEND0_CLUT_CNT() uint32 {
	return volatile.LoadUint32(&o.CLUT_CNT.Reg) & 0x1ff
}
func (o *PPA_Type) SetCLUT_CNT_BLEND1_CLUT_CNT(value uint32) {
	volatile.StoreUint32(&o.CLUT_CNT.Reg, volatile.LoadUint32(&o.CLUT_CNT.Reg)&^(0x3fe00)|value<<9)
}
func (o *PPA_Type) GetCLUT_CNT_BLEND1_CLUT_CNT() uint32 {
	return (volatile.LoadUint32(&o.CLUT_CNT.Reg) & 0x3fe00) >> 9
}

// PPA.BLEND_ST: Blending engine status register
func (o *PPA_Type) SetBLEND_ST_BLEND_SIZE_DIFF_ST(value uint32) {
	volatile.StoreUint32(&o.BLEND_ST.Reg, volatile.LoadUint32(&o.BLEND_ST.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetBLEND_ST_BLEND_SIZE_DIFF_ST() uint32 {
	return volatile.LoadUint32(&o.BLEND_ST.Reg) & 0x1
}

// PPA.SR_PARAM_ERR_ST: Scaling and rotating coefficient error register
func (o *PPA_Type) SetSR_PARAM_ERR_ST_TX_DSCR_VB_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_TX_DSCR_VB_ERR_ST() uint32 {
	return volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x1
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_TX_DSCR_HB_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_TX_DSCR_HB_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x2) >> 1
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_Y_RX_SCAL_EQUAL_0_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x4)|value<<2)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_Y_RX_SCAL_EQUAL_0_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x4) >> 2
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_RX_DSCR_VB_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x8)|value<<3)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_RX_DSCR_VB_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x8) >> 3
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_YDST_LEN_TOO_SAMLL_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x10)|value<<4)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_YDST_LEN_TOO_SAMLL_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x10) >> 4
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_YDST_LEN_TOO_LARGE_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x20)|value<<5)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_YDST_LEN_TOO_LARGE_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x20) >> 5
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_X_RX_SCAL_EQUAL_0_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x40)|value<<6)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_X_RX_SCAL_EQUAL_0_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x40) >> 6
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_RX_DSCR_HB_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x80)|value<<7)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_RX_DSCR_HB_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x80) >> 7
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_XDST_LEN_TOO_SAMLL_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x100)|value<<8)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_XDST_LEN_TOO_SAMLL_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x100) >> 8
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_XDST_LEN_TOO_LARGE_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x200)|value<<9)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_XDST_LEN_TOO_LARGE_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x200) >> 9
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_X_YUV420_RX_SCALE_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x400)|value<<10)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_X_YUV420_RX_SCALE_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x400) >> 10
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_Y_YUV420_RX_SCALE_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x800)|value<<11)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_Y_YUV420_RX_SCALE_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x800) >> 11
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_X_YUV420_TX_SCALE_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x1000)|value<<12)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_X_YUV420_TX_SCALE_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x1000) >> 12
}
func (o *PPA_Type) SetSR_PARAM_ERR_ST_Y_YUV420_TX_SCALE_ERR_ST(value uint32) {
	volatile.StoreUint32(&o.SR_PARAM_ERR_ST.Reg, volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg)&^(0x2000)|value<<13)
}
func (o *PPA_Type) GetSR_PARAM_ERR_ST_Y_YUV420_TX_SCALE_ERR_ST() uint32 {
	return (volatile.LoadUint32(&o.SR_PARAM_ERR_ST.Reg) & 0x2000) >> 13
}

// PPA.SR_STATUS: SR FSM register
func (o *PPA_Type) SetSR_STATUS_SR_RX_DSCR_SAMPLE_STATE(value uint32) {
	volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0x3)|value)
}
func (o *PPA_Type) GetSR_STATUS_SR_RX_DSCR_SAMPLE_STATE() uint32 {
	return volatile.LoadUint32(&o.SR_STATUS.Reg) & 0x3
}
func (o *PPA_Type) SetSR_STATUS_SR_RX_SCAN_STATE(value uint32) {
	volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0xc)|value<<2)
}
func (o *PPA_Type) GetSR_STATUS_SR_RX_SCAN_STATE() uint32 {
	return (volatile.LoadUint32(&o.SR_STATUS.Reg) & 0xc) >> 2
}
func (o *PPA_Type) SetSR_STATUS_SR_TX_DSCR_SAMPLE_STATE(value uint32) {
	volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0x30)|value<<4)
}
func (o *PPA_Type) GetSR_STATUS_SR_TX_DSCR_SAMPLE_STATE() uint32 {
	return (volatile.LoadUint32(&o.SR_STATUS.Reg) & 0x30) >> 4
}
func (o *PPA_Type) SetSR_STATUS_SR_TX_SCAN_STATE(value uint32) {
	volatile.StoreUint32(&o.SR_STATUS.Reg, volatile.LoadUint32(&o.SR_STATUS.Reg)&^(0x1c0)|value<<6)
}
func (o *PPA_Type) GetSR_STATUS_SR_TX_SCAN_STATE() uint32 {
	return (volatile.LoadUint32(&o.SR_STATUS.Reg) & 0x1c0) >> 6
}

// PPA.ECO_LOW: Reserved.
func (o *PPA_Type) SetECO_LOW(value uint32) {
	volatile.StoreUint32(&o.ECO_LOW.Reg, value)
}
func (o *PPA_Type) GetECO_LOW() uint32 {
	return volatile.LoadUint32(&o.ECO_LOW.Reg)
}

// PPA.ECO_HIGH: Reserved.
func (o *PPA_Type) SetECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.ECO_HIGH.Reg, value)
}
func (o *PPA_Type) GetECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.ECO_HIGH.Reg)
}

// PPA.ECO_CELL_CTRL: Reserved.
func (o *PPA_Type) SetECO_CELL_CTRL_RDN_RESULT(value uint32) {
	volatile.StoreUint32(&o.ECO_CELL_CTRL.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg)&^(0x1)|value)
}
func (o *PPA_Type) GetECO_CELL_CTRL_RDN_RESULT() uint32 {
	return volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg) & 0x1
}
func (o *PPA_Type) SetECO_CELL_CTRL_RDN_ENA(value uint32) {
	volatile.StoreUint32(&o.ECO_CELL_CTRL.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *PPA_Type) GetECO_CELL_CTRL_RDN_ENA() uint32 {
	return (volatile.LoadUint32(&o.ECO_CELL_CTRL.Reg) & 0x2) >> 1
}

// PPA.SRAM_CTRL: PPA SRAM Control Register
func (o *PPA_Type) SetSRAM_CTRL_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.SRAM_CTRL.Reg, volatile.LoadUint32(&o.SRAM_CTRL.Reg)&^(0x3fff)|value)
}
func (o *PPA_Type) GetSRAM_CTRL_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.SRAM_CTRL.Reg) & 0x3fff
}

// PPA.DATE: PPA Version register
func (o *PPA_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *PPA_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// PVT Peripheral
type PVT_Type struct {
	PMUP_BITMAP_HIGH0             volatile.Register32 // 0x0
	PMUP_BITMAP_HIGH1             volatile.Register32 // 0x4
	PMUP_BITMAP_HIGH2             volatile.Register32 // 0x8
	PMUP_BITMAP_HIGH3             volatile.Register32 // 0xC
	PMUP_BITMAP_HIGH4             volatile.Register32 // 0x10
	PMUP_BITMAP_LOW0              volatile.Register32 // 0x14
	PMUP_BITMAP_LOW1              volatile.Register32 // 0x18
	PMUP_BITMAP_LOW2              volatile.Register32 // 0x1C
	PMUP_BITMAP_LOW3              volatile.Register32 // 0x20
	PMUP_BITMAP_LOW4              volatile.Register32 // 0x24
	PMUP_DRV_CFG                  volatile.Register32 // 0x28
	PMUP_CHANNEL_CFG              volatile.Register32 // 0x2C
	CLK_CFG                       volatile.Register32 // 0x30
	DBIAS_CHANNEL_SEL0            volatile.Register32 // 0x34
	DBIAS_CHANNEL_SEL1            volatile.Register32 // 0x38
	DBIAS_CHANNEL0_SEL            volatile.Register32 // 0x3C
	DBIAS_CHANNEL1_SEL            volatile.Register32 // 0x40
	DBIAS_CHANNEL2_SEL            volatile.Register32 // 0x44
	DBIAS_CHANNEL3_SEL            volatile.Register32 // 0x48
	DBIAS_CHANNEL4_SEL            volatile.Register32 // 0x4C
	DBIAS_CMD0                    volatile.Register32 // 0x50
	DBIAS_CMD1                    volatile.Register32 // 0x54
	DBIAS_CMD2                    volatile.Register32 // 0x58
	DBIAS_CMD3                    volatile.Register32 // 0x5C
	DBIAS_CMD4                    volatile.Register32 // 0x60
	DBIAS_TIMER                   volatile.Register32 // 0x64
	COMB_PD_SITE0_UNIT0_VT0_CONF1 volatile.Register32 // 0x68
	COMB_PD_SITE0_UNIT1_VT0_CONF1 volatile.Register32 // 0x6C
	COMB_PD_SITE0_UNIT2_VT0_CONF1 volatile.Register32 // 0x70
	COMB_PD_SITE0_UNIT3_VT0_CONF1 volatile.Register32 // 0x74
	COMB_PD_SITE0_UNIT0_VT1_CONF1 volatile.Register32 // 0x78
	COMB_PD_SITE0_UNIT1_VT1_CONF1 volatile.Register32 // 0x7C
	COMB_PD_SITE0_UNIT2_VT1_CONF1 volatile.Register32 // 0x80
	COMB_PD_SITE0_UNIT3_VT1_CONF1 volatile.Register32 // 0x84
	COMB_PD_SITE0_UNIT0_VT2_CONF1 volatile.Register32 // 0x88
	COMB_PD_SITE0_UNIT1_VT2_CONF1 volatile.Register32 // 0x8C
	COMB_PD_SITE0_UNIT2_VT2_CONF1 volatile.Register32 // 0x90
	COMB_PD_SITE0_UNIT3_VT2_CONF1 volatile.Register32 // 0x94
	COMB_PD_SITE1_UNIT0_VT0_CONF1 volatile.Register32 // 0x98
	COMB_PD_SITE1_UNIT1_VT0_CONF1 volatile.Register32 // 0x9C
	COMB_PD_SITE1_UNIT2_VT0_CONF1 volatile.Register32 // 0xA0
	COMB_PD_SITE1_UNIT3_VT0_CONF1 volatile.Register32 // 0xA4
	COMB_PD_SITE1_UNIT0_VT1_CONF1 volatile.Register32 // 0xA8
	COMB_PD_SITE1_UNIT1_VT1_CONF1 volatile.Register32 // 0xAC
	COMB_PD_SITE1_UNIT2_VT1_CONF1 volatile.Register32 // 0xB0
	COMB_PD_SITE1_UNIT3_VT1_CONF1 volatile.Register32 // 0xB4
	COMB_PD_SITE1_UNIT0_VT2_CONF1 volatile.Register32 // 0xB8
	COMB_PD_SITE1_UNIT1_VT2_CONF1 volatile.Register32 // 0xBC
	COMB_PD_SITE1_UNIT2_VT2_CONF1 volatile.Register32 // 0xC0
	COMB_PD_SITE1_UNIT3_VT2_CONF1 volatile.Register32 // 0xC4
	COMB_PD_SITE2_UNIT0_VT0_CONF1 volatile.Register32 // 0xC8
	COMB_PD_SITE2_UNIT1_VT0_CONF1 volatile.Register32 // 0xCC
	COMB_PD_SITE2_UNIT2_VT0_CONF1 volatile.Register32 // 0xD0
	COMB_PD_SITE2_UNIT3_VT0_CONF1 volatile.Register32 // 0xD4
	COMB_PD_SITE2_UNIT0_VT1_CONF1 volatile.Register32 // 0xD8
	COMB_PD_SITE2_UNIT1_VT1_CONF1 volatile.Register32 // 0xDC
	COMB_PD_SITE2_UNIT2_VT1_CONF1 volatile.Register32 // 0xE0
	COMB_PD_SITE2_UNIT3_VT1_CONF1 volatile.Register32 // 0xE4
	COMB_PD_SITE2_UNIT0_VT2_CONF1 volatile.Register32 // 0xE8
	COMB_PD_SITE2_UNIT1_VT2_CONF1 volatile.Register32 // 0xEC
	COMB_PD_SITE2_UNIT2_VT2_CONF1 volatile.Register32 // 0xF0
	COMB_PD_SITE2_UNIT3_VT2_CONF1 volatile.Register32 // 0xF4
	COMB_PD_SITE3_UNIT0_VT0_CONF1 volatile.Register32 // 0xF8
	COMB_PD_SITE3_UNIT1_VT0_CONF1 volatile.Register32 // 0xFC
	COMB_PD_SITE3_UNIT2_VT0_CONF1 volatile.Register32 // 0x100
	COMB_PD_SITE3_UNIT3_VT0_CONF1 volatile.Register32 // 0x104
	COMB_PD_SITE3_UNIT0_VT1_CONF1 volatile.Register32 // 0x108
	COMB_PD_SITE3_UNIT1_VT1_CONF1 volatile.Register32 // 0x10C
	COMB_PD_SITE3_UNIT2_VT1_CONF1 volatile.Register32 // 0x110
	COMB_PD_SITE3_UNIT3_VT1_CONF1 volatile.Register32 // 0x114
	COMB_PD_SITE3_UNIT0_VT2_CONF1 volatile.Register32 // 0x118
	COMB_PD_SITE3_UNIT1_VT2_CONF1 volatile.Register32 // 0x11C
	COMB_PD_SITE3_UNIT2_VT2_CONF1 volatile.Register32 // 0x120
	COMB_PD_SITE3_UNIT3_VT2_CONF1 volatile.Register32 // 0x124
	COMB_PD_SITE0_UNIT0_VT0_CONF2 volatile.Register32 // 0x128
	COMB_PD_SITE0_UNIT1_VT0_CONF2 volatile.Register32 // 0x12C
	COMB_PD_SITE0_UNIT2_VT0_CONF2 volatile.Register32 // 0x130
	COMB_PD_SITE0_UNIT3_VT0_CONF2 volatile.Register32 // 0x134
	COMB_PD_SITE0_UNIT0_VT1_CONF2 volatile.Register32 // 0x138
	COMB_PD_SITE0_UNIT1_VT1_CONF2 volatile.Register32 // 0x13C
	COMB_PD_SITE0_UNIT2_VT1_CONF2 volatile.Register32 // 0x140
	COMB_PD_SITE0_UNIT3_VT1_CONF2 volatile.Register32 // 0x144
	COMB_PD_SITE0_UNIT0_VT2_CONF2 volatile.Register32 // 0x148
	COMB_PD_SITE0_UNIT1_VT2_CONF2 volatile.Register32 // 0x14C
	COMB_PD_SITE0_UNIT2_VT2_CONF2 volatile.Register32 // 0x150
	COMB_PD_SITE0_UNIT3_VT2_CONF2 volatile.Register32 // 0x154
	COMB_PD_SITE1_UNIT0_VT0_CONF2 volatile.Register32 // 0x158
	COMB_PD_SITE1_UNIT1_VT0_CONF2 volatile.Register32 // 0x15C
	COMB_PD_SITE1_UNIT2_VT0_CONF2 volatile.Register32 // 0x160
	COMB_PD_SITE1_UNIT3_VT0_CONF2 volatile.Register32 // 0x164
	COMB_PD_SITE1_UNIT0_VT1_CONF2 volatile.Register32 // 0x168
	COMB_PD_SITE1_UNIT1_VT1_CONF2 volatile.Register32 // 0x16C
	COMB_PD_SITE1_UNIT2_VT1_CONF2 volatile.Register32 // 0x170
	COMB_PD_SITE1_UNIT3_VT1_CONF2 volatile.Register32 // 0x174
	COMB_PD_SITE1_UNIT0_VT2_CONF2 volatile.Register32 // 0x178
	COMB_PD_SITE1_UNIT1_VT2_CONF2 volatile.Register32 // 0x17C
	COMB_PD_SITE1_UNIT2_VT2_CONF2 volatile.Register32 // 0x180
	COMB_PD_SITE1_UNIT3_VT2_CONF2 volatile.Register32 // 0x184
	COMB_PD_SITE2_UNIT0_VT0_CONF2 volatile.Register32 // 0x188
	COMB_PD_SITE2_UNIT1_VT0_CONF2 volatile.Register32 // 0x18C
	COMB_PD_SITE2_UNIT2_VT0_CONF2 volatile.Register32 // 0x190
	COMB_PD_SITE2_UNIT3_VT0_CONF2 volatile.Register32 // 0x194
	COMB_PD_SITE2_UNIT0_VT1_CONF2 volatile.Register32 // 0x198
	COMB_PD_SITE2_UNIT1_VT1_CONF2 volatile.Register32 // 0x19C
	COMB_PD_SITE2_UNIT2_VT1_CONF2 volatile.Register32 // 0x1A0
	COMB_PD_SITE2_UNIT3_VT1_CONF2 volatile.Register32 // 0x1A4
	COMB_PD_SITE2_UNIT0_VT2_CONF2 volatile.Register32 // 0x1A8
	COMB_PD_SITE2_UNIT1_VT2_CONF2 volatile.Register32 // 0x1AC
	COMB_PD_SITE2_UNIT2_VT2_CONF2 volatile.Register32 // 0x1B0
	COMB_PD_SITE2_UNIT3_VT2_CONF2 volatile.Register32 // 0x1B4
	COMB_PD_SITE3_UNIT0_VT0_CONF2 volatile.Register32 // 0x1B8
	COMB_PD_SITE3_UNIT1_VT0_CONF2 volatile.Register32 // 0x1BC
	COMB_PD_SITE3_UNIT2_VT0_CONF2 volatile.Register32 // 0x1C0
	COMB_PD_SITE3_UNIT3_VT0_CONF2 volatile.Register32 // 0x1C4
	COMB_PD_SITE3_UNIT0_VT1_CONF2 volatile.Register32 // 0x1C8
	COMB_PD_SITE3_UNIT1_VT1_CONF2 volatile.Register32 // 0x1CC
	COMB_PD_SITE3_UNIT2_VT1_CONF2 volatile.Register32 // 0x1D0
	COMB_PD_SITE3_UNIT3_VT1_CONF2 volatile.Register32 // 0x1D4
	COMB_PD_SITE3_UNIT0_VT2_CONF2 volatile.Register32 // 0x1D8
	COMB_PD_SITE3_UNIT1_VT2_CONF2 volatile.Register32 // 0x1DC
	COMB_PD_SITE3_UNIT2_VT2_CONF2 volatile.Register32 // 0x1E0
	COMB_PD_SITE3_UNIT3_VT2_CONF2 volatile.Register32 // 0x1E4
	VALUE_UPDATE                  volatile.Register32 // 0x1E8
	_                             [3600]byte
	DATE                          volatile.Register32 // 0xFFC
}

// PVT.PMUP_BITMAP_HIGH0: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_HIGH0(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_HIGH0.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_HIGH0() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH0.Reg)
}

// PVT.PMUP_BITMAP_HIGH1: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_HIGH1(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_HIGH1.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_HIGH1() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH1.Reg)
}

// PVT.PMUP_BITMAP_HIGH2: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_HIGH2(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_HIGH2.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_HIGH2() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH2.Reg)
}

// PVT.PMUP_BITMAP_HIGH3: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_HIGH3(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_HIGH3.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_HIGH3() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH3.Reg)
}

// PVT.PMUP_BITMAP_HIGH4: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_HIGH4(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_HIGH4.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_HIGH4() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_HIGH4.Reg)
}

// PVT.PMUP_BITMAP_LOW0: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_LOW0(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_LOW0.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_LOW0() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_LOW0.Reg)
}

// PVT.PMUP_BITMAP_LOW1: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_LOW1(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_LOW1.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_LOW1() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_LOW1.Reg)
}

// PVT.PMUP_BITMAP_LOW2: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_LOW2(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_LOW2.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_LOW2() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_LOW2.Reg)
}

// PVT.PMUP_BITMAP_LOW3: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_LOW3(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_LOW3.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_LOW3() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_LOW3.Reg)
}

// PVT.PMUP_BITMAP_LOW4: select valid pvt channel
func (o *PVT_Type) SetPMUP_BITMAP_LOW4(value uint32) {
	volatile.StoreUint32(&o.PMUP_BITMAP_LOW4.Reg, value)
}
func (o *PVT_Type) GetPMUP_BITMAP_LOW4() uint32 {
	return volatile.LoadUint32(&o.PMUP_BITMAP_LOW4.Reg)
}

// PVT.PMUP_DRV_CFG: configure pump drv
func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_EN(value uint32) {
	volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x200)|value<<9)
}
func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_EN() uint32 {
	return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x200) >> 9
}
func (o *PVT_Type) SetPMUP_DRV_CFG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x400)|value<<10)
}
func (o *PVT_Type) GetPMUP_DRV_CFG_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x400) >> 10
}
func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV4(value uint32) {
	volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x7800)|value<<11)
}
func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV4() uint32 {
	return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x7800) >> 11
}
func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV3(value uint32) {
	volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x78000)|value<<15)
}
func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV3() uint32 {
	return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x78000) >> 15
}
func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV2(value uint32) {
	volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x780000)|value<<19)
}
func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV2() uint32 {
	return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x780000) >> 19
}
func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV1(value uint32) {
	volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x7800000)|value<<23)
}
func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV1() uint32 {
	return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x7800000) >> 23
}
func (o *PVT_Type) SetPMUP_DRV_CFG_PUMP_DRV0(value uint32) {
	volatile.StoreUint32(&o.PMUP_DRV_CFG.Reg, volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg)&^(0x78000000)|value<<27)
}
func (o *PVT_Type) GetPMUP_DRV_CFG_PUMP_DRV0() uint32 {
	return (volatile.LoadUint32(&o.PMUP_DRV_CFG.Reg) & 0x78000000) >> 27
}

// PVT.PMUP_CHANNEL_CFG: configure the code of valid pump channel code
func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE4(value uint32) {
	volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0xf80)|value<<7)
}
func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE4() uint32 {
	return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0xf80) >> 7
}
func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE3(value uint32) {
	volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0x1f000)|value<<12)
}
func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE3() uint32 {
	return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0x1f000) >> 12
}
func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE2(value uint32) {
	volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0x3e0000)|value<<17)
}
func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE2() uint32 {
	return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0x3e0000) >> 17
}
func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE1(value uint32) {
	volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0x7c00000)|value<<22)
}
func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE1() uint32 {
	return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0x7c00000) >> 22
}
func (o *PVT_Type) SetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE0(value uint32) {
	volatile.StoreUint32(&o.PMUP_CHANNEL_CFG.Reg, volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg)&^(0xf8000000)|value<<27)
}
func (o *PVT_Type) GetPMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE0() uint32 {
	return (volatile.LoadUint32(&o.PMUP_CHANNEL_CFG.Reg) & 0xf8000000) >> 27
}

// PVT.CLK_CFG: configure pvt clk
func (o *PVT_Type) SetCLK_CFG_PUMP_CLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0xff)|value)
}
func (o *PVT_Type) GetCLK_CFG_PUMP_CLK_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.CLK_CFG.Reg) & 0xff
}
func (o *PVT_Type) SetCLK_CFG_MONITOR_CLK_PVT_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0x100)|value<<8)
}
func (o *PVT_Type) GetCLK_CFG_MONITOR_CLK_PVT_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK_CFG.Reg) & 0x100) >> 8
}
func (o *PVT_Type) SetCLK_CFG_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.CLK_CFG.Reg, volatile.LoadUint32(&o.CLK_CFG.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCLK_CFG_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.CLK_CFG.Reg) & 0x80000000) >> 31
}

// PVT.DBIAS_CHANNEL_SEL0: needs desc
func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL3_SEL(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0x7f0)|value<<4)
}
func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL3_SEL() uint32 {
	return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0x7f0) >> 4
}
func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL2_SEL(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0x3f800)|value<<11)
}
func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL2_SEL() uint32 {
	return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0x3f800) >> 11
}
func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL1_SEL(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0x1fc0000)|value<<18)
}
func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL1_SEL() uint32 {
	return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0x1fc0000) >> 18
}
func (o *PVT_Type) SetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL0_SEL(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL0.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg)&^(0xfe000000)|value<<25)
}
func (o *PVT_Type) GetDBIAS_CHANNEL_SEL0_DBIAS_CHANNEL0_SEL() uint32 {
	return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL0.Reg) & 0xfe000000) >> 25
}

// PVT.DBIAS_CHANNEL_SEL1: needs desc
func (o *PVT_Type) SetDBIAS_CHANNEL_SEL1_DBIAS_CHANNEL4_SEL(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL_SEL1.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL1.Reg)&^(0xfe000000)|value<<25)
}
func (o *PVT_Type) GetDBIAS_CHANNEL_SEL1_DBIAS_CHANNEL4_SEL() uint32 {
	return (volatile.LoadUint32(&o.DBIAS_CHANNEL_SEL1.Reg) & 0xfe000000) >> 25
}

// PVT.DBIAS_CHANNEL0_SEL: needs desc
func (o *PVT_Type) SetDBIAS_CHANNEL0_SEL_DBIAS_CHANNEL0_CFG(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL0_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL0_SEL.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CHANNEL0_SEL_DBIAS_CHANNEL0_CFG() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CHANNEL0_SEL.Reg) & 0x1ffff
}

// PVT.DBIAS_CHANNEL1_SEL: needs desc
func (o *PVT_Type) SetDBIAS_CHANNEL1_SEL_DBIAS_CHANNEL1_CFG(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL1_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL1_SEL.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CHANNEL1_SEL_DBIAS_CHANNEL1_CFG() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CHANNEL1_SEL.Reg) & 0x1ffff
}

// PVT.DBIAS_CHANNEL2_SEL: needs desc
func (o *PVT_Type) SetDBIAS_CHANNEL2_SEL_DBIAS_CHANNEL2_CFG(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL2_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL2_SEL.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CHANNEL2_SEL_DBIAS_CHANNEL2_CFG() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CHANNEL2_SEL.Reg) & 0x1ffff
}

// PVT.DBIAS_CHANNEL3_SEL: needs desc
func (o *PVT_Type) SetDBIAS_CHANNEL3_SEL_DBIAS_CHANNEL3_CFG(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL3_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL3_SEL.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CHANNEL3_SEL_DBIAS_CHANNEL3_CFG() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CHANNEL3_SEL.Reg) & 0x1ffff
}

// PVT.DBIAS_CHANNEL4_SEL: needs desc
func (o *PVT_Type) SetDBIAS_CHANNEL4_SEL_DBIAS_CHANNEL4_CFG(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CHANNEL4_SEL.Reg, volatile.LoadUint32(&o.DBIAS_CHANNEL4_SEL.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CHANNEL4_SEL_DBIAS_CHANNEL4_CFG() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CHANNEL4_SEL.Reg) & 0x1ffff
}

// PVT.DBIAS_CMD0: needs desc
func (o *PVT_Type) SetDBIAS_CMD0(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CMD0.Reg, volatile.LoadUint32(&o.DBIAS_CMD0.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CMD0() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CMD0.Reg) & 0x1ffff
}

// PVT.DBIAS_CMD1: needs desc
func (o *PVT_Type) SetDBIAS_CMD1(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CMD1.Reg, volatile.LoadUint32(&o.DBIAS_CMD1.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CMD1() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CMD1.Reg) & 0x1ffff
}

// PVT.DBIAS_CMD2: needs desc
func (o *PVT_Type) SetDBIAS_CMD2(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CMD2.Reg, volatile.LoadUint32(&o.DBIAS_CMD2.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CMD2() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CMD2.Reg) & 0x1ffff
}

// PVT.DBIAS_CMD3: needs desc
func (o *PVT_Type) SetDBIAS_CMD3(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CMD3.Reg, volatile.LoadUint32(&o.DBIAS_CMD3.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CMD3() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CMD3.Reg) & 0x1ffff
}

// PVT.DBIAS_CMD4: needs desc
func (o *PVT_Type) SetDBIAS_CMD4(value uint32) {
	volatile.StoreUint32(&o.DBIAS_CMD4.Reg, volatile.LoadUint32(&o.DBIAS_CMD4.Reg)&^(0x1ffff)|value)
}
func (o *PVT_Type) GetDBIAS_CMD4() uint32 {
	return volatile.LoadUint32(&o.DBIAS_CMD4.Reg) & 0x1ffff
}

// PVT.DBIAS_TIMER: needs desc
func (o *PVT_Type) SetDBIAS_TIMER_TIMER_TARGET(value uint32) {
	volatile.StoreUint32(&o.DBIAS_TIMER.Reg, volatile.LoadUint32(&o.DBIAS_TIMER.Reg)&^(0x7fff8000)|value<<15)
}
func (o *PVT_Type) GetDBIAS_TIMER_TIMER_TARGET() uint32 {
	return (volatile.LoadUint32(&o.DBIAS_TIMER.Reg) & 0x7fff8000) >> 15
}
func (o *PVT_Type) SetDBIAS_TIMER_TIMER_EN(value uint32) {
	volatile.StoreUint32(&o.DBIAS_TIMER.Reg, volatile.LoadUint32(&o.DBIAS_TIMER.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetDBIAS_TIMER_TIMER_EN() uint32 {
	return (volatile.LoadUint32(&o.DBIAS_TIMER.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT0_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT1_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT2_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT3_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT0_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT1_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT2_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT3_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT0_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT1_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT2_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT3_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT0_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT1_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT2_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT3_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT0_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT1_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT2_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT3_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT0_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT1_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT2_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE1_UNIT3_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT0_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT1_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT2_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT3_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT0_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT1_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT2_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT3_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT0_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT1_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT2_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE2_UNIT3_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT0_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT1_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT2_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT3_VT0_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT0_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT1_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT2_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT3_VT1_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT0_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT1_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT2_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE3_UNIT3_VT2_CONF1: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x2) >> 1
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x3fc)|value<<2)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x3fc) >> 2
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x7f800000)|value<<23)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x7f800000) >> 23
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg)&^(0x80000000)|value<<31)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF1.Reg) & 0x80000000) >> 31
}

// PVT.COMB_PD_SITE0_UNIT0_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT1_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT2_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT3_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT0_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT1_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT2_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT3_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT0_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT1_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT2_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE0_UNIT3_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE0_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE0_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE0_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT0_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT1_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT2_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT3_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT0_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT1_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT2_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT3_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT0_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT1_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT2_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE1_UNIT3_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE1_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE1_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE1_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT0_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT1_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT2_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT3_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT0_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT1_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT2_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT3_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT0_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT1_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT2_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE2_UNIT3_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE2_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE2_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE2_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT0_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT1_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT2_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT3_VT0_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT0_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT0_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT1_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT2_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT3_VT1_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT1_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT0_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT0_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT1_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT1_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT2_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT2_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.COMB_PD_SITE3_UNIT3_VT2_CONF2: needs desc
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg)&^(0x3)|value)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3() uint32 {
	return volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg) & 0x3
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg)&^(0x8000)|value<<15)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg) & 0x8000) >> 15
}
func (o *PVT_Type) SetCOMB_PD_SITE3_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3(value uint32) {
	volatile.StoreUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg, volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *PVT_Type) GetCOMB_PD_SITE3_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3() uint32 {
	return (volatile.LoadUint32(&o.COMB_PD_SITE3_UNIT3_VT2_CONF2.Reg) & 0xffff0000) >> 16
}

// PVT.VALUE_UPDATE: needs field desc
func (o *PVT_Type) SetVALUE_UPDATE(value uint32) {
	volatile.StoreUint32(&o.VALUE_UPDATE.Reg, volatile.LoadUint32(&o.VALUE_UPDATE.Reg)&^(0x1)|value)
}
func (o *PVT_Type) GetVALUE_UPDATE() uint32 {
	return volatile.LoadUint32(&o.VALUE_UPDATE.Reg) & 0x1
}
func (o *PVT_Type) SetVALUE_UPDATE_BYPASS(value uint32) {
	volatile.StoreUint32(&o.VALUE_UPDATE.Reg, volatile.LoadUint32(&o.VALUE_UPDATE.Reg)&^(0x2)|value<<1)
}
func (o *PVT_Type) GetVALUE_UPDATE_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.VALUE_UPDATE.Reg) & 0x2) >> 1
}

// PVT.DATE: version register
func (o *PVT_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *PVT_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// Remote Control
type RMT_Type struct {
	TX_CH0DATA        volatile.Register32 // 0x0
	TX_CH1DATA        volatile.Register32 // 0x4
	TX_CH2DATA        volatile.Register32 // 0x8
	TX_CH3DATA        volatile.Register32 // 0xC
	RX_CH0DATA        volatile.Register32 // 0x10
	RX_CH1DATA        volatile.Register32 // 0x14
	RX_CH2DATA        volatile.Register32 // 0x18
	RX_CH3DATA        volatile.Register32 // 0x1C
	TX_CH0CONF0       volatile.Register32 // 0x20
	TX_CH1CONF0       volatile.Register32 // 0x24
	TX_CH2CONF0       volatile.Register32 // 0x28
	TX_CH3CONF0       volatile.Register32 // 0x2C
	RX_CH0CONF0       volatile.Register32 // 0x30
	RX_CH0CONF1       volatile.Register32 // 0x34
	RX_CH1CONF0       volatile.Register32 // 0x38
	RX_CH1CONF1       volatile.Register32 // 0x3C
	RX_CH2CONF0       volatile.Register32 // 0x40
	RX_CH2CONF1       volatile.Register32 // 0x44
	RX_CH3CONF0       volatile.Register32 // 0x48
	RX_CH3CONF1       volatile.Register32 // 0x4C
	TX_CH0STATUS      volatile.Register32 // 0x50
	TX_CH1STATUS      volatile.Register32 // 0x54
	TX_CH2STATUS      volatile.Register32 // 0x58
	TX_CH3STATUS      volatile.Register32 // 0x5C
	RX_CH0STATUS      volatile.Register32 // 0x60
	RX_CH1STATUS      volatile.Register32 // 0x64
	RX_CH2STATUS      volatile.Register32 // 0x68
	RX_CH3STATUS      volatile.Register32 // 0x6C
	INT_RAW           volatile.Register32 // 0x70
	INT_ST            volatile.Register32 // 0x74
	INT_ENA           volatile.Register32 // 0x78
	INT_CLR           volatile.Register32 // 0x7C
	CH0CARRIER_DUTY   volatile.Register32 // 0x80
	CH1CARRIER_DUTY   volatile.Register32 // 0x84
	CH2CARRIER_DUTY   volatile.Register32 // 0x88
	CH3CARRIER_DUTY   volatile.Register32 // 0x8C
	CH0_RX_CARRIER_RM volatile.Register32 // 0x90
	CH1_RX_CARRIER_RM volatile.Register32 // 0x94
	CH2_RX_CARRIER_RM volatile.Register32 // 0x98
	CH3_RX_CARRIER_RM volatile.Register32 // 0x9C
	CH0_TX_LIM        volatile.Register32 // 0xA0
	CH1_TX_LIM        volatile.Register32 // 0xA4
	CH2_TX_LIM        volatile.Register32 // 0xA8
	CH3_TX_LIM        volatile.Register32 // 0xAC
	CH0_RX_LIM        volatile.Register32 // 0xB0
	CH1_RX_LIM        volatile.Register32 // 0xB4
	CH2_RX_LIM        volatile.Register32 // 0xB8
	CH3_RX_LIM        volatile.Register32 // 0xBC
	SYS_CONF          volatile.Register32 // 0xC0
	TX_SIM            volatile.Register32 // 0xC4
	REF_CNT_RST       volatile.Register32 // 0xC8
	DATE              volatile.Register32 // 0xCC
}

// RMT.TX_CH0DATA: The read and write data register for CHANNEL%s by apb fifo access.
func (o *RMT_Type) SetTX_CH0DATA(value uint32) {
	volatile.StoreUint32(&o.TX_CH0DATA.Reg, value)
}
func (o *RMT_Type) GetTX_CH0DATA() uint32 {
	return volatile.LoadUint32(&o.TX_CH0DATA.Reg)
}

// RMT.TX_CH1DATA: The read and write data register for CHANNEL%s by apb fifo access.
func (o *RMT_Type) SetTX_CH1DATA(value uint32) {
	volatile.StoreUint32(&o.TX_CH1DATA.Reg, value)
}
func (o *RMT_Type) GetTX_CH1DATA() uint32 {
	return volatile.LoadUint32(&o.TX_CH1DATA.Reg)
}

// RMT.TX_CH2DATA: The read and write data register for CHANNEL%s by apb fifo access.
func (o *RMT_Type) SetTX_CH2DATA(value uint32) {
	volatile.StoreUint32(&o.TX_CH2DATA.Reg, value)
}
func (o *RMT_Type) GetTX_CH2DATA() uint32 {
	return volatile.LoadUint32(&o.TX_CH2DATA.Reg)
}

// RMT.TX_CH3DATA: The read and write data register for CHANNEL%s by apb fifo access.
func (o *RMT_Type) SetTX_CH3DATA(value uint32) {
	volatile.StoreUint32(&o.TX_CH3DATA.Reg, value)
}
func (o *RMT_Type) GetTX_CH3DATA() uint32 {
	return volatile.LoadUint32(&o.TX_CH3DATA.Reg)
}

// RMT.RX_CH0DATA: The read and write data register for CHANNEL$n by apb fifo access.
func (o *RMT_Type) SetRX_CH0DATA(value uint32) {
	volatile.StoreUint32(&o.RX_CH0DATA.Reg, value)
}
func (o *RMT_Type) GetRX_CH0DATA() uint32 {
	return volatile.LoadUint32(&o.RX_CH0DATA.Reg)
}

// RMT.RX_CH1DATA: The read and write data register for CHANNEL$n by apb fifo access.
func (o *RMT_Type) SetRX_CH1DATA(value uint32) {
	volatile.StoreUint32(&o.RX_CH1DATA.Reg, value)
}
func (o *RMT_Type) GetRX_CH1DATA() uint32 {
	return volatile.LoadUint32(&o.RX_CH1DATA.Reg)
}

// RMT.RX_CH2DATA: The read and write data register for CHANNEL$n by apb fifo access.
func (o *RMT_Type) SetRX_CH2DATA(value uint32) {
	volatile.StoreUint32(&o.RX_CH2DATA.Reg, value)
}
func (o *RMT_Type) GetRX_CH2DATA() uint32 {
	return volatile.LoadUint32(&o.RX_CH2DATA.Reg)
}

// RMT.RX_CH3DATA: The read and write data register for CHANNEL$n by apb fifo access.
func (o *RMT_Type) SetRX_CH3DATA(value uint32) {
	volatile.StoreUint32(&o.RX_CH3DATA.Reg, value)
}
func (o *RMT_Type) GetRX_CH3DATA() uint32 {
	return volatile.LoadUint32(&o.RX_CH3DATA.Reg)
}

// RMT.TX_CH0CONF0: Channel %s configure register 0
func (o *RMT_Type) SetTX_CH0CONF0_TX_START_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetTX_CH0CONF0_TX_START_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x1
}
func (o *RMT_Type) SetTX_CH0CONF0_MEM_RD_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetTX_CH0CONF0_MEM_RD_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetTX_CH0CONF0_APB_MEM_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetTX_CH0CONF0_APB_MEM_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetTX_CH0CONF0_TX_CONTI_MODE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetTX_CH0CONF0_TX_CONTI_MODE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetTX_CH0CONF0_MEM_TX_WRAP_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetTX_CH0CONF0_MEM_TX_WRAP_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetTX_CH0CONF0_IDLE_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetTX_CH0CONF0_IDLE_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetTX_CH0CONF0_IDLE_OUT_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetTX_CH0CONF0_IDLE_OUT_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetTX_CH0CONF0_TX_STOP_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetTX_CH0CONF0_TX_STOP_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetTX_CH0CONF0_DIV_CNT_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0xff00)|value<<8)
}
func (o *RMT_Type) GetTX_CH0CONF0_DIV_CNT_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0xff00) >> 8
}
func (o *RMT_Type) SetTX_CH0CONF0_MEM_SIZE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0xf0000)|value<<16)
}
func (o *RMT_Type) GetTX_CH0CONF0_MEM_SIZE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0xf0000) >> 16
}
func (o *RMT_Type) SetTX_CH0CONF0_CARRIER_EFF_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetTX_CH0CONF0_CARRIER_EFF_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetTX_CH0CONF0_CARRIER_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetTX_CH0CONF0_CARRIER_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetTX_CH0CONF0_CARRIER_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetTX_CH0CONF0_CARRIER_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetTX_CH0CONF0_AFIFO_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetTX_CH0CONF0_AFIFO_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetTX_CH0CONF0_CONF_UPDATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0CONF0.Reg, volatile.LoadUint32(&o.TX_CH0CONF0.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetTX_CH0CONF0_CONF_UPDATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0CONF0.Reg) & 0x1000000) >> 24
}

// RMT.TX_CH1CONF0: Channel %s configure register 0
func (o *RMT_Type) SetTX_CH1CONF0_TX_START_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetTX_CH1CONF0_TX_START_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x1
}
func (o *RMT_Type) SetTX_CH1CONF0_MEM_RD_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetTX_CH1CONF0_MEM_RD_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetTX_CH1CONF0_APB_MEM_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetTX_CH1CONF0_APB_MEM_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetTX_CH1CONF0_TX_CONTI_MODE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetTX_CH1CONF0_TX_CONTI_MODE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetTX_CH1CONF0_MEM_TX_WRAP_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetTX_CH1CONF0_MEM_TX_WRAP_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetTX_CH1CONF0_IDLE_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetTX_CH1CONF0_IDLE_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetTX_CH1CONF0_IDLE_OUT_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetTX_CH1CONF0_IDLE_OUT_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetTX_CH1CONF0_TX_STOP_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetTX_CH1CONF0_TX_STOP_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetTX_CH1CONF0_DIV_CNT_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0xff00)|value<<8)
}
func (o *RMT_Type) GetTX_CH1CONF0_DIV_CNT_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0xff00) >> 8
}
func (o *RMT_Type) SetTX_CH1CONF0_MEM_SIZE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0xf0000)|value<<16)
}
func (o *RMT_Type) GetTX_CH1CONF0_MEM_SIZE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0xf0000) >> 16
}
func (o *RMT_Type) SetTX_CH1CONF0_CARRIER_EFF_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetTX_CH1CONF0_CARRIER_EFF_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetTX_CH1CONF0_CARRIER_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetTX_CH1CONF0_CARRIER_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetTX_CH1CONF0_CARRIER_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetTX_CH1CONF0_CARRIER_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetTX_CH1CONF0_AFIFO_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetTX_CH1CONF0_AFIFO_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetTX_CH1CONF0_CONF_UPDATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1CONF0.Reg, volatile.LoadUint32(&o.TX_CH1CONF0.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetTX_CH1CONF0_CONF_UPDATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1CONF0.Reg) & 0x1000000) >> 24
}

// RMT.TX_CH2CONF0: Channel %s configure register 0
func (o *RMT_Type) SetTX_CH2CONF0_TX_START_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetTX_CH2CONF0_TX_START_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x1
}
func (o *RMT_Type) SetTX_CH2CONF0_MEM_RD_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetTX_CH2CONF0_MEM_RD_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetTX_CH2CONF0_APB_MEM_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetTX_CH2CONF0_APB_MEM_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetTX_CH2CONF0_TX_CONTI_MODE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetTX_CH2CONF0_TX_CONTI_MODE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetTX_CH2CONF0_MEM_TX_WRAP_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetTX_CH2CONF0_MEM_TX_WRAP_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetTX_CH2CONF0_IDLE_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetTX_CH2CONF0_IDLE_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetTX_CH2CONF0_IDLE_OUT_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetTX_CH2CONF0_IDLE_OUT_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetTX_CH2CONF0_TX_STOP_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetTX_CH2CONF0_TX_STOP_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetTX_CH2CONF0_DIV_CNT_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0xff00)|value<<8)
}
func (o *RMT_Type) GetTX_CH2CONF0_DIV_CNT_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0xff00) >> 8
}
func (o *RMT_Type) SetTX_CH2CONF0_MEM_SIZE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0xf0000)|value<<16)
}
func (o *RMT_Type) GetTX_CH2CONF0_MEM_SIZE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0xf0000) >> 16
}
func (o *RMT_Type) SetTX_CH2CONF0_CARRIER_EFF_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetTX_CH2CONF0_CARRIER_EFF_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetTX_CH2CONF0_CARRIER_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetTX_CH2CONF0_CARRIER_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetTX_CH2CONF0_CARRIER_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetTX_CH2CONF0_CARRIER_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetTX_CH2CONF0_AFIFO_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetTX_CH2CONF0_AFIFO_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetTX_CH2CONF0_CONF_UPDATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2CONF0.Reg, volatile.LoadUint32(&o.TX_CH2CONF0.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetTX_CH2CONF0_CONF_UPDATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2CONF0.Reg) & 0x1000000) >> 24
}

// RMT.TX_CH3CONF0: Channel %s configure register 0
func (o *RMT_Type) SetTX_CH3CONF0_TX_START_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetTX_CH3CONF0_TX_START_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x1
}
func (o *RMT_Type) SetTX_CH3CONF0_MEM_RD_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetTX_CH3CONF0_MEM_RD_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetTX_CH3CONF0_APB_MEM_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetTX_CH3CONF0_APB_MEM_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetTX_CH3CONF0_TX_CONTI_MODE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetTX_CH3CONF0_TX_CONTI_MODE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetTX_CH3CONF0_MEM_TX_WRAP_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetTX_CH3CONF0_MEM_TX_WRAP_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetTX_CH3CONF0_IDLE_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetTX_CH3CONF0_IDLE_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetTX_CH3CONF0_IDLE_OUT_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetTX_CH3CONF0_IDLE_OUT_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetTX_CH3CONF0_TX_STOP_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetTX_CH3CONF0_TX_STOP_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetTX_CH3CONF0_DIV_CNT_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0xff00)|value<<8)
}
func (o *RMT_Type) GetTX_CH3CONF0_DIV_CNT_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0xff00) >> 8
}
func (o *RMT_Type) SetTX_CH3CONF0_MEM_SIZE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0xf0000)|value<<16)
}
func (o *RMT_Type) GetTX_CH3CONF0_MEM_SIZE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0xf0000) >> 16
}
func (o *RMT_Type) SetTX_CH3CONF0_CARRIER_EFF_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetTX_CH3CONF0_CARRIER_EFF_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetTX_CH3CONF0_CARRIER_EN_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetTX_CH3CONF0_CARRIER_EN_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetTX_CH3CONF0_CARRIER_OUT_LV_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetTX_CH3CONF0_CARRIER_OUT_LV_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetTX_CH3CONF0_AFIFO_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetTX_CH3CONF0_AFIFO_RST_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetTX_CH3CONF0_CONF_UPDATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3CONF0.Reg, volatile.LoadUint32(&o.TX_CH3CONF0.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetTX_CH3CONF0_CONF_UPDATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3CONF0.Reg) & 0x1000000) >> 24
}

// RMT.RX_CH0CONF0: Channel %s configure register 0
func (o *RMT_Type) SetRX_CH0CONF0_DIV_CNT_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0xff)|value)
}
func (o *RMT_Type) GetRX_CH0CONF0_DIV_CNT_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0xff
}
func (o *RMT_Type) SetRX_CH0CONF0_IDLE_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0x7fff00)|value<<8)
}
func (o *RMT_Type) GetRX_CH0CONF0_IDLE_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0x7fff00) >> 8
}
func (o *RMT_Type) SetRX_CH0CONF0_MEM_SIZE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0xf000000)|value<<24)
}
func (o *RMT_Type) GetRX_CH0CONF0_MEM_SIZE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0xf000000) >> 24
}
func (o *RMT_Type) SetRX_CH0CONF0_CARRIER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetRX_CH0CONF0_CARRIER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetRX_CH0CONF0_CARRIER_OUT_LV_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF0.Reg, volatile.LoadUint32(&o.RX_CH0CONF0.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetRX_CH0CONF0_CARRIER_OUT_LV_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF0.Reg) & 0x20000000) >> 29
}

// RMT.RX_CH0CONF1: Channel %s configure register 1
func (o *RMT_Type) SetRX_CH0CONF1_RX_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetRX_CH0CONF1_RX_EN_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x1
}
func (o *RMT_Type) SetRX_CH0CONF1_MEM_WR_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetRX_CH0CONF1_MEM_WR_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetRX_CH0CONF1_APB_MEM_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetRX_CH0CONF1_APB_MEM_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetRX_CH0CONF1_MEM_OWNER_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetRX_CH0CONF1_MEM_OWNER_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetRX_CH0CONF1_RX_FILTER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetRX_CH0CONF1_RX_FILTER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetRX_CH0CONF1_RX_FILTER_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x1fe0)|value<<5)
}
func (o *RMT_Type) GetRX_CH0CONF1_RX_FILTER_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x1fe0) >> 5
}
func (o *RMT_Type) SetRX_CH0CONF1_MEM_RX_WRAP_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetRX_CH0CONF1_MEM_RX_WRAP_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetRX_CH0CONF1_AFIFO_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetRX_CH0CONF1_AFIFO_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetRX_CH0CONF1_CONF_UPDATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0CONF1.Reg, volatile.LoadUint32(&o.RX_CH0CONF1.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetRX_CH0CONF1_CONF_UPDATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0CONF1.Reg) & 0x8000) >> 15
}

// RMT.RX_CH1CONF0: Channel %s configure register 0
func (o *RMT_Type) SetRX_CH1CONF0_DIV_CNT_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0xff)|value)
}
func (o *RMT_Type) GetRX_CH1CONF0_DIV_CNT_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0xff
}
func (o *RMT_Type) SetRX_CH1CONF0_IDLE_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0x7fff00)|value<<8)
}
func (o *RMT_Type) GetRX_CH1CONF0_IDLE_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0x7fff00) >> 8
}
func (o *RMT_Type) SetRX_CH1CONF0_MEM_SIZE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0xf000000)|value<<24)
}
func (o *RMT_Type) GetRX_CH1CONF0_MEM_SIZE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0xf000000) >> 24
}
func (o *RMT_Type) SetRX_CH1CONF0_CARRIER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetRX_CH1CONF0_CARRIER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetRX_CH1CONF0_CARRIER_OUT_LV_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF0.Reg, volatile.LoadUint32(&o.RX_CH1CONF0.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetRX_CH1CONF0_CARRIER_OUT_LV_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF0.Reg) & 0x20000000) >> 29
}

// RMT.RX_CH1CONF1: Channel %s configure register 1
func (o *RMT_Type) SetRX_CH1CONF1_RX_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetRX_CH1CONF1_RX_EN_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x1
}
func (o *RMT_Type) SetRX_CH1CONF1_MEM_WR_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetRX_CH1CONF1_MEM_WR_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetRX_CH1CONF1_APB_MEM_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetRX_CH1CONF1_APB_MEM_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetRX_CH1CONF1_MEM_OWNER_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetRX_CH1CONF1_MEM_OWNER_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetRX_CH1CONF1_RX_FILTER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetRX_CH1CONF1_RX_FILTER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetRX_CH1CONF1_RX_FILTER_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x1fe0)|value<<5)
}
func (o *RMT_Type) GetRX_CH1CONF1_RX_FILTER_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x1fe0) >> 5
}
func (o *RMT_Type) SetRX_CH1CONF1_MEM_RX_WRAP_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetRX_CH1CONF1_MEM_RX_WRAP_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetRX_CH1CONF1_AFIFO_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetRX_CH1CONF1_AFIFO_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetRX_CH1CONF1_CONF_UPDATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1CONF1.Reg, volatile.LoadUint32(&o.RX_CH1CONF1.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetRX_CH1CONF1_CONF_UPDATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1CONF1.Reg) & 0x8000) >> 15
}

// RMT.RX_CH2CONF0: Channel %s configure register 0
func (o *RMT_Type) SetRX_CH2CONF0_DIV_CNT_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0xff)|value)
}
func (o *RMT_Type) GetRX_CH2CONF0_DIV_CNT_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0xff
}
func (o *RMT_Type) SetRX_CH2CONF0_IDLE_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0x7fff00)|value<<8)
}
func (o *RMT_Type) GetRX_CH2CONF0_IDLE_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0x7fff00) >> 8
}
func (o *RMT_Type) SetRX_CH2CONF0_MEM_SIZE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0xf000000)|value<<24)
}
func (o *RMT_Type) GetRX_CH2CONF0_MEM_SIZE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0xf000000) >> 24
}
func (o *RMT_Type) SetRX_CH2CONF0_CARRIER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetRX_CH2CONF0_CARRIER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetRX_CH2CONF0_CARRIER_OUT_LV_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF0.Reg, volatile.LoadUint32(&o.RX_CH2CONF0.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetRX_CH2CONF0_CARRIER_OUT_LV_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF0.Reg) & 0x20000000) >> 29
}

// RMT.RX_CH2CONF1: Channel %s configure register 1
func (o *RMT_Type) SetRX_CH2CONF1_RX_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetRX_CH2CONF1_RX_EN_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x1
}
func (o *RMT_Type) SetRX_CH2CONF1_MEM_WR_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetRX_CH2CONF1_MEM_WR_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetRX_CH2CONF1_APB_MEM_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetRX_CH2CONF1_APB_MEM_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetRX_CH2CONF1_MEM_OWNER_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetRX_CH2CONF1_MEM_OWNER_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetRX_CH2CONF1_RX_FILTER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetRX_CH2CONF1_RX_FILTER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetRX_CH2CONF1_RX_FILTER_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x1fe0)|value<<5)
}
func (o *RMT_Type) GetRX_CH2CONF1_RX_FILTER_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x1fe0) >> 5
}
func (o *RMT_Type) SetRX_CH2CONF1_MEM_RX_WRAP_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetRX_CH2CONF1_MEM_RX_WRAP_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetRX_CH2CONF1_AFIFO_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetRX_CH2CONF1_AFIFO_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetRX_CH2CONF1_CONF_UPDATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2CONF1.Reg, volatile.LoadUint32(&o.RX_CH2CONF1.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetRX_CH2CONF1_CONF_UPDATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2CONF1.Reg) & 0x8000) >> 15
}

// RMT.RX_CH3CONF0: Channel %s configure register 0
func (o *RMT_Type) SetRX_CH3CONF0_DIV_CNT_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0xff)|value)
}
func (o *RMT_Type) GetRX_CH3CONF0_DIV_CNT_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0xff
}
func (o *RMT_Type) SetRX_CH3CONF0_IDLE_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0x7fff00)|value<<8)
}
func (o *RMT_Type) GetRX_CH3CONF0_IDLE_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0x7fff00) >> 8
}
func (o *RMT_Type) SetRX_CH3CONF0_MEM_SIZE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0xf000000)|value<<24)
}
func (o *RMT_Type) GetRX_CH3CONF0_MEM_SIZE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0xf000000) >> 24
}
func (o *RMT_Type) SetRX_CH3CONF0_CARRIER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetRX_CH3CONF0_CARRIER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetRX_CH3CONF0_CARRIER_OUT_LV_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF0.Reg, volatile.LoadUint32(&o.RX_CH3CONF0.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetRX_CH3CONF0_CARRIER_OUT_LV_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF0.Reg) & 0x20000000) >> 29
}

// RMT.RX_CH3CONF1: Channel %s configure register 1
func (o *RMT_Type) SetRX_CH3CONF1_RX_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetRX_CH3CONF1_RX_EN_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x1
}
func (o *RMT_Type) SetRX_CH3CONF1_MEM_WR_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetRX_CH3CONF1_MEM_WR_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetRX_CH3CONF1_APB_MEM_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetRX_CH3CONF1_APB_MEM_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetRX_CH3CONF1_MEM_OWNER_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetRX_CH3CONF1_MEM_OWNER_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetRX_CH3CONF1_RX_FILTER_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetRX_CH3CONF1_RX_FILTER_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetRX_CH3CONF1_RX_FILTER_THRES_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x1fe0)|value<<5)
}
func (o *RMT_Type) GetRX_CH3CONF1_RX_FILTER_THRES_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x1fe0) >> 5
}
func (o *RMT_Type) SetRX_CH3CONF1_MEM_RX_WRAP_EN_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetRX_CH3CONF1_MEM_RX_WRAP_EN_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetRX_CH3CONF1_AFIFO_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetRX_CH3CONF1_AFIFO_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetRX_CH3CONF1_CONF_UPDATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3CONF1.Reg, volatile.LoadUint32(&o.RX_CH3CONF1.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetRX_CH3CONF1_CONF_UPDATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3CONF1.Reg) & 0x8000) >> 15
}

// RMT.TX_CH0STATUS: Channel %s status register
func (o *RMT_Type) SetTX_CH0STATUS_MEM_RADDR_EX_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetTX_CH0STATUS_MEM_RADDR_EX_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetTX_CH0STATUS_APB_MEM_WADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetTX_CH0STATUS_APB_MEM_WADDR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetTX_CH0STATUS_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetTX_CH0STATUS_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetTX_CH0STATUS_MEM_EMPTY_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetTX_CH0STATUS_MEM_EMPTY_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetTX_CH0STATUS_APB_MEM_WR_ERR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH0STATUS.Reg, volatile.LoadUint32(&o.TX_CH0STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetTX_CH0STATUS_APB_MEM_WR_ERR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH0STATUS.Reg) & 0x4000000) >> 26
}

// RMT.TX_CH1STATUS: Channel %s status register
func (o *RMT_Type) SetTX_CH1STATUS_MEM_RADDR_EX_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetTX_CH1STATUS_MEM_RADDR_EX_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetTX_CH1STATUS_APB_MEM_WADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetTX_CH1STATUS_APB_MEM_WADDR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetTX_CH1STATUS_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetTX_CH1STATUS_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetTX_CH1STATUS_MEM_EMPTY_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetTX_CH1STATUS_MEM_EMPTY_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetTX_CH1STATUS_APB_MEM_WR_ERR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH1STATUS.Reg, volatile.LoadUint32(&o.TX_CH1STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetTX_CH1STATUS_APB_MEM_WR_ERR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH1STATUS.Reg) & 0x4000000) >> 26
}

// RMT.TX_CH2STATUS: Channel %s status register
func (o *RMT_Type) SetTX_CH2STATUS_MEM_RADDR_EX_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetTX_CH2STATUS_MEM_RADDR_EX_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetTX_CH2STATUS_APB_MEM_WADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetTX_CH2STATUS_APB_MEM_WADDR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetTX_CH2STATUS_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetTX_CH2STATUS_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetTX_CH2STATUS_MEM_EMPTY_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetTX_CH2STATUS_MEM_EMPTY_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetTX_CH2STATUS_APB_MEM_WR_ERR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH2STATUS.Reg, volatile.LoadUint32(&o.TX_CH2STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetTX_CH2STATUS_APB_MEM_WR_ERR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH2STATUS.Reg) & 0x4000000) >> 26
}

// RMT.TX_CH3STATUS: Channel %s status register
func (o *RMT_Type) SetTX_CH3STATUS_MEM_RADDR_EX_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetTX_CH3STATUS_MEM_RADDR_EX_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetTX_CH3STATUS_APB_MEM_WADDR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetTX_CH3STATUS_APB_MEM_WADDR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetTX_CH3STATUS_STATE_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetTX_CH3STATUS_STATE_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetTX_CH3STATUS_MEM_EMPTY_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetTX_CH3STATUS_MEM_EMPTY_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetTX_CH3STATUS_APB_MEM_WR_ERR_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_CH3STATUS.Reg, volatile.LoadUint32(&o.TX_CH3STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetTX_CH3STATUS_APB_MEM_WR_ERR_CH0() uint32 {
	return (volatile.LoadUint32(&o.TX_CH3STATUS.Reg) & 0x4000000) >> 26
}

// RMT.RX_CH0STATUS: Channel %s status register
func (o *RMT_Type) SetRX_CH0STATUS_MEM_WADDR_EX_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetRX_CH0STATUS_MEM_WADDR_EX_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetRX_CH0STATUS_APB_MEM_RADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetRX_CH0STATUS_APB_MEM_RADDR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetRX_CH0STATUS_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetRX_CH0STATUS_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetRX_CH0STATUS_MEM_OWNER_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetRX_CH0STATUS_MEM_OWNER_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetRX_CH0STATUS_MEM_FULL_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetRX_CH0STATUS_MEM_FULL_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetRX_CH0STATUS_APB_MEM_RD_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH0STATUS.Reg, volatile.LoadUint32(&o.RX_CH0STATUS.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetRX_CH0STATUS_APB_MEM_RD_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH0STATUS.Reg) & 0x8000000) >> 27
}

// RMT.RX_CH1STATUS: Channel %s status register
func (o *RMT_Type) SetRX_CH1STATUS_MEM_WADDR_EX_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetRX_CH1STATUS_MEM_WADDR_EX_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetRX_CH1STATUS_APB_MEM_RADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetRX_CH1STATUS_APB_MEM_RADDR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetRX_CH1STATUS_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetRX_CH1STATUS_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetRX_CH1STATUS_MEM_OWNER_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetRX_CH1STATUS_MEM_OWNER_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetRX_CH1STATUS_MEM_FULL_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetRX_CH1STATUS_MEM_FULL_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetRX_CH1STATUS_APB_MEM_RD_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH1STATUS.Reg, volatile.LoadUint32(&o.RX_CH1STATUS.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetRX_CH1STATUS_APB_MEM_RD_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH1STATUS.Reg) & 0x8000000) >> 27
}

// RMT.RX_CH2STATUS: Channel %s status register
func (o *RMT_Type) SetRX_CH2STATUS_MEM_WADDR_EX_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetRX_CH2STATUS_MEM_WADDR_EX_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetRX_CH2STATUS_APB_MEM_RADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetRX_CH2STATUS_APB_MEM_RADDR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetRX_CH2STATUS_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetRX_CH2STATUS_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetRX_CH2STATUS_MEM_OWNER_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetRX_CH2STATUS_MEM_OWNER_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetRX_CH2STATUS_MEM_FULL_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetRX_CH2STATUS_MEM_FULL_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetRX_CH2STATUS_APB_MEM_RD_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH2STATUS.Reg, volatile.LoadUint32(&o.RX_CH2STATUS.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetRX_CH2STATUS_APB_MEM_RD_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH2STATUS.Reg) & 0x8000000) >> 27
}

// RMT.RX_CH3STATUS: Channel %s status register
func (o *RMT_Type) SetRX_CH3STATUS_MEM_WADDR_EX_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x3ff)|value)
}
func (o *RMT_Type) GetRX_CH3STATUS_MEM_WADDR_EX_CH4() uint32 {
	return volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x3ff
}
func (o *RMT_Type) SetRX_CH3STATUS_APB_MEM_RADDR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x1ff800)|value<<11)
}
func (o *RMT_Type) GetRX_CH3STATUS_APB_MEM_RADDR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x1ff800) >> 11
}
func (o *RMT_Type) SetRX_CH3STATUS_STATE_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x1c00000)|value<<22)
}
func (o *RMT_Type) GetRX_CH3STATUS_STATE_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x1c00000) >> 22
}
func (o *RMT_Type) SetRX_CH3STATUS_MEM_OWNER_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetRX_CH3STATUS_MEM_OWNER_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetRX_CH3STATUS_MEM_FULL_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetRX_CH3STATUS_MEM_FULL_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetRX_CH3STATUS_APB_MEM_RD_ERR_CH4(value uint32) {
	volatile.StoreUint32(&o.RX_CH3STATUS.Reg, volatile.LoadUint32(&o.RX_CH3STATUS.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetRX_CH3STATUS_APB_MEM_RD_ERR_CH4() uint32 {
	return (volatile.LoadUint32(&o.RX_CH3STATUS.Reg) & 0x8000000) >> 27
}

// RMT.INT_RAW: Raw interrupt status
func (o *RMT_Type) SetINT_RAW_CH0_TX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetINT_RAW_CH0_TX_END_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *RMT_Type) SetINT_RAW_CH1_TX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetINT_RAW_CH1_TX_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetINT_RAW_CH2_TX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetINT_RAW_CH2_TX_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetINT_RAW_CH3_TX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetINT_RAW_CH3_TX_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetINT_RAW_TX_CH0_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetINT_RAW_TX_CH0_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetINT_RAW_TX_CH1_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetINT_RAW_TX_CH1_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetINT_RAW_TX_CH2_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetINT_RAW_TX_CH2_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetINT_RAW_TX_CH3_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetINT_RAW_TX_CH3_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetINT_RAW_CH0_TX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *RMT_Type) GetINT_RAW_CH0_TX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *RMT_Type) SetINT_RAW_CH1_TX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *RMT_Type) GetINT_RAW_CH1_TX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *RMT_Type) SetINT_RAW_CH2_TX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *RMT_Type) GetINT_RAW_CH2_TX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *RMT_Type) SetINT_RAW_CH3_TX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *RMT_Type) GetINT_RAW_CH3_TX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *RMT_Type) SetINT_RAW_CH0_TX_LOOP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *RMT_Type) GetINT_RAW_CH0_TX_LOOP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *RMT_Type) SetINT_RAW_CH1_TX_LOOP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetINT_RAW_CH1_TX_LOOP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetINT_RAW_CH2_TX_LOOP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetINT_RAW_CH2_TX_LOOP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetINT_RAW_CH3_TX_LOOP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetINT_RAW_CH3_TX_LOOP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *RMT_Type) SetINT_RAW_CH4_RX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *RMT_Type) GetINT_RAW_CH4_RX_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *RMT_Type) SetINT_RAW_CH5_RX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *RMT_Type) GetINT_RAW_CH5_RX_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *RMT_Type) SetINT_RAW_CH6_RX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *RMT_Type) GetINT_RAW_CH6_RX_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *RMT_Type) SetINT_RAW_CH7_RX_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetINT_RAW_CH7_RX_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetINT_RAW_RX_CH4_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetINT_RAW_RX_CH4_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetINT_RAW_RX_CH5_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetINT_RAW_RX_CH5_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetINT_RAW_RX_CH6_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetINT_RAW_RX_CH6_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetINT_RAW_RX_CH7_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetINT_RAW_RX_CH7_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetINT_RAW_CH4_RX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetINT_RAW_CH4_RX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000000) >> 24
}
func (o *RMT_Type) SetINT_RAW_CH5_RX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetINT_RAW_CH5_RX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetINT_RAW_CH6_RX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetINT_RAW_CH6_RX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetINT_RAW_CH7_RX_THR_EVENT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetINT_RAW_CH7_RX_THR_EVENT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000000) >> 27
}
func (o *RMT_Type) SetINT_RAW_TX_CH3_DMA_ACCESS_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetINT_RAW_TX_CH3_DMA_ACCESS_FAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetINT_RAW_RX_CH7_DMA_ACCESS_FAIL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetINT_RAW_RX_CH7_DMA_ACCESS_FAIL_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000000) >> 29
}

// RMT.INT_ST: Masked interrupt status
func (o *RMT_Type) SetINT_ST_CH0_TX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetINT_ST_CH0_TX_END_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *RMT_Type) SetINT_ST_CH1_TX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetINT_ST_CH1_TX_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetINT_ST_CH2_TX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetINT_ST_CH2_TX_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetINT_ST_CH3_TX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetINT_ST_CH3_TX_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetINT_ST_TX_CH0_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetINT_ST_TX_CH0_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetINT_ST_TX_CH1_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetINT_ST_TX_CH1_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetINT_ST_TX_CH2_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetINT_ST_TX_CH2_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetINT_ST_TX_CH3_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetINT_ST_TX_CH3_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetINT_ST_CH0_TX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *RMT_Type) GetINT_ST_CH0_TX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *RMT_Type) SetINT_ST_CH1_TX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *RMT_Type) GetINT_ST_CH1_TX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *RMT_Type) SetINT_ST_CH2_TX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *RMT_Type) GetINT_ST_CH2_TX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *RMT_Type) SetINT_ST_CH3_TX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *RMT_Type) GetINT_ST_CH3_TX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *RMT_Type) SetINT_ST_CH0_TX_LOOP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *RMT_Type) GetINT_ST_CH0_TX_LOOP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *RMT_Type) SetINT_ST_CH1_TX_LOOP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetINT_ST_CH1_TX_LOOP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetINT_ST_CH2_TX_LOOP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetINT_ST_CH2_TX_LOOP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetINT_ST_CH3_TX_LOOP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetINT_ST_CH3_TX_LOOP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}
func (o *RMT_Type) SetINT_ST_CH4_RX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *RMT_Type) GetINT_ST_CH4_RX_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16
}
func (o *RMT_Type) SetINT_ST_CH5_RX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *RMT_Type) GetINT_ST_CH5_RX_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17
}
func (o *RMT_Type) SetINT_ST_CH6_RX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *RMT_Type) GetINT_ST_CH6_RX_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18
}
func (o *RMT_Type) SetINT_ST_CH7_RX_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetINT_ST_CH7_RX_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetINT_ST_RX_CH4_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetINT_ST_RX_CH4_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetINT_ST_RX_CH5_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetINT_ST_RX_CH5_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetINT_ST_RX_CH6_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetINT_ST_RX_CH6_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetINT_ST_RX_CH7_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetINT_ST_RX_CH7_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetINT_ST_CH4_RX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetINT_ST_CH4_RX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000000) >> 24
}
func (o *RMT_Type) SetINT_ST_CH5_RX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetINT_ST_CH5_RX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetINT_ST_CH6_RX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetINT_ST_CH6_RX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetINT_ST_CH7_RX_THR_EVENT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetINT_ST_CH7_RX_THR_EVENT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000000) >> 27
}
func (o *RMT_Type) SetINT_ST_TX_CH3_DMA_ACCESS_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetINT_ST_TX_CH3_DMA_ACCESS_FAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetINT_ST_RX_CH7_DMA_ACCESS_FAIL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetINT_ST_RX_CH7_DMA_ACCESS_FAIL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000000) >> 29
}

// RMT.INT_ENA: Interrupt enable bits
func (o *RMT_Type) SetINT_ENA_CH0_TX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetINT_ENA_CH0_TX_END_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *RMT_Type) SetINT_ENA_CH1_TX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetINT_ENA_CH1_TX_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetINT_ENA_CH2_TX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetINT_ENA_CH2_TX_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetINT_ENA_CH3_TX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetINT_ENA_CH3_TX_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetINT_ENA_TX_CH0_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetINT_ENA_TX_CH0_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetINT_ENA_TX_CH1_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetINT_ENA_TX_CH1_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetINT_ENA_TX_CH2_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetINT_ENA_TX_CH2_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetINT_ENA_TX_CH3_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetINT_ENA_TX_CH3_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetINT_ENA_CH0_TX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *RMT_Type) GetINT_ENA_CH0_TX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *RMT_Type) SetINT_ENA_CH1_TX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *RMT_Type) GetINT_ENA_CH1_TX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *RMT_Type) SetINT_ENA_CH2_TX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *RMT_Type) GetINT_ENA_CH2_TX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *RMT_Type) SetINT_ENA_CH3_TX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *RMT_Type) GetINT_ENA_CH3_TX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *RMT_Type) SetINT_ENA_CH0_TX_LOOP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *RMT_Type) GetINT_ENA_CH0_TX_LOOP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *RMT_Type) SetINT_ENA_CH1_TX_LOOP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetINT_ENA_CH1_TX_LOOP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetINT_ENA_CH2_TX_LOOP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetINT_ENA_CH2_TX_LOOP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetINT_ENA_CH3_TX_LOOP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetINT_ENA_CH3_TX_LOOP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}
func (o *RMT_Type) SetINT_ENA_CH4_RX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *RMT_Type) GetINT_ENA_CH4_RX_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16
}
func (o *RMT_Type) SetINT_ENA_CH5_RX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *RMT_Type) GetINT_ENA_CH5_RX_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17
}
func (o *RMT_Type) SetINT_ENA_CH6_RX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *RMT_Type) GetINT_ENA_CH6_RX_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}
func (o *RMT_Type) SetINT_ENA_CH7_RX_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetINT_ENA_CH7_RX_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetINT_ENA_CH4_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetINT_ENA_CH4_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetINT_ENA_CH5_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetINT_ENA_CH5_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetINT_ENA_CH6_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetINT_ENA_CH6_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetINT_ENA_CH7_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetINT_ENA_CH7_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetINT_ENA_CH4_RX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetINT_ENA_CH4_RX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000000) >> 24
}
func (o *RMT_Type) SetINT_ENA_CH5_RX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetINT_ENA_CH5_RX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetINT_ENA_CH6_RX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetINT_ENA_CH6_RX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetINT_ENA_CH7_RX_THR_EVENT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetINT_ENA_CH7_RX_THR_EVENT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000000) >> 27
}
func (o *RMT_Type) SetINT_ENA_TX_CH3_DMA_ACCESS_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetINT_ENA_TX_CH3_DMA_ACCESS_FAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetINT_ENA_RX_CH7_DMA_ACCESS_FAIL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetINT_ENA_RX_CH7_DMA_ACCESS_FAIL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000000) >> 29
}

// RMT.INT_CLR: Interrupt clear bits
func (o *RMT_Type) SetINT_CLR_CH0_TX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetINT_CLR_CH0_TX_END_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *RMT_Type) SetINT_CLR_CH1_TX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetINT_CLR_CH1_TX_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetINT_CLR_CH2_TX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetINT_CLR_CH2_TX_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetINT_CLR_CH3_TX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetINT_CLR_CH3_TX_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetINT_CLR_TX_CH0_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetINT_CLR_TX_CH0_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetINT_CLR_TX_CH1_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetINT_CLR_TX_CH1_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetINT_CLR_TX_CH2_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetINT_CLR_TX_CH2_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetINT_CLR_TX_CH3_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetINT_CLR_TX_CH3_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *RMT_Type) SetINT_CLR_CH0_TX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *RMT_Type) GetINT_CLR_CH0_TX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *RMT_Type) SetINT_CLR_CH1_TX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *RMT_Type) GetINT_CLR_CH1_TX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *RMT_Type) SetINT_CLR_CH2_TX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *RMT_Type) GetINT_CLR_CH2_TX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *RMT_Type) SetINT_CLR_CH3_TX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *RMT_Type) GetINT_CLR_CH3_TX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *RMT_Type) SetINT_CLR_CH0_TX_LOOP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *RMT_Type) GetINT_CLR_CH0_TX_LOOP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *RMT_Type) SetINT_CLR_CH1_TX_LOOP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *RMT_Type) GetINT_CLR_CH1_TX_LOOP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *RMT_Type) SetINT_CLR_CH2_TX_LOOP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *RMT_Type) GetINT_CLR_CH2_TX_LOOP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *RMT_Type) SetINT_CLR_CH3_TX_LOOP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *RMT_Type) GetINT_CLR_CH3_TX_LOOP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}
func (o *RMT_Type) SetINT_CLR_CH4_RX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *RMT_Type) GetINT_CLR_CH4_RX_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16
}
func (o *RMT_Type) SetINT_CLR_CH5_RX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *RMT_Type) GetINT_CLR_CH5_RX_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17
}
func (o *RMT_Type) SetINT_CLR_CH6_RX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *RMT_Type) GetINT_CLR_CH6_RX_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}
func (o *RMT_Type) SetINT_CLR_CH7_RX_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetINT_CLR_CH7_RX_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetINT_CLR_RX_CH4_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetINT_CLR_RX_CH4_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetINT_CLR_RX_CH5_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetINT_CLR_RX_CH5_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200000) >> 21
}
func (o *RMT_Type) SetINT_CLR_RX_CH6_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *RMT_Type) GetINT_CLR_RX_CH6_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400000) >> 22
}
func (o *RMT_Type) SetINT_CLR_RX_CH7_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *RMT_Type) GetINT_CLR_RX_CH7_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800000) >> 23
}
func (o *RMT_Type) SetINT_CLR_CH4_RX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *RMT_Type) GetINT_CLR_CH4_RX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000000) >> 24
}
func (o *RMT_Type) SetINT_CLR_CH5_RX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *RMT_Type) GetINT_CLR_CH5_RX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000000) >> 25
}
func (o *RMT_Type) SetINT_CLR_CH6_RX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetINT_CLR_CH6_RX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetINT_CLR_CH7_RX_THR_EVENT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *RMT_Type) GetINT_CLR_CH7_RX_THR_EVENT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000000) >> 27
}
func (o *RMT_Type) SetINT_CLR_TX_CH3_DMA_ACCESS_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *RMT_Type) GetINT_CLR_TX_CH3_DMA_ACCESS_FAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000000) >> 28
}
func (o *RMT_Type) SetINT_CLR_RX_CH7_DMA_ACCESS_FAIL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *RMT_Type) GetINT_CLR_RX_CH7_DMA_ACCESS_FAIL_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000000) >> 29
}

// RMT.CH0CARRIER_DUTY: Channel %s duty cycle configuration register
func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_LOW_CH(value uint32) {
	volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_LOW_CH() uint32 {
	return volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff
}
func (o *RMT_Type) SetCH0CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) {
	volatile.StoreUint32(&o.CH0CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH0CARRIER_DUTY_CARRIER_HIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0CARRIER_DUTY.Reg) & 0xffff0000) >> 16
}

// RMT.CH1CARRIER_DUTY: Channel %s duty cycle configuration register
func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_LOW_CH(value uint32) {
	volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_LOW_CH() uint32 {
	return volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff
}
func (o *RMT_Type) SetCH1CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) {
	volatile.StoreUint32(&o.CH1CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH1CARRIER_DUTY_CARRIER_HIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1CARRIER_DUTY.Reg) & 0xffff0000) >> 16
}

// RMT.CH2CARRIER_DUTY: Channel %s duty cycle configuration register
func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_LOW_CH(value uint32) {
	volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_LOW_CH() uint32 {
	return volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff
}
func (o *RMT_Type) SetCH2CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) {
	volatile.StoreUint32(&o.CH2CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH2CARRIER_DUTY_CARRIER_HIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2CARRIER_DUTY.Reg) & 0xffff0000) >> 16
}

// RMT.CH3CARRIER_DUTY: Channel %s duty cycle configuration register
func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_LOW_CH(value uint32) {
	volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_LOW_CH() uint32 {
	return volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff
}
func (o *RMT_Type) SetCH3CARRIER_DUTY_CARRIER_HIGH_CH(value uint32) {
	volatile.StoreUint32(&o.CH3CARRIER_DUTY.Reg, volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH3CARRIER_DUTY_CARRIER_HIGH_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3CARRIER_DUTY.Reg) & 0xffff0000) >> 16
}

// RMT.CH0_RX_CARRIER_RM: Channel %s carrier remove register
func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 {
	return volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff
}
func (o *RMT_Type) SetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH0_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16
}

// RMT.CH1_RX_CARRIER_RM: Channel %s carrier remove register
func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 {
	return volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff
}
func (o *RMT_Type) SetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH1_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16
}

// RMT.CH2_RX_CARRIER_RM: Channel %s carrier remove register
func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 {
	return volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff
}
func (o *RMT_Type) SetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH2_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16
}

// RMT.CH3_RX_CARRIER_RM: Channel %s carrier remove register
func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff)|value)
}
func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_LOW_THRES_CH() uint32 {
	return volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff
}
func (o *RMT_Type) SetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_RX_CARRIER_RM.Reg, volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg)&^(0xffff0000)|value<<16)
}
func (o *RMT_Type) GetCH3_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_RX_CARRIER_RM.Reg) & 0xffff0000) >> 16
}

// RMT.CH0_TX_LIM: Channel %s Tx event configuration register
func (o *RMT_Type) SetCH0_TX_LIM_TX_LIM_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH0_TX_LIM_TX_LIM_CH() uint32 {
	return volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x1ff
}
func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x7fe00)|value<<9)
}
func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x7fe00) >> 9
}
func (o *RMT_Type) SetCH0_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetCH0_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetCH0_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetCH0_TX_LIM_LOOP_COUNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetCH0_TX_LIM_LOOP_STOP_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH0_TX_LIM.Reg, volatile.LoadUint32(&o.CH0_TX_LIM.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetCH0_TX_LIM_LOOP_STOP_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH0_TX_LIM.Reg) & 0x200000) >> 21
}

// RMT.CH1_TX_LIM: Channel %s Tx event configuration register
func (o *RMT_Type) SetCH1_TX_LIM_TX_LIM_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH1_TX_LIM_TX_LIM_CH() uint32 {
	return volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x1ff
}
func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x7fe00)|value<<9)
}
func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x7fe00) >> 9
}
func (o *RMT_Type) SetCH1_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetCH1_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetCH1_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetCH1_TX_LIM_LOOP_COUNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetCH1_TX_LIM_LOOP_STOP_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH1_TX_LIM.Reg, volatile.LoadUint32(&o.CH1_TX_LIM.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetCH1_TX_LIM_LOOP_STOP_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH1_TX_LIM.Reg) & 0x200000) >> 21
}

// RMT.CH2_TX_LIM: Channel %s Tx event configuration register
func (o *RMT_Type) SetCH2_TX_LIM_TX_LIM_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH2_TX_LIM_TX_LIM_CH() uint32 {
	return volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x1ff
}
func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x7fe00)|value<<9)
}
func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x7fe00) >> 9
}
func (o *RMT_Type) SetCH2_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetCH2_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetCH2_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetCH2_TX_LIM_LOOP_COUNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetCH2_TX_LIM_LOOP_STOP_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH2_TX_LIM.Reg, volatile.LoadUint32(&o.CH2_TX_LIM.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetCH2_TX_LIM_LOOP_STOP_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH2_TX_LIM.Reg) & 0x200000) >> 21
}

// RMT.CH3_TX_LIM: Channel %s Tx event configuration register
func (o *RMT_Type) SetCH3_TX_LIM_TX_LIM_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH3_TX_LIM_TX_LIM_CH() uint32 {
	return volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x1ff
}
func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_NUM_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x7fe00)|value<<9)
}
func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_NUM_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x7fe00) >> 9
}
func (o *RMT_Type) SetCH3_TX_LIM_TX_LOOP_CNT_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x80000)|value<<19)
}
func (o *RMT_Type) GetCH3_TX_LIM_TX_LOOP_CNT_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x80000) >> 19
}
func (o *RMT_Type) SetCH3_TX_LIM_LOOP_COUNT_RESET_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x100000)|value<<20)
}
func (o *RMT_Type) GetCH3_TX_LIM_LOOP_COUNT_RESET_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x100000) >> 20
}
func (o *RMT_Type) SetCH3_TX_LIM_LOOP_STOP_EN_CH(value uint32) {
	volatile.StoreUint32(&o.CH3_TX_LIM.Reg, volatile.LoadUint32(&o.CH3_TX_LIM.Reg)&^(0x200000)|value<<21)
}
func (o *RMT_Type) GetCH3_TX_LIM_LOOP_STOP_EN_CH() uint32 {
	return (volatile.LoadUint32(&o.CH3_TX_LIM.Reg) & 0x200000) >> 21
}

// RMT.CH0_RX_LIM: Channel %s Rx event configuration register
func (o *RMT_Type) SetCH0_RX_LIM_RX_LIM_CH4(value uint32) {
	volatile.StoreUint32(&o.CH0_RX_LIM.Reg, volatile.LoadUint32(&o.CH0_RX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH0_RX_LIM_RX_LIM_CH4() uint32 {
	return volatile.LoadUint32(&o.CH0_RX_LIM.Reg) & 0x1ff
}

// RMT.CH1_RX_LIM: Channel %s Rx event configuration register
func (o *RMT_Type) SetCH1_RX_LIM_RX_LIM_CH4(value uint32) {
	volatile.StoreUint32(&o.CH1_RX_LIM.Reg, volatile.LoadUint32(&o.CH1_RX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH1_RX_LIM_RX_LIM_CH4() uint32 {
	return volatile.LoadUint32(&o.CH1_RX_LIM.Reg) & 0x1ff
}

// RMT.CH2_RX_LIM: Channel %s Rx event configuration register
func (o *RMT_Type) SetCH2_RX_LIM_RX_LIM_CH4(value uint32) {
	volatile.StoreUint32(&o.CH2_RX_LIM.Reg, volatile.LoadUint32(&o.CH2_RX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH2_RX_LIM_RX_LIM_CH4() uint32 {
	return volatile.LoadUint32(&o.CH2_RX_LIM.Reg) & 0x1ff
}

// RMT.CH3_RX_LIM: Channel %s Rx event configuration register
func (o *RMT_Type) SetCH3_RX_LIM_RX_LIM_CH4(value uint32) {
	volatile.StoreUint32(&o.CH3_RX_LIM.Reg, volatile.LoadUint32(&o.CH3_RX_LIM.Reg)&^(0x1ff)|value)
}
func (o *RMT_Type) GetCH3_RX_LIM_RX_LIM_CH4() uint32 {
	return volatile.LoadUint32(&o.CH3_RX_LIM.Reg) & 0x1ff
}

// RMT.SYS_CONF: RMT apb configuration register
func (o *RMT_Type) SetSYS_CONF_APB_FIFO_MASK(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetSYS_CONF_APB_FIFO_MASK() uint32 {
	return volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x1
}
func (o *RMT_Type) SetSYS_CONF_MEM_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetSYS_CONF_MEM_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetSYS_CONF_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetSYS_CONF_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xff0)|value<<4)
}
func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_NUM() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xff0) >> 4
}
func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_A(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3f000)|value<<12)
}
func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_A() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3f000) >> 12
}
func (o *RMT_Type) SetSYS_CONF_SCLK_DIV_B(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0xfc0000)|value<<18)
}
func (o *RMT_Type) GetSYS_CONF_SCLK_DIV_B() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0xfc0000) >> 18
}
func (o *RMT_Type) SetSYS_CONF_SCLK_SEL(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x3000000)|value<<24)
}
func (o *RMT_Type) GetSYS_CONF_SCLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x3000000) >> 24
}
func (o *RMT_Type) SetSYS_CONF_SCLK_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *RMT_Type) GetSYS_CONF_SCLK_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x4000000) >> 26
}
func (o *RMT_Type) SetSYS_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SYS_CONF.Reg, volatile.LoadUint32(&o.SYS_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *RMT_Type) GetSYS_CONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.SYS_CONF.Reg) & 0x80000000) >> 31
}

// RMT.TX_SIM: RMT TX synchronous register
func (o *RMT_Type) SetTX_SIM_CH0(value uint32) {
	volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetTX_SIM_CH0() uint32 {
	return volatile.LoadUint32(&o.TX_SIM.Reg) & 0x1
}
func (o *RMT_Type) SetTX_SIM_CH1(value uint32) {
	volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetTX_SIM_CH1() uint32 {
	return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetTX_SIM_CH2(value uint32) {
	volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetTX_SIM_CH2() uint32 {
	return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetTX_SIM_CH3(value uint32) {
	volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetTX_SIM_CH3() uint32 {
	return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetTX_SIM_EN(value uint32) {
	volatile.StoreUint32(&o.TX_SIM.Reg, volatile.LoadUint32(&o.TX_SIM.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetTX_SIM_EN() uint32 {
	return (volatile.LoadUint32(&o.TX_SIM.Reg) & 0x10) >> 4
}

// RMT.REF_CNT_RST: RMT clock divider reset register
func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH0(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x1)|value)
}
func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH0() uint32 {
	return volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x1
}
func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH1(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x2)|value<<1)
}
func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH1() uint32 {
	return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x2) >> 1
}
func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH2(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x4)|value<<2)
}
func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH2() uint32 {
	return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x4) >> 2
}
func (o *RMT_Type) SetREF_CNT_RST_TX_REF_CNT_RST_CH3(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x8)|value<<3)
}
func (o *RMT_Type) GetREF_CNT_RST_TX_REF_CNT_RST_CH3() uint32 {
	return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x8) >> 3
}
func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH4(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x10)|value<<4)
}
func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH4() uint32 {
	return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x10) >> 4
}
func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH5(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x20)|value<<5)
}
func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH5() uint32 {
	return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x20) >> 5
}
func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH6(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x40)|value<<6)
}
func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH6() uint32 {
	return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x40) >> 6
}
func (o *RMT_Type) SetREF_CNT_RST_RX_REF_CNT_RST_CH7(value uint32) {
	volatile.StoreUint32(&o.REF_CNT_RST.Reg, volatile.LoadUint32(&o.REF_CNT_RST.Reg)&^(0x80)|value<<7)
}
func (o *RMT_Type) GetREF_CNT_RST_RX_REF_CNT_RST_CH7() uint32 {
	return (volatile.LoadUint32(&o.REF_CNT_RST.Reg) & 0x80) >> 7
}

// RMT.DATE: RMT version register
func (o *RMT_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *RMT_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// RSA (Rivest Shamir Adleman) Accelerator
type RSA_Type struct {
	M_MEM             [4]volatile.Register32 // 0x0
	_                 [496]byte
	Z_MEM             [4]volatile.Register32 // 0x200
	_                 [496]byte
	Y_MEM             [4]volatile.Register32 // 0x400
	_                 [496]byte
	X_MEM             [4]volatile.Register32 // 0x600
	_                 [496]byte
	M_PRIME           volatile.Register32 // 0x800
	MODE              volatile.Register32 // 0x804
	QUERY_CLEAN       volatile.Register32 // 0x808
	SET_START_MODEXP  volatile.Register32 // 0x80C
	SET_START_MODMULT volatile.Register32 // 0x810
	SET_START_MULT    volatile.Register32 // 0x814
	QUERY_IDLE        volatile.Register32 // 0x818
	INT_CLR           volatile.Register32 // 0x81C
	CONSTANT_TIME     volatile.Register32 // 0x820
	SEARCH_ENABLE     volatile.Register32 // 0x824
	SEARCH_POS        volatile.Register32 // 0x828
	INT_ENA           volatile.Register32 // 0x82C
	DATE              volatile.Register32 // 0x830
}

// RSA.M_PRIME: Represents M’
func (o *RSA_Type) SetM_PRIME(value uint32) {
	volatile.StoreUint32(&o.M_PRIME.Reg, value)
}
func (o *RSA_Type) GetM_PRIME() uint32 {
	return volatile.LoadUint32(&o.M_PRIME.Reg)
}

// RSA.MODE: Configures RSA length
func (o *RSA_Type) SetMODE(value uint32) {
	volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7f)|value)
}
func (o *RSA_Type) GetMODE() uint32 {
	return volatile.LoadUint32(&o.MODE.Reg) & 0x7f
}

// RSA.QUERY_CLEAN: RSA clean register
func (o *RSA_Type) SetQUERY_CLEAN(value uint32) {
	volatile.StoreUint32(&o.QUERY_CLEAN.Reg, volatile.LoadUint32(&o.QUERY_CLEAN.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetQUERY_CLEAN() uint32 {
	return volatile.LoadUint32(&o.QUERY_CLEAN.Reg) & 0x1
}

// RSA.SET_START_MODEXP: Starts modular exponentiation
func (o *RSA_Type) SetSET_START_MODEXP(value uint32) {
	volatile.StoreUint32(&o.SET_START_MODEXP.Reg, volatile.LoadUint32(&o.SET_START_MODEXP.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetSET_START_MODEXP() uint32 {
	return volatile.LoadUint32(&o.SET_START_MODEXP.Reg) & 0x1
}

// RSA.SET_START_MODMULT: Starts modular multiplication
func (o *RSA_Type) SetSET_START_MODMULT(value uint32) {
	volatile.StoreUint32(&o.SET_START_MODMULT.Reg, volatile.LoadUint32(&o.SET_START_MODMULT.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetSET_START_MODMULT() uint32 {
	return volatile.LoadUint32(&o.SET_START_MODMULT.Reg) & 0x1
}

// RSA.SET_START_MULT: Starts multiplication
func (o *RSA_Type) SetSET_START_MULT(value uint32) {
	volatile.StoreUint32(&o.SET_START_MULT.Reg, volatile.LoadUint32(&o.SET_START_MULT.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetSET_START_MULT() uint32 {
	return volatile.LoadUint32(&o.SET_START_MULT.Reg) & 0x1
}

// RSA.QUERY_IDLE: Represents the RSA status
func (o *RSA_Type) SetQUERY_IDLE(value uint32) {
	volatile.StoreUint32(&o.QUERY_IDLE.Reg, volatile.LoadUint32(&o.QUERY_IDLE.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetQUERY_IDLE() uint32 {
	return volatile.LoadUint32(&o.QUERY_IDLE.Reg) & 0x1
}

// RSA.INT_CLR: Clears RSA interrupt
func (o *RSA_Type) SetINT_CLR_CLEAR_INTERRUPT(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetINT_CLR_CLEAR_INTERRUPT() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}

// RSA.CONSTANT_TIME: Configures the constant_time option
func (o *RSA_Type) SetCONSTANT_TIME(value uint32) {
	volatile.StoreUint32(&o.CONSTANT_TIME.Reg, volatile.LoadUint32(&o.CONSTANT_TIME.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetCONSTANT_TIME() uint32 {
	return volatile.LoadUint32(&o.CONSTANT_TIME.Reg) & 0x1
}

// RSA.SEARCH_ENABLE: Configures the search option
func (o *RSA_Type) SetSEARCH_ENABLE(value uint32) {
	volatile.StoreUint32(&o.SEARCH_ENABLE.Reg, volatile.LoadUint32(&o.SEARCH_ENABLE.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetSEARCH_ENABLE() uint32 {
	return volatile.LoadUint32(&o.SEARCH_ENABLE.Reg) & 0x1
}

// RSA.SEARCH_POS: Configures the search position
func (o *RSA_Type) SetSEARCH_POS(value uint32) {
	volatile.StoreUint32(&o.SEARCH_POS.Reg, volatile.LoadUint32(&o.SEARCH_POS.Reg)&^(0xfff)|value)
}
func (o *RSA_Type) GetSEARCH_POS() uint32 {
	return volatile.LoadUint32(&o.SEARCH_POS.Reg) & 0xfff
}

// RSA.INT_ENA: Enables the RSA interrupt
func (o *RSA_Type) SetINT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *RSA_Type) GetINT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}

// RSA.DATE: Version control register
func (o *RSA_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value)
}
func (o *RSA_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff
}

// Low-power Analog to Digital Converter
type RTCADC_Type struct {
	READER1_CTRL   volatile.Register32 // 0x0
	READER1_STATUS volatile.Register32 // 0x4
	MEAS1_CTRL1    volatile.Register32 // 0x8
	MEAS1_CTRL2    volatile.Register32 // 0xC
	MEAS1_MUX      volatile.Register32 // 0x10
	ATTEN1         volatile.Register32 // 0x14
	AMP_CTRL1      volatile.Register32 // 0x18
	AMP_CTRL2      volatile.Register32 // 0x1C
	AMP_CTRL3      volatile.Register32 // 0x20
	READER2_CTRL   volatile.Register32 // 0x24
	READER2_STATUS volatile.Register32 // 0x28
	MEAS2_CTRL1    volatile.Register32 // 0x2C
	MEAS2_CTRL2    volatile.Register32 // 0x30
	MEAS2_MUX      volatile.Register32 // 0x34
	ATTEN2         volatile.Register32 // 0x38
	FORCE_WPD_SAR  volatile.Register32 // 0x3C
	MEAS_STATUS    volatile.Register32 // 0x40
	REG_CLKEN      volatile.Register32 // 0x44
	COCPU_INT_RAW  volatile.Register32 // 0x48
	INT_ENA        volatile.Register32 // 0x4C
	INT_ST         volatile.Register32 // 0x50
	INT_CLR        volatile.Register32 // 0x54
	INT_ENA_W1TS   volatile.Register32 // 0x58
	INT_ENA_W1TC   volatile.Register32 // 0x5C
	WAKEUP1        volatile.Register32 // 0x60
	WAKEUP2        volatile.Register32 // 0x64
	WAKEUP_SEL     volatile.Register32 // 0x68
	SAR1_HW_WAKEUP volatile.Register32 // 0x6C
	SAR2_HW_WAKEUP volatile.Register32 // 0x70
	RND_ECO_LOW    volatile.Register32 // 0x74
	RND_ECO_HIGH   volatile.Register32 // 0x78
	RND_ECO_CS     volatile.Register32 // 0x7C
}

// RTCADC.READER1_CTRL: Control the read operation of ADC1.
func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_CLK_DIV(value uint32) {
	volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0xff)|value)
}
func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_CLK_DIV() uint32 {
	return volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0xff
}
func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_CLK_GATED(value uint32) {
	volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_CLK_GATED() uint32 {
	return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x40000) >> 18
}
func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_SAMPLE_NUM(value uint32) {
	volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x7f80000)|value<<19)
}
func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_SAMPLE_NUM() uint32 {
	return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x7f80000) >> 19
}
func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_DATA_INV(value uint32) {
	volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_DATA_INV() uint32 {
	return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x10000000) >> 28
}
func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_INT_EN(value uint32) {
	volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_INT_EN() uint32 {
	return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0x20000000) >> 29
}
func (o *RTCADC_Type) SetREADER1_CTRL_SAR1_EN_PAD_FORCE_ENABLE(value uint32) {
	volatile.StoreUint32(&o.READER1_CTRL.Reg, volatile.LoadUint32(&o.READER1_CTRL.Reg)&^(0xc0000000)|value<<30)
}
func (o *RTCADC_Type) GetREADER1_CTRL_SAR1_EN_PAD_FORCE_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.READER1_CTRL.Reg) & 0xc0000000) >> 30
}

// RTCADC.READER1_STATUS: N/A
func (o *RTCADC_Type) SetREADER1_STATUS(value uint32) {
	volatile.StoreUint32(&o.READER1_STATUS.Reg, value)
}
func (o *RTCADC_Type) GetREADER1_STATUS() uint32 {
	return volatile.LoadUint32(&o.READER1_STATUS.Reg)
}

// RTCADC.MEAS1_CTRL1: N/A
func (o *RTCADC_Type) SetMEAS1_CTRL1_FORCE_XPD_AMP(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0x3000000)|value<<24)
}
func (o *RTCADC_Type) GetMEAS1_CTRL1_FORCE_XPD_AMP() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0x3000000) >> 24
}
func (o *RTCADC_Type) SetMEAS1_CTRL1_AMP_RST_FB_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0xc000000)|value<<26)
}
func (o *RTCADC_Type) GetMEAS1_CTRL1_AMP_RST_FB_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0xc000000) >> 26
}
func (o *RTCADC_Type) SetMEAS1_CTRL1_AMP_SHORT_REF_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0x30000000)|value<<28)
}
func (o *RTCADC_Type) GetMEAS1_CTRL1_AMP_SHORT_REF_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0x30000000) >> 28
}
func (o *RTCADC_Type) SetMEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL1.Reg, volatile.LoadUint32(&o.MEAS1_CTRL1.Reg)&^(0xc0000000)|value<<30)
}
func (o *RTCADC_Type) GetMEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL1.Reg) & 0xc0000000) >> 30
}

// RTCADC.MEAS1_CTRL2: ADC1 configuration registers.
func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_DATA_SAR(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0xffff)|value)
}
func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_DATA_SAR() uint32 {
	return volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0xffff
}
func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_DONE_SAR(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x10000)|value<<16)
}
func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_DONE_SAR() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x10000) >> 16
}
func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_START_SAR(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x20000)|value<<17)
}
func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_START_SAR() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x20000) >> 17
}
func (o *RTCADC_Type) SetMEAS1_CTRL2_MEAS1_START_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x40000)|value<<18)
}
func (o *RTCADC_Type) GetMEAS1_CTRL2_MEAS1_START_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x40000) >> 18
}
func (o *RTCADC_Type) SetMEAS1_CTRL2_SAR1_EN_PAD(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x7ff80000)|value<<19)
}
func (o *RTCADC_Type) GetMEAS1_CTRL2_SAR1_EN_PAD() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x7ff80000) >> 19
}
func (o *RTCADC_Type) SetMEAS1_CTRL2_SAR1_EN_PAD_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS1_CTRL2.Reg, volatile.LoadUint32(&o.MEAS1_CTRL2.Reg)&^(0x80000000)|value<<31)
}
func (o *RTCADC_Type) GetMEAS1_CTRL2_SAR1_EN_PAD_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_CTRL2.Reg) & 0x80000000) >> 31
}

// RTCADC.MEAS1_MUX: SAR ADC1 MUX register.
func (o *RTCADC_Type) SetMEAS1_MUX_SAR1_DIG_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS1_MUX.Reg, volatile.LoadUint32(&o.MEAS1_MUX.Reg)&^(0x80000000)|value<<31)
}
func (o *RTCADC_Type) GetMEAS1_MUX_SAR1_DIG_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS1_MUX.Reg) & 0x80000000) >> 31
}

// RTCADC.ATTEN1: ADC1 attenuation registers.
func (o *RTCADC_Type) SetATTEN1(value uint32) {
	volatile.StoreUint32(&o.ATTEN1.Reg, value)
}
func (o *RTCADC_Type) GetATTEN1() uint32 {
	return volatile.LoadUint32(&o.ATTEN1.Reg)
}

// RTCADC.AMP_CTRL1: N/A
func (o *RTCADC_Type) SetAMP_CTRL1_SAR_AMP_WAIT1(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL1.Reg, volatile.LoadUint32(&o.AMP_CTRL1.Reg)&^(0xffff)|value)
}
func (o *RTCADC_Type) GetAMP_CTRL1_SAR_AMP_WAIT1() uint32 {
	return volatile.LoadUint32(&o.AMP_CTRL1.Reg) & 0xffff
}
func (o *RTCADC_Type) SetAMP_CTRL1_SAR_AMP_WAIT2(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL1.Reg, volatile.LoadUint32(&o.AMP_CTRL1.Reg)&^(0xffff0000)|value<<16)
}
func (o *RTCADC_Type) GetAMP_CTRL1_SAR_AMP_WAIT2() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL1.Reg) & 0xffff0000) >> 16
}

// RTCADC.AMP_CTRL2: N/A
func (o *RTCADC_Type) SetAMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetAMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE() uint32 {
	return volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x1
}
func (o *RTCADC_Type) SetAMP_CTRL2_XPD_SAR_AMP_FSM_IDLE(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetAMP_CTRL2_XPD_SAR_AMP_FSM_IDLE() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x2) >> 1
}
func (o *RTCADC_Type) SetAMP_CTRL2_AMP_RST_FB_FSM_IDLE(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x4)|value<<2)
}
func (o *RTCADC_Type) GetAMP_CTRL2_AMP_RST_FB_FSM_IDLE() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x4) >> 2
}
func (o *RTCADC_Type) SetAMP_CTRL2_AMP_SHORT_REF_FSM_IDLE(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetAMP_CTRL2_AMP_SHORT_REF_FSM_IDLE() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetAMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetAMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetAMP_CTRL2_XPD_SAR_FSM_IDLE(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetAMP_CTRL2_XPD_SAR_FSM_IDLE() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x20) >> 5
}
func (o *RTCADC_Type) SetAMP_CTRL2_SAR_RSTB_FSM_IDLE(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0x40)|value<<6)
}
func (o *RTCADC_Type) GetAMP_CTRL2_SAR_RSTB_FSM_IDLE() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0x40) >> 6
}
func (o *RTCADC_Type) SetAMP_CTRL2_SAR_AMP_WAIT3(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL2.Reg, volatile.LoadUint32(&o.AMP_CTRL2.Reg)&^(0xffff0000)|value<<16)
}
func (o *RTCADC_Type) GetAMP_CTRL2_SAR_AMP_WAIT3() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL2.Reg) & 0xffff0000) >> 16
}

// RTCADC.AMP_CTRL3: N/A
func (o *RTCADC_Type) SetAMP_CTRL3_SAR1_DAC_XPD_FSM(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf)|value)
}
func (o *RTCADC_Type) GetAMP_CTRL3_SAR1_DAC_XPD_FSM() uint32 {
	return volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf
}
func (o *RTCADC_Type) SetAMP_CTRL3_XPD_SAR_AMP_FSM(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf0)|value<<4)
}
func (o *RTCADC_Type) GetAMP_CTRL3_XPD_SAR_AMP_FSM() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf0) >> 4
}
func (o *RTCADC_Type) SetAMP_CTRL3_AMP_RST_FB_FSM(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf00)|value<<8)
}
func (o *RTCADC_Type) GetAMP_CTRL3_AMP_RST_FB_FSM() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf00) >> 8
}
func (o *RTCADC_Type) SetAMP_CTRL3_AMP_SHORT_REF_FSM(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf000)|value<<12)
}
func (o *RTCADC_Type) GetAMP_CTRL3_AMP_SHORT_REF_FSM() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf000) >> 12
}
func (o *RTCADC_Type) SetAMP_CTRL3_AMP_SHORT_REF_GND_FSM(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf0000)|value<<16)
}
func (o *RTCADC_Type) GetAMP_CTRL3_AMP_SHORT_REF_GND_FSM() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf0000) >> 16
}
func (o *RTCADC_Type) SetAMP_CTRL3_XPD_SAR_FSM(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf00000)|value<<20)
}
func (o *RTCADC_Type) GetAMP_CTRL3_XPD_SAR_FSM() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf00000) >> 20
}
func (o *RTCADC_Type) SetAMP_CTRL3_SAR_RSTB_FSM(value uint32) {
	volatile.StoreUint32(&o.AMP_CTRL3.Reg, volatile.LoadUint32(&o.AMP_CTRL3.Reg)&^(0xf000000)|value<<24)
}
func (o *RTCADC_Type) GetAMP_CTRL3_SAR_RSTB_FSM() uint32 {
	return (volatile.LoadUint32(&o.AMP_CTRL3.Reg) & 0xf000000) >> 24
}

// RTCADC.READER2_CTRL: Control the read operation of ADC2.
func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_CLK_DIV(value uint32) {
	volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0xff)|value)
}
func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_CLK_DIV() uint32 {
	return volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0xff
}
func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_WAIT_ARB_CYCLE(value uint32) {
	volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x30000)|value<<16)
}
func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_WAIT_ARB_CYCLE() uint32 {
	return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x30000) >> 16
}
func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_CLK_GATED(value uint32) {
	volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_CLK_GATED() uint32 {
	return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x40000) >> 18
}
func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_SAMPLE_NUM(value uint32) {
	volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x7f80000)|value<<19)
}
func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_SAMPLE_NUM() uint32 {
	return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x7f80000) >> 19
}
func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_EN_PAD_FORCE_ENABLE(value uint32) {
	volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x18000000)|value<<27)
}
func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_EN_PAD_FORCE_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x18000000) >> 27
}
func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_DATA_INV(value uint32) {
	volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_DATA_INV() uint32 {
	return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x20000000) >> 29
}
func (o *RTCADC_Type) SetREADER2_CTRL_SAR2_INT_EN(value uint32) {
	volatile.StoreUint32(&o.READER2_CTRL.Reg, volatile.LoadUint32(&o.READER2_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *RTCADC_Type) GetREADER2_CTRL_SAR2_INT_EN() uint32 {
	return (volatile.LoadUint32(&o.READER2_CTRL.Reg) & 0x40000000) >> 30
}

// RTCADC.READER2_STATUS: N/A
func (o *RTCADC_Type) SetREADER2_STATUS(value uint32) {
	volatile.StoreUint32(&o.READER2_STATUS.Reg, value)
}
func (o *RTCADC_Type) GetREADER2_STATUS() uint32 {
	return volatile.LoadUint32(&o.READER2_STATUS.Reg)
}

// RTCADC.MEAS2_CTRL1: ADC2 configuration registers.
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_CNTL_STATE(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x7)|value)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_CNTL_STATE() uint32 {
	return volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x7
}
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_PWDET_CAL_EN(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_PWDET_CAL_EN() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_PKDET_CAL_EN(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_PKDET_CAL_EN() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_EN_TEST(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_EN_TEST() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0x20) >> 5
}
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_RSTB_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xc0)|value<<6)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_RSTB_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xc0) >> 6
}
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_STANDBY_WAIT(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xff00)|value<<8)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_STANDBY_WAIT() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xff00) >> 8
}
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_RSTB_WAIT(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xff0000)|value<<16)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_RSTB_WAIT() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xff0000) >> 16
}
func (o *RTCADC_Type) SetMEAS2_CTRL1_SAR2_XPD_WAIT(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL1.Reg, volatile.LoadUint32(&o.MEAS2_CTRL1.Reg)&^(0xff000000)|value<<24)
}
func (o *RTCADC_Type) GetMEAS2_CTRL1_SAR2_XPD_WAIT() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL1.Reg) & 0xff000000) >> 24
}

// RTCADC.MEAS2_CTRL2: ADC2 configuration registers.
func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_DATA_SAR(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0xffff)|value)
}
func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_DATA_SAR() uint32 {
	return volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0xffff
}
func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_DONE_SAR(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x10000)|value<<16)
}
func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_DONE_SAR() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x10000) >> 16
}
func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_START_SAR(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x20000)|value<<17)
}
func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_START_SAR() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x20000) >> 17
}
func (o *RTCADC_Type) SetMEAS2_CTRL2_MEAS2_START_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x40000)|value<<18)
}
func (o *RTCADC_Type) GetMEAS2_CTRL2_MEAS2_START_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x40000) >> 18
}
func (o *RTCADC_Type) SetMEAS2_CTRL2_SAR2_EN_PAD(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x7ff80000)|value<<19)
}
func (o *RTCADC_Type) GetMEAS2_CTRL2_SAR2_EN_PAD() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x7ff80000) >> 19
}
func (o *RTCADC_Type) SetMEAS2_CTRL2_SAR2_EN_PAD_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS2_CTRL2.Reg, volatile.LoadUint32(&o.MEAS2_CTRL2.Reg)&^(0x80000000)|value<<31)
}
func (o *RTCADC_Type) GetMEAS2_CTRL2_SAR2_EN_PAD_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_CTRL2.Reg) & 0x80000000) >> 31
}

// RTCADC.MEAS2_MUX: SAR ADC2 MUX register.
func (o *RTCADC_Type) SetMEAS2_MUX_SAR2_PWDET_CCT(value uint32) {
	volatile.StoreUint32(&o.MEAS2_MUX.Reg, volatile.LoadUint32(&o.MEAS2_MUX.Reg)&^(0x70000000)|value<<28)
}
func (o *RTCADC_Type) GetMEAS2_MUX_SAR2_PWDET_CCT() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_MUX.Reg) & 0x70000000) >> 28
}
func (o *RTCADC_Type) SetMEAS2_MUX_SAR2_RTC_FORCE(value uint32) {
	volatile.StoreUint32(&o.MEAS2_MUX.Reg, volatile.LoadUint32(&o.MEAS2_MUX.Reg)&^(0x80000000)|value<<31)
}
func (o *RTCADC_Type) GetMEAS2_MUX_SAR2_RTC_FORCE() uint32 {
	return (volatile.LoadUint32(&o.MEAS2_MUX.Reg) & 0x80000000) >> 31
}

// RTCADC.ATTEN2: ADC1 attenuation registers.
func (o *RTCADC_Type) SetATTEN2(value uint32) {
	volatile.StoreUint32(&o.ATTEN2.Reg, value)
}
func (o *RTCADC_Type) GetATTEN2() uint32 {
	return volatile.LoadUint32(&o.ATTEN2.Reg)
}

// RTCADC.FORCE_WPD_SAR: In sleep, force to use rtc to control ADC
func (o *RTCADC_Type) SetFORCE_WPD_SAR_FORCE_XPD_SAR1(value uint32) {
	volatile.StoreUint32(&o.FORCE_WPD_SAR.Reg, volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg)&^(0x3)|value)
}
func (o *RTCADC_Type) GetFORCE_WPD_SAR_FORCE_XPD_SAR1() uint32 {
	return volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg) & 0x3
}
func (o *RTCADC_Type) SetFORCE_WPD_SAR_FORCE_XPD_SAR2(value uint32) {
	volatile.StoreUint32(&o.FORCE_WPD_SAR.Reg, volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg)&^(0xc)|value<<2)
}
func (o *RTCADC_Type) GetFORCE_WPD_SAR_FORCE_XPD_SAR2() uint32 {
	return (volatile.LoadUint32(&o.FORCE_WPD_SAR.Reg) & 0xc) >> 2
}

// RTCADC.MEAS_STATUS: N/A
func (o *RTCADC_Type) SetMEAS_STATUS_SARADC_MEAS_STATUS(value uint32) {
	volatile.StoreUint32(&o.MEAS_STATUS.Reg, volatile.LoadUint32(&o.MEAS_STATUS.Reg)&^(0xff)|value)
}
func (o *RTCADC_Type) GetMEAS_STATUS_SARADC_MEAS_STATUS() uint32 {
	return volatile.LoadUint32(&o.MEAS_STATUS.Reg) & 0xff
}

// RTCADC.REG_CLKEN: N/A
func (o *RTCADC_Type) SetREG_CLKEN_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REG_CLKEN.Reg, volatile.LoadUint32(&o.REG_CLKEN.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetREG_CLKEN_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.REG_CLKEN.Reg) & 0x1
}

// RTCADC.COCPU_INT_RAW: Interrupt raw registers.
func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC1_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x1
}
func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x2) >> 1
}
func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC1_ERROR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC1_ERROR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x4) >> 2
}
func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC2_ERROR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC2_ERROR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC1_WAKE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC1_WAKE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetCOCPU_INT_RAW_COCPU_SARADC2_WAKE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.COCPU_INT_RAW.Reg, volatile.LoadUint32(&o.COCPU_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetCOCPU_INT_RAW_COCPU_SARADC2_WAKE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.COCPU_INT_RAW.Reg) & 0x20) >> 5
}

// RTCADC.INT_ENA: Interrupt enable registers.
func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC1_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC1_ERROR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC1_ERROR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC2_ERROR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC2_ERROR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC1_WAKE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC1_WAKE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetINT_ENA_COCPU_SARADC2_WAKE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetINT_ENA_COCPU_SARADC2_WAKE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}

// RTCADC.INT_ST: Interrupt status registers.
func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC1_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC1_ERROR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC1_ERROR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC2_ERROR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC2_ERROR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC1_WAKE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC1_WAKE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetINT_ST_COCPU_SARADC2_WAKE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetINT_ST_COCPU_SARADC2_WAKE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}

// RTCADC.INT_CLR: Interrupt clear registers.
func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC1_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC1_ERROR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC1_ERROR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC2_ERROR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC2_ERROR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC1_WAKE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC1_WAKE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetINT_CLR_COCPU_SARADC2_WAKE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetINT_CLR_COCPU_SARADC2_WAKE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}

// RTCADC.INT_ENA_W1TS: Interrupt enable assert registers.
func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC1_INT_ENA_W1TS(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC1_INT_ENA_W1TS() uint32 {
	return volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x1
}
func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC2_INT_ENA_W1TS(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC2_INT_ENA_W1TS() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x2) >> 1
}
func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC1_ERROR_INT_ENA_W1TS(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x4)|value<<2)
}
func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC1_ERROR_INT_ENA_W1TS() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x4) >> 2
}
func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC2_ERROR_INT_ENA_W1TS(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC2_ERROR_INT_ENA_W1TS() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC1_WAKE_INT_ENA_W1TS(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC1_WAKE_INT_ENA_W1TS() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetINT_ENA_W1TS_COCPU_SARADC2_WAKE_INT_ENA_W1TS(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetINT_ENA_W1TS_COCPU_SARADC2_WAKE_INT_ENA_W1TS() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x20) >> 5
}

// RTCADC.INT_ENA_W1TC: Interrupt enable deassert registers.
func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC1_INT_ENA_W1TC(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC1_INT_ENA_W1TC() uint32 {
	return volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x1
}
func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC2_INT_ENA_W1TC(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC2_INT_ENA_W1TC() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x2) >> 1
}
func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC1_ERROR_INT_ENA_W1TC(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x4)|value<<2)
}
func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC1_ERROR_INT_ENA_W1TC() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x4) >> 2
}
func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC2_ERROR_INT_ENA_W1TC(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x8)|value<<3)
}
func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC2_ERROR_INT_ENA_W1TC() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x8) >> 3
}
func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC1_WAKE_INT_ENA_W1TC(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x10)|value<<4)
}
func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC1_WAKE_INT_ENA_W1TC() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x10) >> 4
}
func (o *RTCADC_Type) SetINT_ENA_W1TC_COCPU_SARADC2_WAKE_INT_ENA_W1TC(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x20)|value<<5)
}
func (o *RTCADC_Type) GetINT_ENA_W1TC_COCPU_SARADC2_WAKE_INT_ENA_W1TC() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x20) >> 5
}

// RTCADC.WAKEUP1: ADC1 wakeup configuration registers.
func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_TH_LOW(value uint32) {
	volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0xfff)|value)
}
func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_TH_LOW() uint32 {
	return volatile.LoadUint32(&o.WAKEUP1.Reg) & 0xfff
}
func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_TH_HIGH(value uint32) {
	volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x3ffc000)|value<<14)
}
func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_TH_HIGH() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x3ffc000) >> 14
}
func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_OVER_UPPER_TH(value uint32) {
	volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x20000000)|value<<29)
}
func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_OVER_UPPER_TH() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x20000000) >> 29
}
func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x40000000)|value<<30)
}
func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x40000000) >> 30
}
func (o *RTCADC_Type) SetWAKEUP1_SAR1_WAKEUP_MODE(value uint32) {
	volatile.StoreUint32(&o.WAKEUP1.Reg, volatile.LoadUint32(&o.WAKEUP1.Reg)&^(0x80000000)|value<<31)
}
func (o *RTCADC_Type) GetWAKEUP1_SAR1_WAKEUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP1.Reg) & 0x80000000) >> 31
}

// RTCADC.WAKEUP2: ADC2 wakeup configuration registers.
func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_TH_LOW(value uint32) {
	volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0xfff)|value)
}
func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_TH_LOW() uint32 {
	return volatile.LoadUint32(&o.WAKEUP2.Reg) & 0xfff
}
func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_TH_HIGH(value uint32) {
	volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x3ffc000)|value<<14)
}
func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_TH_HIGH() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x3ffc000) >> 14
}
func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_OVER_UPPER_TH(value uint32) {
	volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x20000000)|value<<29)
}
func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_OVER_UPPER_TH() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x20000000) >> 29
}
func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x40000000)|value<<30)
}
func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x40000000) >> 30
}
func (o *RTCADC_Type) SetWAKEUP2_SAR2_WAKEUP_MODE(value uint32) {
	volatile.StoreUint32(&o.WAKEUP2.Reg, volatile.LoadUint32(&o.WAKEUP2.Reg)&^(0x80000000)|value<<31)
}
func (o *RTCADC_Type) GetWAKEUP2_SAR2_WAKEUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP2.Reg) & 0x80000000) >> 31
}

// RTCADC.WAKEUP_SEL: Wakeup source select register.
func (o *RTCADC_Type) SetWAKEUP_SEL_SAR_WAKEUP_SEL(value uint32) {
	volatile.StoreUint32(&o.WAKEUP_SEL.Reg, volatile.LoadUint32(&o.WAKEUP_SEL.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetWAKEUP_SEL_SAR_WAKEUP_SEL() uint32 {
	return volatile.LoadUint32(&o.WAKEUP_SEL.Reg) & 0x1
}

// RTCADC.SAR1_HW_WAKEUP: Hardware automatic sampling registers for wakeup function.
func (o *RTCADC_Type) SetSAR1_HW_WAKEUP_ADC1_HW_READ_EN_I(value uint32) {
	volatile.StoreUint32(&o.SAR1_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetSAR1_HW_WAKEUP_ADC1_HW_READ_EN_I() uint32 {
	return volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg) & 0x1
}
func (o *RTCADC_Type) SetSAR1_HW_WAKEUP_ADC1_HW_READ_RATE_I(value uint32) {
	volatile.StoreUint32(&o.SAR1_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg)&^(0x1fffe)|value<<1)
}
func (o *RTCADC_Type) GetSAR1_HW_WAKEUP_ADC1_HW_READ_RATE_I() uint32 {
	return (volatile.LoadUint32(&o.SAR1_HW_WAKEUP.Reg) & 0x1fffe) >> 1
}

// RTCADC.SAR2_HW_WAKEUP: Hardware automatic sampling registers for wakeup function.
func (o *RTCADC_Type) SetSAR2_HW_WAKEUP_ADC2_HW_READ_EN_I(value uint32) {
	volatile.StoreUint32(&o.SAR2_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetSAR2_HW_WAKEUP_ADC2_HW_READ_EN_I() uint32 {
	return volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg) & 0x1
}
func (o *RTCADC_Type) SetSAR2_HW_WAKEUP_ADC2_HW_READ_RATE_I(value uint32) {
	volatile.StoreUint32(&o.SAR2_HW_WAKEUP.Reg, volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg)&^(0x1fffe)|value<<1)
}
func (o *RTCADC_Type) GetSAR2_HW_WAKEUP_ADC2_HW_READ_RATE_I() uint32 {
	return (volatile.LoadUint32(&o.SAR2_HW_WAKEUP.Reg) & 0x1fffe) >> 1
}

// RTCADC.RND_ECO_LOW: N/A
func (o *RTCADC_Type) SetRND_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value)
}
func (o *RTCADC_Type) GetRND_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_LOW.Reg)
}

// RTCADC.RND_ECO_HIGH: N/A
func (o *RTCADC_Type) SetRND_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value)
}
func (o *RTCADC_Type) GetRND_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg)
}

// RTCADC.RND_ECO_CS: N/A
func (o *RTCADC_Type) SetRND_ECO_CS_RND_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value)
}
func (o *RTCADC_Type) GetRND_ECO_CS_RND_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1
}
func (o *RTCADC_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *RTCADC_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1
}

// Low-power Timer
type RTC_TIMER_Type struct {
	TAR0_LOW       volatile.Register32 // 0x0
	TAR0_HIGH      volatile.Register32 // 0x4
	TAR1_LOW       volatile.Register32 // 0x8
	TAR1_HIGH      volatile.Register32 // 0xC
	UPDATE         volatile.Register32 // 0x10
	MAIN_BUF0_LOW  volatile.Register32 // 0x14
	MAIN_BUF0_HIGH volatile.Register32 // 0x18
	MAIN_BUF1_LOW  volatile.Register32 // 0x1C
	MAIN_BUF1_HIGH volatile.Register32 // 0x20
	MAIN_OVERFLOW  volatile.Register32 // 0x24
	INT_RAW        volatile.Register32 // 0x28
	INT_ST         volatile.Register32 // 0x2C
	INT_ENA        volatile.Register32 // 0x30
	INT_CLR        volatile.Register32 // 0x34
	LP_INT_RAW     volatile.Register32 // 0x38
	LP_INT_ST      volatile.Register32 // 0x3C
	LP_INT_ENA     volatile.Register32 // 0x40
	LP_INT_CLR     volatile.Register32 // 0x44
	_              [948]byte
	DATE           volatile.Register32 // 0x3FC
}

// RTC_TIMER.TAR0_LOW: need_des
func (o *RTC_TIMER_Type) SetTAR0_LOW(value uint32) {
	volatile.StoreUint32(&o.TAR0_LOW.Reg, value)
}
func (o *RTC_TIMER_Type) GetTAR0_LOW() uint32 {
	return volatile.LoadUint32(&o.TAR0_LOW.Reg)
}

// RTC_TIMER.TAR0_HIGH: need_des
func (o *RTC_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0(value uint32) {
	volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0xffff)|value)
}
func (o *RTC_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_HIGH0() uint32 {
	return volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0xffff
}
func (o *RTC_TIMER_Type) SetTAR0_HIGH_MAIN_TIMER_TAR_EN0(value uint32) {
	volatile.StoreUint32(&o.TAR0_HIGH.Reg, volatile.LoadUint32(&o.TAR0_HIGH.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetTAR0_HIGH_MAIN_TIMER_TAR_EN0() uint32 {
	return (volatile.LoadUint32(&o.TAR0_HIGH.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.TAR1_LOW: need_des
func (o *RTC_TIMER_Type) SetTAR1_LOW(value uint32) {
	volatile.StoreUint32(&o.TAR1_LOW.Reg, value)
}
func (o *RTC_TIMER_Type) GetTAR1_LOW() uint32 {
	return volatile.LoadUint32(&o.TAR1_LOW.Reg)
}

// RTC_TIMER.TAR1_HIGH: need_des
func (o *RTC_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1(value uint32) {
	volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0xffff)|value)
}
func (o *RTC_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_HIGH1() uint32 {
	return volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0xffff
}
func (o *RTC_TIMER_Type) SetTAR1_HIGH_MAIN_TIMER_TAR_EN1(value uint32) {
	volatile.StoreUint32(&o.TAR1_HIGH.Reg, volatile.LoadUint32(&o.TAR1_HIGH.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetTAR1_HIGH_MAIN_TIMER_TAR_EN1() uint32 {
	return (volatile.LoadUint32(&o.TAR1_HIGH.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.UPDATE: need_des
func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_UPDATE(value uint32) {
	volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x10000000)|value<<28)
}
func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x10000000) >> 28
}
func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_XTAL_OFF(value uint32) {
	volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x20000000)|value<<29)
}
func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_XTAL_OFF() uint32 {
	return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x20000000) >> 29
}
func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_STALL(value uint32) {
	volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_STALL() uint32 {
	return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetUPDATE_MAIN_TIMER_SYS_RST(value uint32) {
	volatile.StoreUint32(&o.UPDATE.Reg, volatile.LoadUint32(&o.UPDATE.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetUPDATE_MAIN_TIMER_SYS_RST() uint32 {
	return (volatile.LoadUint32(&o.UPDATE.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.MAIN_BUF0_LOW: need_des
func (o *RTC_TIMER_Type) SetMAIN_BUF0_LOW(value uint32) {
	volatile.StoreUint32(&o.MAIN_BUF0_LOW.Reg, value)
}
func (o *RTC_TIMER_Type) GetMAIN_BUF0_LOW() uint32 {
	return volatile.LoadUint32(&o.MAIN_BUF0_LOW.Reg)
}

// RTC_TIMER.MAIN_BUF0_HIGH: need_des
func (o *RTC_TIMER_Type) SetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH(value uint32) {
	volatile.StoreUint32(&o.MAIN_BUF0_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg)&^(0xffff)|value)
}
func (o *RTC_TIMER_Type) GetMAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH() uint32 {
	return volatile.LoadUint32(&o.MAIN_BUF0_HIGH.Reg) & 0xffff
}

// RTC_TIMER.MAIN_BUF1_LOW: need_des
func (o *RTC_TIMER_Type) SetMAIN_BUF1_LOW(value uint32) {
	volatile.StoreUint32(&o.MAIN_BUF1_LOW.Reg, value)
}
func (o *RTC_TIMER_Type) GetMAIN_BUF1_LOW() uint32 {
	return volatile.LoadUint32(&o.MAIN_BUF1_LOW.Reg)
}

// RTC_TIMER.MAIN_BUF1_HIGH: need_des
func (o *RTC_TIMER_Type) SetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH(value uint32) {
	volatile.StoreUint32(&o.MAIN_BUF1_HIGH.Reg, volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg)&^(0xffff)|value)
}
func (o *RTC_TIMER_Type) GetMAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH() uint32 {
	return volatile.LoadUint32(&o.MAIN_BUF1_HIGH.Reg) & 0xffff
}

// RTC_TIMER.MAIN_OVERFLOW: need_des
func (o *RTC_TIMER_Type) SetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD(value uint32) {
	volatile.StoreUint32(&o.MAIN_OVERFLOW.Reg, volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetMAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD() uint32 {
	return (volatile.LoadUint32(&o.MAIN_OVERFLOW.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.INT_RAW: need_des
func (o *RTC_TIMER_Type) SetINT_RAW_OVERFLOW_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetINT_RAW_OVERFLOW_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetINT_RAW_SOC_WAKEUP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetINT_RAW_SOC_WAKEUP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.INT_ST: need_des
func (o *RTC_TIMER_Type) SetINT_ST_OVERFLOW_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetINT_ST_OVERFLOW_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetINT_ST_SOC_WAKEUP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetINT_ST_SOC_WAKEUP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.INT_ENA: need_des
func (o *RTC_TIMER_Type) SetINT_ENA_OVERFLOW_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetINT_ENA_OVERFLOW_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetINT_ENA_SOC_WAKEUP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetINT_ENA_SOC_WAKEUP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.INT_CLR: need_des
func (o *RTC_TIMER_Type) SetINT_CLR_OVERFLOW_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetINT_CLR_OVERFLOW_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetINT_CLR_SOC_WAKEUP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetINT_CLR_SOC_WAKEUP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.LP_INT_RAW: need_des
func (o *RTC_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.LP_INT_RAW.Reg, volatile.LoadUint32(&o.LP_INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetLP_INT_RAW_MAIN_TIMER_LP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_RAW.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.LP_INT_ST: need_des
func (o *RTC_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetLP_INT_ST_MAIN_TIMER_LP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ST.Reg, volatile.LoadUint32(&o.LP_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetLP_INT_ST_MAIN_TIMER_LP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ST.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.LP_INT_ENA: need_des
func (o *RTC_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.LP_INT_ENA.Reg, volatile.LoadUint32(&o.LP_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetLP_INT_ENA_MAIN_TIMER_LP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_ENA.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.LP_INT_CLR: need_des
func (o *RTC_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *RTC_TIMER_Type) SetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.LP_INT_CLR.Reg, volatile.LoadUint32(&o.LP_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetLP_INT_CLR_MAIN_TIMER_LP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.LP_INT_CLR.Reg) & 0x80000000) >> 31
}

// RTC_TIMER.DATE: need_des
func (o *RTC_TIMER_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value)
}
func (o *RTC_TIMER_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff
}
func (o *RTC_TIMER_Type) SetDATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TIMER_Type) GetDATE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31
}

// LP_TOUCH Peripheral
type RTC_TOUCH_Type struct {
	INT_RAW        volatile.Register32 // 0x0
	INT_ST         volatile.Register32 // 0x4
	INT_ENA        volatile.Register32 // 0x8
	INT_CLR        volatile.Register32 // 0xC
	CHN_STATUS     volatile.Register32 // 0x10
	STATUS_0       volatile.Register32 // 0x14
	STATUS_1       volatile.Register32 // 0x18
	STATUS_2       volatile.Register32 // 0x1C
	STATUS_3       volatile.Register32 // 0x20
	STATUS_4       volatile.Register32 // 0x24
	STATUS_5       volatile.Register32 // 0x28
	STATUS_6       volatile.Register32 // 0x2C
	STATUS_7       volatile.Register32 // 0x30
	STATUS_8       volatile.Register32 // 0x34
	STATUS_9       volatile.Register32 // 0x38
	STATUS_10      volatile.Register32 // 0x3C
	STATUS_11      volatile.Register32 // 0x40
	STATUS_12      volatile.Register32 // 0x44
	STATUS_13      volatile.Register32 // 0x48
	STATUS_14      volatile.Register32 // 0x4C
	STATUS_15      volatile.Register32 // 0x50
	STATUS_16      volatile.Register32 // 0x54
	STATUS_17      volatile.Register32 // 0x58
	CHN_TMP_STATUS volatile.Register32 // 0x5C
	_              [160]byte
	DATE           volatile.Register32 // 0x100
}

// RTC_TOUCH.INT_RAW: need_des
func (o *RTC_TOUCH_Type) SetINT_RAW_SCAN_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *RTC_TOUCH_Type) GetINT_RAW_SCAN_DONE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *RTC_TOUCH_Type) SetINT_RAW_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *RTC_TOUCH_Type) GetINT_RAW_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *RTC_TOUCH_Type) SetINT_RAW_ACTIVE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *RTC_TOUCH_Type) GetINT_RAW_ACTIVE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *RTC_TOUCH_Type) SetINT_RAW_INACTIVE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *RTC_TOUCH_Type) GetINT_RAW_INACTIVE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *RTC_TOUCH_Type) SetINT_RAW_TIMEOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *RTC_TOUCH_Type) GetINT_RAW_TIMEOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *RTC_TOUCH_Type) SetINT_RAW_APPROACH_LOOP_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *RTC_TOUCH_Type) GetINT_RAW_APPROACH_LOOP_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}

// RTC_TOUCH.INT_ST: need_des
func (o *RTC_TOUCH_Type) SetINT_ST_SCAN_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *RTC_TOUCH_Type) GetINT_ST_SCAN_DONE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *RTC_TOUCH_Type) SetINT_ST_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *RTC_TOUCH_Type) GetINT_ST_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *RTC_TOUCH_Type) SetINT_ST_ACTIVE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *RTC_TOUCH_Type) GetINT_ST_ACTIVE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *RTC_TOUCH_Type) SetINT_ST_INACTIVE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *RTC_TOUCH_Type) GetINT_ST_INACTIVE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *RTC_TOUCH_Type) SetINT_ST_TIMEOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *RTC_TOUCH_Type) GetINT_ST_TIMEOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *RTC_TOUCH_Type) SetINT_ST_APPROACH_LOOP_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *RTC_TOUCH_Type) GetINT_ST_APPROACH_LOOP_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}

// RTC_TOUCH.INT_ENA: need_des
func (o *RTC_TOUCH_Type) SetINT_ENA_SCAN_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *RTC_TOUCH_Type) GetINT_ENA_SCAN_DONE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *RTC_TOUCH_Type) SetINT_ENA_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *RTC_TOUCH_Type) GetINT_ENA_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *RTC_TOUCH_Type) SetINT_ENA_ACTIVE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *RTC_TOUCH_Type) GetINT_ENA_ACTIVE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *RTC_TOUCH_Type) SetINT_ENA_INACTIVE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *RTC_TOUCH_Type) GetINT_ENA_INACTIVE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *RTC_TOUCH_Type) SetINT_ENA_TIMEOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *RTC_TOUCH_Type) GetINT_ENA_TIMEOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *RTC_TOUCH_Type) SetINT_ENA_APPROACH_LOOP_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *RTC_TOUCH_Type) GetINT_ENA_APPROACH_LOOP_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}

// RTC_TOUCH.INT_CLR: need_des
func (o *RTC_TOUCH_Type) SetINT_CLR_SCAN_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *RTC_TOUCH_Type) GetINT_CLR_SCAN_DONE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *RTC_TOUCH_Type) SetINT_CLR_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_TOUCH_Type) GetINT_CLR_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *RTC_TOUCH_Type) SetINT_CLR_ACTIVE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_TOUCH_Type) GetINT_CLR_ACTIVE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *RTC_TOUCH_Type) SetINT_CLR_INACTIVE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_TOUCH_Type) GetINT_CLR_INACTIVE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *RTC_TOUCH_Type) SetINT_CLR_TIMEOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_TOUCH_Type) GetINT_CLR_TIMEOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *RTC_TOUCH_Type) SetINT_CLR_APPROACH_LOOP_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_TOUCH_Type) GetINT_CLR_APPROACH_LOOP_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}

// RTC_TOUCH.CHN_STATUS: need_des
func (o *RTC_TOUCH_Type) SetCHN_STATUS_PAD_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.CHN_STATUS.Reg, volatile.LoadUint32(&o.CHN_STATUS.Reg)&^(0x7fff)|value)
}
func (o *RTC_TOUCH_Type) GetCHN_STATUS_PAD_ACTIVE() uint32 {
	return volatile.LoadUint32(&o.CHN_STATUS.Reg) & 0x7fff
}
func (o *RTC_TOUCH_Type) SetCHN_STATUS_MEAS_DONE(value uint32) {
	volatile.StoreUint32(&o.CHN_STATUS.Reg, volatile.LoadUint32(&o.CHN_STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_TOUCH_Type) GetCHN_STATUS_MEAS_DONE() uint32 {
	return (volatile.LoadUint32(&o.CHN_STATUS.Reg) & 0x8000) >> 15
}
func (o *RTC_TOUCH_Type) SetCHN_STATUS_SCAN_CURR(value uint32) {
	volatile.StoreUint32(&o.CHN_STATUS.Reg, volatile.LoadUint32(&o.CHN_STATUS.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetCHN_STATUS_SCAN_CURR() uint32 {
	return (volatile.LoadUint32(&o.CHN_STATUS.Reg) & 0xf0000) >> 16
}

// RTC_TOUCH.STATUS_0: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_0_PAD0_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_0.Reg, volatile.LoadUint32(&o.STATUS_0.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_0_PAD0_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_0.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_0_PAD0_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_0.Reg, volatile.LoadUint32(&o.STATUS_0.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_0_PAD0_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_0.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_0_PAD0_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_0.Reg, volatile.LoadUint32(&o.STATUS_0.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_0_PAD0_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_0.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_1: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_1_PAD1_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_1.Reg, volatile.LoadUint32(&o.STATUS_1.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_1_PAD1_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_1.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_1_PAD1_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_1.Reg, volatile.LoadUint32(&o.STATUS_1.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_1_PAD1_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_1.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_1_PAD1_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_1.Reg, volatile.LoadUint32(&o.STATUS_1.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_1_PAD1_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_1.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_2: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_2_PAD2_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_2.Reg, volatile.LoadUint32(&o.STATUS_2.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_2_PAD2_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_2.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_2_PAD2_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_2.Reg, volatile.LoadUint32(&o.STATUS_2.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_2_PAD2_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_2.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_2_PAD2_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_2.Reg, volatile.LoadUint32(&o.STATUS_2.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_2_PAD2_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_2.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_3: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_3_PAD3_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_3.Reg, volatile.LoadUint32(&o.STATUS_3.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_3_PAD3_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_3.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_3_PAD3_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_3.Reg, volatile.LoadUint32(&o.STATUS_3.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_3_PAD3_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_3.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_3_PAD3_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_3.Reg, volatile.LoadUint32(&o.STATUS_3.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_3_PAD3_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_3.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_4: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_4_PAD4_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_4.Reg, volatile.LoadUint32(&o.STATUS_4.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_4_PAD4_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_4.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_4_PAD4_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_4.Reg, volatile.LoadUint32(&o.STATUS_4.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_4_PAD4_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_4.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_4_PAD4_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_4.Reg, volatile.LoadUint32(&o.STATUS_4.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_4_PAD4_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_4.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_5: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_5_PAD5_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_5.Reg, volatile.LoadUint32(&o.STATUS_5.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_5_PAD5_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_5.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_5_PAD5_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_5.Reg, volatile.LoadUint32(&o.STATUS_5.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_5_PAD5_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_5.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_5_PAD5_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_5.Reg, volatile.LoadUint32(&o.STATUS_5.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_5_PAD5_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_5.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_6: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_6_PAD6_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_6.Reg, volatile.LoadUint32(&o.STATUS_6.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_6_PAD6_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_6.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_6_PAD6_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_6.Reg, volatile.LoadUint32(&o.STATUS_6.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_6_PAD6_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_6.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_6_PAD6_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_6.Reg, volatile.LoadUint32(&o.STATUS_6.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_6_PAD6_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_6.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_7: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_7_PAD7_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_7.Reg, volatile.LoadUint32(&o.STATUS_7.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_7_PAD7_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_7.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_7_PAD7_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_7.Reg, volatile.LoadUint32(&o.STATUS_7.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_7_PAD7_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_7.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_7_PAD7_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_7.Reg, volatile.LoadUint32(&o.STATUS_7.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_7_PAD7_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_7.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_8: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_8_PAD8_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_8.Reg, volatile.LoadUint32(&o.STATUS_8.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_8_PAD8_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_8.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_8_PAD8_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_8.Reg, volatile.LoadUint32(&o.STATUS_8.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_8_PAD8_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_8.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_8_PAD8_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_8.Reg, volatile.LoadUint32(&o.STATUS_8.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_8_PAD8_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_8.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_9: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_9_PAD9_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_9.Reg, volatile.LoadUint32(&o.STATUS_9.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_9_PAD9_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_9.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_9_PAD9_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_9.Reg, volatile.LoadUint32(&o.STATUS_9.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_9_PAD9_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_9.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_9_PAD9_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_9.Reg, volatile.LoadUint32(&o.STATUS_9.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_9_PAD9_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_9.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_10: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_10_PAD10_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_10.Reg, volatile.LoadUint32(&o.STATUS_10.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_10_PAD10_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_10.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_10_PAD10_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_10.Reg, volatile.LoadUint32(&o.STATUS_10.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_10_PAD10_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_10.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_10_PAD10_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_10.Reg, volatile.LoadUint32(&o.STATUS_10.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_10_PAD10_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_10.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_11: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_11_PAD11_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_11.Reg, volatile.LoadUint32(&o.STATUS_11.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_11_PAD11_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_11.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_11_PAD11_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_11.Reg, volatile.LoadUint32(&o.STATUS_11.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_11_PAD11_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_11.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_11_PAD11_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_11.Reg, volatile.LoadUint32(&o.STATUS_11.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_11_PAD11_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_11.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_12: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_12_PAD12_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_12.Reg, volatile.LoadUint32(&o.STATUS_12.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_12_PAD12_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_12.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_12_PAD12_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_12.Reg, volatile.LoadUint32(&o.STATUS_12.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_12_PAD12_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_12.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_12_PAD12_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_12.Reg, volatile.LoadUint32(&o.STATUS_12.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_12_PAD12_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_12.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_13: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_13_PAD13_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_13.Reg, volatile.LoadUint32(&o.STATUS_13.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_13_PAD13_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_13.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_13_PAD13_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_13.Reg, volatile.LoadUint32(&o.STATUS_13.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_13_PAD13_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_13.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_13_PAD13_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_13.Reg, volatile.LoadUint32(&o.STATUS_13.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_13_PAD13_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_13.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_14: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_14_PAD14_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_14.Reg, volatile.LoadUint32(&o.STATUS_14.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_14_PAD14_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_14.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_14_PAD14_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_14.Reg, volatile.LoadUint32(&o.STATUS_14.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_14_PAD14_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_14.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_14_PAD14_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_14.Reg, volatile.LoadUint32(&o.STATUS_14.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_14_PAD14_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_14.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_15: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_15_SLP_DATA(value uint32) {
	volatile.StoreUint32(&o.STATUS_15.Reg, volatile.LoadUint32(&o.STATUS_15.Reg)&^(0xffff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_15_SLP_DATA() uint32 {
	return volatile.LoadUint32(&o.STATUS_15.Reg) & 0xffff
}
func (o *RTC_TOUCH_Type) SetSTATUS_15_SLP_DEBOUNCE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_15.Reg, volatile.LoadUint32(&o.STATUS_15.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_15_SLP_DEBOUNCE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_15.Reg) & 0x70000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_15_SLP_NEG_NOISE_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_15.Reg, volatile.LoadUint32(&o.STATUS_15.Reg)&^(0x780000)|value<<19)
}
func (o *RTC_TOUCH_Type) GetSTATUS_15_SLP_NEG_NOISE_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_15.Reg) & 0x780000) >> 19
}

// RTC_TOUCH.STATUS_16: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_16_APPROACH_PAD2_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_16_APPROACH_PAD2_CNT() uint32 {
	return volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff
}
func (o *RTC_TOUCH_Type) SetSTATUS_16_APPROACH_PAD1_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff00)|value<<8)
}
func (o *RTC_TOUCH_Type) GetSTATUS_16_APPROACH_PAD1_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff00) >> 8
}
func (o *RTC_TOUCH_Type) SetSTATUS_16_APPROACH_PAD0_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff0000)|value<<16)
}
func (o *RTC_TOUCH_Type) GetSTATUS_16_APPROACH_PAD0_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff0000) >> 16
}
func (o *RTC_TOUCH_Type) SetSTATUS_16_SLP_APPROACH_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_16.Reg, volatile.LoadUint32(&o.STATUS_16.Reg)&^(0xff000000)|value<<24)
}
func (o *RTC_TOUCH_Type) GetSTATUS_16_SLP_APPROACH_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_16.Reg) & 0xff000000) >> 24
}

// RTC_TOUCH.STATUS_17: need_des
func (o *RTC_TOUCH_Type) SetSTATUS_17_DCAP_LPF(value uint32) {
	volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x7f)|value)
}
func (o *RTC_TOUCH_Type) GetSTATUS_17_DCAP_LPF() uint32 {
	return volatile.LoadUint32(&o.STATUS_17.Reg) & 0x7f
}
func (o *RTC_TOUCH_Type) SetSTATUS_17_DRES_LPF(value uint32) {
	volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x180)|value<<7)
}
func (o *RTC_TOUCH_Type) GetSTATUS_17_DRES_LPF() uint32 {
	return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x180) >> 7
}
func (o *RTC_TOUCH_Type) SetSTATUS_17_DRV_LS(value uint32) {
	volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x1e00)|value<<9)
}
func (o *RTC_TOUCH_Type) GetSTATUS_17_DRV_LS() uint32 {
	return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x1e00) >> 9
}
func (o *RTC_TOUCH_Type) SetSTATUS_17_DRV_HS(value uint32) {
	volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x3e000)|value<<13)
}
func (o *RTC_TOUCH_Type) GetSTATUS_17_DRV_HS() uint32 {
	return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x3e000) >> 13
}
func (o *RTC_TOUCH_Type) SetSTATUS_17_DBIAS(value uint32) {
	volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x7c0000)|value<<18)
}
func (o *RTC_TOUCH_Type) GetSTATUS_17_DBIAS() uint32 {
	return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x7c0000) >> 18
}
func (o *RTC_TOUCH_Type) SetSTATUS_17_RTC_FREQ_SCAN_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS_17.Reg, volatile.LoadUint32(&o.STATUS_17.Reg)&^(0x1800000)|value<<23)
}
func (o *RTC_TOUCH_Type) GetSTATUS_17_RTC_FREQ_SCAN_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS_17.Reg) & 0x1800000) >> 23
}

// RTC_TOUCH.CHN_TMP_STATUS: need_des
func (o *RTC_TOUCH_Type) SetCHN_TMP_STATUS_PAD_INACTIVE_STATUS(value uint32) {
	volatile.StoreUint32(&o.CHN_TMP_STATUS.Reg, volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg)&^(0x7fff)|value)
}
func (o *RTC_TOUCH_Type) GetCHN_TMP_STATUS_PAD_INACTIVE_STATUS() uint32 {
	return volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg) & 0x7fff
}
func (o *RTC_TOUCH_Type) SetCHN_TMP_STATUS_PAD_ACTIVE_STATUS(value uint32) {
	volatile.StoreUint32(&o.CHN_TMP_STATUS.Reg, volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg)&^(0x3fff8000)|value<<15)
}
func (o *RTC_TOUCH_Type) GetCHN_TMP_STATUS_PAD_ACTIVE_STATUS() uint32 {
	return (volatile.LoadUint32(&o.CHN_TMP_STATUS.Reg) & 0x3fff8000) >> 15
}

// RTC_TOUCH.DATE: need_des
func (o *RTC_TOUCH_Type) SetDATE_RTC_DATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *RTC_TOUCH_Type) GetDATE_RTC_DATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}
func (o *RTC_TOUCH_Type) SetDATE_RTC_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_TOUCH_Type) GetDATE_RTC_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31
}

// Low-power Watchdog Timer
type RTC_WDT_Type struct {
	CONFIG0      volatile.Register32 // 0x0
	CONFIG1      volatile.Register32 // 0x4
	CONFIG2      volatile.Register32 // 0x8
	CONFIG3      volatile.Register32 // 0xC
	CONFIG4      volatile.Register32 // 0x10
	FEED         volatile.Register32 // 0x14
	WPROTECT     volatile.Register32 // 0x18
	SWD_CONFIG   volatile.Register32 // 0x1C
	SWD_WPROTECT volatile.Register32 // 0x20
	INT_RAW      volatile.Register32 // 0x24
	INT_ST       volatile.Register32 // 0x28
	INT_ENA      volatile.Register32 // 0x2C
	INT_CLR      volatile.Register32 // 0x30
	_            [968]byte
	DATE         volatile.Register32 // 0x3FC
}

// RTC_WDT.CONFIG0: need_des
func (o *RTC_WDT_Type) SetCONFIG0_WDT_CHIP_RESET_WIDTH(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xff)|value)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_CHIP_RESET_WIDTH() uint32 {
	return volatile.LoadUint32(&o.CONFIG0.Reg) & 0xff
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_CHIP_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x100)|value<<8)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_CHIP_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x100) >> 8
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_PAUSE_IN_SLP(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x200)|value<<9)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_PAUSE_IN_SLP() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x200) >> 9
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_APPCPU_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x400)|value<<10)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_APPCPU_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x400) >> 10
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_PROCPU_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x800)|value<<11)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_PROCPU_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x800) >> 11
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x1000) >> 12
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xe000)|value<<13)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_SYS_RESET_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0xe000) >> 13
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x70000)|value<<16)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_CPU_RESET_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x70000) >> 16
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG3(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x380000)|value<<19)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG3() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x380000) >> 19
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG2(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x1c00000)|value<<22)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG2() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x1c00000) >> 22
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG1(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0xe000000)|value<<25)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG1() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0xe000000) >> 25
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_STG0(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x70000000)|value<<28)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_STG0() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x70000000) >> 28
}
func (o *RTC_WDT_Type) SetCONFIG0_WDT_EN(value uint32) {
	volatile.StoreUint32(&o.CONFIG0.Reg, volatile.LoadUint32(&o.CONFIG0.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetCONFIG0_WDT_EN() uint32 {
	return (volatile.LoadUint32(&o.CONFIG0.Reg) & 0x80000000) >> 31
}

// RTC_WDT.CONFIG1: need_des
func (o *RTC_WDT_Type) SetCONFIG1(value uint32) {
	volatile.StoreUint32(&o.CONFIG1.Reg, value)
}
func (o *RTC_WDT_Type) GetCONFIG1() uint32 {
	return volatile.LoadUint32(&o.CONFIG1.Reg)
}

// RTC_WDT.CONFIG2: need_des
func (o *RTC_WDT_Type) SetCONFIG2(value uint32) {
	volatile.StoreUint32(&o.CONFIG2.Reg, value)
}
func (o *RTC_WDT_Type) GetCONFIG2() uint32 {
	return volatile.LoadUint32(&o.CONFIG2.Reg)
}

// RTC_WDT.CONFIG3: need_des
func (o *RTC_WDT_Type) SetCONFIG3(value uint32) {
	volatile.StoreUint32(&o.CONFIG3.Reg, value)
}
func (o *RTC_WDT_Type) GetCONFIG3() uint32 {
	return volatile.LoadUint32(&o.CONFIG3.Reg)
}

// RTC_WDT.CONFIG4: need_des
func (o *RTC_WDT_Type) SetCONFIG4(value uint32) {
	volatile.StoreUint32(&o.CONFIG4.Reg, value)
}
func (o *RTC_WDT_Type) GetCONFIG4() uint32 {
	return volatile.LoadUint32(&o.CONFIG4.Reg)
}

// RTC_WDT.FEED: need_des
func (o *RTC_WDT_Type) SetFEED(value uint32) {
	volatile.StoreUint32(&o.FEED.Reg, volatile.LoadUint32(&o.FEED.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetFEED() uint32 {
	return (volatile.LoadUint32(&o.FEED.Reg) & 0x80000000) >> 31
}

// RTC_WDT.WPROTECT: need_des
func (o *RTC_WDT_Type) SetWPROTECT(value uint32) {
	volatile.StoreUint32(&o.WPROTECT.Reg, value)
}
func (o *RTC_WDT_Type) GetWPROTECT() uint32 {
	return volatile.LoadUint32(&o.WPROTECT.Reg)
}

// RTC_WDT.SWD_CONFIG: need_des
func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_RESET_FLAG(value uint32) {
	volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x1)|value)
}
func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_RESET_FLAG() uint32 {
	return volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x1
}
func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_AUTO_FEED_EN(value uint32) {
	volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x40000)|value<<18)
}
func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_AUTO_FEED_EN() uint32 {
	return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x40000) >> 18
}
func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_RST_FLAG_CLR(value uint32) {
	volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x80000)|value<<19)
}
func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_RST_FLAG_CLR() uint32 {
	return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x80000) >> 19
}
func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_SIGNAL_WIDTH(value uint32) {
	volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x3ff00000)|value<<20)
}
func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_SIGNAL_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x3ff00000) >> 20
}
func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_DISABLE(value uint32) {
	volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_DISABLE() uint32 {
	return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x40000000) >> 30
}
func (o *RTC_WDT_Type) SetSWD_CONFIG_SWD_FEED(value uint32) {
	volatile.StoreUint32(&o.SWD_CONFIG.Reg, volatile.LoadUint32(&o.SWD_CONFIG.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetSWD_CONFIG_SWD_FEED() uint32 {
	return (volatile.LoadUint32(&o.SWD_CONFIG.Reg) & 0x80000000) >> 31
}

// RTC_WDT.SWD_WPROTECT: need_des
func (o *RTC_WDT_Type) SetSWD_WPROTECT(value uint32) {
	volatile.StoreUint32(&o.SWD_WPROTECT.Reg, value)
}
func (o *RTC_WDT_Type) GetSWD_WPROTECT() uint32 {
	return volatile.LoadUint32(&o.SWD_WPROTECT.Reg)
}

// RTC_WDT.INT_RAW: need_des
func (o *RTC_WDT_Type) SetINT_RAW_SUPER_WDT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_WDT_Type) GetINT_RAW_SUPER_WDT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *RTC_WDT_Type) SetINT_RAW_LP_WDT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetINT_RAW_LP_WDT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000000) >> 31
}

// RTC_WDT.INT_ST: need_des
func (o *RTC_WDT_Type) SetINT_ST_SUPER_WDT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_WDT_Type) GetINT_ST_SUPER_WDT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000000) >> 30
}
func (o *RTC_WDT_Type) SetINT_ST_LP_WDT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetINT_ST_LP_WDT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000000) >> 31
}

// RTC_WDT.INT_ENA: need_des
func (o *RTC_WDT_Type) SetINT_ENA_SUPER_WDT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_WDT_Type) GetINT_ENA_SUPER_WDT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *RTC_WDT_Type) SetINT_ENA_LP_WDT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetINT_ENA_LP_WDT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000000) >> 31
}

// RTC_WDT.INT_CLR: need_des
func (o *RTC_WDT_Type) SetINT_CLR_SUPER_WDT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_WDT_Type) GetINT_CLR_SUPER_WDT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *RTC_WDT_Type) SetINT_CLR_LP_WDT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetINT_CLR_LP_WDT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000000) >> 31
}

// RTC_WDT.DATE: need_des
func (o *RTC_WDT_Type) SetDATE_LP_WDT_DATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x7fffffff)|value)
}
func (o *RTC_WDT_Type) GetDATE_LP_WDT_DATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x7fffffff
}
func (o *RTC_WDT_Type) SetDATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_WDT_Type) GetDATE_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.DATE.Reg) & 0x80000000) >> 31
}

// SD/MMC Host Controller
type SDHOST_Type struct {
	CTRL         volatile.Register32 // 0x0
	_            [4]byte
	CLKDIV       volatile.Register32 // 0x8
	CLKSRC       volatile.Register32 // 0xC
	CLKENA       volatile.Register32 // 0x10
	TMOUT        volatile.Register32 // 0x14
	CTYPE        volatile.Register32 // 0x18
	BLKSIZ       volatile.Register32 // 0x1C
	BYTCNT       volatile.Register32 // 0x20
	INTMASK      volatile.Register32 // 0x24
	CMDARG       volatile.Register32 // 0x28
	CMD          volatile.Register32 // 0x2C
	RESP0        volatile.Register32 // 0x30
	RESP1        volatile.Register32 // 0x34
	RESP2        volatile.Register32 // 0x38
	RESP3        volatile.Register32 // 0x3C
	MINTSTS      volatile.Register32 // 0x40
	RINTSTS      volatile.Register32 // 0x44
	STATUS       volatile.Register32 // 0x48
	FIFOTH       volatile.Register32 // 0x4C
	CDETECT      volatile.Register32 // 0x50
	WRTPRT       volatile.Register32 // 0x54
	_            [4]byte
	TCBCNT       volatile.Register32 // 0x5C
	TBBCNT       volatile.Register32 // 0x60
	DEBNCE       volatile.Register32 // 0x64
	USRID        volatile.Register32 // 0x68
	VERID        volatile.Register32 // 0x6C
	HCON         volatile.Register32 // 0x70
	UHS          volatile.Register32 // 0x74
	RST_N        volatile.Register32 // 0x78
	_            [4]byte
	BMOD         volatile.Register32 // 0x80
	PLDMND       volatile.Register32 // 0x84
	DBADDR       volatile.Register32 // 0x88
	IDSTS        volatile.Register32 // 0x8C
	IDINTEN      volatile.Register32 // 0x90
	DSCADDR      volatile.Register32 // 0x94
	BUFADDR      volatile.Register32 // 0x98
	_            [100]byte
	CARDTHRCTL   volatile.Register32 // 0x100
	_            [8]byte
	EMMCDDR      volatile.Register32 // 0x10C
	ENSHIFT      volatile.Register32 // 0x110
	_            [236]byte
	BUFFIFO      volatile.Register32 // 0x200
	_            [1532]byte
	CLK_EDGE_SEL volatile.Register32 // 0x800
	RAW_INTS     volatile.Register32 // 0x804
	DLL_CLK_CONF volatile.Register32 // 0x808
	DLL_CONF     volatile.Register32 // 0x80C
}

// SDHOST.CTRL: Control register
func (o *SDHOST_Type) SetCTRL_CONTROLLER_RESET(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetCTRL_CONTROLLER_RESET() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0x1
}
func (o *SDHOST_Type) SetCTRL_FIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetCTRL_FIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1
}
func (o *SDHOST_Type) SetCTRL_DMA_RESET(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2)
}
func (o *SDHOST_Type) GetCTRL_DMA_RESET() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2
}
func (o *SDHOST_Type) SetCTRL_INT_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4)
}
func (o *SDHOST_Type) GetCTRL_INT_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4
}
func (o *SDHOST_Type) SetCTRL_READ_WAIT(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x40)|value<<6)
}
func (o *SDHOST_Type) GetCTRL_READ_WAIT() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x40) >> 6
}
func (o *SDHOST_Type) SetCTRL_SEND_IRQ_RESPONSE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x80)|value<<7)
}
func (o *SDHOST_Type) GetCTRL_SEND_IRQ_RESPONSE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x80) >> 7
}
func (o *SDHOST_Type) SetCTRL_ABORT_READ_DATA(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8)
}
func (o *SDHOST_Type) GetCTRL_ABORT_READ_DATA() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8
}
func (o *SDHOST_Type) SetCTRL_SEND_CCSD(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9)
}
func (o *SDHOST_Type) GetCTRL_SEND_CCSD() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9
}
func (o *SDHOST_Type) SetCTRL_SEND_AUTO_STOP_CCSD(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10)
}
func (o *SDHOST_Type) GetCTRL_SEND_AUTO_STOP_CCSD() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10
}
func (o *SDHOST_Type) SetCTRL_CEATA_DEVICE_INTERRUPT_STATUS(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800)|value<<11)
}
func (o *SDHOST_Type) GetCTRL_CEATA_DEVICE_INTERRUPT_STATUS() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800) >> 11
}

// SDHOST.CLKDIV: Clock divider configuration register
func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER0(value uint32) {
	volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff)|value)
}
func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER0() uint32 {
	return volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff
}
func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER1(value uint32) {
	volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff00)|value<<8)
}
func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER1() uint32 {
	return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff00) >> 8
}
func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER2(value uint32) {
	volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff0000)|value<<16)
}
func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER2() uint32 {
	return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff0000) >> 16
}
func (o *SDHOST_Type) SetCLKDIV_CLK_DIVIDER3(value uint32) {
	volatile.StoreUint32(&o.CLKDIV.Reg, volatile.LoadUint32(&o.CLKDIV.Reg)&^(0xff000000)|value<<24)
}
func (o *SDHOST_Type) GetCLKDIV_CLK_DIVIDER3() uint32 {
	return (volatile.LoadUint32(&o.CLKDIV.Reg) & 0xff000000) >> 24
}

// SDHOST.CLKSRC: Clock source selection register
func (o *SDHOST_Type) SetCLKSRC(value uint32) {
	volatile.StoreUint32(&o.CLKSRC.Reg, volatile.LoadUint32(&o.CLKSRC.Reg)&^(0xf)|value)
}
func (o *SDHOST_Type) GetCLKSRC() uint32 {
	return volatile.LoadUint32(&o.CLKSRC.Reg) & 0xf
}

// SDHOST.CLKENA: Clock enable register
func (o *SDHOST_Type) SetCLKENA_CCLK_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x3)|value)
}
func (o *SDHOST_Type) GetCLKENA_CCLK_ENABLE() uint32 {
	return volatile.LoadUint32(&o.CLKENA.Reg) & 0x3
}
func (o *SDHOST_Type) SetCLKENA_LP_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CLKENA.Reg, volatile.LoadUint32(&o.CLKENA.Reg)&^(0x30000)|value<<16)
}
func (o *SDHOST_Type) GetCLKENA_LP_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.CLKENA.Reg) & 0x30000) >> 16
}

// SDHOST.TMOUT: Data and response timeout configuration register
func (o *SDHOST_Type) SetTMOUT_RESPONSE_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xff)|value)
}
func (o *SDHOST_Type) GetTMOUT_RESPONSE_TIMEOUT() uint32 {
	return volatile.LoadUint32(&o.TMOUT.Reg) & 0xff
}
func (o *SDHOST_Type) SetTMOUT_DATA_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.TMOUT.Reg, volatile.LoadUint32(&o.TMOUT.Reg)&^(0xffffff00)|value<<8)
}
func (o *SDHOST_Type) GetTMOUT_DATA_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.TMOUT.Reg) & 0xffffff00) >> 8
}

// SDHOST.CTYPE: Card bus width configuration register
func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH4(value uint32) {
	volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x3)|value)
}
func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH4() uint32 {
	return volatile.LoadUint32(&o.CTYPE.Reg) & 0x3
}
func (o *SDHOST_Type) SetCTYPE_CARD_WIDTH8(value uint32) {
	volatile.StoreUint32(&o.CTYPE.Reg, volatile.LoadUint32(&o.CTYPE.Reg)&^(0x30000)|value<<16)
}
func (o *SDHOST_Type) GetCTYPE_CARD_WIDTH8() uint32 {
	return (volatile.LoadUint32(&o.CTYPE.Reg) & 0x30000) >> 16
}

// SDHOST.BLKSIZ: Card data block size configuration register
func (o *SDHOST_Type) SetBLKSIZ_BLOCK_SIZE(value uint32) {
	volatile.StoreUint32(&o.BLKSIZ.Reg, volatile.LoadUint32(&o.BLKSIZ.Reg)&^(0xffff)|value)
}
func (o *SDHOST_Type) GetBLKSIZ_BLOCK_SIZE() uint32 {
	return volatile.LoadUint32(&o.BLKSIZ.Reg) & 0xffff
}

// SDHOST.BYTCNT: Data transfer length configuration register
func (o *SDHOST_Type) SetBYTCNT(value uint32) {
	volatile.StoreUint32(&o.BYTCNT.Reg, value)
}
func (o *SDHOST_Type) GetBYTCNT() uint32 {
	return volatile.LoadUint32(&o.BYTCNT.Reg)
}

// SDHOST.INTMASK: SDIO interrupt mask register
func (o *SDHOST_Type) SetINTMASK_INT_MASK(value uint32) {
	volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0xffff)|value)
}
func (o *SDHOST_Type) GetINTMASK_INT_MASK() uint32 {
	return volatile.LoadUint32(&o.INTMASK.Reg) & 0xffff
}
func (o *SDHOST_Type) SetINTMASK_SDIO_INT_MASK(value uint32) {
	volatile.StoreUint32(&o.INTMASK.Reg, volatile.LoadUint32(&o.INTMASK.Reg)&^(0x30000)|value<<16)
}
func (o *SDHOST_Type) GetINTMASK_SDIO_INT_MASK() uint32 {
	return (volatile.LoadUint32(&o.INTMASK.Reg) & 0x30000) >> 16
}

// SDHOST.CMDARG: Command argument data register
func (o *SDHOST_Type) SetCMDARG(value uint32) {
	volatile.StoreUint32(&o.CMDARG.Reg, value)
}
func (o *SDHOST_Type) GetCMDARG() uint32 {
	return volatile.LoadUint32(&o.CMDARG.Reg)
}

// SDHOST.CMD: Command and boot configuration register
func (o *SDHOST_Type) SetCMD_INDEX(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x3f)|value)
}
func (o *SDHOST_Type) GetCMD_INDEX() uint32 {
	return volatile.LoadUint32(&o.CMD.Reg) & 0x3f
}
func (o *SDHOST_Type) SetCMD_RESPONSE_EXPECT(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x40)|value<<6)
}
func (o *SDHOST_Type) GetCMD_RESPONSE_EXPECT() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x40) >> 6
}
func (o *SDHOST_Type) SetCMD_RESPONSE_LENGTH(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80)|value<<7)
}
func (o *SDHOST_Type) GetCMD_RESPONSE_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x80) >> 7
}
func (o *SDHOST_Type) SetCMD_CHECK_RESPONSE_CRC(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x100)|value<<8)
}
func (o *SDHOST_Type) GetCMD_CHECK_RESPONSE_CRC() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x100) >> 8
}
func (o *SDHOST_Type) SetCMD_DATA_EXPECTED(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200)|value<<9)
}
func (o *SDHOST_Type) GetCMD_DATA_EXPECTED() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x200) >> 9
}
func (o *SDHOST_Type) SetCMD_READ_WRITE(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400)|value<<10)
}
func (o *SDHOST_Type) GetCMD_READ_WRITE() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x400) >> 10
}
func (o *SDHOST_Type) SetCMD_TRANSFER_MODE(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800)|value<<11)
}
func (o *SDHOST_Type) GetCMD_TRANSFER_MODE() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x800) >> 11
}
func (o *SDHOST_Type) SetCMD_SEND_AUTO_STOP(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1000)|value<<12)
}
func (o *SDHOST_Type) GetCMD_SEND_AUTO_STOP() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x1000) >> 12
}
func (o *SDHOST_Type) SetCMD_WAIT_PRVDATA_COMPLETE(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2000)|value<<13)
}
func (o *SDHOST_Type) GetCMD_WAIT_PRVDATA_COMPLETE() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x2000) >> 13
}
func (o *SDHOST_Type) SetCMD_STOP_ABORT_CMD(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4000)|value<<14)
}
func (o *SDHOST_Type) GetCMD_STOP_ABORT_CMD() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x4000) >> 14
}
func (o *SDHOST_Type) SetCMD_SEND_INITIALIZATION(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8000)|value<<15)
}
func (o *SDHOST_Type) GetCMD_SEND_INITIALIZATION() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x8000) >> 15
}
func (o *SDHOST_Type) SetCMD_CARD_NUMBER(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1f0000)|value<<16)
}
func (o *SDHOST_Type) GetCMD_CARD_NUMBER() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x1f0000) >> 16
}
func (o *SDHOST_Type) SetCMD_UPDATE_CLOCK_REGISTERS_ONLY(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x200000)|value<<21)
}
func (o *SDHOST_Type) GetCMD_UPDATE_CLOCK_REGISTERS_ONLY() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x200000) >> 21
}
func (o *SDHOST_Type) SetCMD_READ_CEATA_DEVICE(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x400000)|value<<22)
}
func (o *SDHOST_Type) GetCMD_READ_CEATA_DEVICE() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x400000) >> 22
}
func (o *SDHOST_Type) SetCMD_CCS_EXPECTED(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x800000)|value<<23)
}
func (o *SDHOST_Type) GetCMD_CCS_EXPECTED() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x800000) >> 23
}
func (o *SDHOST_Type) SetCMD_USE_HOLE(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x20000000)|value<<29)
}
func (o *SDHOST_Type) GetCMD_USE_HOLE() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x20000000) >> 29
}
func (o *SDHOST_Type) SetCMD_START_CMD(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x80000000)|value<<31)
}
func (o *SDHOST_Type) GetCMD_START_CMD() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x80000000) >> 31
}

// SDHOST.RESP0: Response data register
func (o *SDHOST_Type) SetRESP0(value uint32) {
	volatile.StoreUint32(&o.RESP0.Reg, value)
}
func (o *SDHOST_Type) GetRESP0() uint32 {
	return volatile.LoadUint32(&o.RESP0.Reg)
}

// SDHOST.RESP1: Long response data register
func (o *SDHOST_Type) SetRESP1(value uint32) {
	volatile.StoreUint32(&o.RESP1.Reg, value)
}
func (o *SDHOST_Type) GetRESP1() uint32 {
	return volatile.LoadUint32(&o.RESP1.Reg)
}

// SDHOST.RESP2: Long response data register
func (o *SDHOST_Type) SetRESP2(value uint32) {
	volatile.StoreUint32(&o.RESP2.Reg, value)
}
func (o *SDHOST_Type) GetRESP2() uint32 {
	return volatile.LoadUint32(&o.RESP2.Reg)
}

// SDHOST.RESP3: Long response data register
func (o *SDHOST_Type) SetRESP3(value uint32) {
	volatile.StoreUint32(&o.RESP3.Reg, value)
}
func (o *SDHOST_Type) GetRESP3() uint32 {
	return volatile.LoadUint32(&o.RESP3.Reg)
}

// SDHOST.MINTSTS: Masked interrupt status register
func (o *SDHOST_Type) SetMINTSTS_INT_STATUS_MSK(value uint32) {
	volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0xffff)|value)
}
func (o *SDHOST_Type) GetMINTSTS_INT_STATUS_MSK() uint32 {
	return volatile.LoadUint32(&o.MINTSTS.Reg) & 0xffff
}
func (o *SDHOST_Type) SetMINTSTS_SDIO_INTERRUPT_MSK(value uint32) {
	volatile.StoreUint32(&o.MINTSTS.Reg, volatile.LoadUint32(&o.MINTSTS.Reg)&^(0x30000)|value<<16)
}
func (o *SDHOST_Type) GetMINTSTS_SDIO_INTERRUPT_MSK() uint32 {
	return (volatile.LoadUint32(&o.MINTSTS.Reg) & 0x30000) >> 16
}

// SDHOST.RINTSTS: Raw interrupt status register
func (o *SDHOST_Type) SetRINTSTS_INT_STATUS_RAW(value uint32) {
	volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0xffff)|value)
}
func (o *SDHOST_Type) GetRINTSTS_INT_STATUS_RAW() uint32 {
	return volatile.LoadUint32(&o.RINTSTS.Reg) & 0xffff
}
func (o *SDHOST_Type) SetRINTSTS_SDIO_INTERRUPT_RAW(value uint32) {
	volatile.StoreUint32(&o.RINTSTS.Reg, volatile.LoadUint32(&o.RINTSTS.Reg)&^(0x30000)|value<<16)
}
func (o *SDHOST_Type) GetRINTSTS_SDIO_INTERRUPT_RAW() uint32 {
	return (volatile.LoadUint32(&o.RINTSTS.Reg) & 0x30000) >> 16
}

// SDHOST.STATUS: SD/MMC status register
func (o *SDHOST_Type) SetSTATUS_FIFO_RX_WATERMARK(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetSTATUS_FIFO_RX_WATERMARK() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg) & 0x1
}
func (o *SDHOST_Type) SetSTATUS_FIFO_TX_WATERMARK(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetSTATUS_FIFO_TX_WATERMARK() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1
}
func (o *SDHOST_Type) SetSTATUS_FIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2)
}
func (o *SDHOST_Type) GetSTATUS_FIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2
}
func (o *SDHOST_Type) SetSTATUS_FIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3)
}
func (o *SDHOST_Type) GetSTATUS_FIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3
}
func (o *SDHOST_Type) SetSTATUS_COMMAND_FSM_STATES(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xf0)|value<<4)
}
func (o *SDHOST_Type) GetSTATUS_COMMAND_FSM_STATES() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0xf0) >> 4
}
func (o *SDHOST_Type) SetSTATUS_DATA_3_STATUS(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8)
}
func (o *SDHOST_Type) GetSTATUS_DATA_3_STATUS() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8
}
func (o *SDHOST_Type) SetSTATUS_DATA_BUSY(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x200)|value<<9)
}
func (o *SDHOST_Type) GetSTATUS_DATA_BUSY() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x200) >> 9
}
func (o *SDHOST_Type) SetSTATUS_DATA_STATE_MC_BUSY(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x400)|value<<10)
}
func (o *SDHOST_Type) GetSTATUS_DATA_STATE_MC_BUSY() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x400) >> 10
}
func (o *SDHOST_Type) SetSTATUS_RESPONSE_INDEX(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1f800)|value<<11)
}
func (o *SDHOST_Type) GetSTATUS_RESPONSE_INDEX() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x1f800) >> 11
}
func (o *SDHOST_Type) SetSTATUS_FIFO_COUNT(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x3ffe0000)|value<<17)
}
func (o *SDHOST_Type) GetSTATUS_FIFO_COUNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x3ffe0000) >> 17
}

// SDHOST.FIFOTH: FIFO configuration register
func (o *SDHOST_Type) SetFIFOTH_TX_WMARK(value uint32) {
	volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0xfff)|value)
}
func (o *SDHOST_Type) GetFIFOTH_TX_WMARK() uint32 {
	return volatile.LoadUint32(&o.FIFOTH.Reg) & 0xfff
}
func (o *SDHOST_Type) SetFIFOTH_RX_WMARK(value uint32) {
	volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x7ff0000)|value<<16)
}
func (o *SDHOST_Type) GetFIFOTH_RX_WMARK() uint32 {
	return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x7ff0000) >> 16
}
func (o *SDHOST_Type) SetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE(value uint32) {
	volatile.StoreUint32(&o.FIFOTH.Reg, volatile.LoadUint32(&o.FIFOTH.Reg)&^(0x70000000)|value<<28)
}
func (o *SDHOST_Type) GetFIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE() uint32 {
	return (volatile.LoadUint32(&o.FIFOTH.Reg) & 0x70000000) >> 28
}

// SDHOST.CDETECT: Card detect register
func (o *SDHOST_Type) SetCDETECT_CARD_DETECT_N(value uint32) {
	volatile.StoreUint32(&o.CDETECT.Reg, volatile.LoadUint32(&o.CDETECT.Reg)&^(0x3)|value)
}
func (o *SDHOST_Type) GetCDETECT_CARD_DETECT_N() uint32 {
	return volatile.LoadUint32(&o.CDETECT.Reg) & 0x3
}

// SDHOST.WRTPRT: Card write protection (WP) status register
func (o *SDHOST_Type) SetWRTPRT_WRITE_PROTECT(value uint32) {
	volatile.StoreUint32(&o.WRTPRT.Reg, volatile.LoadUint32(&o.WRTPRT.Reg)&^(0x3)|value)
}
func (o *SDHOST_Type) GetWRTPRT_WRITE_PROTECT() uint32 {
	return volatile.LoadUint32(&o.WRTPRT.Reg) & 0x3
}

// SDHOST.TCBCNT: Transferred byte count register
func (o *SDHOST_Type) SetTCBCNT(value uint32) {
	volatile.StoreUint32(&o.TCBCNT.Reg, value)
}
func (o *SDHOST_Type) GetTCBCNT() uint32 {
	return volatile.LoadUint32(&o.TCBCNT.Reg)
}

// SDHOST.TBBCNT: Transferred byte count register
func (o *SDHOST_Type) SetTBBCNT(value uint32) {
	volatile.StoreUint32(&o.TBBCNT.Reg, value)
}
func (o *SDHOST_Type) GetTBBCNT() uint32 {
	return volatile.LoadUint32(&o.TBBCNT.Reg)
}

// SDHOST.DEBNCE: Debounce filter time configuration register
func (o *SDHOST_Type) SetDEBNCE_DEBOUNCE_COUNT(value uint32) {
	volatile.StoreUint32(&o.DEBNCE.Reg, volatile.LoadUint32(&o.DEBNCE.Reg)&^(0xffffff)|value)
}
func (o *SDHOST_Type) GetDEBNCE_DEBOUNCE_COUNT() uint32 {
	return volatile.LoadUint32(&o.DEBNCE.Reg) & 0xffffff
}

// SDHOST.USRID: User ID (scratchpad) register
func (o *SDHOST_Type) SetUSRID(value uint32) {
	volatile.StoreUint32(&o.USRID.Reg, value)
}
func (o *SDHOST_Type) GetUSRID() uint32 {
	return volatile.LoadUint32(&o.USRID.Reg)
}

// SDHOST.VERID: Version ID (scratchpad) register
func (o *SDHOST_Type) SetVERID(value uint32) {
	volatile.StoreUint32(&o.VERID.Reg, value)
}
func (o *SDHOST_Type) GetVERID() uint32 {
	return volatile.LoadUint32(&o.VERID.Reg)
}

// SDHOST.HCON: Hardware feature register
func (o *SDHOST_Type) SetHCON_CARD_TYPE(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetHCON_CARD_TYPE() uint32 {
	return volatile.LoadUint32(&o.HCON.Reg) & 0x1
}
func (o *SDHOST_Type) SetHCON_CARD_NUM(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3e)|value<<1)
}
func (o *SDHOST_Type) GetHCON_CARD_NUM() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0x3e) >> 1
}
func (o *SDHOST_Type) SetHCON_BUS_TYPE(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x40)|value<<6)
}
func (o *SDHOST_Type) GetHCON_BUS_TYPE() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0x40) >> 6
}
func (o *SDHOST_Type) SetHCON_DATA_WIDTH(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x380)|value<<7)
}
func (o *SDHOST_Type) GetHCON_DATA_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0x380) >> 7
}
func (o *SDHOST_Type) SetHCON_ADDR_WIDTH(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0xfc00)|value<<10)
}
func (o *SDHOST_Type) GetHCON_ADDR_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0xfc00) >> 10
}
func (o *SDHOST_Type) SetHCON_DMA_WIDTH(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x1c0000)|value<<18)
}
func (o *SDHOST_Type) GetHCON_DMA_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0x1c0000) >> 18
}
func (o *SDHOST_Type) SetHCON_RAM_INDISE(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x200000)|value<<21)
}
func (o *SDHOST_Type) GetHCON_RAM_INDISE() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0x200000) >> 21
}
func (o *SDHOST_Type) SetHCON_HOLD(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x400000)|value<<22)
}
func (o *SDHOST_Type) GetHCON_HOLD() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0x400000) >> 22
}
func (o *SDHOST_Type) SetHCON_NUM_CLK_DIV(value uint32) {
	volatile.StoreUint32(&o.HCON.Reg, volatile.LoadUint32(&o.HCON.Reg)&^(0x3000000)|value<<24)
}
func (o *SDHOST_Type) GetHCON_NUM_CLK_DIV() uint32 {
	return (volatile.LoadUint32(&o.HCON.Reg) & 0x3000000) >> 24
}

// SDHOST.UHS: UHS-1 register
func (o *SDHOST_Type) SetUHS_DDR(value uint32) {
	volatile.StoreUint32(&o.UHS.Reg, volatile.LoadUint32(&o.UHS.Reg)&^(0x30000)|value<<16)
}
func (o *SDHOST_Type) GetUHS_DDR() uint32 {
	return (volatile.LoadUint32(&o.UHS.Reg) & 0x30000) >> 16
}

// SDHOST.RST_N: Card reset register
func (o *SDHOST_Type) SetRST_N_CARD_RESET(value uint32) {
	volatile.StoreUint32(&o.RST_N.Reg, volatile.LoadUint32(&o.RST_N.Reg)&^(0x3)|value)
}
func (o *SDHOST_Type) GetRST_N_CARD_RESET() uint32 {
	return volatile.LoadUint32(&o.RST_N.Reg) & 0x3
}

// SDHOST.BMOD: Burst mode transfer configuration register
func (o *SDHOST_Type) SetBMOD_SWR(value uint32) {
	volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetBMOD_SWR() uint32 {
	return volatile.LoadUint32(&o.BMOD.Reg) & 0x1
}
func (o *SDHOST_Type) SetBMOD_FB(value uint32) {
	volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetBMOD_FB() uint32 {
	return (volatile.LoadUint32(&o.BMOD.Reg) & 0x2) >> 1
}
func (o *SDHOST_Type) SetBMOD_DE(value uint32) {
	volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x80)|value<<7)
}
func (o *SDHOST_Type) GetBMOD_DE() uint32 {
	return (volatile.LoadUint32(&o.BMOD.Reg) & 0x80) >> 7
}
func (o *SDHOST_Type) SetBMOD_PBL(value uint32) {
	volatile.StoreUint32(&o.BMOD.Reg, volatile.LoadUint32(&o.BMOD.Reg)&^(0x700)|value<<8)
}
func (o *SDHOST_Type) GetBMOD_PBL() uint32 {
	return (volatile.LoadUint32(&o.BMOD.Reg) & 0x700) >> 8
}

// SDHOST.PLDMND: Poll demand configuration register
func (o *SDHOST_Type) SetPLDMND(value uint32) {
	volatile.StoreUint32(&o.PLDMND.Reg, value)
}
func (o *SDHOST_Type) GetPLDMND() uint32 {
	return volatile.LoadUint32(&o.PLDMND.Reg)
}

// SDHOST.DBADDR: Descriptor base address register
func (o *SDHOST_Type) SetDBADDR(value uint32) {
	volatile.StoreUint32(&o.DBADDR.Reg, value)
}
func (o *SDHOST_Type) GetDBADDR() uint32 {
	return volatile.LoadUint32(&o.DBADDR.Reg)
}

// SDHOST.IDSTS: IDMAC status register
func (o *SDHOST_Type) SetIDSTS_TI(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetIDSTS_TI() uint32 {
	return volatile.LoadUint32(&o.IDSTS.Reg) & 0x1
}
func (o *SDHOST_Type) SetIDSTS_RI(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetIDSTS_RI() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x2) >> 1
}
func (o *SDHOST_Type) SetIDSTS_FBE(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x4)|value<<2)
}
func (o *SDHOST_Type) GetIDSTS_FBE() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x4) >> 2
}
func (o *SDHOST_Type) SetIDSTS_DU(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x10)|value<<4)
}
func (o *SDHOST_Type) GetIDSTS_DU() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x10) >> 4
}
func (o *SDHOST_Type) SetIDSTS_CES(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x20)|value<<5)
}
func (o *SDHOST_Type) GetIDSTS_CES() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x20) >> 5
}
func (o *SDHOST_Type) SetIDSTS_NIS(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x100)|value<<8)
}
func (o *SDHOST_Type) GetIDSTS_NIS() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x100) >> 8
}
func (o *SDHOST_Type) SetIDSTS_AIS(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x200)|value<<9)
}
func (o *SDHOST_Type) GetIDSTS_AIS() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x200) >> 9
}
func (o *SDHOST_Type) SetIDSTS_FBE_CODE(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1c00)|value<<10)
}
func (o *SDHOST_Type) GetIDSTS_FBE_CODE() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1c00) >> 10
}
func (o *SDHOST_Type) SetIDSTS_FSM(value uint32) {
	volatile.StoreUint32(&o.IDSTS.Reg, volatile.LoadUint32(&o.IDSTS.Reg)&^(0x1e000)|value<<13)
}
func (o *SDHOST_Type) GetIDSTS_FSM() uint32 {
	return (volatile.LoadUint32(&o.IDSTS.Reg) & 0x1e000) >> 13
}

// SDHOST.IDINTEN: IDMAC interrupt enable register
func (o *SDHOST_Type) SetIDINTEN_TI(value uint32) {
	volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetIDINTEN_TI() uint32 {
	return volatile.LoadUint32(&o.IDINTEN.Reg) & 0x1
}
func (o *SDHOST_Type) SetIDINTEN_RI(value uint32) {
	volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetIDINTEN_RI() uint32 {
	return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x2) >> 1
}
func (o *SDHOST_Type) SetIDINTEN_FBE(value uint32) {
	volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x4)|value<<2)
}
func (o *SDHOST_Type) GetIDINTEN_FBE() uint32 {
	return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x4) >> 2
}
func (o *SDHOST_Type) SetIDINTEN_DU(value uint32) {
	volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x10)|value<<4)
}
func (o *SDHOST_Type) GetIDINTEN_DU() uint32 {
	return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x10) >> 4
}
func (o *SDHOST_Type) SetIDINTEN_CES(value uint32) {
	volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x20)|value<<5)
}
func (o *SDHOST_Type) GetIDINTEN_CES() uint32 {
	return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x20) >> 5
}
func (o *SDHOST_Type) SetIDINTEN_NI(value uint32) {
	volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x100)|value<<8)
}
func (o *SDHOST_Type) GetIDINTEN_NI() uint32 {
	return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x100) >> 8
}
func (o *SDHOST_Type) SetIDINTEN_AI(value uint32) {
	volatile.StoreUint32(&o.IDINTEN.Reg, volatile.LoadUint32(&o.IDINTEN.Reg)&^(0x200)|value<<9)
}
func (o *SDHOST_Type) GetIDINTEN_AI() uint32 {
	return (volatile.LoadUint32(&o.IDINTEN.Reg) & 0x200) >> 9
}

// SDHOST.DSCADDR: Host descriptor address pointer
func (o *SDHOST_Type) SetDSCADDR(value uint32) {
	volatile.StoreUint32(&o.DSCADDR.Reg, value)
}
func (o *SDHOST_Type) GetDSCADDR() uint32 {
	return volatile.LoadUint32(&o.DSCADDR.Reg)
}

// SDHOST.BUFADDR: Host buffer address pointer register
func (o *SDHOST_Type) SetBUFADDR(value uint32) {
	volatile.StoreUint32(&o.BUFADDR.Reg, value)
}
func (o *SDHOST_Type) GetBUFADDR() uint32 {
	return volatile.LoadUint32(&o.BUFADDR.Reg)
}

// SDHOST.CARDTHRCTL: Card Threshold Control register
func (o *SDHOST_Type) SetCARDTHRCTL_CARDRDTHREN(value uint32) {
	volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetCARDTHRCTL_CARDRDTHREN() uint32 {
	return volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x1
}
func (o *SDHOST_Type) SetCARDTHRCTL_CARDCLRINTEN(value uint32) {
	volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetCARDTHRCTL_CARDCLRINTEN() uint32 {
	return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x2) >> 1
}
func (o *SDHOST_Type) SetCARDTHRCTL_CARDWRTHREN(value uint32) {
	volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0x4)|value<<2)
}
func (o *SDHOST_Type) GetCARDTHRCTL_CARDWRTHREN() uint32 {
	return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0x4) >> 2
}
func (o *SDHOST_Type) SetCARDTHRCTL_CARDTHRESHOLD(value uint32) {
	volatile.StoreUint32(&o.CARDTHRCTL.Reg, volatile.LoadUint32(&o.CARDTHRCTL.Reg)&^(0xffff0000)|value<<16)
}
func (o *SDHOST_Type) GetCARDTHRCTL_CARDTHRESHOLD() uint32 {
	return (volatile.LoadUint32(&o.CARDTHRCTL.Reg) & 0xffff0000) >> 16
}

// SDHOST.EMMCDDR: eMMC DDR register
func (o *SDHOST_Type) SetEMMCDDR_HALFSTARTBIT(value uint32) {
	volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x3)|value)
}
func (o *SDHOST_Type) GetEMMCDDR_HALFSTARTBIT() uint32 {
	return volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x3
}
func (o *SDHOST_Type) SetEMMCDDR_HS400_MODE(value uint32) {
	volatile.StoreUint32(&o.EMMCDDR.Reg, volatile.LoadUint32(&o.EMMCDDR.Reg)&^(0x80000000)|value<<31)
}
func (o *SDHOST_Type) GetEMMCDDR_HS400_MODE() uint32 {
	return (volatile.LoadUint32(&o.EMMCDDR.Reg) & 0x80000000) >> 31
}

// SDHOST.ENSHIFT: Enable Phase Shift register
func (o *SDHOST_Type) SetENSHIFT_ENABLE_SHIFT(value uint32) {
	volatile.StoreUint32(&o.ENSHIFT.Reg, volatile.LoadUint32(&o.ENSHIFT.Reg)&^(0xf)|value)
}
func (o *SDHOST_Type) GetENSHIFT_ENABLE_SHIFT() uint32 {
	return volatile.LoadUint32(&o.ENSHIFT.Reg) & 0xf
}

// SDHOST.BUFFIFO: CPU write and read transmit data by FIFO
func (o *SDHOST_Type) SetBUFFIFO(value uint32) {
	volatile.StoreUint32(&o.BUFFIFO.Reg, value)
}
func (o *SDHOST_Type) GetBUFFIFO() uint32 {
	return volatile.LoadUint32(&o.BUFFIFO.Reg)
}

// SDHOST.CLK_EDGE_SEL: SDIO control register.
func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x7)|value)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL() uint32 {
	return volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x7
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x38)|value<<3)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x38) >> 3
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1c0)|value<<6)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1c0) >> 6
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_H(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e00)|value<<9)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_H() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e00) >> 9
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_L(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e000)|value<<13)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_L() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e000) >> 13
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLLKIN_EDGE_N(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1e0000)|value<<17)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLLKIN_EDGE_N() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1e0000) >> 17
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESDIO_MODE(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x200000)|value<<21)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESDIO_MODE() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x200000) >> 21
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_ESD_MODE(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x400000)|value<<22)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_ESD_MODE() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x400000) >> 22
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_CCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x800000)|value<<23)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_CCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x800000) >> 23
}
func (o *SDHOST_Type) SetCLK_EDGE_SEL_ULTRA_HIGH_SPEED_MODE(value uint32) {
	volatile.StoreUint32(&o.CLK_EDGE_SEL.Reg, volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg)&^(0x1000000)|value<<24)
}
func (o *SDHOST_Type) GetCLK_EDGE_SEL_ULTRA_HIGH_SPEED_MODE() uint32 {
	return (volatile.LoadUint32(&o.CLK_EDGE_SEL.Reg) & 0x1000000) >> 24
}

// SDHOST.RAW_INTS: SDIO raw ints register.
func (o *SDHOST_Type) SetRAW_INTS(value uint32) {
	volatile.StoreUint32(&o.RAW_INTS.Reg, value)
}
func (o *SDHOST_Type) GetRAW_INTS() uint32 {
	return volatile.LoadUint32(&o.RAW_INTS.Reg)
}

// SDHOST.DLL_CLK_CONF: SDIO DLL clock control register.
func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SLF_EN(value uint32) {
	volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SLF_EN() uint32 {
	return volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x1
}
func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_DRV_EN(value uint32) {
	volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_DRV_EN() uint32 {
	return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x2) >> 1
}
func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SAM_EN(value uint32) {
	volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x4)|value<<2)
}
func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SAM_EN() uint32 {
	return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x4) >> 2
}
func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SLF_PHASE(value uint32) {
	volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x1f8)|value<<3)
}
func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SLF_PHASE() uint32 {
	return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x1f8) >> 3
}
func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_DRV_PHASE(value uint32) {
	volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x7e00)|value<<9)
}
func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_DRV_PHASE() uint32 {
	return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x7e00) >> 9
}
func (o *SDHOST_Type) SetDLL_CLK_CONF_DLL_CCLK_IN_SAM_PHASE(value uint32) {
	volatile.StoreUint32(&o.DLL_CLK_CONF.Reg, volatile.LoadUint32(&o.DLL_CLK_CONF.Reg)&^(0x1f8000)|value<<15)
}
func (o *SDHOST_Type) GetDLL_CLK_CONF_DLL_CCLK_IN_SAM_PHASE() uint32 {
	return (volatile.LoadUint32(&o.DLL_CLK_CONF.Reg) & 0x1f8000) >> 15
}

// SDHOST.DLL_CONF: SDIO DLL configuration register.
func (o *SDHOST_Type) SetDLL_CONF_DLL_CAL_STOP(value uint32) {
	volatile.StoreUint32(&o.DLL_CONF.Reg, volatile.LoadUint32(&o.DLL_CONF.Reg)&^(0x1)|value)
}
func (o *SDHOST_Type) GetDLL_CONF_DLL_CAL_STOP() uint32 {
	return volatile.LoadUint32(&o.DLL_CONF.Reg) & 0x1
}
func (o *SDHOST_Type) SetDLL_CONF_DLL_CAL_END(value uint32) {
	volatile.StoreUint32(&o.DLL_CONF.Reg, volatile.LoadUint32(&o.DLL_CONF.Reg)&^(0x2)|value<<1)
}
func (o *SDHOST_Type) GetDLL_CONF_DLL_CAL_END() uint32 {
	return (volatile.LoadUint32(&o.DLL_CONF.Reg) & 0x2) >> 1
}

// SHA (Secure Hash Algorithm) Accelerator
type SHA_Type struct {
	MODE          volatile.Register32 // 0x0
	T_STRING      volatile.Register32 // 0x4
	T_LENGTH      volatile.Register32 // 0x8
	DMA_BLOCK_NUM volatile.Register32 // 0xC
	START         volatile.Register32 // 0x10
	CONTINUE      volatile.Register32 // 0x14
	BUSY          volatile.Register32 // 0x18
	DMA_START     volatile.Register32 // 0x1C
	DMA_CONTINUE  volatile.Register32 // 0x20
	CLEAR_IRQ     volatile.Register32 // 0x24
	IRQ_ENA       volatile.Register32 // 0x28
	DATE          volatile.Register32 // 0x2C
	_             [16]byte
	H_MEM         [16]volatile.Register32 // 0x40
	M_MEM         [16]volatile.Register32 // 0x80
}

// SHA.MODE: Initial configuration register.
func (o *SHA_Type) SetMODE(value uint32) {
	volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x7)|value)
}
func (o *SHA_Type) GetMODE() uint32 {
	return volatile.LoadUint32(&o.MODE.Reg) & 0x7
}

// SHA.T_STRING: SHA 512/t configuration register 0.
func (o *SHA_Type) SetT_STRING(value uint32) {
	volatile.StoreUint32(&o.T_STRING.Reg, value)
}
func (o *SHA_Type) GetT_STRING() uint32 {
	return volatile.LoadUint32(&o.T_STRING.Reg)
}

// SHA.T_LENGTH: SHA 512/t configuration register 1.
func (o *SHA_Type) SetT_LENGTH(value uint32) {
	volatile.StoreUint32(&o.T_LENGTH.Reg, volatile.LoadUint32(&o.T_LENGTH.Reg)&^(0x3f)|value)
}
func (o *SHA_Type) GetT_LENGTH() uint32 {
	return volatile.LoadUint32(&o.T_LENGTH.Reg) & 0x3f
}

// SHA.DMA_BLOCK_NUM: DMA configuration register 0.
func (o *SHA_Type) SetDMA_BLOCK_NUM(value uint32) {
	volatile.StoreUint32(&o.DMA_BLOCK_NUM.Reg, volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg)&^(0x3f)|value)
}
func (o *SHA_Type) GetDMA_BLOCK_NUM() uint32 {
	return volatile.LoadUint32(&o.DMA_BLOCK_NUM.Reg) & 0x3f
}

// SHA.START: Typical SHA configuration register 0.
func (o *SHA_Type) SetSTART(value uint32) {
	volatile.StoreUint32(&o.START.Reg, volatile.LoadUint32(&o.START.Reg)&^(0xfffffffe)|value<<1)
}
func (o *SHA_Type) GetSTART() uint32 {
	return (volatile.LoadUint32(&o.START.Reg) & 0xfffffffe) >> 1
}

// SHA.CONTINUE: Typical SHA configuration register 1.
func (o *SHA_Type) SetCONTINUE(value uint32) {
	volatile.StoreUint32(&o.CONTINUE.Reg, volatile.LoadUint32(&o.CONTINUE.Reg)&^(0xfffffffe)|value<<1)
}
func (o *SHA_Type) GetCONTINUE() uint32 {
	return (volatile.LoadUint32(&o.CONTINUE.Reg) & 0xfffffffe) >> 1
}

// SHA.BUSY: Busy register.
func (o *SHA_Type) SetBUSY_STATE(value uint32) {
	volatile.StoreUint32(&o.BUSY.Reg, volatile.LoadUint32(&o.BUSY.Reg)&^(0x1)|value)
}
func (o *SHA_Type) GetBUSY_STATE() uint32 {
	return volatile.LoadUint32(&o.BUSY.Reg) & 0x1
}

// SHA.DMA_START: DMA configuration register 1.
func (o *SHA_Type) SetDMA_START(value uint32) {
	volatile.StoreUint32(&o.DMA_START.Reg, volatile.LoadUint32(&o.DMA_START.Reg)&^(0x1)|value)
}
func (o *SHA_Type) GetDMA_START() uint32 {
	return volatile.LoadUint32(&o.DMA_START.Reg) & 0x1
}

// SHA.DMA_CONTINUE: DMA configuration register 2.
func (o *SHA_Type) SetDMA_CONTINUE(value uint32) {
	volatile.StoreUint32(&o.DMA_CONTINUE.Reg, volatile.LoadUint32(&o.DMA_CONTINUE.Reg)&^(0x1)|value)
}
func (o *SHA_Type) GetDMA_CONTINUE() uint32 {
	return volatile.LoadUint32(&o.DMA_CONTINUE.Reg) & 0x1
}

// SHA.CLEAR_IRQ: Interrupt clear register.
func (o *SHA_Type) SetCLEAR_IRQ_CLEAR_INTERRUPT(value uint32) {
	volatile.StoreUint32(&o.CLEAR_IRQ.Reg, volatile.LoadUint32(&o.CLEAR_IRQ.Reg)&^(0x1)|value)
}
func (o *SHA_Type) GetCLEAR_IRQ_CLEAR_INTERRUPT() uint32 {
	return volatile.LoadUint32(&o.CLEAR_IRQ.Reg) & 0x1
}

// SHA.IRQ_ENA: Interrupt enable register.
func (o *SHA_Type) SetIRQ_ENA_INTERRUPT_ENA(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENA.Reg, volatile.LoadUint32(&o.IRQ_ENA.Reg)&^(0x1)|value)
}
func (o *SHA_Type) GetIRQ_ENA_INTERRUPT_ENA() uint32 {
	return volatile.LoadUint32(&o.IRQ_ENA.Reg) & 0x1
}

// SHA.DATE: Date register.
func (o *SHA_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0x3fffffff)|value)
}
func (o *SHA_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0x3fffffff
}

// Event Task Matrix
type SOC_ETM_Type struct {
	CH_ENA_AD0     volatile.Register32 // 0x0
	CH_ENA_AD0_SET volatile.Register32 // 0x4
	CH_ENA_AD0_CLR volatile.Register32 // 0x8
	CH_ENA_AD1     volatile.Register32 // 0xC
	CH_ENA_AD1_SET volatile.Register32 // 0x10
	CH_ENA_AD1_CLR volatile.Register32 // 0x14
	CH0_EVT_ID     volatile.Register32 // 0x18
	CH0_TASK_ID    volatile.Register32 // 0x1C
	CH1_EVT_ID     volatile.Register32 // 0x20
	CH1_TASK_ID    volatile.Register32 // 0x24
	CH2_EVT_ID     volatile.Register32 // 0x28
	CH2_TASK_ID    volatile.Register32 // 0x2C
	CH3_EVT_ID     volatile.Register32 // 0x30
	CH3_TASK_ID    volatile.Register32 // 0x34
	CH4_EVT_ID     volatile.Register32 // 0x38
	CH4_TASK_ID    volatile.Register32 // 0x3C
	CH5_EVT_ID     volatile.Register32 // 0x40
	CH5_TASK_ID    volatile.Register32 // 0x44
	CH6_EVT_ID     volatile.Register32 // 0x48
	CH6_TASK_ID    volatile.Register32 // 0x4C
	CH7_EVT_ID     volatile.Register32 // 0x50
	CH7_TASK_ID    volatile.Register32 // 0x54
	CH8_EVT_ID     volatile.Register32 // 0x58
	CH8_TASK_ID    volatile.Register32 // 0x5C
	CH9_EVT_ID     volatile.Register32 // 0x60
	CH9_TASK_ID    volatile.Register32 // 0x64
	CH10_EVT_ID    volatile.Register32 // 0x68
	CH10_TASK_ID   volatile.Register32 // 0x6C
	CH11_EVT_ID    volatile.Register32 // 0x70
	CH11_TASK_ID   volatile.Register32 // 0x74
	CH12_EVT_ID    volatile.Register32 // 0x78
	CH12_TASK_ID   volatile.Register32 // 0x7C
	CH13_EVT_ID    volatile.Register32 // 0x80
	CH13_TASK_ID   volatile.Register32 // 0x84
	CH14_EVT_ID    volatile.Register32 // 0x88
	CH14_TASK_ID   volatile.Register32 // 0x8C
	CH15_EVT_ID    volatile.Register32 // 0x90
	CH15_TASK_ID   volatile.Register32 // 0x94
	CH16_EVT_ID    volatile.Register32 // 0x98
	CH16_TASK_ID   volatile.Register32 // 0x9C
	CH17_EVT_ID    volatile.Register32 // 0xA0
	CH17_TASK_ID   volatile.Register32 // 0xA4
	CH18_EVT_ID    volatile.Register32 // 0xA8
	CH18_TASK_ID   volatile.Register32 // 0xAC
	CH19_EVT_ID    volatile.Register32 // 0xB0
	CH19_TASK_ID   volatile.Register32 // 0xB4
	CH20_EVT_ID    volatile.Register32 // 0xB8
	CH20_TASK_ID   volatile.Register32 // 0xBC
	CH21_EVT_ID    volatile.Register32 // 0xC0
	CH21_TASK_ID   volatile.Register32 // 0xC4
	CH22_EVT_ID    volatile.Register32 // 0xC8
	CH22_TASK_ID   volatile.Register32 // 0xCC
	CH23_EVT_ID    volatile.Register32 // 0xD0
	CH23_TASK_ID   volatile.Register32 // 0xD4
	CH24_EVT_ID    volatile.Register32 // 0xD8
	CH24_TASK_ID   volatile.Register32 // 0xDC
	CH25_EVT_ID    volatile.Register32 // 0xE0
	CH25_TASK_ID   volatile.Register32 // 0xE4
	CH26_EVT_ID    volatile.Register32 // 0xE8
	CH26_TASK_ID   volatile.Register32 // 0xEC
	CH27_EVT_ID    volatile.Register32 // 0xF0
	CH27_TASK_ID   volatile.Register32 // 0xF4
	CH28_EVT_ID    volatile.Register32 // 0xF8
	CH28_TASK_ID   volatile.Register32 // 0xFC
	CH29_EVT_ID    volatile.Register32 // 0x100
	CH29_TASK_ID   volatile.Register32 // 0x104
	CH30_EVT_ID    volatile.Register32 // 0x108
	CH30_TASK_ID   volatile.Register32 // 0x10C
	CH31_EVT_ID    volatile.Register32 // 0x110
	CH31_TASK_ID   volatile.Register32 // 0x114
	CH32_EVT_ID    volatile.Register32 // 0x118
	CH32_TASK_ID   volatile.Register32 // 0x11C
	CH33_EVT_ID    volatile.Register32 // 0x120
	CH33_TASK_ID   volatile.Register32 // 0x124
	CH34_EVT_ID    volatile.Register32 // 0x128
	CH34_TASK_ID   volatile.Register32 // 0x12C
	CH35_EVT_ID    volatile.Register32 // 0x130
	CH35_TASK_ID   volatile.Register32 // 0x134
	CH36_EVT_ID    volatile.Register32 // 0x138
	CH36_TASK_ID   volatile.Register32 // 0x13C
	CH37_EVT_ID    volatile.Register32 // 0x140
	CH37_TASK_ID   volatile.Register32 // 0x144
	CH38_EVT_ID    volatile.Register32 // 0x148
	CH38_TASK_ID   volatile.Register32 // 0x14C
	CH39_EVT_ID    volatile.Register32 // 0x150
	CH39_TASK_ID   volatile.Register32 // 0x154
	CH40_EVT_ID    volatile.Register32 // 0x158
	CH40_TASK_ID   volatile.Register32 // 0x15C
	CH41_EVT_ID    volatile.Register32 // 0x160
	CH41_TASK_ID   volatile.Register32 // 0x164
	CH42_EVT_ID    volatile.Register32 // 0x168
	CH42_TASK_ID   volatile.Register32 // 0x16C
	CH43_EVT_ID    volatile.Register32 // 0x170
	CH43_TASK_ID   volatile.Register32 // 0x174
	CH44_EVT_ID    volatile.Register32 // 0x178
	CH44_TASK_ID   volatile.Register32 // 0x17C
	CH45_EVT_ID    volatile.Register32 // 0x180
	CH45_TASK_ID   volatile.Register32 // 0x184
	CH46_EVT_ID    volatile.Register32 // 0x188
	CH46_TASK_ID   volatile.Register32 // 0x18C
	CH47_EVT_ID    volatile.Register32 // 0x190
	CH47_TASK_ID   volatile.Register32 // 0x194
	CH48_EVT_ID    volatile.Register32 // 0x198
	CH48_TASK_ID   volatile.Register32 // 0x19C
	CH49_EVT_ID    volatile.Register32 // 0x1A0
	CH49_TASK_ID   volatile.Register32 // 0x1A4
	EVT_ST0        volatile.Register32 // 0x1A8
	EVT_ST0_CLR    volatile.Register32 // 0x1AC
	EVT_ST1        volatile.Register32 // 0x1B0
	EVT_ST1_CLR    volatile.Register32 // 0x1B4
	EVT_ST2        volatile.Register32 // 0x1B8
	EVT_ST2_CLR    volatile.Register32 // 0x1BC
	EVT_ST3        volatile.Register32 // 0x1C0
	EVT_ST3_CLR    volatile.Register32 // 0x1C4
	EVT_ST4        volatile.Register32 // 0x1C8
	EVT_ST4_CLR    volatile.Register32 // 0x1CC
	EVT_ST5        volatile.Register32 // 0x1D0
	EVT_ST5_CLR    volatile.Register32 // 0x1D4
	EVT_ST6        volatile.Register32 // 0x1D8
	EVT_ST6_CLR    volatile.Register32 // 0x1DC
	EVT_ST7        volatile.Register32 // 0x1E0
	EVT_ST7_CLR    volatile.Register32 // 0x1E4
	TASK_ST0       volatile.Register32 // 0x1E8
	TASK_ST0_CLR   volatile.Register32 // 0x1EC
	TASK_ST1       volatile.Register32 // 0x1F0
	TASK_ST1_CLR   volatile.Register32 // 0x1F4
	TASK_ST2       volatile.Register32 // 0x1F8
	TASK_ST2_CLR   volatile.Register32 // 0x1FC
	TASK_ST3       volatile.Register32 // 0x200
	TASK_ST3_CLR   volatile.Register32 // 0x204
	TASK_ST4       volatile.Register32 // 0x208
	TASK_ST4_CLR   volatile.Register32 // 0x20C
	TASK_ST5       volatile.Register32 // 0x210
	TASK_ST5_CLR   volatile.Register32 // 0x214
	TASK_ST6       volatile.Register32 // 0x218
	TASK_ST6_CLR   volatile.Register32 // 0x21C
	CLK_EN         volatile.Register32 // 0x220
	DATE           volatile.Register32 // 0x224
}

// SOC_ETM.CH_ENA_AD0: Channel enable status register
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA0(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA0() uint32 {
	return volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA1(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA1() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA2(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA2() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA3(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA3() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA4(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA4() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA5(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA5() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA6(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA6() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA7(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA7() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA8(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA8() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA9(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA9() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA10(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA10() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA11(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA11() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA12(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA12() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA13(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA13() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA14(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA14() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA15(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA15() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA16(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA16() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA17(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA17() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA18(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA18() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA19(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA19() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA20(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA20() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA21(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA21() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA22(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA22() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA23(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA23() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA24(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA24() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA25(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA25() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA26(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA26() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA27(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA27() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA28(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA28() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA29(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA29() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA30(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA30() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CH_ENA31(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0.Reg, volatile.LoadUint32(&o.CH_ENA_AD0.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CH_ENA31() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0.Reg) & 0x80000000) >> 31
}

// SOC_ETM.CH_ENA_AD0_SET: Channel enable set register
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET0(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET0() uint32 {
	return volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET1(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET1() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET2(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET2() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET3(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET3() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET4(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET4() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET5(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET5() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET6(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET6() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET7(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET7() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET8(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET8() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET9(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET9() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET10(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET10() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET11(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET11() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET12(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET12() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET13(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET13() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET14(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET14() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET15(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET15() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET16(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET16() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET17(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET17() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET18(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET18() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET19(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET19() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET20(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET20() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET21(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET21() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET22(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET22() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET23(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET23() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET24(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET24() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET25(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET25() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET26(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET26() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET27(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET27() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET28(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET28() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET29(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET29() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET30(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET30() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_SET_CH_SET31(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_SET_CH_SET31() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_SET.Reg) & 0x80000000) >> 31
}

// SOC_ETM.CH_ENA_AD0_CLR: Channel enable clear register
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR0(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR0() uint32 {
	return volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR1(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR1() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR2(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR2() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR3(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR3() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR4(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR4() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR5(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR5() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR6(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR6() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR7(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR7() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR8(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR8() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR9(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR9() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR10(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR10() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR11(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR11() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR12(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR12() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR13(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR13() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR14(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR14() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR15(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR15() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR16(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR16() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR17(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR17() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR18(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR18() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR19(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR19() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR20(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR20() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR21(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR21() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR22(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR22() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR23(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR23() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR24(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR24() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR25(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR25() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR26(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR26() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR27(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR27() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR28(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR28() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR29(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR29() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR30(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR30() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetCH_ENA_AD0_CLR_CH_CLR31(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD0_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD0_CLR_CH_CLR31() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD0_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.CH_ENA_AD1: Channel enable status register
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA32(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA32() uint32 {
	return volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA33(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA33() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA34(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA34() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA35(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA35() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA36(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA36() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA37(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA37() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA38(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA38() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA39(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA39() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA40(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA40() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA41(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA41() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA42(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA42() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA43(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA43() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA44(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA44() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA45(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA45() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA46(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA46() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA47(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA47() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA48(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA48() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CH_ENA49(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1.Reg, volatile.LoadUint32(&o.CH_ENA_AD1.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CH_ENA49() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1.Reg) & 0x20000) >> 17
}

// SOC_ETM.CH_ENA_AD1_SET: Channel enable set register
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET32(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET32() uint32 {
	return volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET33(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET33() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET34(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET34() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET35(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET35() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET36(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET36() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET37(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET37() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET38(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET38() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET39(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET39() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET40(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET40() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET41(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET41() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET42(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET42() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET43(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET43() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET44(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET44() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET45(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET45() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET46(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET46() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET47(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET47() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET48(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET48() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_SET_CH_SET49(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_SET.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_SET_CH_SET49() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_SET.Reg) & 0x20000) >> 17
}

// SOC_ETM.CH_ENA_AD1_CLR: Channel enable clear register
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR32(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR32() uint32 {
	return volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR33(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR33() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR34(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR34() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR35(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR35() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR36(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR36() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR37(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR37() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR38(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR38() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR39(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR39() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR40(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR40() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR41(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR41() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR42(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR42() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR43(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR43() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR44(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR44() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR45(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR45() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR46(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR46() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR47(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR47() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR48(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR48() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetCH_ENA_AD1_CLR_CH_CLR49(value uint32) {
	volatile.StoreUint32(&o.CH_ENA_AD1_CLR.Reg, volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetCH_ENA_AD1_CLR_CH_CLR49() uint32 {
	return (volatile.LoadUint32(&o.CH_ENA_AD1_CLR.Reg) & 0x20000) >> 17
}

// SOC_ETM.CH0_EVT_ID: Channel0 event id register
func (o *SOC_ETM_Type) SetCH0_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH0_EVT_ID.Reg, volatile.LoadUint32(&o.CH0_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH0_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH0_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH0_TASK_ID: Channel0 task id register
func (o *SOC_ETM_Type) SetCH0_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH0_TASK_ID.Reg, volatile.LoadUint32(&o.CH0_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH0_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH0_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH1_EVT_ID: Channel1 event id register
func (o *SOC_ETM_Type) SetCH1_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH1_EVT_ID.Reg, volatile.LoadUint32(&o.CH1_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH1_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH1_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH1_TASK_ID: Channel1 task id register
func (o *SOC_ETM_Type) SetCH1_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH1_TASK_ID.Reg, volatile.LoadUint32(&o.CH1_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH1_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH1_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH2_EVT_ID: Channel2 event id register
func (o *SOC_ETM_Type) SetCH2_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH2_EVT_ID.Reg, volatile.LoadUint32(&o.CH2_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH2_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH2_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH2_TASK_ID: Channel2 task id register
func (o *SOC_ETM_Type) SetCH2_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH2_TASK_ID.Reg, volatile.LoadUint32(&o.CH2_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH2_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH2_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH3_EVT_ID: Channel3 event id register
func (o *SOC_ETM_Type) SetCH3_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH3_EVT_ID.Reg, volatile.LoadUint32(&o.CH3_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH3_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH3_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH3_TASK_ID: Channel3 task id register
func (o *SOC_ETM_Type) SetCH3_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH3_TASK_ID.Reg, volatile.LoadUint32(&o.CH3_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH3_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH3_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH4_EVT_ID: Channel4 event id register
func (o *SOC_ETM_Type) SetCH4_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH4_EVT_ID.Reg, volatile.LoadUint32(&o.CH4_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH4_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH4_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH4_TASK_ID: Channel4 task id register
func (o *SOC_ETM_Type) SetCH4_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH4_TASK_ID.Reg, volatile.LoadUint32(&o.CH4_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH4_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH4_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH5_EVT_ID: Channel5 event id register
func (o *SOC_ETM_Type) SetCH5_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH5_EVT_ID.Reg, volatile.LoadUint32(&o.CH5_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH5_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH5_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH5_TASK_ID: Channel5 task id register
func (o *SOC_ETM_Type) SetCH5_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH5_TASK_ID.Reg, volatile.LoadUint32(&o.CH5_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH5_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH5_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH6_EVT_ID: Channel6 event id register
func (o *SOC_ETM_Type) SetCH6_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH6_EVT_ID.Reg, volatile.LoadUint32(&o.CH6_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH6_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH6_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH6_TASK_ID: Channel6 task id register
func (o *SOC_ETM_Type) SetCH6_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH6_TASK_ID.Reg, volatile.LoadUint32(&o.CH6_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH6_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH6_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH7_EVT_ID: Channel7 event id register
func (o *SOC_ETM_Type) SetCH7_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH7_EVT_ID.Reg, volatile.LoadUint32(&o.CH7_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH7_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH7_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH7_TASK_ID: Channel7 task id register
func (o *SOC_ETM_Type) SetCH7_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH7_TASK_ID.Reg, volatile.LoadUint32(&o.CH7_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH7_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH7_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH8_EVT_ID: Channel8 event id register
func (o *SOC_ETM_Type) SetCH8_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH8_EVT_ID.Reg, volatile.LoadUint32(&o.CH8_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH8_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH8_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH8_TASK_ID: Channel8 task id register
func (o *SOC_ETM_Type) SetCH8_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH8_TASK_ID.Reg, volatile.LoadUint32(&o.CH8_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH8_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH8_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH9_EVT_ID: Channel9 event id register
func (o *SOC_ETM_Type) SetCH9_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH9_EVT_ID.Reg, volatile.LoadUint32(&o.CH9_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH9_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH9_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH9_TASK_ID: Channel9 task id register
func (o *SOC_ETM_Type) SetCH9_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH9_TASK_ID.Reg, volatile.LoadUint32(&o.CH9_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH9_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH9_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH10_EVT_ID: Channel10 event id register
func (o *SOC_ETM_Type) SetCH10_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH10_EVT_ID.Reg, volatile.LoadUint32(&o.CH10_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH10_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH10_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH10_TASK_ID: Channel10 task id register
func (o *SOC_ETM_Type) SetCH10_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH10_TASK_ID.Reg, volatile.LoadUint32(&o.CH10_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH10_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH10_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH11_EVT_ID: Channel11 event id register
func (o *SOC_ETM_Type) SetCH11_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH11_EVT_ID.Reg, volatile.LoadUint32(&o.CH11_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH11_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH11_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH11_TASK_ID: Channel11 task id register
func (o *SOC_ETM_Type) SetCH11_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH11_TASK_ID.Reg, volatile.LoadUint32(&o.CH11_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH11_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH11_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH12_EVT_ID: Channel12 event id register
func (o *SOC_ETM_Type) SetCH12_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH12_EVT_ID.Reg, volatile.LoadUint32(&o.CH12_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH12_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH12_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH12_TASK_ID: Channel12 task id register
func (o *SOC_ETM_Type) SetCH12_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH12_TASK_ID.Reg, volatile.LoadUint32(&o.CH12_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH12_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH12_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH13_EVT_ID: Channel13 event id register
func (o *SOC_ETM_Type) SetCH13_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH13_EVT_ID.Reg, volatile.LoadUint32(&o.CH13_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH13_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH13_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH13_TASK_ID: Channel13 task id register
func (o *SOC_ETM_Type) SetCH13_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH13_TASK_ID.Reg, volatile.LoadUint32(&o.CH13_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH13_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH13_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH14_EVT_ID: Channel14 event id register
func (o *SOC_ETM_Type) SetCH14_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH14_EVT_ID.Reg, volatile.LoadUint32(&o.CH14_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH14_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH14_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH14_TASK_ID: Channel14 task id register
func (o *SOC_ETM_Type) SetCH14_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH14_TASK_ID.Reg, volatile.LoadUint32(&o.CH14_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH14_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH14_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH15_EVT_ID: Channel15 event id register
func (o *SOC_ETM_Type) SetCH15_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH15_EVT_ID.Reg, volatile.LoadUint32(&o.CH15_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH15_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH15_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH15_TASK_ID: Channel15 task id register
func (o *SOC_ETM_Type) SetCH15_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH15_TASK_ID.Reg, volatile.LoadUint32(&o.CH15_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH15_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH15_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH16_EVT_ID: Channel16 event id register
func (o *SOC_ETM_Type) SetCH16_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH16_EVT_ID.Reg, volatile.LoadUint32(&o.CH16_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH16_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH16_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH16_TASK_ID: Channel16 task id register
func (o *SOC_ETM_Type) SetCH16_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH16_TASK_ID.Reg, volatile.LoadUint32(&o.CH16_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH16_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH16_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH17_EVT_ID: Channel17 event id register
func (o *SOC_ETM_Type) SetCH17_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH17_EVT_ID.Reg, volatile.LoadUint32(&o.CH17_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH17_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH17_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH17_TASK_ID: Channel17 task id register
func (o *SOC_ETM_Type) SetCH17_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH17_TASK_ID.Reg, volatile.LoadUint32(&o.CH17_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH17_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH17_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH18_EVT_ID: Channel18 event id register
func (o *SOC_ETM_Type) SetCH18_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH18_EVT_ID.Reg, volatile.LoadUint32(&o.CH18_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH18_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH18_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH18_TASK_ID: Channel18 task id register
func (o *SOC_ETM_Type) SetCH18_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH18_TASK_ID.Reg, volatile.LoadUint32(&o.CH18_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH18_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH18_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH19_EVT_ID: Channel19 event id register
func (o *SOC_ETM_Type) SetCH19_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH19_EVT_ID.Reg, volatile.LoadUint32(&o.CH19_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH19_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH19_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH19_TASK_ID: Channel19 task id register
func (o *SOC_ETM_Type) SetCH19_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH19_TASK_ID.Reg, volatile.LoadUint32(&o.CH19_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH19_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH19_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH20_EVT_ID: Channel20 event id register
func (o *SOC_ETM_Type) SetCH20_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH20_EVT_ID.Reg, volatile.LoadUint32(&o.CH20_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH20_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH20_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH20_TASK_ID: Channel20 task id register
func (o *SOC_ETM_Type) SetCH20_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH20_TASK_ID.Reg, volatile.LoadUint32(&o.CH20_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH20_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH20_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH21_EVT_ID: Channel21 event id register
func (o *SOC_ETM_Type) SetCH21_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH21_EVT_ID.Reg, volatile.LoadUint32(&o.CH21_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH21_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH21_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH21_TASK_ID: Channel21 task id register
func (o *SOC_ETM_Type) SetCH21_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH21_TASK_ID.Reg, volatile.LoadUint32(&o.CH21_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH21_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH21_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH22_EVT_ID: Channel22 event id register
func (o *SOC_ETM_Type) SetCH22_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH22_EVT_ID.Reg, volatile.LoadUint32(&o.CH22_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH22_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH22_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH22_TASK_ID: Channel22 task id register
func (o *SOC_ETM_Type) SetCH22_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH22_TASK_ID.Reg, volatile.LoadUint32(&o.CH22_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH22_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH22_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH23_EVT_ID: Channel23 event id register
func (o *SOC_ETM_Type) SetCH23_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH23_EVT_ID.Reg, volatile.LoadUint32(&o.CH23_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH23_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH23_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH23_TASK_ID: Channel23 task id register
func (o *SOC_ETM_Type) SetCH23_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH23_TASK_ID.Reg, volatile.LoadUint32(&o.CH23_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH23_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH23_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH24_EVT_ID: Channel24 event id register
func (o *SOC_ETM_Type) SetCH24_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH24_EVT_ID.Reg, volatile.LoadUint32(&o.CH24_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH24_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH24_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH24_TASK_ID: Channel24 task id register
func (o *SOC_ETM_Type) SetCH24_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH24_TASK_ID.Reg, volatile.LoadUint32(&o.CH24_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH24_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH24_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH25_EVT_ID: Channel25 event id register
func (o *SOC_ETM_Type) SetCH25_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH25_EVT_ID.Reg, volatile.LoadUint32(&o.CH25_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH25_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH25_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH25_TASK_ID: Channel25 task id register
func (o *SOC_ETM_Type) SetCH25_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH25_TASK_ID.Reg, volatile.LoadUint32(&o.CH25_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH25_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH25_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH26_EVT_ID: Channel26 event id register
func (o *SOC_ETM_Type) SetCH26_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH26_EVT_ID.Reg, volatile.LoadUint32(&o.CH26_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH26_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH26_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH26_TASK_ID: Channel26 task id register
func (o *SOC_ETM_Type) SetCH26_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH26_TASK_ID.Reg, volatile.LoadUint32(&o.CH26_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH26_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH26_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH27_EVT_ID: Channel27 event id register
func (o *SOC_ETM_Type) SetCH27_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH27_EVT_ID.Reg, volatile.LoadUint32(&o.CH27_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH27_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH27_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH27_TASK_ID: Channel27 task id register
func (o *SOC_ETM_Type) SetCH27_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH27_TASK_ID.Reg, volatile.LoadUint32(&o.CH27_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH27_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH27_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH28_EVT_ID: Channel28 event id register
func (o *SOC_ETM_Type) SetCH28_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH28_EVT_ID.Reg, volatile.LoadUint32(&o.CH28_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH28_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH28_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH28_TASK_ID: Channel28 task id register
func (o *SOC_ETM_Type) SetCH28_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH28_TASK_ID.Reg, volatile.LoadUint32(&o.CH28_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH28_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH28_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH29_EVT_ID: Channel29 event id register
func (o *SOC_ETM_Type) SetCH29_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH29_EVT_ID.Reg, volatile.LoadUint32(&o.CH29_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH29_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH29_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH29_TASK_ID: Channel29 task id register
func (o *SOC_ETM_Type) SetCH29_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH29_TASK_ID.Reg, volatile.LoadUint32(&o.CH29_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH29_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH29_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH30_EVT_ID: Channel30 event id register
func (o *SOC_ETM_Type) SetCH30_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH30_EVT_ID.Reg, volatile.LoadUint32(&o.CH30_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH30_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH30_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH30_TASK_ID: Channel30 task id register
func (o *SOC_ETM_Type) SetCH30_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH30_TASK_ID.Reg, volatile.LoadUint32(&o.CH30_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH30_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH30_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH31_EVT_ID: Channel31 event id register
func (o *SOC_ETM_Type) SetCH31_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH31_EVT_ID.Reg, volatile.LoadUint32(&o.CH31_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH31_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH31_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH31_TASK_ID: Channel31 task id register
func (o *SOC_ETM_Type) SetCH31_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH31_TASK_ID.Reg, volatile.LoadUint32(&o.CH31_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH31_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH31_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH32_EVT_ID: Channel32 event id register
func (o *SOC_ETM_Type) SetCH32_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH32_EVT_ID.Reg, volatile.LoadUint32(&o.CH32_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH32_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH32_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH32_TASK_ID: Channel32 task id register
func (o *SOC_ETM_Type) SetCH32_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH32_TASK_ID.Reg, volatile.LoadUint32(&o.CH32_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH32_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH32_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH33_EVT_ID: Channel33 event id register
func (o *SOC_ETM_Type) SetCH33_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH33_EVT_ID.Reg, volatile.LoadUint32(&o.CH33_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH33_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH33_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH33_TASK_ID: Channel33 task id register
func (o *SOC_ETM_Type) SetCH33_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH33_TASK_ID.Reg, volatile.LoadUint32(&o.CH33_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH33_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH33_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH34_EVT_ID: Channel34 event id register
func (o *SOC_ETM_Type) SetCH34_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH34_EVT_ID.Reg, volatile.LoadUint32(&o.CH34_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH34_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH34_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH34_TASK_ID: Channel34 task id register
func (o *SOC_ETM_Type) SetCH34_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH34_TASK_ID.Reg, volatile.LoadUint32(&o.CH34_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH34_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH34_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH35_EVT_ID: Channel35 event id register
func (o *SOC_ETM_Type) SetCH35_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH35_EVT_ID.Reg, volatile.LoadUint32(&o.CH35_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH35_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH35_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH35_TASK_ID: Channel35 task id register
func (o *SOC_ETM_Type) SetCH35_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH35_TASK_ID.Reg, volatile.LoadUint32(&o.CH35_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH35_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH35_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH36_EVT_ID: Channel36 event id register
func (o *SOC_ETM_Type) SetCH36_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH36_EVT_ID.Reg, volatile.LoadUint32(&o.CH36_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH36_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH36_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH36_TASK_ID: Channel36 task id register
func (o *SOC_ETM_Type) SetCH36_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH36_TASK_ID.Reg, volatile.LoadUint32(&o.CH36_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH36_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH36_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH37_EVT_ID: Channel37 event id register
func (o *SOC_ETM_Type) SetCH37_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH37_EVT_ID.Reg, volatile.LoadUint32(&o.CH37_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH37_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH37_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH37_TASK_ID: Channel37 task id register
func (o *SOC_ETM_Type) SetCH37_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH37_TASK_ID.Reg, volatile.LoadUint32(&o.CH37_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH37_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH37_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH38_EVT_ID: Channel38 event id register
func (o *SOC_ETM_Type) SetCH38_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH38_EVT_ID.Reg, volatile.LoadUint32(&o.CH38_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH38_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH38_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH38_TASK_ID: Channel38 task id register
func (o *SOC_ETM_Type) SetCH38_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH38_TASK_ID.Reg, volatile.LoadUint32(&o.CH38_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH38_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH38_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH39_EVT_ID: Channel39 event id register
func (o *SOC_ETM_Type) SetCH39_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH39_EVT_ID.Reg, volatile.LoadUint32(&o.CH39_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH39_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH39_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH39_TASK_ID: Channel39 task id register
func (o *SOC_ETM_Type) SetCH39_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH39_TASK_ID.Reg, volatile.LoadUint32(&o.CH39_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH39_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH39_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH40_EVT_ID: Channel40 event id register
func (o *SOC_ETM_Type) SetCH40_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH40_EVT_ID.Reg, volatile.LoadUint32(&o.CH40_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH40_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH40_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH40_TASK_ID: Channel40 task id register
func (o *SOC_ETM_Type) SetCH40_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH40_TASK_ID.Reg, volatile.LoadUint32(&o.CH40_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH40_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH40_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH41_EVT_ID: Channel41 event id register
func (o *SOC_ETM_Type) SetCH41_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH41_EVT_ID.Reg, volatile.LoadUint32(&o.CH41_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH41_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH41_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH41_TASK_ID: Channel41 task id register
func (o *SOC_ETM_Type) SetCH41_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH41_TASK_ID.Reg, volatile.LoadUint32(&o.CH41_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH41_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH41_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH42_EVT_ID: Channel42 event id register
func (o *SOC_ETM_Type) SetCH42_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH42_EVT_ID.Reg, volatile.LoadUint32(&o.CH42_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH42_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH42_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH42_TASK_ID: Channel42 task id register
func (o *SOC_ETM_Type) SetCH42_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH42_TASK_ID.Reg, volatile.LoadUint32(&o.CH42_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH42_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH42_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH43_EVT_ID: Channel43 event id register
func (o *SOC_ETM_Type) SetCH43_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH43_EVT_ID.Reg, volatile.LoadUint32(&o.CH43_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH43_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH43_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH43_TASK_ID: Channel43 task id register
func (o *SOC_ETM_Type) SetCH43_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH43_TASK_ID.Reg, volatile.LoadUint32(&o.CH43_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH43_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH43_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH44_EVT_ID: Channel44 event id register
func (o *SOC_ETM_Type) SetCH44_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH44_EVT_ID.Reg, volatile.LoadUint32(&o.CH44_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH44_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH44_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH44_TASK_ID: Channel44 task id register
func (o *SOC_ETM_Type) SetCH44_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH44_TASK_ID.Reg, volatile.LoadUint32(&o.CH44_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH44_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH44_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH45_EVT_ID: Channel45 event id register
func (o *SOC_ETM_Type) SetCH45_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH45_EVT_ID.Reg, volatile.LoadUint32(&o.CH45_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH45_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH45_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH45_TASK_ID: Channel45 task id register
func (o *SOC_ETM_Type) SetCH45_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH45_TASK_ID.Reg, volatile.LoadUint32(&o.CH45_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH45_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH45_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH46_EVT_ID: Channel46 event id register
func (o *SOC_ETM_Type) SetCH46_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH46_EVT_ID.Reg, volatile.LoadUint32(&o.CH46_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH46_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH46_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH46_TASK_ID: Channel46 task id register
func (o *SOC_ETM_Type) SetCH46_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH46_TASK_ID.Reg, volatile.LoadUint32(&o.CH46_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH46_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH46_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH47_EVT_ID: Channel47 event id register
func (o *SOC_ETM_Type) SetCH47_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH47_EVT_ID.Reg, volatile.LoadUint32(&o.CH47_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH47_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH47_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH47_TASK_ID: Channel47 task id register
func (o *SOC_ETM_Type) SetCH47_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH47_TASK_ID.Reg, volatile.LoadUint32(&o.CH47_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH47_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH47_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH48_EVT_ID: Channel48 event id register
func (o *SOC_ETM_Type) SetCH48_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH48_EVT_ID.Reg, volatile.LoadUint32(&o.CH48_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH48_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH48_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH48_TASK_ID: Channel48 task id register
func (o *SOC_ETM_Type) SetCH48_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH48_TASK_ID.Reg, volatile.LoadUint32(&o.CH48_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH48_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH48_TASK_ID.Reg) & 0xff
}

// SOC_ETM.CH49_EVT_ID: Channel49 event id register
func (o *SOC_ETM_Type) SetCH49_EVT_ID(value uint32) {
	volatile.StoreUint32(&o.CH49_EVT_ID.Reg, volatile.LoadUint32(&o.CH49_EVT_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH49_EVT_ID() uint32 {
	return volatile.LoadUint32(&o.CH49_EVT_ID.Reg) & 0xff
}

// SOC_ETM.CH49_TASK_ID: Channel49 task id register
func (o *SOC_ETM_Type) SetCH49_TASK_ID(value uint32) {
	volatile.StoreUint32(&o.CH49_TASK_ID.Reg, volatile.LoadUint32(&o.CH49_TASK_ID.Reg)&^(0xff)|value)
}
func (o *SOC_ETM_Type) GetCH49_TASK_ID() uint32 {
	return volatile.LoadUint32(&o.CH49_TASK_ID.Reg) & 0xff
}

// SOC_ETM.EVT_ST0: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH0_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH0_RISE_EDGE_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH1_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH1_RISE_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH2_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH2_RISE_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH3_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH3_RISE_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH4_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH4_RISE_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH5_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH5_RISE_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH6_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH6_RISE_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH7_RISE_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH7_RISE_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH0_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH0_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH1_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH1_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH2_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH2_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH3_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH3_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH4_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH4_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH5_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH5_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH6_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH6_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH7_FALL_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH7_FALL_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH0_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH0_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH1_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH1_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH2_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH2_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH3_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH3_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH4_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH4_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH5_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH5_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH6_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH6_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_CH7_ANY_EDGE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_CH7_ANY_EDGE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_POS0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_POS0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_NEG0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_NEG0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_POS1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_POS1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST0_GPIO_EVT_ZERO_DET_NEG1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST0_GPIO_EVT_ZERO_DET_NEG1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0.Reg, volatile.LoadUint32(&o.EVT_ST0.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST0_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH0_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH0_RISE_EDGE_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH1_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH1_RISE_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH2_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH2_RISE_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH3_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH3_RISE_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH4_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH4_RISE_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH5_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH5_RISE_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH6_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH6_RISE_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH7_RISE_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH7_RISE_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH0_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH0_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH1_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH1_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH2_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH2_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH3_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH3_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH4_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH4_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH5_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH5_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH6_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH6_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH7_FALL_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH7_FALL_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH0_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH0_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH1_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH1_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH2_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH2_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH3_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH3_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH4_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH4_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH5_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH5_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH6_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH6_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_CH7_ANY_EDGE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_CH7_ANY_EDGE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST0_CLR.Reg, volatile.LoadUint32(&o.EVT_ST0_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST0_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST1: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH4_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH4_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER3_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIME_OVF_TIMER3_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER0_CMP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER0_CMP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER1_CMP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER1_CMP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER2_CMP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER2_CMP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST1_LEDC_EVT_TIMER3_CMP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST1_LEDC_EVT_TIMER3_CMP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST1_TG0_EVT_CNT_CMP_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST1_TG0_EVT_CNT_CMP_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST1_TG0_EVT_CNT_CMP_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST1_TG0_EVT_CNT_CMP_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST1_TG1_EVT_CNT_CMP_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST1_TG1_EVT_CNT_CMP_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST1_TG1_EVT_CNT_CMP_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST1_TG1_EVT_CNT_CMP_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST1_SYSTIMER_EVT_CNT_CMP0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST1_SYSTIMER_EVT_CNT_CMP0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST1_SYSTIMER_EVT_CNT_CMP1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST1_SYSTIMER_EVT_CNT_CMP1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST1_SYSTIMER_EVT_CNT_CMP2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST1_SYSTIMER_EVT_CNT_CMP2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER0_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER0_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER1_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER1_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER2_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER2_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER0_TEZ_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER0_TEZ_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST1_MCPWM0_EVT_TIMER1_TEZ_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1.Reg, volatile.LoadUint32(&o.EVT_ST1.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST1_MCPWM0_EVT_TIMER1_TEZ_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST1_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER0_CMP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER0_CMP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER1_CMP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER1_CMP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER2_CMP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER2_CMP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_LEDC_EVT_TIMER3_CMP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_LEDC_EVT_TIMER3_CMP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER2_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER2_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_TEZ_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER0_TEZ_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_TEZ_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST1_CLR.Reg, volatile.LoadUint32(&o.EVT_ST1_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST1_CLR_MCPWM0_EVT_TIMER1_TEZ_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST1_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST2: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER2_TEZ_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER2_TEZ_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER0_TEP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER0_TEP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER1_TEP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER1_TEP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TIMER2_TEP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TIMER2_TEP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEA_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEA_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEA_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEA_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEA_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEA_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEB_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEB_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEB_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEB_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEB_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEB_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F0_CLR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F0_CLR_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F1_CLR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F1_CLR_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_F2_CLR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_F2_CLR_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ0_CBC_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ0_CBC_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ1_CBC_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ1_CBC_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ2_CBC_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ2_CBC_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ0_OST_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ0_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ1_OST_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ1_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_TZ2_OST_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_TZ2_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_CAP0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_CAP0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_CAP1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_CAP1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_CAP2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_CAP2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEE1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEE1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEE1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEE1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEE1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEE1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP0_TEE2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP0_TEE2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP1_TEE2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP1_TEE2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM0_EVT_OP2_TEE2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM0_EVT_OP2_TEE2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST2_MCPWM1_EVT_TIMER0_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2.Reg, volatile.LoadUint32(&o.EVT_ST2.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST2_MCPWM1_EVT_TIMER0_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST2_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEZ_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEZ_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER0_TEP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER0_TEP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER1_TEP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER1_TEP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEA_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEA_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEA_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEA_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEA_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEA_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEB_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEB_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEB_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEB_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEB_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEB_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F0_CLR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F0_CLR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F1_CLR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F1_CLR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_F2_CLR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_F2_CLR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ0_CBC_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ0_CBC_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ1_CBC_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ1_CBC_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ2_CBC_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ2_CBC_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ0_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ0_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ1_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ1_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_TZ2_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_TZ2_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_CAP0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_CAP0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_CAP1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_CAP1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_CAP2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_CAP2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP0_TEE2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP1_TEE2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM0_EVT_OP2_TEE2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST2_CLR_MCPWM1_EVT_TIMER0_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST2_CLR.Reg, volatile.LoadUint32(&o.EVT_ST2_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST2_CLR_MCPWM1_EVT_TIMER0_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST2_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST3: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER1_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER1_STOP_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER2_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER2_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER0_TEZ_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER0_TEZ_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER1_TEZ_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER1_TEZ_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER2_TEZ_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER2_TEZ_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER0_TEP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER0_TEP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER1_TEP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER1_TEP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TIMER2_TEP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TIMER2_TEP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP0_TEA_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP0_TEA_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP1_TEA_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP1_TEA_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP2_TEA_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP2_TEA_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP0_TEB_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP0_TEB_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP1_TEB_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP1_TEB_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP2_TEB_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP2_TEB_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F0_CLR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F0_CLR_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F1_CLR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F1_CLR_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_F2_CLR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_F2_CLR_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ0_CBC_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ0_CBC_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ1_CBC_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ1_CBC_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ2_CBC_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ2_CBC_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ0_OST_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ0_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ1_OST_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ1_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_TZ2_OST_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_TZ2_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_CAP0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_CAP0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_CAP1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_CAP1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_CAP2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_CAP2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP0_TEE1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP0_TEE1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP1_TEE1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP1_TEE1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST3_MCPWM1_EVT_OP2_TEE1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3.Reg, volatile.LoadUint32(&o.EVT_ST3.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST3_MCPWM1_EVT_OP2_TEE1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST3_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_STOP_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEZ_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEZ_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEZ_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEZ_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEZ_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEZ_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEA_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEA_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEA_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEA_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEA_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEA_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEB_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEB_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEB_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEB_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEB_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEB_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F0_CLR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F0_CLR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F1_CLR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F1_CLR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_F2_CLR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_F2_CLR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ0_CBC_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ0_CBC_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ1_CBC_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ1_CBC_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ2_CBC_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ2_CBC_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ0_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ0_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ1_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ1_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_TZ2_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_TZ2_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_CAP0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_CAP0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_CAP1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_CAP1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_CAP2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_CAP2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP0_TEE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP1_TEE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST3_CLR.Reg, volatile.LoadUint32(&o.EVT_ST3_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST3_CLR_MCPWM1_EVT_OP2_TEE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST3_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST4: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST4_MCPWM1_EVT_OP0_TEE2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST4_MCPWM1_EVT_OP0_TEE2_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST4_MCPWM1_EVT_OP1_TEE2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST4_MCPWM1_EVT_OP1_TEE2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST4_MCPWM1_EVT_OP2_TEE2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST4_MCPWM1_EVT_OP2_TEE2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_CONV_CMPLT0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_CONV_CMPLT0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_ABOVE_THRESH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_EQ_BELOW_THRESH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_RESULT_DONE0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_RESULT_DONE0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_STOPPED0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_STOPPED0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST4_ADC_EVT_STARTED0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST4_ADC_EVT_STARTED0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_DONE3_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_DONE3_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST4_REGDMA_EVT_ERR3_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST4_REGDMA_EVT_ERR3_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST4_TMPSNSR_EVT_OVER_LIMIT_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST4_TMPSNSR_EVT_OVER_LIMIT_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_RX_DONE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_RX_DONE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_TX_DONE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_TX_DONE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_X_WORDS_RECEIVED_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_X_WORDS_RECEIVED_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S0_EVT_X_WORDS_SENT_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S0_EVT_X_WORDS_SENT_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_RX_DONE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_RX_DONE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_TX_DONE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_TX_DONE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_X_WORDS_RECEIVED_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_X_WORDS_RECEIVED_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S1_EVT_X_WORDS_SENT_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S1_EVT_X_WORDS_SENT_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_RX_DONE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_RX_DONE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_TX_DONE_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_TX_DONE_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_X_WORDS_RECEIVED_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_X_WORDS_RECEIVED_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST4_I2S2_EVT_X_WORDS_SENT_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4.Reg, volatile.LoadUint32(&o.EVT_ST4.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST4_I2S2_EVT_X_WORDS_SENT_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST4_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_MCPWM1_EVT_OP0_TEE2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_MCPWM1_EVT_OP0_TEE2_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_MCPWM1_EVT_OP1_TEE2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_MCPWM1_EVT_OP1_TEE2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_MCPWM1_EVT_OP2_TEE2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_MCPWM1_EVT_OP2_TEE2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_CONV_CMPLT0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_CONV_CMPLT0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_RESULT_DONE0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_RESULT_DONE0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_STOPPED0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_STOPPED0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_ADC_EVT_STARTED0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_ADC_EVT_STARTED0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_DONE3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_DONE3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_REGDMA_EVT_ERR3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_REGDMA_EVT_ERR3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_TMPSNSR_EVT_OVER_LIMIT_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_TMPSNSR_EVT_OVER_LIMIT_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_RX_DONE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_RX_DONE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_TX_DONE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_TX_DONE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S0_EVT_X_WORDS_SENT_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S0_EVT_X_WORDS_SENT_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_RX_DONE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_RX_DONE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_TX_DONE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_TX_DONE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S1_EVT_X_WORDS_SENT_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S1_EVT_X_WORDS_SENT_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_RX_DONE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_RX_DONE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_TX_DONE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_TX_DONE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST4_CLR_I2S2_EVT_X_WORDS_SENT_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST4_CLR.Reg, volatile.LoadUint32(&o.EVT_ST4_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST4_CLR_I2S2_EVT_X_WORDS_SENT_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST4_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST5: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST5_ULP_EVT_ERR_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST5_ULP_EVT_ERR_INTR_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST5_ULP_EVT_HALT_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST5_ULP_EVT_HALT_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST5_ULP_EVT_START_INTR_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST5_ULP_EVT_START_INTR_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST5_RTC_EVT_TICK_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST5_RTC_EVT_TICK_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST5_RTC_EVT_OVF_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST5_RTC_EVT_OVF_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST5_RTC_EVT_CMP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST5_RTC_EVT_CMP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_DONE_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5.Reg, volatile.LoadUint32(&o.EVT_ST5.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST5_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_ULP_EVT_ERR_INTR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_ULP_EVT_ERR_INTR_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_ULP_EVT_HALT_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_ULP_EVT_HALT_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_ULP_EVT_START_INTR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_ULP_EVT_START_INTR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_RTC_EVT_TICK_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_RTC_EVT_TICK_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_RTC_EVT_OVF_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_RTC_EVT_OVF_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_RTC_EVT_CMP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_RTC_EVT_CMP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST5_CLR.Reg, volatile.LoadUint32(&o.EVT_ST5_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST5_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST6: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_DONE_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST6_PMU_EVT_SLEEP_WEEKUP_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST6_PMU_EVT_SLEEP_WEEKUP_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST6_DMA2D_EVT_IN_DONE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST6_DMA2D_EVT_IN_DONE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST6_DMA2D_EVT_IN_DONE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST6_DMA2D_EVT_IN_DONE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST6_DMA2D_EVT_IN_SUC_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6.Reg, volatile.LoadUint32(&o.EVT_ST6.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST6_DMA2D_EVT_IN_SUC_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST6_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_PMU_EVT_SLEEP_WEEKUP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_PMU_EVT_SLEEP_WEEKUP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetEVT_ST6_CLR_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST6_CLR.Reg, volatile.LoadUint32(&o.EVT_ST6_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetEVT_ST6_CLR_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST6_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.EVT_ST7: Events trigger status register
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_IN_SUC_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_IN_SUC_EOF_CH1_ST() uint32 {
	return volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_DONE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_DONE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_DONE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_DONE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_DONE_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_DONE_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7.Reg, volatile.LoadUint32(&o.EVT_ST7.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7.Reg) & 0x200) >> 9
}

// SOC_ETM.EVT_ST7_CLR: Events trigger status clear register
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.EVT_ST7_CLR.Reg, volatile.LoadUint32(&o.EVT_ST7_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetEVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.EVT_ST7_CLR.Reg) & 0x200) >> 9
}

// SOC_ETM.TASK_ST0: Tasks trigger status register
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH0_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH0_SET_ST() uint32 {
	return volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH1_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH1_SET_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH2_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH2_SET_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH3_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH3_SET_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH4_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH4_SET_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH5_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH5_SET_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH6_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH6_SET_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH7_SET_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH7_SET_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH0_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH0_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH1_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH1_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH2_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH2_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH3_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH3_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH4_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH4_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH5_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH5_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH6_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH6_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH7_CLEAR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH7_CLEAR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH0_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH0_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH1_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH1_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH2_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH2_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH3_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH3_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH4_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH4_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH5_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH5_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH6_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH6_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST0_GPIO_TASK_CH7_TOGGLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST0_GPIO_TASK_CH7_TOGGLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER0_RES_UPDATE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER0_RES_UPDATE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER1_RES_UPDATE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER1_RES_UPDATE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER2_RES_UPDATE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER2_RES_UPDATE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_TIMER3_RES_UPDATE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_TIMER3_RES_UPDATE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0.Reg, volatile.LoadUint32(&o.TASK_ST0.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST0_CLR: Tasks trigger status clear register
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH0_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH0_SET_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH1_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH1_SET_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH2_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH2_SET_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH3_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH3_SET_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH4_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH4_SET_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH5_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH5_SET_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH6_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH6_SET_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH7_SET_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH7_SET_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH0_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH0_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH1_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH1_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH2_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH2_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH3_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH3_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH4_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH4_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH5_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH5_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH6_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH6_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH7_CLEAR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH7_CLEAR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH0_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH0_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH1_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH1_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH2_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH2_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH3_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH3_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH4_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH4_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH5_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH5_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH6_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH6_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_GPIO_TASK_CH7_TOGGLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_GPIO_TASK_CH7_TOGGLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST0_CLR.Reg, volatile.LoadUint32(&o.TASK_ST0_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST0_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST1: Tasks trigger status register
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST() uint32 {
	return volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER0_CAP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER0_CAP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER1_CAP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER1_CAP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER2_CAP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER2_CAP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER3_CAP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER3_CAP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH4_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH4_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_OVF_CNT_RST_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER0_RST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER0_RST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER1_RST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER1_RST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER2_RST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER2_RST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER3_RST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER3_RST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER0_RESUME_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER0_RESUME_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER1_RESUME_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER1_RESUME_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER2_RESUME_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER2_RESUME_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST1_LEDC_TASK_TIMER3_RESUME_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1.Reg, volatile.LoadUint32(&o.TASK_ST1.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST1_LEDC_TASK_TIMER3_RESUME_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST1_CLR: Tasks trigger status clear register
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER0_CAP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER0_CAP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER1_CAP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER1_CAP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER2_CAP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER2_CAP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER3_CAP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER3_CAP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER0_RST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER0_RST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER1_RST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER1_RST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER2_RST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER2_RST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER3_RST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER3_RST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER0_RESUME_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER0_RESUME_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER1_RESUME_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER1_RESUME_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER2_RESUME_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER2_RESUME_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST1_CLR_LEDC_TASK_TIMER3_RESUME_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST1_CLR.Reg, volatile.LoadUint32(&o.TASK_ST1_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST1_CLR_LEDC_TASK_TIMER3_RESUME_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST1_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST2: Tasks trigger status register
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER0_PAUSE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER0_PAUSE_ST() uint32 {
	return volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER1_PAUSE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER1_PAUSE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER2_PAUSE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER2_PAUSE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_TIMER3_PAUSE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_TIMER3_PAUSE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH4_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESTART_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH4_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH3_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH3_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH4_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH4_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH5_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH5_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH6_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH6_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH7_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST2_LEDC_TASK_GAMMA_RESUME_CH7_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_CNT_START_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_CNT_START_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_ALARM_START_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_ALARM_START_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_CNT_STOP_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_CNT_STOP_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST2_TG0_TASK_CNT_RELOAD_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2.Reg, volatile.LoadUint32(&o.TASK_ST2.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST2_TG0_TASK_CNT_RELOAD_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST2_CLR: Tasks trigger status clear register
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER0_PAUSE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER0_PAUSE_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER1_PAUSE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER1_PAUSE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER2_PAUSE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER2_PAUSE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_TIMER3_PAUSE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_TIMER3_PAUSE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_CNT_START_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_CNT_START_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_ALARM_START_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_ALARM_START_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_CNT_STOP_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_CNT_STOP_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST2_CLR_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST2_CLR.Reg, volatile.LoadUint32(&o.TASK_ST2_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST2_CLR_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST2_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST3: Tasks trigger status register
func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_CAP_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_CAP_TIMER0_ST() uint32 {
	return volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_START_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_START_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_ALARM_START_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_ALARM_START_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_STOP_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_STOP_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_RELOAD_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_RELOAD_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG0_TASK_CNT_CAP_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG0_TASK_CNT_CAP_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_START_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_START_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_ALARM_START_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_ALARM_START_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_STOP_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_STOP_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_CAP_TIMER0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_CAP_TIMER0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_START_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_START_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_ALARM_START_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_ALARM_START_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_STOP_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_STOP_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_RELOAD_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST3_TG1_TASK_CNT_CAP_TIMER1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST3_TG1_TASK_CNT_CAP_TIMER1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR0_A_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR0_A_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR1_A_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR1_A_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR2_A_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR2_A_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR0_B_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR0_B_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR1_B_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR1_B_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_CMPR2_B_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_CMPR2_B_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_GEN_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_GEN_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER0_SYN_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER0_SYN_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER1_SYN_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER1_SYN_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER2_SYN_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER2_SYN_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER0_PERIOD_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER0_PERIOD_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER1_PERIOD_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER1_PERIOD_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TIMER2_PERIOD_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TIMER2_PERIOD_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TZ0_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TZ0_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TZ1_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TZ1_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST3_MCPWM0_TASK_TZ2_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3.Reg, volatile.LoadUint32(&o.TASK_ST3.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST3_MCPWM0_TASK_TZ2_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST3_CLR: Tasks trigger status clear register
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER0_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_START_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_START_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_ALARM_START_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_ALARM_START_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_STOP_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_STOP_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_START_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_A_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_A_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_A_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_A_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_A_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_A_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_B_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR0_B_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_B_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR1_B_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_B_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_CMPR2_B_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_GEN_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_GEN_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_SYN_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_SYN_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_SYN_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_SYN_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_SYN_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_SYN_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TZ0_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TZ0_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TZ1_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TZ1_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST3_CLR_MCPWM0_TASK_TZ2_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST3_CLR.Reg, volatile.LoadUint32(&o.TASK_ST3_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST3_CLR_MCPWM0_TASK_TZ2_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST3_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST4: Tasks trigger status register
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CLR0_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CLR0_OST_ST() uint32 {
	return volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CLR1_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CLR1_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CLR2_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CLR2_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CAP0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CAP0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CAP1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CAP1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM0_TASK_CAP2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM0_TASK_CAP2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR0_A_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR0_A_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR1_A_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR1_A_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR2_A_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR2_A_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR0_B_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR0_B_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR1_B_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR1_B_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CMPR2_B_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CMPR2_B_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_GEN_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_GEN_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER0_SYN_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER0_SYN_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER1_SYN_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER1_SYN_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER2_SYN_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER2_SYN_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER0_PERIOD_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER0_PERIOD_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER1_PERIOD_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER1_PERIOD_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TIMER2_PERIOD_UP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TIMER2_PERIOD_UP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TZ0_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TZ0_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TZ1_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TZ1_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_TZ2_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_TZ2_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CLR0_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CLR0_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CLR1_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CLR1_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CLR2_OST_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CLR2_OST_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CAP0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CAP0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CAP1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CAP1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST4_MCPWM1_TASK_CAP2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST4_MCPWM1_TASK_CAP2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_SAMPLE0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_SAMPLE0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_SAMPLE1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_SAMPLE1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_START0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_START0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST4_ADC_TASK_STOP0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4.Reg, volatile.LoadUint32(&o.TASK_ST4.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST4_ADC_TASK_STOP0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST4_CLR: Tasks trigger status clear register
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CLR0_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CLR0_OST_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CLR1_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CLR1_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CLR2_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CLR2_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CAP0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CAP0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CAP1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CAP1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM0_TASK_CAP2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM0_TASK_CAP2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_A_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_A_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_A_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_A_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_A_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_A_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_B_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR0_B_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_B_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR1_B_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_B_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CMPR2_B_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_GEN_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_GEN_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_SYN_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_SYN_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_SYN_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_SYN_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_SYN_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_SYN_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TZ0_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TZ0_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TZ1_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TZ1_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_TZ2_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_TZ2_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CLR0_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CLR0_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CLR1_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CLR1_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CLR2_OST_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CLR2_OST_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CAP0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CAP0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CAP1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CAP1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_MCPWM1_TASK_CAP2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_MCPWM1_TASK_CAP2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_SAMPLE0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_SAMPLE0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_SAMPLE1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_SAMPLE1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_START0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_START0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST4_CLR_ADC_TASK_STOP0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST4_CLR.Reg, volatile.LoadUint32(&o.TASK_ST4_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST4_CLR_ADC_TASK_STOP0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST4_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST5: Tasks trigger status register
func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START0_ST() uint32 {
	return volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST5_REGDMA_TASK_START3_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST5_REGDMA_TASK_START3_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST5_TMPSNSR_TASK_START_SAMPLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST5_TMPSNSR_TASK_START_SAMPLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST5_TMPSNSR_TASK_STOP_SAMPLE_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST5_TMPSNSR_TASK_STOP_SAMPLE_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_START_RX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_START_RX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_START_TX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_START_TX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_STOP_RX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_STOP_RX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S0_TASK_STOP_TX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S0_TASK_STOP_TX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_START_RX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_START_RX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_START_TX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_START_TX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_STOP_RX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_STOP_RX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S1_TASK_STOP_TX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S1_TASK_STOP_TX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_START_RX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_START_RX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_START_TX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_START_TX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_STOP_RX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_STOP_RX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST5_I2S2_TASK_STOP_TX_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST5_I2S2_TASK_STOP_TX_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST5_ULP_TASK_WAKEUP_CPU_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST5_ULP_TASK_WAKEUP_CPU_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST5_ULP_TASK_INT_CPU_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST5_ULP_TASK_INT_CPU_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_START_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_START_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_STOP_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_STOP_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_CLR_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_CLR_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST5_RTC_TASK_TRIGGERFLW_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST5_RTC_TASK_TRIGGERFLW_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_IN_START_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_IN_START_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_IN_START_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_IN_START_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_IN_START_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_IN_START_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AHB_TASK_OUT_START_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AXI_TASK_IN_START_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AXI_TASK_IN_START_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST5_PDMA_AXI_TASK_IN_START_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5.Reg, volatile.LoadUint32(&o.TASK_ST5.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST5_PDMA_AXI_TASK_IN_START_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST5_CLR: Tasks trigger status clear register
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START0_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_REGDMA_TASK_START3_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_REGDMA_TASK_START3_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_TMPSNSR_TASK_START_SAMPLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_TMPSNSR_TASK_START_SAMPLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_START_RX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_START_RX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_START_TX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_START_TX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_STOP_RX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_STOP_RX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S0_TASK_STOP_TX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S0_TASK_STOP_TX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_START_RX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_START_RX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_START_TX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_START_TX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_STOP_RX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_STOP_RX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S1_TASK_STOP_TX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S1_TASK_STOP_TX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_START_RX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_START_RX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x4000) >> 14
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_START_TX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_START_TX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x8000) >> 15
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_STOP_RX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_STOP_RX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x10000) >> 16
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_I2S2_TASK_STOP_TX_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_I2S2_TASK_STOP_TX_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x20000) >> 17
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_ULP_TASK_WAKEUP_CPU_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_ULP_TASK_WAKEUP_CPU_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x40000) >> 18
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_ULP_TASK_INT_CPU_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_ULP_TASK_INT_CPU_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x80000) >> 19
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_START_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_START_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x100000) >> 20
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_STOP_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x200000)|value<<21)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_STOP_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x200000) >> 21
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_CLR_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x400000)|value<<22)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_CLR_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x400000) >> 22
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_RTC_TASK_TRIGGERFLW_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x800000)|value<<23)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_RTC_TASK_TRIGGERFLW_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x800000) >> 23
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x1000000)|value<<24)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x1000000) >> 24
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x2000000)|value<<25)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x2000000) >> 25
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x4000000)|value<<26)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x4000000) >> 26
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x8000000)|value<<27)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x8000000) >> 27
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x10000000) >> 28
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x20000000) >> 29
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x40000000) >> 30
}
func (o *SOC_ETM_Type) SetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST5_CLR.Reg, volatile.LoadUint32(&o.TASK_ST5_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SOC_ETM_Type) GetTASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST5_CLR.Reg) & 0x80000000) >> 31
}

// SOC_ETM.TASK_ST6: Tasks trigger status register
func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_IN_START_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_IN_START_CH2_ST() uint32 {
	return volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST6_PDMA_AXI_TASK_OUT_START_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST6_PMU_TASK_SLEEP_REQ_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST6_PMU_TASK_SLEEP_REQ_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_START_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_START_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_START_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_START_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_START_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_START_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_START_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_START_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_START_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_START_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH0_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH0_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH1_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH1_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH2_ST(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6.Reg, volatile.LoadUint32(&o.TASK_ST6.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH2_ST() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6.Reg) & 0x4000) >> 14
}

// SOC_ETM.TASK_ST6_CLR: Tasks trigger status clear register
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_IN_START_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_IN_START_CH2_ST_CLR() uint32 {
	return volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x1
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x2) >> 1
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x4) >> 2
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x8) >> 3
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_PMU_TASK_SLEEP_REQ_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_PMU_TASK_SLEEP_REQ_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x10) >> 4
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x20) >> 5
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_START_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x40) >> 6
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x80) >> 7
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x100) >> 8
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x200) >> 9
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x400) >> 10
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_START_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x800) >> 11
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x1000) >> 12
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x2000) >> 13
}
func (o *SOC_ETM_Type) SetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR(value uint32) {
	volatile.StoreUint32(&o.TASK_ST6_CLR.Reg, volatile.LoadUint32(&o.TASK_ST6_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SOC_ETM_Type) GetTASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR() uint32 {
	return (volatile.LoadUint32(&o.TASK_ST6_CLR.Reg) & 0x4000) >> 14
}

// SOC_ETM.CLK_EN: ETM clock enable register
func (o *SOC_ETM_Type) SetCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_EN.Reg, volatile.LoadUint32(&o.CLK_EN.Reg)&^(0x1)|value)
}
func (o *SOC_ETM_Type) GetCLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_EN.Reg) & 0x1
}

// SOC_ETM.DATE: ETM date register
func (o *SOC_ETM_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *SOC_ETM_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// SPI (Serial Peripheral Interface) Controller 0
type SPI0_Type struct {
	SPI_MEM_CMD                  volatile.Register32 // 0x0
	_                            [4]byte
	SPI_MEM_CTRL                 volatile.Register32 // 0x8
	SPI_MEM_CTRL1                volatile.Register32 // 0xC
	SPI_MEM_CTRL2                volatile.Register32 // 0x10
	SPI_MEM_CLOCK                volatile.Register32 // 0x14
	SPI_MEM_USER                 volatile.Register32 // 0x18
	SPI_MEM_USER1                volatile.Register32 // 0x1C
	SPI_MEM_USER2                volatile.Register32 // 0x20
	_                            [8]byte
	SPI_MEM_RD_STATUS            volatile.Register32 // 0x2C
	_                            [4]byte
	SPI_MEM_MISC                 volatile.Register32 // 0x34
	_                            [4]byte
	SPI_MEM_CACHE_FCTRL          volatile.Register32 // 0x3C
	SPI_MEM_CACHE_SCTRL          volatile.Register32 // 0x40
	SPI_MEM_SRAM_CMD             volatile.Register32 // 0x44
	SPI_MEM_SRAM_DRD_CMD         volatile.Register32 // 0x48
	SPI_MEM_SRAM_DWR_CMD         volatile.Register32 // 0x4C
	SPI_MEM_SRAM_CLK             volatile.Register32 // 0x50
	SPI_MEM_FSM                  volatile.Register32 // 0x54
	_                            [104]byte
	SPI_MEM_INT_ENA              volatile.Register32 // 0xC0
	SPI_MEM_INT_CLR              volatile.Register32 // 0xC4
	SPI_MEM_INT_RAW              volatile.Register32 // 0xC8
	SPI_MEM_INT_ST               volatile.Register32 // 0xCC
	_                            [4]byte
	SPI_MEM_DDR                  volatile.Register32 // 0xD4
	SPI_SMEM_DDR                 volatile.Register32 // 0xD8
	_                            [36]byte
	SPI_FMEM_PMS0_ATTR           volatile.Register32 // 0x100
	SPI_FMEM_PMS1_ATTR           volatile.Register32 // 0x104
	SPI_FMEM_PMS2_ATTR           volatile.Register32 // 0x108
	SPI_FMEM_PMS3_ATTR           volatile.Register32 // 0x10C
	SPI_FMEM_PMS0_ADDR           volatile.Register32 // 0x110
	SPI_FMEM_PMS1_ADDR           volatile.Register32 // 0x114
	SPI_FMEM_PMS2_ADDR           volatile.Register32 // 0x118
	SPI_FMEM_PMS3_ADDR           volatile.Register32 // 0x11C
	SPI_FMEM_PMS0_SIZE           volatile.Register32 // 0x120
	SPI_FMEM_PMS1_SIZE           volatile.Register32 // 0x124
	SPI_FMEM_PMS2_SIZE           volatile.Register32 // 0x128
	SPI_FMEM_PMS3_SIZE           volatile.Register32 // 0x12C
	SPI_SMEM_PMS0_ATTR           volatile.Register32 // 0x130
	SPI_SMEM_PMS1_ATTR           volatile.Register32 // 0x134
	SPI_SMEM_PMS2_ATTR           volatile.Register32 // 0x138
	SPI_SMEM_PMS3_ATTR           volatile.Register32 // 0x13C
	SPI_SMEM_PMS0_ADDR           volatile.Register32 // 0x140
	SPI_SMEM_PMS1_ADDR           volatile.Register32 // 0x144
	SPI_SMEM_PMS2_ADDR           volatile.Register32 // 0x148
	SPI_SMEM_PMS3_ADDR           volatile.Register32 // 0x14C
	SPI_SMEM_PMS0_SIZE           volatile.Register32 // 0x150
	SPI_SMEM_PMS1_SIZE           volatile.Register32 // 0x154
	SPI_SMEM_PMS2_SIZE           volatile.Register32 // 0x158
	SPI_SMEM_PMS3_SIZE           volatile.Register32 // 0x15C
	_                            [4]byte
	SPI_MEM_PMS_REJECT           volatile.Register32 // 0x164
	SPI_MEM_ECC_CTRL             volatile.Register32 // 0x168
	SPI_MEM_ECC_ERR_ADDR         volatile.Register32 // 0x16C
	SPI_MEM_AXI_ERR_ADDR         volatile.Register32 // 0x170
	SPI_SMEM_ECC_CTRL            volatile.Register32 // 0x174
	SPI_SMEM_AXI_ADDR_CTRL       volatile.Register32 // 0x178
	SPI_MEM_AXI_ERR_RESP_EN      volatile.Register32 // 0x17C
	SPI_MEM_TIMING_CALI          volatile.Register32 // 0x180
	SPI_MEM_DIN_MODE             volatile.Register32 // 0x184
	SPI_MEM_DIN_NUM              volatile.Register32 // 0x188
	SPI_MEM_DOUT_MODE            volatile.Register32 // 0x18C
	SPI_SMEM_TIMING_CALI         volatile.Register32 // 0x190
	SPI_SMEM_DIN_MODE            volatile.Register32 // 0x194
	SPI_SMEM_DIN_NUM             volatile.Register32 // 0x198
	SPI_SMEM_DOUT_MODE           volatile.Register32 // 0x19C
	SPI_SMEM_AC                  volatile.Register32 // 0x1A0
	SPI_SMEM_DIN_HEX_MODE        volatile.Register32 // 0x1A4
	SPI_SMEM_DIN_HEX_NUM         volatile.Register32 // 0x1A8
	SPI_SMEM_DOUT_HEX_MODE       volatile.Register32 // 0x1AC
	_                            [80]byte
	SPI_MEM_CLOCK_GATE           volatile.Register32 // 0x200
	_                            [252]byte
	SPI_MEM_XTS_PLAIN_BASE       volatile.Register32 // 0x300
	_                            [60]byte
	SPI_MEM_XTS_LINESIZE         volatile.Register32 // 0x340
	SPI_MEM_XTS_DESTINATION      volatile.Register32 // 0x344
	SPI_MEM_XTS_PHYSICAL_ADDRESS volatile.Register32 // 0x348
	SPI_MEM_XTS_TRIGGER          volatile.Register32 // 0x34C
	SPI_MEM_XTS_RELEASE          volatile.Register32 // 0x350
	SPI_MEM_XTS_DESTROY          volatile.Register32 // 0x354
	SPI_MEM_XTS_STATE            volatile.Register32 // 0x358
	SPI_MEM_XTS_DATE             volatile.Register32 // 0x35C
	_                            [28]byte
	SPI_MEM_MMU_ITEM_CONTENT     volatile.Register32 // 0x37C
	SPI_MEM_MMU_ITEM_INDEX       volatile.Register32 // 0x380
	SPI_MEM_MMU_POWER_CTRL       volatile.Register32 // 0x384
	SPI_MEM_DPA_CTRL             volatile.Register32 // 0x388
	_                            [100]byte
	SPI_MEM_REGISTERRND_ECO_HIGH volatile.Register32 // 0x3F0
	SPI_MEM_REGISTERRND_ECO_LOW  volatile.Register32 // 0x3F4
	_                            [4]byte
	SPI_MEM_DATE                 volatile.Register32 // 0x3FC
}

// SPI0.SPI_MEM_CMD: SPI0 FSM status register
func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf
}
func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18)
}
func (o *SPI0_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18
}

// SPI0.SPI_MEM_CTRL: SPI0 control register.
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_CTRL1: SPI0 control1 register.
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x200000)|value<<21)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x200000) >> 21
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x400000)|value<<22)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x400000) >> 22
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x800000)|value<<23)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x800000) >> 23
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x1000000) >> 24
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x2000000)|value<<25)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x2000000) >> 25
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x4000000) >> 26
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RAM0_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x8000000) >> 27
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_CTRL2: SPI0 control2 register.
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1f)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1f
}
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x3e0)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x3e0) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1c00)|value<<10)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1c00) >> 10
}
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x1000000) >> 24
}
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x7e000000)|value<<25)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x7e000000) >> 25
}
func (o *SPI0_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_CLOCK: SPI clock division control register.
func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff
}
func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16)
}
func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16
}
func (o *SPI0_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_USER: SPI0 user register.
func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_HOLD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_HOLD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CS_SETUP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CS_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26
}
func (o *SPI0_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29
}

// SPI0.SPI_MEM_USER1: SPI0 user1 register.
func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value)
}
func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f
}
func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x1c0)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DBYTELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x1c0) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26)
}
func (o *SPI0_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26
}

// SPI0.SPI_MEM_USER2: SPI0 user2 register.
func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff
}
func (o *SPI0_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28
}

// SPI0.SPI_MEM_RD_STATUS: SPI0 read control register.
func (o *SPI0_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16)
}
func (o *SPI0_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16
}

// SPI0.SPI_MEM_MISC: SPI0 misc register
func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_FSUB_PIN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_FSUB_PIN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_SSUB_PIN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_SSUB_PIN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10)
}
func (o *SPI0_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10
}

// SPI0.SPI_MEM_CACHE_FCTRL: SPI0 bit mode control register.
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_CACHE_SCTRL: SPI0 external RAM control register
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc0)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc0) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc000)|value<<14)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc000) >> 14
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x100000)|value<<20)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x100000) >> 20
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0x200000)|value<<21)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0x200000) >> 21
}
func (o *SPI0_Type) SetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_SCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg)&^(0xfc00000)|value<<22)
}
func (o *SPI0_Type) GetSPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_SCTRL.Reg) & 0xfc00000) >> 22
}

// SPI0.SPI_MEM_SRAM_CMD: SPI0 external RAM mode control register
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x3fc)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x3fc) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400)|value<<10)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400) >> 10
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800)|value<<11)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800) >> 11
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x8000) >> 15
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x10000)|value<<16)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x10000) >> 16
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x20000)|value<<17)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x20000) >> 17
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000)|value<<18)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000) >> 18
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000)|value<<19)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000) >> 19
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x100000)|value<<20)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x100000) >> 20
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x200000)|value<<21)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x200000) >> 21
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x400000)|value<<22)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x400000) >> 22
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x800000)|value<<23)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x800000) >> 23
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x1000000) >> 24
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x2000000)|value<<25)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x2000000) >> 25
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_HEX(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDIN_HEX() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x4000000) >> 26
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_HEX(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_HEX() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x8000000) >> 27
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CMD.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_SRAM_DRD_CMD: SPI0 external RAM DDR read command control register
func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xffff
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg)&^(0xf0000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DRD_CMD.Reg) & 0xf0000000) >> 28
}

// SPI0.SPI_MEM_SRAM_DWR_CMD: SPI0 external RAM DDR write command control register
func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xffff
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg)&^(0xf0000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_DWR_CMD.Reg) & 0xf0000000) >> 28
}

// SPI0.SPI_MEM_SRAM_CLK: SPI0 external RAM clock control register
func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff00)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff00) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0xff0000)|value<<16)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0xff0000) >> 16
}
func (o *SPI0_Type) SetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SRAM_CLK.Reg, volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SRAM_CLK.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_FSM: SPI0 FSM status register
func (o *SPI0_Type) SetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FSM.Reg, volatile.LoadUint32(&o.SPI_MEM_FSM.Reg)&^(0xf80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FSM.Reg) & 0xf80) >> 7
}

// SPI0.SPI_MEM_INT_ENA: SPI0 interrupt enable register
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_DQS0_AFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_DQS0_AFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_DQS1_AFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_DQS1_AFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO1_UDF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO1_UDF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO0_UDF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO0_UDF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_INT_CLR: SPI0 interrupt clear register
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_DQS0_AFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_DQS0_AFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_DQS1_AFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_DQS1_AFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO1_UDF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO1_UDF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO0_UDF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO0_UDF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_INT_RAW: SPI0 interrupt raw register
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_DQS0_AFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_DQS0_AFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_DQS1_AFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_DQS1_AFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO1_UDF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO1_UDF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO0_UDF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO0_UDF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_INT_ST: SPI0 interrupt status register
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_DQS0_AFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_DQS0_AFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_DQS1_AFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_DQS1_AFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO1_UDF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO1_UDF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO0_UDF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_INT_ST_SPI_MEM_BUS_FIFO0_UDF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_DDR: SPI0 flash DDR mode control register
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30
}

// SPI0.SPI_SMEM_DDR: SPI0 external RAM DDR mode control register
func (o *SPI0_Type) SetSPI_SMEM_DDR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_RDAT_SWP(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_RDAT_SWP() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_WDAT_SWP(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_WDAT_SWP() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_CMD_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_CMD_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0xfe0)|value<<5)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0xfe0) >> 5
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1fc000)|value<<14)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1fc000) >> 14
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_DQS_LOOP(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x200000)|value<<21)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_DQS_LOOP() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x200000) >> 21
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x1000000) >> 24
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x4000000) >> 26
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x8000000) >> 27
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DDR.Reg) & 0x40000000) >> 30
}

// SPI0.SPI_FMEM_PMS0_ATTR: MSPI flash PMS section %s attribute register
func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS0_ATTR_SPI_FMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS0_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_FMEM_PMS1_ATTR: MSPI flash PMS section %s attribute register
func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS1_ATTR_SPI_FMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS1_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_FMEM_PMS2_ATTR: MSPI flash PMS section %s attribute register
func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS2_ATTR_SPI_FMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS2_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_FMEM_PMS3_ATTR: MSPI flash PMS section %s attribute register
func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS3_ATTR_SPI_FMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_FMEM_PMS3_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_FMEM_PMS0_ADDR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS0_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS0_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS0_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_FMEM_PMS1_ADDR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS1_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS1_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS1_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_FMEM_PMS2_ADDR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS2_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS2_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS2_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_FMEM_PMS3_ADDR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS3_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS3_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS3_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_FMEM_PMS0_SIZE: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS0_SIZE_SPI_FMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS0_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_FMEM_PMS1_SIZE: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS1_SIZE_SPI_FMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS1_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_FMEM_PMS2_SIZE: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS2_SIZE_SPI_FMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS2_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_FMEM_PMS3_SIZE: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_FMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_FMEM_PMS3_SIZE_SPI_FMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_FMEM_PMS3_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_SMEM_PMS0_ATTR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS0_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS0_ATTR_SPI_SMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS0_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_SMEM_PMS1_ATTR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS1_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS1_ATTR_SPI_SMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS1_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_SMEM_PMS2_ATTR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS2_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS2_ATTR_SPI_SMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS2_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_SMEM_PMS3_ATTR: SPI1 flash PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_RD_ATTR() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_WR_ATTR() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS3_ATTR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS3_ATTR_SPI_SMEM_PMS_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_PMS3_ATTR.Reg) & 0x4) >> 2
}

// SPI0.SPI_SMEM_PMS0_ADDR: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS0_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS0_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS0_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS0_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_SMEM_PMS1_ADDR: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS1_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS1_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS1_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS1_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_SMEM_PMS2_ADDR: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS2_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS2_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS2_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS2_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_SMEM_PMS3_ADDR: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS3_ADDR_S(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS3_ADDR.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS3_ADDR_S() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS3_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_SMEM_PMS0_SIZE: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS0_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS0_SIZE_SPI_SMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS0_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_SMEM_PMS1_SIZE: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS1_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS1_SIZE_SPI_SMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS1_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_SMEM_PMS2_SIZE: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS2_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS2_SIZE_SPI_SMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS2_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_SMEM_PMS3_SIZE: SPI1 external RAM PMS section %s start address register
func (o *SPI0_Type) SetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_PMS3_SIZE.Reg, volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg)&^(0x7fff)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_PMS3_SIZE_SPI_SMEM_PMS_SIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_PMS3_SIZE.Reg) & 0x7fff
}

// SPI0.SPI_MEM_PMS_REJECT: SPI1 access reject register
func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x7ffffff
}
func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PM_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x8000000) >> 27
}
func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_PMS_REJECT.Reg, volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_PMS_REJECT.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_ECC_CTRL: MSPI ECC control register
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x7e0)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_CNT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x7e0) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1f800)|value<<11)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1f800) >> 11
}
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x20000) >> 17
}
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xc0000) >> 18
}
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x100000) >> 20
}
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x200000) >> 21
}
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0x1000000) >> 24
}
func (o *SPI0_Type) SetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg)&^(0xfe000000)|value<<25)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_ECC_CTRL.Reg) & 0xfe000000) >> 25
}

// SPI0.SPI_MEM_ECC_ERR_ADDR: MSPI ECC error address register
func (o *SPI0_Type) SetSPI_MEM_ECC_ERR_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_ECC_ERR_ADDR() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_ECC_ERR_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_MEM_AXI_ERR_ADDR: SPI0 AXI request error address.
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg)&^(0x7ffffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_ADDR() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_ADDR.Reg) & 0x7ffffff
}

// SPI0.SPI_SMEM_ECC_CTRL: MSPI ECC control register
func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x20000)|value<<17)
}
func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x20000) >> 17
}
func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0xc0000)|value<<18)
}
func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0xc0000) >> 18
}
func (o *SPI0_Type) SetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_ECC_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *SPI0_Type) GetSPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_ECC_CTRL.Reg) & 0x100000) >> 20
}

// SPI0.SPI_SMEM_AXI_ADDR_CTRL: SPI0 AXI address control register
func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_MEM_ALL_FIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_MEM_ALL_FIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x4000000) >> 26
}
func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_RDATA_AFIFO_REMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_RDATA_AFIFO_REMPTY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x8000000) >> 27
}
func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_RADDR_AFIFO_REMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_RADDR_AFIFO_REMPTY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x10000000) >> 28
}
func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_WDATA_AFIFO_REMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_WDATA_AFIFO_REMPTY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x20000000) >> 29
}
func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_WBLEN_AFIFO_REMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_WBLEN_AFIFO_REMPTY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_SMEM_AXI_ADDR_CTRL_SPI_ALL_AXI_TRANS_AFIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg, volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_SMEM_AXI_ADDR_CTRL_SPI_ALL_AXI_TRANS_AFIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AXI_ADDR_CTRL.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_AXI_ERR_RESP_EN: SPI0 AXI error response enable register
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_VLD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_VLD() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_GID(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_GID() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_SIZE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_FLASH(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_FLASH() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_SENS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_SENS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_WSTRB(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_WSTRB() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_VLD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_VLD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_GID(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_GID() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x100) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_ECC(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x200)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_ECC() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x200) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_SENS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x400)|value<<10)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_SENS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x400) >> 10
}
func (o *SPI0_Type) SetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_AXI_SIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg, volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg)&^(0x800)|value<<11)
}
func (o *SPI0_Type) GetSPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_AXI_SIZE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_AXI_ERR_RESP_EN.Reg) & 0x800) >> 11
}

// SPI0.SPI_MEM_TIMING_CALI: SPI0 flash timing calibration register
func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_TIMING_CALI_UPDATE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_TIMING_CALI_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x40) >> 6
}

// SPI0.SPI_MEM_DIN_MODE: MSPI flash input timing delay mode control register
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00)|value<<9)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00) >> 9
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000)|value<<12)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000) >> 12
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x38000)|value<<15)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x38000) >> 15
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x1c0000) >> 18
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0xe00000)|value<<21)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0xe00000) >> 21
}
func (o *SPI0_Type) SetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg)&^(0x7000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_MODE.Reg) & 0x7000000) >> 24
}

// SPI0.SPI_MEM_DIN_NUM: MSPI flash input timing delay number control register
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc0)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc0) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x300)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x300) >> 8
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc00)|value<<10)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc00) >> 10
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x3000)|value<<12)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x3000) >> 12
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0xc000)|value<<14)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0xc000) >> 14
}
func (o *SPI0_Type) SetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg)&^(0x30000)|value<<16)
}
func (o *SPI0_Type) GetSPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DIN_NUM.Reg) & 0x30000) >> 16
}

// SPI0.SPI_MEM_DOUT_MODE: MSPI flash output timing adjustment control register
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DOUT_MODE.Reg) & 0x100) >> 8
}

// SPI0.SPI_SMEM_TIMING_CALI: MSPI external RAM timing calibration register
func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x1c)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x1c) >> 2
}
func (o *SPI0_Type) SetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_TIMING_CALI.Reg) & 0x20) >> 5
}

// SPI0.SPI_SMEM_DIN_MODE: MSPI external RAM input timing delay mode control register
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38)|value<<3)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38) >> 3
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0)|value<<6)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0) >> 6
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00)|value<<9)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00) >> 9
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000)|value<<12)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000) >> 12
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x38000)|value<<15)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x38000) >> 15
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x1c0000)|value<<18)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x1c0000) >> 18
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0xe00000)|value<<21)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0xe00000) >> 21
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg)&^(0x7000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_MODE.Reg) & 0x7000000) >> 24
}

// SPI0.SPI_SMEM_DIN_NUM: MSPI external RAM input timing delay number control register
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30)|value<<4)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30) >> 4
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc0)|value<<6)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc0) >> 6
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x300)|value<<8)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x300) >> 8
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc00)|value<<10)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc00) >> 10
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x3000)|value<<12)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x3000) >> 12
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0xc000)|value<<14)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0xc000) >> 14
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg)&^(0x30000)|value<<16)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_NUM.Reg) & 0x30000) >> 16
}

// SPI0.SPI_SMEM_DOUT_MODE: MSPI external RAM output timing adjustment control register
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_MODE.Reg) & 0x100) >> 8
}

// SPI0.SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7c)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7c) >> 2
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0xf80)|value<<7)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0xf80) >> 7
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7000)|value<<12)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7000) >> 12
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x8000) >> 15
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x10000)|value<<16)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x10000) >> 16
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x7e000000)|value<<25)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x7e000000) >> 25
}
func (o *SPI0_Type) SetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_AC.Reg, volatile.LoadUint32(&o.SPI_SMEM_AC.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_AC.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_SMEM_DIN_HEX_MODE: MSPI 16x external RAM input timing delay mode control register
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN08_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN08_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x7
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN09_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x38)|value<<3)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN09_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x38) >> 3
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN10_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x1c0)|value<<6)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN10_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x1c0) >> 6
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN11_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0xe00)|value<<9)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN11_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0xe00) >> 9
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN12_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x7000)|value<<12)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN12_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x7000) >> 12
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN13_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x38000)|value<<15)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN13_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x38000) >> 15
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN14_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x1c0000)|value<<18)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN14_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x1c0000) >> 18
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN15_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0xe00000)|value<<21)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN15_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0xe00000) >> 21
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DINS_HEX_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg)&^(0x7000000)|value<<24)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DINS_HEX_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_MODE.Reg) & 0x7000000) >> 24
}

// SPI0.SPI_SMEM_DIN_HEX_NUM: MSPI 16x external RAM input timing delay number control register
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN08_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN08_NUM() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x3
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN09_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN09_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN10_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x30)|value<<4)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN10_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x30) >> 4
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN11_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc0)|value<<6)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN11_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc0) >> 6
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN12_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x300)|value<<8)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN12_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x300) >> 8
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN13_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc00)|value<<10)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN13_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc00) >> 10
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN14_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x3000)|value<<12)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN14_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x3000) >> 12
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN15_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0xc000)|value<<14)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN15_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0xc000) >> 14
}
func (o *SPI0_Type) SetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DINS_HEX_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg, volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg)&^(0x30000)|value<<16)
}
func (o *SPI0_Type) GetSPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DINS_HEX_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DIN_HEX_NUM.Reg) & 0x30000) >> 16
}

// SPI0.SPI_SMEM_DOUT_HEX_MODE: MSPI 16x external RAM output timing adjustment control register
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT08_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT08_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT09_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT09_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT10_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT10_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT11_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT11_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT12_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT12_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT13_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT13_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT14_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT14_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT15_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT15_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUTS_HEX_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg, volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg)&^(0x100)|value<<8)
}
func (o *SPI0_Type) GetSPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUTS_HEX_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SMEM_DOUT_HEX_MODE.Reg) & 0x100) >> 8
}

// SPI0.SPI_MEM_CLOCK_GATE: SPI0 clock gate register
func (o *SPI0_Type) SetSPI_MEM_CLOCK_GATE_SPI_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_CLOCK_GATE_SPI_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1
}

// SPI0.SPI_MEM_XTS_PLAIN_BASE: The base address of the memory that stores plaintext in Manual Encryption
func (o *SPI0_Type) SetSPI_MEM_XTS_PLAIN_BASE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg, value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_PLAIN_BASE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_PLAIN_BASE.Reg)
}

// SPI0.SPI_MEM_XTS_LINESIZE: Manual Encryption Line-Size register
func (o *SPI0_Type) SetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_LINESIZE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_LINESIZE.Reg) & 0x3
}

// SPI0.SPI_MEM_XTS_DESTINATION: Manual Encryption destination register
func (o *SPI0_Type) SetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_DESTINATION.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTINATION.Reg) & 0x1
}

// SPI0.SPI_MEM_XTS_PHYSICAL_ADDRESS: Manual Encryption physical address register
func (o *SPI0_Type) SetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg)&^(0x3ffffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_PHYSICAL_ADDRESS.Reg) & 0x3ffffff
}

// SPI0.SPI_MEM_XTS_TRIGGER: Manual Encryption physical address register
func (o *SPI0_Type) SetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_TRIGGER.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_TRIGGER.Reg) & 0x1
}

// SPI0.SPI_MEM_XTS_RELEASE: Manual Encryption physical address register
func (o *SPI0_Type) SetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_RELEASE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_RELEASE.Reg) & 0x1
}

// SPI0.SPI_MEM_XTS_DESTROY: Manual Encryption physical address register
func (o *SPI0_Type) SetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_DESTROY.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_DESTROY.Reg) & 0x1
}

// SPI0.SPI_MEM_XTS_STATE: Manual Encryption physical address register
func (o *SPI0_Type) SetSPI_MEM_XTS_STATE_SPI_XTS_STATE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_STATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_STATE_SPI_XTS_STATE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_STATE.Reg) & 0x3
}

// SPI0.SPI_MEM_XTS_DATE: Manual Encryption version register
func (o *SPI0_Type) SetSPI_MEM_XTS_DATE_SPI_XTS_DATE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_XTS_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg)&^(0x3fffffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_XTS_DATE_SPI_XTS_DATE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_XTS_DATE.Reg) & 0x3fffffff
}

// SPI0.SPI_MEM_MMU_ITEM_CONTENT: MSPI-MMU item content register
func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_CONTENT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg, value)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_CONTENT() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_CONTENT.Reg)
}

// SPI0.SPI_MEM_MMU_ITEM_INDEX: MSPI-MMU item index register
func (o *SPI0_Type) SetSPI_MEM_MMU_ITEM_INDEX(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg, value)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_ITEM_INDEX() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_MMU_ITEM_INDEX.Reg)
}

// SPI0.SPI_MEM_MMU_POWER_CTRL: MSPI MMU power control register
func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x1
}
func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x3fff0000)|value<<16)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x3fff0000) >> 16
}
func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x40000000) >> 30
}
func (o *SPI0_Type) SetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI0_Type) GetSPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MMU_POWER_CTRL.Reg) & 0x80000000) >> 31
}

// SPI0.SPI_MEM_DPA_CTRL: SPI memory cryption DPA register
func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x7
}
func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DPA_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DPA_CTRL.Reg) & 0x10) >> 4
}

// SPI0.SPI_MEM_REGISTERRND_ECO_HIGH: MSPI ECO high register
func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg, value)
}
func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_HIGH.Reg)
}

// SPI0.SPI_MEM_REGISTERRND_ECO_LOW: MSPI ECO low register
func (o *SPI0_Type) SetSPI_MEM_REGISTERRND_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg, value)
}
func (o *SPI0_Type) GetSPI_MEM_REGISTERRND_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_REGISTERRND_ECO_LOW.Reg)
}

// SPI0.SPI_MEM_DATE: SPI0 version control register
func (o *SPI0_Type) SetSPI_MEM_DATE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value)
}
func (o *SPI0_Type) GetSPI_MEM_DATE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff
}

// SPI (Serial Peripheral Interface) Controller 1
type SPI1_Type struct {
	SPI_MEM_CMD              volatile.Register32 // 0x0
	SPI_MEM_ADDR             volatile.Register32 // 0x4
	SPI_MEM_CTRL             volatile.Register32 // 0x8
	SPI_MEM_CTRL1            volatile.Register32 // 0xC
	SPI_MEM_CTRL2            volatile.Register32 // 0x10
	SPI_MEM_CLOCK            volatile.Register32 // 0x14
	SPI_MEM_USER             volatile.Register32 // 0x18
	SPI_MEM_USER1            volatile.Register32 // 0x1C
	SPI_MEM_USER2            volatile.Register32 // 0x20
	SPI_MEM_MOSI_DLEN        volatile.Register32 // 0x24
	SPI_MEM_MISO_DLEN        volatile.Register32 // 0x28
	SPI_MEM_RD_STATUS        volatile.Register32 // 0x2C
	_                        [4]byte
	SPI_MEM_MISC             volatile.Register32 // 0x34
	SPI_MEM_TX_CRC           volatile.Register32 // 0x38
	SPI_MEM_CACHE_FCTRL      volatile.Register32 // 0x3C
	_                        [24]byte
	SPI_MEM_W0               volatile.Register32 // 0x58
	SPI_MEM_W1               volatile.Register32 // 0x5C
	SPI_MEM_W2               volatile.Register32 // 0x60
	SPI_MEM_W3               volatile.Register32 // 0x64
	SPI_MEM_W4               volatile.Register32 // 0x68
	SPI_MEM_W5               volatile.Register32 // 0x6C
	SPI_MEM_W6               volatile.Register32 // 0x70
	SPI_MEM_W7               volatile.Register32 // 0x74
	SPI_MEM_W8               volatile.Register32 // 0x78
	SPI_MEM_W9               volatile.Register32 // 0x7C
	SPI_MEM_W10              volatile.Register32 // 0x80
	SPI_MEM_W11              volatile.Register32 // 0x84
	SPI_MEM_W12              volatile.Register32 // 0x88
	SPI_MEM_W13              volatile.Register32 // 0x8C
	SPI_MEM_W14              volatile.Register32 // 0x90
	SPI_MEM_W15              volatile.Register32 // 0x94
	SPI_MEM_FLASH_WAITI_CTRL volatile.Register32 // 0x98
	SPI_MEM_FLASH_SUS_CTRL   volatile.Register32 // 0x9C
	SPI_MEM_FLASH_SUS_CMD    volatile.Register32 // 0xA0
	SPI_MEM_SUS_STATUS       volatile.Register32 // 0xA4
	_                        [24]byte
	SPI_MEM_INT_ENA          volatile.Register32 // 0xC0
	SPI_MEM_INT_CLR          volatile.Register32 // 0xC4
	SPI_MEM_INT_RAW          volatile.Register32 // 0xC8
	SPI_MEM_INT_ST           volatile.Register32 // 0xCC
	_                        [4]byte
	SPI_MEM_DDR              volatile.Register32 // 0xD4
	_                        [168]byte
	SPI_MEM_TIMING_CALI      volatile.Register32 // 0x180
	_                        [124]byte
	SPI_MEM_CLOCK_GATE       volatile.Register32 // 0x200
	_                        [504]byte
	SPI_MEM_DATE             volatile.Register32 // 0x3FC
}

// SPI1.SPI_MEM_CMD: SPI1 memory command register
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_MST_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf)|value)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_MST_ST() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_SLV_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0xf0)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_SLV_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0xf0) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000)|value<<17)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000) >> 17
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_USR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000)|value<<18)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_USR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000) >> 18
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_HPM(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000)|value<<19)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_HPM() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000) >> 19
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RES(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x100000)|value<<20)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RES() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x100000) >> 20
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_DP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x200000)|value<<21)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_DP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x200000) >> 21
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_CE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x400000)|value<<22)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_CE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x400000) >> 22
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_BE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x800000)|value<<23)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_BE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x800000) >> 23
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_SE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_SE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x1000000) >> 24
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_PP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x2000000)|value<<25)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_PP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x2000000) >> 25
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRSR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x4000000) >> 26
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDSR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x8000000) >> 27
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_RDID(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_RDID() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x10000000) >> 28
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WRDI() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x20000000) >> 29
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_WREN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_WREN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x40000000) >> 30
}
func (o *SPI1_Type) SetSPI_MEM_CMD_SPI_MEM_FLASH_READ(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_CMD.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI1_Type) GetSPI_MEM_CMD_SPI_MEM_FLASH_READ() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CMD.Reg) & 0x80000000) >> 31
}

// SPI1.SPI_MEM_ADDR: SPI1 address register
func (o *SPI1_Type) SetSPI_MEM_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_ADDR.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_ADDR() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_ADDR.Reg)
}

// SPI1.SPI_MEM_CTRL: SPI1 control register.
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDOUT_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FDIN_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x20) >> 5
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FADDR_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40) >> 6
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100) >> 8
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCMD_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200) >> 9
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400) >> 10
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800)|value<<11)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_TX_CRC_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800) >> 11
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FASTRD_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x2000) >> 13
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x4000) >> 14
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_RESANDRES(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_RESANDRES() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x8000) >> 15
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_Q_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_Q_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x40000) >> 18
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_D_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x80000)|value<<19)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_D_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x80000) >> 19
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x100000) >> 20
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x200000) >> 21
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_WRSR_2B(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_WRSR_2B() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x400000) >> 22
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_DIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x800000) >> 23
}
func (o *SPI1_Type) SetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL_SPI_MEM_FREAD_QIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL.Reg) & 0x1000000) >> 24
}

// SPI1.SPI_MEM_CTRL1: SPI1 control1 register.
func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0x3)|value)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CLK_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0x3
}
func (o *SPI1_Type) SetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL1.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg)&^(0xffc)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL1.Reg) & 0xffc) >> 2
}

// SPI1.SPI_MEM_CTRL2: SPI1 control2 register.
func (o *SPI1_Type) SetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CTRL2.Reg, volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI1_Type) GetSPI_MEM_CTRL2_SPI_MEM_SYNC_RESET() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CTRL2.Reg) & 0x80000000) >> 31
}

// SPI1.SPI_MEM_CLOCK: SPI1 clock division control register.
func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff)|value)
}
func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_L() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff
}
func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff00)|value<<8)
}
func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_H() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff00) >> 8
}
func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0xff0000)|value<<16)
}
func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLKCNT_N() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0xff0000) >> 16
}
func (o *SPI1_Type) SetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI1_Type) GetSPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CLOCK.Reg) & 0x80000000) >> 31
}

// SPI1.SPI_MEM_USER: SPI1 user register.
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x200)|value<<9)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_CK_OUT_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x200) >> 9
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000)|value<<12)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000) >> 12
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000)|value<<13)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000) >> 13
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_DIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000)|value<<14)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_DIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000) >> 14
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_FWRITE_QIO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000)|value<<15)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_FWRITE_QIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000) >> 15
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x1000000) >> 24
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x2000000)|value<<25)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x2000000) >> 25
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x4000000) >> 26
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MOSI(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MOSI() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x8000000) >> 27
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_MISO(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_MISO() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x10000000) >> 28
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x20000000) >> 29
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x40000000) >> 30
}
func (o *SPI1_Type) SetSPI_MEM_USER_SPI_MEM_USR_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER.Reg, volatile.LoadUint32(&o.SPI_MEM_USER.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI1_Type) GetSPI_MEM_USER_SPI_MEM_USR_COMMAND() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER.Reg) & 0x80000000) >> 31
}

// SPI1.SPI_MEM_USER1: SPI1 user1 register.
func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0x3f)|value)
}
func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0x3f
}
func (o *SPI1_Type) SetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER1.Reg, volatile.LoadUint32(&o.SPI_MEM_USER1.Reg)&^(0xfc000000)|value<<26)
}
func (o *SPI1_Type) GetSPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER1.Reg) & 0xfc000000) >> 26
}

// SPI1.SPI_MEM_USER2: SPI1 user2 register.
func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xffff)|value)
}
func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xffff
}
func (o *SPI1_Type) SetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_USER2.Reg, volatile.LoadUint32(&o.SPI_MEM_USER2.Reg)&^(0xf0000000)|value<<28)
}
func (o *SPI1_Type) GetSPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_USER2.Reg) & 0xf0000000) >> 28
}

// SPI1.SPI_MEM_MOSI_DLEN: SPI1 send data bit length control register.
func (o *SPI1_Type) SetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MOSI_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg)&^(0x3ff)|value)
}
func (o *SPI1_Type) GetSPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_MOSI_DLEN.Reg) & 0x3ff
}

// SPI1.SPI_MEM_MISO_DLEN: SPI1 receive data bit length control register.
func (o *SPI1_Type) SetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISO_DLEN.Reg, volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg)&^(0x3ff)|value)
}
func (o *SPI1_Type) GetSPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_MISO_DLEN.Reg) & 0x3ff
}

// SPI1.SPI_MEM_RD_STATUS: SPI1 status register.
func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_STATUS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xffff)|value)
}
func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_STATUS() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xffff
}
func (o *SPI1_Type) SetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_RD_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg)&^(0xff0000)|value<<16)
}
func (o *SPI1_Type) GetSPI_MEM_RD_STATUS_SPI_MEM_WB_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_RD_STATUS.Reg) & 0xff0000) >> 16
}

// SPI1.SPI_MEM_MISC: SPI1 misc register
func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS0_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS0_DIS() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS1_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS1_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x200)|value<<9)
}
func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x200) >> 9
}
func (o *SPI1_Type) SetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_MISC.Reg, volatile.LoadUint32(&o.SPI_MEM_MISC.Reg)&^(0x400)|value<<10)
}
func (o *SPI1_Type) GetSPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_MISC.Reg) & 0x400) >> 10
}

// SPI1.SPI_MEM_TX_CRC: SPI1 TX CRC data register.
func (o *SPI1_Type) SetSPI_MEM_TX_CRC(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TX_CRC.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_TX_CRC() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_TX_CRC.Reg)
}

// SPI1.SPI_MEM_CACHE_FCTRL: SPI1 bit mode control register.
func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x20) >> 5
}
func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x40)|value<<6)
}
func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x40) >> 6
}
func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x80)|value<<7)
}
func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x80) >> 7
}
func (o *SPI1_Type) SetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CACHE_FCTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg)&^(0x100)|value<<8)
}
func (o *SPI1_Type) GetSPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_CACHE_FCTRL.Reg) & 0x100) >> 8
}

// SPI1.SPI_MEM_W0: SPI1 memory data buffer0
func (o *SPI1_Type) SetSPI_MEM_W0(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W0.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W0() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W0.Reg)
}

// SPI1.SPI_MEM_W1: SPI1 memory data buffer1
func (o *SPI1_Type) SetSPI_MEM_W1(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W1.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W1() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W1.Reg)
}

// SPI1.SPI_MEM_W2: SPI1 memory data buffer2
func (o *SPI1_Type) SetSPI_MEM_W2(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W2.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W2() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W2.Reg)
}

// SPI1.SPI_MEM_W3: SPI1 memory data buffer3
func (o *SPI1_Type) SetSPI_MEM_W3(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W3.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W3() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W3.Reg)
}

// SPI1.SPI_MEM_W4: SPI1 memory data buffer4
func (o *SPI1_Type) SetSPI_MEM_W4(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W4.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W4() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W4.Reg)
}

// SPI1.SPI_MEM_W5: SPI1 memory data buffer5
func (o *SPI1_Type) SetSPI_MEM_W5(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W5.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W5() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W5.Reg)
}

// SPI1.SPI_MEM_W6: SPI1 memory data buffer6
func (o *SPI1_Type) SetSPI_MEM_W6(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W6.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W6() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W6.Reg)
}

// SPI1.SPI_MEM_W7: SPI1 memory data buffer7
func (o *SPI1_Type) SetSPI_MEM_W7(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W7.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W7() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W7.Reg)
}

// SPI1.SPI_MEM_W8: SPI1 memory data buffer8
func (o *SPI1_Type) SetSPI_MEM_W8(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W8.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W8() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W8.Reg)
}

// SPI1.SPI_MEM_W9: SPI1 memory data buffer9
func (o *SPI1_Type) SetSPI_MEM_W9(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W9.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W9() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W9.Reg)
}

// SPI1.SPI_MEM_W10: SPI1 memory data buffer10
func (o *SPI1_Type) SetSPI_MEM_W10(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W10.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W10() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W10.Reg)
}

// SPI1.SPI_MEM_W11: SPI1 memory data buffer11
func (o *SPI1_Type) SetSPI_MEM_W11(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W11.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W11() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W11.Reg)
}

// SPI1.SPI_MEM_W12: SPI1 memory data buffer12
func (o *SPI1_Type) SetSPI_MEM_W12(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W12.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W12() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W12.Reg)
}

// SPI1.SPI_MEM_W13: SPI1 memory data buffer13
func (o *SPI1_Type) SetSPI_MEM_W13(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W13.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W13() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W13.Reg)
}

// SPI1.SPI_MEM_W14: SPI1 memory data buffer14
func (o *SPI1_Type) SetSPI_MEM_W14(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W14.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W14() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W14.Reg)
}

// SPI1.SPI_MEM_W15: SPI1 memory data buffer15
func (o *SPI1_Type) SetSPI_MEM_W15(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_W15.Reg, value)
}
func (o *SPI1_Type) GetSPI_MEM_W15() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_W15.Reg)
}

// SPI1.SPI_MEM_FLASH_WAITI_CTRL: SPI1 wait idle control register
func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x18)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x18) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0x200) >> 9
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xfc00)|value<<10)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xfc00) >> 10
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg)&^(0xffff0000)|value<<16)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_WAITI_CTRL.Reg) & 0xffff0000) >> 16
}

// SPI1.SPI_MEM_FLASH_SUS_CTRL: SPI1 flash suspend control register
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x20) >> 5
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x3fffc0)|value<<6)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x3fffc0) >> 6
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x400000) >> 22
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x800000) >> 23
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0x1000000) >> 24
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg)&^(0xfe000000)|value<<25)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CTRL.Reg) & 0xfe000000) >> 25
}

// SPI1.SPI_MEM_FLASH_SUS_CMD: SPI1 flash suspend command register
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff)|value)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff
}
func (o *SPI1_Type) SetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg, volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg)&^(0xffff0000)|value<<16)
}
func (o *SPI1_Type) GetSPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_FLASH_SUS_CMD.Reg) & 0xffff0000) >> 16
}

// SPI1.SPI_MEM_SUS_STATUS: SPI1 flash suspend status register
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x20) >> 5
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x40)|value<<6)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x40) >> 6
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x80)|value<<7)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x80) >> 7
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0x8000) >> 15
}
func (o *SPI1_Type) SetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_SUS_STATUS.Reg, volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg)&^(0xffff0000)|value<<16)
}
func (o *SPI1_Type) GetSPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_SUS_STATUS.Reg) & 0xffff0000) >> 16
}

// SPI1.SPI_MEM_INT_ENA: SPI1 interrupt enable register
func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ENA.Reg) & 0x400) >> 10
}

// SPI1.SPI_MEM_INT_CLR: SPI1 interrupt clear register
func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SPI1_Type) GetSPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_CLR.Reg) & 0x400) >> 10
}

// SPI1.SPI_MEM_INT_RAW: SPI1 interrupt raw register
func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *SPI1_Type) GetSPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_RAW.Reg) & 0x400) >> 10
}

// SPI1.SPI_MEM_INT_ST: SPI1 interrupt status register
func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_INT_ST.Reg, volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *SPI1_Type) GetSPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_INT_ST.Reg) & 0x400) >> 10
}

// SPI1.SPI_MEM_DDR: SPI1 DDR control register
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_VAR_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4) >> 2
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8)|value<<3)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8) >> 3
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10)|value<<4)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10) >> 4
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0xfe0)|value<<5)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0xfe0) >> 5
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1fc000)|value<<14)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1fc000) >> 14
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x200000)|value<<21)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x200000) >> 21
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x1000000) >> 24
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_DQS_CA_IN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x4000000) >> 26
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x8000000) >> 27
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x10000000) >> 28
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x20000000) >> 29
}
func (o *SPI1_Type) SetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DDR.Reg, volatile.LoadUint32(&o.SPI_MEM_DDR.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI1_Type) GetSPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_DDR.Reg) & 0x40000000) >> 30
}

// SPI1.SPI_MEM_TIMING_CALI: SPI1 timing control register
func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x2)|value<<1)
}
func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x2) >> 1
}
func (o *SPI1_Type) SetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_TIMING_CALI.Reg, volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg)&^(0x1c)|value<<2)
}
func (o *SPI1_Type) GetSPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MEM_TIMING_CALI.Reg) & 0x1c) >> 2
}

// SPI1.SPI_MEM_CLOCK_GATE: SPI1 clk_gate register
func (o *SPI1_Type) SetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_CLOCK_GATE.Reg, volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *SPI1_Type) GetSPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_CLOCK_GATE.Reg) & 0x1
}

// SPI1.SPI_MEM_DATE: Version control register
func (o *SPI1_Type) SetSPI_MEM_DATE(value uint32) {
	volatile.StoreUint32(&o.SPI_MEM_DATE.Reg, volatile.LoadUint32(&o.SPI_MEM_DATE.Reg)&^(0xfffffff)|value)
}
func (o *SPI1_Type) GetSPI_MEM_DATE() uint32 {
	return volatile.LoadUint32(&o.SPI_MEM_DATE.Reg) & 0xfffffff
}

// SPI (Serial Peripheral Interface) Controller 2
type SPI2_Type struct {
	SPI_CMD         volatile.Register32 // 0x0
	SPI_ADDR        volatile.Register32 // 0x4
	SPI_CTRL        volatile.Register32 // 0x8
	SPI_CLOCK       volatile.Register32 // 0xC
	SPI_USER        volatile.Register32 // 0x10
	SPI_USER1       volatile.Register32 // 0x14
	SPI_USER2       volatile.Register32 // 0x18
	SPI_MS_DLEN     volatile.Register32 // 0x1C
	SPI_MISC        volatile.Register32 // 0x20
	SPI_DIN_MODE    volatile.Register32 // 0x24
	SPI_DIN_NUM     volatile.Register32 // 0x28
	SPI_DOUT_MODE   volatile.Register32 // 0x2C
	SPI_DMA_CONF    volatile.Register32 // 0x30
	SPI_DMA_INT_ENA volatile.Register32 // 0x34
	SPI_DMA_INT_CLR volatile.Register32 // 0x38
	SPI_DMA_INT_RAW volatile.Register32 // 0x3C
	SPI_DMA_INT_ST  volatile.Register32 // 0x40
	SPI_DMA_INT_SET volatile.Register32 // 0x44
	_               [80]byte
	SPI_W0          volatile.Register32 // 0x98
	SPI_W1          volatile.Register32 // 0x9C
	SPI_W2          volatile.Register32 // 0xA0
	SPI_W3          volatile.Register32 // 0xA4
	SPI_W4          volatile.Register32 // 0xA8
	SPI_W5          volatile.Register32 // 0xAC
	SPI_W6          volatile.Register32 // 0xB0
	SPI_W7          volatile.Register32 // 0xB4
	SPI_W8          volatile.Register32 // 0xB8
	SPI_W9          volatile.Register32 // 0xBC
	SPI_W10         volatile.Register32 // 0xC0
	SPI_W11         volatile.Register32 // 0xC4
	SPI_W12         volatile.Register32 // 0xC8
	SPI_W13         volatile.Register32 // 0xCC
	SPI_W14         volatile.Register32 // 0xD0
	SPI_W15         volatile.Register32 // 0xD4
	_               [8]byte
	SPI_SLAVE       volatile.Register32 // 0xE0
	SPI_SLAVE1      volatile.Register32 // 0xE4
	SPI_CLK_GATE    volatile.Register32 // 0xE8
	_               [4]byte
	SPI_DATE        volatile.Register32 // 0xF0
}

// SPI2.SPI_CMD: Command control register
func (o *SPI2_Type) SetSPI_CMD_SPI_CONF_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x3ffff)|value)
}
func (o *SPI2_Type) GetSPI_CMD_SPI_CONF_BITLEN() uint32 {
	return volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x3ffff
}
func (o *SPI2_Type) SetSPI_CMD_SPI_UPDATE(value uint32) {
	volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x800000)|value<<23)
}
func (o *SPI2_Type) GetSPI_CMD_SPI_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x800000) >> 23
}
func (o *SPI2_Type) SetSPI_CMD_SPI_USR(value uint32) {
	volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI2_Type) GetSPI_CMD_SPI_USR() uint32 {
	return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x1000000) >> 24
}

// SPI2.SPI_ADDR: Address value register
func (o *SPI2_Type) SetSPI_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_ADDR.Reg, value)
}
func (o *SPI2_Type) GetSPI_ADDR() uint32 {
	return volatile.LoadUint32(&o.SPI_ADDR.Reg)
}

// SPI2.SPI_CTRL: SPI control register
func (o *SPI2_Type) SetSPI_CTRL_SPI_DUMMY_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_DUMMY_OUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FADDR_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FADDR_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FADDR_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FADDR_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FADDR_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FADDR_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FCMD_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FCMD_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FCMD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FCMD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FCMD_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x400)|value<<10)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FCMD_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x400) >> 10
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FREAD_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FREAD_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000) >> 14
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FREAD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FREAD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8000) >> 15
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_FREAD_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_FREAD_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_Q_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_Q_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_D_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_D_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_HOLD_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_HOLD_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100000) >> 20
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_WP_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_WP_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200000) >> 21
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_RD_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x1800000)|value<<23)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_RD_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x1800000) >> 23
}
func (o *SPI2_Type) SetSPI_CTRL_SPI_WR_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x6000000)|value<<25)
}
func (o *SPI2_Type) GetSPI_CTRL_SPI_WR_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x6000000) >> 25
}

// SPI2.SPI_CLOCK: SPI clock control register
func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKCNT_L(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f)|value)
}
func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKCNT_L() uint32 {
	return volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f
}
func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKCNT_H(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0xfc0)|value<<6)
}
func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKCNT_H() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0xfc0) >> 6
}
func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKCNT_N(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f000)|value<<12)
}
func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKCNT_N() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f000) >> 12
}
func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLKDIV_PRE(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3c0000)|value<<18)
}
func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLKDIV_PRE() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3c0000) >> 18
}
func (o *SPI2_Type) SetSPI_CLOCK_SPI_CLK_EQU_SYSCLK(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI2_Type) GetSPI_CLOCK_SPI_CLK_EQU_SYSCLK() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x80000000) >> 31
}

// SPI2.SPI_USER: SPI USER control register
func (o *SPI2_Type) SetSPI_USER_SPI_DOUTDIN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_USER_SPI_DOUTDIN() uint32 {
	return volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_USER_SPI_QPI_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_USER_SPI_QPI_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_USER_SPI_OPI_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_USER_SPI_OPI_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_USER_SPI_TSCK_I_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_USER_SPI_TSCK_I_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_USER_SPI_CS_HOLD(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_USER_SPI_CS_HOLD() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_USER_SPI_CS_SETUP(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_USER_SPI_CS_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_USER_SPI_RSCK_I_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_USER_SPI_RSCK_I_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_USER_SPI_CK_OUT_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_USER_SPI_CK_OUT_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_USER_SPI_FWRITE_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000)|value<<12)
}
func (o *SPI2_Type) GetSPI_USER_SPI_FWRITE_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000) >> 12
}
func (o *SPI2_Type) SetSPI_USER_SPI_FWRITE_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000)|value<<13)
}
func (o *SPI2_Type) GetSPI_USER_SPI_FWRITE_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000) >> 13
}
func (o *SPI2_Type) SetSPI_USER_SPI_FWRITE_OCT(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000)|value<<14)
}
func (o *SPI2_Type) GetSPI_USER_SPI_FWRITE_OCT() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000) >> 14
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_CONF_NXT(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000)|value<<15)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_CONF_NXT() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000) >> 15
}
func (o *SPI2_Type) SetSPI_USER_SPI_SIO(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000)|value<<17)
}
func (o *SPI2_Type) GetSPI_USER_SPI_SIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000) >> 17
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_MISO_HIGHPART(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_MISO_HIGHPART() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000000) >> 24
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_MOSI_HIGHPART(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000000)|value<<25)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_MOSI_HIGHPART() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000000) >> 25
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_DUMMY_IDLE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_DUMMY_IDLE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000000) >> 26
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_MOSI(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_MOSI() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000000) >> 27
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_MISO(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_MISO() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000000) >> 28
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000000) >> 29
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40000000) >> 30
}
func (o *SPI2_Type) SetSPI_USER_SPI_USR_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI2_Type) GetSPI_USER_SPI_USR_COMMAND() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80000000) >> 31
}

// SPI2.SPI_USER1: SPI USER control register 1
func (o *SPI2_Type) SetSPI_USER1_SPI_USR_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xff)|value)
}
func (o *SPI2_Type) GetSPI_USER1_SPI_USR_DUMMY_CYCLELEN() uint32 {
	return volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xff
}
func (o *SPI2_Type) SetSPI_USER1_SPI_MST_WFULL_ERR_END_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_USER1_SPI_MST_WFULL_ERR_END_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_USER1_SPI_CS_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x3e0000)|value<<17)
}
func (o *SPI2_Type) GetSPI_USER1_SPI_CS_SETUP_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x3e0000) >> 17
}
func (o *SPI2_Type) SetSPI_USER1_SPI_CS_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x7c00000)|value<<22)
}
func (o *SPI2_Type) GetSPI_USER1_SPI_CS_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x7c00000) >> 22
}
func (o *SPI2_Type) SetSPI_USER1_SPI_USR_ADDR_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xf8000000)|value<<27)
}
func (o *SPI2_Type) GetSPI_USER1_SPI_USR_ADDR_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xf8000000) >> 27
}

// SPI2.SPI_USER2: SPI USER control register 2
func (o *SPI2_Type) SetSPI_USER2_SPI_USR_COMMAND_VALUE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xffff)|value)
}
func (o *SPI2_Type) GetSPI_USER2_SPI_USR_COMMAND_VALUE() uint32 {
	return volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xffff
}
func (o *SPI2_Type) SetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI2_Type) GetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0x8000000) >> 27
}
func (o *SPI2_Type) SetSPI_USER2_SPI_USR_COMMAND_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xf0000000)|value<<28)
}
func (o *SPI2_Type) GetSPI_USER2_SPI_USR_COMMAND_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xf0000000) >> 28
}

// SPI2.SPI_MS_DLEN: SPI data bit length control register
func (o *SPI2_Type) SetSPI_MS_DLEN_SPI_MS_DATA_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MS_DLEN.Reg, volatile.LoadUint32(&o.SPI_MS_DLEN.Reg)&^(0x3ffff)|value)
}
func (o *SPI2_Type) GetSPI_MS_DLEN_SPI_MS_DATA_BITLEN() uint32 {
	return volatile.LoadUint32(&o.SPI_MS_DLEN.Reg) & 0x3ffff
}

// SPI2.SPI_MISC: SPI misc register
func (o *SPI2_Type) SetSPI_MISC_SPI_CS0_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CS0_DIS() uint32 {
	return volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CS1_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CS1_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CS2_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CS2_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CS3_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CS3_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CS4_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CS4_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CS5_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CS5_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CK_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CK_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_MISC_SPI_MASTER_CS_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1f80)|value<<7)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_MASTER_CS_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1f80) >> 7
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CLK_DATA_DTR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CLK_DATA_DTR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_MISC_SPI_DATA_DTR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20000)|value<<17)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_DATA_DTR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20000) >> 17
}
func (o *SPI2_Type) SetSPI_MISC_SPI_ADDR_DTR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_ADDR_DTR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CMD_DTR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CMD_DTR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_MISC_SPI_SLAVE_CS_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x800000)|value<<23)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_SLAVE_CS_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x800000) >> 23
}
func (o *SPI2_Type) SetSPI_MISC_SPI_DQS_IDLE_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_DQS_IDLE_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1000000) >> 24
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CK_IDLE_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CK_IDLE_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20000000) >> 29
}
func (o *SPI2_Type) SetSPI_MISC_SPI_CS_KEEP_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_CS_KEEP_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40000000) >> 30
}
func (o *SPI2_Type) SetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI2_Type) GetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x80000000) >> 31
}

// SPI2.SPI_DIN_MODE: SPI input delay mode configuration
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x3)|value)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x3
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc)|value<<2)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc) >> 2
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x30)|value<<4)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x30) >> 4
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc0)|value<<6)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc0) >> 6
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN4_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x300)|value<<8)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN4_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x300) >> 8
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN5_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc00)|value<<10)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN5_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc00) >> 10
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN6_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x3000)|value<<12)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN6_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x3000) >> 12
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_DIN7_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc000)|value<<14)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_DIN7_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc000) >> 14
}
func (o *SPI2_Type) SetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x10000) >> 16
}

// SPI2.SPI_DIN_NUM: SPI input delay number configuration
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN0_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x3)|value)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN0_NUM() uint32 {
	return volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x3
}
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN1_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc)|value<<2)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN1_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc) >> 2
}
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN2_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x30)|value<<4)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN2_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x30) >> 4
}
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN3_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc0)|value<<6)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN3_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc0) >> 6
}
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN4_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x300)|value<<8)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN4_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x300) >> 8
}
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN5_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc00)|value<<10)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN5_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc00) >> 10
}
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN6_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x3000)|value<<12)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN6_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x3000) >> 12
}
func (o *SPI2_Type) SetSPI_DIN_NUM_SPI_DIN7_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc000)|value<<14)
}
func (o *SPI2_Type) GetSPI_DIN_NUM_SPI_DIN7_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc000) >> 14
}

// SPI2.SPI_DOUT_MODE: SPI output delay mode configuration
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT4_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT4_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT5_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT5_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT6_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT6_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_DOUT7_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_DOUT7_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_DOUT_MODE_SPI_D_DQS_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_DOUT_MODE_SPI_D_DQS_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x100) >> 8
}

// SPI2.SPI_DMA_CONF: SPI DMA control register
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x100000) >> 20
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_RX_EOF_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_RX_EOF_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x200000) >> 21
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_RX_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_RX_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x8000000) >> 27
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_TX_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_TX_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x10000000) >> 28
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_RX_AFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_RX_AFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x20000000) >> 29
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_BUF_AFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_BUF_AFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000000) >> 30
}
func (o *SPI2_Type) SetSPI_DMA_CONF_SPI_DMA_AFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI2_Type) GetSPI_DMA_CONF_SPI_DMA_AFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000000) >> 31
}

// SPI2.SPI_DMA_INT_ENA: SPI interrupt enable register
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x400) >> 10
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x800) >> 11
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1000) >> 12
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2000) >> 13
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SEG_MAGIC_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SEG_MAGIC_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x4000) >> 14
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8000) >> 15
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20000) >> 17
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100000) >> 20
}

// SPI2.SPI_DMA_INT_CLR: SPI interrupt clear register
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x400) >> 10
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x800) >> 11
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1000) >> 12
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2000) >> 13
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SEG_MAGIC_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SEG_MAGIC_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x4000) >> 14
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8000) >> 15
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20000) >> 17
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SPI2_Type) GetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100000) >> 20
}

// SPI2.SPI_DMA_INT_RAW: SPI interrupt raw register
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x400) >> 10
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x800) >> 11
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1000) >> 12
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2000) >> 13
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SEG_MAGIC_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SEG_MAGIC_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x4000) >> 14
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8000) >> 15
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20000) >> 17
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *SPI2_Type) GetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100000) >> 20
}

// SPI2.SPI_DMA_INT_ST: SPI interrupt status register
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x400) >> 10
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x800) >> 11
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1000) >> 12
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2000) >> 13
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SEG_MAGIC_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SEG_MAGIC_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x4000) >> 14
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8000) >> 15
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20000) >> 17
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_APP2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_APP2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_DMA_INT_ST_SPI_APP1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *SPI2_Type) GetSPI_DMA_INT_ST_SPI_APP1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100000) >> 20
}

// SPI2.SPI_DMA_INT_SET: SPI interrupt software set register
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10)|value<<4)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10) >> 4
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20)|value<<5)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20) >> 5
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40)|value<<6)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40) >> 6
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80)|value<<7)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80) >> 7
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x400)|value<<10)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x400) >> 10
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x800)|value<<11)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x800) >> 11
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1000)|value<<12)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1000) >> 12
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2000)|value<<13)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2000) >> 13
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SEG_MAGIC_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x4000)|value<<14)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SEG_MAGIC_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x4000) >> 14
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8000)|value<<15)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8000) >> 15
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10000)|value<<16)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10000) >> 16
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20000)|value<<17)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20000) >> 17
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40000)|value<<18)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40000) >> 18
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_APP2_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80000)|value<<19)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_APP2_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80000) >> 19
}
func (o *SPI2_Type) SetSPI_DMA_INT_SET_SPI_APP1_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100000)|value<<20)
}
func (o *SPI2_Type) GetSPI_DMA_INT_SET_SPI_APP1_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100000) >> 20
}

// SPI2.SPI_W0: SPI CPU-controlled buffer0
func (o *SPI2_Type) SetSPI_W0(value uint32) {
	volatile.StoreUint32(&o.SPI_W0.Reg, value)
}
func (o *SPI2_Type) GetSPI_W0() uint32 {
	return volatile.LoadUint32(&o.SPI_W0.Reg)
}

// SPI2.SPI_W1: SPI CPU-controlled buffer1
func (o *SPI2_Type) SetSPI_W1(value uint32) {
	volatile.StoreUint32(&o.SPI_W1.Reg, value)
}
func (o *SPI2_Type) GetSPI_W1() uint32 {
	return volatile.LoadUint32(&o.SPI_W1.Reg)
}

// SPI2.SPI_W2: SPI CPU-controlled buffer2
func (o *SPI2_Type) SetSPI_W2(value uint32) {
	volatile.StoreUint32(&o.SPI_W2.Reg, value)
}
func (o *SPI2_Type) GetSPI_W2() uint32 {
	return volatile.LoadUint32(&o.SPI_W2.Reg)
}

// SPI2.SPI_W3: SPI CPU-controlled buffer3
func (o *SPI2_Type) SetSPI_W3(value uint32) {
	volatile.StoreUint32(&o.SPI_W3.Reg, value)
}
func (o *SPI2_Type) GetSPI_W3() uint32 {
	return volatile.LoadUint32(&o.SPI_W3.Reg)
}

// SPI2.SPI_W4: SPI CPU-controlled buffer4
func (o *SPI2_Type) SetSPI_W4(value uint32) {
	volatile.StoreUint32(&o.SPI_W4.Reg, value)
}
func (o *SPI2_Type) GetSPI_W4() uint32 {
	return volatile.LoadUint32(&o.SPI_W4.Reg)
}

// SPI2.SPI_W5: SPI CPU-controlled buffer5
func (o *SPI2_Type) SetSPI_W5(value uint32) {
	volatile.StoreUint32(&o.SPI_W5.Reg, value)
}
func (o *SPI2_Type) GetSPI_W5() uint32 {
	return volatile.LoadUint32(&o.SPI_W5.Reg)
}

// SPI2.SPI_W6: SPI CPU-controlled buffer6
func (o *SPI2_Type) SetSPI_W6(value uint32) {
	volatile.StoreUint32(&o.SPI_W6.Reg, value)
}
func (o *SPI2_Type) GetSPI_W6() uint32 {
	return volatile.LoadUint32(&o.SPI_W6.Reg)
}

// SPI2.SPI_W7: SPI CPU-controlled buffer7
func (o *SPI2_Type) SetSPI_W7(value uint32) {
	volatile.StoreUint32(&o.SPI_W7.Reg, value)
}
func (o *SPI2_Type) GetSPI_W7() uint32 {
	return volatile.LoadUint32(&o.SPI_W7.Reg)
}

// SPI2.SPI_W8: SPI CPU-controlled buffer8
func (o *SPI2_Type) SetSPI_W8(value uint32) {
	volatile.StoreUint32(&o.SPI_W8.Reg, value)
}
func (o *SPI2_Type) GetSPI_W8() uint32 {
	return volatile.LoadUint32(&o.SPI_W8.Reg)
}

// SPI2.SPI_W9: SPI CPU-controlled buffer9
func (o *SPI2_Type) SetSPI_W9(value uint32) {
	volatile.StoreUint32(&o.SPI_W9.Reg, value)
}
func (o *SPI2_Type) GetSPI_W9() uint32 {
	return volatile.LoadUint32(&o.SPI_W9.Reg)
}

// SPI2.SPI_W10: SPI CPU-controlled buffer10
func (o *SPI2_Type) SetSPI_W10(value uint32) {
	volatile.StoreUint32(&o.SPI_W10.Reg, value)
}
func (o *SPI2_Type) GetSPI_W10() uint32 {
	return volatile.LoadUint32(&o.SPI_W10.Reg)
}

// SPI2.SPI_W11: SPI CPU-controlled buffer11
func (o *SPI2_Type) SetSPI_W11(value uint32) {
	volatile.StoreUint32(&o.SPI_W11.Reg, value)
}
func (o *SPI2_Type) GetSPI_W11() uint32 {
	return volatile.LoadUint32(&o.SPI_W11.Reg)
}

// SPI2.SPI_W12: SPI CPU-controlled buffer12
func (o *SPI2_Type) SetSPI_W12(value uint32) {
	volatile.StoreUint32(&o.SPI_W12.Reg, value)
}
func (o *SPI2_Type) GetSPI_W12() uint32 {
	return volatile.LoadUint32(&o.SPI_W12.Reg)
}

// SPI2.SPI_W13: SPI CPU-controlled buffer13
func (o *SPI2_Type) SetSPI_W13(value uint32) {
	volatile.StoreUint32(&o.SPI_W13.Reg, value)
}
func (o *SPI2_Type) GetSPI_W13() uint32 {
	return volatile.LoadUint32(&o.SPI_W13.Reg)
}

// SPI2.SPI_W14: SPI CPU-controlled buffer14
func (o *SPI2_Type) SetSPI_W14(value uint32) {
	volatile.StoreUint32(&o.SPI_W14.Reg, value)
}
func (o *SPI2_Type) GetSPI_W14() uint32 {
	return volatile.LoadUint32(&o.SPI_W14.Reg)
}

// SPI2.SPI_W15: SPI CPU-controlled buffer15
func (o *SPI2_Type) SetSPI_W15(value uint32) {
	volatile.StoreUint32(&o.SPI_W15.Reg, value)
}
func (o *SPI2_Type) GetSPI_W15() uint32 {
	return volatile.LoadUint32(&o.SPI_W15.Reg)
}

// SPI2.SPI_SLAVE: SPI slave control register
func (o *SPI2_Type) SetSPI_SLAVE_SPI_CLK_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3)|value)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_CLK_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_CLK_MODE_13(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_CLK_MODE_13() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4) >> 2
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_RSCK_DATA_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8)|value<<3)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_RSCK_DATA_OUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8) >> 3
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x100)|value<<8)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x100) >> 8
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x200)|value<<9)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x200) >> 9
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x400)|value<<10)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x400) >> 10
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x800)|value<<11)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x800) >> 11
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0xff000)|value<<12)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0xff000) >> 12
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_DMA_SEG_MAGIC_VALUE(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3c00000)|value<<22)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_DMA_SEG_MAGIC_VALUE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3c00000) >> 22
}
func (o *SPI2_Type) SetSPI_SLAVE_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI2_Type) GetSPI_SLAVE_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4000000) >> 26
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_SOFT_RESET(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_SOFT_RESET() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8000000) >> 27
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_USR_CONF(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_USR_CONF() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x10000000) >> 28
}
func (o *SPI2_Type) SetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI2_Type) GetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x20000000) >> 29
}

// SPI2.SPI_SLAVE1: SPI slave control register 1
func (o *SPI2_Type) SetSPI_SLAVE1_SPI_SLV_DATA_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3ffff)|value)
}
func (o *SPI2_Type) GetSPI_SLAVE1_SPI_SLV_DATA_BITLEN() uint32 {
	return volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3ffff
}
func (o *SPI2_Type) SetSPI_SLAVE1_SPI_SLV_LAST_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3fc0000)|value<<18)
}
func (o *SPI2_Type) GetSPI_SLAVE1_SPI_SLV_LAST_COMMAND() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3fc0000) >> 18
}
func (o *SPI2_Type) SetSPI_SLAVE1_SPI_SLV_LAST_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xfc000000)|value<<26)
}
func (o *SPI2_Type) GetSPI_SLAVE1_SPI_SLV_LAST_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xfc000000) >> 26
}

// SPI2.SPI_CLK_GATE: SPI module clock and register clock control
func (o *SPI2_Type) SetSPI_CLK_GATE_SPI_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x1)|value)
}
func (o *SPI2_Type) GetSPI_CLK_GATE_SPI_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x1
}
func (o *SPI2_Type) SetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x2)|value<<1)
}
func (o *SPI2_Type) GetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x2) >> 1
}
func (o *SPI2_Type) SetSPI_CLK_GATE_SPI_MST_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x4)|value<<2)
}
func (o *SPI2_Type) GetSPI_CLK_GATE_SPI_MST_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x4) >> 2
}

// SPI2.SPI_DATE: Version control
func (o *SPI2_Type) SetSPI_DATE(value uint32) {
	volatile.StoreUint32(&o.SPI_DATE.Reg, volatile.LoadUint32(&o.SPI_DATE.Reg)&^(0xfffffff)|value)
}
func (o *SPI2_Type) GetSPI_DATE() uint32 {
	return volatile.LoadUint32(&o.SPI_DATE.Reg) & 0xfffffff
}

// SPI (Serial Peripheral Interface) Controller 3
type SPI3_Type struct {
	SPI_CMD         volatile.Register32 // 0x0
	SPI_ADDR        volatile.Register32 // 0x4
	SPI_CTRL        volatile.Register32 // 0x8
	SPI_CLOCK       volatile.Register32 // 0xC
	SPI_USER        volatile.Register32 // 0x10
	SPI_USER1       volatile.Register32 // 0x14
	SPI_USER2       volatile.Register32 // 0x18
	SPI_MS_DLEN     volatile.Register32 // 0x1C
	SPI_MISC        volatile.Register32 // 0x20
	SPI_DIN_MODE    volatile.Register32 // 0x24
	SPI_DIN_NUM     volatile.Register32 // 0x28
	SPI_DOUT_MODE   volatile.Register32 // 0x2C
	SPI_DMA_CONF    volatile.Register32 // 0x30
	SPI_DMA_INT_ENA volatile.Register32 // 0x34
	SPI_DMA_INT_CLR volatile.Register32 // 0x38
	SPI_DMA_INT_RAW volatile.Register32 // 0x3C
	SPI_DMA_INT_ST  volatile.Register32 // 0x40
	SPI_DMA_INT_SET volatile.Register32 // 0x44
	_               [80]byte
	SPI_W0          volatile.Register32 // 0x98
	SPI_W1          volatile.Register32 // 0x9C
	SPI_W2          volatile.Register32 // 0xA0
	SPI_W3          volatile.Register32 // 0xA4
	SPI_W4          volatile.Register32 // 0xA8
	SPI_W5          volatile.Register32 // 0xAC
	SPI_W6          volatile.Register32 // 0xB0
	SPI_W7          volatile.Register32 // 0xB4
	SPI_W8          volatile.Register32 // 0xB8
	SPI_W9          volatile.Register32 // 0xBC
	SPI_W10         volatile.Register32 // 0xC0
	SPI_W11         volatile.Register32 // 0xC4
	SPI_W12         volatile.Register32 // 0xC8
	SPI_W13         volatile.Register32 // 0xCC
	SPI_W14         volatile.Register32 // 0xD0
	SPI_W15         volatile.Register32 // 0xD4
	_               [8]byte
	SPI_SLAVE       volatile.Register32 // 0xE0
	SPI_SLAVE1      volatile.Register32 // 0xE4
	SPI_CLK_GATE    volatile.Register32 // 0xE8
	_               [4]byte
	SPI_DATE        volatile.Register32 // 0xF0
}

// SPI3.SPI_CMD: Command control register
func (o *SPI3_Type) SetSPI_CMD_SPI_UPDATE(value uint32) {
	volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x800000)|value<<23)
}
func (o *SPI3_Type) GetSPI_CMD_SPI_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x800000) >> 23
}
func (o *SPI3_Type) SetSPI_CMD_SPI_USR(value uint32) {
	volatile.StoreUint32(&o.SPI_CMD.Reg, volatile.LoadUint32(&o.SPI_CMD.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI3_Type) GetSPI_CMD_SPI_USR() uint32 {
	return (volatile.LoadUint32(&o.SPI_CMD.Reg) & 0x1000000) >> 24
}

// SPI3.SPI_ADDR: Address value register
func (o *SPI3_Type) SetSPI_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_ADDR.Reg, value)
}
func (o *SPI3_Type) GetSPI_ADDR() uint32 {
	return volatile.LoadUint32(&o.SPI_ADDR.Reg)
}

// SPI3.SPI_CTRL: SPI control register
func (o *SPI3_Type) SetSPI_CTRL_SPI_DUMMY_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_DUMMY_OUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_FADDR_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x20)|value<<5)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_FADDR_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x20) >> 5
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_FADDR_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_FADDR_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_FCMD_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_FCMD_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_FCMD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_FCMD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_FREAD_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x4000)|value<<14)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_FREAD_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x4000) >> 14
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_FREAD_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x8000)|value<<15)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_FREAD_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x8000) >> 15
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_Q_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x40000)|value<<18)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_Q_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x40000) >> 18
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_D_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x80000)|value<<19)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_D_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x80000) >> 19
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_HOLD_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x100000)|value<<20)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_HOLD_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x100000) >> 20
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_WP_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x200000)|value<<21)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_WP_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x200000) >> 21
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_RD_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x1800000)|value<<23)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_RD_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x1800000) >> 23
}
func (o *SPI3_Type) SetSPI_CTRL_SPI_WR_BIT_ORDER(value uint32) {
	volatile.StoreUint32(&o.SPI_CTRL.Reg, volatile.LoadUint32(&o.SPI_CTRL.Reg)&^(0x6000000)|value<<25)
}
func (o *SPI3_Type) GetSPI_CTRL_SPI_WR_BIT_ORDER() uint32 {
	return (volatile.LoadUint32(&o.SPI_CTRL.Reg) & 0x6000000) >> 25
}

// SPI3.SPI_CLOCK: SPI clock control register
func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKCNT_L(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f)|value)
}
func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKCNT_L() uint32 {
	return volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f
}
func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKCNT_H(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0xfc0)|value<<6)
}
func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKCNT_H() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0xfc0) >> 6
}
func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKCNT_N(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3f000)|value<<12)
}
func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKCNT_N() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3f000) >> 12
}
func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLKDIV_PRE(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x3c0000)|value<<18)
}
func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLKDIV_PRE() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x3c0000) >> 18
}
func (o *SPI3_Type) SetSPI_CLOCK_SPI_CLK_EQU_SYSCLK(value uint32) {
	volatile.StoreUint32(&o.SPI_CLOCK.Reg, volatile.LoadUint32(&o.SPI_CLOCK.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI3_Type) GetSPI_CLOCK_SPI_CLK_EQU_SYSCLK() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLOCK.Reg) & 0x80000000) >> 31
}

// SPI3.SPI_USER: SPI USER control register
func (o *SPI3_Type) SetSPI_USER_SPI_DOUTDIN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_USER_SPI_DOUTDIN() uint32 {
	return volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_USER_SPI_QPI_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_USER_SPI_QPI_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_USER_SPI_TSCK_I_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20)|value<<5)
}
func (o *SPI3_Type) GetSPI_USER_SPI_TSCK_I_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20) >> 5
}
func (o *SPI3_Type) SetSPI_USER_SPI_CS_HOLD(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_USER_SPI_CS_HOLD() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_USER_SPI_CS_SETUP(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80)|value<<7)
}
func (o *SPI3_Type) GetSPI_USER_SPI_CS_SETUP() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80) >> 7
}
func (o *SPI3_Type) SetSPI_USER_SPI_RSCK_I_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_USER_SPI_RSCK_I_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_USER_SPI_CK_OUT_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_USER_SPI_CK_OUT_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_USER_SPI_FWRITE_DUAL(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000)|value<<12)
}
func (o *SPI3_Type) GetSPI_USER_SPI_FWRITE_DUAL() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000) >> 12
}
func (o *SPI3_Type) SetSPI_USER_SPI_FWRITE_QUAD(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000)|value<<13)
}
func (o *SPI3_Type) GetSPI_USER_SPI_FWRITE_QUAD() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000) >> 13
}
func (o *SPI3_Type) SetSPI_USER_SPI_SIO(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000)|value<<17)
}
func (o *SPI3_Type) GetSPI_USER_SPI_SIO() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000) >> 17
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_MISO_HIGHPART(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_MISO_HIGHPART() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x1000000) >> 24
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_MOSI_HIGHPART(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x2000000)|value<<25)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_MOSI_HIGHPART() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x2000000) >> 25
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_DUMMY_IDLE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_DUMMY_IDLE() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x4000000) >> 26
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_MOSI(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_MOSI() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x8000000) >> 27
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_MISO(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_MISO() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x10000000) >> 28
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_DUMMY(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_DUMMY() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x20000000) >> 29
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x40000000) >> 30
}
func (o *SPI3_Type) SetSPI_USER_SPI_USR_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_USER.Reg, volatile.LoadUint32(&o.SPI_USER.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI3_Type) GetSPI_USER_SPI_USR_COMMAND() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER.Reg) & 0x80000000) >> 31
}

// SPI3.SPI_USER1: SPI USER control register 1
func (o *SPI3_Type) SetSPI_USER1_SPI_USR_DUMMY_CYCLELEN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xff)|value)
}
func (o *SPI3_Type) GetSPI_USER1_SPI_USR_DUMMY_CYCLELEN() uint32 {
	return volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xff
}
func (o *SPI3_Type) SetSPI_USER1_SPI_MST_WFULL_ERR_END_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x10000)|value<<16)
}
func (o *SPI3_Type) GetSPI_USER1_SPI_MST_WFULL_ERR_END_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x10000) >> 16
}
func (o *SPI3_Type) SetSPI_USER1_SPI_CS_SETUP_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x3e0000)|value<<17)
}
func (o *SPI3_Type) GetSPI_USER1_SPI_CS_SETUP_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x3e0000) >> 17
}
func (o *SPI3_Type) SetSPI_USER1_SPI_CS_HOLD_TIME(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0x7c00000)|value<<22)
}
func (o *SPI3_Type) GetSPI_USER1_SPI_CS_HOLD_TIME() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0x7c00000) >> 22
}
func (o *SPI3_Type) SetSPI_USER1_SPI_USR_ADDR_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER1.Reg, volatile.LoadUint32(&o.SPI_USER1.Reg)&^(0xf8000000)|value<<27)
}
func (o *SPI3_Type) GetSPI_USER1_SPI_USR_ADDR_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER1.Reg) & 0xf8000000) >> 27
}

// SPI3.SPI_USER2: SPI USER control register 2
func (o *SPI3_Type) SetSPI_USER2_SPI_USR_COMMAND_VALUE(value uint32) {
	volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xffff)|value)
}
func (o *SPI3_Type) GetSPI_USER2_SPI_USR_COMMAND_VALUE() uint32 {
	return volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xffff
}
func (o *SPI3_Type) SetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI3_Type) GetSPI_USER2_SPI_MST_REMPTY_ERR_END_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0x8000000) >> 27
}
func (o *SPI3_Type) SetSPI_USER2_SPI_USR_COMMAND_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_USER2.Reg, volatile.LoadUint32(&o.SPI_USER2.Reg)&^(0xf0000000)|value<<28)
}
func (o *SPI3_Type) GetSPI_USER2_SPI_USR_COMMAND_BITLEN() uint32 {
	return (volatile.LoadUint32(&o.SPI_USER2.Reg) & 0xf0000000) >> 28
}

// SPI3.SPI_MS_DLEN: SPI data bit length control register
func (o *SPI3_Type) SetSPI_MS_DLEN_SPI_MS_DATA_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_MS_DLEN.Reg, volatile.LoadUint32(&o.SPI_MS_DLEN.Reg)&^(0x3ffff)|value)
}
func (o *SPI3_Type) GetSPI_MS_DLEN_SPI_MS_DATA_BITLEN() uint32 {
	return volatile.LoadUint32(&o.SPI_MS_DLEN.Reg) & 0x3ffff
}

// SPI3.SPI_MISC: SPI misc register
func (o *SPI3_Type) SetSPI_MISC_SPI_CS0_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_CS0_DIS() uint32 {
	return volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_MISC_SPI_CS1_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_CS1_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_MISC_SPI_CS2_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_CS2_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_MISC_SPI_CK_DIS(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_CK_DIS() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_MISC_SPI_MASTER_CS_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x380)|value<<7)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_MASTER_CS_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x380) >> 7
}
func (o *SPI3_Type) SetSPI_MISC_SPI_SLAVE_CS_POL(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x800000)|value<<23)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_SLAVE_CS_POL() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x800000) >> 23
}
func (o *SPI3_Type) SetSPI_MISC_SPI_CK_IDLE_EDGE(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_CK_IDLE_EDGE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x20000000) >> 29
}
func (o *SPI3_Type) SetSPI_MISC_SPI_CS_KEEP_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_CS_KEEP_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x40000000) >> 30
}
func (o *SPI3_Type) SetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP(value uint32) {
	volatile.StoreUint32(&o.SPI_MISC.Reg, volatile.LoadUint32(&o.SPI_MISC.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI3_Type) GetSPI_MISC_SPI_QUAD_DIN_PIN_SWAP() uint32 {
	return (volatile.LoadUint32(&o.SPI_MISC.Reg) & 0x80000000) >> 31
}

// SPI3.SPI_DIN_MODE: SPI input delay mode configuration
func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x3)|value)
}
func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x3
}
func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc)|value<<2)
}
func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc) >> 2
}
func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x30)|value<<4)
}
func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x30) >> 4
}
func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_DIN3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0xc0)|value<<6)
}
func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_DIN3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0xc0) >> 6
}
func (o *SPI3_Type) SetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_MODE.Reg, volatile.LoadUint32(&o.SPI_DIN_MODE.Reg)&^(0x10000)|value<<16)
}
func (o *SPI3_Type) GetSPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_MODE.Reg) & 0x10000) >> 16
}

// SPI3.SPI_DIN_NUM: SPI input delay number configuration
func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN0_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x3)|value)
}
func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN0_NUM() uint32 {
	return volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x3
}
func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN1_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc)|value<<2)
}
func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN1_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc) >> 2
}
func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN2_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0x30)|value<<4)
}
func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN2_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0x30) >> 4
}
func (o *SPI3_Type) SetSPI_DIN_NUM_SPI_DIN3_NUM(value uint32) {
	volatile.StoreUint32(&o.SPI_DIN_NUM.Reg, volatile.LoadUint32(&o.SPI_DIN_NUM.Reg)&^(0xc0)|value<<6)
}
func (o *SPI3_Type) GetSPI_DIN_NUM_SPI_DIN3_NUM() uint32 {
	return (volatile.LoadUint32(&o.SPI_DIN_NUM.Reg) & 0xc0) >> 6
}

// SPI3.SPI_DOUT_MODE: SPI output delay mode configuration
func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT0_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT0_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT1_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT1_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT2_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT2_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_DOUT_MODE_SPI_DOUT3_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_DOUT_MODE.Reg, volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_DOUT_MODE_SPI_DOUT3_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_DOUT_MODE.Reg) & 0x8) >> 3
}

// SPI3.SPI_DMA_CONF: SPI DMA control register
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_INFIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000)|value<<18)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000) >> 18
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000) >> 19
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x100000) >> 20
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_RX_EOF_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_RX_EOF_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x200000) >> 21
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_RX_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_RX_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x8000000) >> 27
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_TX_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_TX_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x10000000) >> 28
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_RX_AFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_RX_AFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x20000000) >> 29
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_BUF_AFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_BUF_AFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x40000000) >> 30
}
func (o *SPI3_Type) SetSPI_DMA_CONF_SPI_DMA_AFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_CONF.Reg, volatile.LoadUint32(&o.SPI_DMA_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI3_Type) GetSPI_DMA_CONF_SPI_DMA_AFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_CONF.Reg) & 0x80000000) >> 31
}

// SPI3.SPI_DMA_INT_ENA: SPI interrupt enable register
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10) >> 4
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20) >> 5
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80) >> 7
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x400) >> 10
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x800) >> 11
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x1000) >> 12
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x2000) >> 13
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x8000) >> 15
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x10000) >> 16
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x20000) >> 17
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x40000) >> 18
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_APP2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x80000) >> 19
}
func (o *SPI3_Type) SetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ENA.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg)&^(0x100000)|value<<20)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ENA_SPI_APP1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ENA.Reg) & 0x100000) >> 20
}

// SPI3.SPI_DMA_INT_CLR: SPI interrupt clear register
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10) >> 4
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20) >> 5
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80) >> 7
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x400) >> 10
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x800) >> 11
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x1000) >> 12
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x2000) >> 13
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x8000) >> 15
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x10000) >> 16
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x20000) >> 17
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x40000) >> 18
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_APP2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x80000) >> 19
}
func (o *SPI3_Type) SetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_CLR.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg)&^(0x100000)|value<<20)
}
func (o *SPI3_Type) GetSPI_DMA_INT_CLR_SPI_APP1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_CLR.Reg) & 0x100000) >> 20
}

// SPI3.SPI_DMA_INT_RAW: SPI interrupt raw register
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10) >> 4
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20) >> 5
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80) >> 7
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x400) >> 10
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x800) >> 11
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x1000) >> 12
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x2000) >> 13
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x8000) >> 15
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x10000) >> 16
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x20000) >> 17
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x40000) >> 18
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_APP2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x80000) >> 19
}
func (o *SPI3_Type) SetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_RAW.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg)&^(0x100000)|value<<20)
}
func (o *SPI3_Type) GetSPI_DMA_INT_RAW_SPI_APP1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_RAW.Reg) & 0x100000) >> 20
}

// SPI3.SPI_DMA_INT_ST: SPI interrupt status register
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10) >> 4
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20) >> 5
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80) >> 7
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x400) >> 10
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x800) >> 11
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x1000) >> 12
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x2000) >> 13
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x8000) >> 15
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x10000) >> 16
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x20000) >> 17
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x40000) >> 18
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_APP2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_APP2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x80000) >> 19
}
func (o *SPI3_Type) SetSPI_DMA_INT_ST_SPI_APP1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_ST.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg)&^(0x100000)|value<<20)
}
func (o *SPI3_Type) GetSPI_DMA_INT_ST_SPI_APP1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_ST.Reg) & 0x100000) >> 20
}

// SPI3.SPI_DMA_INT_SET: SPI interrupt software set register
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET() uint32 {
	return volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10)|value<<4)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10) >> 4
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20)|value<<5)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20) >> 5
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40)|value<<6)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40) >> 6
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80)|value<<7)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80) >> 7
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x400)|value<<10)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x400) >> 10
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x800)|value<<11)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x800) >> 11
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x1000)|value<<12)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x1000) >> 12
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x2000)|value<<13)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x2000) >> 13
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x8000)|value<<15)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x8000) >> 15
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x10000)|value<<16)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x10000) >> 16
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x20000)|value<<17)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x20000) >> 17
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x40000)|value<<18)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x40000) >> 18
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_APP2_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x80000)|value<<19)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_APP2_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x80000) >> 19
}
func (o *SPI3_Type) SetSPI_DMA_INT_SET_SPI_APP1_INT_SET(value uint32) {
	volatile.StoreUint32(&o.SPI_DMA_INT_SET.Reg, volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg)&^(0x100000)|value<<20)
}
func (o *SPI3_Type) GetSPI_DMA_INT_SET_SPI_APP1_INT_SET() uint32 {
	return (volatile.LoadUint32(&o.SPI_DMA_INT_SET.Reg) & 0x100000) >> 20
}

// SPI3.SPI_W0: SPI CPU-controlled buffer0
func (o *SPI3_Type) SetSPI_W0(value uint32) {
	volatile.StoreUint32(&o.SPI_W0.Reg, value)
}
func (o *SPI3_Type) GetSPI_W0() uint32 {
	return volatile.LoadUint32(&o.SPI_W0.Reg)
}

// SPI3.SPI_W1: SPI CPU-controlled buffer1
func (o *SPI3_Type) SetSPI_W1(value uint32) {
	volatile.StoreUint32(&o.SPI_W1.Reg, value)
}
func (o *SPI3_Type) GetSPI_W1() uint32 {
	return volatile.LoadUint32(&o.SPI_W1.Reg)
}

// SPI3.SPI_W2: SPI CPU-controlled buffer2
func (o *SPI3_Type) SetSPI_W2(value uint32) {
	volatile.StoreUint32(&o.SPI_W2.Reg, value)
}
func (o *SPI3_Type) GetSPI_W2() uint32 {
	return volatile.LoadUint32(&o.SPI_W2.Reg)
}

// SPI3.SPI_W3: SPI CPU-controlled buffer3
func (o *SPI3_Type) SetSPI_W3(value uint32) {
	volatile.StoreUint32(&o.SPI_W3.Reg, value)
}
func (o *SPI3_Type) GetSPI_W3() uint32 {
	return volatile.LoadUint32(&o.SPI_W3.Reg)
}

// SPI3.SPI_W4: SPI CPU-controlled buffer4
func (o *SPI3_Type) SetSPI_W4(value uint32) {
	volatile.StoreUint32(&o.SPI_W4.Reg, value)
}
func (o *SPI3_Type) GetSPI_W4() uint32 {
	return volatile.LoadUint32(&o.SPI_W4.Reg)
}

// SPI3.SPI_W5: SPI CPU-controlled buffer5
func (o *SPI3_Type) SetSPI_W5(value uint32) {
	volatile.StoreUint32(&o.SPI_W5.Reg, value)
}
func (o *SPI3_Type) GetSPI_W5() uint32 {
	return volatile.LoadUint32(&o.SPI_W5.Reg)
}

// SPI3.SPI_W6: SPI CPU-controlled buffer6
func (o *SPI3_Type) SetSPI_W6(value uint32) {
	volatile.StoreUint32(&o.SPI_W6.Reg, value)
}
func (o *SPI3_Type) GetSPI_W6() uint32 {
	return volatile.LoadUint32(&o.SPI_W6.Reg)
}

// SPI3.SPI_W7: SPI CPU-controlled buffer7
func (o *SPI3_Type) SetSPI_W7(value uint32) {
	volatile.StoreUint32(&o.SPI_W7.Reg, value)
}
func (o *SPI3_Type) GetSPI_W7() uint32 {
	return volatile.LoadUint32(&o.SPI_W7.Reg)
}

// SPI3.SPI_W8: SPI CPU-controlled buffer8
func (o *SPI3_Type) SetSPI_W8(value uint32) {
	volatile.StoreUint32(&o.SPI_W8.Reg, value)
}
func (o *SPI3_Type) GetSPI_W8() uint32 {
	return volatile.LoadUint32(&o.SPI_W8.Reg)
}

// SPI3.SPI_W9: SPI CPU-controlled buffer9
func (o *SPI3_Type) SetSPI_W9(value uint32) {
	volatile.StoreUint32(&o.SPI_W9.Reg, value)
}
func (o *SPI3_Type) GetSPI_W9() uint32 {
	return volatile.LoadUint32(&o.SPI_W9.Reg)
}

// SPI3.SPI_W10: SPI CPU-controlled buffer10
func (o *SPI3_Type) SetSPI_W10(value uint32) {
	volatile.StoreUint32(&o.SPI_W10.Reg, value)
}
func (o *SPI3_Type) GetSPI_W10() uint32 {
	return volatile.LoadUint32(&o.SPI_W10.Reg)
}

// SPI3.SPI_W11: SPI CPU-controlled buffer11
func (o *SPI3_Type) SetSPI_W11(value uint32) {
	volatile.StoreUint32(&o.SPI_W11.Reg, value)
}
func (o *SPI3_Type) GetSPI_W11() uint32 {
	return volatile.LoadUint32(&o.SPI_W11.Reg)
}

// SPI3.SPI_W12: SPI CPU-controlled buffer12
func (o *SPI3_Type) SetSPI_W12(value uint32) {
	volatile.StoreUint32(&o.SPI_W12.Reg, value)
}
func (o *SPI3_Type) GetSPI_W12() uint32 {
	return volatile.LoadUint32(&o.SPI_W12.Reg)
}

// SPI3.SPI_W13: SPI CPU-controlled buffer13
func (o *SPI3_Type) SetSPI_W13(value uint32) {
	volatile.StoreUint32(&o.SPI_W13.Reg, value)
}
func (o *SPI3_Type) GetSPI_W13() uint32 {
	return volatile.LoadUint32(&o.SPI_W13.Reg)
}

// SPI3.SPI_W14: SPI CPU-controlled buffer14
func (o *SPI3_Type) SetSPI_W14(value uint32) {
	volatile.StoreUint32(&o.SPI_W14.Reg, value)
}
func (o *SPI3_Type) GetSPI_W14() uint32 {
	return volatile.LoadUint32(&o.SPI_W14.Reg)
}

// SPI3.SPI_W15: SPI CPU-controlled buffer15
func (o *SPI3_Type) SetSPI_W15(value uint32) {
	volatile.StoreUint32(&o.SPI_W15.Reg, value)
}
func (o *SPI3_Type) GetSPI_W15() uint32 {
	return volatile.LoadUint32(&o.SPI_W15.Reg)
}

// SPI3.SPI_SLAVE: SPI slave control register
func (o *SPI3_Type) SetSPI_SLAVE_SPI_CLK_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x3)|value)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_CLK_MODE() uint32 {
	return volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x3
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_CLK_MODE_13(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_CLK_MODE_13() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4) >> 2
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_RSCK_DATA_OUT(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8)|value<<3)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_RSCK_DATA_OUT() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8) >> 3
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x100)|value<<8)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x100) >> 8
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x200)|value<<9)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x200) >> 9
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x400)|value<<10)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x400) >> 10
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x800)|value<<11)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x800) >> 11
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0xff000)|value<<12)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_SLV_LAST_BYTE_STRB() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0xff000) >> 12
}
func (o *SPI3_Type) SetSPI_SLAVE_MODE(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI3_Type) GetSPI_SLAVE_MODE() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x4000000) >> 26
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_SOFT_RESET(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x8000000)|value<<27)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_SOFT_RESET() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x8000000) >> 27
}
func (o *SPI3_Type) SetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE.Reg, volatile.LoadUint32(&o.SPI_SLAVE.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI3_Type) GetSPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE.Reg) & 0x20000000) >> 29
}

// SPI3.SPI_SLAVE1: SPI slave control register 1
func (o *SPI3_Type) SetSPI_SLAVE1_SPI_SLV_DATA_BITLEN(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3ffff)|value)
}
func (o *SPI3_Type) GetSPI_SLAVE1_SPI_SLV_DATA_BITLEN() uint32 {
	return volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3ffff
}
func (o *SPI3_Type) SetSPI_SLAVE1_SPI_SLV_LAST_COMMAND(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0x3fc0000)|value<<18)
}
func (o *SPI3_Type) GetSPI_SLAVE1_SPI_SLV_LAST_COMMAND() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0x3fc0000) >> 18
}
func (o *SPI3_Type) SetSPI_SLAVE1_SPI_SLV_LAST_ADDR(value uint32) {
	volatile.StoreUint32(&o.SPI_SLAVE1.Reg, volatile.LoadUint32(&o.SPI_SLAVE1.Reg)&^(0xfc000000)|value<<26)
}
func (o *SPI3_Type) GetSPI_SLAVE1_SPI_SLV_LAST_ADDR() uint32 {
	return (volatile.LoadUint32(&o.SPI_SLAVE1.Reg) & 0xfc000000) >> 26
}

// SPI3.SPI_CLK_GATE: SPI module clock and register clock control
func (o *SPI3_Type) SetSPI_CLK_GATE_SPI_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x1)|value)
}
func (o *SPI3_Type) GetSPI_CLK_GATE_SPI_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x1
}
func (o *SPI3_Type) SetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x2)|value<<1)
}
func (o *SPI3_Type) GetSPI_CLK_GATE_SPI_MST_CLK_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x2) >> 1
}
func (o *SPI3_Type) SetSPI_CLK_GATE_SPI_MST_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.SPI_CLK_GATE.Reg, volatile.LoadUint32(&o.SPI_CLK_GATE.Reg)&^(0x4)|value<<2)
}
func (o *SPI3_Type) GetSPI_CLK_GATE_SPI_MST_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.SPI_CLK_GATE.Reg) & 0x4) >> 2
}

// SPI3.SPI_DATE: Version control
func (o *SPI3_Type) SetSPI_DATE(value uint32) {
	volatile.StoreUint32(&o.SPI_DATE.Reg, volatile.LoadUint32(&o.SPI_DATE.Reg)&^(0xfffffff)|value)
}
func (o *SPI3_Type) GetSPI_DATE() uint32 {
	return volatile.LoadUint32(&o.SPI_DATE.Reg) & 0xfffffff
}

// System Timer
type SYSTIMER_Type struct {
	CONF            volatile.Register32 // 0x0
	UNIT0_OP        volatile.Register32 // 0x4
	UNIT1_OP        volatile.Register32 // 0x8
	UNIT0_LOAD_HI   volatile.Register32 // 0xC
	UNIT0_LOAD_LO   volatile.Register32 // 0x10
	UNIT1_LOAD_HI   volatile.Register32 // 0x14
	UNIT1_LOAD_LO   volatile.Register32 // 0x18
	TARGET0_HI      volatile.Register32 // 0x1C
	TARGET0_LO      volatile.Register32 // 0x20
	TARGET1_HI      volatile.Register32 // 0x24
	TARGET1_LO      volatile.Register32 // 0x28
	TARGET2_HI      volatile.Register32 // 0x2C
	TARGET2_LO      volatile.Register32 // 0x30
	TARGET0_CONF    volatile.Register32 // 0x34
	TARGET1_CONF    volatile.Register32 // 0x38
	TARGET2_CONF    volatile.Register32 // 0x3C
	UNIT0_VALUE_HI  volatile.Register32 // 0x40
	UNIT0_VALUE_LO  volatile.Register32 // 0x44
	UNIT1_VALUE_HI  volatile.Register32 // 0x48
	UNIT1_VALUE_LO  volatile.Register32 // 0x4C
	COMP0_LOAD      volatile.Register32 // 0x50
	COMP1_LOAD      volatile.Register32 // 0x54
	COMP2_LOAD      volatile.Register32 // 0x58
	UNIT0_LOAD      volatile.Register32 // 0x5C
	UNIT1_LOAD      volatile.Register32 // 0x60
	INT_ENA         volatile.Register32 // 0x64
	INT_RAW         volatile.Register32 // 0x68
	INT_CLR         volatile.Register32 // 0x6C
	INT_ST          volatile.Register32 // 0x70
	REAL_TARGET0_LO volatile.Register32 // 0x74
	REAL_TARGET0_HI volatile.Register32 // 0x78
	REAL_TARGET1_LO volatile.Register32 // 0x7C
	REAL_TARGET1_HI volatile.Register32 // 0x80
	REAL_TARGET2_LO volatile.Register32 // 0x84
	REAL_TARGET2_HI volatile.Register32 // 0x88
	_               [112]byte
	DATE            volatile.Register32 // 0xFC
}

// SYSTIMER.CONF: Configure system timer clock
func (o *SYSTIMER_Type) SetCONF_SYSTIMER_CLK_FO(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetCONF_SYSTIMER_CLK_FO() uint32 {
	return volatile.LoadUint32(&o.CONF.Reg) & 0x1
}
func (o *SYSTIMER_Type) SetCONF_ETM_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1)
}
func (o *SYSTIMER_Type) GetCONF_ETM_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1
}
func (o *SYSTIMER_Type) SetCONF_TARGET2_WORK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x400000)|value<<22)
}
func (o *SYSTIMER_Type) GetCONF_TARGET2_WORK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x400000) >> 22
}
func (o *SYSTIMER_Type) SetCONF_TARGET1_WORK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x800000)|value<<23)
}
func (o *SYSTIMER_Type) GetCONF_TARGET1_WORK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x800000) >> 23
}
func (o *SYSTIMER_Type) SetCONF_TARGET0_WORK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *SYSTIMER_Type) GetCONF_TARGET0_WORK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x1000000) >> 24
}
func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE1_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE1_STALL_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000000) >> 25
}
func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_CORE0_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_CORE0_STALL_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x4000000) >> 26
}
func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE1_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000000)|value<<27)
}
func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE1_STALL_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000000) >> 27
}
func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_CORE0_STALL_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_CORE0_STALL_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x10000000) >> 28
}
func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT1_WORK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT1_WORK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000000) >> 29
}
func (o *SYSTIMER_Type) SetCONF_TIMER_UNIT0_WORK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTIMER_Type) GetCONF_TIMER_UNIT0_WORK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000000) >> 30
}
func (o *SYSTIMER_Type) SetCONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTIMER_Type) GetCONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000000) >> 31
}

// SYSTIMER.UNIT0_OP: system timer unit0 value update register
func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_VALUE_VALID(value uint32) {
	volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_VALUE_VALID() uint32 {
	return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x20000000) >> 29
}
func (o *SYSTIMER_Type) SetUNIT0_OP_TIMER_UNIT0_UPDATE(value uint32) {
	volatile.StoreUint32(&o.UNIT0_OP.Reg, volatile.LoadUint32(&o.UNIT0_OP.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTIMER_Type) GetUNIT0_OP_TIMER_UNIT0_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.UNIT0_OP.Reg) & 0x40000000) >> 30
}

// SYSTIMER.UNIT1_OP: system timer unit1 value update register
func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_VALUE_VALID(value uint32) {
	volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_VALUE_VALID() uint32 {
	return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x20000000) >> 29
}
func (o *SYSTIMER_Type) SetUNIT1_OP_TIMER_UNIT1_UPDATE(value uint32) {
	volatile.StoreUint32(&o.UNIT1_OP.Reg, volatile.LoadUint32(&o.UNIT1_OP.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTIMER_Type) GetUNIT1_OP_TIMER_UNIT1_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.UNIT1_OP.Reg) & 0x40000000) >> 30
}

// SYSTIMER.UNIT0_LOAD_HI: system timer unit0 value high load register
func (o *SYSTIMER_Type) SetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI(value uint32) {
	volatile.StoreUint32(&o.UNIT0_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetUNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI() uint32 {
	return volatile.LoadUint32(&o.UNIT0_LOAD_HI.Reg) & 0xfffff
}

// SYSTIMER.UNIT0_LOAD_LO: system timer unit0 value low load register
func (o *SYSTIMER_Type) SetUNIT0_LOAD_LO(value uint32) {
	volatile.StoreUint32(&o.UNIT0_LOAD_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetUNIT0_LOAD_LO() uint32 {
	return volatile.LoadUint32(&o.UNIT0_LOAD_LO.Reg)
}

// SYSTIMER.UNIT1_LOAD_HI: system timer unit1 value high load register
func (o *SYSTIMER_Type) SetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI(value uint32) {
	volatile.StoreUint32(&o.UNIT1_LOAD_HI.Reg, volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetUNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI() uint32 {
	return volatile.LoadUint32(&o.UNIT1_LOAD_HI.Reg) & 0xfffff
}

// SYSTIMER.UNIT1_LOAD_LO: system timer unit1 value low load register
func (o *SYSTIMER_Type) SetUNIT1_LOAD_LO(value uint32) {
	volatile.StoreUint32(&o.UNIT1_LOAD_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetUNIT1_LOAD_LO() uint32 {
	return volatile.LoadUint32(&o.UNIT1_LOAD_LO.Reg)
}

// SYSTIMER.TARGET0_HI: system timer comp0 value high register
func (o *SYSTIMER_Type) SetTARGET0_HI_TIMER_TARGET0_HI(value uint32) {
	volatile.StoreUint32(&o.TARGET0_HI.Reg, volatile.LoadUint32(&o.TARGET0_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetTARGET0_HI_TIMER_TARGET0_HI() uint32 {
	return volatile.LoadUint32(&o.TARGET0_HI.Reg) & 0xfffff
}

// SYSTIMER.TARGET0_LO: system timer comp0 value low register
func (o *SYSTIMER_Type) SetTARGET0_LO(value uint32) {
	volatile.StoreUint32(&o.TARGET0_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetTARGET0_LO() uint32 {
	return volatile.LoadUint32(&o.TARGET0_LO.Reg)
}

// SYSTIMER.TARGET1_HI: system timer comp1 value high register
func (o *SYSTIMER_Type) SetTARGET1_HI_TIMER_TARGET1_HI(value uint32) {
	volatile.StoreUint32(&o.TARGET1_HI.Reg, volatile.LoadUint32(&o.TARGET1_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetTARGET1_HI_TIMER_TARGET1_HI() uint32 {
	return volatile.LoadUint32(&o.TARGET1_HI.Reg) & 0xfffff
}

// SYSTIMER.TARGET1_LO: system timer comp1 value low register
func (o *SYSTIMER_Type) SetTARGET1_LO(value uint32) {
	volatile.StoreUint32(&o.TARGET1_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetTARGET1_LO() uint32 {
	return volatile.LoadUint32(&o.TARGET1_LO.Reg)
}

// SYSTIMER.TARGET2_HI: system timer comp2 value high register
func (o *SYSTIMER_Type) SetTARGET2_HI_TIMER_TARGET2_HI(value uint32) {
	volatile.StoreUint32(&o.TARGET2_HI.Reg, volatile.LoadUint32(&o.TARGET2_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetTARGET2_HI_TIMER_TARGET2_HI() uint32 {
	return volatile.LoadUint32(&o.TARGET2_HI.Reg) & 0xfffff
}

// SYSTIMER.TARGET2_LO: system timer comp2 value low register
func (o *SYSTIMER_Type) SetTARGET2_LO(value uint32) {
	volatile.StoreUint32(&o.TARGET2_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetTARGET2_LO() uint32 {
	return volatile.LoadUint32(&o.TARGET2_LO.Reg)
}

// SYSTIMER.TARGET0_CONF: system timer comp0 target mode register
func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD(value uint32) {
	volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x3ffffff)|value)
}
func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD() uint32 {
	return volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x3ffffff
}
func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_PERIOD_MODE(value uint32) {
	volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_PERIOD_MODE() uint32 {
	return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x40000000) >> 30
}
func (o *SYSTIMER_Type) SetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL(value uint32) {
	volatile.StoreUint32(&o.TARGET0_CONF.Reg, volatile.LoadUint32(&o.TARGET0_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTIMER_Type) GetTARGET0_CONF_TARGET0_TIMER_UNIT_SEL() uint32 {
	return (volatile.LoadUint32(&o.TARGET0_CONF.Reg) & 0x80000000) >> 31
}

// SYSTIMER.TARGET1_CONF: system timer comp1 target mode register
func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD(value uint32) {
	volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x3ffffff)|value)
}
func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD() uint32 {
	return volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x3ffffff
}
func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_PERIOD_MODE(value uint32) {
	volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_PERIOD_MODE() uint32 {
	return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x40000000) >> 30
}
func (o *SYSTIMER_Type) SetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL(value uint32) {
	volatile.StoreUint32(&o.TARGET1_CONF.Reg, volatile.LoadUint32(&o.TARGET1_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTIMER_Type) GetTARGET1_CONF_TARGET1_TIMER_UNIT_SEL() uint32 {
	return (volatile.LoadUint32(&o.TARGET1_CONF.Reg) & 0x80000000) >> 31
}

// SYSTIMER.TARGET2_CONF: system timer comp2 target mode register
func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD(value uint32) {
	volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x3ffffff)|value)
}
func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD() uint32 {
	return volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x3ffffff
}
func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_PERIOD_MODE(value uint32) {
	volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_PERIOD_MODE() uint32 {
	return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x40000000) >> 30
}
func (o *SYSTIMER_Type) SetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL(value uint32) {
	volatile.StoreUint32(&o.TARGET2_CONF.Reg, volatile.LoadUint32(&o.TARGET2_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTIMER_Type) GetTARGET2_CONF_TARGET2_TIMER_UNIT_SEL() uint32 {
	return (volatile.LoadUint32(&o.TARGET2_CONF.Reg) & 0x80000000) >> 31
}

// SYSTIMER.UNIT0_VALUE_HI: system timer unit0 value high register
func (o *SYSTIMER_Type) SetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI(value uint32) {
	volatile.StoreUint32(&o.UNIT0_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetUNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI() uint32 {
	return volatile.LoadUint32(&o.UNIT0_VALUE_HI.Reg) & 0xfffff
}

// SYSTIMER.UNIT0_VALUE_LO: system timer unit0 value low register
func (o *SYSTIMER_Type) SetUNIT0_VALUE_LO(value uint32) {
	volatile.StoreUint32(&o.UNIT0_VALUE_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetUNIT0_VALUE_LO() uint32 {
	return volatile.LoadUint32(&o.UNIT0_VALUE_LO.Reg)
}

// SYSTIMER.UNIT1_VALUE_HI: system timer unit1 value high register
func (o *SYSTIMER_Type) SetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI(value uint32) {
	volatile.StoreUint32(&o.UNIT1_VALUE_HI.Reg, volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetUNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI() uint32 {
	return volatile.LoadUint32(&o.UNIT1_VALUE_HI.Reg) & 0xfffff
}

// SYSTIMER.UNIT1_VALUE_LO: system timer unit1 value low register
func (o *SYSTIMER_Type) SetUNIT1_VALUE_LO(value uint32) {
	volatile.StoreUint32(&o.UNIT1_VALUE_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetUNIT1_VALUE_LO() uint32 {
	return volatile.LoadUint32(&o.UNIT1_VALUE_LO.Reg)
}

// SYSTIMER.COMP0_LOAD: system timer comp0 conf sync register
func (o *SYSTIMER_Type) SetCOMP0_LOAD_TIMER_COMP0_LOAD(value uint32) {
	volatile.StoreUint32(&o.COMP0_LOAD.Reg, volatile.LoadUint32(&o.COMP0_LOAD.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetCOMP0_LOAD_TIMER_COMP0_LOAD() uint32 {
	return volatile.LoadUint32(&o.COMP0_LOAD.Reg) & 0x1
}

// SYSTIMER.COMP1_LOAD: system timer comp1 conf sync register
func (o *SYSTIMER_Type) SetCOMP1_LOAD_TIMER_COMP1_LOAD(value uint32) {
	volatile.StoreUint32(&o.COMP1_LOAD.Reg, volatile.LoadUint32(&o.COMP1_LOAD.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetCOMP1_LOAD_TIMER_COMP1_LOAD() uint32 {
	return volatile.LoadUint32(&o.COMP1_LOAD.Reg) & 0x1
}

// SYSTIMER.COMP2_LOAD: system timer comp2 conf sync register
func (o *SYSTIMER_Type) SetCOMP2_LOAD_TIMER_COMP2_LOAD(value uint32) {
	volatile.StoreUint32(&o.COMP2_LOAD.Reg, volatile.LoadUint32(&o.COMP2_LOAD.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetCOMP2_LOAD_TIMER_COMP2_LOAD() uint32 {
	return volatile.LoadUint32(&o.COMP2_LOAD.Reg) & 0x1
}

// SYSTIMER.UNIT0_LOAD: system timer unit0 conf sync register
func (o *SYSTIMER_Type) SetUNIT0_LOAD_TIMER_UNIT0_LOAD(value uint32) {
	volatile.StoreUint32(&o.UNIT0_LOAD.Reg, volatile.LoadUint32(&o.UNIT0_LOAD.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetUNIT0_LOAD_TIMER_UNIT0_LOAD() uint32 {
	return volatile.LoadUint32(&o.UNIT0_LOAD.Reg) & 0x1
}

// SYSTIMER.UNIT1_LOAD: system timer unit1 conf sync register
func (o *SYSTIMER_Type) SetUNIT1_LOAD_TIMER_UNIT1_LOAD(value uint32) {
	volatile.StoreUint32(&o.UNIT1_LOAD.Reg, volatile.LoadUint32(&o.UNIT1_LOAD.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetUNIT1_LOAD_TIMER_UNIT1_LOAD() uint32 {
	return volatile.LoadUint32(&o.UNIT1_LOAD.Reg) & 0x1
}

// SYSTIMER.INT_ENA: systimer interrupt enable register
func (o *SYSTIMER_Type) SetINT_ENA_TARGET0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetINT_ENA_TARGET0_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *SYSTIMER_Type) SetINT_ENA_TARGET1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *SYSTIMER_Type) GetINT_ENA_TARGET1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *SYSTIMER_Type) SetINT_ENA_TARGET2_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *SYSTIMER_Type) GetINT_ENA_TARGET2_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}

// SYSTIMER.INT_RAW: systimer interrupt raw register
func (o *SYSTIMER_Type) SetINT_RAW_TARGET0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetINT_RAW_TARGET0_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *SYSTIMER_Type) SetINT_RAW_TARGET1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *SYSTIMER_Type) GetINT_RAW_TARGET1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *SYSTIMER_Type) SetINT_RAW_TARGET2_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *SYSTIMER_Type) GetINT_RAW_TARGET2_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}

// SYSTIMER.INT_CLR: systimer interrupt clear register
func (o *SYSTIMER_Type) SetINT_CLR_TARGET0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetINT_CLR_TARGET0_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *SYSTIMER_Type) SetINT_CLR_TARGET1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTIMER_Type) GetINT_CLR_TARGET1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *SYSTIMER_Type) SetINT_CLR_TARGET2_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *SYSTIMER_Type) GetINT_CLR_TARGET2_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}

// SYSTIMER.INT_ST: systimer interrupt status register
func (o *SYSTIMER_Type) SetINT_ST_TARGET0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *SYSTIMER_Type) GetINT_ST_TARGET0_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *SYSTIMER_Type) SetINT_ST_TARGET1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *SYSTIMER_Type) GetINT_ST_TARGET1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *SYSTIMER_Type) SetINT_ST_TARGET2_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *SYSTIMER_Type) GetINT_ST_TARGET2_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}

// SYSTIMER.REAL_TARGET0_LO: system timer comp0 actual target value low register
func (o *SYSTIMER_Type) SetREAL_TARGET0_LO(value uint32) {
	volatile.StoreUint32(&o.REAL_TARGET0_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetREAL_TARGET0_LO() uint32 {
	return volatile.LoadUint32(&o.REAL_TARGET0_LO.Reg)
}

// SYSTIMER.REAL_TARGET0_HI: system timer comp0 actual target value high register
func (o *SYSTIMER_Type) SetREAL_TARGET0_HI_TARGET0_HI_RO(value uint32) {
	volatile.StoreUint32(&o.REAL_TARGET0_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetREAL_TARGET0_HI_TARGET0_HI_RO() uint32 {
	return volatile.LoadUint32(&o.REAL_TARGET0_HI.Reg) & 0xfffff
}

// SYSTIMER.REAL_TARGET1_LO: system timer comp1 actual target value low register
func (o *SYSTIMER_Type) SetREAL_TARGET1_LO(value uint32) {
	volatile.StoreUint32(&o.REAL_TARGET1_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetREAL_TARGET1_LO() uint32 {
	return volatile.LoadUint32(&o.REAL_TARGET1_LO.Reg)
}

// SYSTIMER.REAL_TARGET1_HI: system timer comp1 actual target value high register
func (o *SYSTIMER_Type) SetREAL_TARGET1_HI_TARGET1_HI_RO(value uint32) {
	volatile.StoreUint32(&o.REAL_TARGET1_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetREAL_TARGET1_HI_TARGET1_HI_RO() uint32 {
	return volatile.LoadUint32(&o.REAL_TARGET1_HI.Reg) & 0xfffff
}

// SYSTIMER.REAL_TARGET2_LO: system timer comp2 actual target value low register
func (o *SYSTIMER_Type) SetREAL_TARGET2_LO(value uint32) {
	volatile.StoreUint32(&o.REAL_TARGET2_LO.Reg, value)
}
func (o *SYSTIMER_Type) GetREAL_TARGET2_LO() uint32 {
	return volatile.LoadUint32(&o.REAL_TARGET2_LO.Reg)
}

// SYSTIMER.REAL_TARGET2_HI: system timer comp2 actual target value high register
func (o *SYSTIMER_Type) SetREAL_TARGET2_HI_TARGET2_HI_RO(value uint32) {
	volatile.StoreUint32(&o.REAL_TARGET2_HI.Reg, volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg)&^(0xfffff)|value)
}
func (o *SYSTIMER_Type) GetREAL_TARGET2_HI_TARGET2_HI_RO() uint32 {
	return volatile.LoadUint32(&o.REAL_TARGET2_HI.Reg) & 0xfffff
}

// SYSTIMER.DATE: system timer version control register
func (o *SYSTIMER_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *SYSTIMER_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// Timer Group 0
type TIMG_Type struct {
	T0CONFIG       volatile.Register32 // 0x0
	T0LO           volatile.Register32 // 0x4
	T0HI           volatile.Register32 // 0x8
	T0UPDATE       volatile.Register32 // 0xC
	T0ALARMLO      volatile.Register32 // 0x10
	T0ALARMHI      volatile.Register32 // 0x14
	T0LOADLO       volatile.Register32 // 0x18
	T0LOADHI       volatile.Register32 // 0x1C
	T0LOAD         volatile.Register32 // 0x20
	_              [36]byte
	WDTCONFIG0     volatile.Register32 // 0x48
	WDTCONFIG1     volatile.Register32 // 0x4C
	WDTCONFIG2     volatile.Register32 // 0x50
	WDTCONFIG3     volatile.Register32 // 0x54
	WDTCONFIG4     volatile.Register32 // 0x58
	WDTCONFIG5     volatile.Register32 // 0x5C
	WDTFEED        volatile.Register32 // 0x60
	WDTWPROTECT    volatile.Register32 // 0x64
	RTCCALICFG     volatile.Register32 // 0x68
	RTCCALICFG1    volatile.Register32 // 0x6C
	INT_ENA_TIMERS volatile.Register32 // 0x70
	INT_RAW_TIMERS volatile.Register32 // 0x74
	INT_ST_TIMERS  volatile.Register32 // 0x78
	INT_CLR_TIMERS volatile.Register32 // 0x7C
	RTCCALICFG2    volatile.Register32 // 0x80
	_              [116]byte
	NTIMERS_DATE   volatile.Register32 // 0xF8
	REGCLK         volatile.Register32 // 0xFC
}

// TIMG.T0CONFIG: Timer %s configuration register
func (o *TIMG_Type) SetT0CONFIG_USE_XTAL(value uint32) {
	volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x200)|value<<9)
}
func (o *TIMG_Type) GetT0CONFIG_USE_XTAL() uint32 {
	return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x200) >> 9
}
func (o *TIMG_Type) SetT0CONFIG_ALARM_EN(value uint32) {
	volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x400)|value<<10)
}
func (o *TIMG_Type) GetT0CONFIG_ALARM_EN() uint32 {
	return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x400) >> 10
}
func (o *TIMG_Type) SetT0CONFIG_DIVCNT_RST(value uint32) {
	volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1000)|value<<12)
}
func (o *TIMG_Type) GetT0CONFIG_DIVCNT_RST() uint32 {
	return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1000) >> 12
}
func (o *TIMG_Type) SetT0CONFIG_DIVIDER(value uint32) {
	volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x1fffe000)|value<<13)
}
func (o *TIMG_Type) GetT0CONFIG_DIVIDER() uint32 {
	return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x1fffe000) >> 13
}
func (o *TIMG_Type) SetT0CONFIG_AUTORELOAD(value uint32) {
	volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x20000000)|value<<29)
}
func (o *TIMG_Type) GetT0CONFIG_AUTORELOAD() uint32 {
	return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x20000000) >> 29
}
func (o *TIMG_Type) SetT0CONFIG_INCREASE(value uint32) {
	volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x40000000)|value<<30)
}
func (o *TIMG_Type) GetT0CONFIG_INCREASE() uint32 {
	return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x40000000) >> 30
}
func (o *TIMG_Type) SetT0CONFIG_EN(value uint32) {
	volatile.StoreUint32(&o.T0CONFIG.Reg, volatile.LoadUint32(&o.T0CONFIG.Reg)&^(0x80000000)|value<<31)
}
func (o *TIMG_Type) GetT0CONFIG_EN() uint32 {
	return (volatile.LoadUint32(&o.T0CONFIG.Reg) & 0x80000000) >> 31
}

// TIMG.T0LO: Timer %s current value, low 32 bits
func (o *TIMG_Type) SetT0LO(value uint32) {
	volatile.StoreUint32(&o.T0LO.Reg, value)
}
func (o *TIMG_Type) GetT0LO() uint32 {
	return volatile.LoadUint32(&o.T0LO.Reg)
}

// TIMG.T0HI: Timer %s current value, high 22 bits
func (o *TIMG_Type) SetT0HI_HI(value uint32) {
	volatile.StoreUint32(&o.T0HI.Reg, volatile.LoadUint32(&o.T0HI.Reg)&^(0x3fffff)|value)
}
func (o *TIMG_Type) GetT0HI_HI() uint32 {
	return volatile.LoadUint32(&o.T0HI.Reg) & 0x3fffff
}

// TIMG.T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG
func (o *TIMG_Type) SetT0UPDATE_UPDATE(value uint32) {
	volatile.StoreUint32(&o.T0UPDATE.Reg, volatile.LoadUint32(&o.T0UPDATE.Reg)&^(0x80000000)|value<<31)
}
func (o *TIMG_Type) GetT0UPDATE_UPDATE() uint32 {
	return (volatile.LoadUint32(&o.T0UPDATE.Reg) & 0x80000000) >> 31
}

// TIMG.T0ALARMLO: Timer %s alarm value, low 32 bits
func (o *TIMG_Type) SetT0ALARMLO(value uint32) {
	volatile.StoreUint32(&o.T0ALARMLO.Reg, value)
}
func (o *TIMG_Type) GetT0ALARMLO() uint32 {
	return volatile.LoadUint32(&o.T0ALARMLO.Reg)
}

// TIMG.T0ALARMHI: Timer %s alarm value, high bits
func (o *TIMG_Type) SetT0ALARMHI_ALARM_HI(value uint32) {
	volatile.StoreUint32(&o.T0ALARMHI.Reg, volatile.LoadUint32(&o.T0ALARMHI.Reg)&^(0x3fffff)|value)
}
func (o *TIMG_Type) GetT0ALARMHI_ALARM_HI() uint32 {
	return volatile.LoadUint32(&o.T0ALARMHI.Reg) & 0x3fffff
}

// TIMG.T0LOADLO: Timer %s reload value, low 32 bits
func (o *TIMG_Type) SetT0LOADLO(value uint32) {
	volatile.StoreUint32(&o.T0LOADLO.Reg, value)
}
func (o *TIMG_Type) GetT0LOADLO() uint32 {
	return volatile.LoadUint32(&o.T0LOADLO.Reg)
}

// TIMG.T0LOADHI: Timer %s reload value, high 22 bits
func (o *TIMG_Type) SetT0LOADHI_LOAD_HI(value uint32) {
	volatile.StoreUint32(&o.T0LOADHI.Reg, volatile.LoadUint32(&o.T0LOADHI.Reg)&^(0x3fffff)|value)
}
func (o *TIMG_Type) GetT0LOADHI_LOAD_HI() uint32 {
	return volatile.LoadUint32(&o.T0LOADHI.Reg) & 0x3fffff
}

// TIMG.T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG
func (o *TIMG_Type) SetT0LOAD(value uint32) {
	volatile.StoreUint32(&o.T0LOAD.Reg, value)
}
func (o *TIMG_Type) GetT0LOAD() uint32 {
	return volatile.LoadUint32(&o.T0LOAD.Reg)
}

// TIMG.WDTCONFIG0: Watchdog timer configuration register
func (o *TIMG_Type) SetWDTCONFIG0_WDT_APPCPU_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1000)|value<<12)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_APPCPU_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1000) >> 12
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_PROCPU_RESET_EN(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x2000)|value<<13)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_PROCPU_RESET_EN() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x2000) >> 13
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x4000)|value<<14)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_FLASHBOOT_MOD_EN() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x4000) >> 14
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_SYS_RESET_LENGTH(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x38000)|value<<15)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_SYS_RESET_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x38000) >> 15
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_CPU_RESET_LENGTH(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1c0000)|value<<18)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_CPU_RESET_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1c0000) >> 18
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_USE_XTAL(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x200000)|value<<21)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_USE_XTAL() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x200000) >> 21
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_CONF_UPDATE_EN(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x400000)|value<<22)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_CONF_UPDATE_EN() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x400000) >> 22
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG3(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x1800000)|value<<23)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG3() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x1800000) >> 23
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG2(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x6000000)|value<<25)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG2() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x6000000) >> 25
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG1(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x18000000)|value<<27)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG1() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x18000000) >> 27
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_STG0(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x60000000)|value<<29)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_STG0() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x60000000) >> 29
}
func (o *TIMG_Type) SetWDTCONFIG0_WDT_EN(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG0.Reg, volatile.LoadUint32(&o.WDTCONFIG0.Reg)&^(0x80000000)|value<<31)
}
func (o *TIMG_Type) GetWDTCONFIG0_WDT_EN() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG0.Reg) & 0x80000000) >> 31
}

// TIMG.WDTCONFIG1: Watchdog timer prescaler register
func (o *TIMG_Type) SetWDTCONFIG1_WDT_DIVCNT_RST(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0x1)|value)
}
func (o *TIMG_Type) GetWDTCONFIG1_WDT_DIVCNT_RST() uint32 {
	return volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0x1
}
func (o *TIMG_Type) SetWDTCONFIG1_WDT_CLK_PRESCALE(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG1.Reg, volatile.LoadUint32(&o.WDTCONFIG1.Reg)&^(0xffff0000)|value<<16)
}
func (o *TIMG_Type) GetWDTCONFIG1_WDT_CLK_PRESCALE() uint32 {
	return (volatile.LoadUint32(&o.WDTCONFIG1.Reg) & 0xffff0000) >> 16
}

// TIMG.WDTCONFIG2: Watchdog timer stage 0 timeout value
func (o *TIMG_Type) SetWDTCONFIG2(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG2.Reg, value)
}
func (o *TIMG_Type) GetWDTCONFIG2() uint32 {
	return volatile.LoadUint32(&o.WDTCONFIG2.Reg)
}

// TIMG.WDTCONFIG3: Watchdog timer stage 1 timeout value
func (o *TIMG_Type) SetWDTCONFIG3(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG3.Reg, value)
}
func (o *TIMG_Type) GetWDTCONFIG3() uint32 {
	return volatile.LoadUint32(&o.WDTCONFIG3.Reg)
}

// TIMG.WDTCONFIG4: Watchdog timer stage 2 timeout value
func (o *TIMG_Type) SetWDTCONFIG4(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG4.Reg, value)
}
func (o *TIMG_Type) GetWDTCONFIG4() uint32 {
	return volatile.LoadUint32(&o.WDTCONFIG4.Reg)
}

// TIMG.WDTCONFIG5: Watchdog timer stage 3 timeout value
func (o *TIMG_Type) SetWDTCONFIG5(value uint32) {
	volatile.StoreUint32(&o.WDTCONFIG5.Reg, value)
}
func (o *TIMG_Type) GetWDTCONFIG5() uint32 {
	return volatile.LoadUint32(&o.WDTCONFIG5.Reg)
}

// TIMG.WDTFEED: Write to feed the watchdog timer
func (o *TIMG_Type) SetWDTFEED(value uint32) {
	volatile.StoreUint32(&o.WDTFEED.Reg, value)
}
func (o *TIMG_Type) GetWDTFEED() uint32 {
	return volatile.LoadUint32(&o.WDTFEED.Reg)
}

// TIMG.WDTWPROTECT: Watchdog write protect register
func (o *TIMG_Type) SetWDTWPROTECT(value uint32) {
	volatile.StoreUint32(&o.WDTWPROTECT.Reg, value)
}
func (o *TIMG_Type) GetWDTWPROTECT() uint32 {
	return volatile.LoadUint32(&o.WDTWPROTECT.Reg)
}

// TIMG.RTCCALICFG: RTC calibration configure register
func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START_CYCLING(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x1000)|value<<12)
}
func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START_CYCLING() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x1000) >> 12
}
func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_CLK_SEL(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x6000)|value<<13)
}
func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_CLK_SEL() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x6000) >> 13
}
func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_RDY(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x8000)|value<<15)
}
func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_RDY() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x8000) >> 15
}
func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_MAX(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x7fff0000)|value<<16)
}
func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_MAX() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x7fff0000) >> 16
}
func (o *TIMG_Type) SetRTCCALICFG_RTC_CALI_START(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG.Reg, volatile.LoadUint32(&o.RTCCALICFG.Reg)&^(0x80000000)|value<<31)
}
func (o *TIMG_Type) GetRTCCALICFG_RTC_CALI_START() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG.Reg) & 0x80000000) >> 31
}

// TIMG.RTCCALICFG1: RTC calibration configure1 register
func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0x1)|value)
}
func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD() uint32 {
	return volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0x1
}
func (o *TIMG_Type) SetRTCCALICFG1_RTC_CALI_VALUE(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG1.Reg, volatile.LoadUint32(&o.RTCCALICFG1.Reg)&^(0xffffff80)|value<<7)
}
func (o *TIMG_Type) GetRTCCALICFG1_RTC_CALI_VALUE() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG1.Reg) & 0xffffff80) >> 7
}

// TIMG.INT_ENA_TIMERS: Interrupt enable bits
func (o *TIMG_Type) SetINT_ENA_TIMERS_T0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x1)|value)
}
func (o *TIMG_Type) GetINT_ENA_TIMERS_T0_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x1
}
func (o *TIMG_Type) SetINT_ENA_TIMERS_T1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x2)|value<<1)
}
func (o *TIMG_Type) GetINT_ENA_TIMERS_T1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x2) >> 1
}
func (o *TIMG_Type) SetINT_ENA_TIMERS_WDT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_TIMERS.Reg, volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg)&^(0x4)|value<<2)
}
func (o *TIMG_Type) GetINT_ENA_TIMERS_WDT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA_TIMERS.Reg) & 0x4) >> 2
}

// TIMG.INT_RAW_TIMERS: Raw interrupt status
func (o *TIMG_Type) SetINT_RAW_TIMERS_T0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x1)|value)
}
func (o *TIMG_Type) GetINT_RAW_TIMERS_T0_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x1
}
func (o *TIMG_Type) SetINT_RAW_TIMERS_T1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x2)|value<<1)
}
func (o *TIMG_Type) GetINT_RAW_TIMERS_T1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x2) >> 1
}
func (o *TIMG_Type) SetINT_RAW_TIMERS_WDT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW_TIMERS.Reg, volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg)&^(0x4)|value<<2)
}
func (o *TIMG_Type) GetINT_RAW_TIMERS_WDT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW_TIMERS.Reg) & 0x4) >> 2
}

// TIMG.INT_ST_TIMERS: Masked interrupt status
func (o *TIMG_Type) SetINT_ST_TIMERS_T0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x1)|value)
}
func (o *TIMG_Type) GetINT_ST_TIMERS_T0_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x1
}
func (o *TIMG_Type) SetINT_ST_TIMERS_T1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x2)|value<<1)
}
func (o *TIMG_Type) GetINT_ST_TIMERS_T1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x2) >> 1
}
func (o *TIMG_Type) SetINT_ST_TIMERS_WDT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST_TIMERS.Reg, volatile.LoadUint32(&o.INT_ST_TIMERS.Reg)&^(0x4)|value<<2)
}
func (o *TIMG_Type) GetINT_ST_TIMERS_WDT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST_TIMERS.Reg) & 0x4) >> 2
}

// TIMG.INT_CLR_TIMERS: Interrupt clear bits
func (o *TIMG_Type) SetINT_CLR_TIMERS_T0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x1)|value)
}
func (o *TIMG_Type) GetINT_CLR_TIMERS_T0_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x1
}
func (o *TIMG_Type) SetINT_CLR_TIMERS_T1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x2)|value<<1)
}
func (o *TIMG_Type) GetINT_CLR_TIMERS_T1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x2) >> 1
}
func (o *TIMG_Type) SetINT_CLR_TIMERS_WDT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR_TIMERS.Reg, volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg)&^(0x4)|value<<2)
}
func (o *TIMG_Type) GetINT_CLR_TIMERS_WDT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR_TIMERS.Reg) & 0x4) >> 2
}

// TIMG.RTCCALICFG2: Timer group calibration register
func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x1)|value)
}
func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT() uint32 {
	return volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x1
}
func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0x78)|value<<3)
}
func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0x78) >> 3
}
func (o *TIMG_Type) SetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES(value uint32) {
	volatile.StoreUint32(&o.RTCCALICFG2.Reg, volatile.LoadUint32(&o.RTCCALICFG2.Reg)&^(0xffffff80)|value<<7)
}
func (o *TIMG_Type) GetRTCCALICFG2_RTC_CALI_TIMEOUT_THRES() uint32 {
	return (volatile.LoadUint32(&o.RTCCALICFG2.Reg) & 0xffffff80) >> 7
}

// TIMG.NTIMERS_DATE: Timer version control register
func (o *TIMG_Type) SetNTIMERS_DATE_NTIMGS_DATE(value uint32) {
	volatile.StoreUint32(&o.NTIMERS_DATE.Reg, volatile.LoadUint32(&o.NTIMERS_DATE.Reg)&^(0xfffffff)|value)
}
func (o *TIMG_Type) GetNTIMERS_DATE_NTIMGS_DATE() uint32 {
	return volatile.LoadUint32(&o.NTIMERS_DATE.Reg) & 0xfffffff
}

// TIMG.REGCLK: Timer group clock gate register
func (o *TIMG_Type) SetREGCLK_ETM_EN(value uint32) {
	volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x10000000)|value<<28)
}
func (o *TIMG_Type) GetREGCLK_ETM_EN() uint32 {
	return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x10000000) >> 28
}
func (o *TIMG_Type) SetREGCLK_WDT_CLK_IS_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x20000000)|value<<29)
}
func (o *TIMG_Type) GetREGCLK_WDT_CLK_IS_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x20000000) >> 29
}
func (o *TIMG_Type) SetREGCLK_TIMER_CLK_IS_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x40000000)|value<<30)
}
func (o *TIMG_Type) GetREGCLK_TIMER_CLK_IS_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x40000000) >> 30
}
func (o *TIMG_Type) SetREGCLK_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.REGCLK.Reg, volatile.LoadUint32(&o.REGCLK.Reg)&^(0x80000000)|value<<31)
}
func (o *TIMG_Type) GetREGCLK_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.REGCLK.Reg) & 0x80000000) >> 31
}

// TRACE0 Peripheral
type TRACE_Type struct {
	MEM_START_ADDR            volatile.Register32 // 0x0
	MEM_END_ADDR              volatile.Register32 // 0x4
	MEM_CURRENT_ADDR          volatile.Register32 // 0x8
	MEM_ADDR_UPDATE           volatile.Register32 // 0xC
	FIFO_STATUS               volatile.Register32 // 0x10
	INTR_ENA                  volatile.Register32 // 0x14
	INTR_RAW                  volatile.Register32 // 0x18
	INTR_CLR                  volatile.Register32 // 0x1C
	TRIGGER                   volatile.Register32 // 0x20
	CONFIG                    volatile.Register32 // 0x24
	FILTER_CONTROL            volatile.Register32 // 0x28
	FILTER_MATCH_CONTROL      volatile.Register32 // 0x2C
	FILTER_COMPARATOR_CONTROL volatile.Register32 // 0x30
	FILTER_P_COMPARATOR_MATCH volatile.Register32 // 0x34
	FILTER_S_COMPARATOR_MATCH volatile.Register32 // 0x38
	RESYNC_PROLONGED          volatile.Register32 // 0x3C
	AHB_CONFIG                volatile.Register32 // 0x40
	CLOCK_GATE                volatile.Register32 // 0x44
	_                         [948]byte
	DATE                      volatile.Register32 // 0x3FC
}

// TRACE.MEM_START_ADDR: mem start addr
func (o *TRACE_Type) SetMEM_START_ADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_START_ADDR.Reg, value)
}
func (o *TRACE_Type) GetMEM_START_ADDR() uint32 {
	return volatile.LoadUint32(&o.MEM_START_ADDR.Reg)
}

// TRACE.MEM_END_ADDR: mem end addr
func (o *TRACE_Type) SetMEM_END_ADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_END_ADDR.Reg, value)
}
func (o *TRACE_Type) GetMEM_END_ADDR() uint32 {
	return volatile.LoadUint32(&o.MEM_END_ADDR.Reg)
}

// TRACE.MEM_CURRENT_ADDR: mem current addr
func (o *TRACE_Type) SetMEM_CURRENT_ADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_CURRENT_ADDR.Reg, value)
}
func (o *TRACE_Type) GetMEM_CURRENT_ADDR() uint32 {
	return volatile.LoadUint32(&o.MEM_CURRENT_ADDR.Reg)
}

// TRACE.MEM_ADDR_UPDATE: mem addr update
func (o *TRACE_Type) SetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE(value uint32) {
	volatile.StoreUint32(&o.MEM_ADDR_UPDATE.Reg, volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetMEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE() uint32 {
	return volatile.LoadUint32(&o.MEM_ADDR_UPDATE.Reg) & 0x1
}

// TRACE.FIFO_STATUS: fifo status register
func (o *TRACE_Type) SetFIFO_STATUS_FIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetFIFO_STATUS_FIFO_EMPTY() uint32 {
	return volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x1
}
func (o *TRACE_Type) SetFIFO_STATUS_WORK_STATUS(value uint32) {
	volatile.StoreUint32(&o.FIFO_STATUS.Reg, volatile.LoadUint32(&o.FIFO_STATUS.Reg)&^(0x6)|value<<1)
}
func (o *TRACE_Type) GetFIFO_STATUS_WORK_STATUS() uint32 {
	return (volatile.LoadUint32(&o.FIFO_STATUS.Reg) & 0x6) >> 1
}

// TRACE.INTR_ENA: interrupt enable register
func (o *TRACE_Type) SetINTR_ENA_FIFO_OVERFLOW_INTR_ENA(value uint32) {
	volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetINTR_ENA_FIFO_OVERFLOW_INTR_ENA() uint32 {
	return volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x1
}
func (o *TRACE_Type) SetINTR_ENA_MEM_FULL_INTR_ENA(value uint32) {
	volatile.StoreUint32(&o.INTR_ENA.Reg, volatile.LoadUint32(&o.INTR_ENA.Reg)&^(0x2)|value<<1)
}
func (o *TRACE_Type) GetINTR_ENA_MEM_FULL_INTR_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTR_ENA.Reg) & 0x2) >> 1
}

// TRACE.INTR_RAW: interrupt status register
func (o *TRACE_Type) SetINTR_RAW_FIFO_OVERFLOW_INTR_RAW(value uint32) {
	volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetINTR_RAW_FIFO_OVERFLOW_INTR_RAW() uint32 {
	return volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x1
}
func (o *TRACE_Type) SetINTR_RAW_MEM_FULL_INTR_RAW(value uint32) {
	volatile.StoreUint32(&o.INTR_RAW.Reg, volatile.LoadUint32(&o.INTR_RAW.Reg)&^(0x2)|value<<1)
}
func (o *TRACE_Type) GetINTR_RAW_MEM_FULL_INTR_RAW() uint32 {
	return (volatile.LoadUint32(&o.INTR_RAW.Reg) & 0x2) >> 1
}

// TRACE.INTR_CLR: interrupt clear register
func (o *TRACE_Type) SetINTR_CLR_FIFO_OVERFLOW_INTR_CLR(value uint32) {
	volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetINTR_CLR_FIFO_OVERFLOW_INTR_CLR() uint32 {
	return volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x1
}
func (o *TRACE_Type) SetINTR_CLR_MEM_FULL_INTR_CLR(value uint32) {
	volatile.StoreUint32(&o.INTR_CLR.Reg, volatile.LoadUint32(&o.INTR_CLR.Reg)&^(0x2)|value<<1)
}
func (o *TRACE_Type) GetINTR_CLR_MEM_FULL_INTR_CLR() uint32 {
	return (volatile.LoadUint32(&o.INTR_CLR.Reg) & 0x2) >> 1
}

// TRACE.TRIGGER: trigger register
func (o *TRACE_Type) SetTRIGGER_ON(value uint32) {
	volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetTRIGGER_ON() uint32 {
	return volatile.LoadUint32(&o.TRIGGER.Reg) & 0x1
}
func (o *TRACE_Type) SetTRIGGER_OFF(value uint32) {
	volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x2)|value<<1)
}
func (o *TRACE_Type) GetTRIGGER_OFF() uint32 {
	return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x2) >> 1
}
func (o *TRACE_Type) SetTRIGGER_MEM_LOOP(value uint32) {
	volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x4)|value<<2)
}
func (o *TRACE_Type) GetTRIGGER_MEM_LOOP() uint32 {
	return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x4) >> 2
}
func (o *TRACE_Type) SetTRIGGER_RESTART_ENA(value uint32) {
	volatile.StoreUint32(&o.TRIGGER.Reg, volatile.LoadUint32(&o.TRIGGER.Reg)&^(0x8)|value<<3)
}
func (o *TRACE_Type) GetTRIGGER_RESTART_ENA() uint32 {
	return (volatile.LoadUint32(&o.TRIGGER.Reg) & 0x8) >> 3
}

// TRACE.CONFIG: trace configuration register
func (o *TRACE_Type) SetCONFIG_DM_TRIGGER_ENA(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetCONFIG_DM_TRIGGER_ENA() uint32 {
	return volatile.LoadUint32(&o.CONFIG.Reg) & 0x1
}
func (o *TRACE_Type) SetCONFIG_RESET_ENA(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *TRACE_Type) GetCONFIG_RESET_ENA() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2) >> 1
}
func (o *TRACE_Type) SetCONFIG_HALT_ENA(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4)|value<<2)
}
func (o *TRACE_Type) GetCONFIG_HALT_ENA() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4) >> 2
}
func (o *TRACE_Type) SetCONFIG_STALL_ENA(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x8)|value<<3)
}
func (o *TRACE_Type) GetCONFIG_STALL_ENA() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x8) >> 3
}
func (o *TRACE_Type) SetCONFIG_FULL_ADDRESS(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x10)|value<<4)
}
func (o *TRACE_Type) GetCONFIG_FULL_ADDRESS() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x10) >> 4
}
func (o *TRACE_Type) SetCONFIG_IMPLICIT_EXCEPT(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x20)|value<<5)
}
func (o *TRACE_Type) GetCONFIG_IMPLICIT_EXCEPT() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x20) >> 5
}

// TRACE.FILTER_CONTROL: filter control register
func (o *TRACE_Type) SetFILTER_CONTROL_FILTER_EN(value uint32) {
	volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetFILTER_CONTROL_FILTER_EN() uint32 {
	return volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x1
}
func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_COMP(value uint32) {
	volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x2)|value<<1)
}
func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_COMP() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x2) >> 1
}
func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_PRIVILEGE(value uint32) {
	volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x4)|value<<2)
}
func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_PRIVILEGE() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x4) >> 2
}
func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_ECAUSE(value uint32) {
	volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x8)|value<<3)
}
func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_ECAUSE() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x8) >> 3
}
func (o *TRACE_Type) SetFILTER_CONTROL_MATCH_INTERRUPT(value uint32) {
	volatile.StoreUint32(&o.FILTER_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_CONTROL.Reg)&^(0x10)|value<<4)
}
func (o *TRACE_Type) GetFILTER_CONTROL_MATCH_INTERRUPT() uint32 {
	return (volatile.LoadUint32(&o.FILTER_CONTROL.Reg) & 0x10) >> 4
}

// TRACE.FILTER_MATCH_CONTROL: filter match control register
func (o *TRACE_Type) SetFILTER_MATCH_CONTROL_MATCH_CHOICE_PRIVILEGE(value uint32) {
	volatile.StoreUint32(&o.FILTER_MATCH_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetFILTER_MATCH_CONTROL_MATCH_CHOICE_PRIVILEGE() uint32 {
	return volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg) & 0x1
}
func (o *TRACE_Type) SetFILTER_MATCH_CONTROL_MATCH_VALUE_INTERRUPT(value uint32) {
	volatile.StoreUint32(&o.FILTER_MATCH_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg)&^(0x2)|value<<1)
}
func (o *TRACE_Type) GetFILTER_MATCH_CONTROL_MATCH_VALUE_INTERRUPT() uint32 {
	return (volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg) & 0x2) >> 1
}
func (o *TRACE_Type) SetFILTER_MATCH_CONTROL_MATCH_CHOICE_ECAUSE(value uint32) {
	volatile.StoreUint32(&o.FILTER_MATCH_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg)&^(0xfc)|value<<2)
}
func (o *TRACE_Type) GetFILTER_MATCH_CONTROL_MATCH_CHOICE_ECAUSE() uint32 {
	return (volatile.LoadUint32(&o.FILTER_MATCH_CONTROL.Reg) & 0xfc) >> 2
}

// TRACE.FILTER_COMPARATOR_CONTROL: filter comparator match control register
func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_P_INPUT(value uint32) {
	volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_P_INPUT() uint32 {
	return volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x1
}
func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_P_FUNCTION(value uint32) {
	volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x1c)|value<<2)
}
func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_P_FUNCTION() uint32 {
	return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x1c) >> 2
}
func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_P_NOTIFY(value uint32) {
	volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x20)|value<<5)
}
func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_P_NOTIFY() uint32 {
	return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x20) >> 5
}
func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_S_INPUT(value uint32) {
	volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x100)|value<<8)
}
func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_S_INPUT() uint32 {
	return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x100) >> 8
}
func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_S_FUNCTION(value uint32) {
	volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x1c00)|value<<10)
}
func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_S_FUNCTION() uint32 {
	return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x1c00) >> 10
}
func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_S_NOTIFY(value uint32) {
	volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x2000)|value<<13)
}
func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_S_NOTIFY() uint32 {
	return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x2000) >> 13
}
func (o *TRACE_Type) SetFILTER_COMPARATOR_CONTROL_MATCH_MODE(value uint32) {
	volatile.StoreUint32(&o.FILTER_COMPARATOR_CONTROL.Reg, volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg)&^(0x30000)|value<<16)
}
func (o *TRACE_Type) GetFILTER_COMPARATOR_CONTROL_MATCH_MODE() uint32 {
	return (volatile.LoadUint32(&o.FILTER_COMPARATOR_CONTROL.Reg) & 0x30000) >> 16
}

// TRACE.FILTER_P_COMPARATOR_MATCH: primary comparator match value
func (o *TRACE_Type) SetFILTER_P_COMPARATOR_MATCH(value uint32) {
	volatile.StoreUint32(&o.FILTER_P_COMPARATOR_MATCH.Reg, value)
}
func (o *TRACE_Type) GetFILTER_P_COMPARATOR_MATCH() uint32 {
	return volatile.LoadUint32(&o.FILTER_P_COMPARATOR_MATCH.Reg)
}

// TRACE.FILTER_S_COMPARATOR_MATCH: secondary comparator match value
func (o *TRACE_Type) SetFILTER_S_COMPARATOR_MATCH(value uint32) {
	volatile.StoreUint32(&o.FILTER_S_COMPARATOR_MATCH.Reg, value)
}
func (o *TRACE_Type) GetFILTER_S_COMPARATOR_MATCH() uint32 {
	return volatile.LoadUint32(&o.FILTER_S_COMPARATOR_MATCH.Reg)
}

// TRACE.RESYNC_PROLONGED: resync configuration register
func (o *TRACE_Type) SetRESYNC_PROLONGED(value uint32) {
	volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0xffffff)|value)
}
func (o *TRACE_Type) GetRESYNC_PROLONGED() uint32 {
	return volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0xffffff
}
func (o *TRACE_Type) SetRESYNC_PROLONGED_RESYNC_MODE(value uint32) {
	volatile.StoreUint32(&o.RESYNC_PROLONGED.Reg, volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg)&^(0x3000000)|value<<24)
}
func (o *TRACE_Type) GetRESYNC_PROLONGED_RESYNC_MODE() uint32 {
	return (volatile.LoadUint32(&o.RESYNC_PROLONGED.Reg) & 0x3000000) >> 24
}

// TRACE.AHB_CONFIG: AHB config register
func (o *TRACE_Type) SetAHB_CONFIG_HBURST(value uint32) {
	volatile.StoreUint32(&o.AHB_CONFIG.Reg, volatile.LoadUint32(&o.AHB_CONFIG.Reg)&^(0x7)|value)
}
func (o *TRACE_Type) GetAHB_CONFIG_HBURST() uint32 {
	return volatile.LoadUint32(&o.AHB_CONFIG.Reg) & 0x7
}
func (o *TRACE_Type) SetAHB_CONFIG_MAX_INCR(value uint32) {
	volatile.StoreUint32(&o.AHB_CONFIG.Reg, volatile.LoadUint32(&o.AHB_CONFIG.Reg)&^(0x38)|value<<3)
}
func (o *TRACE_Type) GetAHB_CONFIG_MAX_INCR() uint32 {
	return (volatile.LoadUint32(&o.AHB_CONFIG.Reg) & 0x38) >> 3
}

// TRACE.CLOCK_GATE: Clock gate control register
func (o *TRACE_Type) SetCLOCK_GATE_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLOCK_GATE.Reg, volatile.LoadUint32(&o.CLOCK_GATE.Reg)&^(0x1)|value)
}
func (o *TRACE_Type) GetCLOCK_GATE_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLOCK_GATE.Reg) & 0x1
}

// TRACE.DATE: Version control register
func (o *TRACE_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, volatile.LoadUint32(&o.DATE.Reg)&^(0xfffffff)|value)
}
func (o *TRACE_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg) & 0xfffffff
}

// Low-power Temperature Sensor
type TSENS_Type struct {
	CTRL         volatile.Register32 // 0x0
	CTRL2        volatile.Register32 // 0x4
	INT_RAW      volatile.Register32 // 0x8
	INT_ST       volatile.Register32 // 0xC
	INT_ENA      volatile.Register32 // 0x10
	INT_CLR      volatile.Register32 // 0x14
	CLK_CONF     volatile.Register32 // 0x18
	INT_ENA_W1TS volatile.Register32 // 0x1C
	INT_ENA_W1TC volatile.Register32 // 0x20
	WAKEUP_CTRL  volatile.Register32 // 0x24
	SAMPLE_RATE  volatile.Register32 // 0x28
	RND_ECO_LOW  volatile.Register32 // 0x2C
	RND_ECO_HIGH volatile.Register32 // 0x30
	RND_ECO_CS   volatile.Register32 // 0x34
}

// TSENS.CTRL: Tsens configuration.
func (o *TSENS_Type) SetCTRL_OUT(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0xff)|value)
}
func (o *TSENS_Type) GetCTRL_OUT() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0xff
}
func (o *TSENS_Type) SetCTRL_READY(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x100)|value<<8)
}
func (o *TSENS_Type) GetCTRL_READY() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x100) >> 8
}
func (o *TSENS_Type) SetCTRL_SAMPLE_EN(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x200)|value<<9)
}
func (o *TSENS_Type) GetCTRL_SAMPLE_EN() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x200) >> 9
}
func (o *TSENS_Type) SetCTRL_WAKEUP_MASK(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400)|value<<10)
}
func (o *TSENS_Type) GetCTRL_WAKEUP_MASK() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400) >> 10
}
func (o *TSENS_Type) SetCTRL_INT_EN(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1000)|value<<12)
}
func (o *TSENS_Type) GetCTRL_INT_EN() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x1000) >> 12
}
func (o *TSENS_Type) SetCTRL_IN_INV(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2000)|value<<13)
}
func (o *TSENS_Type) GetCTRL_IN_INV() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2000) >> 13
}
func (o *TSENS_Type) SetCTRL_CLK_DIV(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x3fc000)|value<<14)
}
func (o *TSENS_Type) GetCTRL_CLK_DIV() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x3fc000) >> 14
}
func (o *TSENS_Type) SetCTRL_POWER_UP(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x400000)|value<<22)
}
func (o *TSENS_Type) GetCTRL_POWER_UP() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x400000) >> 22
}
func (o *TSENS_Type) SetCTRL_POWER_UP_FORCE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x800000)|value<<23)
}
func (o *TSENS_Type) GetCTRL_POWER_UP_FORCE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x800000) >> 23
}

// TSENS.CTRL2: Tsens configuration.
func (o *TSENS_Type) SetCTRL2_XPD_WAIT(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0xfff)|value)
}
func (o *TSENS_Type) GetCTRL2_XPD_WAIT() uint32 {
	return volatile.LoadUint32(&o.CTRL2.Reg) & 0xfff
}
func (o *TSENS_Type) SetCTRL2_XPD_FORCE(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x3000)|value<<12)
}
func (o *TSENS_Type) GetCTRL2_XPD_FORCE() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x3000) >> 12
}
func (o *TSENS_Type) SetCTRL2_CLK_INV(value uint32) {
	volatile.StoreUint32(&o.CTRL2.Reg, volatile.LoadUint32(&o.CTRL2.Reg)&^(0x4000)|value<<14)
}
func (o *TSENS_Type) GetCTRL2_CLK_INV() uint32 {
	return (volatile.LoadUint32(&o.CTRL2.Reg) & 0x4000) >> 14
}

// TSENS.INT_RAW: Tsens interrupt raw registers.
func (o *TSENS_Type) SetINT_RAW_COCPU_TSENS_WAKE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetINT_RAW_COCPU_TSENS_WAKE_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}

// TSENS.INT_ST: Tsens interrupt status registers.
func (o *TSENS_Type) SetINT_ST_COCPU_TSENS_WAKE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetINT_ST_COCPU_TSENS_WAKE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}

// TSENS.INT_ENA: Tsens interrupt enable registers.
func (o *TSENS_Type) SetINT_ENA_COCPU_TSENS_WAKE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetINT_ENA_COCPU_TSENS_WAKE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}

// TSENS.INT_CLR: Tsens interrupt clear registers.
func (o *TSENS_Type) SetINT_CLR_COCPU_TSENS_WAKE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetINT_CLR_COCPU_TSENS_WAKE_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}

// TSENS.CLK_CONF: Tsens regbank configuration registers.
func (o *TSENS_Type) SetCLK_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetCLK_CONF_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1
}

// TSENS.INT_ENA_W1TS: Tsens wakeup interrupt enable assert.
func (o *TSENS_Type) SetINT_ENA_W1TS_COCPU_TSENS_WAKE_INT_ENA_W1TS(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TS.Reg, volatile.LoadUint32(&o.INT_ENA_W1TS.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetINT_ENA_W1TS_COCPU_TSENS_WAKE_INT_ENA_W1TS() uint32 {
	return volatile.LoadUint32(&o.INT_ENA_W1TS.Reg) & 0x1
}

// TSENS.INT_ENA_W1TC: Tsens wakeup interrupt enable deassert.
func (o *TSENS_Type) SetINT_ENA_W1TC_COCPU_TSENS_WAKE_INT_ENA_W1TC(value uint32) {
	volatile.StoreUint32(&o.INT_ENA_W1TC.Reg, volatile.LoadUint32(&o.INT_ENA_W1TC.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetINT_ENA_W1TC_COCPU_TSENS_WAKE_INT_ENA_W1TC() uint32 {
	return volatile.LoadUint32(&o.INT_ENA_W1TC.Reg) & 0x1
}

// TSENS.WAKEUP_CTRL: Tsens wakeup control registers.
func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_TH_LOW(value uint32) {
	volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0xff)|value)
}
func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_TH_LOW() uint32 {
	return volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0xff
}
func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_TH_HIGH(value uint32) {
	volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x3fc000)|value<<14)
}
func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_TH_HIGH() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x3fc000) >> 14
}
func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_OVER_UPPER_TH(value uint32) {
	volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x20000000)|value<<29)
}
func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_OVER_UPPER_TH() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x20000000) >> 29
}
func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x40000000)|value<<30)
}
func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x40000000) >> 30
}
func (o *TSENS_Type) SetWAKEUP_CTRL_WAKEUP_MODE(value uint32) {
	volatile.StoreUint32(&o.WAKEUP_CTRL.Reg, volatile.LoadUint32(&o.WAKEUP_CTRL.Reg)&^(0x80000000)|value<<31)
}
func (o *TSENS_Type) GetWAKEUP_CTRL_WAKEUP_MODE() uint32 {
	return (volatile.LoadUint32(&o.WAKEUP_CTRL.Reg) & 0x80000000) >> 31
}

// TSENS.SAMPLE_RATE: Hardware automatic sampling control registers.
func (o *TSENS_Type) SetSAMPLE_RATE(value uint32) {
	volatile.StoreUint32(&o.SAMPLE_RATE.Reg, volatile.LoadUint32(&o.SAMPLE_RATE.Reg)&^(0xffff)|value)
}
func (o *TSENS_Type) GetSAMPLE_RATE() uint32 {
	return volatile.LoadUint32(&o.SAMPLE_RATE.Reg) & 0xffff
}

// TSENS.RND_ECO_LOW: N/A
func (o *TSENS_Type) SetRND_ECO_LOW(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_LOW.Reg, value)
}
func (o *TSENS_Type) GetRND_ECO_LOW() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_LOW.Reg)
}

// TSENS.RND_ECO_HIGH: N/A
func (o *TSENS_Type) SetRND_ECO_HIGH(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_HIGH.Reg, value)
}
func (o *TSENS_Type) GetRND_ECO_HIGH() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_HIGH.Reg)
}

// TSENS.RND_ECO_CS: N/A
func (o *TSENS_Type) SetRND_ECO_CS_RND_ECO_EN(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x1)|value)
}
func (o *TSENS_Type) GetRND_ECO_CS_RND_ECO_EN() uint32 {
	return volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x1
}
func (o *TSENS_Type) SetRND_ECO_CS_RND_ECO_RESULT(value uint32) {
	volatile.StoreUint32(&o.RND_ECO_CS.Reg, volatile.LoadUint32(&o.RND_ECO_CS.Reg)&^(0x2)|value<<1)
}
func (o *TSENS_Type) GetRND_ECO_CS_RND_ECO_RESULT() uint32 {
	return (volatile.LoadUint32(&o.RND_ECO_CS.Reg) & 0x2) >> 1
}

// Two-Wire Automotive Interface
type TWAI_Type struct {
	MODE                volatile.Register32 // 0x0
	CMD                 volatile.Register32 // 0x4
	STATUS              volatile.Register32 // 0x8
	INTERRUPT           volatile.Register32 // 0xC
	INTERRUPT_ENABLE    volatile.Register32 // 0x10
	_                   [4]byte
	BUS_TIMING_0        volatile.Register32 // 0x18
	BUS_TIMING_1        volatile.Register32 // 0x1C
	_                   [12]byte
	ARB_LOST_CAP        volatile.Register32 // 0x2C
	ERR_CODE_CAP        volatile.Register32 // 0x30
	ERR_WARNING_LIMIT   volatile.Register32 // 0x34
	RX_ERR_CNT          volatile.Register32 // 0x38
	TX_ERR_CNT          volatile.Register32 // 0x3C
	DATA_0              volatile.Register32 // 0x40
	DATA_1              volatile.Register32 // 0x44
	DATA_2              volatile.Register32 // 0x48
	DATA_3              volatile.Register32 // 0x4C
	DATA_4              volatile.Register32 // 0x50
	DATA_5              volatile.Register32 // 0x54
	DATA_6              volatile.Register32 // 0x58
	DATA_7              volatile.Register32 // 0x5C
	DATA_8              volatile.Register32 // 0x60
	DATA_9              volatile.Register32 // 0x64
	DATA_10             volatile.Register32 // 0x68
	DATA_11             volatile.Register32 // 0x6C
	DATA_12             volatile.Register32 // 0x70
	RX_MESSAGE_COUNTER  volatile.Register32 // 0x74
	_                   [4]byte
	CLOCK_DIVIDER       volatile.Register32 // 0x7C
	SW_STANDBY_CFG      volatile.Register32 // 0x80
	HW_CFG              volatile.Register32 // 0x84
	HW_STANDBY_CNT      volatile.Register32 // 0x88
	IDLE_INTR_CNT       volatile.Register32 // 0x8C
	ECO_CFG             volatile.Register32 // 0x90
	TIMESTAMP_DATA      volatile.Register32 // 0x94
	TIMESTAMP_PRESCALER volatile.Register32 // 0x98
	TIMESTAMP_CFG       volatile.Register32 // 0x9C
}

// TWAI.MODE: TWAI mode register.
func (o *TWAI_Type) SetMODE_RESET_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetMODE_RESET_MODE() uint32 {
	return volatile.LoadUint32(&o.MODE.Reg) & 0x1
}
func (o *TWAI_Type) SetMODE_LISTEN_ONLY_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x2)|value<<1)
}
func (o *TWAI_Type) GetMODE_LISTEN_ONLY_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE.Reg) & 0x2) >> 1
}
func (o *TWAI_Type) SetMODE_SELF_TEST_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x4)|value<<2)
}
func (o *TWAI_Type) GetMODE_SELF_TEST_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE.Reg) & 0x4) >> 2
}
func (o *TWAI_Type) SetMODE_ACCEPTANCE_FILTER_MODE(value uint32) {
	volatile.StoreUint32(&o.MODE.Reg, volatile.LoadUint32(&o.MODE.Reg)&^(0x8)|value<<3)
}
func (o *TWAI_Type) GetMODE_ACCEPTANCE_FILTER_MODE() uint32 {
	return (volatile.LoadUint32(&o.MODE.Reg) & 0x8) >> 3
}

// TWAI.CMD: TWAI command register.
func (o *TWAI_Type) SetCMD_TX_REQUEST(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetCMD_TX_REQUEST() uint32 {
	return volatile.LoadUint32(&o.CMD.Reg) & 0x1
}
func (o *TWAI_Type) SetCMD_ABORT_TX(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x2)|value<<1)
}
func (o *TWAI_Type) GetCMD_ABORT_TX() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x2) >> 1
}
func (o *TWAI_Type) SetCMD_RELEASE_BUFFER(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x4)|value<<2)
}
func (o *TWAI_Type) GetCMD_RELEASE_BUFFER() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x4) >> 2
}
func (o *TWAI_Type) SetCMD_CLEAR_DATA_OVERRUN(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x8)|value<<3)
}
func (o *TWAI_Type) GetCMD_CLEAR_DATA_OVERRUN() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x8) >> 3
}
func (o *TWAI_Type) SetCMD_SELF_RX_REQUEST(value uint32) {
	volatile.StoreUint32(&o.CMD.Reg, volatile.LoadUint32(&o.CMD.Reg)&^(0x10)|value<<4)
}
func (o *TWAI_Type) GetCMD_SELF_RX_REQUEST() uint32 {
	return (volatile.LoadUint32(&o.CMD.Reg) & 0x10) >> 4
}

// TWAI.STATUS: TWAI status register.
func (o *TWAI_Type) SetSTATUS_RECEIVE_BUFFER(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetSTATUS_RECEIVE_BUFFER() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg) & 0x1
}
func (o *TWAI_Type) SetSTATUS_OVERRUN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2)|value<<1)
}
func (o *TWAI_Type) GetSTATUS_OVERRUN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2) >> 1
}
func (o *TWAI_Type) SetSTATUS_TRANSMIT_BUFFER(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4)|value<<2)
}
func (o *TWAI_Type) GetSTATUS_TRANSMIT_BUFFER() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4) >> 2
}
func (o *TWAI_Type) SetSTATUS_TRANSMISSION_COMPLETE(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8)|value<<3)
}
func (o *TWAI_Type) GetSTATUS_TRANSMISSION_COMPLETE() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8) >> 3
}
func (o *TWAI_Type) SetSTATUS_RECEIVE(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x10)|value<<4)
}
func (o *TWAI_Type) GetSTATUS_RECEIVE() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x10) >> 4
}
func (o *TWAI_Type) SetSTATUS_TRANSMIT(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20)|value<<5)
}
func (o *TWAI_Type) GetSTATUS_TRANSMIT() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20) >> 5
}
func (o *TWAI_Type) SetSTATUS_ERR(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40)|value<<6)
}
func (o *TWAI_Type) GetSTATUS_ERR() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40) >> 6
}
func (o *TWAI_Type) SetSTATUS_NODE_BUS_OFF(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80)|value<<7)
}
func (o *TWAI_Type) GetSTATUS_NODE_BUS_OFF() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80) >> 7
}
func (o *TWAI_Type) SetSTATUS_MISS(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x100)|value<<8)
}
func (o *TWAI_Type) GetSTATUS_MISS() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x100) >> 8
}

// TWAI.INTERRUPT: Interrupt signals' register.
func (o *TWAI_Type) SetINTERRUPT_RECEIVE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetINTERRUPT_RECEIVE_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x1
}
func (o *TWAI_Type) SetINTERRUPT_TRANSMIT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x2)|value<<1)
}
func (o *TWAI_Type) GetINTERRUPT_TRANSMIT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x2) >> 1
}
func (o *TWAI_Type) SetINTERRUPT_ERR_WARNING_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x4)|value<<2)
}
func (o *TWAI_Type) GetINTERRUPT_ERR_WARNING_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x4) >> 2
}
func (o *TWAI_Type) SetINTERRUPT_DATA_OVERRUN_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x8)|value<<3)
}
func (o *TWAI_Type) GetINTERRUPT_DATA_OVERRUN_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x8) >> 3
}
func (o *TWAI_Type) SetINTERRUPT_TS_COUNTER_OVFL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x10)|value<<4)
}
func (o *TWAI_Type) GetINTERRUPT_TS_COUNTER_OVFL_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x10) >> 4
}
func (o *TWAI_Type) SetINTERRUPT_ERR_PASSIVE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x20)|value<<5)
}
func (o *TWAI_Type) GetINTERRUPT_ERR_PASSIVE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x20) >> 5
}
func (o *TWAI_Type) SetINTERRUPT_ARBITRATION_LOST_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x40)|value<<6)
}
func (o *TWAI_Type) GetINTERRUPT_ARBITRATION_LOST_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x40) >> 6
}
func (o *TWAI_Type) SetINTERRUPT_BUS_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x80)|value<<7)
}
func (o *TWAI_Type) GetINTERRUPT_BUS_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x80) >> 7
}
func (o *TWAI_Type) SetINTERRUPT_IDLE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT.Reg, volatile.LoadUint32(&o.INTERRUPT.Reg)&^(0x100)|value<<8)
}
func (o *TWAI_Type) GetINTERRUPT_IDLE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT.Reg) & 0x100) >> 8
}

// TWAI.INTERRUPT_ENABLE: Interrupt enable register.
func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x1
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x2)|value<<1)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x2) >> 1
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x4)|value<<2)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x4) >> 2
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x8)|value<<3)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x8) >> 3
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_TS_COUNTER_OVFL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x10)|value<<4)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_TS_COUNTER_OVFL_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x10) >> 4
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x20)|value<<5)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x20) >> 5
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x40)|value<<6)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x40) >> 6
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_BUS_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x80)|value<<7)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_BUS_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x80) >> 7
}
func (o *TWAI_Type) SetINTERRUPT_ENABLE_IDLE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT_ENABLE.Reg, volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg)&^(0x100)|value<<8)
}
func (o *TWAI_Type) GetINTERRUPT_ENABLE_IDLE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT_ENABLE.Reg) & 0x100) >> 8
}

// TWAI.BUS_TIMING_0: Bit timing configuration register 0.
func (o *TWAI_Type) SetBUS_TIMING_0_BAUD_PRESC(value uint32) {
	volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0x3fff)|value)
}
func (o *TWAI_Type) GetBUS_TIMING_0_BAUD_PRESC() uint32 {
	return volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0x3fff
}
func (o *TWAI_Type) SetBUS_TIMING_0_SYNC_JUMP_WIDTH(value uint32) {
	volatile.StoreUint32(&o.BUS_TIMING_0.Reg, volatile.LoadUint32(&o.BUS_TIMING_0.Reg)&^(0xc000)|value<<14)
}
func (o *TWAI_Type) GetBUS_TIMING_0_SYNC_JUMP_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.BUS_TIMING_0.Reg) & 0xc000) >> 14
}

// TWAI.BUS_TIMING_1: Bit timing configuration register 1.
func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEGMENT1(value uint32) {
	volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0xf)|value)
}
func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEGMENT1() uint32 {
	return volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0xf
}
func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SEGMENT2(value uint32) {
	volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x70)|value<<4)
}
func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SEGMENT2() uint32 {
	return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x70) >> 4
}
func (o *TWAI_Type) SetBUS_TIMING_1_TIME_SAMPLING(value uint32) {
	volatile.StoreUint32(&o.BUS_TIMING_1.Reg, volatile.LoadUint32(&o.BUS_TIMING_1.Reg)&^(0x80)|value<<7)
}
func (o *TWAI_Type) GetBUS_TIMING_1_TIME_SAMPLING() uint32 {
	return (volatile.LoadUint32(&o.BUS_TIMING_1.Reg) & 0x80) >> 7
}

// TWAI.ARB_LOST_CAP: TWAI arbiter lost capture register.
func (o *TWAI_Type) SetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE(value uint32) {
	volatile.StoreUint32(&o.ARB_LOST_CAP.Reg, volatile.LoadUint32(&o.ARB_LOST_CAP.Reg)&^(0x1f)|value)
}
func (o *TWAI_Type) GetARB_LOST_CAP_ARBITRATION_LOST_CAPTURE() uint32 {
	return volatile.LoadUint32(&o.ARB_LOST_CAP.Reg) & 0x1f
}

// TWAI.ERR_CODE_CAP: TWAI error info capture register.
func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT(value uint32) {
	volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x1f)|value)
}
func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT() uint32 {
	return volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x1f
}
func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION(value uint32) {
	volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0x20)|value<<5)
}
func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION() uint32 {
	return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0x20) >> 5
}
func (o *TWAI_Type) SetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE(value uint32) {
	volatile.StoreUint32(&o.ERR_CODE_CAP.Reg, volatile.LoadUint32(&o.ERR_CODE_CAP.Reg)&^(0xc0)|value<<6)
}
func (o *TWAI_Type) GetERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE() uint32 {
	return (volatile.LoadUint32(&o.ERR_CODE_CAP.Reg) & 0xc0) >> 6
}

// TWAI.ERR_WARNING_LIMIT: TWAI error threshold configuration register.
func (o *TWAI_Type) SetERR_WARNING_LIMIT(value uint32) {
	volatile.StoreUint32(&o.ERR_WARNING_LIMIT.Reg, volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetERR_WARNING_LIMIT() uint32 {
	return volatile.LoadUint32(&o.ERR_WARNING_LIMIT.Reg) & 0xff
}

// TWAI.RX_ERR_CNT: Rx error counter register.
func (o *TWAI_Type) SetRX_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.RX_ERR_CNT.Reg, volatile.LoadUint32(&o.RX_ERR_CNT.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetRX_ERR_CNT() uint32 {
	return volatile.LoadUint32(&o.RX_ERR_CNT.Reg) & 0xff
}

// TWAI.TX_ERR_CNT: Tx error counter register.
func (o *TWAI_Type) SetTX_ERR_CNT(value uint32) {
	volatile.StoreUint32(&o.TX_ERR_CNT.Reg, volatile.LoadUint32(&o.TX_ERR_CNT.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetTX_ERR_CNT() uint32 {
	return volatile.LoadUint32(&o.TX_ERR_CNT.Reg) & 0xff
}

// TWAI.DATA_0: Data register 0.
func (o *TWAI_Type) SetDATA_0(value uint32) {
	volatile.StoreUint32(&o.DATA_0.Reg, volatile.LoadUint32(&o.DATA_0.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_0() uint32 {
	return volatile.LoadUint32(&o.DATA_0.Reg) & 0xff
}

// TWAI.DATA_1: Data register 1.
func (o *TWAI_Type) SetDATA_1(value uint32) {
	volatile.StoreUint32(&o.DATA_1.Reg, volatile.LoadUint32(&o.DATA_1.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_1() uint32 {
	return volatile.LoadUint32(&o.DATA_1.Reg) & 0xff
}

// TWAI.DATA_2: Data register 2.
func (o *TWAI_Type) SetDATA_2(value uint32) {
	volatile.StoreUint32(&o.DATA_2.Reg, volatile.LoadUint32(&o.DATA_2.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_2() uint32 {
	return volatile.LoadUint32(&o.DATA_2.Reg) & 0xff
}

// TWAI.DATA_3: Data register 3.
func (o *TWAI_Type) SetDATA_3(value uint32) {
	volatile.StoreUint32(&o.DATA_3.Reg, volatile.LoadUint32(&o.DATA_3.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_3() uint32 {
	return volatile.LoadUint32(&o.DATA_3.Reg) & 0xff
}

// TWAI.DATA_4: Data register 4.
func (o *TWAI_Type) SetDATA_4(value uint32) {
	volatile.StoreUint32(&o.DATA_4.Reg, volatile.LoadUint32(&o.DATA_4.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_4() uint32 {
	return volatile.LoadUint32(&o.DATA_4.Reg) & 0xff
}

// TWAI.DATA_5: Data register 5.
func (o *TWAI_Type) SetDATA_5(value uint32) {
	volatile.StoreUint32(&o.DATA_5.Reg, volatile.LoadUint32(&o.DATA_5.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_5() uint32 {
	return volatile.LoadUint32(&o.DATA_5.Reg) & 0xff
}

// TWAI.DATA_6: Data register 6.
func (o *TWAI_Type) SetDATA_6(value uint32) {
	volatile.StoreUint32(&o.DATA_6.Reg, volatile.LoadUint32(&o.DATA_6.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_6() uint32 {
	return volatile.LoadUint32(&o.DATA_6.Reg) & 0xff
}

// TWAI.DATA_7: Data register 7.
func (o *TWAI_Type) SetDATA_7(value uint32) {
	volatile.StoreUint32(&o.DATA_7.Reg, volatile.LoadUint32(&o.DATA_7.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_7() uint32 {
	return volatile.LoadUint32(&o.DATA_7.Reg) & 0xff
}

// TWAI.DATA_8: Data register 8.
func (o *TWAI_Type) SetDATA_8(value uint32) {
	volatile.StoreUint32(&o.DATA_8.Reg, volatile.LoadUint32(&o.DATA_8.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_8() uint32 {
	return volatile.LoadUint32(&o.DATA_8.Reg) & 0xff
}

// TWAI.DATA_9: Data register 9.
func (o *TWAI_Type) SetDATA_9(value uint32) {
	volatile.StoreUint32(&o.DATA_9.Reg, volatile.LoadUint32(&o.DATA_9.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_9() uint32 {
	return volatile.LoadUint32(&o.DATA_9.Reg) & 0xff
}

// TWAI.DATA_10: Data register 10.
func (o *TWAI_Type) SetDATA_10(value uint32) {
	volatile.StoreUint32(&o.DATA_10.Reg, volatile.LoadUint32(&o.DATA_10.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_10() uint32 {
	return volatile.LoadUint32(&o.DATA_10.Reg) & 0xff
}

// TWAI.DATA_11: Data register 11.
func (o *TWAI_Type) SetDATA_11(value uint32) {
	volatile.StoreUint32(&o.DATA_11.Reg, volatile.LoadUint32(&o.DATA_11.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_11() uint32 {
	return volatile.LoadUint32(&o.DATA_11.Reg) & 0xff
}

// TWAI.DATA_12: Data register 12.
func (o *TWAI_Type) SetDATA_12(value uint32) {
	volatile.StoreUint32(&o.DATA_12.Reg, volatile.LoadUint32(&o.DATA_12.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetDATA_12() uint32 {
	return volatile.LoadUint32(&o.DATA_12.Reg) & 0xff
}

// TWAI.RX_MESSAGE_COUNTER: Received message counter register.
func (o *TWAI_Type) SetRX_MESSAGE_COUNTER(value uint32) {
	volatile.StoreUint32(&o.RX_MESSAGE_COUNTER.Reg, volatile.LoadUint32(&o.RX_MESSAGE_COUNTER.Reg)&^(0x7f)|value)
}
func (o *TWAI_Type) GetRX_MESSAGE_COUNTER() uint32 {
	return volatile.LoadUint32(&o.RX_MESSAGE_COUNTER.Reg) & 0x7f
}

// TWAI.CLOCK_DIVIDER: Clock divider register.
func (o *TWAI_Type) SetCLOCK_DIVIDER_CD(value uint32) {
	volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0xff)|value)
}
func (o *TWAI_Type) GetCLOCK_DIVIDER_CD() uint32 {
	return volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0xff
}
func (o *TWAI_Type) SetCLOCK_DIVIDER_CLOCK_OFF(value uint32) {
	volatile.StoreUint32(&o.CLOCK_DIVIDER.Reg, volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg)&^(0x100)|value<<8)
}
func (o *TWAI_Type) GetCLOCK_DIVIDER_CLOCK_OFF() uint32 {
	return (volatile.LoadUint32(&o.CLOCK_DIVIDER.Reg) & 0x100) >> 8
}

// TWAI.SW_STANDBY_CFG: Software configure standby pin directly.
func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_EN(value uint32) {
	volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_EN() uint32 {
	return volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x1
}
func (o *TWAI_Type) SetSW_STANDBY_CFG_SW_STANDBY_CLR(value uint32) {
	volatile.StoreUint32(&o.SW_STANDBY_CFG.Reg, volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg)&^(0x2)|value<<1)
}
func (o *TWAI_Type) GetSW_STANDBY_CFG_SW_STANDBY_CLR() uint32 {
	return (volatile.LoadUint32(&o.SW_STANDBY_CFG.Reg) & 0x2) >> 1
}

// TWAI.HW_CFG: Hardware configure standby pin.
func (o *TWAI_Type) SetHW_CFG_HW_STANDBY_EN(value uint32) {
	volatile.StoreUint32(&o.HW_CFG.Reg, volatile.LoadUint32(&o.HW_CFG.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetHW_CFG_HW_STANDBY_EN() uint32 {
	return volatile.LoadUint32(&o.HW_CFG.Reg) & 0x1
}

// TWAI.HW_STANDBY_CNT: Configure standby counter.
func (o *TWAI_Type) SetHW_STANDBY_CNT(value uint32) {
	volatile.StoreUint32(&o.HW_STANDBY_CNT.Reg, value)
}
func (o *TWAI_Type) GetHW_STANDBY_CNT() uint32 {
	return volatile.LoadUint32(&o.HW_STANDBY_CNT.Reg)
}

// TWAI.IDLE_INTR_CNT: Configure idle interrupt counter.
func (o *TWAI_Type) SetIDLE_INTR_CNT(value uint32) {
	volatile.StoreUint32(&o.IDLE_INTR_CNT.Reg, value)
}
func (o *TWAI_Type) GetIDLE_INTR_CNT() uint32 {
	return volatile.LoadUint32(&o.IDLE_INTR_CNT.Reg)
}

// TWAI.ECO_CFG: ECO configuration register.
func (o *TWAI_Type) SetECO_CFG_RDN_ENA(value uint32) {
	volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetECO_CFG_RDN_ENA() uint32 {
	return volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x1
}
func (o *TWAI_Type) SetECO_CFG_RDN_RESULT(value uint32) {
	volatile.StoreUint32(&o.ECO_CFG.Reg, volatile.LoadUint32(&o.ECO_CFG.Reg)&^(0x2)|value<<1)
}
func (o *TWAI_Type) GetECO_CFG_RDN_RESULT() uint32 {
	return (volatile.LoadUint32(&o.ECO_CFG.Reg) & 0x2) >> 1
}

// TWAI.TIMESTAMP_DATA: Timestamp data register
func (o *TWAI_Type) SetTIMESTAMP_DATA(value uint32) {
	volatile.StoreUint32(&o.TIMESTAMP_DATA.Reg, value)
}
func (o *TWAI_Type) GetTIMESTAMP_DATA() uint32 {
	return volatile.LoadUint32(&o.TIMESTAMP_DATA.Reg)
}

// TWAI.TIMESTAMP_PRESCALER: Timestamp configuration register
func (o *TWAI_Type) SetTIMESTAMP_PRESCALER_TS_DIV_NUM(value uint32) {
	volatile.StoreUint32(&o.TIMESTAMP_PRESCALER.Reg, volatile.LoadUint32(&o.TIMESTAMP_PRESCALER.Reg)&^(0xffff)|value)
}
func (o *TWAI_Type) GetTIMESTAMP_PRESCALER_TS_DIV_NUM() uint32 {
	return volatile.LoadUint32(&o.TIMESTAMP_PRESCALER.Reg) & 0xffff
}

// TWAI.TIMESTAMP_CFG: Timestamp configuration register
func (o *TWAI_Type) SetTIMESTAMP_CFG_TS_ENABLE(value uint32) {
	volatile.StoreUint32(&o.TIMESTAMP_CFG.Reg, volatile.LoadUint32(&o.TIMESTAMP_CFG.Reg)&^(0x1)|value)
}
func (o *TWAI_Type) GetTIMESTAMP_CFG_TS_ENABLE() uint32 {
	return volatile.LoadUint32(&o.TIMESTAMP_CFG.Reg) & 0x1
}

// UART (Universal Asynchronous Receiver-Transmitter) Controller 0
type UART_Type struct {
	FIFO                volatile.Register32 // 0x0
	INT_RAW             volatile.Register32 // 0x4
	INT_ST              volatile.Register32 // 0x8
	INT_ENA             volatile.Register32 // 0xC
	INT_CLR             volatile.Register32 // 0x10
	CLKDIV_SYNC         volatile.Register32 // 0x14
	RX_FILT             volatile.Register32 // 0x18
	STATUS              volatile.Register32 // 0x1C
	CONF0_SYNC          volatile.Register32 // 0x20
	CONF1               volatile.Register32 // 0x24
	_                   [4]byte
	HWFC_CONF_SYNC      volatile.Register32 // 0x2C
	SLEEP_CONF0         volatile.Register32 // 0x30
	SLEEP_CONF1         volatile.Register32 // 0x34
	SLEEP_CONF2         volatile.Register32 // 0x38
	SWFC_CONF0_SYNC     volatile.Register32 // 0x3C
	SWFC_CONF1          volatile.Register32 // 0x40
	TXBRK_CONF_SYNC     volatile.Register32 // 0x44
	IDLE_CONF_SYNC      volatile.Register32 // 0x48
	RS485_CONF_SYNC     volatile.Register32 // 0x4C
	AT_CMD_PRECNT_SYNC  volatile.Register32 // 0x50
	AT_CMD_POSTCNT_SYNC volatile.Register32 // 0x54
	AT_CMD_GAPTOUT_SYNC volatile.Register32 // 0x58
	AT_CMD_CHAR_SYNC    volatile.Register32 // 0x5C
	MEM_CONF            volatile.Register32 // 0x60
	TOUT_CONF_SYNC      volatile.Register32 // 0x64
	MEM_TX_STATUS       volatile.Register32 // 0x68
	MEM_RX_STATUS       volatile.Register32 // 0x6C
	FSM_STATUS          volatile.Register32 // 0x70
	POSPULSE            volatile.Register32 // 0x74
	NEGPULSE            volatile.Register32 // 0x78
	LOWPULSE            volatile.Register32 // 0x7C
	HIGHPULSE           volatile.Register32 // 0x80
	RXD_CNT             volatile.Register32 // 0x84
	CLK_CONF            volatile.Register32 // 0x88
	DATE                volatile.Register32 // 0x8C
	AFIFO_STATUS        volatile.Register32 // 0x90
	_                   [4]byte
	REG_UPDATE          volatile.Register32 // 0x98
	ID                  volatile.Register32 // 0x9C
}

// UART.FIFO: FIFO data register
func (o *UART_Type) SetFIFO_RXFIFO_RD_BYTE(value uint32) {
	volatile.StoreUint32(&o.FIFO.Reg, volatile.LoadUint32(&o.FIFO.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetFIFO_RXFIFO_RD_BYTE() uint32 {
	return volatile.LoadUint32(&o.FIFO.Reg) & 0xff
}

// UART.INT_RAW: Raw interrupt status
func (o *UART_Type) SetINT_RAW_RXFIFO_FULL_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetINT_RAW_RXFIFO_FULL_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *UART_Type) SetINT_RAW_TXFIFO_EMPTY_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetINT_RAW_TXFIFO_EMPTY_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetINT_RAW_PARITY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *UART_Type) GetINT_RAW_PARITY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *UART_Type) SetINT_RAW_FRM_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetINT_RAW_FRM_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetINT_RAW_RXFIFO_OVF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetINT_RAW_RXFIFO_OVF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetINT_RAW_DSR_CHG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetINT_RAW_DSR_CHG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetINT_RAW_CTS_CHG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetINT_RAW_CTS_CHG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetINT_RAW_BRK_DET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetINT_RAW_BRK_DET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetINT_RAW_RXFIFO_TOUT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetINT_RAW_RXFIFO_TOUT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *UART_Type) SetINT_RAW_SW_XON_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetINT_RAW_SW_XON_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetINT_RAW_SW_XOFF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *UART_Type) GetINT_RAW_SW_XOFF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *UART_Type) SetINT_RAW_GLITCH_DET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetINT_RAW_GLITCH_DET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetINT_RAW_TX_BRK_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetINT_RAW_TX_BRK_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *UART_Type) SetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *UART_Type) GetINT_RAW_TX_BRK_IDLE_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *UART_Type) SetINT_RAW_TX_DONE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *UART_Type) GetINT_RAW_TX_DONE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *UART_Type) SetINT_RAW_RS485_PARITY_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *UART_Type) GetINT_RAW_RS485_PARITY_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}
func (o *UART_Type) SetINT_RAW_RS485_FRM_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10000)|value<<16)
}
func (o *UART_Type) GetINT_RAW_RS485_FRM_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10000) >> 16
}
func (o *UART_Type) SetINT_RAW_RS485_CLASH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20000)|value<<17)
}
func (o *UART_Type) GetINT_RAW_RS485_CLASH_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20000) >> 17
}
func (o *UART_Type) SetINT_RAW_AT_CMD_CHAR_DET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40000)|value<<18)
}
func (o *UART_Type) GetINT_RAW_AT_CMD_CHAR_DET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40000) >> 18
}
func (o *UART_Type) SetINT_RAW_WAKEUP_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80000)|value<<19)
}
func (o *UART_Type) GetINT_RAW_WAKEUP_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80000) >> 19
}

// UART.INT_ST: Masked interrupt status
func (o *UART_Type) SetINT_ST_RXFIFO_FULL_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetINT_ST_RXFIFO_FULL_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *UART_Type) SetINT_ST_TXFIFO_EMPTY_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetINT_ST_TXFIFO_EMPTY_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetINT_ST_PARITY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *UART_Type) GetINT_ST_PARITY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *UART_Type) SetINT_ST_FRM_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetINT_ST_FRM_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetINT_ST_RXFIFO_OVF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetINT_ST_RXFIFO_OVF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetINT_ST_DSR_CHG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetINT_ST_DSR_CHG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetINT_ST_CTS_CHG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetINT_ST_CTS_CHG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetINT_ST_BRK_DET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetINT_ST_BRK_DET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetINT_ST_RXFIFO_TOUT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetINT_ST_RXFIFO_TOUT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *UART_Type) SetINT_ST_SW_XON_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetINT_ST_SW_XON_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetINT_ST_SW_XOFF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *UART_Type) GetINT_ST_SW_XOFF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *UART_Type) SetINT_ST_GLITCH_DET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetINT_ST_GLITCH_DET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetINT_ST_TX_BRK_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetINT_ST_TX_BRK_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *UART_Type) SetINT_ST_TX_BRK_IDLE_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *UART_Type) GetINT_ST_TX_BRK_IDLE_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *UART_Type) SetINT_ST_TX_DONE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *UART_Type) GetINT_ST_TX_DONE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *UART_Type) SetINT_ST_RS485_PARITY_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *UART_Type) GetINT_ST_RS485_PARITY_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}
func (o *UART_Type) SetINT_ST_RS485_FRM_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10000)|value<<16)
}
func (o *UART_Type) GetINT_ST_RS485_FRM_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10000) >> 16
}
func (o *UART_Type) SetINT_ST_RS485_CLASH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20000)|value<<17)
}
func (o *UART_Type) GetINT_ST_RS485_CLASH_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20000) >> 17
}
func (o *UART_Type) SetINT_ST_AT_CMD_CHAR_DET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40000)|value<<18)
}
func (o *UART_Type) GetINT_ST_AT_CMD_CHAR_DET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40000) >> 18
}
func (o *UART_Type) SetINT_ST_WAKEUP_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80000)|value<<19)
}
func (o *UART_Type) GetINT_ST_WAKEUP_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80000) >> 19
}

// UART.INT_ENA: Interrupt enable bits
func (o *UART_Type) SetINT_ENA_RXFIFO_FULL_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetINT_ENA_RXFIFO_FULL_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *UART_Type) SetINT_ENA_TXFIFO_EMPTY_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetINT_ENA_TXFIFO_EMPTY_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetINT_ENA_PARITY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *UART_Type) GetINT_ENA_PARITY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *UART_Type) SetINT_ENA_FRM_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetINT_ENA_FRM_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetINT_ENA_RXFIFO_OVF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetINT_ENA_RXFIFO_OVF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetINT_ENA_DSR_CHG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetINT_ENA_DSR_CHG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetINT_ENA_CTS_CHG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetINT_ENA_CTS_CHG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetINT_ENA_BRK_DET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetINT_ENA_BRK_DET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetINT_ENA_RXFIFO_TOUT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetINT_ENA_RXFIFO_TOUT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *UART_Type) SetINT_ENA_SW_XON_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetINT_ENA_SW_XON_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetINT_ENA_SW_XOFF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *UART_Type) GetINT_ENA_SW_XOFF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *UART_Type) SetINT_ENA_GLITCH_DET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetINT_ENA_GLITCH_DET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetINT_ENA_TX_BRK_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetINT_ENA_TX_BRK_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *UART_Type) SetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *UART_Type) GetINT_ENA_TX_BRK_IDLE_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *UART_Type) SetINT_ENA_TX_DONE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *UART_Type) GetINT_ENA_TX_DONE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *UART_Type) SetINT_ENA_RS485_PARITY_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *UART_Type) GetINT_ENA_RS485_PARITY_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}
func (o *UART_Type) SetINT_ENA_RS485_FRM_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10000)|value<<16)
}
func (o *UART_Type) GetINT_ENA_RS485_FRM_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10000) >> 16
}
func (o *UART_Type) SetINT_ENA_RS485_CLASH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20000)|value<<17)
}
func (o *UART_Type) GetINT_ENA_RS485_CLASH_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20000) >> 17
}
func (o *UART_Type) SetINT_ENA_AT_CMD_CHAR_DET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40000)|value<<18)
}
func (o *UART_Type) GetINT_ENA_AT_CMD_CHAR_DET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40000) >> 18
}
func (o *UART_Type) SetINT_ENA_WAKEUP_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80000)|value<<19)
}
func (o *UART_Type) GetINT_ENA_WAKEUP_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80000) >> 19
}

// UART.INT_CLR: Interrupt clear bits
func (o *UART_Type) SetINT_CLR_RXFIFO_FULL_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetINT_CLR_RXFIFO_FULL_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *UART_Type) SetINT_CLR_TXFIFO_EMPTY_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetINT_CLR_TXFIFO_EMPTY_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetINT_CLR_PARITY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *UART_Type) GetINT_CLR_PARITY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *UART_Type) SetINT_CLR_FRM_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetINT_CLR_FRM_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetINT_CLR_RXFIFO_OVF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetINT_CLR_RXFIFO_OVF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetINT_CLR_DSR_CHG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetINT_CLR_DSR_CHG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetINT_CLR_CTS_CHG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetINT_CLR_CTS_CHG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetINT_CLR_BRK_DET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetINT_CLR_BRK_DET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetINT_CLR_RXFIFO_TOUT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetINT_CLR_RXFIFO_TOUT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *UART_Type) SetINT_CLR_SW_XON_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetINT_CLR_SW_XON_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetINT_CLR_SW_XOFF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *UART_Type) GetINT_CLR_SW_XOFF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *UART_Type) SetINT_CLR_GLITCH_DET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetINT_CLR_GLITCH_DET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetINT_CLR_TX_BRK_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetINT_CLR_TX_BRK_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *UART_Type) SetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *UART_Type) GetINT_CLR_TX_BRK_IDLE_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *UART_Type) SetINT_CLR_TX_DONE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *UART_Type) GetINT_CLR_TX_DONE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *UART_Type) SetINT_CLR_RS485_PARITY_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *UART_Type) GetINT_CLR_RS485_PARITY_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}
func (o *UART_Type) SetINT_CLR_RS485_FRM_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10000)|value<<16)
}
func (o *UART_Type) GetINT_CLR_RS485_FRM_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10000) >> 16
}
func (o *UART_Type) SetINT_CLR_RS485_CLASH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20000)|value<<17)
}
func (o *UART_Type) GetINT_CLR_RS485_CLASH_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20000) >> 17
}
func (o *UART_Type) SetINT_CLR_AT_CMD_CHAR_DET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40000)|value<<18)
}
func (o *UART_Type) GetINT_CLR_AT_CMD_CHAR_DET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40000) >> 18
}
func (o *UART_Type) SetINT_CLR_WAKEUP_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80000)|value<<19)
}
func (o *UART_Type) GetINT_CLR_WAKEUP_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80000) >> 19
}

// UART.CLKDIV_SYNC: Clock divider configuration
func (o *UART_Type) SetCLKDIV_SYNC_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xfff)|value)
}
func (o *UART_Type) GetCLKDIV_SYNC_CLKDIV() uint32 {
	return volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xfff
}
func (o *UART_Type) SetCLKDIV_SYNC_CLKDIV_FRAG(value uint32) {
	volatile.StoreUint32(&o.CLKDIV_SYNC.Reg, volatile.LoadUint32(&o.CLKDIV_SYNC.Reg)&^(0xf00000)|value<<20)
}
func (o *UART_Type) GetCLKDIV_SYNC_CLKDIV_FRAG() uint32 {
	return (volatile.LoadUint32(&o.CLKDIV_SYNC.Reg) & 0xf00000) >> 20
}

// UART.RX_FILT: Rx Filter configuration
func (o *UART_Type) SetRX_FILT_GLITCH_FILT(value uint32) {
	volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetRX_FILT_GLITCH_FILT() uint32 {
	return volatile.LoadUint32(&o.RX_FILT.Reg) & 0xff
}
func (o *UART_Type) SetRX_FILT_GLITCH_FILT_EN(value uint32) {
	volatile.StoreUint32(&o.RX_FILT.Reg, volatile.LoadUint32(&o.RX_FILT.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetRX_FILT_GLITCH_FILT_EN() uint32 {
	return (volatile.LoadUint32(&o.RX_FILT.Reg) & 0x100) >> 8
}

// UART.STATUS: UART status register
func (o *UART_Type) SetSTATUS_RXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetSTATUS_RXFIFO_CNT() uint32 {
	return volatile.LoadUint32(&o.STATUS.Reg) & 0xff
}
func (o *UART_Type) SetSTATUS_DSRN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x2000)|value<<13)
}
func (o *UART_Type) GetSTATUS_DSRN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x2000) >> 13
}
func (o *UART_Type) SetSTATUS_CTSN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x4000)|value<<14)
}
func (o *UART_Type) GetSTATUS_CTSN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x4000) >> 14
}
func (o *UART_Type) SetSTATUS_RXD(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x8000)|value<<15)
}
func (o *UART_Type) GetSTATUS_RXD() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x8000) >> 15
}
func (o *UART_Type) SetSTATUS_TXFIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0xff0000)|value<<16)
}
func (o *UART_Type) GetSTATUS_TXFIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0xff0000) >> 16
}
func (o *UART_Type) SetSTATUS_DTRN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x20000000)|value<<29)
}
func (o *UART_Type) GetSTATUS_DTRN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x20000000) >> 29
}
func (o *UART_Type) SetSTATUS_RTSN(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x40000000)|value<<30)
}
func (o *UART_Type) GetSTATUS_RTSN() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x40000000) >> 30
}
func (o *UART_Type) SetSTATUS_TXD(value uint32) {
	volatile.StoreUint32(&o.STATUS.Reg, volatile.LoadUint32(&o.STATUS.Reg)&^(0x80000000)|value<<31)
}
func (o *UART_Type) GetSTATUS_TXD() uint32 {
	return (volatile.LoadUint32(&o.STATUS.Reg) & 0x80000000) >> 31
}

// UART.CONF0_SYNC: a
func (o *UART_Type) SetCONF0_SYNC_PARITY(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetCONF0_SYNC_PARITY() uint32 {
	return volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1
}
func (o *UART_Type) SetCONF0_SYNC_PARITY_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetCONF0_SYNC_PARITY_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetCONF0_SYNC_BIT_NUM(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0xc)|value<<2)
}
func (o *UART_Type) GetCONF0_SYNC_BIT_NUM() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0xc) >> 2
}
func (o *UART_Type) SetCONF0_SYNC_STOP_BIT_NUM(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x30)|value<<4)
}
func (o *UART_Type) GetCONF0_SYNC_STOP_BIT_NUM() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x30) >> 4
}
func (o *UART_Type) SetCONF0_SYNC_TXD_BRK(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40)|value<<6)
}
func (o *UART_Type) GetCONF0_SYNC_TXD_BRK() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40) >> 6
}
func (o *UART_Type) SetCONF0_SYNC_IRDA_DPLX(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x80)|value<<7)
}
func (o *UART_Type) GetCONF0_SYNC_IRDA_DPLX() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x80) >> 7
}
func (o *UART_Type) SetCONF0_SYNC_IRDA_TX_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetCONF0_SYNC_IRDA_TX_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x100) >> 8
}
func (o *UART_Type) SetCONF0_SYNC_IRDA_WCTL(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x200)|value<<9)
}
func (o *UART_Type) GetCONF0_SYNC_IRDA_WCTL() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x200) >> 9
}
func (o *UART_Type) SetCONF0_SYNC_IRDA_TX_INV(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x400)|value<<10)
}
func (o *UART_Type) GetCONF0_SYNC_IRDA_TX_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x400) >> 10
}
func (o *UART_Type) SetCONF0_SYNC_IRDA_RX_INV(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x800)|value<<11)
}
func (o *UART_Type) GetCONF0_SYNC_IRDA_RX_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x800) >> 11
}
func (o *UART_Type) SetCONF0_SYNC_LOOPBACK(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x1000)|value<<12)
}
func (o *UART_Type) GetCONF0_SYNC_LOOPBACK() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x1000) >> 12
}
func (o *UART_Type) SetCONF0_SYNC_TX_FLOW_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x2000)|value<<13)
}
func (o *UART_Type) GetCONF0_SYNC_TX_FLOW_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x2000) >> 13
}
func (o *UART_Type) SetCONF0_SYNC_IRDA_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x4000)|value<<14)
}
func (o *UART_Type) GetCONF0_SYNC_IRDA_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x4000) >> 14
}
func (o *UART_Type) SetCONF0_SYNC_RXD_INV(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x8000)|value<<15)
}
func (o *UART_Type) GetCONF0_SYNC_RXD_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x8000) >> 15
}
func (o *UART_Type) SetCONF0_SYNC_TXD_INV(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x10000)|value<<16)
}
func (o *UART_Type) GetCONF0_SYNC_TXD_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x10000) >> 16
}
func (o *UART_Type) SetCONF0_SYNC_DIS_RX_DAT_OVF(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x20000)|value<<17)
}
func (o *UART_Type) GetCONF0_SYNC_DIS_RX_DAT_OVF() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x20000) >> 17
}
func (o *UART_Type) SetCONF0_SYNC_ERR_WR_MASK(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x40000)|value<<18)
}
func (o *UART_Type) GetCONF0_SYNC_ERR_WR_MASK() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x40000) >> 18
}
func (o *UART_Type) SetCONF0_SYNC_AUTOBAUD_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x80000)|value<<19)
}
func (o *UART_Type) GetCONF0_SYNC_AUTOBAUD_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x80000) >> 19
}
func (o *UART_Type) SetCONF0_SYNC_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x100000)|value<<20)
}
func (o *UART_Type) GetCONF0_SYNC_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x100000) >> 20
}
func (o *UART_Type) SetCONF0_SYNC_SW_RTS(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x200000)|value<<21)
}
func (o *UART_Type) GetCONF0_SYNC_SW_RTS() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x200000) >> 21
}
func (o *UART_Type) SetCONF0_SYNC_RXFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x400000)|value<<22)
}
func (o *UART_Type) GetCONF0_SYNC_RXFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x400000) >> 22
}
func (o *UART_Type) SetCONF0_SYNC_TXFIFO_RST(value uint32) {
	volatile.StoreUint32(&o.CONF0_SYNC.Reg, volatile.LoadUint32(&o.CONF0_SYNC.Reg)&^(0x800000)|value<<23)
}
func (o *UART_Type) GetCONF0_SYNC_TXFIFO_RST() uint32 {
	return (volatile.LoadUint32(&o.CONF0_SYNC.Reg) & 0x800000) >> 23
}

// UART.CONF1: Configuration register 1
func (o *UART_Type) SetCONF1_RXFIFO_FULL_THRHD(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetCONF1_RXFIFO_FULL_THRHD() uint32 {
	return volatile.LoadUint32(&o.CONF1.Reg) & 0xff
}
func (o *UART_Type) SetCONF1_TXFIFO_EMPTY_THRHD(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0xff00)|value<<8)
}
func (o *UART_Type) GetCONF1_TXFIFO_EMPTY_THRHD() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0xff00) >> 8
}
func (o *UART_Type) SetCONF1_CTS_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10000)|value<<16)
}
func (o *UART_Type) GetCONF1_CTS_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10000) >> 16
}
func (o *UART_Type) SetCONF1_DSR_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20000)|value<<17)
}
func (o *UART_Type) GetCONF1_DSR_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20000) >> 17
}
func (o *UART_Type) SetCONF1_RTS_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x40000)|value<<18)
}
func (o *UART_Type) GetCONF1_RTS_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x40000) >> 18
}
func (o *UART_Type) SetCONF1_DTR_INV(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80000)|value<<19)
}
func (o *UART_Type) GetCONF1_DTR_INV() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80000) >> 19
}
func (o *UART_Type) SetCONF1_SW_DTR(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100000)|value<<20)
}
func (o *UART_Type) GetCONF1_SW_DTR() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100000) >> 20
}
func (o *UART_Type) SetCONF1_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x200000)|value<<21)
}
func (o *UART_Type) GetCONF1_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x200000) >> 21
}

// UART.HWFC_CONF_SYNC: Hardware flow-control configuration
func (o *UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_THRHD(value uint32) {
	volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_THRHD() uint32 {
	return volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0xff
}
func (o *UART_Type) SetHWFC_CONF_SYNC_RX_FLOW_EN(value uint32) {
	volatile.StoreUint32(&o.HWFC_CONF_SYNC.Reg, volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg)&^(0x100)|value<<8)
}
func (o *UART_Type) GetHWFC_CONF_SYNC_RX_FLOW_EN() uint32 {
	return (volatile.LoadUint32(&o.HWFC_CONF_SYNC.Reg) & 0x100) >> 8
}

// UART.SLEEP_CONF0: UART sleep configure register 0
func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR1(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR1() uint32 {
	return volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff
}
func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR2(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff00)|value<<8)
}
func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR2() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff00) >> 8
}
func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR3(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff0000)|value<<16)
}
func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR3() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff0000) >> 16
}
func (o *UART_Type) SetSLEEP_CONF0_WK_CHAR4(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF0.Reg, volatile.LoadUint32(&o.SLEEP_CONF0.Reg)&^(0xff000000)|value<<24)
}
func (o *UART_Type) GetSLEEP_CONF0_WK_CHAR4() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF0.Reg) & 0xff000000) >> 24
}

// UART.SLEEP_CONF1: UART sleep configure register 1
func (o *UART_Type) SetSLEEP_CONF1_WK_CHAR0(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF1.Reg, volatile.LoadUint32(&o.SLEEP_CONF1.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetSLEEP_CONF1_WK_CHAR0() uint32 {
	return volatile.LoadUint32(&o.SLEEP_CONF1.Reg) & 0xff
}

// UART.SLEEP_CONF2: UART sleep configure register 2
func (o *UART_Type) SetSLEEP_CONF2_ACTIVE_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3ff)|value)
}
func (o *UART_Type) GetSLEEP_CONF2_ACTIVE_THRESHOLD() uint32 {
	return volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3ff
}
func (o *UART_Type) SetSLEEP_CONF2_RX_WAKE_UP_THRHD(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3fc00)|value<<10)
}
func (o *UART_Type) GetSLEEP_CONF2_RX_WAKE_UP_THRHD() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3fc00) >> 10
}
func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_NUM(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x1c0000)|value<<18)
}
func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_NUM() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x1c0000) >> 18
}
func (o *UART_Type) SetSLEEP_CONF2_WK_CHAR_MASK(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0x3e00000)|value<<21)
}
func (o *UART_Type) GetSLEEP_CONF2_WK_CHAR_MASK() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0x3e00000) >> 21
}
func (o *UART_Type) SetSLEEP_CONF2_WK_MODE_SEL(value uint32) {
	volatile.StoreUint32(&o.SLEEP_CONF2.Reg, volatile.LoadUint32(&o.SLEEP_CONF2.Reg)&^(0xc000000)|value<<26)
}
func (o *UART_Type) GetSLEEP_CONF2_WK_MODE_SEL() uint32 {
	return (volatile.LoadUint32(&o.SLEEP_CONF2.Reg) & 0xc000000) >> 26
}

// UART.SWFC_CONF0_SYNC: Software flow-control character configuration
func (o *UART_Type) SetSWFC_CONF0_SYNC_XON_CHAR(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_XON_CHAR() uint32 {
	return volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_XOFF_CHAR(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0xff00)|value<<8)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_XOFF_CHAR() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0xff00) >> 8
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x10000)|value<<16)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_XON_XOFF_STILL_SEND() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x10000) >> 16
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_SW_FLOW_CON_EN(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x20000)|value<<17)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_SW_FLOW_CON_EN() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x20000) >> 17
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_XONOFF_DEL(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x40000)|value<<18)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_XONOFF_DEL() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x40000) >> 18
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_FORCE_XON(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x80000)|value<<19)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_FORCE_XON() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x80000) >> 19
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_FORCE_XOFF(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x100000)|value<<20)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_FORCE_XOFF() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x100000) >> 20
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_SEND_XON(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x200000)|value<<21)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_SEND_XON() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x200000) >> 21
}
func (o *UART_Type) SetSWFC_CONF0_SYNC_SEND_XOFF(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF0_SYNC.Reg, volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg)&^(0x400000)|value<<22)
}
func (o *UART_Type) GetSWFC_CONF0_SYNC_SEND_XOFF() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF0_SYNC.Reg) & 0x400000) >> 22
}

// UART.SWFC_CONF1: Software flow-control character configuration
func (o *UART_Type) SetSWFC_CONF1_XON_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetSWFC_CONF1_XON_THRESHOLD() uint32 {
	return volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff
}
func (o *UART_Type) SetSWFC_CONF1_XOFF_THRESHOLD(value uint32) {
	volatile.StoreUint32(&o.SWFC_CONF1.Reg, volatile.LoadUint32(&o.SWFC_CONF1.Reg)&^(0xff00)|value<<8)
}
func (o *UART_Type) GetSWFC_CONF1_XOFF_THRESHOLD() uint32 {
	return (volatile.LoadUint32(&o.SWFC_CONF1.Reg) & 0xff00) >> 8
}

// UART.TXBRK_CONF_SYNC: Tx Break character configuration
func (o *UART_Type) SetTXBRK_CONF_SYNC_TX_BRK_NUM(value uint32) {
	volatile.StoreUint32(&o.TXBRK_CONF_SYNC.Reg, volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetTXBRK_CONF_SYNC_TX_BRK_NUM() uint32 {
	return volatile.LoadUint32(&o.TXBRK_CONF_SYNC.Reg) & 0xff
}

// UART.IDLE_CONF_SYNC: Frame-end idle configuration
func (o *UART_Type) SetIDLE_CONF_SYNC_RX_IDLE_THRHD(value uint32) {
	volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0x3ff)|value)
}
func (o *UART_Type) GetIDLE_CONF_SYNC_RX_IDLE_THRHD() uint32 {
	return volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0x3ff
}
func (o *UART_Type) SetIDLE_CONF_SYNC_TX_IDLE_NUM(value uint32) {
	volatile.StoreUint32(&o.IDLE_CONF_SYNC.Reg, volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg)&^(0xffc00)|value<<10)
}
func (o *UART_Type) GetIDLE_CONF_SYNC_TX_IDLE_NUM() uint32 {
	return (volatile.LoadUint32(&o.IDLE_CONF_SYNC.Reg) & 0xffc00) >> 10
}

// UART.RS485_CONF_SYNC: RS485 mode configuration
func (o *UART_Type) SetRS485_CONF_SYNC_RS485_EN(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetRS485_CONF_SYNC_RS485_EN() uint32 {
	return volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x1
}
func (o *UART_Type) SetRS485_CONF_SYNC_DL0_EN(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetRS485_CONF_SYNC_DL0_EN() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetRS485_CONF_SYNC_DL1_EN(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x4)|value<<2)
}
func (o *UART_Type) GetRS485_CONF_SYNC_DL1_EN() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x4) >> 2
}
func (o *UART_Type) SetRS485_CONF_SYNC_RS485TX_RX_EN(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetRS485_CONF_SYNC_RS485TX_RX_EN() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x8) >> 3
}
func (o *UART_Type) SetRS485_CONF_SYNC_RS485RXBY_TX_EN(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x10)|value<<4)
}
func (o *UART_Type) GetRS485_CONF_SYNC_RS485RXBY_TX_EN() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x10) >> 4
}
func (o *UART_Type) SetRS485_CONF_SYNC_RS485_RX_DLY_NUM(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x20)|value<<5)
}
func (o *UART_Type) GetRS485_CONF_SYNC_RS485_RX_DLY_NUM() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x20) >> 5
}
func (o *UART_Type) SetRS485_CONF_SYNC_RS485_TX_DLY_NUM(value uint32) {
	volatile.StoreUint32(&o.RS485_CONF_SYNC.Reg, volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg)&^(0x3c0)|value<<6)
}
func (o *UART_Type) GetRS485_CONF_SYNC_RS485_TX_DLY_NUM() uint32 {
	return (volatile.LoadUint32(&o.RS485_CONF_SYNC.Reg) & 0x3c0) >> 6
}

// UART.AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration
func (o *UART_Type) SetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_PRECNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetAT_CMD_PRECNT_SYNC_PRE_IDLE_NUM() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_PRECNT_SYNC.Reg) & 0xffff
}

// UART.AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration
func (o *UART_Type) SetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_POSTCNT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetAT_CMD_POSTCNT_SYNC_POST_IDLE_NUM() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_POSTCNT_SYNC.Reg) & 0xffff
}

// UART.AT_CMD_GAPTOUT_SYNC: Timeout configuration
func (o *UART_Type) SetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg)&^(0xffff)|value)
}
func (o *UART_Type) GetAT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_GAPTOUT_SYNC.Reg) & 0xffff
}

// UART.AT_CMD_CHAR_SYNC: AT escape sequence detection configuration
func (o *UART_Type) SetAT_CMD_CHAR_SYNC_AT_CMD_CHAR(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetAT_CMD_CHAR_SYNC_AT_CMD_CHAR() uint32 {
	return volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff
}
func (o *UART_Type) SetAT_CMD_CHAR_SYNC_CHAR_NUM(value uint32) {
	volatile.StoreUint32(&o.AT_CMD_CHAR_SYNC.Reg, volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg)&^(0xff00)|value<<8)
}
func (o *UART_Type) GetAT_CMD_CHAR_SYNC_CHAR_NUM() uint32 {
	return (volatile.LoadUint32(&o.AT_CMD_CHAR_SYNC.Reg) & 0xff00) >> 8
}

// UART.MEM_CONF: UART memory power configuration
func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2000000) >> 25
}
func (o *UART_Type) SetMEM_CONF_MEM_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *UART_Type) GetMEM_CONF_MEM_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x4000000) >> 26
}

// UART.TOUT_CONF_SYNC: UART threshold and allocation configuration
func (o *UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_EN(value uint32) {
	volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_EN() uint32 {
	return volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x1
}
func (o *UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS(value uint32) {
	volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_FLOW_DIS() uint32 {
	return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetTOUT_CONF_SYNC_RX_TOUT_THRHD(value uint32) {
	volatile.StoreUint32(&o.TOUT_CONF_SYNC.Reg, volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg)&^(0xffc)|value<<2)
}
func (o *UART_Type) GetTOUT_CONF_SYNC_RX_TOUT_THRHD() uint32 {
	return (volatile.LoadUint32(&o.TOUT_CONF_SYNC.Reg) & 0xffc) >> 2
}

// UART.MEM_TX_STATUS: Tx-SRAM write and read offset address.
func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_WADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_WADDR() uint32 {
	return volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0xff
}
func (o *UART_Type) SetMEM_TX_STATUS_TX_SRAM_RADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_TX_STATUS.Reg, volatile.LoadUint32(&o.MEM_TX_STATUS.Reg)&^(0x1fe00)|value<<9)
}
func (o *UART_Type) GetMEM_TX_STATUS_TX_SRAM_RADDR() uint32 {
	return (volatile.LoadUint32(&o.MEM_TX_STATUS.Reg) & 0x1fe00) >> 9
}

// UART.MEM_RX_STATUS: Rx-SRAM write and read offset address.
func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_RADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0xff)|value)
}
func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_RADDR() uint32 {
	return volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0xff
}
func (o *UART_Type) SetMEM_RX_STATUS_RX_SRAM_WADDR(value uint32) {
	volatile.StoreUint32(&o.MEM_RX_STATUS.Reg, volatile.LoadUint32(&o.MEM_RX_STATUS.Reg)&^(0x1fe00)|value<<9)
}
func (o *UART_Type) GetMEM_RX_STATUS_RX_SRAM_WADDR() uint32 {
	return (volatile.LoadUint32(&o.MEM_RX_STATUS.Reg) & 0x1fe00) >> 9
}

// UART.FSM_STATUS: UART transmit and receive status.
func (o *UART_Type) SetFSM_STATUS_ST_URX_OUT(value uint32) {
	volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf)|value)
}
func (o *UART_Type) GetFSM_STATUS_ST_URX_OUT() uint32 {
	return volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf
}
func (o *UART_Type) SetFSM_STATUS_ST_UTX_OUT(value uint32) {
	volatile.StoreUint32(&o.FSM_STATUS.Reg, volatile.LoadUint32(&o.FSM_STATUS.Reg)&^(0xf0)|value<<4)
}
func (o *UART_Type) GetFSM_STATUS_ST_UTX_OUT() uint32 {
	return (volatile.LoadUint32(&o.FSM_STATUS.Reg) & 0xf0) >> 4
}

// UART.POSPULSE: Autobaud high pulse register
func (o *UART_Type) SetPOSPULSE_POSEDGE_MIN_CNT(value uint32) {
	volatile.StoreUint32(&o.POSPULSE.Reg, volatile.LoadUint32(&o.POSPULSE.Reg)&^(0xfff)|value)
}
func (o *UART_Type) GetPOSPULSE_POSEDGE_MIN_CNT() uint32 {
	return volatile.LoadUint32(&o.POSPULSE.Reg) & 0xfff
}

// UART.NEGPULSE: Autobaud low pulse register
func (o *UART_Type) SetNEGPULSE_NEGEDGE_MIN_CNT(value uint32) {
	volatile.StoreUint32(&o.NEGPULSE.Reg, volatile.LoadUint32(&o.NEGPULSE.Reg)&^(0xfff)|value)
}
func (o *UART_Type) GetNEGPULSE_NEGEDGE_MIN_CNT() uint32 {
	return volatile.LoadUint32(&o.NEGPULSE.Reg) & 0xfff
}

// UART.LOWPULSE: Autobaud minimum low pulse duration register
func (o *UART_Type) SetLOWPULSE_MIN_CNT(value uint32) {
	volatile.StoreUint32(&o.LOWPULSE.Reg, volatile.LoadUint32(&o.LOWPULSE.Reg)&^(0xfff)|value)
}
func (o *UART_Type) GetLOWPULSE_MIN_CNT() uint32 {
	return volatile.LoadUint32(&o.LOWPULSE.Reg) & 0xfff
}

// UART.HIGHPULSE: Autobaud minimum high pulse duration register
func (o *UART_Type) SetHIGHPULSE_MIN_CNT(value uint32) {
	volatile.StoreUint32(&o.HIGHPULSE.Reg, volatile.LoadUint32(&o.HIGHPULSE.Reg)&^(0xfff)|value)
}
func (o *UART_Type) GetHIGHPULSE_MIN_CNT() uint32 {
	return volatile.LoadUint32(&o.HIGHPULSE.Reg) & 0xfff
}

// UART.RXD_CNT: Autobaud edge change count register
func (o *UART_Type) SetRXD_CNT_RXD_EDGE_CNT(value uint32) {
	volatile.StoreUint32(&o.RXD_CNT.Reg, volatile.LoadUint32(&o.RXD_CNT.Reg)&^(0x3ff)|value)
}
func (o *UART_Type) GetRXD_CNT_RXD_EDGE_CNT() uint32 {
	return volatile.LoadUint32(&o.RXD_CNT.Reg) & 0x3ff
}

// UART.CLK_CONF: UART core clock configuration
func (o *UART_Type) SetCLK_CONF_TX_SCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x1000000)|value<<24)
}
func (o *UART_Type) GetCLK_CONF_TX_SCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x1000000) >> 24
}
func (o *UART_Type) SetCLK_CONF_RX_SCLK_EN(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x2000000)|value<<25)
}
func (o *UART_Type) GetCLK_CONF_RX_SCLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x2000000) >> 25
}
func (o *UART_Type) SetCLK_CONF_TX_RST_CORE(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x4000000)|value<<26)
}
func (o *UART_Type) GetCLK_CONF_TX_RST_CORE() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x4000000) >> 26
}
func (o *UART_Type) SetCLK_CONF_RX_RST_CORE(value uint32) {
	volatile.StoreUint32(&o.CLK_CONF.Reg, volatile.LoadUint32(&o.CLK_CONF.Reg)&^(0x8000000)|value<<27)
}
func (o *UART_Type) GetCLK_CONF_RX_RST_CORE() uint32 {
	return (volatile.LoadUint32(&o.CLK_CONF.Reg) & 0x8000000) >> 27
}

// UART.DATE: UART Version register
func (o *UART_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *UART_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// UART.AFIFO_STATUS: UART AFIFO Status
func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_FULL() uint32 {
	return volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x1
}
func (o *UART_Type) SetAFIFO_STATUS_TX_AFIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *UART_Type) GetAFIFO_STATUS_TX_AFIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x2) >> 1
}
func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x4) >> 2
}
func (o *UART_Type) SetAFIFO_STATUS_RX_AFIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.AFIFO_STATUS.Reg, volatile.LoadUint32(&o.AFIFO_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *UART_Type) GetAFIFO_STATUS_RX_AFIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.AFIFO_STATUS.Reg) & 0x8) >> 3
}

// UART.REG_UPDATE: UART Registers Configuration Update register
func (o *UART_Type) SetREG_UPDATE(value uint32) {
	volatile.StoreUint32(&o.REG_UPDATE.Reg, volatile.LoadUint32(&o.REG_UPDATE.Reg)&^(0x1)|value)
}
func (o *UART_Type) GetREG_UPDATE() uint32 {
	return volatile.LoadUint32(&o.REG_UPDATE.Reg) & 0x1
}

// UART.ID: UART ID register
func (o *UART_Type) SetID(value uint32) {
	volatile.StoreUint32(&o.ID.Reg, value)
}
func (o *UART_Type) GetID() uint32 {
	return volatile.LoadUint32(&o.ID.Reg)
}

// Universal Host Controller Interface 0
type UHCI_Type struct {
	CONF0        volatile.Register32 // 0x0
	INT_RAW      volatile.Register32 // 0x4
	INT_ST       volatile.Register32 // 0x8
	INT_ENA      volatile.Register32 // 0xC
	INT_CLR      volatile.Register32 // 0x10
	CONF1        volatile.Register32 // 0x14
	STATE0       volatile.Register32 // 0x18
	STATE1       volatile.Register32 // 0x1C
	ESCAPE_CONF  volatile.Register32 // 0x20
	HUNG_CONF    volatile.Register32 // 0x24
	ACK_NUM      volatile.Register32 // 0x28
	RX_HEAD      volatile.Register32 // 0x2C
	QUICK_SENT   volatile.Register32 // 0x30
	REG_Q0_WORD0 volatile.Register32 // 0x34
	REG_Q0_WORD1 volatile.Register32 // 0x38
	REG_Q1_WORD0 volatile.Register32 // 0x3C
	REG_Q1_WORD1 volatile.Register32 // 0x40
	REG_Q2_WORD0 volatile.Register32 // 0x44
	REG_Q2_WORD1 volatile.Register32 // 0x48
	REG_Q3_WORD0 volatile.Register32 // 0x4C
	REG_Q3_WORD1 volatile.Register32 // 0x50
	REG_Q4_WORD0 volatile.Register32 // 0x54
	REG_Q4_WORD1 volatile.Register32 // 0x58
	REG_Q5_WORD0 volatile.Register32 // 0x5C
	REG_Q5_WORD1 volatile.Register32 // 0x60
	REG_Q6_WORD0 volatile.Register32 // 0x64
	REG_Q6_WORD1 volatile.Register32 // 0x68
	ESC_CONF0    volatile.Register32 // 0x6C
	ESC_CONF1    volatile.Register32 // 0x70
	ESC_CONF2    volatile.Register32 // 0x74
	ESC_CONF3    volatile.Register32 // 0x78
	PKT_THRES    volatile.Register32 // 0x7C
	DATE         volatile.Register32 // 0x80
}

// UHCI.CONF0: UHCI Configuration Register0
func (o *UHCI_Type) SetCONF0_TX_RST(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value)
}
func (o *UHCI_Type) GetCONF0_TX_RST() uint32 {
	return volatile.LoadUint32(&o.CONF0.Reg) & 0x1
}
func (o *UHCI_Type) SetCONF0_RX_RST(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1)
}
func (o *UHCI_Type) GetCONF0_RX_RST() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1
}
func (o *UHCI_Type) SetCONF0_UART_SEL(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1c)|value<<2)
}
func (o *UHCI_Type) GetCONF0_UART_SEL() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1c) >> 2
}
func (o *UHCI_Type) SetCONF0_SEPER_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x20)|value<<5)
}
func (o *UHCI_Type) GetCONF0_SEPER_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x20) >> 5
}
func (o *UHCI_Type) SetCONF0_HEAD_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x40)|value<<6)
}
func (o *UHCI_Type) GetCONF0_HEAD_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x40) >> 6
}
func (o *UHCI_Type) SetCONF0_CRC_REC_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetCONF0_CRC_REC_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7
}
func (o *UHCI_Type) SetCONF0_UART_IDLE_EOF_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8)
}
func (o *UHCI_Type) GetCONF0_UART_IDLE_EOF_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8
}
func (o *UHCI_Type) SetCONF0_LEN_EOF_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9)
}
func (o *UHCI_Type) GetCONF0_LEN_EOF_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9
}
func (o *UHCI_Type) SetCONF0_ENCODE_CRC_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10)
}
func (o *UHCI_Type) GetCONF0_ENCODE_CRC_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10
}
func (o *UHCI_Type) SetCONF0_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11)
}
func (o *UHCI_Type) GetCONF0_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11
}
func (o *UHCI_Type) SetCONF0_UART_RX_BRK_EOF_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12)
}
func (o *UHCI_Type) GetCONF0_UART_RX_BRK_EOF_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12
}

// UHCI.INT_RAW: UHCI Interrupt Raw Register
func (o *UHCI_Type) SetINT_RAW_RX_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *UHCI_Type) GetINT_RAW_RX_START_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *UHCI_Type) SetINT_RAW_TX_START_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *UHCI_Type) GetINT_RAW_TX_START_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *UHCI_Type) SetINT_RAW_RX_HUNG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *UHCI_Type) GetINT_RAW_RX_HUNG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *UHCI_Type) SetINT_RAW_TX_HUNG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetINT_RAW_TX_HUNG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *UHCI_Type) SetINT_RAW_SEND_S_REG_Q_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *UHCI_Type) GetINT_RAW_SEND_S_REG_Q_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *UHCI_Type) SetINT_RAW_SEND_A_REG_Q_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *UHCI_Type) GetINT_RAW_SEND_A_REG_Q_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *UHCI_Type) SetINT_RAW_OUT_EOF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *UHCI_Type) GetINT_RAW_OUT_EOF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *UHCI_Type) SetINT_RAW_APP_CTRL0_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetINT_RAW_APP_CTRL0_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *UHCI_Type) SetINT_RAW_APP_CTRL1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *UHCI_Type) GetINT_RAW_APP_CTRL1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}

// UHCI.INT_ST: UHCI Interrupt Status Register
func (o *UHCI_Type) SetINT_ST_RX_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *UHCI_Type) GetINT_ST_RX_START_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *UHCI_Type) SetINT_ST_TX_START_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *UHCI_Type) GetINT_ST_TX_START_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *UHCI_Type) SetINT_ST_RX_HUNG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *UHCI_Type) GetINT_ST_RX_HUNG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *UHCI_Type) SetINT_ST_TX_HUNG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetINT_ST_TX_HUNG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *UHCI_Type) SetINT_ST_SEND_S_REG_Q_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *UHCI_Type) GetINT_ST_SEND_S_REG_Q_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *UHCI_Type) SetINT_ST_SEND_A_REG_Q_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *UHCI_Type) GetINT_ST_SEND_A_REG_Q_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *UHCI_Type) SetINT_ST_OUTLINK_EOF_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *UHCI_Type) GetINT_ST_OUTLINK_EOF_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *UHCI_Type) SetINT_ST_APP_CTRL0_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetINT_ST_APP_CTRL0_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *UHCI_Type) SetINT_ST_APP_CTRL1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *UHCI_Type) GetINT_ST_APP_CTRL1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}

// UHCI.INT_ENA: UHCI Interrupt Enable Register
func (o *UHCI_Type) SetINT_ENA_RX_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *UHCI_Type) GetINT_ENA_RX_START_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *UHCI_Type) SetINT_ENA_TX_START_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *UHCI_Type) GetINT_ENA_TX_START_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *UHCI_Type) SetINT_ENA_RX_HUNG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *UHCI_Type) GetINT_ENA_RX_HUNG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *UHCI_Type) SetINT_ENA_TX_HUNG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetINT_ENA_TX_HUNG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *UHCI_Type) SetINT_ENA_SEND_S_REG_Q_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *UHCI_Type) GetINT_ENA_SEND_S_REG_Q_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *UHCI_Type) SetINT_ENA_SEND_A_REG_Q_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *UHCI_Type) GetINT_ENA_SEND_A_REG_Q_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *UHCI_Type) SetINT_ENA_OUTLINK_EOF_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *UHCI_Type) GetINT_ENA_OUTLINK_EOF_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *UHCI_Type) SetINT_ENA_APP_CTRL0_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetINT_ENA_APP_CTRL0_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *UHCI_Type) SetINT_ENA_APP_CTRL1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *UHCI_Type) GetINT_ENA_APP_CTRL1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}

// UHCI.INT_CLR: UHCI Interrupt Clear Register
func (o *UHCI_Type) SetINT_CLR_RX_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *UHCI_Type) GetINT_CLR_RX_START_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *UHCI_Type) SetINT_CLR_TX_START_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *UHCI_Type) GetINT_CLR_TX_START_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *UHCI_Type) SetINT_CLR_RX_HUNG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *UHCI_Type) GetINT_CLR_RX_HUNG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *UHCI_Type) SetINT_CLR_TX_HUNG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetINT_CLR_TX_HUNG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *UHCI_Type) SetINT_CLR_SEND_S_REG_Q_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *UHCI_Type) GetINT_CLR_SEND_S_REG_Q_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *UHCI_Type) SetINT_CLR_SEND_A_REG_Q_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *UHCI_Type) GetINT_CLR_SEND_A_REG_Q_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *UHCI_Type) SetINT_CLR_OUTLINK_EOF_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *UHCI_Type) GetINT_CLR_OUTLINK_EOF_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *UHCI_Type) SetINT_CLR_APP_CTRL0_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetINT_CLR_APP_CTRL0_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *UHCI_Type) SetINT_CLR_APP_CTRL1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *UHCI_Type) GetINT_CLR_APP_CTRL1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}

// UHCI.CONF1: UHCI Configuration Register1
func (o *UHCI_Type) SetCONF1_CHECK_SUM_EN(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x1)|value)
}
func (o *UHCI_Type) GetCONF1_CHECK_SUM_EN() uint32 {
	return volatile.LoadUint32(&o.CONF1.Reg) & 0x1
}
func (o *UHCI_Type) SetCONF1_CHECK_SEQ_EN(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x2)|value<<1)
}
func (o *UHCI_Type) GetCONF1_CHECK_SEQ_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x2) >> 1
}
func (o *UHCI_Type) SetCONF1_CRC_DISABLE(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x4)|value<<2)
}
func (o *UHCI_Type) GetCONF1_CRC_DISABLE() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x4) >> 2
}
func (o *UHCI_Type) SetCONF1_SAVE_HEAD(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetCONF1_SAVE_HEAD() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x8) >> 3
}
func (o *UHCI_Type) SetCONF1_TX_CHECK_SUM_RE(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x10)|value<<4)
}
func (o *UHCI_Type) GetCONF1_TX_CHECK_SUM_RE() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x10) >> 4
}
func (o *UHCI_Type) SetCONF1_TX_ACK_NUM_RE(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x20)|value<<5)
}
func (o *UHCI_Type) GetCONF1_TX_ACK_NUM_RE() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x20) >> 5
}
func (o *UHCI_Type) SetCONF1_WAIT_SW_START(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetCONF1_WAIT_SW_START() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x80) >> 7
}
func (o *UHCI_Type) SetCONF1_SW_START(value uint32) {
	volatile.StoreUint32(&o.CONF1.Reg, volatile.LoadUint32(&o.CONF1.Reg)&^(0x100)|value<<8)
}
func (o *UHCI_Type) GetCONF1_SW_START() uint32 {
	return (volatile.LoadUint32(&o.CONF1.Reg) & 0x100) >> 8
}

// UHCI.STATE0: UHCI Receive Status Register
func (o *UHCI_Type) SetSTATE0_RX_ERR_CAUSE(value uint32) {
	volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x7)|value)
}
func (o *UHCI_Type) GetSTATE0_RX_ERR_CAUSE() uint32 {
	return volatile.LoadUint32(&o.STATE0.Reg) & 0x7
}
func (o *UHCI_Type) SetSTATE0_DECODE_STATE(value uint32) {
	volatile.StoreUint32(&o.STATE0.Reg, volatile.LoadUint32(&o.STATE0.Reg)&^(0x38)|value<<3)
}
func (o *UHCI_Type) GetSTATE0_DECODE_STATE() uint32 {
	return (volatile.LoadUint32(&o.STATE0.Reg) & 0x38) >> 3
}

// UHCI.STATE1: UHCI Transmit Status Register
func (o *UHCI_Type) SetSTATE1_ENCODE_STATE(value uint32) {
	volatile.StoreUint32(&o.STATE1.Reg, volatile.LoadUint32(&o.STATE1.Reg)&^(0x7)|value)
}
func (o *UHCI_Type) GetSTATE1_ENCODE_STATE() uint32 {
	return volatile.LoadUint32(&o.STATE1.Reg) & 0x7
}

// UHCI.ESCAPE_CONF: UHCI Escapes Configuration Register0
func (o *UHCI_Type) SetESCAPE_CONF_TX_C0_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x1)|value)
}
func (o *UHCI_Type) GetESCAPE_CONF_TX_C0_ESC_EN() uint32 {
	return volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x1
}
func (o *UHCI_Type) SetESCAPE_CONF_TX_DB_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x2)|value<<1)
}
func (o *UHCI_Type) GetESCAPE_CONF_TX_DB_ESC_EN() uint32 {
	return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x2) >> 1
}
func (o *UHCI_Type) SetESCAPE_CONF_TX_11_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x4)|value<<2)
}
func (o *UHCI_Type) GetESCAPE_CONF_TX_11_ESC_EN() uint32 {
	return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x4) >> 2
}
func (o *UHCI_Type) SetESCAPE_CONF_TX_13_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetESCAPE_CONF_TX_13_ESC_EN() uint32 {
	return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x8) >> 3
}
func (o *UHCI_Type) SetESCAPE_CONF_RX_C0_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x10)|value<<4)
}
func (o *UHCI_Type) GetESCAPE_CONF_RX_C0_ESC_EN() uint32 {
	return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x10) >> 4
}
func (o *UHCI_Type) SetESCAPE_CONF_RX_DB_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x20)|value<<5)
}
func (o *UHCI_Type) GetESCAPE_CONF_RX_DB_ESC_EN() uint32 {
	return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x20) >> 5
}
func (o *UHCI_Type) SetESCAPE_CONF_RX_11_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x40)|value<<6)
}
func (o *UHCI_Type) GetESCAPE_CONF_RX_11_ESC_EN() uint32 {
	return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x40) >> 6
}
func (o *UHCI_Type) SetESCAPE_CONF_RX_13_ESC_EN(value uint32) {
	volatile.StoreUint32(&o.ESCAPE_CONF.Reg, volatile.LoadUint32(&o.ESCAPE_CONF.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetESCAPE_CONF_RX_13_ESC_EN() uint32 {
	return (volatile.LoadUint32(&o.ESCAPE_CONF.Reg) & 0x80) >> 7
}

// UHCI.HUNG_CONF: UHCI Hung Configuration Register0
func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff)|value)
}
func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT() uint32 {
	return volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff
}
func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT(value uint32) {
	volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700)|value<<8)
}
func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700) >> 8
}
func (o *UHCI_Type) SetHUNG_CONF_TXFIFO_TIMEOUT_ENA(value uint32) {
	volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800)|value<<11)
}
func (o *UHCI_Type) GetHUNG_CONF_TXFIFO_TIMEOUT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800) >> 11
}
func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0xff000)|value<<12)
}
func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0xff000) >> 12
}
func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT(value uint32) {
	volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x700000)|value<<20)
}
func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_SHIFT() uint32 {
	return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x700000) >> 20
}
func (o *UHCI_Type) SetHUNG_CONF_RXFIFO_TIMEOUT_ENA(value uint32) {
	volatile.StoreUint32(&o.HUNG_CONF.Reg, volatile.LoadUint32(&o.HUNG_CONF.Reg)&^(0x800000)|value<<23)
}
func (o *UHCI_Type) GetHUNG_CONF_RXFIFO_TIMEOUT_ENA() uint32 {
	return (volatile.LoadUint32(&o.HUNG_CONF.Reg) & 0x800000) >> 23
}

// UHCI.ACK_NUM: UHCI Ack Value Configuration Register0
func (o *UHCI_Type) SetACK_NUM(value uint32) {
	volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x7)|value)
}
func (o *UHCI_Type) GetACK_NUM() uint32 {
	return volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x7
}
func (o *UHCI_Type) SetACK_NUM_LOAD(value uint32) {
	volatile.StoreUint32(&o.ACK_NUM.Reg, volatile.LoadUint32(&o.ACK_NUM.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetACK_NUM_LOAD() uint32 {
	return (volatile.LoadUint32(&o.ACK_NUM.Reg) & 0x8) >> 3
}

// UHCI.RX_HEAD: UHCI Head Register
func (o *UHCI_Type) SetRX_HEAD(value uint32) {
	volatile.StoreUint32(&o.RX_HEAD.Reg, value)
}
func (o *UHCI_Type) GetRX_HEAD() uint32 {
	return volatile.LoadUint32(&o.RX_HEAD.Reg)
}

// UHCI.QUICK_SENT: UCHI Quick send Register
func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_NUM(value uint32) {
	volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x7)|value)
}
func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_NUM() uint32 {
	return volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x7
}
func (o *UHCI_Type) SetQUICK_SENT_SINGLE_SEND_EN(value uint32) {
	volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x8)|value<<3)
}
func (o *UHCI_Type) GetQUICK_SENT_SINGLE_SEND_EN() uint32 {
	return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x8) >> 3
}
func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_NUM(value uint32) {
	volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x70)|value<<4)
}
func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_NUM() uint32 {
	return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x70) >> 4
}
func (o *UHCI_Type) SetQUICK_SENT_ALWAYS_SEND_EN(value uint32) {
	volatile.StoreUint32(&o.QUICK_SENT.Reg, volatile.LoadUint32(&o.QUICK_SENT.Reg)&^(0x80)|value<<7)
}
func (o *UHCI_Type) GetQUICK_SENT_ALWAYS_SEND_EN() uint32 {
	return (volatile.LoadUint32(&o.QUICK_SENT.Reg) & 0x80) >> 7
}

// UHCI.REG_Q0_WORD0: UHCI Q0_WORD0 Quick Send Register
func (o *UHCI_Type) SetREG_Q0_WORD0(value uint32) {
	volatile.StoreUint32(&o.REG_Q0_WORD0.Reg, value)
}
func (o *UHCI_Type) GetREG_Q0_WORD0() uint32 {
	return volatile.LoadUint32(&o.REG_Q0_WORD0.Reg)
}

// UHCI.REG_Q0_WORD1: UHCI Q0_WORD1 Quick Send Register
func (o *UHCI_Type) SetREG_Q0_WORD1(value uint32) {
	volatile.StoreUint32(&o.REG_Q0_WORD1.Reg, value)
}
func (o *UHCI_Type) GetREG_Q0_WORD1() uint32 {
	return volatile.LoadUint32(&o.REG_Q0_WORD1.Reg)
}

// UHCI.REG_Q1_WORD0: UHCI Q1_WORD0 Quick Send Register
func (o *UHCI_Type) SetREG_Q1_WORD0(value uint32) {
	volatile.StoreUint32(&o.REG_Q1_WORD0.Reg, value)
}
func (o *UHCI_Type) GetREG_Q1_WORD0() uint32 {
	return volatile.LoadUint32(&o.REG_Q1_WORD0.Reg)
}

// UHCI.REG_Q1_WORD1: UHCI Q1_WORD1 Quick Send Register
func (o *UHCI_Type) SetREG_Q1_WORD1(value uint32) {
	volatile.StoreUint32(&o.REG_Q1_WORD1.Reg, value)
}
func (o *UHCI_Type) GetREG_Q1_WORD1() uint32 {
	return volatile.LoadUint32(&o.REG_Q1_WORD1.Reg)
}

// UHCI.REG_Q2_WORD0: UHCI Q2_WORD0 Quick Send Register
func (o *UHCI_Type) SetREG_Q2_WORD0(value uint32) {
	volatile.StoreUint32(&o.REG_Q2_WORD0.Reg, value)
}
func (o *UHCI_Type) GetREG_Q2_WORD0() uint32 {
	return volatile.LoadUint32(&o.REG_Q2_WORD0.Reg)
}

// UHCI.REG_Q2_WORD1: UHCI Q2_WORD1 Quick Send Register
func (o *UHCI_Type) SetREG_Q2_WORD1(value uint32) {
	volatile.StoreUint32(&o.REG_Q2_WORD1.Reg, value)
}
func (o *UHCI_Type) GetREG_Q2_WORD1() uint32 {
	return volatile.LoadUint32(&o.REG_Q2_WORD1.Reg)
}

// UHCI.REG_Q3_WORD0: UHCI Q3_WORD0 Quick Send Register
func (o *UHCI_Type) SetREG_Q3_WORD0(value uint32) {
	volatile.StoreUint32(&o.REG_Q3_WORD0.Reg, value)
}
func (o *UHCI_Type) GetREG_Q3_WORD0() uint32 {
	return volatile.LoadUint32(&o.REG_Q3_WORD0.Reg)
}

// UHCI.REG_Q3_WORD1: UHCI Q3_WORD1 Quick Send Register
func (o *UHCI_Type) SetREG_Q3_WORD1(value uint32) {
	volatile.StoreUint32(&o.REG_Q3_WORD1.Reg, value)
}
func (o *UHCI_Type) GetREG_Q3_WORD1() uint32 {
	return volatile.LoadUint32(&o.REG_Q3_WORD1.Reg)
}

// UHCI.REG_Q4_WORD0: UHCI Q4_WORD0 Quick Send Register
func (o *UHCI_Type) SetREG_Q4_WORD0(value uint32) {
	volatile.StoreUint32(&o.REG_Q4_WORD0.Reg, value)
}
func (o *UHCI_Type) GetREG_Q4_WORD0() uint32 {
	return volatile.LoadUint32(&o.REG_Q4_WORD0.Reg)
}

// UHCI.REG_Q4_WORD1: UHCI Q4_WORD1 Quick Send Register
func (o *UHCI_Type) SetREG_Q4_WORD1(value uint32) {
	volatile.StoreUint32(&o.REG_Q4_WORD1.Reg, value)
}
func (o *UHCI_Type) GetREG_Q4_WORD1() uint32 {
	return volatile.LoadUint32(&o.REG_Q4_WORD1.Reg)
}

// UHCI.REG_Q5_WORD0: UHCI Q5_WORD0 Quick Send Register
func (o *UHCI_Type) SetREG_Q5_WORD0(value uint32) {
	volatile.StoreUint32(&o.REG_Q5_WORD0.Reg, value)
}
func (o *UHCI_Type) GetREG_Q5_WORD0() uint32 {
	return volatile.LoadUint32(&o.REG_Q5_WORD0.Reg)
}

// UHCI.REG_Q5_WORD1: UHCI Q5_WORD1 Quick Send Register
func (o *UHCI_Type) SetREG_Q5_WORD1(value uint32) {
	volatile.StoreUint32(&o.REG_Q5_WORD1.Reg, value)
}
func (o *UHCI_Type) GetREG_Q5_WORD1() uint32 {
	return volatile.LoadUint32(&o.REG_Q5_WORD1.Reg)
}

// UHCI.REG_Q6_WORD0: UHCI Q6_WORD0 Quick Send Register
func (o *UHCI_Type) SetREG_Q6_WORD0(value uint32) {
	volatile.StoreUint32(&o.REG_Q6_WORD0.Reg, value)
}
func (o *UHCI_Type) GetREG_Q6_WORD0() uint32 {
	return volatile.LoadUint32(&o.REG_Q6_WORD0.Reg)
}

// UHCI.REG_Q6_WORD1: UHCI Q6_WORD1 Quick Send Register
func (o *UHCI_Type) SetREG_Q6_WORD1(value uint32) {
	volatile.StoreUint32(&o.REG_Q6_WORD1.Reg, value)
}
func (o *UHCI_Type) GetREG_Q6_WORD1() uint32 {
	return volatile.LoadUint32(&o.REG_Q6_WORD1.Reg)
}

// UHCI.ESC_CONF0: UHCI Escapes Sequence Configuration Register0
func (o *UHCI_Type) SetESC_CONF0_SEPER_CHAR(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff)|value)
}
func (o *UHCI_Type) GetESC_CONF0_SEPER_CHAR() uint32 {
	return volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff
}
func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR0(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff00)|value<<8)
}
func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR0() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff00) >> 8
}
func (o *UHCI_Type) SetESC_CONF0_SEPER_ESC_CHAR1(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF0.Reg, volatile.LoadUint32(&o.ESC_CONF0.Reg)&^(0xff0000)|value<<16)
}
func (o *UHCI_Type) GetESC_CONF0_SEPER_ESC_CHAR1() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF0.Reg) & 0xff0000) >> 16
}

// UHCI.ESC_CONF1: UHCI Escapes Sequence Configuration Register1
func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff)|value)
}
func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0() uint32 {
	return volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff
}
func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR0(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff00)|value<<8)
}
func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR0() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff00) >> 8
}
func (o *UHCI_Type) SetESC_CONF1_ESC_SEQ0_CHAR1(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF1.Reg, volatile.LoadUint32(&o.ESC_CONF1.Reg)&^(0xff0000)|value<<16)
}
func (o *UHCI_Type) GetESC_CONF1_ESC_SEQ0_CHAR1() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF1.Reg) & 0xff0000) >> 16
}

// UHCI.ESC_CONF2: UHCI Escapes Sequence Configuration Register2
func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff)|value)
}
func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1() uint32 {
	return volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff
}
func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR0(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff00)|value<<8)
}
func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR0() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff00) >> 8
}
func (o *UHCI_Type) SetESC_CONF2_ESC_SEQ1_CHAR1(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF2.Reg, volatile.LoadUint32(&o.ESC_CONF2.Reg)&^(0xff0000)|value<<16)
}
func (o *UHCI_Type) GetESC_CONF2_ESC_SEQ1_CHAR1() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF2.Reg) & 0xff0000) >> 16
}

// UHCI.ESC_CONF3: UHCI Escapes Sequence Configuration Register3
func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff)|value)
}
func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2() uint32 {
	return volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff
}
func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR0(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff00)|value<<8)
}
func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR0() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff00) >> 8
}
func (o *UHCI_Type) SetESC_CONF3_ESC_SEQ2_CHAR1(value uint32) {
	volatile.StoreUint32(&o.ESC_CONF3.Reg, volatile.LoadUint32(&o.ESC_CONF3.Reg)&^(0xff0000)|value<<16)
}
func (o *UHCI_Type) GetESC_CONF3_ESC_SEQ2_CHAR1() uint32 {
	return (volatile.LoadUint32(&o.ESC_CONF3.Reg) & 0xff0000) >> 16
}

// UHCI.PKT_THRES: UCHI Packet Length Configuration Register
func (o *UHCI_Type) SetPKT_THRES_PKT_THRS(value uint32) {
	volatile.StoreUint32(&o.PKT_THRES.Reg, volatile.LoadUint32(&o.PKT_THRES.Reg)&^(0x1fff)|value)
}
func (o *UHCI_Type) GetPKT_THRES_PKT_THRS() uint32 {
	return volatile.LoadUint32(&o.PKT_THRES.Reg) & 0x1fff
}

// UHCI.DATE: UHCI Version Register
func (o *UHCI_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *UHCI_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// Full-speed USB Serial/JTAG Controller
type USB_DEVICE_Type struct {
	EP1               volatile.Register32 // 0x0
	EP1_CONF          volatile.Register32 // 0x4
	INT_RAW           volatile.Register32 // 0x8
	INT_ST            volatile.Register32 // 0xC
	INT_ENA           volatile.Register32 // 0x10
	INT_CLR           volatile.Register32 // 0x14
	CONF0             volatile.Register32 // 0x18
	TEST              volatile.Register32 // 0x1C
	JFIFO_ST          volatile.Register32 // 0x20
	FRAM_NUM          volatile.Register32 // 0x24
	IN_EP0_ST         volatile.Register32 // 0x28
	IN_EP1_ST         volatile.Register32 // 0x2C
	IN_EP2_ST         volatile.Register32 // 0x30
	IN_EP3_ST         volatile.Register32 // 0x34
	OUT_EP0_ST        volatile.Register32 // 0x38
	OUT_EP1_ST        volatile.Register32 // 0x3C
	OUT_EP2_ST        volatile.Register32 // 0x40
	MISC_CONF         volatile.Register32 // 0x44
	MEM_CONF          volatile.Register32 // 0x48
	CHIP_RST          volatile.Register32 // 0x4C
	SET_LINE_CODE_W0  volatile.Register32 // 0x50
	SET_LINE_CODE_W1  volatile.Register32 // 0x54
	GET_LINE_CODE_W0  volatile.Register32 // 0x58
	GET_LINE_CODE_W1  volatile.Register32 // 0x5C
	CONFIG_UPDATE     volatile.Register32 // 0x60
	SER_AFIFO_CONFIG  volatile.Register32 // 0x64
	BUS_RESET_ST      volatile.Register32 // 0x68
	ECO_LOW_48        volatile.Register32 // 0x6C
	ECO_HIGH_48       volatile.Register32 // 0x70
	ECO_CELL_CTRL_48  volatile.Register32 // 0x74
	ECO_LOW_APB       volatile.Register32 // 0x78
	ECO_HIGH_APB      volatile.Register32 // 0x7C
	ECO_CELL_CTRL_APB volatile.Register32 // 0x80
	SRAM_CTRL         volatile.Register32 // 0x84
	DATE              volatile.Register32 // 0x88
}

// USB_DEVICE.EP1: FIFO access for the CDC-ACM data IN and OUT endpoints.
func (o *USB_DEVICE_Type) SetEP1_USB_SERIAL_JTAG_RDWR_BYTE(value uint32) {
	volatile.StoreUint32(&o.EP1.Reg, volatile.LoadUint32(&o.EP1.Reg)&^(0xff)|value)
}
func (o *USB_DEVICE_Type) GetEP1_USB_SERIAL_JTAG_RDWR_BYTE() uint32 {
	return volatile.LoadUint32(&o.EP1.Reg) & 0xff
}

// USB_DEVICE.EP1_CONF: Configuration and control registers for the CDC-ACM FIFOs.
func (o *USB_DEVICE_Type) SetEP1_CONF_USB_SERIAL_JTAG_WR_DONE(value uint32) {
	volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetEP1_CONF_USB_SERIAL_JTAG_WR_DONE() uint32 {
	return volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetEP1_CONF_USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE(value uint32) {
	volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetEP1_CONF_USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE() uint32 {
	return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetEP1_CONF_USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL(value uint32) {
	volatile.StoreUint32(&o.EP1_CONF.Reg, volatile.LoadUint32(&o.EP1_CONF.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetEP1_CONF_USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL() uint32 {
	return (volatile.LoadUint32(&o.EP1_CONF.Reg) & 0x4) >> 2
}

// USB_DEVICE.INT_RAW: Interrupt raw status register.
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW() uint32 {
	return volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SOF_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SOF_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8)|value<<3)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8) >> 3
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_PID_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x10)|value<<4)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_PID_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x10) >> 4
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_CRC5_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x20)|value<<5)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_CRC5_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x20) >> 5
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_CRC16_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x40)|value<<6)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_CRC16_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x40) >> 6
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_STUFF_ERR_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x80)|value<<7)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_STUFF_ERR_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x80) >> 7
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x100)|value<<8)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x100) >> 8
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x200)|value<<9)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x200) >> 9
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x400)|value<<10)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x400) >> 10
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x800)|value<<11)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x800) >> 11
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_RTS_CHG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x1000)|value<<12)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_RTS_CHG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x1000) >> 12
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_DTR_CHG_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x2000)|value<<13)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_DTR_CHG_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x2000) >> 13
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x4000)|value<<14)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x4000) >> 14
}
func (o *USB_DEVICE_Type) SetINT_RAW_USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW(value uint32) {
	volatile.StoreUint32(&o.INT_RAW.Reg, volatile.LoadUint32(&o.INT_RAW.Reg)&^(0x8000)|value<<15)
}
func (o *USB_DEVICE_Type) GetINT_RAW_USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW() uint32 {
	return (volatile.LoadUint32(&o.INT_RAW.Reg) & 0x8000) >> 15
}

// USB_DEVICE.INT_ST: Interrupt status register.
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST() uint32 {
	return volatile.LoadUint32(&o.INT_ST.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SOF_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SOF_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8)|value<<3)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8) >> 3
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_PID_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x10)|value<<4)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_PID_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x10) >> 4
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_CRC5_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x20)|value<<5)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_CRC5_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x20) >> 5
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_CRC16_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x40)|value<<6)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_CRC16_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x40) >> 6
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_STUFF_ERR_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x80)|value<<7)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_STUFF_ERR_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x80) >> 7
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x100)|value<<8)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x100) >> 8
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x200)|value<<9)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x200) >> 9
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x400)|value<<10)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x400) >> 10
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x800)|value<<11)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x800) >> 11
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_RTS_CHG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x1000)|value<<12)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_RTS_CHG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x1000) >> 12
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_DTR_CHG_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x2000)|value<<13)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_DTR_CHG_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x2000) >> 13
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x4000)|value<<14)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x4000) >> 14
}
func (o *USB_DEVICE_Type) SetINT_ST_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST(value uint32) {
	volatile.StoreUint32(&o.INT_ST.Reg, volatile.LoadUint32(&o.INT_ST.Reg)&^(0x8000)|value<<15)
}
func (o *USB_DEVICE_Type) GetINT_ST_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST() uint32 {
	return (volatile.LoadUint32(&o.INT_ST.Reg) & 0x8000) >> 15
}

// USB_DEVICE.INT_ENA: Interrupt enable status register.
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA() uint32 {
	return volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SOF_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SOF_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8)|value<<3)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8) >> 3
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_PID_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x10)|value<<4)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_PID_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x10) >> 4
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_CRC5_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x20)|value<<5)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_CRC5_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x20) >> 5
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_CRC16_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x40)|value<<6)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_CRC16_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x40) >> 6
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_STUFF_ERR_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x80)|value<<7)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_STUFF_ERR_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x80) >> 7
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x100)|value<<8)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x100) >> 8
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x200)|value<<9)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x200) >> 9
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x400)|value<<10)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x400) >> 10
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x800)|value<<11)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x800) >> 11
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_RTS_CHG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x1000)|value<<12)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_RTS_CHG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x1000) >> 12
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_DTR_CHG_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x2000)|value<<13)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_DTR_CHG_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x2000) >> 13
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x4000)|value<<14)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x4000) >> 14
}
func (o *USB_DEVICE_Type) SetINT_ENA_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA(value uint32) {
	volatile.StoreUint32(&o.INT_ENA.Reg, volatile.LoadUint32(&o.INT_ENA.Reg)&^(0x8000)|value<<15)
}
func (o *USB_DEVICE_Type) GetINT_ENA_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA() uint32 {
	return (volatile.LoadUint32(&o.INT_ENA.Reg) & 0x8000) >> 15
}

// USB_DEVICE.INT_CLR: Interrupt clear status register.
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR() uint32 {
	return volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SOF_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SOF_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8)|value<<3)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8) >> 3
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_PID_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x10)|value<<4)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_PID_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x10) >> 4
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_CRC5_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x20)|value<<5)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_CRC5_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x20) >> 5
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_CRC16_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x40)|value<<6)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_CRC16_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x40) >> 6
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_STUFF_ERR_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x80)|value<<7)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_STUFF_ERR_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x80) >> 7
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x100)|value<<8)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x100) >> 8
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x200)|value<<9)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x200) >> 9
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x400)|value<<10)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x400) >> 10
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x800)|value<<11)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x800) >> 11
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_RTS_CHG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x1000)|value<<12)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_RTS_CHG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x1000) >> 12
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_DTR_CHG_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x2000)|value<<13)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_DTR_CHG_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x2000) >> 13
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x4000)|value<<14)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x4000) >> 14
}
func (o *USB_DEVICE_Type) SetINT_CLR_USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR(value uint32) {
	volatile.StoreUint32(&o.INT_CLR.Reg, volatile.LoadUint32(&o.INT_CLR.Reg)&^(0x8000)|value<<15)
}
func (o *USB_DEVICE_Type) GetINT_CLR_USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR() uint32 {
	return (volatile.LoadUint32(&o.INT_CLR.Reg) & 0x8000) >> 15
}

// USB_DEVICE.CONF0: PHY hardware configuration.
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_PHY_SEL(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_PHY_SEL() uint32 {
	return volatile.LoadUint32(&o.CONF0.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_EXCHG_PINS(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_EXCHG_PINS() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_VREFH(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x18)|value<<3)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_VREFH() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x18) >> 3
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_VREFL(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x60)|value<<5)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_VREFL() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x60) >> 5
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_VREF_OVERRIDE(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x80)|value<<7)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_VREF_OVERRIDE() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x80) >> 7
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_PAD_PULL_OVERRIDE(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x100)|value<<8)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_PAD_PULL_OVERRIDE() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x100) >> 8
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DP_PULLUP(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x200)|value<<9)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DP_PULLUP() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x200) >> 9
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DP_PULLDOWN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x400)|value<<10)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DP_PULLDOWN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x400) >> 10
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DM_PULLUP(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x800)|value<<11)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DM_PULLUP() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x800) >> 11
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_DM_PULLDOWN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x1000)|value<<12)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_DM_PULLDOWN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x1000) >> 12
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_PULLUP_VALUE(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x2000)|value<<13)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_PULLUP_VALUE() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x2000) >> 13
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_USB_PAD_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x4000)|value<<14)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_USB_PAD_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x4000) >> 14
}
func (o *USB_DEVICE_Type) SetCONF0_USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN(value uint32) {
	volatile.StoreUint32(&o.CONF0.Reg, volatile.LoadUint32(&o.CONF0.Reg)&^(0x8000)|value<<15)
}
func (o *USB_DEVICE_Type) GetCONF0_USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN() uint32 {
	return (volatile.LoadUint32(&o.CONF0.Reg) & 0x8000) >> 15
}

// USB_DEVICE.TEST: Registers used for debugging the PHY.
func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_ENABLE(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_ENABLE() uint32 {
	return volatile.LoadUint32(&o.TEST.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_USB_OE(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_USB_OE() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_TX_DP(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_TX_DP() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_TX_DM(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x8)|value<<3)
}
func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_TX_DM() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x8) >> 3
}
func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_RX_RCV(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x10)|value<<4)
}
func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_RX_RCV() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x10) >> 4
}
func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_RX_DP(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x20)|value<<5)
}
func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_RX_DP() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x20) >> 5
}
func (o *USB_DEVICE_Type) SetTEST_USB_SERIAL_JTAG_TEST_RX_DM(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x40)|value<<6)
}
func (o *USB_DEVICE_Type) GetTEST_USB_SERIAL_JTAG_TEST_RX_DM() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x40) >> 6
}

// USB_DEVICE.JFIFO_ST: JTAG FIFO status and control registers.
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_CNT() uint32 {
	return volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x8)|value<<3)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x8) >> 3
}
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_CNT(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x30)|value<<4)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_CNT() uint32 {
	return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x30) >> 4
}
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_EMPTY(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x40)|value<<6)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_EMPTY() uint32 {
	return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x40) >> 6
}
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_FULL(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x80)|value<<7)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_FULL() uint32 {
	return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x80) >> 7
}
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x100)|value<<8)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x100) >> 8
}
func (o *USB_DEVICE_Type) SetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_RESET(value uint32) {
	volatile.StoreUint32(&o.JFIFO_ST.Reg, volatile.LoadUint32(&o.JFIFO_ST.Reg)&^(0x200)|value<<9)
}
func (o *USB_DEVICE_Type) GetJFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_RESET() uint32 {
	return (volatile.LoadUint32(&o.JFIFO_ST.Reg) & 0x200) >> 9
}

// USB_DEVICE.FRAM_NUM: Last received SOF frame index register.
func (o *USB_DEVICE_Type) SetFRAM_NUM_USB_SERIAL_JTAG_SOF_FRAME_INDEX(value uint32) {
	volatile.StoreUint32(&o.FRAM_NUM.Reg, volatile.LoadUint32(&o.FRAM_NUM.Reg)&^(0x7ff)|value)
}
func (o *USB_DEVICE_Type) GetFRAM_NUM_USB_SERIAL_JTAG_SOF_FRAME_INDEX() uint32 {
	return volatile.LoadUint32(&o.FRAM_NUM.Reg) & 0x7ff
}

// USB_DEVICE.IN_EP0_ST: Control IN endpoint status information.
func (o *USB_DEVICE_Type) SetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_STATE(value uint32) {
	volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_STATE() uint32 {
	return volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_WR_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0x1fc)|value<<2)
}
func (o *USB_DEVICE_Type) GetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_WR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0x1fc) >> 2
}
func (o *USB_DEVICE_Type) SetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_RD_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP0_ST.Reg, volatile.LoadUint32(&o.IN_EP0_ST.Reg)&^(0xfe00)|value<<9)
}
func (o *USB_DEVICE_Type) GetIN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_RD_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP0_ST.Reg) & 0xfe00) >> 9
}

// USB_DEVICE.IN_EP1_ST: CDC-ACM IN endpoint status information.
func (o *USB_DEVICE_Type) SetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_STATE(value uint32) {
	volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_STATE() uint32 {
	return volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_WR_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0x1fc)|value<<2)
}
func (o *USB_DEVICE_Type) GetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_WR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0x1fc) >> 2
}
func (o *USB_DEVICE_Type) SetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_RD_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP1_ST.Reg, volatile.LoadUint32(&o.IN_EP1_ST.Reg)&^(0xfe00)|value<<9)
}
func (o *USB_DEVICE_Type) GetIN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_RD_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP1_ST.Reg) & 0xfe00) >> 9
}

// USB_DEVICE.IN_EP2_ST: CDC-ACM interrupt IN endpoint status information.
func (o *USB_DEVICE_Type) SetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_STATE(value uint32) {
	volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_STATE() uint32 {
	return volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_WR_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0x1fc)|value<<2)
}
func (o *USB_DEVICE_Type) GetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_WR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0x1fc) >> 2
}
func (o *USB_DEVICE_Type) SetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_RD_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP2_ST.Reg, volatile.LoadUint32(&o.IN_EP2_ST.Reg)&^(0xfe00)|value<<9)
}
func (o *USB_DEVICE_Type) GetIN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_RD_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP2_ST.Reg) & 0xfe00) >> 9
}

// USB_DEVICE.IN_EP3_ST: JTAG IN endpoint status information.
func (o *USB_DEVICE_Type) SetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_STATE(value uint32) {
	volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_STATE() uint32 {
	return volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_WR_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0x1fc)|value<<2)
}
func (o *USB_DEVICE_Type) GetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_WR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0x1fc) >> 2
}
func (o *USB_DEVICE_Type) SetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_RD_ADDR(value uint32) {
	volatile.StoreUint32(&o.IN_EP3_ST.Reg, volatile.LoadUint32(&o.IN_EP3_ST.Reg)&^(0xfe00)|value<<9)
}
func (o *USB_DEVICE_Type) GetIN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_RD_ADDR() uint32 {
	return (volatile.LoadUint32(&o.IN_EP3_ST.Reg) & 0xfe00) >> 9
}

// USB_DEVICE.OUT_EP0_ST: Control OUT endpoint status information.
func (o *USB_DEVICE_Type) SetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_STATE(value uint32) {
	volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_STATE() uint32 {
	return volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_WR_ADDR(value uint32) {
	volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0x1fc)|value<<2)
}
func (o *USB_DEVICE_Type) GetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_WR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0x1fc) >> 2
}
func (o *USB_DEVICE_Type) SetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_RD_ADDR(value uint32) {
	volatile.StoreUint32(&o.OUT_EP0_ST.Reg, volatile.LoadUint32(&o.OUT_EP0_ST.Reg)&^(0xfe00)|value<<9)
}
func (o *USB_DEVICE_Type) GetOUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_RD_ADDR() uint32 {
	return (volatile.LoadUint32(&o.OUT_EP0_ST.Reg) & 0xfe00) >> 9
}

// USB_DEVICE.OUT_EP1_ST: CDC-ACM OUT endpoint status information.
func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_STATE(value uint32) {
	volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_STATE() uint32 {
	return volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_WR_ADDR(value uint32) {
	volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x1fc)|value<<2)
}
func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_WR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x1fc) >> 2
}
func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_RD_ADDR(value uint32) {
	volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0xfe00)|value<<9)
}
func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_RD_ADDR() uint32 {
	return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0xfe00) >> 9
}
func (o *USB_DEVICE_Type) SetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT(value uint32) {
	volatile.StoreUint32(&o.OUT_EP1_ST.Reg, volatile.LoadUint32(&o.OUT_EP1_ST.Reg)&^(0x7f0000)|value<<16)
}
func (o *USB_DEVICE_Type) GetOUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT() uint32 {
	return (volatile.LoadUint32(&o.OUT_EP1_ST.Reg) & 0x7f0000) >> 16
}

// USB_DEVICE.OUT_EP2_ST: JTAG OUT endpoint status information.
func (o *USB_DEVICE_Type) SetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_STATE(value uint32) {
	volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x3)|value)
}
func (o *USB_DEVICE_Type) GetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_STATE() uint32 {
	return volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x3
}
func (o *USB_DEVICE_Type) SetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_WR_ADDR(value uint32) {
	volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0x1fc)|value<<2)
}
func (o *USB_DEVICE_Type) GetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_WR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0x1fc) >> 2
}
func (o *USB_DEVICE_Type) SetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_RD_ADDR(value uint32) {
	volatile.StoreUint32(&o.OUT_EP2_ST.Reg, volatile.LoadUint32(&o.OUT_EP2_ST.Reg)&^(0xfe00)|value<<9)
}
func (o *USB_DEVICE_Type) GetOUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_RD_ADDR() uint32 {
	return (volatile.LoadUint32(&o.OUT_EP2_ST.Reg) & 0xfe00) >> 9
}

// USB_DEVICE.MISC_CONF: Clock enable control
func (o *USB_DEVICE_Type) SetMISC_CONF_USB_SERIAL_JTAG_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.MISC_CONF.Reg, volatile.LoadUint32(&o.MISC_CONF.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetMISC_CONF_USB_SERIAL_JTAG_CLK_EN() uint32 {
	return volatile.LoadUint32(&o.MISC_CONF.Reg) & 0x1
}

// USB_DEVICE.MEM_CONF: Memory power control
func (o *USB_DEVICE_Type) SetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_PD(value uint32) {
	volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_PD() uint32 {
	return volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.MEM_CONF.Reg, volatile.LoadUint32(&o.MEM_CONF.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetMEM_CONF_USB_SERIAL_JTAG_USB_MEM_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.MEM_CONF.Reg) & 0x2) >> 1
}

// USB_DEVICE.CHIP_RST: CDC-ACM chip reset control.
func (o *USB_DEVICE_Type) SetCHIP_RST_USB_SERIAL_JTAG_RTS(value uint32) {
	volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetCHIP_RST_USB_SERIAL_JTAG_RTS() uint32 {
	return volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetCHIP_RST_USB_SERIAL_JTAG_DTR(value uint32) {
	volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetCHIP_RST_USB_SERIAL_JTAG_DTR() uint32 {
	return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetCHIP_RST_USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS(value uint32) {
	volatile.StoreUint32(&o.CHIP_RST.Reg, volatile.LoadUint32(&o.CHIP_RST.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetCHIP_RST_USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS() uint32 {
	return (volatile.LoadUint32(&o.CHIP_RST.Reg) & 0x4) >> 2
}

// USB_DEVICE.SET_LINE_CODE_W0: W0 of SET_LINE_CODING command.
func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W0(value uint32) {
	volatile.StoreUint32(&o.SET_LINE_CODE_W0.Reg, value)
}
func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W0() uint32 {
	return volatile.LoadUint32(&o.SET_LINE_CODE_W0.Reg)
}

// USB_DEVICE.SET_LINE_CODE_W1: W1 of SET_LINE_CODING command.
func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BCHAR_FORMAT(value uint32) {
	volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff)|value)
}
func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BCHAR_FORMAT() uint32 {
	return volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff
}
func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BPARITY_TYPE(value uint32) {
	volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8)
}
func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BPARITY_TYPE() uint32 {
	return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff00) >> 8
}
func (o *USB_DEVICE_Type) SetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BDATA_BITS(value uint32) {
	volatile.StoreUint32(&o.SET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16)
}
func (o *USB_DEVICE_Type) GetSET_LINE_CODE_W1_USB_SERIAL_JTAG_BDATA_BITS() uint32 {
	return (volatile.LoadUint32(&o.SET_LINE_CODE_W1.Reg) & 0xff0000) >> 16
}

// USB_DEVICE.GET_LINE_CODE_W0: W0 of GET_LINE_CODING command.
func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W0(value uint32) {
	volatile.StoreUint32(&o.GET_LINE_CODE_W0.Reg, value)
}
func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W0() uint32 {
	return volatile.LoadUint32(&o.GET_LINE_CODE_W0.Reg)
}

// USB_DEVICE.GET_LINE_CODE_W1: W1 of GET_LINE_CODING command.
func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BDATA_BITS(value uint32) {
	volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff)|value)
}
func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BDATA_BITS() uint32 {
	return volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff
}
func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BPARITY_TYPE(value uint32) {
	volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff00)|value<<8)
}
func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BPARITY_TYPE() uint32 {
	return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff00) >> 8
}
func (o *USB_DEVICE_Type) SetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BCHAR_FORMAT(value uint32) {
	volatile.StoreUint32(&o.GET_LINE_CODE_W1.Reg, volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg)&^(0xff0000)|value<<16)
}
func (o *USB_DEVICE_Type) GetGET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BCHAR_FORMAT() uint32 {
	return (volatile.LoadUint32(&o.GET_LINE_CODE_W1.Reg) & 0xff0000) >> 16
}

// USB_DEVICE.CONFIG_UPDATE: Configuration registers' value update
func (o *USB_DEVICE_Type) SetCONFIG_UPDATE_USB_SERIAL_JTAG_CONFIG_UPDATE(value uint32) {
	volatile.StoreUint32(&o.CONFIG_UPDATE.Reg, volatile.LoadUint32(&o.CONFIG_UPDATE.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetCONFIG_UPDATE_USB_SERIAL_JTAG_CONFIG_UPDATE() uint32 {
	return volatile.LoadUint32(&o.CONFIG_UPDATE.Reg) & 0x1
}

// USB_DEVICE.SER_AFIFO_CONFIG: Serial AFIFO configure register
func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR(value uint32) {
	volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR() uint32 {
	return volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD(value uint32) {
	volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD() uint32 {
	return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x2) >> 1
}
func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR(value uint32) {
	volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x4)|value<<2)
}
func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR() uint32 {
	return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x4) >> 2
}
func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD(value uint32) {
	volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x8)|value<<3)
}
func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD() uint32 {
	return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x8) >> 3
}
func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY(value uint32) {
	volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x10)|value<<4)
}
func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY() uint32 {
	return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x10) >> 4
}
func (o *USB_DEVICE_Type) SetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL(value uint32) {
	volatile.StoreUint32(&o.SER_AFIFO_CONFIG.Reg, volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg)&^(0x20)|value<<5)
}
func (o *USB_DEVICE_Type) GetSER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL() uint32 {
	return (volatile.LoadUint32(&o.SER_AFIFO_CONFIG.Reg) & 0x20) >> 5
}

// USB_DEVICE.BUS_RESET_ST: USB Bus reset status register
func (o *USB_DEVICE_Type) SetBUS_RESET_ST_USB_SERIAL_JTAG_USB_BUS_RESET_ST(value uint32) {
	volatile.StoreUint32(&o.BUS_RESET_ST.Reg, volatile.LoadUint32(&o.BUS_RESET_ST.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetBUS_RESET_ST_USB_SERIAL_JTAG_USB_BUS_RESET_ST() uint32 {
	return volatile.LoadUint32(&o.BUS_RESET_ST.Reg) & 0x1
}

// USB_DEVICE.ECO_LOW_48: Reserved.
func (o *USB_DEVICE_Type) SetECO_LOW_48(value uint32) {
	volatile.StoreUint32(&o.ECO_LOW_48.Reg, value)
}
func (o *USB_DEVICE_Type) GetECO_LOW_48() uint32 {
	return volatile.LoadUint32(&o.ECO_LOW_48.Reg)
}

// USB_DEVICE.ECO_HIGH_48: Reserved.
func (o *USB_DEVICE_Type) SetECO_HIGH_48(value uint32) {
	volatile.StoreUint32(&o.ECO_HIGH_48.Reg, value)
}
func (o *USB_DEVICE_Type) GetECO_HIGH_48() uint32 {
	return volatile.LoadUint32(&o.ECO_HIGH_48.Reg)
}

// USB_DEVICE.ECO_CELL_CTRL_48: Reserved.
func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_RESULT_48(value uint32) {
	volatile.StoreUint32(&o.ECO_CELL_CTRL_48.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_RESULT_48() uint32 {
	return volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_ENA_48(value uint32) {
	volatile.StoreUint32(&o.ECO_CELL_CTRL_48.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_ENA_48() uint32 {
	return (volatile.LoadUint32(&o.ECO_CELL_CTRL_48.Reg) & 0x2) >> 1
}

// USB_DEVICE.ECO_LOW_APB: Reserved.
func (o *USB_DEVICE_Type) SetECO_LOW_APB(value uint32) {
	volatile.StoreUint32(&o.ECO_LOW_APB.Reg, value)
}
func (o *USB_DEVICE_Type) GetECO_LOW_APB() uint32 {
	return volatile.LoadUint32(&o.ECO_LOW_APB.Reg)
}

// USB_DEVICE.ECO_HIGH_APB: Reserved.
func (o *USB_DEVICE_Type) SetECO_HIGH_APB(value uint32) {
	volatile.StoreUint32(&o.ECO_HIGH_APB.Reg, value)
}
func (o *USB_DEVICE_Type) GetECO_HIGH_APB() uint32 {
	return volatile.LoadUint32(&o.ECO_HIGH_APB.Reg)
}

// USB_DEVICE.ECO_CELL_CTRL_APB: Reserved.
func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_RESULT_APB(value uint32) {
	volatile.StoreUint32(&o.ECO_CELL_CTRL_APB.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg)&^(0x1)|value)
}
func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_RESULT_APB() uint32 {
	return volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg) & 0x1
}
func (o *USB_DEVICE_Type) SetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_ENA_APB(value uint32) {
	volatile.StoreUint32(&o.ECO_CELL_CTRL_APB.Reg, volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg)&^(0x2)|value<<1)
}
func (o *USB_DEVICE_Type) GetECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_ENA_APB() uint32 {
	return (volatile.LoadUint32(&o.ECO_CELL_CTRL_APB.Reg) & 0x2) >> 1
}

// USB_DEVICE.SRAM_CTRL: PPA SRAM Control Register
func (o *USB_DEVICE_Type) SetSRAM_CTRL_USB_SERIAL_JTAG_MEM_AUX_CTRL(value uint32) {
	volatile.StoreUint32(&o.SRAM_CTRL.Reg, volatile.LoadUint32(&o.SRAM_CTRL.Reg)&^(0x3fff)|value)
}
func (o *USB_DEVICE_Type) GetSRAM_CTRL_USB_SERIAL_JTAG_MEM_AUX_CTRL() uint32 {
	return volatile.LoadUint32(&o.SRAM_CTRL.Reg) & 0x3fff
}

// USB_DEVICE.DATE: Date register
func (o *USB_DEVICE_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *USB_DEVICE_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// USB_WRAP Peripheral
type USB_WRAP_Type struct {
	OTG_CONF  volatile.Register32 // 0x0
	TEST_CONF volatile.Register32 // 0x4
	_         [1012]byte
	DATE      volatile.Register32 // 0x3FC
}

// USB_WRAP.OTG_CONF: USB wrapper configuration registers.
func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_OVERRIDE(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1)|value)
}
func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_OVERRIDE() uint32 {
	return volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1
}
func (o *USB_WRAP_Type) SetOTG_CONF_SRP_SESSEND_VALUE(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2)|value<<1)
}
func (o *USB_WRAP_Type) GetOTG_CONF_SRP_SESSEND_VALUE() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2) >> 1
}
func (o *USB_WRAP_Type) SetOTG_CONF_PHY_SEL(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4)|value<<2)
}
func (o *USB_WRAP_Type) GetOTG_CONF_PHY_SEL() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4) >> 2
}
func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PD(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8)|value<<3)
}
func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PD() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8) >> 3
}
func (o *USB_WRAP_Type) SetOTG_CONF_DBNCE_FLTR_BYPASS(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10)|value<<4)
}
func (o *USB_WRAP_Type) GetOTG_CONF_DBNCE_FLTR_BYPASS() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10) >> 4
}
func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS_OVERRIDE(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20)|value<<5)
}
func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS_OVERRIDE() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20) >> 5
}
func (o *USB_WRAP_Type) SetOTG_CONF_EXCHG_PINS(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40)|value<<6)
}
func (o *USB_WRAP_Type) GetOTG_CONF_EXCHG_PINS() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40) >> 6
}
func (o *USB_WRAP_Type) SetOTG_CONF_VREFH(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x180)|value<<7)
}
func (o *USB_WRAP_Type) GetOTG_CONF_VREFH() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x180) >> 7
}
func (o *USB_WRAP_Type) SetOTG_CONF_VREFL(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x600)|value<<9)
}
func (o *USB_WRAP_Type) GetOTG_CONF_VREFL() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x600) >> 9
}
func (o *USB_WRAP_Type) SetOTG_CONF_VREF_OVERRIDE(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x800)|value<<11)
}
func (o *USB_WRAP_Type) GetOTG_CONF_VREF_OVERRIDE() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x800) >> 11
}
func (o *USB_WRAP_Type) SetOTG_CONF_PAD_PULL_OVERRIDE(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x1000)|value<<12)
}
func (o *USB_WRAP_Type) GetOTG_CONF_PAD_PULL_OVERRIDE() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x1000) >> 12
}
func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLUP(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x2000)|value<<13)
}
func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLUP() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x2000) >> 13
}
func (o *USB_WRAP_Type) SetOTG_CONF_DP_PULLDOWN(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x4000)|value<<14)
}
func (o *USB_WRAP_Type) GetOTG_CONF_DP_PULLDOWN() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x4000) >> 14
}
func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLUP(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x8000)|value<<15)
}
func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLUP() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x8000) >> 15
}
func (o *USB_WRAP_Type) SetOTG_CONF_DM_PULLDOWN(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x10000)|value<<16)
}
func (o *USB_WRAP_Type) GetOTG_CONF_DM_PULLDOWN() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x10000) >> 16
}
func (o *USB_WRAP_Type) SetOTG_CONF_PULLUP_VALUE(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x20000)|value<<17)
}
func (o *USB_WRAP_Type) GetOTG_CONF_PULLUP_VALUE() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x20000) >> 17
}
func (o *USB_WRAP_Type) SetOTG_CONF_USB_PAD_ENABLE(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x40000)|value<<18)
}
func (o *USB_WRAP_Type) GetOTG_CONF_USB_PAD_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x40000) >> 18
}
func (o *USB_WRAP_Type) SetOTG_CONF_AHB_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000)|value<<19)
}
func (o *USB_WRAP_Type) GetOTG_CONF_AHB_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000) >> 19
}
func (o *USB_WRAP_Type) SetOTG_CONF_PHY_CLK_FORCE_ON(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x100000)|value<<20)
}
func (o *USB_WRAP_Type) GetOTG_CONF_PHY_CLK_FORCE_ON() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x100000) >> 20
}
func (o *USB_WRAP_Type) SetOTG_CONF_PHY_TX_EDGE_SEL(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x200000)|value<<21)
}
func (o *USB_WRAP_Type) GetOTG_CONF_PHY_TX_EDGE_SEL() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x200000) >> 21
}
func (o *USB_WRAP_Type) SetOTG_CONF_DFIFO_FORCE_PU(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x400000)|value<<22)
}
func (o *USB_WRAP_Type) GetOTG_CONF_DFIFO_FORCE_PU() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x400000) >> 22
}
func (o *USB_WRAP_Type) SetOTG_CONF_CLK_EN(value uint32) {
	volatile.StoreUint32(&o.OTG_CONF.Reg, volatile.LoadUint32(&o.OTG_CONF.Reg)&^(0x80000000)|value<<31)
}
func (o *USB_WRAP_Type) GetOTG_CONF_CLK_EN() uint32 {
	return (volatile.LoadUint32(&o.OTG_CONF.Reg) & 0x80000000) >> 31
}

// USB_WRAP.TEST_CONF: USB wrapper test configuration registers.
func (o *USB_WRAP_Type) SetTEST_CONF_TEST_ENABLE(value uint32) {
	volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x1)|value)
}
func (o *USB_WRAP_Type) GetTEST_CONF_TEST_ENABLE() uint32 {
	return volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x1
}
func (o *USB_WRAP_Type) SetTEST_CONF_TEST_USB_OE(value uint32) {
	volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x2)|value<<1)
}
func (o *USB_WRAP_Type) GetTEST_CONF_TEST_USB_OE() uint32 {
	return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x2) >> 1
}
func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DP(value uint32) {
	volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x4)|value<<2)
}
func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DP() uint32 {
	return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x4) >> 2
}
func (o *USB_WRAP_Type) SetTEST_CONF_TEST_TX_DM(value uint32) {
	volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x8)|value<<3)
}
func (o *USB_WRAP_Type) GetTEST_CONF_TEST_TX_DM() uint32 {
	return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x8) >> 3
}
func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_RCV(value uint32) {
	volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x10)|value<<4)
}
func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_RCV() uint32 {
	return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x10) >> 4
}
func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DP(value uint32) {
	volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x20)|value<<5)
}
func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DP() uint32 {
	return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x20) >> 5
}
func (o *USB_WRAP_Type) SetTEST_CONF_TEST_RX_DM(value uint32) {
	volatile.StoreUint32(&o.TEST_CONF.Reg, volatile.LoadUint32(&o.TEST_CONF.Reg)&^(0x40)|value<<6)
}
func (o *USB_WRAP_Type) GetTEST_CONF_TEST_RX_DM() uint32 {
	return (volatile.LoadUint32(&o.TEST_CONF.Reg) & 0x40) >> 6
}

// USB_WRAP.DATE: Date register.
func (o *USB_WRAP_Type) SetDATE(value uint32) {
	volatile.StoreUint32(&o.DATE.Reg, value)
}
func (o *USB_WRAP_Type) GetDATE() uint32 {
	return volatile.LoadUint32(&o.DATE.Reg)
}

// Constants for ADC: ADC (Analog to Digital Converter)
const (
	// CTRL: Register
	// Position of START_FORCE field.
	ADC_CTRL_START_FORCE_Pos = 0x0
	// Bit mask of START_FORCE field.
	ADC_CTRL_START_FORCE_Msk = 0x1
	// Bit START_FORCE.
	ADC_CTRL_START_FORCE = 0x1
	// Position of START field.
	ADC_CTRL_START_Pos = 0x1
	// Bit mask of START field.
	ADC_CTRL_START_Msk = 0x2
	// Bit START.
	ADC_CTRL_START = 0x2
	// Position of WORK_MODE field.
	ADC_CTRL_WORK_MODE_Pos = 0x2
	// Bit mask of WORK_MODE field.
	ADC_CTRL_WORK_MODE_Msk = 0xc
	// Position of SAR_SEL field.
	ADC_CTRL_SAR_SEL_Pos = 0x4
	// Bit mask of SAR_SEL field.
	ADC_CTRL_SAR_SEL_Msk = 0x10
	// Bit SAR_SEL.
	ADC_CTRL_SAR_SEL = 0x10
	// Position of SAR_CLK_GATED field.
	ADC_CTRL_SAR_CLK_GATED_Pos = 0x5
	// Bit mask of SAR_CLK_GATED field.
	ADC_CTRL_SAR_CLK_GATED_Msk = 0x20
	// Bit SAR_CLK_GATED.
	ADC_CTRL_SAR_CLK_GATED = 0x20
	// Position of SAR_CLK_DIV field.
	ADC_CTRL_SAR_CLK_DIV_Pos = 0x6
	// Bit mask of SAR_CLK_DIV field.
	ADC_CTRL_SAR_CLK_DIV_Msk = 0x3fc0
	// Position of SAR1_PATT_LEN field.
	ADC_CTRL_SAR1_PATT_LEN_Pos = 0xe
	// Bit mask of SAR1_PATT_LEN field.
	ADC_CTRL_SAR1_PATT_LEN_Msk = 0x3c000
	// Position of SAR2_PATT_LEN field.
	ADC_CTRL_SAR2_PATT_LEN_Pos = 0x12
	// Bit mask of SAR2_PATT_LEN field.
	ADC_CTRL_SAR2_PATT_LEN_Msk = 0x3c0000
	// Position of SAR1_PATT_P_CLEAR field.
	ADC_CTRL_SAR1_PATT_P_CLEAR_Pos = 0x16
	// Bit mask of SAR1_PATT_P_CLEAR field.
	ADC_CTRL_SAR1_PATT_P_CLEAR_Msk = 0x400000
	// Bit SAR1_PATT_P_CLEAR.
	ADC_CTRL_SAR1_PATT_P_CLEAR = 0x400000
	// Position of SAR2_PATT_P_CLEAR field.
	ADC_CTRL_SAR2_PATT_P_CLEAR_Pos = 0x17
	// Bit mask of SAR2_PATT_P_CLEAR field.
	ADC_CTRL_SAR2_PATT_P_CLEAR_Msk = 0x800000
	// Bit SAR2_PATT_P_CLEAR.
	ADC_CTRL_SAR2_PATT_P_CLEAR = 0x800000
	// Position of DATA_SAR_SEL field.
	ADC_CTRL_DATA_SAR_SEL_Pos = 0x18
	// Bit mask of DATA_SAR_SEL field.
	ADC_CTRL_DATA_SAR_SEL_Msk = 0x1000000
	// Bit DATA_SAR_SEL.
	ADC_CTRL_DATA_SAR_SEL = 0x1000000
	// Position of DATA_TO_I2S field.
	ADC_CTRL_DATA_TO_I2S_Pos = 0x19
	// Bit mask of DATA_TO_I2S field.
	ADC_CTRL_DATA_TO_I2S_Msk = 0x2000000
	// Bit DATA_TO_I2S.
	ADC_CTRL_DATA_TO_I2S = 0x2000000
	// Position of XPD_SAR1_FORCE field.
	ADC_CTRL_XPD_SAR1_FORCE_Pos = 0x1a
	// Bit mask of XPD_SAR1_FORCE field.
	ADC_CTRL_XPD_SAR1_FORCE_Msk = 0xc000000
	// Position of XPD_SAR2_FORCE field.
	ADC_CTRL_XPD_SAR2_FORCE_Pos = 0x1c
	// Bit mask of XPD_SAR2_FORCE field.
	ADC_CTRL_XPD_SAR2_FORCE_Msk = 0x30000000
	// Position of WAIT_ARB_CYCLE field.
	ADC_CTRL_WAIT_ARB_CYCLE_Pos = 0x1e
	// Bit mask of WAIT_ARB_CYCLE field.
	ADC_CTRL_WAIT_ARB_CYCLE_Msk = 0xc0000000

	// CTRL2: Register
	// Position of MEAS_NUM_LIMIT field.
	ADC_CTRL2_MEAS_NUM_LIMIT_Pos = 0x0
	// Bit mask of MEAS_NUM_LIMIT field.
	ADC_CTRL2_MEAS_NUM_LIMIT_Msk = 0x1
	// Bit MEAS_NUM_LIMIT.
	ADC_CTRL2_MEAS_NUM_LIMIT = 0x1
	// Position of MAX_MEAS_NUM field.
	ADC_CTRL2_MAX_MEAS_NUM_Pos = 0x1
	// Bit mask of MAX_MEAS_NUM field.
	ADC_CTRL2_MAX_MEAS_NUM_Msk = 0x1fe
	// Position of SAR1_INV field.
	ADC_CTRL2_SAR1_INV_Pos = 0x9
	// Bit mask of SAR1_INV field.
	ADC_CTRL2_SAR1_INV_Msk = 0x200
	// Bit SAR1_INV.
	ADC_CTRL2_SAR1_INV = 0x200
	// Position of SAR2_INV field.
	ADC_CTRL2_SAR2_INV_Pos = 0xa
	// Bit mask of SAR2_INV field.
	ADC_CTRL2_SAR2_INV_Msk = 0x400
	// Bit SAR2_INV.
	ADC_CTRL2_SAR2_INV = 0x400
	// Position of TIMER_SEL field.
	ADC_CTRL2_TIMER_SEL_Pos = 0xb
	// Bit mask of TIMER_SEL field.
	ADC_CTRL2_TIMER_SEL_Msk = 0x800
	// Bit TIMER_SEL.
	ADC_CTRL2_TIMER_SEL = 0x800
	// Position of TIMER_TARGET field.
	ADC_CTRL2_TIMER_TARGET_Pos = 0xc
	// Bit mask of TIMER_TARGET field.
	ADC_CTRL2_TIMER_TARGET_Msk = 0xfff000
	// Position of TIMER_EN field.
	ADC_CTRL2_TIMER_EN_Pos = 0x18
	// Bit mask of TIMER_EN field.
	ADC_CTRL2_TIMER_EN_Msk = 0x1000000
	// Bit TIMER_EN.
	ADC_CTRL2_TIMER_EN = 0x1000000

	// FILTER_CTRL1: Register
	// Position of FILTER_FACTOR1 field.
	ADC_FILTER_CTRL1_FILTER_FACTOR1_Pos = 0x1a
	// Bit mask of FILTER_FACTOR1 field.
	ADC_FILTER_CTRL1_FILTER_FACTOR1_Msk = 0x1c000000
	// Position of FILTER_FACTOR0 field.
	ADC_FILTER_CTRL1_FILTER_FACTOR0_Pos = 0x1d
	// Bit mask of FILTER_FACTOR0 field.
	ADC_FILTER_CTRL1_FILTER_FACTOR0_Msk = 0xe0000000

	// FSM_WAIT: Register
	// Position of XPD_WAIT field.
	ADC_FSM_WAIT_XPD_WAIT_Pos = 0x0
	// Bit mask of XPD_WAIT field.
	ADC_FSM_WAIT_XPD_WAIT_Msk = 0xff
	// Position of RSTB_WAIT field.
	ADC_FSM_WAIT_RSTB_WAIT_Pos = 0x8
	// Bit mask of RSTB_WAIT field.
	ADC_FSM_WAIT_RSTB_WAIT_Msk = 0xff00
	// Position of STANDBY_WAIT field.
	ADC_FSM_WAIT_STANDBY_WAIT_Pos = 0x10
	// Bit mask of STANDBY_WAIT field.
	ADC_FSM_WAIT_STANDBY_WAIT_Msk = 0xff0000

	// SAR1_STATUS: Register
	// Position of SAR1_STATUS field.
	ADC_SAR1_STATUS_SAR1_STATUS_Pos = 0x0
	// Bit mask of SAR1_STATUS field.
	ADC_SAR1_STATUS_SAR1_STATUS_Msk = 0xffffffff

	// SAR2_STATUS: Register
	// Position of SAR2_STATUS field.
	ADC_SAR2_STATUS_SAR2_STATUS_Pos = 0x0
	// Bit mask of SAR2_STATUS field.
	ADC_SAR2_STATUS_SAR2_STATUS_Msk = 0xffffffff

	// SAR1_PATT_TAB1: Register
	// Position of SAR1_PATT_TAB1 field.
	ADC_SAR1_PATT_TAB1_SAR1_PATT_TAB1_Pos = 0x0
	// Bit mask of SAR1_PATT_TAB1 field.
	ADC_SAR1_PATT_TAB1_SAR1_PATT_TAB1_Msk = 0xffffff

	// SAR1_PATT_TAB2: Register
	// Position of SAR1_PATT_TAB2 field.
	ADC_SAR1_PATT_TAB2_SAR1_PATT_TAB2_Pos = 0x0
	// Bit mask of SAR1_PATT_TAB2 field.
	ADC_SAR1_PATT_TAB2_SAR1_PATT_TAB2_Msk = 0xffffff

	// SAR1_PATT_TAB3: Register
	// Position of SAR1_PATT_TAB3 field.
	ADC_SAR1_PATT_TAB3_SAR1_PATT_TAB3_Pos = 0x0
	// Bit mask of SAR1_PATT_TAB3 field.
	ADC_SAR1_PATT_TAB3_SAR1_PATT_TAB3_Msk = 0xffffff

	// SAR1_PATT_TAB4: Register
	// Position of SAR1_PATT_TAB4 field.
	ADC_SAR1_PATT_TAB4_SAR1_PATT_TAB4_Pos = 0x0
	// Bit mask of SAR1_PATT_TAB4 field.
	ADC_SAR1_PATT_TAB4_SAR1_PATT_TAB4_Msk = 0xffffff

	// SAR2_PATT_TAB1: Register
	// Position of SAR2_PATT_TAB1 field.
	ADC_SAR2_PATT_TAB1_SAR2_PATT_TAB1_Pos = 0x0
	// Bit mask of SAR2_PATT_TAB1 field.
	ADC_SAR2_PATT_TAB1_SAR2_PATT_TAB1_Msk = 0xffffff

	// SAR2_PATT_TAB2: Register
	// Position of SAR2_PATT_TAB2 field.
	ADC_SAR2_PATT_TAB2_SAR2_PATT_TAB2_Pos = 0x0
	// Bit mask of SAR2_PATT_TAB2 field.
	ADC_SAR2_PATT_TAB2_SAR2_PATT_TAB2_Msk = 0xffffff

	// SAR2_PATT_TAB3: Register
	// Position of SAR2_PATT_TAB3 field.
	ADC_SAR2_PATT_TAB3_SAR2_PATT_TAB3_Pos = 0x0
	// Bit mask of SAR2_PATT_TAB3 field.
	ADC_SAR2_PATT_TAB3_SAR2_PATT_TAB3_Msk = 0xffffff

	// SAR2_PATT_TAB4: Register
	// Position of SAR2_PATT_TAB4 field.
	ADC_SAR2_PATT_TAB4_SAR2_PATT_TAB4_Pos = 0x0
	// Bit mask of SAR2_PATT_TAB4 field.
	ADC_SAR2_PATT_TAB4_SAR2_PATT_TAB4_Msk = 0xffffff

	// ARB_CTRL: Register
	// Position of ARB_APB_FORCE field.
	ADC_ARB_CTRL_ARB_APB_FORCE_Pos = 0x2
	// Bit mask of ARB_APB_FORCE field.
	ADC_ARB_CTRL_ARB_APB_FORCE_Msk = 0x4
	// Bit ARB_APB_FORCE.
	ADC_ARB_CTRL_ARB_APB_FORCE = 0x4
	// Position of ARB_RTC_FORCE field.
	ADC_ARB_CTRL_ARB_RTC_FORCE_Pos = 0x3
	// Bit mask of ARB_RTC_FORCE field.
	ADC_ARB_CTRL_ARB_RTC_FORCE_Msk = 0x8
	// Bit ARB_RTC_FORCE.
	ADC_ARB_CTRL_ARB_RTC_FORCE = 0x8
	// Position of ARB_WIFI_FORCE field.
	ADC_ARB_CTRL_ARB_WIFI_FORCE_Pos = 0x4
	// Bit mask of ARB_WIFI_FORCE field.
	ADC_ARB_CTRL_ARB_WIFI_FORCE_Msk = 0x10
	// Bit ARB_WIFI_FORCE.
	ADC_ARB_CTRL_ARB_WIFI_FORCE = 0x10
	// Position of ARB_GRANT_FORCE field.
	ADC_ARB_CTRL_ARB_GRANT_FORCE_Pos = 0x5
	// Bit mask of ARB_GRANT_FORCE field.
	ADC_ARB_CTRL_ARB_GRANT_FORCE_Msk = 0x20
	// Bit ARB_GRANT_FORCE.
	ADC_ARB_CTRL_ARB_GRANT_FORCE = 0x20
	// Position of ARB_APB_PRIORITY field.
	ADC_ARB_CTRL_ARB_APB_PRIORITY_Pos = 0x6
	// Bit mask of ARB_APB_PRIORITY field.
	ADC_ARB_CTRL_ARB_APB_PRIORITY_Msk = 0xc0
	// Position of ARB_RTC_PRIORITY field.
	ADC_ARB_CTRL_ARB_RTC_PRIORITY_Pos = 0x8
	// Bit mask of ARB_RTC_PRIORITY field.
	ADC_ARB_CTRL_ARB_RTC_PRIORITY_Msk = 0x300
	// Position of ARB_WIFI_PRIORITY field.
	ADC_ARB_CTRL_ARB_WIFI_PRIORITY_Pos = 0xa
	// Bit mask of ARB_WIFI_PRIORITY field.
	ADC_ARB_CTRL_ARB_WIFI_PRIORITY_Msk = 0xc00
	// Position of ARB_FIX_PRIORITY field.
	ADC_ARB_CTRL_ARB_FIX_PRIORITY_Pos = 0xc
	// Bit mask of ARB_FIX_PRIORITY field.
	ADC_ARB_CTRL_ARB_FIX_PRIORITY_Msk = 0x1000
	// Bit ARB_FIX_PRIORITY.
	ADC_ARB_CTRL_ARB_FIX_PRIORITY = 0x1000

	// FILTER_CTRL0: Register
	// Position of FILTER_CHANNEL1 field.
	ADC_FILTER_CTRL0_FILTER_CHANNEL1_Pos = 0xe
	// Bit mask of FILTER_CHANNEL1 field.
	ADC_FILTER_CTRL0_FILTER_CHANNEL1_Msk = 0x7c000
	// Position of FILTER_CHANNEL0 field.
	ADC_FILTER_CTRL0_FILTER_CHANNEL0_Pos = 0x13
	// Bit mask of FILTER_CHANNEL0 field.
	ADC_FILTER_CTRL0_FILTER_CHANNEL0_Msk = 0xf80000
	// Position of FILTER_RESET field.
	ADC_FILTER_CTRL0_FILTER_RESET_Pos = 0x1f
	// Bit mask of FILTER_RESET field.
	ADC_FILTER_CTRL0_FILTER_RESET_Msk = 0x80000000
	// Bit FILTER_RESET.
	ADC_FILTER_CTRL0_FILTER_RESET = 0x80000000

	// SAR1_DATA_STATUS: Register
	// Position of APB_SARADC1_DATA field.
	ADC_SAR1_DATA_STATUS_APB_SARADC1_DATA_Pos = 0x0
	// Bit mask of APB_SARADC1_DATA field.
	ADC_SAR1_DATA_STATUS_APB_SARADC1_DATA_Msk = 0x1ffff

	// THRES0_CTRL: Register
	// Position of THRES0_CHANNEL field.
	ADC_THRES0_CTRL_THRES0_CHANNEL_Pos = 0x0
	// Bit mask of THRES0_CHANNEL field.
	ADC_THRES0_CTRL_THRES0_CHANNEL_Msk = 0x1f
	// Position of THRES0_HIGH field.
	ADC_THRES0_CTRL_THRES0_HIGH_Pos = 0x5
	// Bit mask of THRES0_HIGH field.
	ADC_THRES0_CTRL_THRES0_HIGH_Msk = 0x3ffe0
	// Position of THRES0_LOW field.
	ADC_THRES0_CTRL_THRES0_LOW_Pos = 0x12
	// Bit mask of THRES0_LOW field.
	ADC_THRES0_CTRL_THRES0_LOW_Msk = 0x7ffc0000

	// THRES1_CTRL: Register
	// Position of THRES1_CHANNEL field.
	ADC_THRES1_CTRL_THRES1_CHANNEL_Pos = 0x0
	// Bit mask of THRES1_CHANNEL field.
	ADC_THRES1_CTRL_THRES1_CHANNEL_Msk = 0x1f
	// Position of THRES1_HIGH field.
	ADC_THRES1_CTRL_THRES1_HIGH_Pos = 0x5
	// Bit mask of THRES1_HIGH field.
	ADC_THRES1_CTRL_THRES1_HIGH_Msk = 0x3ffe0
	// Position of THRES1_LOW field.
	ADC_THRES1_CTRL_THRES1_LOW_Pos = 0x12
	// Bit mask of THRES1_LOW field.
	ADC_THRES1_CTRL_THRES1_LOW_Msk = 0x7ffc0000

	// THRES_CTRL: Register
	// Position of THRES_ALL_EN field.
	ADC_THRES_CTRL_THRES_ALL_EN_Pos = 0x1b
	// Bit mask of THRES_ALL_EN field.
	ADC_THRES_CTRL_THRES_ALL_EN_Msk = 0x8000000
	// Bit THRES_ALL_EN.
	ADC_THRES_CTRL_THRES_ALL_EN = 0x8000000
	// Position of THRES3_EN field.
	ADC_THRES_CTRL_THRES3_EN_Pos = 0x1c
	// Bit mask of THRES3_EN field.
	ADC_THRES_CTRL_THRES3_EN_Msk = 0x10000000
	// Bit THRES3_EN.
	ADC_THRES_CTRL_THRES3_EN = 0x10000000
	// Position of THRES2_EN field.
	ADC_THRES_CTRL_THRES2_EN_Pos = 0x1d
	// Bit mask of THRES2_EN field.
	ADC_THRES_CTRL_THRES2_EN_Msk = 0x20000000
	// Bit THRES2_EN.
	ADC_THRES_CTRL_THRES2_EN = 0x20000000
	// Position of THRES1_EN field.
	ADC_THRES_CTRL_THRES1_EN_Pos = 0x1e
	// Bit mask of THRES1_EN field.
	ADC_THRES_CTRL_THRES1_EN_Msk = 0x40000000
	// Bit THRES1_EN.
	ADC_THRES_CTRL_THRES1_EN = 0x40000000
	// Position of THRES0_EN field.
	ADC_THRES_CTRL_THRES0_EN_Pos = 0x1f
	// Bit mask of THRES0_EN field.
	ADC_THRES_CTRL_THRES0_EN_Msk = 0x80000000
	// Bit THRES0_EN.
	ADC_THRES_CTRL_THRES0_EN = 0x80000000

	// INT_ENA: Register
	// Position of THRES1_LOW_INT_ENA field.
	ADC_INT_ENA_THRES1_LOW_INT_ENA_Pos = 0x1a
	// Bit mask of THRES1_LOW_INT_ENA field.
	ADC_INT_ENA_THRES1_LOW_INT_ENA_Msk = 0x4000000
	// Bit THRES1_LOW_INT_ENA.
	ADC_INT_ENA_THRES1_LOW_INT_ENA = 0x4000000
	// Position of THRES0_LOW_INT_ENA field.
	ADC_INT_ENA_THRES0_LOW_INT_ENA_Pos = 0x1b
	// Bit mask of THRES0_LOW_INT_ENA field.
	ADC_INT_ENA_THRES0_LOW_INT_ENA_Msk = 0x8000000
	// Bit THRES0_LOW_INT_ENA.
	ADC_INT_ENA_THRES0_LOW_INT_ENA = 0x8000000
	// Position of THRES1_HIGH_INT_ENA field.
	ADC_INT_ENA_THRES1_HIGH_INT_ENA_Pos = 0x1c
	// Bit mask of THRES1_HIGH_INT_ENA field.
	ADC_INT_ENA_THRES1_HIGH_INT_ENA_Msk = 0x10000000
	// Bit THRES1_HIGH_INT_ENA.
	ADC_INT_ENA_THRES1_HIGH_INT_ENA = 0x10000000
	// Position of THRES0_HIGH_INT_ENA field.
	ADC_INT_ENA_THRES0_HIGH_INT_ENA_Pos = 0x1d
	// Bit mask of THRES0_HIGH_INT_ENA field.
	ADC_INT_ENA_THRES0_HIGH_INT_ENA_Msk = 0x20000000
	// Bit THRES0_HIGH_INT_ENA.
	ADC_INT_ENA_THRES0_HIGH_INT_ENA = 0x20000000
	// Position of SAR2_DONE_INT_ENA field.
	ADC_INT_ENA_SAR2_DONE_INT_ENA_Pos = 0x1e
	// Bit mask of SAR2_DONE_INT_ENA field.
	ADC_INT_ENA_SAR2_DONE_INT_ENA_Msk = 0x40000000
	// Bit SAR2_DONE_INT_ENA.
	ADC_INT_ENA_SAR2_DONE_INT_ENA = 0x40000000
	// Position of SAR1_DONE_INT_ENA field.
	ADC_INT_ENA_SAR1_DONE_INT_ENA_Pos = 0x1f
	// Bit mask of SAR1_DONE_INT_ENA field.
	ADC_INT_ENA_SAR1_DONE_INT_ENA_Msk = 0x80000000
	// Bit SAR1_DONE_INT_ENA.
	ADC_INT_ENA_SAR1_DONE_INT_ENA = 0x80000000

	// INT_RAW: Register
	// Position of THRES1_LOW_INT_RAW field.
	ADC_INT_RAW_THRES1_LOW_INT_RAW_Pos = 0x1a
	// Bit mask of THRES1_LOW_INT_RAW field.
	ADC_INT_RAW_THRES1_LOW_INT_RAW_Msk = 0x4000000
	// Bit THRES1_LOW_INT_RAW.
	ADC_INT_RAW_THRES1_LOW_INT_RAW = 0x4000000
	// Position of THRES0_LOW_INT_RAW field.
	ADC_INT_RAW_THRES0_LOW_INT_RAW_Pos = 0x1b
	// Bit mask of THRES0_LOW_INT_RAW field.
	ADC_INT_RAW_THRES0_LOW_INT_RAW_Msk = 0x8000000
	// Bit THRES0_LOW_INT_RAW.
	ADC_INT_RAW_THRES0_LOW_INT_RAW = 0x8000000
	// Position of THRES1_HIGH_INT_RAW field.
	ADC_INT_RAW_THRES1_HIGH_INT_RAW_Pos = 0x1c
	// Bit mask of THRES1_HIGH_INT_RAW field.
	ADC_INT_RAW_THRES1_HIGH_INT_RAW_Msk = 0x10000000
	// Bit THRES1_HIGH_INT_RAW.
	ADC_INT_RAW_THRES1_HIGH_INT_RAW = 0x10000000
	// Position of THRES0_HIGH_INT_RAW field.
	ADC_INT_RAW_THRES0_HIGH_INT_RAW_Pos = 0x1d
	// Bit mask of THRES0_HIGH_INT_RAW field.
	ADC_INT_RAW_THRES0_HIGH_INT_RAW_Msk = 0x20000000
	// Bit THRES0_HIGH_INT_RAW.
	ADC_INT_RAW_THRES0_HIGH_INT_RAW = 0x20000000
	// Position of SAR2_DONE_INT_RAW field.
	ADC_INT_RAW_SAR2_DONE_INT_RAW_Pos = 0x1e
	// Bit mask of SAR2_DONE_INT_RAW field.
	ADC_INT_RAW_SAR2_DONE_INT_RAW_Msk = 0x40000000
	// Bit SAR2_DONE_INT_RAW.
	ADC_INT_RAW_SAR2_DONE_INT_RAW = 0x40000000
	// Position of SAR1_DONE_INT_RAW field.
	ADC_INT_RAW_SAR1_DONE_INT_RAW_Pos = 0x1f
	// Bit mask of SAR1_DONE_INT_RAW field.
	ADC_INT_RAW_SAR1_DONE_INT_RAW_Msk = 0x80000000
	// Bit SAR1_DONE_INT_RAW.
	ADC_INT_RAW_SAR1_DONE_INT_RAW = 0x80000000

	// INT_ST: Register
	// Position of THRES1_LOW_INT_ST field.
	ADC_INT_ST_THRES1_LOW_INT_ST_Pos = 0x1a
	// Bit mask of THRES1_LOW_INT_ST field.
	ADC_INT_ST_THRES1_LOW_INT_ST_Msk = 0x4000000
	// Bit THRES1_LOW_INT_ST.
	ADC_INT_ST_THRES1_LOW_INT_ST = 0x4000000
	// Position of THRES0_LOW_INT_ST field.
	ADC_INT_ST_THRES0_LOW_INT_ST_Pos = 0x1b
	// Bit mask of THRES0_LOW_INT_ST field.
	ADC_INT_ST_THRES0_LOW_INT_ST_Msk = 0x8000000
	// Bit THRES0_LOW_INT_ST.
	ADC_INT_ST_THRES0_LOW_INT_ST = 0x8000000
	// Position of THRES1_HIGH_INT_ST field.
	ADC_INT_ST_THRES1_HIGH_INT_ST_Pos = 0x1c
	// Bit mask of THRES1_HIGH_INT_ST field.
	ADC_INT_ST_THRES1_HIGH_INT_ST_Msk = 0x10000000
	// Bit THRES1_HIGH_INT_ST.
	ADC_INT_ST_THRES1_HIGH_INT_ST = 0x10000000
	// Position of THRES0_HIGH_INT_ST field.
	ADC_INT_ST_THRES0_HIGH_INT_ST_Pos = 0x1d
	// Bit mask of THRES0_HIGH_INT_ST field.
	ADC_INT_ST_THRES0_HIGH_INT_ST_Msk = 0x20000000
	// Bit THRES0_HIGH_INT_ST.
	ADC_INT_ST_THRES0_HIGH_INT_ST = 0x20000000
	// Position of APB_SARADC2_DONE_INT_ST field.
	ADC_INT_ST_APB_SARADC2_DONE_INT_ST_Pos = 0x1e
	// Bit mask of APB_SARADC2_DONE_INT_ST field.
	ADC_INT_ST_APB_SARADC2_DONE_INT_ST_Msk = 0x40000000
	// Bit APB_SARADC2_DONE_INT_ST.
	ADC_INT_ST_APB_SARADC2_DONE_INT_ST = 0x40000000
	// Position of APB_SARADC1_DONE_INT_ST field.
	ADC_INT_ST_APB_SARADC1_DONE_INT_ST_Pos = 0x1f
	// Bit mask of APB_SARADC1_DONE_INT_ST field.
	ADC_INT_ST_APB_SARADC1_DONE_INT_ST_Msk = 0x80000000
	// Bit APB_SARADC1_DONE_INT_ST.
	ADC_INT_ST_APB_SARADC1_DONE_INT_ST = 0x80000000

	// INT_CLR: Register
	// Position of THRES1_LOW_INT_CLR field.
	ADC_INT_CLR_THRES1_LOW_INT_CLR_Pos = 0x1a
	// Bit mask of THRES1_LOW_INT_CLR field.
	ADC_INT_CLR_THRES1_LOW_INT_CLR_Msk = 0x4000000
	// Bit THRES1_LOW_INT_CLR.
	ADC_INT_CLR_THRES1_LOW_INT_CLR = 0x4000000
	// Position of THRES0_LOW_INT_CLR field.
	ADC_INT_CLR_THRES0_LOW_INT_CLR_Pos = 0x1b
	// Bit mask of THRES0_LOW_INT_CLR field.
	ADC_INT_CLR_THRES0_LOW_INT_CLR_Msk = 0x8000000
	// Bit THRES0_LOW_INT_CLR.
	ADC_INT_CLR_THRES0_LOW_INT_CLR = 0x8000000
	// Position of THRES1_HIGH_INT_CLR field.
	ADC_INT_CLR_THRES1_HIGH_INT_CLR_Pos = 0x1c
	// Bit mask of THRES1_HIGH_INT_CLR field.
	ADC_INT_CLR_THRES1_HIGH_INT_CLR_Msk = 0x10000000
	// Bit THRES1_HIGH_INT_CLR.
	ADC_INT_CLR_THRES1_HIGH_INT_CLR = 0x10000000
	// Position of THRES0_HIGH_INT_CLR field.
	ADC_INT_CLR_THRES0_HIGH_INT_CLR_Pos = 0x1d
	// Bit mask of THRES0_HIGH_INT_CLR field.
	ADC_INT_CLR_THRES0_HIGH_INT_CLR_Msk = 0x20000000
	// Bit THRES0_HIGH_INT_CLR.
	ADC_INT_CLR_THRES0_HIGH_INT_CLR = 0x20000000
	// Position of APB_SARADC2_DONE_INT_CLR field.
	ADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Pos = 0x1e
	// Bit mask of APB_SARADC2_DONE_INT_CLR field.
	ADC_INT_CLR_APB_SARADC2_DONE_INT_CLR_Msk = 0x40000000
	// Bit APB_SARADC2_DONE_INT_CLR.
	ADC_INT_CLR_APB_SARADC2_DONE_INT_CLR = 0x40000000
	// Position of APB_SARADC1_DONE_INT_CLR field.
	ADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Pos = 0x1f
	// Bit mask of APB_SARADC1_DONE_INT_CLR field.
	ADC_INT_CLR_APB_SARADC1_DONE_INT_CLR_Msk = 0x80000000
	// Bit APB_SARADC1_DONE_INT_CLR.
	ADC_INT_CLR_APB_SARADC1_DONE_INT_CLR = 0x80000000

	// DMA_CONF: Register
	// Position of APB_ADC_EOF_NUM field.
	ADC_DMA_CONF_APB_ADC_EOF_NUM_Pos = 0x0
	// Bit mask of APB_ADC_EOF_NUM field.
	ADC_DMA_CONF_APB_ADC_EOF_NUM_Msk = 0xffff
	// Position of APB_ADC_RESET_FSM field.
	ADC_DMA_CONF_APB_ADC_RESET_FSM_Pos = 0x1e
	// Bit mask of APB_ADC_RESET_FSM field.
	ADC_DMA_CONF_APB_ADC_RESET_FSM_Msk = 0x40000000
	// Bit APB_ADC_RESET_FSM.
	ADC_DMA_CONF_APB_ADC_RESET_FSM = 0x40000000
	// Position of APB_ADC_TRANS field.
	ADC_DMA_CONF_APB_ADC_TRANS_Pos = 0x1f
	// Bit mask of APB_ADC_TRANS field.
	ADC_DMA_CONF_APB_ADC_TRANS_Msk = 0x80000000
	// Bit APB_ADC_TRANS.
	ADC_DMA_CONF_APB_ADC_TRANS = 0x80000000

	// SAR2_DATA_STATUS: Register
	// Position of APB_SARADC2_DATA field.
	ADC_SAR2_DATA_STATUS_APB_SARADC2_DATA_Pos = 0x0
	// Bit mask of APB_SARADC2_DATA field.
	ADC_SAR2_DATA_STATUS_APB_SARADC2_DATA_Msk = 0x1ffff

	// CALI: Register
	// Position of CFG field.
	ADC_CALI_CFG_Pos = 0x0
	// Bit mask of CFG field.
	ADC_CALI_CFG_Msk = 0x1ffff

	// RND_ECO_LOW: Register
	// Position of RND_ECO_LOW field.
	ADC_RND_ECO_LOW_RND_ECO_LOW_Pos = 0x0
	// Bit mask of RND_ECO_LOW field.
	ADC_RND_ECO_LOW_RND_ECO_LOW_Msk = 0xffffffff

	// RND_ECO_HIGH: Register
	// Position of RND_ECO_HIGH field.
	ADC_RND_ECO_HIGH_RND_ECO_HIGH_Pos = 0x0
	// Bit mask of RND_ECO_HIGH field.
	ADC_RND_ECO_HIGH_RND_ECO_HIGH_Msk = 0xffffffff

	// RND_ECO_CS: Register
	// Position of RND_ECO_EN field.
	ADC_RND_ECO_CS_RND_ECO_EN_Pos = 0x0
	// Bit mask of RND_ECO_EN field.
	ADC_RND_ECO_CS_RND_ECO_EN_Msk = 0x1
	// Bit RND_ECO_EN.
	ADC_RND_ECO_CS_RND_ECO_EN = 0x1
	// Position of RND_ECO_RESULT field.
	ADC_RND_ECO_CS_RND_ECO_RESULT_Pos = 0x1
	// Bit mask of RND_ECO_RESULT field.
	ADC_RND_ECO_CS_RND_ECO_RESULT_Msk = 0x2
	// Bit RND_ECO_RESULT.
	ADC_RND_ECO_CS_RND_ECO_RESULT = 0x2

	// CTRL_DATE: Register
	// Position of CTRL_DATE field.
	ADC_CTRL_DATE_CTRL_DATE_Pos = 0x0
	// Bit mask of CTRL_DATE field.
	ADC_CTRL_DATE_CTRL_DATE_Msk = 0x7fffffff
	// Position of CLK_EN field.
	ADC_CTRL_DATE_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	ADC_CTRL_DATE_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	ADC_CTRL_DATE_CLK_EN = 0x80000000
)

// Constants for AES: AES (Advanced Encryption Standard) Accelerator
const (
	// KEY_0: Key material key_0 configure register
	// Position of KEY_0 field.
	AES_KEY_0_KEY_0_Pos = 0x0
	// Bit mask of KEY_0 field.
	AES_KEY_0_KEY_0_Msk = 0xffffffff

	// KEY_1: Key material key_1 configure register
	// Position of KEY_1 field.
	AES_KEY_1_KEY_1_Pos = 0x0
	// Bit mask of KEY_1 field.
	AES_KEY_1_KEY_1_Msk = 0xffffffff

	// KEY_2: Key material key_2 configure register
	// Position of KEY_2 field.
	AES_KEY_2_KEY_2_Pos = 0x0
	// Bit mask of KEY_2 field.
	AES_KEY_2_KEY_2_Msk = 0xffffffff

	// KEY_3: Key material key_3 configure register
	// Position of KEY_3 field.
	AES_KEY_3_KEY_3_Pos = 0x0
	// Bit mask of KEY_3 field.
	AES_KEY_3_KEY_3_Msk = 0xffffffff

	// KEY_4: Key material key_4 configure register
	// Position of KEY_4 field.
	AES_KEY_4_KEY_4_Pos = 0x0
	// Bit mask of KEY_4 field.
	AES_KEY_4_KEY_4_Msk = 0xffffffff

	// KEY_5: Key material key_5 configure register
	// Position of KEY_5 field.
	AES_KEY_5_KEY_5_Pos = 0x0
	// Bit mask of KEY_5 field.
	AES_KEY_5_KEY_5_Msk = 0xffffffff

	// KEY_6: Key material key_6 configure register
	// Position of KEY_6 field.
	AES_KEY_6_KEY_6_Pos = 0x0
	// Bit mask of KEY_6 field.
	AES_KEY_6_KEY_6_Msk = 0xffffffff

	// KEY_7: Key material key_7 configure register
	// Position of KEY_7 field.
	AES_KEY_7_KEY_7_Pos = 0x0
	// Bit mask of KEY_7 field.
	AES_KEY_7_KEY_7_Msk = 0xffffffff

	// TEXT_IN_0: source text material text_in_0 configure register
	// Position of TEXT_IN_0 field.
	AES_TEXT_IN_0_TEXT_IN_0_Pos = 0x0
	// Bit mask of TEXT_IN_0 field.
	AES_TEXT_IN_0_TEXT_IN_0_Msk = 0xffffffff

	// TEXT_IN_1: source text material text_in_1 configure register
	// Position of TEXT_IN_1 field.
	AES_TEXT_IN_1_TEXT_IN_1_Pos = 0x0
	// Bit mask of TEXT_IN_1 field.
	AES_TEXT_IN_1_TEXT_IN_1_Msk = 0xffffffff

	// TEXT_IN_2: source text material text_in_2 configure register
	// Position of TEXT_IN_2 field.
	AES_TEXT_IN_2_TEXT_IN_2_Pos = 0x0
	// Bit mask of TEXT_IN_2 field.
	AES_TEXT_IN_2_TEXT_IN_2_Msk = 0xffffffff

	// TEXT_IN_3: source text material text_in_3 configure register
	// Position of TEXT_IN_3 field.
	AES_TEXT_IN_3_TEXT_IN_3_Pos = 0x0
	// Bit mask of TEXT_IN_3 field.
	AES_TEXT_IN_3_TEXT_IN_3_Msk = 0xffffffff

	// TEXT_OUT_0: result text material text_out_0 configure register
	// Position of TEXT_OUT_0 field.
	AES_TEXT_OUT_0_TEXT_OUT_0_Pos = 0x0
	// Bit mask of TEXT_OUT_0 field.
	AES_TEXT_OUT_0_TEXT_OUT_0_Msk = 0xffffffff

	// TEXT_OUT_1: result text material text_out_1 configure register
	// Position of TEXT_OUT_1 field.
	AES_TEXT_OUT_1_TEXT_OUT_1_Pos = 0x0
	// Bit mask of TEXT_OUT_1 field.
	AES_TEXT_OUT_1_TEXT_OUT_1_Msk = 0xffffffff

	// TEXT_OUT_2: result text material text_out_2 configure register
	// Position of TEXT_OUT_2 field.
	AES_TEXT_OUT_2_TEXT_OUT_2_Pos = 0x0
	// Bit mask of TEXT_OUT_2 field.
	AES_TEXT_OUT_2_TEXT_OUT_2_Msk = 0xffffffff

	// TEXT_OUT_3: result text material text_out_3 configure register
	// Position of TEXT_OUT_3 field.
	AES_TEXT_OUT_3_TEXT_OUT_3_Pos = 0x0
	// Bit mask of TEXT_OUT_3 field.
	AES_TEXT_OUT_3_TEXT_OUT_3_Msk = 0xffffffff

	// MODE: AES Mode register
	// Position of MODE field.
	AES_MODE_MODE_Pos = 0x0
	// Bit mask of MODE field.
	AES_MODE_MODE_Msk = 0x7

	// ENDIAN: AES Endian configure register
	// Position of ENDIAN field.
	AES_ENDIAN_ENDIAN_Pos = 0x0
	// Bit mask of ENDIAN field.
	AES_ENDIAN_ENDIAN_Msk = 0x3f

	// TRIGGER: AES trigger register
	// Position of TRIGGER field.
	AES_TRIGGER_TRIGGER_Pos = 0x0
	// Bit mask of TRIGGER field.
	AES_TRIGGER_TRIGGER_Msk = 0x1
	// Bit TRIGGER.
	AES_TRIGGER_TRIGGER = 0x1

	// STATE: AES state register
	// Position of STATE field.
	AES_STATE_STATE_Pos = 0x0
	// Bit mask of STATE field.
	AES_STATE_STATE_Msk = 0x3

	// DMA_ENABLE: DMA-AES working mode register
	// Position of DMA_ENABLE field.
	AES_DMA_ENABLE_DMA_ENABLE_Pos = 0x0
	// Bit mask of DMA_ENABLE field.
	AES_DMA_ENABLE_DMA_ENABLE_Msk = 0x1
	// Bit DMA_ENABLE.
	AES_DMA_ENABLE_DMA_ENABLE = 0x1

	// BLOCK_MODE: AES cipher block mode register
	// Position of BLOCK_MODE field.
	AES_BLOCK_MODE_BLOCK_MODE_Pos = 0x0
	// Bit mask of BLOCK_MODE field.
	AES_BLOCK_MODE_BLOCK_MODE_Msk = 0x7

	// BLOCK_NUM: AES block number register
	// Position of BLOCK_NUM field.
	AES_BLOCK_NUM_BLOCK_NUM_Pos = 0x0
	// Bit mask of BLOCK_NUM field.
	AES_BLOCK_NUM_BLOCK_NUM_Msk = 0xffffffff

	// INC_SEL: Standard incrementing function configure register
	// Position of INC_SEL field.
	AES_INC_SEL_INC_SEL_Pos = 0x0
	// Bit mask of INC_SEL field.
	AES_INC_SEL_INC_SEL_Msk = 0x1
	// Bit INC_SEL.
	AES_INC_SEL_INC_SEL = 0x1

	// AAD_BLOCK_NUM: Additional Authential Data block number register
	// Position of AAD_BLOCK_NUM field.
	AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Pos = 0x0
	// Bit mask of AAD_BLOCK_NUM field.
	AES_AAD_BLOCK_NUM_AAD_BLOCK_NUM_Msk = 0xffffffff

	// REMAINDER_BIT_NUM: AES remainder bit number register
	// Position of REMAINDER_BIT_NUM field.
	AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Pos = 0x0
	// Bit mask of REMAINDER_BIT_NUM field.
	AES_REMAINDER_BIT_NUM_REMAINDER_BIT_NUM_Msk = 0x7f

	// CONTINUE: AES continue register
	// Position of CONTINUE field.
	AES_CONTINUE_CONTINUE_Pos = 0x0
	// Bit mask of CONTINUE field.
	AES_CONTINUE_CONTINUE_Msk = 0x1
	// Bit CONTINUE.
	AES_CONTINUE_CONTINUE = 0x1

	// INT_CLEAR: AES Interrupt clear register
	// Position of INT_CLEAR field.
	AES_INT_CLEAR_INT_CLEAR_Pos = 0x0
	// Bit mask of INT_CLEAR field.
	AES_INT_CLEAR_INT_CLEAR_Msk = 0x1
	// Bit INT_CLEAR.
	AES_INT_CLEAR_INT_CLEAR = 0x1

	// INT_ENA: AES Interrupt enable register
	// Position of INT_ENA field.
	AES_INT_ENA_INT_ENA_Pos = 0x0
	// Bit mask of INT_ENA field.
	AES_INT_ENA_INT_ENA_Msk = 0x1
	// Bit INT_ENA.
	AES_INT_ENA_INT_ENA = 0x1

	// DATE: AES version control register
	// Position of DATE field.
	AES_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	AES_DATE_DATE_Msk = 0x3fffffff

	// DMA_EXIT: AES-DMA exit config
	// Position of DMA_EXIT field.
	AES_DMA_EXIT_DMA_EXIT_Pos = 0x0
	// Bit mask of DMA_EXIT field.
	AES_DMA_EXIT_DMA_EXIT_Msk = 0x1
	// Bit DMA_EXIT.
	AES_DMA_EXIT_DMA_EXIT = 0x1
)

// Constants for AHB_DMA: AHB_DMA Peripheral
const (
	// IN_INT_RAW_CH0: Raw status interrupt of channel 0
	// Position of IN_DONE_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH_INT_RAW.
	AHB_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_RAW.
	AHB_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW = 0x2
	// Position of IN_ERR_EOF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_RAW.
	AHB_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW = 0x4
	// Position of IN_DSCR_ERR_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_RAW.
	AHB_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_RAW.
	AHB_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW = 0x10
	// Position of INFIFO_OVF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_INFIFO_OVF_CH_INT_RAW_Pos = 0x5
	// Bit mask of INFIFO_OVF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_INFIFO_OVF_CH_INT_RAW_Msk = 0x20
	// Bit INFIFO_OVF_CH_INT_RAW.
	AHB_DMA_IN_INT_RAW_CH_INFIFO_OVF_CH_INT_RAW = 0x20
	// Position of INFIFO_UDF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_INFIFO_UDF_CH_INT_RAW_Pos = 0x6
	// Bit mask of INFIFO_UDF_CH_INT_RAW field.
	AHB_DMA_IN_INT_RAW_CH_INFIFO_UDF_CH_INT_RAW_Msk = 0x40
	// Bit INFIFO_UDF_CH_INT_RAW.
	AHB_DMA_IN_INT_RAW_CH_INFIFO_UDF_CH_INT_RAW = 0x40

	// IN_INT_ST_CH0: Masked interrupt of channel 0
	// Position of IN_DONE_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH_INT_ST.
	AHB_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_ST.
	AHB_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST = 0x2
	// Position of IN_ERR_EOF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_ST.
	AHB_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST = 0x4
	// Position of IN_DSCR_ERR_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_ST.
	AHB_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_ST.
	AHB_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST = 0x10
	// Position of INFIFO_OVF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST_Pos = 0x5
	// Bit mask of INFIFO_OVF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST_Msk = 0x20
	// Bit INFIFO_OVF_CH_INT_ST.
	AHB_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST = 0x20
	// Position of INFIFO_UDF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST_Pos = 0x6
	// Bit mask of INFIFO_UDF_CH_INT_ST field.
	AHB_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST_Msk = 0x40
	// Bit INFIFO_UDF_CH_INT_ST.
	AHB_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST = 0x40

	// IN_INT_ENA_CH0: Interrupt enable bits of channel 0
	// Position of IN_DONE_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH_INT_ENA.
	AHB_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_ENA.
	AHB_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA = 0x2
	// Position of IN_ERR_EOF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_ENA.
	AHB_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA = 0x4
	// Position of IN_DSCR_ERR_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_ENA.
	AHB_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_ENA.
	AHB_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA = 0x10
	// Position of INFIFO_OVF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_INFIFO_OVF_CH_INT_ENA_Pos = 0x5
	// Bit mask of INFIFO_OVF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_INFIFO_OVF_CH_INT_ENA_Msk = 0x20
	// Bit INFIFO_OVF_CH_INT_ENA.
	AHB_DMA_IN_INT_ENA_CH_INFIFO_OVF_CH_INT_ENA = 0x20
	// Position of INFIFO_UDF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_INFIFO_UDF_CH_INT_ENA_Pos = 0x6
	// Bit mask of INFIFO_UDF_CH_INT_ENA field.
	AHB_DMA_IN_INT_ENA_CH_INFIFO_UDF_CH_INT_ENA_Msk = 0x40
	// Bit INFIFO_UDF_CH_INT_ENA.
	AHB_DMA_IN_INT_ENA_CH_INFIFO_UDF_CH_INT_ENA = 0x40

	// IN_INT_CLR_CH0: Interrupt clear bits of channel 0
	// Position of IN_DONE_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH_INT_CLR.
	AHB_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_CLR.
	AHB_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR = 0x2
	// Position of IN_ERR_EOF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_CLR.
	AHB_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR = 0x4
	// Position of IN_DSCR_ERR_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_CLR.
	AHB_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_CLR.
	AHB_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR = 0x10
	// Position of INFIFO_OVF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_INFIFO_OVF_CH_INT_CLR_Pos = 0x5
	// Bit mask of INFIFO_OVF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_INFIFO_OVF_CH_INT_CLR_Msk = 0x20
	// Bit INFIFO_OVF_CH_INT_CLR.
	AHB_DMA_IN_INT_CLR_CH_INFIFO_OVF_CH_INT_CLR = 0x20
	// Position of INFIFO_UDF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_INFIFO_UDF_CH_INT_CLR_Pos = 0x6
	// Bit mask of INFIFO_UDF_CH_INT_CLR field.
	AHB_DMA_IN_INT_CLR_CH_INFIFO_UDF_CH_INT_CLR_Msk = 0x40
	// Bit INFIFO_UDF_CH_INT_CLR.
	AHB_DMA_IN_INT_CLR_CH_INFIFO_UDF_CH_INT_CLR = 0x40

	// OUT_INT_RAW_CH0: Raw status interrupt of channel 0
	// Position of OUT_DONE_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW_Msk = 0x1
	// Bit OUT_DONE_CH_INT_RAW.
	AHB_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW = 0x1
	// Position of OUT_EOF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW_Msk = 0x2
	// Bit OUT_EOF_CH_INT_RAW.
	AHB_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_RAW.
	AHB_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_RAW.
	AHB_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW = 0x8
	// Position of OUTFIFO_OVF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_CH_INT_RAW_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_CH_INT_RAW_Msk = 0x10
	// Bit OUTFIFO_OVF_CH_INT_RAW.
	AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_OVF_CH_INT_RAW = 0x10
	// Position of OUTFIFO_UDF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_CH_INT_RAW_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_CH_INT_RAW field.
	AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_CH_INT_RAW_Msk = 0x20
	// Bit OUTFIFO_UDF_CH_INT_RAW.
	AHB_DMA_OUT_INT_RAW_CH_OUTFIFO_UDF_CH_INT_RAW = 0x20

	// OUT_INT_ST_CH0: Masked interrupt of channel 0
	// Position of OUT_DONE_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST_Msk = 0x1
	// Bit OUT_DONE_CH_INT_ST.
	AHB_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST = 0x1
	// Position of OUT_EOF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST_Msk = 0x2
	// Bit OUT_EOF_CH_INT_ST.
	AHB_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_ST.
	AHB_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_ST.
	AHB_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST = 0x8
	// Position of OUTFIFO_OVF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST_Msk = 0x10
	// Bit OUTFIFO_OVF_CH_INT_ST.
	AHB_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST = 0x10
	// Position of OUTFIFO_UDF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_CH_INT_ST field.
	AHB_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST_Msk = 0x20
	// Bit OUTFIFO_UDF_CH_INT_ST.
	AHB_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST = 0x20

	// OUT_INT_ENA_CH0: Interrupt enable bits of channel 0
	// Position of OUT_DONE_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA_Msk = 0x1
	// Bit OUT_DONE_CH_INT_ENA.
	AHB_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA = 0x1
	// Position of OUT_EOF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA_Msk = 0x2
	// Bit OUT_EOF_CH_INT_ENA.
	AHB_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_ENA.
	AHB_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_ENA.
	AHB_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA = 0x8
	// Position of OUTFIFO_OVF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_CH_INT_ENA_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_CH_INT_ENA_Msk = 0x10
	// Bit OUTFIFO_OVF_CH_INT_ENA.
	AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_OVF_CH_INT_ENA = 0x10
	// Position of OUTFIFO_UDF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_CH_INT_ENA_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_CH_INT_ENA field.
	AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_CH_INT_ENA_Msk = 0x20
	// Bit OUTFIFO_UDF_CH_INT_ENA.
	AHB_DMA_OUT_INT_ENA_CH_OUTFIFO_UDF_CH_INT_ENA = 0x20

	// OUT_INT_CLR_CH0: Interrupt clear bits of channel 0
	// Position of OUT_DONE_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR_Msk = 0x1
	// Bit OUT_DONE_CH_INT_CLR.
	AHB_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR = 0x1
	// Position of OUT_EOF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR_Msk = 0x2
	// Bit OUT_EOF_CH_INT_CLR.
	AHB_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_CLR.
	AHB_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_CLR.
	AHB_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR = 0x8
	// Position of OUTFIFO_OVF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_CH_INT_CLR_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_CH_INT_CLR_Msk = 0x10
	// Bit OUTFIFO_OVF_CH_INT_CLR.
	AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_OVF_CH_INT_CLR = 0x10
	// Position of OUTFIFO_UDF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_CH_INT_CLR_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_CH_INT_CLR field.
	AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_CH_INT_CLR_Msk = 0x20
	// Bit OUTFIFO_UDF_CH_INT_CLR.
	AHB_DMA_OUT_INT_CLR_CH_OUTFIFO_UDF_CH_INT_CLR = 0x20

	// AHB_TEST: reserved
	// Position of AHB_TESTMODE field.
	AHB_DMA_AHB_TEST_AHB_TESTMODE_Pos = 0x0
	// Bit mask of AHB_TESTMODE field.
	AHB_DMA_AHB_TEST_AHB_TESTMODE_Msk = 0x7
	// Position of AHB_TESTADDR field.
	AHB_DMA_AHB_TEST_AHB_TESTADDR_Pos = 0x4
	// Bit mask of AHB_TESTADDR field.
	AHB_DMA_AHB_TEST_AHB_TESTADDR_Msk = 0x30

	// MISC_CONF: MISC register
	// Position of AHBM_RST_INTER field.
	AHB_DMA_MISC_CONF_AHBM_RST_INTER_Pos = 0x0
	// Bit mask of AHBM_RST_INTER field.
	AHB_DMA_MISC_CONF_AHBM_RST_INTER_Msk = 0x1
	// Bit AHBM_RST_INTER.
	AHB_DMA_MISC_CONF_AHBM_RST_INTER = 0x1
	// Position of ARB_PRI_DIS field.
	AHB_DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x2
	// Bit mask of ARB_PRI_DIS field.
	AHB_DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x4
	// Bit ARB_PRI_DIS.
	AHB_DMA_MISC_CONF_ARB_PRI_DIS = 0x4
	// Position of CLK_EN field.
	AHB_DMA_MISC_CONF_CLK_EN_Pos = 0x3
	// Bit mask of CLK_EN field.
	AHB_DMA_MISC_CONF_CLK_EN_Msk = 0x8
	// Bit CLK_EN.
	AHB_DMA_MISC_CONF_CLK_EN = 0x8

	// DATE: Version control register
	// Position of DATE field.
	AHB_DMA_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	AHB_DMA_DATE_DATE_Msk = 0xffffffff

	// IN_CONF0_CH0: Configure 0 register of Rx channel 0
	// Position of IN_RST_CH field.
	AHB_DMA_IN_CONF0_CH_IN_RST_CH_Pos = 0x0
	// Bit mask of IN_RST_CH field.
	AHB_DMA_IN_CONF0_CH_IN_RST_CH_Msk = 0x1
	// Bit IN_RST_CH.
	AHB_DMA_IN_CONF0_CH_IN_RST_CH = 0x1
	// Position of IN_LOOP_TEST_CH field.
	AHB_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH_Pos = 0x1
	// Bit mask of IN_LOOP_TEST_CH field.
	AHB_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH_Msk = 0x2
	// Bit IN_LOOP_TEST_CH.
	AHB_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH = 0x2
	// Position of INDSCR_BURST_EN_CH field.
	AHB_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH_Pos = 0x2
	// Bit mask of INDSCR_BURST_EN_CH field.
	AHB_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH_Msk = 0x4
	// Bit INDSCR_BURST_EN_CH.
	AHB_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH = 0x4
	// Position of IN_DATA_BURST_EN_CH field.
	AHB_DMA_IN_CONF0_CH_IN_DATA_BURST_EN_CH_Pos = 0x3
	// Bit mask of IN_DATA_BURST_EN_CH field.
	AHB_DMA_IN_CONF0_CH_IN_DATA_BURST_EN_CH_Msk = 0x8
	// Bit IN_DATA_BURST_EN_CH.
	AHB_DMA_IN_CONF0_CH_IN_DATA_BURST_EN_CH = 0x8
	// Position of MEM_TRANS_EN_CH field.
	AHB_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH_Pos = 0x4
	// Bit mask of MEM_TRANS_EN_CH field.
	AHB_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH_Msk = 0x10
	// Bit MEM_TRANS_EN_CH.
	AHB_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH = 0x10
	// Position of IN_ETM_EN_CH field.
	AHB_DMA_IN_CONF0_CH_IN_ETM_EN_CH_Pos = 0x5
	// Bit mask of IN_ETM_EN_CH field.
	AHB_DMA_IN_CONF0_CH_IN_ETM_EN_CH_Msk = 0x20
	// Bit IN_ETM_EN_CH.
	AHB_DMA_IN_CONF0_CH_IN_ETM_EN_CH = 0x20

	// IN_CONF1_CH0: Configure 1 register of Rx channel 0
	// Position of IN_CHECK_OWNER_CH field.
	AHB_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH_Pos = 0xc
	// Bit mask of IN_CHECK_OWNER_CH field.
	AHB_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH_Msk = 0x1000
	// Bit IN_CHECK_OWNER_CH.
	AHB_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH = 0x1000

	// INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0
	// Position of INFIFO_FULL_CH field.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_FULL_CH_Pos = 0x0
	// Bit mask of INFIFO_FULL_CH field.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_FULL_CH_Msk = 0x1
	// Bit INFIFO_FULL_CH.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_FULL_CH = 0x1
	// Position of INFIFO_EMPTY_CH field.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_CH_Pos = 0x1
	// Bit mask of INFIFO_EMPTY_CH field.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_CH_Msk = 0x2
	// Bit INFIFO_EMPTY_CH.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_EMPTY_CH = 0x2
	// Position of INFIFO_CNT_CH field.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_CNT_CH_Pos = 0x2
	// Bit mask of INFIFO_CNT_CH field.
	AHB_DMA_INFIFO_STATUS_CH_INFIFO_CNT_CH_Msk = 0xfc
	// Position of IN_REMAIN_UNDER_1B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH_Pos = 0x17
	// Bit mask of IN_REMAIN_UNDER_1B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH_Msk = 0x800000
	// Bit IN_REMAIN_UNDER_1B_CH.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH = 0x800000
	// Position of IN_REMAIN_UNDER_2B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH_Pos = 0x18
	// Bit mask of IN_REMAIN_UNDER_2B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH_Msk = 0x1000000
	// Bit IN_REMAIN_UNDER_2B_CH.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH = 0x1000000
	// Position of IN_REMAIN_UNDER_3B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH_Pos = 0x19
	// Bit mask of IN_REMAIN_UNDER_3B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH_Msk = 0x2000000
	// Bit IN_REMAIN_UNDER_3B_CH.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH = 0x2000000
	// Position of IN_REMAIN_UNDER_4B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH_Pos = 0x1a
	// Bit mask of IN_REMAIN_UNDER_4B_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH_Msk = 0x4000000
	// Bit IN_REMAIN_UNDER_4B_CH.
	AHB_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH = 0x4000000
	// Position of IN_BUF_HUNGRY_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH_Pos = 0x1b
	// Bit mask of IN_BUF_HUNGRY_CH field.
	AHB_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH_Msk = 0x8000000
	// Bit IN_BUF_HUNGRY_CH.
	AHB_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH = 0x8000000

	// IN_POP_CH0: Pop control register of Rx channel 0
	// Position of INFIFO_RDATA_CH field.
	AHB_DMA_IN_POP_CH_INFIFO_RDATA_CH_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH field.
	AHB_DMA_IN_POP_CH_INFIFO_RDATA_CH_Msk = 0xfff
	// Position of INFIFO_POP_CH field.
	AHB_DMA_IN_POP_CH_INFIFO_POP_CH_Pos = 0xc
	// Bit mask of INFIFO_POP_CH field.
	AHB_DMA_IN_POP_CH_INFIFO_POP_CH_Msk = 0x1000
	// Bit INFIFO_POP_CH.
	AHB_DMA_IN_POP_CH_INFIFO_POP_CH = 0x1000

	// IN_LINK_CH0: Link descriptor configure and control register of Rx channel 0
	// Position of INLINK_AUTO_RET_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_AUTO_RET_CH_Pos = 0x0
	// Bit mask of INLINK_AUTO_RET_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_AUTO_RET_CH_Msk = 0x1
	// Bit INLINK_AUTO_RET_CH.
	AHB_DMA_IN_LINK_CH_INLINK_AUTO_RET_CH = 0x1
	// Position of INLINK_STOP_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_STOP_CH_Pos = 0x1
	// Bit mask of INLINK_STOP_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_STOP_CH_Msk = 0x2
	// Bit INLINK_STOP_CH.
	AHB_DMA_IN_LINK_CH_INLINK_STOP_CH = 0x2
	// Position of INLINK_START_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_START_CH_Pos = 0x2
	// Bit mask of INLINK_START_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_START_CH_Msk = 0x4
	// Bit INLINK_START_CH.
	AHB_DMA_IN_LINK_CH_INLINK_START_CH = 0x4
	// Position of INLINK_RESTART_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_RESTART_CH_Pos = 0x3
	// Bit mask of INLINK_RESTART_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_RESTART_CH_Msk = 0x8
	// Bit INLINK_RESTART_CH.
	AHB_DMA_IN_LINK_CH_INLINK_RESTART_CH = 0x8
	// Position of INLINK_PARK_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_PARK_CH_Pos = 0x4
	// Bit mask of INLINK_PARK_CH field.
	AHB_DMA_IN_LINK_CH_INLINK_PARK_CH_Msk = 0x10
	// Bit INLINK_PARK_CH.
	AHB_DMA_IN_LINK_CH_INLINK_PARK_CH = 0x10

	// IN_STATE_CH0: Receive status of Rx channel 0
	// Position of INLINK_DSCR_ADDR_CH field.
	AHB_DMA_IN_STATE_CH_INLINK_DSCR_ADDR_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_ADDR_CH field.
	AHB_DMA_IN_STATE_CH_INLINK_DSCR_ADDR_CH_Msk = 0x3ffff
	// Position of IN_DSCR_STATE_CH field.
	AHB_DMA_IN_STATE_CH_IN_DSCR_STATE_CH_Pos = 0x12
	// Bit mask of IN_DSCR_STATE_CH field.
	AHB_DMA_IN_STATE_CH_IN_DSCR_STATE_CH_Msk = 0xc0000
	// Position of IN_STATE_CH field.
	AHB_DMA_IN_STATE_CH_IN_STATE_CH_Pos = 0x14
	// Bit mask of IN_STATE_CH field.
	AHB_DMA_IN_STATE_CH_IN_STATE_CH_Msk = 0x700000

	// IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0
	// Position of IN_SUC_EOF_DES_ADDR_CH field.
	AHB_DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_CH_Pos = 0x0
	// Bit mask of IN_SUC_EOF_DES_ADDR_CH field.
	AHB_DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_CH_Msk = 0xffffffff

	// IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0
	// Position of IN_ERR_EOF_DES_ADDR_CH field.
	AHB_DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_CH_Pos = 0x0
	// Bit mask of IN_ERR_EOF_DES_ADDR_CH field.
	AHB_DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_CH_Msk = 0xffffffff

	// IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0
	// Position of INLINK_DSCR_CH field.
	AHB_DMA_IN_DSCR_CH_INLINK_DSCR_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_CH field.
	AHB_DMA_IN_DSCR_CH_INLINK_DSCR_CH_Msk = 0xffffffff

	// IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0
	// Position of INLINK_DSCR_BF0_CH field.
	AHB_DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF0_CH field.
	AHB_DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_CH_Msk = 0xffffffff

	// IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0
	// Position of INLINK_DSCR_BF1_CH field.
	AHB_DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF1_CH field.
	AHB_DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_CH_Msk = 0xffffffff

	// IN_PRI_CH0: Priority register of Rx channel 0
	// Position of RX_PRI_CH field.
	AHB_DMA_IN_PRI_CH_RX_PRI_CH_Pos = 0x0
	// Bit mask of RX_PRI_CH field.
	AHB_DMA_IN_PRI_CH_RX_PRI_CH_Msk = 0xf

	// IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0
	// Position of PERI_IN_SEL_CH field.
	AHB_DMA_IN_PERI_SEL_CH_PERI_IN_SEL_CH_Pos = 0x0
	// Bit mask of PERI_IN_SEL_CH field.
	AHB_DMA_IN_PERI_SEL_CH_PERI_IN_SEL_CH_Msk = 0x3f

	// OUT_CONF0_CH0: Configure 0 register of Tx channel 0
	// Position of OUT_RST_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Pos = 0x0
	// Bit mask of OUT_RST_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Msk = 0x1
	// Bit OUT_RST_CH0.
	AHB_DMA_OUT_CONF0_CH0_OUT_RST_CH0 = 0x1
	// Position of OUT_LOOP_TEST_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0_Pos = 0x1
	// Bit mask of OUT_LOOP_TEST_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0_Msk = 0x2
	// Bit OUT_LOOP_TEST_CH0.
	AHB_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0 = 0x2
	// Position of OUT_AUTO_WRBACK_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Pos = 0x2
	// Bit mask of OUT_AUTO_WRBACK_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Msk = 0x4
	// Bit OUT_AUTO_WRBACK_CH0.
	AHB_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0 = 0x4
	// Position of OUT_EOF_MODE_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Pos = 0x3
	// Bit mask of OUT_EOF_MODE_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Msk = 0x8
	// Bit OUT_EOF_MODE_CH0.
	AHB_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0 = 0x8
	// Position of OUTDSCR_BURST_EN_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Pos = 0x4
	// Bit mask of OUTDSCR_BURST_EN_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Msk = 0x10
	// Bit OUTDSCR_BURST_EN_CH0.
	AHB_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0 = 0x10
	// Position of OUT_DATA_BURST_EN_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0_Pos = 0x5
	// Bit mask of OUT_DATA_BURST_EN_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0_Msk = 0x20
	// Bit OUT_DATA_BURST_EN_CH0.
	AHB_DMA_OUT_CONF0_CH0_OUT_DATA_BURST_EN_CH0 = 0x20
	// Position of OUT_ETM_EN_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0_Pos = 0x6
	// Bit mask of OUT_ETM_EN_CH0 field.
	AHB_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0_Msk = 0x40
	// Bit OUT_ETM_EN_CH0.
	AHB_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0 = 0x40

	// OUT_CONF1_CH0: Configure 1 register of Tx channel 0
	// Position of OUT_CHECK_OWNER_CH field.
	AHB_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH_Pos = 0xc
	// Bit mask of OUT_CHECK_OWNER_CH field.
	AHB_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH_Msk = 0x1000
	// Bit OUT_CHECK_OWNER_CH.
	AHB_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH = 0x1000

	// OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel 0
	// Position of OUTFIFO_FULL_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_CH_Pos = 0x0
	// Bit mask of OUTFIFO_FULL_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_CH_Msk = 0x1
	// Bit OUTFIFO_FULL_CH.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_FULL_CH = 0x1
	// Position of OUTFIFO_EMPTY_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_CH_Pos = 0x1
	// Bit mask of OUTFIFO_EMPTY_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_CH_Msk = 0x2
	// Bit OUTFIFO_EMPTY_CH.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_EMPTY_CH = 0x2
	// Position of OUTFIFO_CNT_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_CH_Pos = 0x2
	// Bit mask of OUTFIFO_CNT_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUTFIFO_CNT_CH_Msk = 0xfc
	// Position of OUT_REMAIN_UNDER_1B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH_Pos = 0x17
	// Bit mask of OUT_REMAIN_UNDER_1B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH_Msk = 0x800000
	// Bit OUT_REMAIN_UNDER_1B_CH.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH = 0x800000
	// Position of OUT_REMAIN_UNDER_2B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH_Pos = 0x18
	// Bit mask of OUT_REMAIN_UNDER_2B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH_Msk = 0x1000000
	// Bit OUT_REMAIN_UNDER_2B_CH.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH = 0x1000000
	// Position of OUT_REMAIN_UNDER_3B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH_Pos = 0x19
	// Bit mask of OUT_REMAIN_UNDER_3B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH_Msk = 0x2000000
	// Bit OUT_REMAIN_UNDER_3B_CH.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH = 0x2000000
	// Position of OUT_REMAIN_UNDER_4B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH_Pos = 0x1a
	// Bit mask of OUT_REMAIN_UNDER_4B_CH field.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH_Msk = 0x4000000
	// Bit OUT_REMAIN_UNDER_4B_CH.
	AHB_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH = 0x4000000

	// OUT_PUSH_CH0: Push control register of Rx channel 0
	// Position of OUTFIFO_WDATA_CH field.
	AHB_DMA_OUT_PUSH_CH_OUTFIFO_WDATA_CH_Pos = 0x0
	// Bit mask of OUTFIFO_WDATA_CH field.
	AHB_DMA_OUT_PUSH_CH_OUTFIFO_WDATA_CH_Msk = 0x1ff
	// Position of OUTFIFO_PUSH_CH field.
	AHB_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH_Pos = 0x9
	// Bit mask of OUTFIFO_PUSH_CH field.
	AHB_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH_Msk = 0x200
	// Bit OUTFIFO_PUSH_CH.
	AHB_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH = 0x200

	// OUT_LINK_CH0: Link descriptor configure and control register of Tx channel 0
	// Position of OUTLINK_STOP_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_STOP_CH_Pos = 0x0
	// Bit mask of OUTLINK_STOP_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_STOP_CH_Msk = 0x1
	// Bit OUTLINK_STOP_CH.
	AHB_DMA_OUT_LINK_CH_OUTLINK_STOP_CH = 0x1
	// Position of OUTLINK_START_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_START_CH_Pos = 0x1
	// Bit mask of OUTLINK_START_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_START_CH_Msk = 0x2
	// Bit OUTLINK_START_CH.
	AHB_DMA_OUT_LINK_CH_OUTLINK_START_CH = 0x2
	// Position of OUTLINK_RESTART_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_RESTART_CH_Pos = 0x2
	// Bit mask of OUTLINK_RESTART_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_RESTART_CH_Msk = 0x4
	// Bit OUTLINK_RESTART_CH.
	AHB_DMA_OUT_LINK_CH_OUTLINK_RESTART_CH = 0x4
	// Position of OUTLINK_PARK_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_PARK_CH_Pos = 0x3
	// Bit mask of OUTLINK_PARK_CH field.
	AHB_DMA_OUT_LINK_CH_OUTLINK_PARK_CH_Msk = 0x8
	// Bit OUTLINK_PARK_CH.
	AHB_DMA_OUT_LINK_CH_OUTLINK_PARK_CH = 0x8

	// OUT_STATE_CH0: Transmit status of Tx channel 0
	// Position of OUTLINK_DSCR_ADDR_CH field.
	AHB_DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_ADDR_CH field.
	AHB_DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_CH_Msk = 0x3ffff
	// Position of OUT_DSCR_STATE_CH field.
	AHB_DMA_OUT_STATE_CH_OUT_DSCR_STATE_CH_Pos = 0x12
	// Bit mask of OUT_DSCR_STATE_CH field.
	AHB_DMA_OUT_STATE_CH_OUT_DSCR_STATE_CH_Msk = 0xc0000
	// Position of OUT_STATE_CH field.
	AHB_DMA_OUT_STATE_CH_OUT_STATE_CH_Pos = 0x14
	// Bit mask of OUT_STATE_CH field.
	AHB_DMA_OUT_STATE_CH_OUT_STATE_CH_Msk = 0x700000

	// OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel 0
	// Position of OUT_EOF_DES_ADDR_CH field.
	AHB_DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_CH_Pos = 0x0
	// Bit mask of OUT_EOF_DES_ADDR_CH field.
	AHB_DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_CH_Msk = 0xffffffff

	// OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel 0
	// Position of OUT_EOF_BFR_DES_ADDR_CH field.
	AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_CH_Pos = 0x0
	// Bit mask of OUT_EOF_BFR_DES_ADDR_CH field.
	AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_CH_Msk = 0xffffffff

	// OUT_DSCR_CH0: Current inlink descriptor address of Tx channel 0
	// Position of OUTLINK_DSCR_CH field.
	AHB_DMA_OUT_DSCR_CH_OUTLINK_DSCR_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_CH field.
	AHB_DMA_OUT_DSCR_CH_OUTLINK_DSCR_CH_Msk = 0xffffffff

	// OUT_DSCR_BF0_CH0: The last inlink descriptor address of Tx channel 0
	// Position of OUTLINK_DSCR_BF0_CH field.
	AHB_DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF0_CH field.
	AHB_DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_CH_Msk = 0xffffffff

	// OUT_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Tx channel 0
	// Position of OUTLINK_DSCR_BF1_CH field.
	AHB_DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF1_CH field.
	AHB_DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_CH_Msk = 0xffffffff

	// OUT_PRI_CH0: Priority register of Tx channel 0.
	// Position of TX_PRI_CH field.
	AHB_DMA_OUT_PRI_CH_TX_PRI_CH_Pos = 0x0
	// Bit mask of TX_PRI_CH field.
	AHB_DMA_OUT_PRI_CH_TX_PRI_CH_Msk = 0xf

	// OUT_PERI_SEL_CH0: Peripheral selection of Tx channel 0
	// Position of PERI_OUT_SEL_CH field.
	AHB_DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_CH_Pos = 0x0
	// Bit mask of PERI_OUT_SEL_CH field.
	AHB_DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_CH_Msk = 0x3f

	// OUT_CONF0_CH0: Configure 0 register of Tx channel 1
	// Position of OUT_RST_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_RST_CH_Pos = 0x0
	// Bit mask of OUT_RST_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_RST_CH_Msk = 0x1
	// Bit OUT_RST_CH.
	AHB_DMA_OUT_CONF0_CH_OUT_RST_CH = 0x1
	// Position of OUT_LOOP_TEST_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_LOOP_TEST_CH_Pos = 0x1
	// Bit mask of OUT_LOOP_TEST_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_LOOP_TEST_CH_Msk = 0x2
	// Bit OUT_LOOP_TEST_CH.
	AHB_DMA_OUT_CONF0_CH_OUT_LOOP_TEST_CH = 0x2
	// Position of OUT_AUTO_WRBACK_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_CH_Pos = 0x2
	// Bit mask of OUT_AUTO_WRBACK_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_CH_Msk = 0x4
	// Bit OUT_AUTO_WRBACK_CH.
	AHB_DMA_OUT_CONF0_CH_OUT_AUTO_WRBACK_CH = 0x4
	// Position of OUT_EOF_MODE_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_EOF_MODE_CH_Pos = 0x3
	// Bit mask of OUT_EOF_MODE_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_EOF_MODE_CH_Msk = 0x8
	// Bit OUT_EOF_MODE_CH.
	AHB_DMA_OUT_CONF0_CH_OUT_EOF_MODE_CH = 0x8
	// Position of OUTDSCR_BURST_EN_CH field.
	AHB_DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_CH_Pos = 0x4
	// Bit mask of OUTDSCR_BURST_EN_CH field.
	AHB_DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_CH_Msk = 0x10
	// Bit OUTDSCR_BURST_EN_CH.
	AHB_DMA_OUT_CONF0_CH_OUTDSCR_BURST_EN_CH = 0x10
	// Position of OUT_DATA_BURST_EN_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_CH_Pos = 0x5
	// Bit mask of OUT_DATA_BURST_EN_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_CH_Msk = 0x20
	// Bit OUT_DATA_BURST_EN_CH.
	AHB_DMA_OUT_CONF0_CH_OUT_DATA_BURST_EN_CH = 0x20
	// Position of OUT_ETM_EN_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_ETM_EN_CH_Pos = 0x6
	// Bit mask of OUT_ETM_EN_CH field.
	AHB_DMA_OUT_CONF0_CH_OUT_ETM_EN_CH_Msk = 0x40
	// Bit OUT_ETM_EN_CH.
	AHB_DMA_OUT_CONF0_CH_OUT_ETM_EN_CH = 0x40

	// OUT_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
	// Position of OUT_CRC_INIT_DATA_CH field.
	AHB_DMA_OUT_CRC_INIT_DATA_CH_OUT_CRC_INIT_DATA_CH_Pos = 0x0
	// Bit mask of OUT_CRC_INIT_DATA_CH field.
	AHB_DMA_OUT_CRC_INIT_DATA_CH_OUT_CRC_INIT_DATA_CH_Msk = 0xffffffff

	// TX_CRC_WIDTH_CH0: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
	// Position of TX_CRC_WIDTH_CH field.
	AHB_DMA_TX_CRC_WIDTH_CH_TX_CRC_WIDTH_CH_Pos = 0x0
	// Bit mask of TX_CRC_WIDTH_CH field.
	AHB_DMA_TX_CRC_WIDTH_CH_TX_CRC_WIDTH_CH_Msk = 0x3
	// Position of TX_CRC_LAUTCH_FLGA_CH field.
	AHB_DMA_TX_CRC_WIDTH_CH_TX_CRC_LAUTCH_FLGA_CH_Pos = 0x2
	// Bit mask of TX_CRC_LAUTCH_FLGA_CH field.
	AHB_DMA_TX_CRC_WIDTH_CH_TX_CRC_LAUTCH_FLGA_CH_Msk = 0x4
	// Bit TX_CRC_LAUTCH_FLGA_CH.
	AHB_DMA_TX_CRC_WIDTH_CH_TX_CRC_LAUTCH_FLGA_CH = 0x4

	// OUT_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
	// Position of OUT_CRC_CLEAR_CH field.
	AHB_DMA_OUT_CRC_CLEAR_CH_OUT_CRC_CLEAR_CH_Pos = 0x0
	// Bit mask of OUT_CRC_CLEAR_CH field.
	AHB_DMA_OUT_CRC_CLEAR_CH_OUT_CRC_CLEAR_CH_Msk = 0x1
	// Bit OUT_CRC_CLEAR_CH.
	AHB_DMA_OUT_CRC_CLEAR_CH_OUT_CRC_CLEAR_CH = 0x1

	// OUT_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
	// Position of OUT_CRC_FINAL_RESULT_CH field.
	AHB_DMA_OUT_CRC_FINAL_RESULT_CH_OUT_CRC_FINAL_RESULT_CH_Pos = 0x0
	// Bit mask of OUT_CRC_FINAL_RESULT_CH field.
	AHB_DMA_OUT_CRC_FINAL_RESULT_CH_OUT_CRC_FINAL_RESULT_CH_Msk = 0xffffffff

	// TX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
	// Position of TX_CRC_EN_WR_DATA_CH field.
	AHB_DMA_TX_CRC_EN_WR_DATA_CH_TX_CRC_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of TX_CRC_EN_WR_DATA_CH field.
	AHB_DMA_TX_CRC_EN_WR_DATA_CH_TX_CRC_EN_WR_DATA_CH_Msk = 0xffffffff

	// TX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
	// Position of TX_CRC_EN_ADDR_CH field.
	AHB_DMA_TX_CRC_EN_ADDR_CH_TX_CRC_EN_ADDR_CH_Pos = 0x0
	// Bit mask of TX_CRC_EN_ADDR_CH field.
	AHB_DMA_TX_CRC_EN_ADDR_CH_TX_CRC_EN_ADDR_CH_Msk = 0xffffffff

	// TX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
	// Position of TX_CRC_DATA_EN_WR_DATA_CH field.
	AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH_TX_CRC_DATA_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of TX_CRC_DATA_EN_WR_DATA_CH field.
	AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH_TX_CRC_DATA_EN_WR_DATA_CH_Msk = 0xff

	// TX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
	// Position of TX_CRC_DATA_EN_ADDR_CH field.
	AHB_DMA_TX_CRC_DATA_EN_ADDR_CH_TX_CRC_DATA_EN_ADDR_CH_Pos = 0x0
	// Bit mask of TX_CRC_DATA_EN_ADDR_CH field.
	AHB_DMA_TX_CRC_DATA_EN_ADDR_CH_TX_CRC_DATA_EN_ADDR_CH_Msk = 0xffffffff

	// TX_CH_ARB_WEIGH_CH0: This register is used to config ch0 arbiter weigh
	// Position of TX_CH_ARB_WEIGH_CH field.
	AHB_DMA_TX_CH_ARB_WEIGH_CH_TX_CH_ARB_WEIGH_CH_Pos = 0x0
	// Bit mask of TX_CH_ARB_WEIGH_CH field.
	AHB_DMA_TX_CH_ARB_WEIGH_CH_TX_CH_ARB_WEIGH_CH_Msk = 0xf

	// TX_ARB_WEIGH_OPT_DIR_CH0: This register is used to config off or on weigh optimization
	// Position of TX_ARB_WEIGH_OPT_DIR_CH field.
	AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH_TX_ARB_WEIGH_OPT_DIR_CH_Pos = 0x0
	// Bit mask of TX_ARB_WEIGH_OPT_DIR_CH field.
	AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH_TX_ARB_WEIGH_OPT_DIR_CH_Msk = 0x1
	// Bit TX_ARB_WEIGH_OPT_DIR_CH.
	AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH_TX_ARB_WEIGH_OPT_DIR_CH = 0x1

	// IN_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
	// Position of IN_CRC_INIT_DATA_CH field.
	AHB_DMA_IN_CRC_INIT_DATA_CH_IN_CRC_INIT_DATA_CH_Pos = 0x0
	// Bit mask of IN_CRC_INIT_DATA_CH field.
	AHB_DMA_IN_CRC_INIT_DATA_CH_IN_CRC_INIT_DATA_CH_Msk = 0xffffffff

	// RX_CRC_WIDTH_CH0: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
	// Position of RX_CRC_WIDTH_CH field.
	AHB_DMA_RX_CRC_WIDTH_CH_RX_CRC_WIDTH_CH_Pos = 0x0
	// Bit mask of RX_CRC_WIDTH_CH field.
	AHB_DMA_RX_CRC_WIDTH_CH_RX_CRC_WIDTH_CH_Msk = 0x3
	// Position of RX_CRC_LAUTCH_FLGA_CH field.
	AHB_DMA_RX_CRC_WIDTH_CH_RX_CRC_LAUTCH_FLGA_CH_Pos = 0x2
	// Bit mask of RX_CRC_LAUTCH_FLGA_CH field.
	AHB_DMA_RX_CRC_WIDTH_CH_RX_CRC_LAUTCH_FLGA_CH_Msk = 0x4
	// Bit RX_CRC_LAUTCH_FLGA_CH.
	AHB_DMA_RX_CRC_WIDTH_CH_RX_CRC_LAUTCH_FLGA_CH = 0x4

	// IN_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
	// Position of IN_CRC_CLEAR_CH field.
	AHB_DMA_IN_CRC_CLEAR_CH_IN_CRC_CLEAR_CH_Pos = 0x0
	// Bit mask of IN_CRC_CLEAR_CH field.
	AHB_DMA_IN_CRC_CLEAR_CH_IN_CRC_CLEAR_CH_Msk = 0x1
	// Bit IN_CRC_CLEAR_CH.
	AHB_DMA_IN_CRC_CLEAR_CH_IN_CRC_CLEAR_CH = 0x1

	// IN_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
	// Position of IN_CRC_FINAL_RESULT_CH field.
	AHB_DMA_IN_CRC_FINAL_RESULT_CH_IN_CRC_FINAL_RESULT_CH_Pos = 0x0
	// Bit mask of IN_CRC_FINAL_RESULT_CH field.
	AHB_DMA_IN_CRC_FINAL_RESULT_CH_IN_CRC_FINAL_RESULT_CH_Msk = 0xffffffff

	// RX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
	// Position of RX_CRC_EN_WR_DATA_CH field.
	AHB_DMA_RX_CRC_EN_WR_DATA_CH_RX_CRC_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of RX_CRC_EN_WR_DATA_CH field.
	AHB_DMA_RX_CRC_EN_WR_DATA_CH_RX_CRC_EN_WR_DATA_CH_Msk = 0xffffffff

	// RX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
	// Position of RX_CRC_EN_ADDR_CH field.
	AHB_DMA_RX_CRC_EN_ADDR_CH_RX_CRC_EN_ADDR_CH_Pos = 0x0
	// Bit mask of RX_CRC_EN_ADDR_CH field.
	AHB_DMA_RX_CRC_EN_ADDR_CH_RX_CRC_EN_ADDR_CH_Msk = 0xffffffff

	// RX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
	// Position of RX_CRC_DATA_EN_WR_DATA_CH field.
	AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH_RX_CRC_DATA_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of RX_CRC_DATA_EN_WR_DATA_CH field.
	AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH_RX_CRC_DATA_EN_WR_DATA_CH_Msk = 0xff

	// RX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
	// Position of RX_CRC_DATA_EN_ADDR_CH field.
	AHB_DMA_RX_CRC_DATA_EN_ADDR_CH_RX_CRC_DATA_EN_ADDR_CH_Pos = 0x0
	// Bit mask of RX_CRC_DATA_EN_ADDR_CH field.
	AHB_DMA_RX_CRC_DATA_EN_ADDR_CH_RX_CRC_DATA_EN_ADDR_CH_Msk = 0xffffffff

	// RX_CH_ARB_WEIGH_CH0: This register is used to config ch0 arbiter weigh
	// Position of RX_CH_ARB_WEIGH_CH field.
	AHB_DMA_RX_CH_ARB_WEIGH_CH_RX_CH_ARB_WEIGH_CH_Pos = 0x0
	// Bit mask of RX_CH_ARB_WEIGH_CH field.
	AHB_DMA_RX_CH_ARB_WEIGH_CH_RX_CH_ARB_WEIGH_CH_Msk = 0xf

	// RX_ARB_WEIGH_OPT_DIR_CH0: This register is used to config off or on weigh optimization
	// Position of RX_ARB_WEIGH_OPT_DIR_CH field.
	AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH_RX_ARB_WEIGH_OPT_DIR_CH_Pos = 0x0
	// Bit mask of RX_ARB_WEIGH_OPT_DIR_CH field.
	AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH_RX_ARB_WEIGH_OPT_DIR_CH_Msk = 0x1
	// Bit RX_ARB_WEIGH_OPT_DIR_CH.
	AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH_RX_ARB_WEIGH_OPT_DIR_CH = 0x1

	// IN_LINK_ADDR_CH0: Link descriptor configure of Rx channel 0
	// Position of INLINK_ADDR_CH field.
	AHB_DMA_IN_LINK_ADDR_CH_INLINK_ADDR_CH_Pos = 0x0
	// Bit mask of INLINK_ADDR_CH field.
	AHB_DMA_IN_LINK_ADDR_CH_INLINK_ADDR_CH_Msk = 0xffffffff

	// OUT_LINK_ADDR_CH0: Link descriptor configure of Tx channel 0
	// Position of OUTLINK_ADDR_CH field.
	AHB_DMA_OUT_LINK_ADDR_CH_OUTLINK_ADDR_CH_Pos = 0x0
	// Bit mask of OUTLINK_ADDR_CH field.
	AHB_DMA_OUT_LINK_ADDR_CH_OUTLINK_ADDR_CH_Msk = 0xffffffff

	// INTR_MEM_START_ADDR: The start address of accessible address space.
	// Position of ACCESS_INTR_MEM_START_ADDR field.
	AHB_DMA_INTR_MEM_START_ADDR_ACCESS_INTR_MEM_START_ADDR_Pos = 0x0
	// Bit mask of ACCESS_INTR_MEM_START_ADDR field.
	AHB_DMA_INTR_MEM_START_ADDR_ACCESS_INTR_MEM_START_ADDR_Msk = 0xffffffff

	// INTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error.
	// Position of ACCESS_INTR_MEM_END_ADDR field.
	AHB_DMA_INTR_MEM_END_ADDR_ACCESS_INTR_MEM_END_ADDR_Pos = 0x0
	// Bit mask of ACCESS_INTR_MEM_END_ADDR field.
	AHB_DMA_INTR_MEM_END_ADDR_ACCESS_INTR_MEM_END_ADDR_Msk = 0xffffffff

	// ARB_TIMEOUT_TX: This retister is used to config arbiter time slice for tx dir
	// Position of ARB_TIMEOUT_TX field.
	AHB_DMA_ARB_TIMEOUT_TX_ARB_TIMEOUT_TX_Pos = 0x0
	// Bit mask of ARB_TIMEOUT_TX field.
	AHB_DMA_ARB_TIMEOUT_TX_ARB_TIMEOUT_TX_Msk = 0xffff

	// ARB_TIMEOUT_RX: This retister is used to config arbiter time slice for rx dir
	// Position of ARB_TIMEOUT_RX field.
	AHB_DMA_ARB_TIMEOUT_RX_ARB_TIMEOUT_RX_Pos = 0x0
	// Bit mask of ARB_TIMEOUT_RX field.
	AHB_DMA_ARB_TIMEOUT_RX_ARB_TIMEOUT_RX_Msk = 0xffff

	// WEIGHT_EN_TX: This register is used to config arbiter weigh function to on or off for tx dir
	// Position of WEIGHT_EN_TX field.
	AHB_DMA_WEIGHT_EN_TX_WEIGHT_EN_TX_Pos = 0x0
	// Bit mask of WEIGHT_EN_TX field.
	AHB_DMA_WEIGHT_EN_TX_WEIGHT_EN_TX_Msk = 0x1
	// Bit WEIGHT_EN_TX.
	AHB_DMA_WEIGHT_EN_TX_WEIGHT_EN_TX = 0x1

	// WEIGHT_EN_RX: This register is used to config arbiter weigh function to on or off for rx dir
	// Position of WEIGHT_EN_RX field.
	AHB_DMA_WEIGHT_EN_RX_WEIGHT_EN_RX_Pos = 0x0
	// Bit mask of WEIGHT_EN_RX field.
	AHB_DMA_WEIGHT_EN_RX_WEIGHT_EN_RX_Msk = 0x1
	// Bit WEIGHT_EN_RX.
	AHB_DMA_WEIGHT_EN_RX_WEIGHT_EN_RX = 0x1
)

// Constants for LP_I2C_ANA_MST: LP_I2C_ANA_MST Peripheral
const (
	// I2C0_CTRL: need des
	// Position of I2C0_CTRL field.
	ANA_I2C_MST_I2C0_CTRL_I2C0_CTRL_Pos = 0x0
	// Bit mask of I2C0_CTRL field.
	ANA_I2C_MST_I2C0_CTRL_I2C0_CTRL_Msk = 0x1ffffff
	// Position of I2C0_BUSY field.
	ANA_I2C_MST_I2C0_CTRL_I2C0_BUSY_Pos = 0x19
	// Bit mask of I2C0_BUSY field.
	ANA_I2C_MST_I2C0_CTRL_I2C0_BUSY_Msk = 0x2000000
	// Bit I2C0_BUSY.
	ANA_I2C_MST_I2C0_CTRL_I2C0_BUSY = 0x2000000

	// I2C1_CTRL: need des
	// Position of I2C1_CTRL field.
	ANA_I2C_MST_I2C1_CTRL_I2C1_CTRL_Pos = 0x0
	// Bit mask of I2C1_CTRL field.
	ANA_I2C_MST_I2C1_CTRL_I2C1_CTRL_Msk = 0x1ffffff
	// Position of I2C1_BUSY field.
	ANA_I2C_MST_I2C1_CTRL_I2C1_BUSY_Pos = 0x19
	// Bit mask of I2C1_BUSY field.
	ANA_I2C_MST_I2C1_CTRL_I2C1_BUSY_Msk = 0x2000000
	// Bit I2C1_BUSY.
	ANA_I2C_MST_I2C1_CTRL_I2C1_BUSY = 0x2000000

	// I2C0_CONF: need des
	// Position of I2C0_CONF field.
	ANA_I2C_MST_I2C0_CONF_I2C0_CONF_Pos = 0x0
	// Bit mask of I2C0_CONF field.
	ANA_I2C_MST_I2C0_CONF_I2C0_CONF_Msk = 0xffffff
	// Position of I2C0_STATUS field.
	ANA_I2C_MST_I2C0_CONF_I2C0_STATUS_Pos = 0x18
	// Bit mask of I2C0_STATUS field.
	ANA_I2C_MST_I2C0_CONF_I2C0_STATUS_Msk = 0xff000000

	// I2C1_CONF: need des
	// Position of I2C1_CONF field.
	ANA_I2C_MST_I2C1_CONF_I2C1_CONF_Pos = 0x0
	// Bit mask of I2C1_CONF field.
	ANA_I2C_MST_I2C1_CONF_I2C1_CONF_Msk = 0xffffff
	// Position of I2C1_STATUS field.
	ANA_I2C_MST_I2C1_CONF_I2C1_STATUS_Pos = 0x18
	// Bit mask of I2C1_STATUS field.
	ANA_I2C_MST_I2C1_CONF_I2C1_STATUS_Msk = 0xff000000

	// I2C_BURST_CONF: need des
	// Position of I2C_MST_BURST_CTRL field.
	ANA_I2C_MST_I2C_BURST_CONF_I2C_MST_BURST_CTRL_Pos = 0x0
	// Bit mask of I2C_MST_BURST_CTRL field.
	ANA_I2C_MST_I2C_BURST_CONF_I2C_MST_BURST_CTRL_Msk = 0xffffffff

	// I2C_BURST_STATUS: need des
	// Position of I2C_MST_BURST_DONE field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST_BURST_DONE_Pos = 0x0
	// Bit mask of I2C_MST_BURST_DONE field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST_BURST_DONE_Msk = 0x1
	// Bit I2C_MST_BURST_DONE.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST_BURST_DONE = 0x1
	// Position of I2C_MST0_BURST_ERR_FLAG field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST0_BURST_ERR_FLAG_Pos = 0x1
	// Bit mask of I2C_MST0_BURST_ERR_FLAG field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST0_BURST_ERR_FLAG_Msk = 0x2
	// Bit I2C_MST0_BURST_ERR_FLAG.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST0_BURST_ERR_FLAG = 0x2
	// Position of I2C_MST1_BURST_ERR_FLAG field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST1_BURST_ERR_FLAG_Pos = 0x2
	// Bit mask of I2C_MST1_BURST_ERR_FLAG field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST1_BURST_ERR_FLAG_Msk = 0x4
	// Bit I2C_MST1_BURST_ERR_FLAG.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST1_BURST_ERR_FLAG = 0x4
	// Position of I2C_MST_BURST_TIMEOUT_CNT field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST_BURST_TIMEOUT_CNT_Pos = 0x14
	// Bit mask of I2C_MST_BURST_TIMEOUT_CNT field.
	ANA_I2C_MST_I2C_BURST_STATUS_I2C_MST_BURST_TIMEOUT_CNT_Msk = 0xfff00000

	// ANA_CONF0: need des
	// Position of ANA_CONF0 field.
	ANA_I2C_MST_ANA_CONF0_ANA_CONF0_Pos = 0x0
	// Bit mask of ANA_CONF0 field.
	ANA_I2C_MST_ANA_CONF0_ANA_CONF0_Msk = 0xffffff
	// Position of ANA_STATUS0 field.
	ANA_I2C_MST_ANA_CONF0_ANA_STATUS0_Pos = 0x18
	// Bit mask of ANA_STATUS0 field.
	ANA_I2C_MST_ANA_CONF0_ANA_STATUS0_Msk = 0xff000000

	// ANA_CONF1: need des
	// Position of ANA_CONF1 field.
	ANA_I2C_MST_ANA_CONF1_ANA_CONF1_Pos = 0x0
	// Bit mask of ANA_CONF1 field.
	ANA_I2C_MST_ANA_CONF1_ANA_CONF1_Msk = 0xffffff
	// Position of ANA_STATUS1 field.
	ANA_I2C_MST_ANA_CONF1_ANA_STATUS1_Pos = 0x18
	// Bit mask of ANA_STATUS1 field.
	ANA_I2C_MST_ANA_CONF1_ANA_STATUS1_Msk = 0xff000000

	// ANA_CONF2: need des
	// Position of ANA_CONF2 field.
	ANA_I2C_MST_ANA_CONF2_ANA_CONF2_Pos = 0x0
	// Bit mask of ANA_CONF2 field.
	ANA_I2C_MST_ANA_CONF2_ANA_CONF2_Msk = 0xffffff
	// Position of ANA_STATUS2 field.
	ANA_I2C_MST_ANA_CONF2_ANA_STATUS2_Pos = 0x18
	// Bit mask of ANA_STATUS2 field.
	ANA_I2C_MST_ANA_CONF2_ANA_STATUS2_Msk = 0xff000000

	// I2C0_CTRL1: need des
	// Position of I2C0_SCL_PULSE_DUR field.
	ANA_I2C_MST_I2C0_CTRL1_I2C0_SCL_PULSE_DUR_Pos = 0x0
	// Bit mask of I2C0_SCL_PULSE_DUR field.
	ANA_I2C_MST_I2C0_CTRL1_I2C0_SCL_PULSE_DUR_Msk = 0x3f
	// Position of I2C0_SDA_SIDE_GUARD field.
	ANA_I2C_MST_I2C0_CTRL1_I2C0_SDA_SIDE_GUARD_Pos = 0x6
	// Bit mask of I2C0_SDA_SIDE_GUARD field.
	ANA_I2C_MST_I2C0_CTRL1_I2C0_SDA_SIDE_GUARD_Msk = 0x7c0

	// I2C1_CTRL1: need des
	// Position of I2C1_SCL_PULSE_DUR field.
	ANA_I2C_MST_I2C1_CTRL1_I2C1_SCL_PULSE_DUR_Pos = 0x0
	// Bit mask of I2C1_SCL_PULSE_DUR field.
	ANA_I2C_MST_I2C1_CTRL1_I2C1_SCL_PULSE_DUR_Msk = 0x3f
	// Position of I2C1_SDA_SIDE_GUARD field.
	ANA_I2C_MST_I2C1_CTRL1_I2C1_SDA_SIDE_GUARD_Pos = 0x6
	// Bit mask of I2C1_SDA_SIDE_GUARD field.
	ANA_I2C_MST_I2C1_CTRL1_I2C1_SDA_SIDE_GUARD_Msk = 0x7c0

	// HW_I2C_CTRL: need des
	// Position of HW_I2C_SCL_PULSE_DUR field.
	ANA_I2C_MST_HW_I2C_CTRL_HW_I2C_SCL_PULSE_DUR_Pos = 0x0
	// Bit mask of HW_I2C_SCL_PULSE_DUR field.
	ANA_I2C_MST_HW_I2C_CTRL_HW_I2C_SCL_PULSE_DUR_Msk = 0x3f
	// Position of HW_I2C_SDA_SIDE_GUARD field.
	ANA_I2C_MST_HW_I2C_CTRL_HW_I2C_SDA_SIDE_GUARD_Pos = 0x6
	// Bit mask of HW_I2C_SDA_SIDE_GUARD field.
	ANA_I2C_MST_HW_I2C_CTRL_HW_I2C_SDA_SIDE_GUARD_Msk = 0x7c0
	// Position of ARBITER_DIS field.
	ANA_I2C_MST_HW_I2C_CTRL_ARBITER_DIS_Pos = 0xb
	// Bit mask of ARBITER_DIS field.
	ANA_I2C_MST_HW_I2C_CTRL_ARBITER_DIS_Msk = 0x800
	// Bit ARBITER_DIS.
	ANA_I2C_MST_HW_I2C_CTRL_ARBITER_DIS = 0x800

	// NOUSE: need des
	// Position of I2C_MST_NOUSE field.
	ANA_I2C_MST_NOUSE_I2C_MST_NOUSE_Pos = 0x0
	// Bit mask of I2C_MST_NOUSE field.
	ANA_I2C_MST_NOUSE_I2C_MST_NOUSE_Msk = 0xffffffff

	// CLK160M: need des
	// Position of CLK_I2C_MST_SEL_160M field.
	ANA_I2C_MST_CLK160M_CLK_I2C_MST_SEL_160M_Pos = 0x0
	// Bit mask of CLK_I2C_MST_SEL_160M field.
	ANA_I2C_MST_CLK160M_CLK_I2C_MST_SEL_160M_Msk = 0x1
	// Bit CLK_I2C_MST_SEL_160M.
	ANA_I2C_MST_CLK160M_CLK_I2C_MST_SEL_160M = 0x1

	// DATE: need des
	// Position of DATE field.
	ANA_I2C_MST_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	ANA_I2C_MST_DATE_DATE_Msk = 0xfffffff
	// Position of I2C_MST_CLK_EN field.
	ANA_I2C_MST_DATE_I2C_MST_CLK_EN_Pos = 0x1c
	// Bit mask of I2C_MST_CLK_EN field.
	ANA_I2C_MST_DATE_I2C_MST_CLK_EN_Msk = 0x10000000
	// Bit I2C_MST_CLK_EN.
	ANA_I2C_MST_DATE_I2C_MST_CLK_EN = 0x10000000
)

// Constants for ASSIST_DEBUG: Debug Assist
const (
	// CORE_0_INTR_ENA: core0 monitor enable configuration register
	// Position of CORE_0_AREA_DRAM0_0_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_0_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA_Msk = 0x1
	// Bit CORE_0_AREA_DRAM0_0_RD_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_RD_ENA = 0x1
	// Position of CORE_0_AREA_DRAM0_0_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Pos = 0x1
	// Bit mask of CORE_0_AREA_DRAM0_0_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA_Msk = 0x2
	// Bit CORE_0_AREA_DRAM0_0_WR_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_0_WR_ENA = 0x2
	// Position of CORE_0_AREA_DRAM0_1_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Pos = 0x2
	// Bit mask of CORE_0_AREA_DRAM0_1_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA_Msk = 0x4
	// Bit CORE_0_AREA_DRAM0_1_RD_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_RD_ENA = 0x4
	// Position of CORE_0_AREA_DRAM0_1_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Pos = 0x3
	// Bit mask of CORE_0_AREA_DRAM0_1_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA_Msk = 0x8
	// Bit CORE_0_AREA_DRAM0_1_WR_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_DRAM0_1_WR_ENA = 0x8
	// Position of CORE_0_AREA_PIF_0_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Pos = 0x4
	// Bit mask of CORE_0_AREA_PIF_0_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_ENA_Msk = 0x10
	// Bit CORE_0_AREA_PIF_0_RD_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_RD_ENA = 0x10
	// Position of CORE_0_AREA_PIF_0_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Pos = 0x5
	// Bit mask of CORE_0_AREA_PIF_0_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_ENA_Msk = 0x20
	// Bit CORE_0_AREA_PIF_0_WR_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_0_WR_ENA = 0x20
	// Position of CORE_0_AREA_PIF_1_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Pos = 0x6
	// Bit mask of CORE_0_AREA_PIF_1_RD_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_ENA_Msk = 0x40
	// Bit CORE_0_AREA_PIF_1_RD_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_RD_ENA = 0x40
	// Position of CORE_0_AREA_PIF_1_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Pos = 0x7
	// Bit mask of CORE_0_AREA_PIF_1_WR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_ENA_Msk = 0x80
	// Bit CORE_0_AREA_PIF_1_WR_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_AREA_PIF_1_WR_ENA = 0x80
	// Position of CORE_0_SP_SPILL_MIN_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Pos = 0x8
	// Bit mask of CORE_0_SP_SPILL_MIN_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_ENA_Msk = 0x100
	// Bit CORE_0_SP_SPILL_MIN_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MIN_ENA = 0x100
	// Position of CORE_0_SP_SPILL_MAX_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Pos = 0x9
	// Bit mask of CORE_0_SP_SPILL_MAX_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_ENA_Msk = 0x200
	// Bit CORE_0_SP_SPILL_MAX_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_SP_SPILL_MAX_ENA = 0x200
	// Position of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xa
	// Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x400
	// Bit CORE_0_IRAM0_EXCEPTION_MONITOR_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA = 0x400
	// Position of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xb
	// Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x800
	// Bit CORE_0_DRAM0_EXCEPTION_MONITOR_ENA.
	ASSIST_DEBUG_CORE_0_INTR_ENA_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA = 0x800

	// CORE_0_INTR_RAW: core0 monitor interrupt status register
	// Position of CORE_0_AREA_DRAM0_0_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_0_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW_Msk = 0x1
	// Bit CORE_0_AREA_DRAM0_0_RD_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_RD_RAW = 0x1
	// Position of CORE_0_AREA_DRAM0_0_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Pos = 0x1
	// Bit mask of CORE_0_AREA_DRAM0_0_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW_Msk = 0x2
	// Bit CORE_0_AREA_DRAM0_0_WR_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_0_WR_RAW = 0x2
	// Position of CORE_0_AREA_DRAM0_1_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Pos = 0x2
	// Bit mask of CORE_0_AREA_DRAM0_1_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW_Msk = 0x4
	// Bit CORE_0_AREA_DRAM0_1_RD_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_RD_RAW = 0x4
	// Position of CORE_0_AREA_DRAM0_1_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Pos = 0x3
	// Bit mask of CORE_0_AREA_DRAM0_1_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW_Msk = 0x8
	// Bit CORE_0_AREA_DRAM0_1_WR_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_DRAM0_1_WR_RAW = 0x8
	// Position of CORE_0_AREA_PIF_0_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Pos = 0x4
	// Bit mask of CORE_0_AREA_PIF_0_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW_Msk = 0x10
	// Bit CORE_0_AREA_PIF_0_RD_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_RD_RAW = 0x10
	// Position of CORE_0_AREA_PIF_0_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Pos = 0x5
	// Bit mask of CORE_0_AREA_PIF_0_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW_Msk = 0x20
	// Bit CORE_0_AREA_PIF_0_WR_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_0_WR_RAW = 0x20
	// Position of CORE_0_AREA_PIF_1_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Pos = 0x6
	// Bit mask of CORE_0_AREA_PIF_1_RD_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW_Msk = 0x40
	// Bit CORE_0_AREA_PIF_1_RD_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_RD_RAW = 0x40
	// Position of CORE_0_AREA_PIF_1_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Pos = 0x7
	// Bit mask of CORE_0_AREA_PIF_1_WR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW_Msk = 0x80
	// Bit CORE_0_AREA_PIF_1_WR_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_AREA_PIF_1_WR_RAW = 0x80
	// Position of CORE_0_SP_SPILL_MIN_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Pos = 0x8
	// Bit mask of CORE_0_SP_SPILL_MIN_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW_Msk = 0x100
	// Bit CORE_0_SP_SPILL_MIN_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MIN_RAW = 0x100
	// Position of CORE_0_SP_SPILL_MAX_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Pos = 0x9
	// Bit mask of CORE_0_SP_SPILL_MAX_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW_Msk = 0x200
	// Bit CORE_0_SP_SPILL_MAX_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_SP_SPILL_MAX_RAW = 0x200
	// Position of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xa
	// Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x400
	// Bit CORE_0_IRAM0_EXCEPTION_MONITOR_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW = 0x400
	// Position of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xb
	// Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x800
	// Bit CORE_0_DRAM0_EXCEPTION_MONITOR_RAW.
	ASSIST_DEBUG_CORE_0_INTR_RAW_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW = 0x800

	// CORE_0_INTR_RLS: core0 monitor interrupt enable register
	// Position of CORE_0_AREA_DRAM0_0_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_RD_RLS_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_0_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_RD_RLS_Msk = 0x1
	// Bit CORE_0_AREA_DRAM0_0_RD_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_RD_RLS = 0x1
	// Position of CORE_0_AREA_DRAM0_0_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_WR_RLS_Pos = 0x1
	// Bit mask of CORE_0_AREA_DRAM0_0_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_WR_RLS_Msk = 0x2
	// Bit CORE_0_AREA_DRAM0_0_WR_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_0_WR_RLS = 0x2
	// Position of CORE_0_AREA_DRAM0_1_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_RD_RLS_Pos = 0x2
	// Bit mask of CORE_0_AREA_DRAM0_1_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_RD_RLS_Msk = 0x4
	// Bit CORE_0_AREA_DRAM0_1_RD_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_RD_RLS = 0x4
	// Position of CORE_0_AREA_DRAM0_1_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_WR_RLS_Pos = 0x3
	// Bit mask of CORE_0_AREA_DRAM0_1_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_WR_RLS_Msk = 0x8
	// Bit CORE_0_AREA_DRAM0_1_WR_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_DRAM0_1_WR_RLS = 0x8
	// Position of CORE_0_AREA_PIF_0_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_0_RD_RLS_Pos = 0x4
	// Bit mask of CORE_0_AREA_PIF_0_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_0_RD_RLS_Msk = 0x10
	// Bit CORE_0_AREA_PIF_0_RD_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_0_RD_RLS = 0x10
	// Position of CORE_0_AREA_PIF_0_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_0_WR_RLS_Pos = 0x5
	// Bit mask of CORE_0_AREA_PIF_0_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_0_WR_RLS_Msk = 0x20
	// Bit CORE_0_AREA_PIF_0_WR_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_0_WR_RLS = 0x20
	// Position of CORE_0_AREA_PIF_1_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_1_RD_RLS_Pos = 0x6
	// Bit mask of CORE_0_AREA_PIF_1_RD_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_1_RD_RLS_Msk = 0x40
	// Bit CORE_0_AREA_PIF_1_RD_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_1_RD_RLS = 0x40
	// Position of CORE_0_AREA_PIF_1_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_1_WR_RLS_Pos = 0x7
	// Bit mask of CORE_0_AREA_PIF_1_WR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_1_WR_RLS_Msk = 0x80
	// Bit CORE_0_AREA_PIF_1_WR_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_AREA_PIF_1_WR_RLS = 0x80
	// Position of CORE_0_SP_SPILL_MIN_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_SP_SPILL_MIN_RLS_Pos = 0x8
	// Bit mask of CORE_0_SP_SPILL_MIN_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_SP_SPILL_MIN_RLS_Msk = 0x100
	// Bit CORE_0_SP_SPILL_MIN_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_SP_SPILL_MIN_RLS = 0x100
	// Position of CORE_0_SP_SPILL_MAX_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_SP_SPILL_MAX_RLS_Pos = 0x9
	// Bit mask of CORE_0_SP_SPILL_MAX_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_SP_SPILL_MAX_RLS_Msk = 0x200
	// Bit CORE_0_SP_SPILL_MAX_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_SP_SPILL_MAX_RLS = 0x200
	// Position of CORE_0_IRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_Pos = 0xa
	// Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_Msk = 0x400
	// Bit CORE_0_IRAM0_EXCEPTION_MONITOR_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS = 0x400
	// Position of CORE_0_DRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_Pos = 0xb
	// Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_Msk = 0x800
	// Bit CORE_0_DRAM0_EXCEPTION_MONITOR_RLS.
	ASSIST_DEBUG_CORE_0_INTR_RLS_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS = 0x800

	// CORE_0_INTR_CLR: core0 monitor interrupt clr register
	// Position of CORE_0_AREA_DRAM0_0_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_0_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR_Msk = 0x1
	// Bit CORE_0_AREA_DRAM0_0_RD_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_RD_CLR = 0x1
	// Position of CORE_0_AREA_DRAM0_0_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Pos = 0x1
	// Bit mask of CORE_0_AREA_DRAM0_0_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR_Msk = 0x2
	// Bit CORE_0_AREA_DRAM0_0_WR_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_0_WR_CLR = 0x2
	// Position of CORE_0_AREA_DRAM0_1_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Pos = 0x2
	// Bit mask of CORE_0_AREA_DRAM0_1_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR_Msk = 0x4
	// Bit CORE_0_AREA_DRAM0_1_RD_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_RD_CLR = 0x4
	// Position of CORE_0_AREA_DRAM0_1_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Pos = 0x3
	// Bit mask of CORE_0_AREA_DRAM0_1_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR_Msk = 0x8
	// Bit CORE_0_AREA_DRAM0_1_WR_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_DRAM0_1_WR_CLR = 0x8
	// Position of CORE_0_AREA_PIF_0_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Pos = 0x4
	// Bit mask of CORE_0_AREA_PIF_0_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR_Msk = 0x10
	// Bit CORE_0_AREA_PIF_0_RD_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_RD_CLR = 0x10
	// Position of CORE_0_AREA_PIF_0_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Pos = 0x5
	// Bit mask of CORE_0_AREA_PIF_0_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR_Msk = 0x20
	// Bit CORE_0_AREA_PIF_0_WR_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_0_WR_CLR = 0x20
	// Position of CORE_0_AREA_PIF_1_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Pos = 0x6
	// Bit mask of CORE_0_AREA_PIF_1_RD_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR_Msk = 0x40
	// Bit CORE_0_AREA_PIF_1_RD_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_RD_CLR = 0x40
	// Position of CORE_0_AREA_PIF_1_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Pos = 0x7
	// Bit mask of CORE_0_AREA_PIF_1_WR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR_Msk = 0x80
	// Bit CORE_0_AREA_PIF_1_WR_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_AREA_PIF_1_WR_CLR = 0x80
	// Position of CORE_0_SP_SPILL_MIN_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Pos = 0x8
	// Bit mask of CORE_0_SP_SPILL_MIN_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR_Msk = 0x100
	// Bit CORE_0_SP_SPILL_MIN_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MIN_CLR = 0x100
	// Position of CORE_0_SP_SPILL_MAX_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Pos = 0x9
	// Bit mask of CORE_0_SP_SPILL_MAX_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR_Msk = 0x200
	// Bit CORE_0_SP_SPILL_MAX_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_SP_SPILL_MAX_CLR = 0x200
	// Position of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xa
	// Bit mask of CORE_0_IRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x400
	// Bit CORE_0_IRAM0_EXCEPTION_MONITOR_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR = 0x400
	// Position of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xb
	// Bit mask of CORE_0_DRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x800
	// Bit CORE_0_DRAM0_EXCEPTION_MONITOR_CLR.
	ASSIST_DEBUG_CORE_0_INTR_CLR_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR = 0x800

	// CORE_0_AREA_DRAM0_0_MIN: core0 dram0 region0 addr configuration register
	// Position of CORE_0_AREA_DRAM0_0_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_0_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_CORE_0_AREA_DRAM0_0_MIN_Msk = 0xffffffff

	// CORE_0_AREA_DRAM0_0_MAX: core0 dram0 region0 addr configuration register
	// Position of CORE_0_AREA_DRAM0_0_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_0_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_CORE_0_AREA_DRAM0_0_MAX_Msk = 0xffffffff

	// CORE_0_AREA_DRAM0_1_MIN: core0 dram0 region1 addr configuration register
	// Position of CORE_0_AREA_DRAM0_1_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_1_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_CORE_0_AREA_DRAM0_1_MIN_Msk = 0xffffffff

	// CORE_0_AREA_DRAM0_1_MAX: core0 dram0 region1 addr configuration register
	// Position of CORE_0_AREA_DRAM0_1_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Pos = 0x0
	// Bit mask of CORE_0_AREA_DRAM0_1_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_CORE_0_AREA_DRAM0_1_MAX_Msk = 0xffffffff

	// CORE_0_AREA_PIF_0_MIN: core0 PIF region0 addr configuration register
	// Position of CORE_0_AREA_PIF_0_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Pos = 0x0
	// Bit mask of CORE_0_AREA_PIF_0_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_CORE_0_AREA_PIF_0_MIN_Msk = 0xffffffff

	// CORE_0_AREA_PIF_0_MAX: core0 PIF region0 addr configuration register
	// Position of CORE_0_AREA_PIF_0_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Pos = 0x0
	// Bit mask of CORE_0_AREA_PIF_0_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_CORE_0_AREA_PIF_0_MAX_Msk = 0xffffffff

	// CORE_0_AREA_PIF_1_MIN: core0 PIF region1 addr configuration register
	// Position of CORE_0_AREA_PIF_1_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Pos = 0x0
	// Bit mask of CORE_0_AREA_PIF_1_MIN field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_CORE_0_AREA_PIF_1_MIN_Msk = 0xffffffff

	// CORE_0_AREA_PIF_1_MAX: core0 PIF region1 addr configuration register
	// Position of CORE_0_AREA_PIF_1_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Pos = 0x0
	// Bit mask of CORE_0_AREA_PIF_1_MAX field.
	ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_CORE_0_AREA_PIF_1_MAX_Msk = 0xffffffff

	// CORE_0_AREA_PC: core0 area pc status register
	// Position of CORE_0_AREA_PC field.
	ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Pos = 0x0
	// Bit mask of CORE_0_AREA_PC field.
	ASSIST_DEBUG_CORE_0_AREA_PC_CORE_0_AREA_PC_Msk = 0xffffffff

	// CORE_0_AREA_SP: core0 area sp status register
	// Position of CORE_0_AREA_SP field.
	ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Pos = 0x0
	// Bit mask of CORE_0_AREA_SP field.
	ASSIST_DEBUG_CORE_0_AREA_SP_CORE_0_AREA_SP_Msk = 0xffffffff

	// CORE_0_SP_MIN: stack min value
	// Position of CORE_0_SP_MIN field.
	ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Pos = 0x0
	// Bit mask of CORE_0_SP_MIN field.
	ASSIST_DEBUG_CORE_0_SP_MIN_CORE_0_SP_MIN_Msk = 0xffffffff

	// CORE_0_SP_MAX: stack max value
	// Position of CORE_0_SP_MAX field.
	ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Pos = 0x0
	// Bit mask of CORE_0_SP_MAX field.
	ASSIST_DEBUG_CORE_0_SP_MAX_CORE_0_SP_MAX_Msk = 0xffffffff

	// CORE_0_SP_PC: stack monitor pc status register
	// Position of CORE_0_SP_PC field.
	ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Pos = 0x0
	// Bit mask of CORE_0_SP_PC field.
	ASSIST_DEBUG_CORE_0_SP_PC_CORE_0_SP_PC_Msk = 0xffffffff

	// CORE_0_RCD_EN: record enable configuration register
	// Position of CORE_0_RCD_RECORDEN field.
	ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Pos = 0x0
	// Bit mask of CORE_0_RCD_RECORDEN field.
	ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN_Msk = 0x1
	// Bit CORE_0_RCD_RECORDEN.
	ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_RECORDEN = 0x1
	// Position of CORE_0_RCD_PDEBUGEN field.
	ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Pos = 0x1
	// Bit mask of CORE_0_RCD_PDEBUGEN field.
	ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN_Msk = 0x2
	// Bit CORE_0_RCD_PDEBUGEN.
	ASSIST_DEBUG_CORE_0_RCD_EN_CORE_0_RCD_PDEBUGEN = 0x2

	// CORE_0_RCD_PDEBUGPC: record status regsiter
	// Position of CORE_0_RCD_PDEBUGPC field.
	ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Pos = 0x0
	// Bit mask of CORE_0_RCD_PDEBUGPC field.
	ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_CORE_0_RCD_PDEBUGPC_Msk = 0xffffffff

	// CORE_0_RCD_PDEBUGSP: record status regsiter
	// Position of CORE_0_RCD_PDEBUGSP field.
	ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Pos = 0x0
	// Bit mask of CORE_0_RCD_PDEBUGSP field.
	ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_CORE_0_RCD_PDEBUGSP_Msk = 0xffffffff

	// CORE_0_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0
	// Position of CORE_0_IRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Pos = 0x0
	// Bit mask of CORE_0_IRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_ADDR_0_Msk = 0xffffff
	// Position of CORE_0_IRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Pos = 0x18
	// Bit mask of CORE_0_IRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0_Msk = 0x1000000
	// Bit CORE_0_IRAM0_RECORDING_WR_0.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_WR_0 = 0x1000000
	// Position of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Pos = 0x19
	// Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_0 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0_Msk = 0x2000000
	// Bit CORE_0_IRAM0_RECORDING_LOADSTORE_0.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_CORE_0_IRAM0_RECORDING_LOADSTORE_0 = 0x2000000

	// CORE_0_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1
	// Position of CORE_0_IRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Pos = 0x0
	// Bit mask of CORE_0_IRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_ADDR_1_Msk = 0xffffff
	// Position of CORE_0_IRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Pos = 0x18
	// Bit mask of CORE_0_IRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1_Msk = 0x1000000
	// Bit CORE_0_IRAM0_RECORDING_WR_1.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_WR_1 = 0x1000000
	// Position of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Pos = 0x19
	// Bit mask of CORE_0_IRAM0_RECORDING_LOADSTORE_1 field.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1_Msk = 0x2000000
	// Bit CORE_0_IRAM0_RECORDING_LOADSTORE_1.
	ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_CORE_0_IRAM0_RECORDING_LOADSTORE_1 = 0x2000000

	// CORE_0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2
	// Position of CORE_0_DRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Pos = 0x0
	// Bit mask of CORE_0_DRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0_Msk = 0x1
	// Bit CORE_0_DRAM0_RECORDING_WR_0.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_WR_0 = 0x1
	// Position of CORE_0_DRAM0_RECORDING_BYTEEN_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Pos = 0x1
	// Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_CORE_0_DRAM0_RECORDING_BYTEEN_0_Msk = 0x1fffe

	// CORE_0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3
	// Position of CORE_0_DRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_ADDR_0_Pos = 0x0
	// Bit mask of CORE_0_DRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_CORE_0_DRAM0_RECORDING_ADDR_0_Msk = 0xffffff

	// CORE_0_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4
	// Position of CORE_0_DRAM0_RECORDING_PC_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_PC_0_Pos = 0x0
	// Bit mask of CORE_0_DRAM0_RECORDING_PC_0 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_CORE_0_DRAM0_RECORDING_PC_0_Msk = 0xffffffff

	// CORE_0_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5
	// Position of CORE_0_DRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1_Pos = 0x0
	// Bit mask of CORE_0_DRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1_Msk = 0x1
	// Bit CORE_0_DRAM0_RECORDING_WR_1.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_WR_1 = 0x1
	// Position of CORE_0_DRAM0_RECORDING_BYTEEN_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_BYTEEN_1_Pos = 0x1
	// Bit mask of CORE_0_DRAM0_RECORDING_BYTEEN_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_CORE_0_DRAM0_RECORDING_BYTEEN_1_Msk = 0x1fffe

	// CORE_0_DRAM0_EXCEPTION_MONITOR_4: exception monitor status register6
	// Position of CORE_0_DRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_ADDR_1_Pos = 0x0
	// Bit mask of CORE_0_DRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_CORE_0_DRAM0_RECORDING_ADDR_1_Msk = 0xffffff

	// CORE_0_DRAM0_EXCEPTION_MONITOR_5: exception monitor status register7
	// Position of CORE_0_DRAM0_RECORDING_PC_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_CORE_0_DRAM0_RECORDING_PC_1_Pos = 0x0
	// Bit mask of CORE_0_DRAM0_RECORDING_PC_1 field.
	ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_CORE_0_DRAM0_RECORDING_PC_1_Msk = 0xffffffff

	// CORE_0_LASTPC_BEFORE_EXCEPTION: cpu status register
	// Position of CORE_0_LASTPC_BEFORE_EXC field.
	ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Pos = 0x0
	// Bit mask of CORE_0_LASTPC_BEFORE_EXC field.
	ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_CORE_0_LASTPC_BEFORE_EXC_Msk = 0xffffffff

	// CORE_0_DEBUG_MODE: cpu status register
	// Position of CORE_0_DEBUG_MODE field.
	ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Pos = 0x0
	// Bit mask of CORE_0_DEBUG_MODE field.
	ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODE_Msk = 0x1
	// Bit CORE_0_DEBUG_MODE.
	ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODE = 0x1
	// Position of CORE_0_DEBUG_MODULE_ACTIVE field.
	ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Pos = 0x1
	// Bit mask of CORE_0_DEBUG_MODULE_ACTIVE field.
	ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE_Msk = 0x2
	// Bit CORE_0_DEBUG_MODULE_ACTIVE.
	ASSIST_DEBUG_CORE_0_DEBUG_MODE_CORE_0_DEBUG_MODULE_ACTIVE = 0x2

	// CORE_1_INTR_ENA: core1 monitor enable configuration register
	// Position of CORE_1_AREA_DRAM0_0_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_0_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA_Msk = 0x1
	// Bit CORE_1_AREA_DRAM0_0_RD_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_RD_ENA = 0x1
	// Position of CORE_1_AREA_DRAM0_0_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA_Pos = 0x1
	// Bit mask of CORE_1_AREA_DRAM0_0_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA_Msk = 0x2
	// Bit CORE_1_AREA_DRAM0_0_WR_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_0_WR_ENA = 0x2
	// Position of CORE_1_AREA_DRAM0_1_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA_Pos = 0x2
	// Bit mask of CORE_1_AREA_DRAM0_1_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA_Msk = 0x4
	// Bit CORE_1_AREA_DRAM0_1_RD_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_RD_ENA = 0x4
	// Position of CORE_1_AREA_DRAM0_1_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA_Pos = 0x3
	// Bit mask of CORE_1_AREA_DRAM0_1_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA_Msk = 0x8
	// Bit CORE_1_AREA_DRAM0_1_WR_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_DRAM0_1_WR_ENA = 0x8
	// Position of CORE_1_AREA_PIF_0_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_ENA_Pos = 0x4
	// Bit mask of CORE_1_AREA_PIF_0_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_ENA_Msk = 0x10
	// Bit CORE_1_AREA_PIF_0_RD_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_RD_ENA = 0x10
	// Position of CORE_1_AREA_PIF_0_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_ENA_Pos = 0x5
	// Bit mask of CORE_1_AREA_PIF_0_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_ENA_Msk = 0x20
	// Bit CORE_1_AREA_PIF_0_WR_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_0_WR_ENA = 0x20
	// Position of CORE_1_AREA_PIF_1_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_ENA_Pos = 0x6
	// Bit mask of CORE_1_AREA_PIF_1_RD_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_ENA_Msk = 0x40
	// Bit CORE_1_AREA_PIF_1_RD_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_RD_ENA = 0x40
	// Position of CORE_1_AREA_PIF_1_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_ENA_Pos = 0x7
	// Bit mask of CORE_1_AREA_PIF_1_WR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_ENA_Msk = 0x80
	// Bit CORE_1_AREA_PIF_1_WR_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_AREA_PIF_1_WR_ENA = 0x80
	// Position of CORE_1_SP_SPILL_MIN_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_ENA_Pos = 0x8
	// Bit mask of CORE_1_SP_SPILL_MIN_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_ENA_Msk = 0x100
	// Bit CORE_1_SP_SPILL_MIN_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MIN_ENA = 0x100
	// Position of CORE_1_SP_SPILL_MAX_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_ENA_Pos = 0x9
	// Bit mask of CORE_1_SP_SPILL_MAX_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_ENA_Msk = 0x200
	// Bit CORE_1_SP_SPILL_MAX_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_SP_SPILL_MAX_ENA = 0x200
	// Position of CORE_1_IRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xa
	// Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x400
	// Bit CORE_1_IRAM0_EXCEPTION_MONITOR_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA = 0x400
	// Position of CORE_1_DRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_Pos = 0xb
	// Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_ENA field.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_Msk = 0x800
	// Bit CORE_1_DRAM0_EXCEPTION_MONITOR_ENA.
	ASSIST_DEBUG_CORE_1_INTR_ENA_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA = 0x800

	// CORE_1_INTR_RAW: core1 monitor interrupt status register
	// Position of CORE_1_AREA_DRAM0_0_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_0_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW_Msk = 0x1
	// Bit CORE_1_AREA_DRAM0_0_RD_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_RD_RAW = 0x1
	// Position of CORE_1_AREA_DRAM0_0_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW_Pos = 0x1
	// Bit mask of CORE_1_AREA_DRAM0_0_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW_Msk = 0x2
	// Bit CORE_1_AREA_DRAM0_0_WR_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_0_WR_RAW = 0x2
	// Position of CORE_1_AREA_DRAM0_1_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW_Pos = 0x2
	// Bit mask of CORE_1_AREA_DRAM0_1_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW_Msk = 0x4
	// Bit CORE_1_AREA_DRAM0_1_RD_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_RD_RAW = 0x4
	// Position of CORE_1_AREA_DRAM0_1_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW_Pos = 0x3
	// Bit mask of CORE_1_AREA_DRAM0_1_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW_Msk = 0x8
	// Bit CORE_1_AREA_DRAM0_1_WR_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_DRAM0_1_WR_RAW = 0x8
	// Position of CORE_1_AREA_PIF_0_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW_Pos = 0x4
	// Bit mask of CORE_1_AREA_PIF_0_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW_Msk = 0x10
	// Bit CORE_1_AREA_PIF_0_RD_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_RD_RAW = 0x10
	// Position of CORE_1_AREA_PIF_0_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW_Pos = 0x5
	// Bit mask of CORE_1_AREA_PIF_0_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW_Msk = 0x20
	// Bit CORE_1_AREA_PIF_0_WR_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_0_WR_RAW = 0x20
	// Position of CORE_1_AREA_PIF_1_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW_Pos = 0x6
	// Bit mask of CORE_1_AREA_PIF_1_RD_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW_Msk = 0x40
	// Bit CORE_1_AREA_PIF_1_RD_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_RD_RAW = 0x40
	// Position of CORE_1_AREA_PIF_1_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW_Pos = 0x7
	// Bit mask of CORE_1_AREA_PIF_1_WR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW_Msk = 0x80
	// Bit CORE_1_AREA_PIF_1_WR_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_AREA_PIF_1_WR_RAW = 0x80
	// Position of CORE_1_SP_SPILL_MIN_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW_Pos = 0x8
	// Bit mask of CORE_1_SP_SPILL_MIN_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW_Msk = 0x100
	// Bit CORE_1_SP_SPILL_MIN_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MIN_RAW = 0x100
	// Position of CORE_1_SP_SPILL_MAX_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW_Pos = 0x9
	// Bit mask of CORE_1_SP_SPILL_MAX_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW_Msk = 0x200
	// Bit CORE_1_SP_SPILL_MAX_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_SP_SPILL_MAX_RAW = 0x200
	// Position of CORE_1_IRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xa
	// Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x400
	// Bit CORE_1_IRAM0_EXCEPTION_MONITOR_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW = 0x400
	// Position of CORE_1_DRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_Pos = 0xb
	// Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_RAW field.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_Msk = 0x800
	// Bit CORE_1_DRAM0_EXCEPTION_MONITOR_RAW.
	ASSIST_DEBUG_CORE_1_INTR_RAW_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW = 0x800

	// CORE_1_INTR_RLS: core1 monitor interrupt enable register
	// Position of CORE_1_AREA_DRAM0_0_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_RD_RLS_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_0_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_RD_RLS_Msk = 0x1
	// Bit CORE_1_AREA_DRAM0_0_RD_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_RD_RLS = 0x1
	// Position of CORE_1_AREA_DRAM0_0_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_WR_RLS_Pos = 0x1
	// Bit mask of CORE_1_AREA_DRAM0_0_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_WR_RLS_Msk = 0x2
	// Bit CORE_1_AREA_DRAM0_0_WR_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_0_WR_RLS = 0x2
	// Position of CORE_1_AREA_DRAM0_1_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_RD_RLS_Pos = 0x2
	// Bit mask of CORE_1_AREA_DRAM0_1_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_RD_RLS_Msk = 0x4
	// Bit CORE_1_AREA_DRAM0_1_RD_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_RD_RLS = 0x4
	// Position of CORE_1_AREA_DRAM0_1_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_WR_RLS_Pos = 0x3
	// Bit mask of CORE_1_AREA_DRAM0_1_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_WR_RLS_Msk = 0x8
	// Bit CORE_1_AREA_DRAM0_1_WR_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_DRAM0_1_WR_RLS = 0x8
	// Position of CORE_1_AREA_PIF_0_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_0_RD_RLS_Pos = 0x4
	// Bit mask of CORE_1_AREA_PIF_0_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_0_RD_RLS_Msk = 0x10
	// Bit CORE_1_AREA_PIF_0_RD_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_0_RD_RLS = 0x10
	// Position of CORE_1_AREA_PIF_0_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_0_WR_RLS_Pos = 0x5
	// Bit mask of CORE_1_AREA_PIF_0_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_0_WR_RLS_Msk = 0x20
	// Bit CORE_1_AREA_PIF_0_WR_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_0_WR_RLS = 0x20
	// Position of CORE_1_AREA_PIF_1_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_1_RD_RLS_Pos = 0x6
	// Bit mask of CORE_1_AREA_PIF_1_RD_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_1_RD_RLS_Msk = 0x40
	// Bit CORE_1_AREA_PIF_1_RD_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_1_RD_RLS = 0x40
	// Position of CORE_1_AREA_PIF_1_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_1_WR_RLS_Pos = 0x7
	// Bit mask of CORE_1_AREA_PIF_1_WR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_1_WR_RLS_Msk = 0x80
	// Bit CORE_1_AREA_PIF_1_WR_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_AREA_PIF_1_WR_RLS = 0x80
	// Position of CORE_1_SP_SPILL_MIN_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_SP_SPILL_MIN_RLS_Pos = 0x8
	// Bit mask of CORE_1_SP_SPILL_MIN_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_SP_SPILL_MIN_RLS_Msk = 0x100
	// Bit CORE_1_SP_SPILL_MIN_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_SP_SPILL_MIN_RLS = 0x100
	// Position of CORE_1_SP_SPILL_MAX_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_SP_SPILL_MAX_RLS_Pos = 0x9
	// Bit mask of CORE_1_SP_SPILL_MAX_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_SP_SPILL_MAX_RLS_Msk = 0x200
	// Bit CORE_1_SP_SPILL_MAX_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_SP_SPILL_MAX_RLS = 0x200
	// Position of CORE_1_IRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_Pos = 0xa
	// Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_Msk = 0x400
	// Bit CORE_1_IRAM0_EXCEPTION_MONITOR_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS = 0x400
	// Position of CORE_1_DRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_Pos = 0xb
	// Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_RLS field.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_Msk = 0x800
	// Bit CORE_1_DRAM0_EXCEPTION_MONITOR_RLS.
	ASSIST_DEBUG_CORE_1_INTR_RLS_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS = 0x800

	// CORE_1_INTR_CLR: core1 monitor interrupt clr register
	// Position of CORE_1_AREA_DRAM0_0_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_0_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR_Msk = 0x1
	// Bit CORE_1_AREA_DRAM0_0_RD_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_RD_CLR = 0x1
	// Position of CORE_1_AREA_DRAM0_0_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR_Pos = 0x1
	// Bit mask of CORE_1_AREA_DRAM0_0_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR_Msk = 0x2
	// Bit CORE_1_AREA_DRAM0_0_WR_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_0_WR_CLR = 0x2
	// Position of CORE_1_AREA_DRAM0_1_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR_Pos = 0x2
	// Bit mask of CORE_1_AREA_DRAM0_1_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR_Msk = 0x4
	// Bit CORE_1_AREA_DRAM0_1_RD_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_RD_CLR = 0x4
	// Position of CORE_1_AREA_DRAM0_1_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR_Pos = 0x3
	// Bit mask of CORE_1_AREA_DRAM0_1_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR_Msk = 0x8
	// Bit CORE_1_AREA_DRAM0_1_WR_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_DRAM0_1_WR_CLR = 0x8
	// Position of CORE_1_AREA_PIF_0_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR_Pos = 0x4
	// Bit mask of CORE_1_AREA_PIF_0_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR_Msk = 0x10
	// Bit CORE_1_AREA_PIF_0_RD_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_RD_CLR = 0x10
	// Position of CORE_1_AREA_PIF_0_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR_Pos = 0x5
	// Bit mask of CORE_1_AREA_PIF_0_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR_Msk = 0x20
	// Bit CORE_1_AREA_PIF_0_WR_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_0_WR_CLR = 0x20
	// Position of CORE_1_AREA_PIF_1_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR_Pos = 0x6
	// Bit mask of CORE_1_AREA_PIF_1_RD_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR_Msk = 0x40
	// Bit CORE_1_AREA_PIF_1_RD_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_RD_CLR = 0x40
	// Position of CORE_1_AREA_PIF_1_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR_Pos = 0x7
	// Bit mask of CORE_1_AREA_PIF_1_WR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR_Msk = 0x80
	// Bit CORE_1_AREA_PIF_1_WR_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_AREA_PIF_1_WR_CLR = 0x80
	// Position of CORE_1_SP_SPILL_MIN_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR_Pos = 0x8
	// Bit mask of CORE_1_SP_SPILL_MIN_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR_Msk = 0x100
	// Bit CORE_1_SP_SPILL_MIN_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MIN_CLR = 0x100
	// Position of CORE_1_SP_SPILL_MAX_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR_Pos = 0x9
	// Bit mask of CORE_1_SP_SPILL_MAX_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR_Msk = 0x200
	// Bit CORE_1_SP_SPILL_MAX_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_SP_SPILL_MAX_CLR = 0x200
	// Position of CORE_1_IRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xa
	// Bit mask of CORE_1_IRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x400
	// Bit CORE_1_IRAM0_EXCEPTION_MONITOR_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR = 0x400
	// Position of CORE_1_DRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_Pos = 0xb
	// Bit mask of CORE_1_DRAM0_EXCEPTION_MONITOR_CLR field.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_Msk = 0x800
	// Bit CORE_1_DRAM0_EXCEPTION_MONITOR_CLR.
	ASSIST_DEBUG_CORE_1_INTR_CLR_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR = 0x800

	// CORE_1_AREA_DRAM0_0_MIN: core1 dram0 region0 addr configuration register
	// Position of CORE_1_AREA_DRAM0_0_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_CORE_1_AREA_DRAM0_0_MIN_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_0_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_CORE_1_AREA_DRAM0_0_MIN_Msk = 0xffffffff

	// CORE_1_AREA_DRAM0_0_MAX: core1 dram0 region0 addr configuration register
	// Position of CORE_1_AREA_DRAM0_0_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_CORE_1_AREA_DRAM0_0_MAX_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_0_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_CORE_1_AREA_DRAM0_0_MAX_Msk = 0xffffffff

	// CORE_1_AREA_DRAM0_1_MIN: core1 dram0 region1 addr configuration register
	// Position of CORE_1_AREA_DRAM0_1_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_CORE_1_AREA_DRAM0_1_MIN_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_1_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_CORE_1_AREA_DRAM0_1_MIN_Msk = 0xffffffff

	// CORE_1_AREA_DRAM0_1_MAX: core1 dram0 region1 addr configuration register
	// Position of CORE_1_AREA_DRAM0_1_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_CORE_1_AREA_DRAM0_1_MAX_Pos = 0x0
	// Bit mask of CORE_1_AREA_DRAM0_1_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_CORE_1_AREA_DRAM0_1_MAX_Msk = 0xffffffff

	// CORE_1_AREA_PIF_0_MIN: core1 PIF region0 addr configuration register
	// Position of CORE_1_AREA_PIF_0_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_CORE_1_AREA_PIF_0_MIN_Pos = 0x0
	// Bit mask of CORE_1_AREA_PIF_0_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_CORE_1_AREA_PIF_0_MIN_Msk = 0xffffffff

	// CORE_1_AREA_PIF_0_MAX: core1 PIF region0 addr configuration register
	// Position of CORE_1_AREA_PIF_0_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_CORE_1_AREA_PIF_0_MAX_Pos = 0x0
	// Bit mask of CORE_1_AREA_PIF_0_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_CORE_1_AREA_PIF_0_MAX_Msk = 0xffffffff

	// CORE_1_AREA_PIF_1_MIN: core1 PIF region1 addr configuration register
	// Position of CORE_1_AREA_PIF_1_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_CORE_1_AREA_PIF_1_MIN_Pos = 0x0
	// Bit mask of CORE_1_AREA_PIF_1_MIN field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_CORE_1_AREA_PIF_1_MIN_Msk = 0xffffffff

	// CORE_1_AREA_PIF_1_MAX: core1 PIF region1 addr configuration register
	// Position of CORE_1_AREA_PIF_1_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_CORE_1_AREA_PIF_1_MAX_Pos = 0x0
	// Bit mask of CORE_1_AREA_PIF_1_MAX field.
	ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_CORE_1_AREA_PIF_1_MAX_Msk = 0xffffffff

	// CORE_1_AREA_PC: core1 area pc status register
	// Position of CORE_1_AREA_PC field.
	ASSIST_DEBUG_CORE_1_AREA_PC_CORE_1_AREA_PC_Pos = 0x0
	// Bit mask of CORE_1_AREA_PC field.
	ASSIST_DEBUG_CORE_1_AREA_PC_CORE_1_AREA_PC_Msk = 0xffffffff

	// CORE_1_AREA_SP: core1 area sp status register
	// Position of CORE_1_AREA_SP field.
	ASSIST_DEBUG_CORE_1_AREA_SP_CORE_1_AREA_SP_Pos = 0x0
	// Bit mask of CORE_1_AREA_SP field.
	ASSIST_DEBUG_CORE_1_AREA_SP_CORE_1_AREA_SP_Msk = 0xffffffff

	// CORE_1_SP_MIN: stack min value
	// Position of CORE_1_SP_MIN field.
	ASSIST_DEBUG_CORE_1_SP_MIN_CORE_1_SP_MIN_Pos = 0x0
	// Bit mask of CORE_1_SP_MIN field.
	ASSIST_DEBUG_CORE_1_SP_MIN_CORE_1_SP_MIN_Msk = 0xffffffff

	// CORE_1_SP_MAX: stack max value
	// Position of CORE_1_SP_MAX field.
	ASSIST_DEBUG_CORE_1_SP_MAX_CORE_1_SP_MAX_Pos = 0x0
	// Bit mask of CORE_1_SP_MAX field.
	ASSIST_DEBUG_CORE_1_SP_MAX_CORE_1_SP_MAX_Msk = 0xffffffff

	// CORE_1_SP_PC: stack monitor pc status register
	// Position of CORE_1_SP_PC field.
	ASSIST_DEBUG_CORE_1_SP_PC_CORE_1_SP_PC_Pos = 0x0
	// Bit mask of CORE_1_SP_PC field.
	ASSIST_DEBUG_CORE_1_SP_PC_CORE_1_SP_PC_Msk = 0xffffffff

	// CORE_1_RCD_EN: record enable configuration register
	// Position of CORE_1_RCD_RECORDEN field.
	ASSIST_DEBUG_CORE_1_RCD_EN_CORE_1_RCD_RECORDEN_Pos = 0x0
	// Bit mask of CORE_1_RCD_RECORDEN field.
	ASSIST_DEBUG_CORE_1_RCD_EN_CORE_1_RCD_RECORDEN_Msk = 0x1
	// Bit CORE_1_RCD_RECORDEN.
	ASSIST_DEBUG_CORE_1_RCD_EN_CORE_1_RCD_RECORDEN = 0x1
	// Position of CORE_1_RCD_PDEBUGEN field.
	ASSIST_DEBUG_CORE_1_RCD_EN_CORE_1_RCD_PDEBUGEN_Pos = 0x1
	// Bit mask of CORE_1_RCD_PDEBUGEN field.
	ASSIST_DEBUG_CORE_1_RCD_EN_CORE_1_RCD_PDEBUGEN_Msk = 0x2
	// Bit CORE_1_RCD_PDEBUGEN.
	ASSIST_DEBUG_CORE_1_RCD_EN_CORE_1_RCD_PDEBUGEN = 0x2

	// CORE_1_RCD_PDEBUGPC: record status regsiter
	// Position of CORE_1_RCD_PDEBUGPC field.
	ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_CORE_1_RCD_PDEBUGPC_Pos = 0x0
	// Bit mask of CORE_1_RCD_PDEBUGPC field.
	ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_CORE_1_RCD_PDEBUGPC_Msk = 0xffffffff

	// CORE_1_RCD_PDEBUGSP: record status regsiter
	// Position of CORE_1_RCD_PDEBUGSP field.
	ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_CORE_1_RCD_PDEBUGSP_Pos = 0x0
	// Bit mask of CORE_1_RCD_PDEBUGSP field.
	ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_CORE_1_RCD_PDEBUGSP_Msk = 0xffffffff

	// CORE_1_IRAM0_EXCEPTION_MONITOR_0: exception monitor status register0
	// Position of CORE_1_IRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0_Pos = 0x0
	// Bit mask of CORE_1_IRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_ADDR_0_Msk = 0xffffff
	// Position of CORE_1_IRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0_Pos = 0x18
	// Bit mask of CORE_1_IRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0_Msk = 0x1000000
	// Bit CORE_1_IRAM0_RECORDING_WR_0.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_WR_0 = 0x1000000
	// Position of CORE_1_IRAM0_RECORDING_LOADSTORE_0 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0_Pos = 0x19
	// Bit mask of CORE_1_IRAM0_RECORDING_LOADSTORE_0 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0_Msk = 0x2000000
	// Bit CORE_1_IRAM0_RECORDING_LOADSTORE_0.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_CORE_1_IRAM0_RECORDING_LOADSTORE_0 = 0x2000000

	// CORE_1_IRAM0_EXCEPTION_MONITOR_1: exception monitor status register1
	// Position of CORE_1_IRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1_Pos = 0x0
	// Bit mask of CORE_1_IRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_ADDR_1_Msk = 0xffffff
	// Position of CORE_1_IRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1_Pos = 0x18
	// Bit mask of CORE_1_IRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1_Msk = 0x1000000
	// Bit CORE_1_IRAM0_RECORDING_WR_1.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_WR_1 = 0x1000000
	// Position of CORE_1_IRAM0_RECORDING_LOADSTORE_1 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1_Pos = 0x19
	// Bit mask of CORE_1_IRAM0_RECORDING_LOADSTORE_1 field.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1_Msk = 0x2000000
	// Bit CORE_1_IRAM0_RECORDING_LOADSTORE_1.
	ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_CORE_1_IRAM0_RECORDING_LOADSTORE_1 = 0x2000000

	// CORE_1_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register2
	// Position of CORE_1_DRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0_Pos = 0x0
	// Bit mask of CORE_1_DRAM0_RECORDING_WR_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0_Msk = 0x1
	// Bit CORE_1_DRAM0_RECORDING_WR_0.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_WR_0 = 0x1
	// Position of CORE_1_DRAM0_RECORDING_BYTEEN_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_BYTEEN_0_Pos = 0x1
	// Bit mask of CORE_1_DRAM0_RECORDING_BYTEEN_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_CORE_1_DRAM0_RECORDING_BYTEEN_0_Msk = 0x1fffe

	// CORE_1_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register3
	// Position of CORE_1_DRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_ADDR_0_Pos = 0x0
	// Bit mask of CORE_1_DRAM0_RECORDING_ADDR_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_CORE_1_DRAM0_RECORDING_ADDR_0_Msk = 0xffffff

	// CORE_1_DRAM0_EXCEPTION_MONITOR_2: exception monitor status register4
	// Position of CORE_1_DRAM0_RECORDING_PC_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_CORE_1_DRAM0_RECORDING_PC_0_Pos = 0x0
	// Bit mask of CORE_1_DRAM0_RECORDING_PC_0 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_CORE_1_DRAM0_RECORDING_PC_0_Msk = 0xffffffff

	// CORE_1_DRAM0_EXCEPTION_MONITOR_3: exception monitor status register5
	// Position of CORE_1_DRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1_Pos = 0x0
	// Bit mask of CORE_1_DRAM0_RECORDING_WR_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1_Msk = 0x1
	// Bit CORE_1_DRAM0_RECORDING_WR_1.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_WR_1 = 0x1
	// Position of CORE_1_DRAM0_RECORDING_BYTEEN_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_BYTEEN_1_Pos = 0x1
	// Bit mask of CORE_1_DRAM0_RECORDING_BYTEEN_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_CORE_1_DRAM0_RECORDING_BYTEEN_1_Msk = 0x1fffe

	// CORE_1_DRAM0_EXCEPTION_MONITOR_4: exception monitor status register6
	// Position of CORE_1_DRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_ADDR_1_Pos = 0x0
	// Bit mask of CORE_1_DRAM0_RECORDING_ADDR_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_CORE_1_DRAM0_RECORDING_ADDR_1_Msk = 0xffffff

	// CORE_1_DRAM0_EXCEPTION_MONITOR_5: exception monitor status register7
	// Position of CORE_1_DRAM0_RECORDING_PC_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_CORE_1_DRAM0_RECORDING_PC_1_Pos = 0x0
	// Bit mask of CORE_1_DRAM0_RECORDING_PC_1 field.
	ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_CORE_1_DRAM0_RECORDING_PC_1_Msk = 0xffffffff

	// CORE_1_LASTPC_BEFORE_EXCEPTION: cpu status register
	// Position of CORE_1_LASTPC_BEFORE_EXC field.
	ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_CORE_1_LASTPC_BEFORE_EXC_Pos = 0x0
	// Bit mask of CORE_1_LASTPC_BEFORE_EXC field.
	ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_CORE_1_LASTPC_BEFORE_EXC_Msk = 0xffffffff

	// CORE_1_DEBUG_MODE: cpu status register
	// Position of CORE_1_DEBUG_MODE field.
	ASSIST_DEBUG_CORE_1_DEBUG_MODE_CORE_1_DEBUG_MODE_Pos = 0x0
	// Bit mask of CORE_1_DEBUG_MODE field.
	ASSIST_DEBUG_CORE_1_DEBUG_MODE_CORE_1_DEBUG_MODE_Msk = 0x1
	// Bit CORE_1_DEBUG_MODE.
	ASSIST_DEBUG_CORE_1_DEBUG_MODE_CORE_1_DEBUG_MODE = 0x1
	// Position of CORE_1_DEBUG_MODULE_ACTIVE field.
	ASSIST_DEBUG_CORE_1_DEBUG_MODE_CORE_1_DEBUG_MODULE_ACTIVE_Pos = 0x1
	// Bit mask of CORE_1_DEBUG_MODULE_ACTIVE field.
	ASSIST_DEBUG_CORE_1_DEBUG_MODE_CORE_1_DEBUG_MODULE_ACTIVE_Msk = 0x2
	// Bit CORE_1_DEBUG_MODULE_ACTIVE.
	ASSIST_DEBUG_CORE_1_DEBUG_MODE_CORE_1_DEBUG_MODULE_ACTIVE = 0x2

	// CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: exception monitor status register6
	// Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field.
	ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Pos = 0x0
	// Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 field.
	ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_Msk = 0xfffff

	// CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: exception monitor status register7
	// Position of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field.
	ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Pos = 0x0
	// Bit mask of CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 field.
	ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_Msk = 0xfffff

	// CLOCK_GATE: clock register
	// Position of CLK_EN field.
	ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	ASSIST_DEBUG_CLOCK_GATE_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	ASSIST_DEBUG_CLOCK_GATE_CLK_EN = 0x1

	// DATE: version register
	// Position of ASSIST_DEBUG_DATE field.
	ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Pos = 0x0
	// Bit mask of ASSIST_DEBUG_DATE field.
	ASSIST_DEBUG_DATE_ASSIST_DEBUG_DATE_Msk = 0xfffffff
)

// Constants for AXI_DMA: AXI_DMA Peripheral
const (
	// IN_INT_RAW_CH0: Raw status interrupt of channel 0
	// Position of IN_DONE_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_IN_DONE_CH_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_IN_SUC_EOF_CH_INT_RAW = 0x2
	// Position of IN_ERR_EOF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_IN_ERR_EOF_CH_INT_RAW = 0x4
	// Position of IN_DSCR_ERR_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_IN_DSCR_ERR_CH_INT_RAW = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_IN_DSCR_EMPTY_CH_INT_RAW = 0x10
	// Position of INFIFO_L1_OVF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L1_OVF_CH_INT_RAW_Pos = 0x5
	// Bit mask of INFIFO_L1_OVF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L1_OVF_CH_INT_RAW_Msk = 0x20
	// Bit INFIFO_L1_OVF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L1_OVF_CH_INT_RAW = 0x20
	// Position of INFIFO_L1_UDF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L1_UDF_CH_INT_RAW_Pos = 0x6
	// Bit mask of INFIFO_L1_UDF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L1_UDF_CH_INT_RAW_Msk = 0x40
	// Bit INFIFO_L1_UDF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L1_UDF_CH_INT_RAW = 0x40
	// Position of INFIFO_L2_OVF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L2_OVF_CH_INT_RAW_Pos = 0x7
	// Bit mask of INFIFO_L2_OVF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L2_OVF_CH_INT_RAW_Msk = 0x80
	// Bit INFIFO_L2_OVF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L2_OVF_CH_INT_RAW = 0x80
	// Position of INFIFO_L2_UDF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L2_UDF_CH_INT_RAW_Pos = 0x8
	// Bit mask of INFIFO_L2_UDF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L2_UDF_CH_INT_RAW_Msk = 0x100
	// Bit INFIFO_L2_UDF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L2_UDF_CH_INT_RAW = 0x100
	// Position of INFIFO_L3_OVF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L3_OVF_CH_INT_RAW_Pos = 0x9
	// Bit mask of INFIFO_L3_OVF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L3_OVF_CH_INT_RAW_Msk = 0x200
	// Bit INFIFO_L3_OVF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L3_OVF_CH_INT_RAW = 0x200
	// Position of INFIFO_L3_UDF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L3_UDF_CH_INT_RAW_Pos = 0xa
	// Bit mask of INFIFO_L3_UDF_CH_INT_RAW field.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L3_UDF_CH_INT_RAW_Msk = 0x400
	// Bit INFIFO_L3_UDF_CH_INT_RAW.
	AXI_DMA_IN_INT_RAW_CH_INFIFO_L3_UDF_CH_INT_RAW = 0x400

	// IN_INT_ST_CH0: Masked interrupt of channel 0
	// Position of IN_DONE_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_IN_DONE_CH_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_IN_SUC_EOF_CH_INT_ST = 0x2
	// Position of IN_ERR_EOF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_IN_ERR_EOF_CH_INT_ST = 0x4
	// Position of IN_DSCR_ERR_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_IN_DSCR_ERR_CH_INT_ST = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_IN_DSCR_EMPTY_CH_INT_ST = 0x10
	// Position of INFIFO_OVF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST_Pos = 0x5
	// Bit mask of INFIFO_OVF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST_Msk = 0x20
	// Bit INFIFO_OVF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_INFIFO_OVF_CH_INT_ST = 0x20
	// Position of INFIFO_UDF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST_Pos = 0x6
	// Bit mask of INFIFO_UDF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST_Msk = 0x40
	// Bit INFIFO_UDF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_INFIFO_UDF_CH_INT_ST = 0x40
	// Position of INFIFO_L1_OVF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L1_OVF_CH_INT_ST_Pos = 0x7
	// Bit mask of INFIFO_L1_OVF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L1_OVF_CH_INT_ST_Msk = 0x80
	// Bit INFIFO_L1_OVF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L1_OVF_CH_INT_ST = 0x80
	// Position of INFIFO_L1_UDF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L1_UDF_CH_INT_ST_Pos = 0x8
	// Bit mask of INFIFO_L1_UDF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L1_UDF_CH_INT_ST_Msk = 0x100
	// Bit INFIFO_L1_UDF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L1_UDF_CH_INT_ST = 0x100
	// Position of INFIFO_L3_OVF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L3_OVF_CH_INT_ST_Pos = 0x9
	// Bit mask of INFIFO_L3_OVF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L3_OVF_CH_INT_ST_Msk = 0x200
	// Bit INFIFO_L3_OVF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L3_OVF_CH_INT_ST = 0x200
	// Position of INFIFO_L3_UDF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L3_UDF_CH_INT_ST_Pos = 0xa
	// Bit mask of INFIFO_L3_UDF_CH_INT_ST field.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L3_UDF_CH_INT_ST_Msk = 0x400
	// Bit INFIFO_L3_UDF_CH_INT_ST.
	AXI_DMA_IN_INT_ST_CH_INFIFO_L3_UDF_CH_INT_ST = 0x400

	// IN_INT_ENA_CH0: Interrupt enable bits of channel 0
	// Position of IN_DONE_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_IN_DONE_CH_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_IN_SUC_EOF_CH_INT_ENA = 0x2
	// Position of IN_ERR_EOF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_IN_ERR_EOF_CH_INT_ENA = 0x4
	// Position of IN_DSCR_ERR_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_IN_DSCR_ERR_CH_INT_ENA = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_IN_DSCR_EMPTY_CH_INT_ENA = 0x10
	// Position of INFIFO_L1_OVF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L1_OVF_CH_INT_ENA_Pos = 0x5
	// Bit mask of INFIFO_L1_OVF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L1_OVF_CH_INT_ENA_Msk = 0x20
	// Bit INFIFO_L1_OVF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L1_OVF_CH_INT_ENA = 0x20
	// Position of INFIFO_L1_UDF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L1_UDF_CH_INT_ENA_Pos = 0x6
	// Bit mask of INFIFO_L1_UDF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L1_UDF_CH_INT_ENA_Msk = 0x40
	// Bit INFIFO_L1_UDF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L1_UDF_CH_INT_ENA = 0x40
	// Position of INFIFO_L2_OVF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L2_OVF_CH_INT_ENA_Pos = 0x7
	// Bit mask of INFIFO_L2_OVF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L2_OVF_CH_INT_ENA_Msk = 0x80
	// Bit INFIFO_L2_OVF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L2_OVF_CH_INT_ENA = 0x80
	// Position of INFIFO_L2_UDF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L2_UDF_CH_INT_ENA_Pos = 0x8
	// Bit mask of INFIFO_L2_UDF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L2_UDF_CH_INT_ENA_Msk = 0x100
	// Bit INFIFO_L2_UDF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L2_UDF_CH_INT_ENA = 0x100
	// Position of INFIFO_L3_OVF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L3_OVF_CH_INT_ENA_Pos = 0x9
	// Bit mask of INFIFO_L3_OVF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L3_OVF_CH_INT_ENA_Msk = 0x200
	// Bit INFIFO_L3_OVF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L3_OVF_CH_INT_ENA = 0x200
	// Position of INFIFO_L3_UDF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L3_UDF_CH_INT_ENA_Pos = 0xa
	// Bit mask of INFIFO_L3_UDF_CH_INT_ENA field.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L3_UDF_CH_INT_ENA_Msk = 0x400
	// Bit INFIFO_L3_UDF_CH_INT_ENA.
	AXI_DMA_IN_INT_ENA_CH_INFIFO_L3_UDF_CH_INT_ENA = 0x400

	// IN_INT_CLR_CH0: Interrupt clear bits of channel 0
	// Position of IN_DONE_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_IN_DONE_CH_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_IN_SUC_EOF_CH_INT_CLR = 0x2
	// Position of IN_ERR_EOF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR_Msk = 0x4
	// Bit IN_ERR_EOF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_IN_ERR_EOF_CH_INT_CLR = 0x4
	// Position of IN_DSCR_ERR_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR_Msk = 0x8
	// Bit IN_DSCR_ERR_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_IN_DSCR_ERR_CH_INT_CLR = 0x8
	// Position of IN_DSCR_EMPTY_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR_Pos = 0x4
	// Bit mask of IN_DSCR_EMPTY_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR_Msk = 0x10
	// Bit IN_DSCR_EMPTY_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_IN_DSCR_EMPTY_CH_INT_CLR = 0x10
	// Position of INFIFO_L1_OVF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L1_OVF_CH_INT_CLR_Pos = 0x5
	// Bit mask of INFIFO_L1_OVF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L1_OVF_CH_INT_CLR_Msk = 0x20
	// Bit INFIFO_L1_OVF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L1_OVF_CH_INT_CLR = 0x20
	// Position of INFIFO_L1_UDF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L1_UDF_CH_INT_CLR_Pos = 0x6
	// Bit mask of INFIFO_L1_UDF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L1_UDF_CH_INT_CLR_Msk = 0x40
	// Bit INFIFO_L1_UDF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L1_UDF_CH_INT_CLR = 0x40
	// Position of INFIFO_L2_OVF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L2_OVF_CH_INT_CLR_Pos = 0x7
	// Bit mask of INFIFO_L2_OVF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L2_OVF_CH_INT_CLR_Msk = 0x80
	// Bit INFIFO_L2_OVF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L2_OVF_CH_INT_CLR = 0x80
	// Position of INFIFO_L2_UDF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L2_UDF_CH_INT_CLR_Pos = 0x8
	// Bit mask of INFIFO_L2_UDF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L2_UDF_CH_INT_CLR_Msk = 0x100
	// Bit INFIFO_L2_UDF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L2_UDF_CH_INT_CLR = 0x100
	// Position of INFIFO_L3_OVF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L3_OVF_CH_INT_CLR_Pos = 0x9
	// Bit mask of INFIFO_L3_OVF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L3_OVF_CH_INT_CLR_Msk = 0x200
	// Bit INFIFO_L3_OVF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L3_OVF_CH_INT_CLR = 0x200
	// Position of INFIFO_L3_UDF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L3_UDF_CH_INT_CLR_Pos = 0xa
	// Bit mask of INFIFO_L3_UDF_CH_INT_CLR field.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L3_UDF_CH_INT_CLR_Msk = 0x400
	// Bit INFIFO_L3_UDF_CH_INT_CLR.
	AXI_DMA_IN_INT_CLR_CH_INFIFO_L3_UDF_CH_INT_CLR = 0x400

	// IN_CONF0_CH0: Configure 0 register of Rx channel 0
	// Position of IN_RST_CH field.
	AXI_DMA_IN_CONF0_CH_IN_RST_CH_Pos = 0x0
	// Bit mask of IN_RST_CH field.
	AXI_DMA_IN_CONF0_CH_IN_RST_CH_Msk = 0x1
	// Bit IN_RST_CH.
	AXI_DMA_IN_CONF0_CH_IN_RST_CH = 0x1
	// Position of IN_LOOP_TEST_CH field.
	AXI_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH_Pos = 0x1
	// Bit mask of IN_LOOP_TEST_CH field.
	AXI_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH_Msk = 0x2
	// Bit IN_LOOP_TEST_CH.
	AXI_DMA_IN_CONF0_CH_IN_LOOP_TEST_CH = 0x2
	// Position of MEM_TRANS_EN_CH field.
	AXI_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH_Pos = 0x2
	// Bit mask of MEM_TRANS_EN_CH field.
	AXI_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH_Msk = 0x4
	// Bit MEM_TRANS_EN_CH.
	AXI_DMA_IN_CONF0_CH_MEM_TRANS_EN_CH = 0x4
	// Position of IN_ETM_EN_CH field.
	AXI_DMA_IN_CONF0_CH_IN_ETM_EN_CH_Pos = 0x3
	// Bit mask of IN_ETM_EN_CH field.
	AXI_DMA_IN_CONF0_CH_IN_ETM_EN_CH_Msk = 0x8
	// Bit IN_ETM_EN_CH.
	AXI_DMA_IN_CONF0_CH_IN_ETM_EN_CH = 0x8
	// Position of IN_BURST_SIZE_SEL_CH field.
	AXI_DMA_IN_CONF0_CH_IN_BURST_SIZE_SEL_CH_Pos = 0x4
	// Bit mask of IN_BURST_SIZE_SEL_CH field.
	AXI_DMA_IN_CONF0_CH_IN_BURST_SIZE_SEL_CH_Msk = 0x70
	// Position of IN_CMD_DISABLE_CH field.
	AXI_DMA_IN_CONF0_CH_IN_CMD_DISABLE_CH_Pos = 0x7
	// Bit mask of IN_CMD_DISABLE_CH field.
	AXI_DMA_IN_CONF0_CH_IN_CMD_DISABLE_CH_Msk = 0x80
	// Bit IN_CMD_DISABLE_CH.
	AXI_DMA_IN_CONF0_CH_IN_CMD_DISABLE_CH = 0x80
	// Position of IN_ECC_AEC_EN_CH field.
	AXI_DMA_IN_CONF0_CH_IN_ECC_AEC_EN_CH_Pos = 0x8
	// Bit mask of IN_ECC_AEC_EN_CH field.
	AXI_DMA_IN_CONF0_CH_IN_ECC_AEC_EN_CH_Msk = 0x100
	// Bit IN_ECC_AEC_EN_CH.
	AXI_DMA_IN_CONF0_CH_IN_ECC_AEC_EN_CH = 0x100
	// Position of INDSCR_BURST_EN_CH field.
	AXI_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH_Pos = 0x9
	// Bit mask of INDSCR_BURST_EN_CH field.
	AXI_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH_Msk = 0x200
	// Bit INDSCR_BURST_EN_CH.
	AXI_DMA_IN_CONF0_CH_INDSCR_BURST_EN_CH = 0x200

	// IN_CONF1_CH0: Configure 1 register of Rx channel 0
	// Position of IN_CHECK_OWNER_CH field.
	AXI_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH_Pos = 0xc
	// Bit mask of IN_CHECK_OWNER_CH field.
	AXI_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH_Msk = 0x1000
	// Bit IN_CHECK_OWNER_CH.
	AXI_DMA_IN_CONF1_CH_IN_CHECK_OWNER_CH = 0x1000

	// INFIFO_STATUS_CH0: Receive FIFO status of Rx channel 0
	// Position of INFIFO_L3_FULL_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_FULL_CH_Pos = 0x0
	// Bit mask of INFIFO_L3_FULL_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_FULL_CH_Msk = 0x1
	// Bit INFIFO_L3_FULL_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_FULL_CH = 0x1
	// Position of INFIFO_L3_EMPTY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_EMPTY_CH_Pos = 0x1
	// Bit mask of INFIFO_L3_EMPTY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_EMPTY_CH_Msk = 0x2
	// Bit INFIFO_L3_EMPTY_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_EMPTY_CH = 0x2
	// Position of INFIFO_L3_CNT_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_CNT_CH_Pos = 0x2
	// Bit mask of INFIFO_L3_CNT_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_CNT_CH_Msk = 0xfc
	// Position of INFIFO_L3_UDF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_UDF_CH_Pos = 0x8
	// Bit mask of INFIFO_L3_UDF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_UDF_CH_Msk = 0x100
	// Bit INFIFO_L3_UDF_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_UDF_CH = 0x100
	// Position of INFIFO_L3_OVF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_OVF_CH_Pos = 0x9
	// Bit mask of INFIFO_L3_OVF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_OVF_CH_Msk = 0x200
	// Bit INFIFO_L3_OVF_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L3_OVF_CH = 0x200
	// Position of INFIFO_L1_FULL_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_FULL_CH_Pos = 0xa
	// Bit mask of INFIFO_L1_FULL_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_FULL_CH_Msk = 0x400
	// Bit INFIFO_L1_FULL_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_FULL_CH = 0x400
	// Position of INFIFO_L1_EMPTY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_EMPTY_CH_Pos = 0xb
	// Bit mask of INFIFO_L1_EMPTY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_EMPTY_CH_Msk = 0x800
	// Bit INFIFO_L1_EMPTY_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_EMPTY_CH = 0x800
	// Position of INFIFO_L1_UDF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_UDF_CH_Pos = 0xc
	// Bit mask of INFIFO_L1_UDF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_UDF_CH_Msk = 0x1000
	// Bit INFIFO_L1_UDF_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_UDF_CH = 0x1000
	// Position of INFIFO_L1_OVF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_OVF_CH_Pos = 0xd
	// Bit mask of INFIFO_L1_OVF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_OVF_CH_Msk = 0x2000
	// Bit INFIFO_L1_OVF_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L1_OVF_CH = 0x2000
	// Position of INFIFO_L2_FULL_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_FULL_CH_Pos = 0xe
	// Bit mask of INFIFO_L2_FULL_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_FULL_CH_Msk = 0x4000
	// Bit INFIFO_L2_FULL_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_FULL_CH = 0x4000
	// Position of INFIFO_L2_EMPTY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_EMPTY_CH_Pos = 0xf
	// Bit mask of INFIFO_L2_EMPTY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_EMPTY_CH_Msk = 0x8000
	// Bit INFIFO_L2_EMPTY_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_EMPTY_CH = 0x8000
	// Position of INFIFO_L2_UDF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_UDF_CH_Pos = 0x10
	// Bit mask of INFIFO_L2_UDF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_UDF_CH_Msk = 0x10000
	// Bit INFIFO_L2_UDF_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_UDF_CH = 0x10000
	// Position of INFIFO_L2_OVF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_OVF_CH_Pos = 0x11
	// Bit mask of INFIFO_L2_OVF_CH field.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_OVF_CH_Msk = 0x20000
	// Bit INFIFO_L2_OVF_CH.
	AXI_DMA_INFIFO_STATUS_CH_INFIFO_L2_OVF_CH = 0x20000
	// Position of IN_REMAIN_UNDER_1B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH_Pos = 0x17
	// Bit mask of IN_REMAIN_UNDER_1B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH_Msk = 0x800000
	// Bit IN_REMAIN_UNDER_1B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_1B_CH = 0x800000
	// Position of IN_REMAIN_UNDER_2B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH_Pos = 0x18
	// Bit mask of IN_REMAIN_UNDER_2B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH_Msk = 0x1000000
	// Bit IN_REMAIN_UNDER_2B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_2B_CH = 0x1000000
	// Position of IN_REMAIN_UNDER_3B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH_Pos = 0x19
	// Bit mask of IN_REMAIN_UNDER_3B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH_Msk = 0x2000000
	// Bit IN_REMAIN_UNDER_3B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_3B_CH = 0x2000000
	// Position of IN_REMAIN_UNDER_4B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH_Pos = 0x1a
	// Bit mask of IN_REMAIN_UNDER_4B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH_Msk = 0x4000000
	// Bit IN_REMAIN_UNDER_4B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_4B_CH = 0x4000000
	// Position of IN_REMAIN_UNDER_5B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_5B_CH_Pos = 0x1b
	// Bit mask of IN_REMAIN_UNDER_5B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_5B_CH_Msk = 0x8000000
	// Bit IN_REMAIN_UNDER_5B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_5B_CH = 0x8000000
	// Position of IN_REMAIN_UNDER_6B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_6B_CH_Pos = 0x1c
	// Bit mask of IN_REMAIN_UNDER_6B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_6B_CH_Msk = 0x10000000
	// Bit IN_REMAIN_UNDER_6B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_6B_CH = 0x10000000
	// Position of IN_REMAIN_UNDER_7B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_7B_CH_Pos = 0x1d
	// Bit mask of IN_REMAIN_UNDER_7B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_7B_CH_Msk = 0x20000000
	// Bit IN_REMAIN_UNDER_7B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_7B_CH = 0x20000000
	// Position of IN_REMAIN_UNDER_8B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_8B_CH_Pos = 0x1e
	// Bit mask of IN_REMAIN_UNDER_8B_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_8B_CH_Msk = 0x40000000
	// Bit IN_REMAIN_UNDER_8B_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_REMAIN_UNDER_8B_CH = 0x40000000
	// Position of IN_BUF_HUNGRY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH_Pos = 0x1f
	// Bit mask of IN_BUF_HUNGRY_CH field.
	AXI_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH_Msk = 0x80000000
	// Bit IN_BUF_HUNGRY_CH.
	AXI_DMA_INFIFO_STATUS_CH_IN_BUF_HUNGRY_CH = 0x80000000

	// IN_POP_CH0: Pop control register of Rx channel 0
	// Position of INFIFO_RDATA_CH field.
	AXI_DMA_IN_POP_CH_INFIFO_RDATA_CH_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH field.
	AXI_DMA_IN_POP_CH_INFIFO_RDATA_CH_Msk = 0xfff
	// Position of INFIFO_POP_CH field.
	AXI_DMA_IN_POP_CH_INFIFO_POP_CH_Pos = 0xc
	// Bit mask of INFIFO_POP_CH field.
	AXI_DMA_IN_POP_CH_INFIFO_POP_CH_Msk = 0x1000
	// Bit INFIFO_POP_CH.
	AXI_DMA_IN_POP_CH_INFIFO_POP_CH = 0x1000

	// IN_LINK1_CH0: Link descriptor configure and control register of Rx channel 0
	// Position of INLINK_AUTO_RET_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_AUTO_RET_CH_Pos = 0x0
	// Bit mask of INLINK_AUTO_RET_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_AUTO_RET_CH_Msk = 0x1
	// Bit INLINK_AUTO_RET_CH.
	AXI_DMA_IN_LINK1_CH_INLINK_AUTO_RET_CH = 0x1
	// Position of INLINK_STOP_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_STOP_CH_Pos = 0x1
	// Bit mask of INLINK_STOP_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_STOP_CH_Msk = 0x2
	// Bit INLINK_STOP_CH.
	AXI_DMA_IN_LINK1_CH_INLINK_STOP_CH = 0x2
	// Position of INLINK_START_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_START_CH_Pos = 0x2
	// Bit mask of INLINK_START_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_START_CH_Msk = 0x4
	// Bit INLINK_START_CH.
	AXI_DMA_IN_LINK1_CH_INLINK_START_CH = 0x4
	// Position of INLINK_RESTART_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_RESTART_CH_Pos = 0x3
	// Bit mask of INLINK_RESTART_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_RESTART_CH_Msk = 0x8
	// Bit INLINK_RESTART_CH.
	AXI_DMA_IN_LINK1_CH_INLINK_RESTART_CH = 0x8
	// Position of INLINK_PARK_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_PARK_CH_Pos = 0x4
	// Bit mask of INLINK_PARK_CH field.
	AXI_DMA_IN_LINK1_CH_INLINK_PARK_CH_Msk = 0x10
	// Bit INLINK_PARK_CH.
	AXI_DMA_IN_LINK1_CH_INLINK_PARK_CH = 0x10

	// IN_LINK2_CH0: Link descriptor configure and control register of Rx channel 0
	// Position of INLINK_ADDR_CH field.
	AXI_DMA_IN_LINK2_CH_INLINK_ADDR_CH_Pos = 0x0
	// Bit mask of INLINK_ADDR_CH field.
	AXI_DMA_IN_LINK2_CH_INLINK_ADDR_CH_Msk = 0xffffffff

	// IN_STATE_CH0: Receive status of Rx channel 0
	// Position of INLINK_DSCR_ADDR_CH field.
	AXI_DMA_IN_STATE_CH_INLINK_DSCR_ADDR_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_ADDR_CH field.
	AXI_DMA_IN_STATE_CH_INLINK_DSCR_ADDR_CH_Msk = 0x3ffff
	// Position of IN_DSCR_STATE_CH field.
	AXI_DMA_IN_STATE_CH_IN_DSCR_STATE_CH_Pos = 0x12
	// Bit mask of IN_DSCR_STATE_CH field.
	AXI_DMA_IN_STATE_CH_IN_DSCR_STATE_CH_Msk = 0xc0000
	// Position of IN_STATE_CH field.
	AXI_DMA_IN_STATE_CH_IN_STATE_CH_Pos = 0x14
	// Bit mask of IN_STATE_CH field.
	AXI_DMA_IN_STATE_CH_IN_STATE_CH_Msk = 0x700000

	// IN_SUC_EOF_DES_ADDR_CH0: Inlink descriptor address when EOF occurs of Rx channel 0
	// Position of IN_SUC_EOF_DES_ADDR_CH field.
	AXI_DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_CH_Pos = 0x0
	// Bit mask of IN_SUC_EOF_DES_ADDR_CH field.
	AXI_DMA_IN_SUC_EOF_DES_ADDR_CH_IN_SUC_EOF_DES_ADDR_CH_Msk = 0xffffffff

	// IN_ERR_EOF_DES_ADDR_CH0: Inlink descriptor address when errors occur of Rx channel 0
	// Position of IN_ERR_EOF_DES_ADDR_CH field.
	AXI_DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_CH_Pos = 0x0
	// Bit mask of IN_ERR_EOF_DES_ADDR_CH field.
	AXI_DMA_IN_ERR_EOF_DES_ADDR_CH_IN_ERR_EOF_DES_ADDR_CH_Msk = 0xffffffff

	// IN_DSCR_CH0: Current inlink descriptor address of Rx channel 0
	// Position of INLINK_DSCR_CH field.
	AXI_DMA_IN_DSCR_CH_INLINK_DSCR_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_CH field.
	AXI_DMA_IN_DSCR_CH_INLINK_DSCR_CH_Msk = 0xffffffff

	// IN_DSCR_BF0_CH0: The last inlink descriptor address of Rx channel 0
	// Position of INLINK_DSCR_BF0_CH field.
	AXI_DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF0_CH field.
	AXI_DMA_IN_DSCR_BF0_CH_INLINK_DSCR_BF0_CH_Msk = 0xffffffff

	// IN_DSCR_BF1_CH0: The second-to-last inlink descriptor address of Rx channel 0
	// Position of INLINK_DSCR_BF1_CH field.
	AXI_DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_CH_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF1_CH field.
	AXI_DMA_IN_DSCR_BF1_CH_INLINK_DSCR_BF1_CH_Msk = 0xffffffff

	// IN_PRI_CH0: Priority register of Rx channel 0
	// Position of RX_PRI_CH field.
	AXI_DMA_IN_PRI_CH_RX_PRI_CH_Pos = 0x0
	// Bit mask of RX_PRI_CH field.
	AXI_DMA_IN_PRI_CH_RX_PRI_CH_Msk = 0xf
	// Position of RX_CH_ARB_WEIGH_CH field.
	AXI_DMA_IN_PRI_CH_RX_CH_ARB_WEIGH_CH_Pos = 0x4
	// Bit mask of RX_CH_ARB_WEIGH_CH field.
	AXI_DMA_IN_PRI_CH_RX_CH_ARB_WEIGH_CH_Msk = 0xf0
	// Position of RX_ARB_WEIGH_OPT_DIR_CH field.
	AXI_DMA_IN_PRI_CH_RX_ARB_WEIGH_OPT_DIR_CH_Pos = 0x8
	// Bit mask of RX_ARB_WEIGH_OPT_DIR_CH field.
	AXI_DMA_IN_PRI_CH_RX_ARB_WEIGH_OPT_DIR_CH_Msk = 0x100
	// Bit RX_ARB_WEIGH_OPT_DIR_CH.
	AXI_DMA_IN_PRI_CH_RX_ARB_WEIGH_OPT_DIR_CH = 0x100

	// IN_PERI_SEL_CH0: Peripheral selection of Rx channel 0
	// Position of PERI_IN_SEL_CH field.
	AXI_DMA_IN_PERI_SEL_CH_PERI_IN_SEL_CH_Pos = 0x0
	// Bit mask of PERI_IN_SEL_CH field.
	AXI_DMA_IN_PERI_SEL_CH_PERI_IN_SEL_CH_Msk = 0x3f

	// IN_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
	// Position of IN_CRC_INIT_DATA_CH field.
	AXI_DMA_IN_CRC_INIT_DATA_CH_IN_CRC_INIT_DATA_CH_Pos = 0x0
	// Bit mask of IN_CRC_INIT_DATA_CH field.
	AXI_DMA_IN_CRC_INIT_DATA_CH_IN_CRC_INIT_DATA_CH_Msk = 0xffffffff

	// RX_CRC_WIDTH_CH0: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
	// Position of RX_CRC_WIDTH_CH field.
	AXI_DMA_RX_CRC_WIDTH_CH_RX_CRC_WIDTH_CH_Pos = 0x0
	// Bit mask of RX_CRC_WIDTH_CH field.
	AXI_DMA_RX_CRC_WIDTH_CH_RX_CRC_WIDTH_CH_Msk = 0x3
	// Position of RX_CRC_LAUTCH_FLGA_CH field.
	AXI_DMA_RX_CRC_WIDTH_CH_RX_CRC_LAUTCH_FLGA_CH_Pos = 0x2
	// Bit mask of RX_CRC_LAUTCH_FLGA_CH field.
	AXI_DMA_RX_CRC_WIDTH_CH_RX_CRC_LAUTCH_FLGA_CH_Msk = 0x4
	// Bit RX_CRC_LAUTCH_FLGA_CH.
	AXI_DMA_RX_CRC_WIDTH_CH_RX_CRC_LAUTCH_FLGA_CH = 0x4

	// IN_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
	// Position of IN_CRC_CLEAR_CH field.
	AXI_DMA_IN_CRC_CLEAR_CH_IN_CRC_CLEAR_CH_Pos = 0x0
	// Bit mask of IN_CRC_CLEAR_CH field.
	AXI_DMA_IN_CRC_CLEAR_CH_IN_CRC_CLEAR_CH_Msk = 0x1
	// Bit IN_CRC_CLEAR_CH.
	AXI_DMA_IN_CRC_CLEAR_CH_IN_CRC_CLEAR_CH = 0x1

	// IN_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
	// Position of IN_CRC_FINAL_RESULT_CH field.
	AXI_DMA_IN_CRC_FINAL_RESULT_CH_IN_CRC_FINAL_RESULT_CH_Pos = 0x0
	// Bit mask of IN_CRC_FINAL_RESULT_CH field.
	AXI_DMA_IN_CRC_FINAL_RESULT_CH_IN_CRC_FINAL_RESULT_CH_Msk = 0xffffffff

	// RX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
	// Position of RX_CRC_EN_WR_DATA_CH field.
	AXI_DMA_RX_CRC_EN_WR_DATA_CH_RX_CRC_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of RX_CRC_EN_WR_DATA_CH field.
	AXI_DMA_RX_CRC_EN_WR_DATA_CH_RX_CRC_EN_WR_DATA_CH_Msk = 0xffffffff

	// RX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
	// Position of RX_CRC_EN_ADDR_CH field.
	AXI_DMA_RX_CRC_EN_ADDR_CH_RX_CRC_EN_ADDR_CH_Pos = 0x0
	// Bit mask of RX_CRC_EN_ADDR_CH field.
	AXI_DMA_RX_CRC_EN_ADDR_CH_RX_CRC_EN_ADDR_CH_Msk = 0xffffffff

	// RX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
	// Position of RX_CRC_DATA_EN_WR_DATA_CH field.
	AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH_RX_CRC_DATA_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of RX_CRC_DATA_EN_WR_DATA_CH field.
	AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH_RX_CRC_DATA_EN_WR_DATA_CH_Msk = 0xffff

	// RX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
	// Position of RX_CRC_DATA_EN_ADDR_CH field.
	AXI_DMA_RX_CRC_DATA_EN_ADDR_CH_RX_CRC_DATA_EN_ADDR_CH_Pos = 0x0
	// Bit mask of RX_CRC_DATA_EN_ADDR_CH field.
	AXI_DMA_RX_CRC_DATA_EN_ADDR_CH_RX_CRC_DATA_EN_ADDR_CH_Msk = 0xffffffff

	// OUT_INT_RAW_CH0: Raw status interrupt of channel0
	// Position of OUT_DONE_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW_Msk = 0x1
	// Bit OUT_DONE_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUT_DONE_CH_INT_RAW = 0x1
	// Position of OUT_EOF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW_Msk = 0x2
	// Bit OUT_EOF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUT_EOF_CH_INT_RAW = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUT_DSCR_ERR_CH_INT_RAW = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUT_TOTAL_EOF_CH_INT_RAW = 0x8
	// Position of OUTFIFO_L1_OVF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L1_OVF_CH_INT_RAW_Pos = 0x4
	// Bit mask of OUTFIFO_L1_OVF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L1_OVF_CH_INT_RAW_Msk = 0x10
	// Bit OUTFIFO_L1_OVF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L1_OVF_CH_INT_RAW = 0x10
	// Position of OUTFIFO_L1_UDF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L1_UDF_CH_INT_RAW_Pos = 0x5
	// Bit mask of OUTFIFO_L1_UDF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L1_UDF_CH_INT_RAW_Msk = 0x20
	// Bit OUTFIFO_L1_UDF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L1_UDF_CH_INT_RAW = 0x20
	// Position of OUTFIFO_L2_OVF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L2_OVF_CH_INT_RAW_Pos = 0x6
	// Bit mask of OUTFIFO_L2_OVF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L2_OVF_CH_INT_RAW_Msk = 0x40
	// Bit OUTFIFO_L2_OVF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L2_OVF_CH_INT_RAW = 0x40
	// Position of OUTFIFO_L2_UDF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L2_UDF_CH_INT_RAW_Pos = 0x7
	// Bit mask of OUTFIFO_L2_UDF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L2_UDF_CH_INT_RAW_Msk = 0x80
	// Bit OUTFIFO_L2_UDF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L2_UDF_CH_INT_RAW = 0x80
	// Position of OUTFIFO_L3_OVF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L3_OVF_CH_INT_RAW_Pos = 0x8
	// Bit mask of OUTFIFO_L3_OVF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L3_OVF_CH_INT_RAW_Msk = 0x100
	// Bit OUTFIFO_L3_OVF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L3_OVF_CH_INT_RAW = 0x100
	// Position of OUTFIFO_L3_UDF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L3_UDF_CH_INT_RAW_Pos = 0x9
	// Bit mask of OUTFIFO_L3_UDF_CH_INT_RAW field.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L3_UDF_CH_INT_RAW_Msk = 0x200
	// Bit OUTFIFO_L3_UDF_CH_INT_RAW.
	AXI_DMA_OUT_INT_RAW_CH_OUTFIFO_L3_UDF_CH_INT_RAW = 0x200

	// OUT_INT_ST_CH0: Masked interrupt of channel0
	// Position of OUT_DONE_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST_Msk = 0x1
	// Bit OUT_DONE_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUT_DONE_CH_INT_ST = 0x1
	// Position of OUT_EOF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST_Msk = 0x2
	// Bit OUT_EOF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUT_EOF_CH_INT_ST = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUT_DSCR_ERR_CH_INT_ST = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUT_TOTAL_EOF_CH_INT_ST = 0x8
	// Position of OUTFIFO_OVF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST_Msk = 0x10
	// Bit OUTFIFO_OVF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_OVF_CH_INT_ST = 0x10
	// Position of OUTFIFO_UDF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST_Msk = 0x20
	// Bit OUTFIFO_UDF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_UDF_CH_INT_ST = 0x20
	// Position of OUTFIFO_L1_OVF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L1_OVF_CH_INT_ST_Pos = 0x6
	// Bit mask of OUTFIFO_L1_OVF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L1_OVF_CH_INT_ST_Msk = 0x40
	// Bit OUTFIFO_L1_OVF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L1_OVF_CH_INT_ST = 0x40
	// Position of OUTFIFO_L1_UDF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L1_UDF_CH_INT_ST_Pos = 0x7
	// Bit mask of OUTFIFO_L1_UDF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L1_UDF_CH_INT_ST_Msk = 0x80
	// Bit OUTFIFO_L1_UDF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L1_UDF_CH_INT_ST = 0x80
	// Position of OUTFIFO_L3_OVF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L3_OVF_CH_INT_ST_Pos = 0x8
	// Bit mask of OUTFIFO_L3_OVF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L3_OVF_CH_INT_ST_Msk = 0x100
	// Bit OUTFIFO_L3_OVF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L3_OVF_CH_INT_ST = 0x100
	// Position of OUTFIFO_L3_UDF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L3_UDF_CH_INT_ST_Pos = 0x9
	// Bit mask of OUTFIFO_L3_UDF_CH_INT_ST field.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L3_UDF_CH_INT_ST_Msk = 0x200
	// Bit OUTFIFO_L3_UDF_CH_INT_ST.
	AXI_DMA_OUT_INT_ST_CH_OUTFIFO_L3_UDF_CH_INT_ST = 0x200

	// OUT_INT_ENA_CH0: Interrupt enable bits of channel0
	// Position of OUT_DONE_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA_Msk = 0x1
	// Bit OUT_DONE_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUT_DONE_CH_INT_ENA = 0x1
	// Position of OUT_EOF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA_Msk = 0x2
	// Bit OUT_EOF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUT_EOF_CH_INT_ENA = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUT_DSCR_ERR_CH_INT_ENA = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUT_TOTAL_EOF_CH_INT_ENA = 0x8
	// Position of OUTFIFO_L1_OVF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L1_OVF_CH_INT_ENA_Pos = 0x4
	// Bit mask of OUTFIFO_L1_OVF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L1_OVF_CH_INT_ENA_Msk = 0x10
	// Bit OUTFIFO_L1_OVF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L1_OVF_CH_INT_ENA = 0x10
	// Position of OUTFIFO_L1_UDF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L1_UDF_CH_INT_ENA_Pos = 0x5
	// Bit mask of OUTFIFO_L1_UDF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L1_UDF_CH_INT_ENA_Msk = 0x20
	// Bit OUTFIFO_L1_UDF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L1_UDF_CH_INT_ENA = 0x20
	// Position of OUTFIFO_L2_OVF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L2_OVF_CH_INT_ENA_Pos = 0x6
	// Bit mask of OUTFIFO_L2_OVF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L2_OVF_CH_INT_ENA_Msk = 0x40
	// Bit OUTFIFO_L2_OVF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L2_OVF_CH_INT_ENA = 0x40
	// Position of OUTFIFO_L2_UDF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L2_UDF_CH_INT_ENA_Pos = 0x7
	// Bit mask of OUTFIFO_L2_UDF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L2_UDF_CH_INT_ENA_Msk = 0x80
	// Bit OUTFIFO_L2_UDF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L2_UDF_CH_INT_ENA = 0x80
	// Position of OUTFIFO_L3_OVF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L3_OVF_CH_INT_ENA_Pos = 0x8
	// Bit mask of OUTFIFO_L3_OVF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L3_OVF_CH_INT_ENA_Msk = 0x100
	// Bit OUTFIFO_L3_OVF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L3_OVF_CH_INT_ENA = 0x100
	// Position of OUTFIFO_L3_UDF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L3_UDF_CH_INT_ENA_Pos = 0x9
	// Bit mask of OUTFIFO_L3_UDF_CH_INT_ENA field.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L3_UDF_CH_INT_ENA_Msk = 0x200
	// Bit OUTFIFO_L3_UDF_CH_INT_ENA.
	AXI_DMA_OUT_INT_ENA_CH_OUTFIFO_L3_UDF_CH_INT_ENA = 0x200

	// OUT_INT_CLR_CH0: Interrupt clear bits of channel0
	// Position of OUT_DONE_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR_Pos = 0x0
	// Bit mask of OUT_DONE_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR_Msk = 0x1
	// Bit OUT_DONE_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUT_DONE_CH_INT_CLR = 0x1
	// Position of OUT_EOF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR_Pos = 0x1
	// Bit mask of OUT_EOF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR_Msk = 0x2
	// Bit OUT_EOF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUT_EOF_CH_INT_CLR = 0x2
	// Position of OUT_DSCR_ERR_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUT_DSCR_ERR_CH_INT_CLR = 0x4
	// Position of OUT_TOTAL_EOF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUT_TOTAL_EOF_CH_INT_CLR = 0x8
	// Position of OUTFIFO_L1_OVF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L1_OVF_CH_INT_CLR_Pos = 0x4
	// Bit mask of OUTFIFO_L1_OVF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L1_OVF_CH_INT_CLR_Msk = 0x10
	// Bit OUTFIFO_L1_OVF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L1_OVF_CH_INT_CLR = 0x10
	// Position of OUTFIFO_L1_UDF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L1_UDF_CH_INT_CLR_Pos = 0x5
	// Bit mask of OUTFIFO_L1_UDF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L1_UDF_CH_INT_CLR_Msk = 0x20
	// Bit OUTFIFO_L1_UDF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L1_UDF_CH_INT_CLR = 0x20
	// Position of OUTFIFO_L2_OVF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L2_OVF_CH_INT_CLR_Pos = 0x6
	// Bit mask of OUTFIFO_L2_OVF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L2_OVF_CH_INT_CLR_Msk = 0x40
	// Bit OUTFIFO_L2_OVF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L2_OVF_CH_INT_CLR = 0x40
	// Position of OUTFIFO_L2_UDF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L2_UDF_CH_INT_CLR_Pos = 0x7
	// Bit mask of OUTFIFO_L2_UDF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L2_UDF_CH_INT_CLR_Msk = 0x80
	// Bit OUTFIFO_L2_UDF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L2_UDF_CH_INT_CLR = 0x80
	// Position of OUTFIFO_L3_OVF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L3_OVF_CH_INT_CLR_Pos = 0x8
	// Bit mask of OUTFIFO_L3_OVF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L3_OVF_CH_INT_CLR_Msk = 0x100
	// Bit OUTFIFO_L3_OVF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L3_OVF_CH_INT_CLR = 0x100
	// Position of OUTFIFO_L3_UDF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L3_UDF_CH_INT_CLR_Pos = 0x9
	// Bit mask of OUTFIFO_L3_UDF_CH_INT_CLR field.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L3_UDF_CH_INT_CLR_Msk = 0x200
	// Bit OUTFIFO_L3_UDF_CH_INT_CLR.
	AXI_DMA_OUT_INT_CLR_CH_OUTFIFO_L3_UDF_CH_INT_CLR = 0x200

	// OUT_CONF0_CH0: Configure 0 register of Tx channel0
	// Position of OUT_RST_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Pos = 0x0
	// Bit mask of OUT_RST_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Msk = 0x1
	// Bit OUT_RST_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUT_RST_CH0 = 0x1
	// Position of OUT_LOOP_TEST_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0_Pos = 0x1
	// Bit mask of OUT_LOOP_TEST_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0_Msk = 0x2
	// Bit OUT_LOOP_TEST_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUT_LOOP_TEST_CH0 = 0x2
	// Position of OUT_AUTO_WRBACK_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Pos = 0x2
	// Bit mask of OUT_AUTO_WRBACK_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Msk = 0x4
	// Bit OUT_AUTO_WRBACK_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0 = 0x4
	// Position of OUT_EOF_MODE_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Pos = 0x3
	// Bit mask of OUT_EOF_MODE_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Msk = 0x8
	// Bit OUT_EOF_MODE_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0 = 0x8
	// Position of OUT_ETM_EN_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0_Pos = 0x4
	// Bit mask of OUT_ETM_EN_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0_Msk = 0x10
	// Bit OUT_ETM_EN_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUT_ETM_EN_CH0 = 0x10
	// Position of OUT_BURST_SIZE_SEL_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_BURST_SIZE_SEL_CH0_Pos = 0x5
	// Bit mask of OUT_BURST_SIZE_SEL_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_BURST_SIZE_SEL_CH0_Msk = 0xe0
	// Position of OUT_CMD_DISABLE_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_CMD_DISABLE_CH0_Pos = 0x8
	// Bit mask of OUT_CMD_DISABLE_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_CMD_DISABLE_CH0_Msk = 0x100
	// Bit OUT_CMD_DISABLE_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUT_CMD_DISABLE_CH0 = 0x100
	// Position of OUT_ECC_AEC_EN_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_ECC_AEC_EN_CH0_Pos = 0x9
	// Bit mask of OUT_ECC_AEC_EN_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUT_ECC_AEC_EN_CH0_Msk = 0x200
	// Bit OUT_ECC_AEC_EN_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUT_ECC_AEC_EN_CH0 = 0x200
	// Position of OUTDSCR_BURST_EN_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Pos = 0xa
	// Bit mask of OUTDSCR_BURST_EN_CH0 field.
	AXI_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Msk = 0x400
	// Bit OUTDSCR_BURST_EN_CH0.
	AXI_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0 = 0x400

	// OUT_CONF1_CH0: Configure 1 register of Tx channel0
	// Position of OUT_CHECK_OWNER_CH field.
	AXI_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH_Pos = 0xc
	// Bit mask of OUT_CHECK_OWNER_CH field.
	AXI_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH_Msk = 0x1000
	// Bit OUT_CHECK_OWNER_CH.
	AXI_DMA_OUT_CONF1_CH_OUT_CHECK_OWNER_CH = 0x1000

	// OUTFIFO_STATUS_CH0: Transmit FIFO status of Tx channel0
	// Position of OUTFIFO_L3_FULL_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_FULL_CH_Pos = 0x0
	// Bit mask of OUTFIFO_L3_FULL_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_FULL_CH_Msk = 0x1
	// Bit OUTFIFO_L3_FULL_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_FULL_CH = 0x1
	// Position of OUTFIFO_L3_EMPTY_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_EMPTY_CH_Pos = 0x1
	// Bit mask of OUTFIFO_L3_EMPTY_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_EMPTY_CH_Msk = 0x2
	// Bit OUTFIFO_L3_EMPTY_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_EMPTY_CH = 0x2
	// Position of OUTFIFO_L3_CNT_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_CNT_CH_Pos = 0x2
	// Bit mask of OUTFIFO_L3_CNT_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_CNT_CH_Msk = 0xfc
	// Position of OUTFIFO_L3_UDF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_UDF_CH_Pos = 0x8
	// Bit mask of OUTFIFO_L3_UDF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_UDF_CH_Msk = 0x100
	// Bit OUTFIFO_L3_UDF_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_UDF_CH = 0x100
	// Position of OUTFIFO_L3_OVF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_OVF_CH_Pos = 0x9
	// Bit mask of OUTFIFO_L3_OVF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_OVF_CH_Msk = 0x200
	// Bit OUTFIFO_L3_OVF_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L3_OVF_CH = 0x200
	// Position of OUTFIFO_L1_FULL_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_FULL_CH_Pos = 0xa
	// Bit mask of OUTFIFO_L1_FULL_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_FULL_CH_Msk = 0x400
	// Bit OUTFIFO_L1_FULL_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_FULL_CH = 0x400
	// Position of OUTFIFO_L1_EMPTY_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_EMPTY_CH_Pos = 0xb
	// Bit mask of OUTFIFO_L1_EMPTY_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_EMPTY_CH_Msk = 0x800
	// Bit OUTFIFO_L1_EMPTY_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_EMPTY_CH = 0x800
	// Position of OUTFIFO_L1_UDF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_UDF_CH_Pos = 0xc
	// Bit mask of OUTFIFO_L1_UDF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_UDF_CH_Msk = 0x1000
	// Bit OUTFIFO_L1_UDF_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_UDF_CH = 0x1000
	// Position of OUTFIFO_L1_OVF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_OVF_CH_Pos = 0xd
	// Bit mask of OUTFIFO_L1_OVF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_OVF_CH_Msk = 0x2000
	// Bit OUTFIFO_L1_OVF_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L1_OVF_CH = 0x2000
	// Position of OUTFIFO_L2_FULL_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_FULL_CH_Pos = 0xe
	// Bit mask of OUTFIFO_L2_FULL_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_FULL_CH_Msk = 0x4000
	// Bit OUTFIFO_L2_FULL_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_FULL_CH = 0x4000
	// Position of OUTFIFO_L2_EMPTY_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_EMPTY_CH_Pos = 0xf
	// Bit mask of OUTFIFO_L2_EMPTY_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_EMPTY_CH_Msk = 0x8000
	// Bit OUTFIFO_L2_EMPTY_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_EMPTY_CH = 0x8000
	// Position of OUTFIFO_L2_UDF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_UDF_CH_Pos = 0x10
	// Bit mask of OUTFIFO_L2_UDF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_UDF_CH_Msk = 0x10000
	// Bit OUTFIFO_L2_UDF_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_UDF_CH = 0x10000
	// Position of OUTFIFO_L2_OVF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_OVF_CH_Pos = 0x11
	// Bit mask of OUTFIFO_L2_OVF_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_OVF_CH_Msk = 0x20000
	// Bit OUTFIFO_L2_OVF_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUTFIFO_L2_OVF_CH = 0x20000
	// Position of OUT_REMAIN_UNDER_1B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH_Pos = 0x17
	// Bit mask of OUT_REMAIN_UNDER_1B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH_Msk = 0x800000
	// Bit OUT_REMAIN_UNDER_1B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_1B_CH = 0x800000
	// Position of OUT_REMAIN_UNDER_2B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH_Pos = 0x18
	// Bit mask of OUT_REMAIN_UNDER_2B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH_Msk = 0x1000000
	// Bit OUT_REMAIN_UNDER_2B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_2B_CH = 0x1000000
	// Position of OUT_REMAIN_UNDER_3B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH_Pos = 0x19
	// Bit mask of OUT_REMAIN_UNDER_3B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH_Msk = 0x2000000
	// Bit OUT_REMAIN_UNDER_3B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_3B_CH = 0x2000000
	// Position of OUT_REMAIN_UNDER_4B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH_Pos = 0x1a
	// Bit mask of OUT_REMAIN_UNDER_4B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH_Msk = 0x4000000
	// Bit OUT_REMAIN_UNDER_4B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_4B_CH = 0x4000000
	// Position of OUT_REMAIN_UNDER_5B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_5B_CH_Pos = 0x1b
	// Bit mask of OUT_REMAIN_UNDER_5B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_5B_CH_Msk = 0x8000000
	// Bit OUT_REMAIN_UNDER_5B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_5B_CH = 0x8000000
	// Position of OUT_REMAIN_UNDER_6B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_6B_CH_Pos = 0x1c
	// Bit mask of OUT_REMAIN_UNDER_6B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_6B_CH_Msk = 0x10000000
	// Bit OUT_REMAIN_UNDER_6B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_6B_CH = 0x10000000
	// Position of OUT_REMAIN_UNDER_7B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_7B_CH_Pos = 0x1d
	// Bit mask of OUT_REMAIN_UNDER_7B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_7B_CH_Msk = 0x20000000
	// Bit OUT_REMAIN_UNDER_7B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_7B_CH = 0x20000000
	// Position of OUT_REMAIN_UNDER_8B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_8B_CH_Pos = 0x1e
	// Bit mask of OUT_REMAIN_UNDER_8B_CH field.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_8B_CH_Msk = 0x40000000
	// Bit OUT_REMAIN_UNDER_8B_CH.
	AXI_DMA_OUTFIFO_STATUS_CH_OUT_REMAIN_UNDER_8B_CH = 0x40000000

	// OUT_PUSH_CH0: Push control register of Tx channel0
	// Position of OUTFIFO_WDATA_CH field.
	AXI_DMA_OUT_PUSH_CH_OUTFIFO_WDATA_CH_Pos = 0x0
	// Bit mask of OUTFIFO_WDATA_CH field.
	AXI_DMA_OUT_PUSH_CH_OUTFIFO_WDATA_CH_Msk = 0x1ff
	// Position of OUTFIFO_PUSH_CH field.
	AXI_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH_Pos = 0x9
	// Bit mask of OUTFIFO_PUSH_CH field.
	AXI_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH_Msk = 0x200
	// Bit OUTFIFO_PUSH_CH.
	AXI_DMA_OUT_PUSH_CH_OUTFIFO_PUSH_CH = 0x200

	// OUT_LINK1_CH0: Link descriptor configure and control register of Tx channel0
	// Position of OUTLINK_STOP_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_STOP_CH_Pos = 0x0
	// Bit mask of OUTLINK_STOP_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_STOP_CH_Msk = 0x1
	// Bit OUTLINK_STOP_CH.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_STOP_CH = 0x1
	// Position of OUTLINK_START_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_START_CH_Pos = 0x1
	// Bit mask of OUTLINK_START_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_START_CH_Msk = 0x2
	// Bit OUTLINK_START_CH.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_START_CH = 0x2
	// Position of OUTLINK_RESTART_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_RESTART_CH_Pos = 0x2
	// Bit mask of OUTLINK_RESTART_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_RESTART_CH_Msk = 0x4
	// Bit OUTLINK_RESTART_CH.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_RESTART_CH = 0x4
	// Position of OUTLINK_PARK_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_PARK_CH_Pos = 0x3
	// Bit mask of OUTLINK_PARK_CH field.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_PARK_CH_Msk = 0x8
	// Bit OUTLINK_PARK_CH.
	AXI_DMA_OUT_LINK1_CH_OUTLINK_PARK_CH = 0x8

	// OUT_LINK2_CH0: Link descriptor configure and control register of Tx channel0
	// Position of OUTLINK_ADDR_CH field.
	AXI_DMA_OUT_LINK2_CH_OUTLINK_ADDR_CH_Pos = 0x0
	// Bit mask of OUTLINK_ADDR_CH field.
	AXI_DMA_OUT_LINK2_CH_OUTLINK_ADDR_CH_Msk = 0xffffffff

	// OUT_STATE_CH0: Transmit status of Tx channel0
	// Position of OUTLINK_DSCR_ADDR_CH field.
	AXI_DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_ADDR_CH field.
	AXI_DMA_OUT_STATE_CH_OUTLINK_DSCR_ADDR_CH_Msk = 0x3ffff
	// Position of OUT_DSCR_STATE_CH field.
	AXI_DMA_OUT_STATE_CH_OUT_DSCR_STATE_CH_Pos = 0x12
	// Bit mask of OUT_DSCR_STATE_CH field.
	AXI_DMA_OUT_STATE_CH_OUT_DSCR_STATE_CH_Msk = 0xc0000
	// Position of OUT_STATE_CH field.
	AXI_DMA_OUT_STATE_CH_OUT_STATE_CH_Pos = 0x14
	// Bit mask of OUT_STATE_CH field.
	AXI_DMA_OUT_STATE_CH_OUT_STATE_CH_Msk = 0x700000

	// OUT_EOF_DES_ADDR_CH0: Outlink descriptor address when EOF occurs of Tx channel0
	// Position of OUT_EOF_DES_ADDR_CH field.
	AXI_DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_CH_Pos = 0x0
	// Bit mask of OUT_EOF_DES_ADDR_CH field.
	AXI_DMA_OUT_EOF_DES_ADDR_CH_OUT_EOF_DES_ADDR_CH_Msk = 0xffffffff

	// OUT_EOF_BFR_DES_ADDR_CH0: The last outlink descriptor address when EOF occurs of Tx channel0
	// Position of OUT_EOF_BFR_DES_ADDR_CH field.
	AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_CH_Pos = 0x0
	// Bit mask of OUT_EOF_BFR_DES_ADDR_CH field.
	AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH_OUT_EOF_BFR_DES_ADDR_CH_Msk = 0xffffffff

	// OUT_DSCR_CH0: Current outlink descriptor address of Tx channel0
	// Position of OUTLINK_DSCR_CH field.
	AXI_DMA_OUT_DSCR_CH_OUTLINK_DSCR_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_CH field.
	AXI_DMA_OUT_DSCR_CH_OUTLINK_DSCR_CH_Msk = 0xffffffff

	// OUT_DSCR_BF0_CH0: The last outlink descriptor address of Tx channel0
	// Position of OUTLINK_DSCR_BF0_CH field.
	AXI_DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF0_CH field.
	AXI_DMA_OUT_DSCR_BF0_CH_OUTLINK_DSCR_BF0_CH_Msk = 0xffffffff

	// OUT_DSCR_BF1_CH0: The second-to-last outlink descriptor address of Tx channel0
	// Position of OUTLINK_DSCR_BF1_CH field.
	AXI_DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_CH_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF1_CH field.
	AXI_DMA_OUT_DSCR_BF1_CH_OUTLINK_DSCR_BF1_CH_Msk = 0xffffffff

	// OUT_PRI_CH0: Priority register of Tx channel0.
	// Position of TX_PRI_CH field.
	AXI_DMA_OUT_PRI_CH_TX_PRI_CH_Pos = 0x0
	// Bit mask of TX_PRI_CH field.
	AXI_DMA_OUT_PRI_CH_TX_PRI_CH_Msk = 0xf
	// Position of TX_CH_ARB_WEIGH_CH field.
	AXI_DMA_OUT_PRI_CH_TX_CH_ARB_WEIGH_CH_Pos = 0x4
	// Bit mask of TX_CH_ARB_WEIGH_CH field.
	AXI_DMA_OUT_PRI_CH_TX_CH_ARB_WEIGH_CH_Msk = 0xf0
	// Position of TX_ARB_WEIGH_OPT_DIR_CH field.
	AXI_DMA_OUT_PRI_CH_TX_ARB_WEIGH_OPT_DIR_CH_Pos = 0x8
	// Bit mask of TX_ARB_WEIGH_OPT_DIR_CH field.
	AXI_DMA_OUT_PRI_CH_TX_ARB_WEIGH_OPT_DIR_CH_Msk = 0x100
	// Bit TX_ARB_WEIGH_OPT_DIR_CH.
	AXI_DMA_OUT_PRI_CH_TX_ARB_WEIGH_OPT_DIR_CH = 0x100

	// OUT_PERI_SEL_CH0: Peripheral selection of Tx channel0
	// Position of PERI_OUT_SEL_CH field.
	AXI_DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_CH_Pos = 0x0
	// Bit mask of PERI_OUT_SEL_CH field.
	AXI_DMA_OUT_PERI_SEL_CH_PERI_OUT_SEL_CH_Msk = 0x3f

	// OUT_CRC_INIT_DATA_CH0: This register is used to config ch0 crc initial data(max 32 bit)
	// Position of OUT_CRC_INIT_DATA_CH field.
	AXI_DMA_OUT_CRC_INIT_DATA_CH_OUT_CRC_INIT_DATA_CH_Pos = 0x0
	// Bit mask of OUT_CRC_INIT_DATA_CH field.
	AXI_DMA_OUT_CRC_INIT_DATA_CH_OUT_CRC_INIT_DATA_CH_Msk = 0xffffffff

	// TX_CRC_WIDTH_CH0: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32
	// Position of TX_CRC_WIDTH_CH field.
	AXI_DMA_TX_CRC_WIDTH_CH_TX_CRC_WIDTH_CH_Pos = 0x0
	// Bit mask of TX_CRC_WIDTH_CH field.
	AXI_DMA_TX_CRC_WIDTH_CH_TX_CRC_WIDTH_CH_Msk = 0x3
	// Position of TX_CRC_LAUTCH_FLGA_CH field.
	AXI_DMA_TX_CRC_WIDTH_CH_TX_CRC_LAUTCH_FLGA_CH_Pos = 0x2
	// Bit mask of TX_CRC_LAUTCH_FLGA_CH field.
	AXI_DMA_TX_CRC_WIDTH_CH_TX_CRC_LAUTCH_FLGA_CH_Msk = 0x4
	// Bit TX_CRC_LAUTCH_FLGA_CH.
	AXI_DMA_TX_CRC_WIDTH_CH_TX_CRC_LAUTCH_FLGA_CH = 0x4

	// OUT_CRC_CLEAR_CH0: This register is used to clear ch0 crc result
	// Position of OUT_CRC_CLEAR_CH field.
	AXI_DMA_OUT_CRC_CLEAR_CH_OUT_CRC_CLEAR_CH_Pos = 0x0
	// Bit mask of OUT_CRC_CLEAR_CH field.
	AXI_DMA_OUT_CRC_CLEAR_CH_OUT_CRC_CLEAR_CH_Msk = 0x1
	// Bit OUT_CRC_CLEAR_CH.
	AXI_DMA_OUT_CRC_CLEAR_CH_OUT_CRC_CLEAR_CH = 0x1

	// OUT_CRC_FINAL_RESULT_CH0: This register is used to store ch0 crc result
	// Position of OUT_CRC_FINAL_RESULT_CH field.
	AXI_DMA_OUT_CRC_FINAL_RESULT_CH_OUT_CRC_FINAL_RESULT_CH_Pos = 0x0
	// Bit mask of OUT_CRC_FINAL_RESULT_CH field.
	AXI_DMA_OUT_CRC_FINAL_RESULT_CH_OUT_CRC_FINAL_RESULT_CH_Msk = 0xffffffff

	// TX_CRC_EN_WR_DATA_CH0: This resister is used to config ch0 crc en for every bit
	// Position of TX_CRC_EN_WR_DATA_CH field.
	AXI_DMA_TX_CRC_EN_WR_DATA_CH_TX_CRC_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of TX_CRC_EN_WR_DATA_CH field.
	AXI_DMA_TX_CRC_EN_WR_DATA_CH_TX_CRC_EN_WR_DATA_CH_Msk = 0xffffffff

	// TX_CRC_EN_ADDR_CH0: This register is used to config ch0 crc en addr
	// Position of TX_CRC_EN_ADDR_CH field.
	AXI_DMA_TX_CRC_EN_ADDR_CH_TX_CRC_EN_ADDR_CH_Pos = 0x0
	// Bit mask of TX_CRC_EN_ADDR_CH field.
	AXI_DMA_TX_CRC_EN_ADDR_CH_TX_CRC_EN_ADDR_CH_Msk = 0xffffffff

	// TX_CRC_DATA_EN_WR_DATA_CH0: This register is used to config crc data_8bit en
	// Position of TX_CRC_DATA_EN_WR_DATA_CH field.
	AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH_TX_CRC_DATA_EN_WR_DATA_CH_Pos = 0x0
	// Bit mask of TX_CRC_DATA_EN_WR_DATA_CH field.
	AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH_TX_CRC_DATA_EN_WR_DATA_CH_Msk = 0xffff

	// TX_CRC_DATA_EN_ADDR_CH0: This register is used to config addr of crc data_8bit en
	// Position of TX_CRC_DATA_EN_ADDR_CH field.
	AXI_DMA_TX_CRC_DATA_EN_ADDR_CH_TX_CRC_DATA_EN_ADDR_CH_Pos = 0x0
	// Bit mask of TX_CRC_DATA_EN_ADDR_CH field.
	AXI_DMA_TX_CRC_DATA_EN_ADDR_CH_TX_CRC_DATA_EN_ADDR_CH_Msk = 0xffffffff

	// OUT_CONF0_CH1: Configure 0 register of Tx channel1
	// Position of OUT_RST_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_RST_CH1_Pos = 0x0
	// Bit mask of OUT_RST_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_RST_CH1_Msk = 0x1
	// Bit OUT_RST_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUT_RST_CH1 = 0x1
	// Position of OUT_LOOP_TEST_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_LOOP_TEST_CH1_Pos = 0x1
	// Bit mask of OUT_LOOP_TEST_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_LOOP_TEST_CH1_Msk = 0x2
	// Bit OUT_LOOP_TEST_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUT_LOOP_TEST_CH1 = 0x2
	// Position of OUT_AUTO_WRBACK_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1_Pos = 0x2
	// Bit mask of OUT_AUTO_WRBACK_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1_Msk = 0x4
	// Bit OUT_AUTO_WRBACK_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1 = 0x4
	// Position of OUT_EOF_MODE_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_EOF_MODE_CH1_Pos = 0x3
	// Bit mask of OUT_EOF_MODE_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_EOF_MODE_CH1_Msk = 0x8
	// Bit OUT_EOF_MODE_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUT_EOF_MODE_CH1 = 0x8
	// Position of OUT_ETM_EN_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_ETM_EN_CH1_Pos = 0x4
	// Bit mask of OUT_ETM_EN_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_ETM_EN_CH1_Msk = 0x10
	// Bit OUT_ETM_EN_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUT_ETM_EN_CH1 = 0x10
	// Position of OUT_BURST_SIZE_SEL_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_BURST_SIZE_SEL_CH1_Pos = 0x5
	// Bit mask of OUT_BURST_SIZE_SEL_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_BURST_SIZE_SEL_CH1_Msk = 0xe0
	// Position of OUT_CMD_DISABLE_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_CMD_DISABLE_CH1_Pos = 0x8
	// Bit mask of OUT_CMD_DISABLE_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_CMD_DISABLE_CH1_Msk = 0x100
	// Bit OUT_CMD_DISABLE_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUT_CMD_DISABLE_CH1 = 0x100
	// Position of OUT_ECC_AEC_EN_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_ECC_AEC_EN_CH1_Pos = 0x9
	// Bit mask of OUT_ECC_AEC_EN_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUT_ECC_AEC_EN_CH1_Msk = 0x200
	// Bit OUT_ECC_AEC_EN_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUT_ECC_AEC_EN_CH1 = 0x200
	// Position of OUTDSCR_BURST_EN_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1_Pos = 0xa
	// Bit mask of OUTDSCR_BURST_EN_CH1 field.
	AXI_DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1_Msk = 0x400
	// Bit OUTDSCR_BURST_EN_CH1.
	AXI_DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1 = 0x400

	// OUT_CONF0_CH2: Configure 0 register of Tx channel2
	// Position of OUT_RST_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_RST_CH2_Pos = 0x0
	// Bit mask of OUT_RST_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_RST_CH2_Msk = 0x1
	// Bit OUT_RST_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUT_RST_CH2 = 0x1
	// Position of OUT_LOOP_TEST_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_LOOP_TEST_CH2_Pos = 0x1
	// Bit mask of OUT_LOOP_TEST_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_LOOP_TEST_CH2_Msk = 0x2
	// Bit OUT_LOOP_TEST_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUT_LOOP_TEST_CH2 = 0x2
	// Position of OUT_AUTO_WRBACK_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2_Pos = 0x2
	// Bit mask of OUT_AUTO_WRBACK_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2_Msk = 0x4
	// Bit OUT_AUTO_WRBACK_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2 = 0x4
	// Position of OUT_EOF_MODE_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_EOF_MODE_CH2_Pos = 0x3
	// Bit mask of OUT_EOF_MODE_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_EOF_MODE_CH2_Msk = 0x8
	// Bit OUT_EOF_MODE_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUT_EOF_MODE_CH2 = 0x8
	// Position of OUT_ETM_EN_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_ETM_EN_CH2_Pos = 0x4
	// Bit mask of OUT_ETM_EN_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_ETM_EN_CH2_Msk = 0x10
	// Bit OUT_ETM_EN_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUT_ETM_EN_CH2 = 0x10
	// Position of OUT_BURST_SIZE_SEL_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_BURST_SIZE_SEL_CH2_Pos = 0x5
	// Bit mask of OUT_BURST_SIZE_SEL_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_BURST_SIZE_SEL_CH2_Msk = 0xe0
	// Position of OUT_CMD_DISABLE_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_CMD_DISABLE_CH2_Pos = 0x8
	// Bit mask of OUT_CMD_DISABLE_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_CMD_DISABLE_CH2_Msk = 0x100
	// Bit OUT_CMD_DISABLE_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUT_CMD_DISABLE_CH2 = 0x100
	// Position of OUT_ECC_AEC_EN_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_ECC_AEC_EN_CH2_Pos = 0x9
	// Bit mask of OUT_ECC_AEC_EN_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUT_ECC_AEC_EN_CH2_Msk = 0x200
	// Bit OUT_ECC_AEC_EN_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUT_ECC_AEC_EN_CH2 = 0x200
	// Position of OUTDSCR_BURST_EN_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2_Pos = 0xa
	// Bit mask of OUTDSCR_BURST_EN_CH2 field.
	AXI_DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2_Msk = 0x400
	// Bit OUTDSCR_BURST_EN_CH2.
	AXI_DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2 = 0x400

	// ARB_TIMEOUT: This retister is used to config arbiter time slice
	// Position of TX field.
	AXI_DMA_ARB_TIMEOUT_TX_Pos = 0x0
	// Bit mask of TX field.
	AXI_DMA_ARB_TIMEOUT_TX_Msk = 0xffff
	// Position of RX field.
	AXI_DMA_ARB_TIMEOUT_RX_Pos = 0x10
	// Bit mask of RX field.
	AXI_DMA_ARB_TIMEOUT_RX_Msk = 0xffff0000

	// WEIGHT_EN: This register is used to config arbiter weight function to on or off
	// Position of TX field.
	AXI_DMA_WEIGHT_EN_TX_Pos = 0x0
	// Bit mask of TX field.
	AXI_DMA_WEIGHT_EN_TX_Msk = 0x1
	// Bit TX.
	AXI_DMA_WEIGHT_EN_TX = 0x1
	// Position of RX field.
	AXI_DMA_WEIGHT_EN_RX_Pos = 0x1
	// Bit mask of RX field.
	AXI_DMA_WEIGHT_EN_RX_Msk = 0x2
	// Bit RX.
	AXI_DMA_WEIGHT_EN_RX = 0x2

	// IN_MEM_CONF: Mem power configure register of Rx channel
	// Position of IN_MEM_CLK_FORCE_EN field.
	AXI_DMA_IN_MEM_CONF_IN_MEM_CLK_FORCE_EN_Pos = 0x0
	// Bit mask of IN_MEM_CLK_FORCE_EN field.
	AXI_DMA_IN_MEM_CONF_IN_MEM_CLK_FORCE_EN_Msk = 0x1
	// Bit IN_MEM_CLK_FORCE_EN.
	AXI_DMA_IN_MEM_CONF_IN_MEM_CLK_FORCE_EN = 0x1
	// Position of IN_MEM_FORCE_PU field.
	AXI_DMA_IN_MEM_CONF_IN_MEM_FORCE_PU_Pos = 0x1
	// Bit mask of IN_MEM_FORCE_PU field.
	AXI_DMA_IN_MEM_CONF_IN_MEM_FORCE_PU_Msk = 0x2
	// Bit IN_MEM_FORCE_PU.
	AXI_DMA_IN_MEM_CONF_IN_MEM_FORCE_PU = 0x2
	// Position of IN_MEM_FORCE_PD field.
	AXI_DMA_IN_MEM_CONF_IN_MEM_FORCE_PD_Pos = 0x2
	// Bit mask of IN_MEM_FORCE_PD field.
	AXI_DMA_IN_MEM_CONF_IN_MEM_FORCE_PD_Msk = 0x4
	// Bit IN_MEM_FORCE_PD.
	AXI_DMA_IN_MEM_CONF_IN_MEM_FORCE_PD = 0x4
	// Position of OUT_MEM_CLK_FORCE_EN field.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_CLK_FORCE_EN_Pos = 0x3
	// Bit mask of OUT_MEM_CLK_FORCE_EN field.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_CLK_FORCE_EN_Msk = 0x8
	// Bit OUT_MEM_CLK_FORCE_EN.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_CLK_FORCE_EN = 0x8
	// Position of OUT_MEM_FORCE_PU field.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_FORCE_PU_Pos = 0x4
	// Bit mask of OUT_MEM_FORCE_PU field.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_FORCE_PU_Msk = 0x10
	// Bit OUT_MEM_FORCE_PU.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_FORCE_PU = 0x10
	// Position of OUT_MEM_FORCE_PD field.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_FORCE_PD_Pos = 0x5
	// Bit mask of OUT_MEM_FORCE_PD field.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_FORCE_PD_Msk = 0x20
	// Bit OUT_MEM_FORCE_PD.
	AXI_DMA_IN_MEM_CONF_OUT_MEM_FORCE_PD = 0x20

	// INTR_MEM_START_ADDR: The start address of accessible address space.
	// Position of ACCESS_INTR_MEM_START_ADDR field.
	AXI_DMA_INTR_MEM_START_ADDR_ACCESS_INTR_MEM_START_ADDR_Pos = 0x0
	// Bit mask of ACCESS_INTR_MEM_START_ADDR field.
	AXI_DMA_INTR_MEM_START_ADDR_ACCESS_INTR_MEM_START_ADDR_Msk = 0xffffffff

	// INTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error.
	// Position of ACCESS_INTR_MEM_END_ADDR field.
	AXI_DMA_INTR_MEM_END_ADDR_ACCESS_INTR_MEM_END_ADDR_Pos = 0x0
	// Bit mask of ACCESS_INTR_MEM_END_ADDR field.
	AXI_DMA_INTR_MEM_END_ADDR_ACCESS_INTR_MEM_END_ADDR_Msk = 0xffffffff

	// EXTR_MEM_START_ADDR: The start address of accessible address space.
	// Position of ACCESS_EXTR_MEM_START_ADDR field.
	AXI_DMA_EXTR_MEM_START_ADDR_ACCESS_EXTR_MEM_START_ADDR_Pos = 0x0
	// Bit mask of ACCESS_EXTR_MEM_START_ADDR field.
	AXI_DMA_EXTR_MEM_START_ADDR_ACCESS_EXTR_MEM_START_ADDR_Msk = 0xffffffff

	// EXTR_MEM_END_ADDR: The end address of accessible address space. The access address beyond this range would lead to descriptor error.
	// Position of ACCESS_EXTR_MEM_END_ADDR field.
	AXI_DMA_EXTR_MEM_END_ADDR_ACCESS_EXTR_MEM_END_ADDR_Pos = 0x0
	// Bit mask of ACCESS_EXTR_MEM_END_ADDR field.
	AXI_DMA_EXTR_MEM_END_ADDR_ACCESS_EXTR_MEM_END_ADDR_Msk = 0xffffffff

	// IN_RESET_AVAIL_CH0: The rx channel 0 reset valid_flag register.
	// Position of IN_RESET_AVAIL_CH field.
	AXI_DMA_IN_RESET_AVAIL_CH_IN_RESET_AVAIL_CH_Pos = 0x0
	// Bit mask of IN_RESET_AVAIL_CH field.
	AXI_DMA_IN_RESET_AVAIL_CH_IN_RESET_AVAIL_CH_Msk = 0x1
	// Bit IN_RESET_AVAIL_CH.
	AXI_DMA_IN_RESET_AVAIL_CH_IN_RESET_AVAIL_CH = 0x1

	// OUT_RESET_AVAIL_CH0: The tx channel 0 reset valid_flag register.
	// Position of OUT_RESET_AVAIL_CH field.
	AXI_DMA_OUT_RESET_AVAIL_CH_OUT_RESET_AVAIL_CH_Pos = 0x0
	// Bit mask of OUT_RESET_AVAIL_CH field.
	AXI_DMA_OUT_RESET_AVAIL_CH_OUT_RESET_AVAIL_CH_Msk = 0x1
	// Bit OUT_RESET_AVAIL_CH.
	AXI_DMA_OUT_RESET_AVAIL_CH_OUT_RESET_AVAIL_CH = 0x1

	// MISC_CONF: MISC register
	// Position of AXIM_RST_WR_INTER field.
	AXI_DMA_MISC_CONF_AXIM_RST_WR_INTER_Pos = 0x0
	// Bit mask of AXIM_RST_WR_INTER field.
	AXI_DMA_MISC_CONF_AXIM_RST_WR_INTER_Msk = 0x1
	// Bit AXIM_RST_WR_INTER.
	AXI_DMA_MISC_CONF_AXIM_RST_WR_INTER = 0x1
	// Position of AXIM_RST_RD_INTER field.
	AXI_DMA_MISC_CONF_AXIM_RST_RD_INTER_Pos = 0x1
	// Bit mask of AXIM_RST_RD_INTER field.
	AXI_DMA_MISC_CONF_AXIM_RST_RD_INTER_Msk = 0x2
	// Bit AXIM_RST_RD_INTER.
	AXI_DMA_MISC_CONF_AXIM_RST_RD_INTER = 0x2
	// Position of ARB_PRI_DIS field.
	AXI_DMA_MISC_CONF_ARB_PRI_DIS_Pos = 0x3
	// Bit mask of ARB_PRI_DIS field.
	AXI_DMA_MISC_CONF_ARB_PRI_DIS_Msk = 0x8
	// Bit ARB_PRI_DIS.
	AXI_DMA_MISC_CONF_ARB_PRI_DIS = 0x8
	// Position of CLK_EN field.
	AXI_DMA_MISC_CONF_CLK_EN_Pos = 0x4
	// Bit mask of CLK_EN field.
	AXI_DMA_MISC_CONF_CLK_EN_Msk = 0x10
	// Bit CLK_EN.
	AXI_DMA_MISC_CONF_CLK_EN = 0x10

	// RDN_RESULT: reserved
	// Position of RDN_ENA field.
	AXI_DMA_RDN_RESULT_RDN_ENA_Pos = 0x0
	// Bit mask of RDN_ENA field.
	AXI_DMA_RDN_RESULT_RDN_ENA_Msk = 0x1
	// Bit RDN_ENA.
	AXI_DMA_RDN_RESULT_RDN_ENA = 0x1
	// Position of RDN_RESULT field.
	AXI_DMA_RDN_RESULT_RDN_RESULT_Pos = 0x1
	// Bit mask of RDN_RESULT field.
	AXI_DMA_RDN_RESULT_RDN_RESULT_Msk = 0x2
	// Bit RDN_RESULT.
	AXI_DMA_RDN_RESULT_RDN_RESULT = 0x2

	// RDN_ECO_HIGH: reserved
	// Position of RDN_ECO_HIGH field.
	AXI_DMA_RDN_ECO_HIGH_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of RDN_ECO_HIGH field.
	AXI_DMA_RDN_ECO_HIGH_RDN_ECO_HIGH_Msk = 0xffffffff

	// RDN_ECO_LOW: reserved
	// Position of RDN_ECO_LOW field.
	AXI_DMA_RDN_ECO_LOW_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of RDN_ECO_LOW field.
	AXI_DMA_RDN_ECO_LOW_RDN_ECO_LOW_Msk = 0xffffffff

	// WRESP_CNT: AXI wr responce cnt register.
	// Position of WRESP_CNT field.
	AXI_DMA_WRESP_CNT_WRESP_CNT_Pos = 0x0
	// Bit mask of WRESP_CNT field.
	AXI_DMA_WRESP_CNT_WRESP_CNT_Msk = 0xf

	// RRESP_CNT: AXI wr responce cnt register.
	// Position of RRESP_CNT field.
	AXI_DMA_RRESP_CNT_RRESP_CNT_Pos = 0x0
	// Bit mask of RRESP_CNT field.
	AXI_DMA_RRESP_CNT_RRESP_CNT_Msk = 0xf

	// INFIFO_STATUS1_CH0: Receive FIFO status of Rx channel 0
	// Position of L1INFIFO_CNT_CH field.
	AXI_DMA_INFIFO_STATUS1_CH_L1INFIFO_CNT_CH_Pos = 0x0
	// Bit mask of L1INFIFO_CNT_CH field.
	AXI_DMA_INFIFO_STATUS1_CH_L1INFIFO_CNT_CH_Msk = 0x3f
	// Position of L2INFIFO_CNT_CH field.
	AXI_DMA_INFIFO_STATUS1_CH_L2INFIFO_CNT_CH_Pos = 0x6
	// Bit mask of L2INFIFO_CNT_CH field.
	AXI_DMA_INFIFO_STATUS1_CH_L2INFIFO_CNT_CH_Msk = 0x3c0

	// OUTFIFO_STATUS1_CH0: Receive FIFO status of Tx channel 0
	// Position of L1OUTFIFO_CNT_CH field.
	AXI_DMA_OUTFIFO_STATUS1_CH_L1OUTFIFO_CNT_CH_Pos = 0x0
	// Bit mask of L1OUTFIFO_CNT_CH field.
	AXI_DMA_OUTFIFO_STATUS1_CH_L1OUTFIFO_CNT_CH_Msk = 0x3f
	// Position of L2OUTFIFO_CNT_CH field.
	AXI_DMA_OUTFIFO_STATUS1_CH_L2OUTFIFO_CNT_CH_Pos = 0x6
	// Bit mask of L2OUTFIFO_CNT_CH field.
	AXI_DMA_OUTFIFO_STATUS1_CH_L2OUTFIFO_CNT_CH_Msk = 0x3c0

	// DATE: Version control register
	// Position of DATE field.
	AXI_DMA_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	AXI_DMA_DATE_DATE_Msk = 0xffffffff
)

// Constants for BITSCRAMBLER: BITSCRAMBLER Peripheral
const (
	// TX_INST_CFG0: Control and configuration registers
	// Position of TX_INST_IDX field.
	BITSCRAMBLER_TX_INST_CFG0_TX_INST_IDX_Pos = 0x0
	// Bit mask of TX_INST_IDX field.
	BITSCRAMBLER_TX_INST_CFG0_TX_INST_IDX_Msk = 0x7
	// Position of TX_INST_POS field.
	BITSCRAMBLER_TX_INST_CFG0_TX_INST_POS_Pos = 0x3
	// Bit mask of TX_INST_POS field.
	BITSCRAMBLER_TX_INST_CFG0_TX_INST_POS_Msk = 0x78

	// TX_INST_CFG1: Control and configuration registers
	// Position of TX_INST field.
	BITSCRAMBLER_TX_INST_CFG1_TX_INST_Pos = 0x0
	// Bit mask of TX_INST field.
	BITSCRAMBLER_TX_INST_CFG1_TX_INST_Msk = 0xffffffff

	// RX_INST_CFG0: Control and configuration registers
	// Position of RX_INST_IDX field.
	BITSCRAMBLER_RX_INST_CFG0_RX_INST_IDX_Pos = 0x0
	// Bit mask of RX_INST_IDX field.
	BITSCRAMBLER_RX_INST_CFG0_RX_INST_IDX_Msk = 0x7
	// Position of RX_INST_POS field.
	BITSCRAMBLER_RX_INST_CFG0_RX_INST_POS_Pos = 0x3
	// Bit mask of RX_INST_POS field.
	BITSCRAMBLER_RX_INST_CFG0_RX_INST_POS_Msk = 0x78

	// RX_INST_CFG1: Control and configuration registers
	// Position of RX_INST field.
	BITSCRAMBLER_RX_INST_CFG1_RX_INST_Pos = 0x0
	// Bit mask of RX_INST field.
	BITSCRAMBLER_RX_INST_CFG1_RX_INST_Msk = 0xffffffff

	// TX_LUT_CFG0: Control and configuration registers
	// Position of TX_LUT_IDX field.
	BITSCRAMBLER_TX_LUT_CFG0_TX_LUT_IDX_Pos = 0x0
	// Bit mask of TX_LUT_IDX field.
	BITSCRAMBLER_TX_LUT_CFG0_TX_LUT_IDX_Msk = 0x7ff
	// Position of TX_LUT_MODE field.
	BITSCRAMBLER_TX_LUT_CFG0_TX_LUT_MODE_Pos = 0xb
	// Bit mask of TX_LUT_MODE field.
	BITSCRAMBLER_TX_LUT_CFG0_TX_LUT_MODE_Msk = 0x1800

	// TX_LUT_CFG1: Control and configuration registers
	// Position of TX_LUT field.
	BITSCRAMBLER_TX_LUT_CFG1_TX_LUT_Pos = 0x0
	// Bit mask of TX_LUT field.
	BITSCRAMBLER_TX_LUT_CFG1_TX_LUT_Msk = 0xffffffff

	// RX_LUT_CFG0: Control and configuration registers
	// Position of RX_LUT_IDX field.
	BITSCRAMBLER_RX_LUT_CFG0_RX_LUT_IDX_Pos = 0x0
	// Bit mask of RX_LUT_IDX field.
	BITSCRAMBLER_RX_LUT_CFG0_RX_LUT_IDX_Msk = 0x7ff
	// Position of RX_LUT_MODE field.
	BITSCRAMBLER_RX_LUT_CFG0_RX_LUT_MODE_Pos = 0xb
	// Bit mask of RX_LUT_MODE field.
	BITSCRAMBLER_RX_LUT_CFG0_RX_LUT_MODE_Msk = 0x1800

	// RX_LUT_CFG1: Control and configuration registers
	// Position of RX_LUT field.
	BITSCRAMBLER_RX_LUT_CFG1_RX_LUT_Pos = 0x0
	// Bit mask of RX_LUT field.
	BITSCRAMBLER_RX_LUT_CFG1_RX_LUT_Msk = 0xffffffff

	// TX_TAILING_BITS: Control and configuration registers
	// Position of TX_TAILING_BITS field.
	BITSCRAMBLER_TX_TAILING_BITS_TX_TAILING_BITS_Pos = 0x0
	// Bit mask of TX_TAILING_BITS field.
	BITSCRAMBLER_TX_TAILING_BITS_TX_TAILING_BITS_Msk = 0xffff

	// RX_TAILING_BITS: Control and configuration registers
	// Position of RX_TAILING_BITS field.
	BITSCRAMBLER_RX_TAILING_BITS_RX_TAILING_BITS_Pos = 0x0
	// Bit mask of RX_TAILING_BITS field.
	BITSCRAMBLER_RX_TAILING_BITS_RX_TAILING_BITS_Msk = 0xffff

	// TX_CTRL: Control and configuration registers
	// Position of TX_ENA field.
	BITSCRAMBLER_TX_CTRL_TX_ENA_Pos = 0x0
	// Bit mask of TX_ENA field.
	BITSCRAMBLER_TX_CTRL_TX_ENA_Msk = 0x1
	// Bit TX_ENA.
	BITSCRAMBLER_TX_CTRL_TX_ENA = 0x1
	// Position of TX_PAUSE field.
	BITSCRAMBLER_TX_CTRL_TX_PAUSE_Pos = 0x1
	// Bit mask of TX_PAUSE field.
	BITSCRAMBLER_TX_CTRL_TX_PAUSE_Msk = 0x2
	// Bit TX_PAUSE.
	BITSCRAMBLER_TX_CTRL_TX_PAUSE = 0x2
	// Position of TX_HALT field.
	BITSCRAMBLER_TX_CTRL_TX_HALT_Pos = 0x2
	// Bit mask of TX_HALT field.
	BITSCRAMBLER_TX_CTRL_TX_HALT_Msk = 0x4
	// Bit TX_HALT.
	BITSCRAMBLER_TX_CTRL_TX_HALT = 0x4
	// Position of TX_EOF_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_EOF_MODE_Pos = 0x3
	// Bit mask of TX_EOF_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_EOF_MODE_Msk = 0x8
	// Bit TX_EOF_MODE.
	BITSCRAMBLER_TX_CTRL_TX_EOF_MODE = 0x8
	// Position of TX_COND_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_COND_MODE_Pos = 0x4
	// Bit mask of TX_COND_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_COND_MODE_Msk = 0x10
	// Bit TX_COND_MODE.
	BITSCRAMBLER_TX_CTRL_TX_COND_MODE = 0x10
	// Position of TX_FETCH_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_FETCH_MODE_Pos = 0x5
	// Bit mask of TX_FETCH_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_FETCH_MODE_Msk = 0x20
	// Bit TX_FETCH_MODE.
	BITSCRAMBLER_TX_CTRL_TX_FETCH_MODE = 0x20
	// Position of TX_HALT_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_HALT_MODE_Pos = 0x6
	// Bit mask of TX_HALT_MODE field.
	BITSCRAMBLER_TX_CTRL_TX_HALT_MODE_Msk = 0x40
	// Bit TX_HALT_MODE.
	BITSCRAMBLER_TX_CTRL_TX_HALT_MODE = 0x40
	// Position of TX_RD_DUMMY field.
	BITSCRAMBLER_TX_CTRL_TX_RD_DUMMY_Pos = 0x7
	// Bit mask of TX_RD_DUMMY field.
	BITSCRAMBLER_TX_CTRL_TX_RD_DUMMY_Msk = 0x80
	// Bit TX_RD_DUMMY.
	BITSCRAMBLER_TX_CTRL_TX_RD_DUMMY = 0x80
	// Position of TX_FIFO_RST field.
	BITSCRAMBLER_TX_CTRL_TX_FIFO_RST_Pos = 0x8
	// Bit mask of TX_FIFO_RST field.
	BITSCRAMBLER_TX_CTRL_TX_FIFO_RST_Msk = 0x100
	// Bit TX_FIFO_RST.
	BITSCRAMBLER_TX_CTRL_TX_FIFO_RST = 0x100

	// RX_CTRL: Control and configuration registers
	// Position of RX_ENA field.
	BITSCRAMBLER_RX_CTRL_RX_ENA_Pos = 0x0
	// Bit mask of RX_ENA field.
	BITSCRAMBLER_RX_CTRL_RX_ENA_Msk = 0x1
	// Bit RX_ENA.
	BITSCRAMBLER_RX_CTRL_RX_ENA = 0x1
	// Position of RX_PAUSE field.
	BITSCRAMBLER_RX_CTRL_RX_PAUSE_Pos = 0x1
	// Bit mask of RX_PAUSE field.
	BITSCRAMBLER_RX_CTRL_RX_PAUSE_Msk = 0x2
	// Bit RX_PAUSE.
	BITSCRAMBLER_RX_CTRL_RX_PAUSE = 0x2
	// Position of RX_HALT field.
	BITSCRAMBLER_RX_CTRL_RX_HALT_Pos = 0x2
	// Bit mask of RX_HALT field.
	BITSCRAMBLER_RX_CTRL_RX_HALT_Msk = 0x4
	// Bit RX_HALT.
	BITSCRAMBLER_RX_CTRL_RX_HALT = 0x4
	// Position of RX_EOF_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_EOF_MODE_Pos = 0x3
	// Bit mask of RX_EOF_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_EOF_MODE_Msk = 0x8
	// Bit RX_EOF_MODE.
	BITSCRAMBLER_RX_CTRL_RX_EOF_MODE = 0x8
	// Position of RX_COND_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_COND_MODE_Pos = 0x4
	// Bit mask of RX_COND_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_COND_MODE_Msk = 0x10
	// Bit RX_COND_MODE.
	BITSCRAMBLER_RX_CTRL_RX_COND_MODE = 0x10
	// Position of RX_FETCH_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_FETCH_MODE_Pos = 0x5
	// Bit mask of RX_FETCH_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_FETCH_MODE_Msk = 0x20
	// Bit RX_FETCH_MODE.
	BITSCRAMBLER_RX_CTRL_RX_FETCH_MODE = 0x20
	// Position of RX_HALT_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_HALT_MODE_Pos = 0x6
	// Bit mask of RX_HALT_MODE field.
	BITSCRAMBLER_RX_CTRL_RX_HALT_MODE_Msk = 0x40
	// Bit RX_HALT_MODE.
	BITSCRAMBLER_RX_CTRL_RX_HALT_MODE = 0x40
	// Position of RX_RD_DUMMY field.
	BITSCRAMBLER_RX_CTRL_RX_RD_DUMMY_Pos = 0x7
	// Bit mask of RX_RD_DUMMY field.
	BITSCRAMBLER_RX_CTRL_RX_RD_DUMMY_Msk = 0x80
	// Bit RX_RD_DUMMY.
	BITSCRAMBLER_RX_CTRL_RX_RD_DUMMY = 0x80
	// Position of RX_FIFO_RST field.
	BITSCRAMBLER_RX_CTRL_RX_FIFO_RST_Pos = 0x8
	// Bit mask of RX_FIFO_RST field.
	BITSCRAMBLER_RX_CTRL_RX_FIFO_RST_Msk = 0x100
	// Bit RX_FIFO_RST.
	BITSCRAMBLER_RX_CTRL_RX_FIFO_RST = 0x100

	// TX_STATE: Status registers
	// Position of TX_IN_IDLE field.
	BITSCRAMBLER_TX_STATE_TX_IN_IDLE_Pos = 0x0
	// Bit mask of TX_IN_IDLE field.
	BITSCRAMBLER_TX_STATE_TX_IN_IDLE_Msk = 0x1
	// Bit TX_IN_IDLE.
	BITSCRAMBLER_TX_STATE_TX_IN_IDLE = 0x1
	// Position of TX_IN_RUN field.
	BITSCRAMBLER_TX_STATE_TX_IN_RUN_Pos = 0x1
	// Bit mask of TX_IN_RUN field.
	BITSCRAMBLER_TX_STATE_TX_IN_RUN_Msk = 0x2
	// Bit TX_IN_RUN.
	BITSCRAMBLER_TX_STATE_TX_IN_RUN = 0x2
	// Position of TX_IN_WAIT field.
	BITSCRAMBLER_TX_STATE_TX_IN_WAIT_Pos = 0x2
	// Bit mask of TX_IN_WAIT field.
	BITSCRAMBLER_TX_STATE_TX_IN_WAIT_Msk = 0x4
	// Bit TX_IN_WAIT.
	BITSCRAMBLER_TX_STATE_TX_IN_WAIT = 0x4
	// Position of TX_IN_PAUSE field.
	BITSCRAMBLER_TX_STATE_TX_IN_PAUSE_Pos = 0x3
	// Bit mask of TX_IN_PAUSE field.
	BITSCRAMBLER_TX_STATE_TX_IN_PAUSE_Msk = 0x8
	// Bit TX_IN_PAUSE.
	BITSCRAMBLER_TX_STATE_TX_IN_PAUSE = 0x8
	// Position of TX_FIFO_EMPTY field.
	BITSCRAMBLER_TX_STATE_TX_FIFO_EMPTY_Pos = 0x4
	// Bit mask of TX_FIFO_EMPTY field.
	BITSCRAMBLER_TX_STATE_TX_FIFO_EMPTY_Msk = 0x10
	// Bit TX_FIFO_EMPTY.
	BITSCRAMBLER_TX_STATE_TX_FIFO_EMPTY = 0x10
	// Position of TX_EOF_GET_CNT field.
	BITSCRAMBLER_TX_STATE_TX_EOF_GET_CNT_Pos = 0x10
	// Bit mask of TX_EOF_GET_CNT field.
	BITSCRAMBLER_TX_STATE_TX_EOF_GET_CNT_Msk = 0x3fff0000
	// Position of TX_EOF_OVERLOAD field.
	BITSCRAMBLER_TX_STATE_TX_EOF_OVERLOAD_Pos = 0x1e
	// Bit mask of TX_EOF_OVERLOAD field.
	BITSCRAMBLER_TX_STATE_TX_EOF_OVERLOAD_Msk = 0x40000000
	// Bit TX_EOF_OVERLOAD.
	BITSCRAMBLER_TX_STATE_TX_EOF_OVERLOAD = 0x40000000
	// Position of TX_EOF_TRACE_CLR field.
	BITSCRAMBLER_TX_STATE_TX_EOF_TRACE_CLR_Pos = 0x1f
	// Bit mask of TX_EOF_TRACE_CLR field.
	BITSCRAMBLER_TX_STATE_TX_EOF_TRACE_CLR_Msk = 0x80000000
	// Bit TX_EOF_TRACE_CLR.
	BITSCRAMBLER_TX_STATE_TX_EOF_TRACE_CLR = 0x80000000

	// RX_STATE: Status registers
	// Position of RX_IN_IDLE field.
	BITSCRAMBLER_RX_STATE_RX_IN_IDLE_Pos = 0x0
	// Bit mask of RX_IN_IDLE field.
	BITSCRAMBLER_RX_STATE_RX_IN_IDLE_Msk = 0x1
	// Bit RX_IN_IDLE.
	BITSCRAMBLER_RX_STATE_RX_IN_IDLE = 0x1
	// Position of RX_IN_RUN field.
	BITSCRAMBLER_RX_STATE_RX_IN_RUN_Pos = 0x1
	// Bit mask of RX_IN_RUN field.
	BITSCRAMBLER_RX_STATE_RX_IN_RUN_Msk = 0x2
	// Bit RX_IN_RUN.
	BITSCRAMBLER_RX_STATE_RX_IN_RUN = 0x2
	// Position of RX_IN_WAIT field.
	BITSCRAMBLER_RX_STATE_RX_IN_WAIT_Pos = 0x2
	// Bit mask of RX_IN_WAIT field.
	BITSCRAMBLER_RX_STATE_RX_IN_WAIT_Msk = 0x4
	// Bit RX_IN_WAIT.
	BITSCRAMBLER_RX_STATE_RX_IN_WAIT = 0x4
	// Position of RX_IN_PAUSE field.
	BITSCRAMBLER_RX_STATE_RX_IN_PAUSE_Pos = 0x3
	// Bit mask of RX_IN_PAUSE field.
	BITSCRAMBLER_RX_STATE_RX_IN_PAUSE_Msk = 0x8
	// Bit RX_IN_PAUSE.
	BITSCRAMBLER_RX_STATE_RX_IN_PAUSE = 0x8
	// Position of RX_FIFO_FULL field.
	BITSCRAMBLER_RX_STATE_RX_FIFO_FULL_Pos = 0x4
	// Bit mask of RX_FIFO_FULL field.
	BITSCRAMBLER_RX_STATE_RX_FIFO_FULL_Msk = 0x10
	// Bit RX_FIFO_FULL.
	BITSCRAMBLER_RX_STATE_RX_FIFO_FULL = 0x10
	// Position of RX_EOF_GET_CNT field.
	BITSCRAMBLER_RX_STATE_RX_EOF_GET_CNT_Pos = 0x10
	// Bit mask of RX_EOF_GET_CNT field.
	BITSCRAMBLER_RX_STATE_RX_EOF_GET_CNT_Msk = 0x3fff0000
	// Position of RX_EOF_OVERLOAD field.
	BITSCRAMBLER_RX_STATE_RX_EOF_OVERLOAD_Pos = 0x1e
	// Bit mask of RX_EOF_OVERLOAD field.
	BITSCRAMBLER_RX_STATE_RX_EOF_OVERLOAD_Msk = 0x40000000
	// Bit RX_EOF_OVERLOAD.
	BITSCRAMBLER_RX_STATE_RX_EOF_OVERLOAD = 0x40000000
	// Position of RX_EOF_TRACE_CLR field.
	BITSCRAMBLER_RX_STATE_RX_EOF_TRACE_CLR_Pos = 0x1f
	// Bit mask of RX_EOF_TRACE_CLR field.
	BITSCRAMBLER_RX_STATE_RX_EOF_TRACE_CLR_Msk = 0x80000000
	// Bit RX_EOF_TRACE_CLR.
	BITSCRAMBLER_RX_STATE_RX_EOF_TRACE_CLR = 0x80000000

	// SYS: Control and configuration registers
	// Position of LOOP_MODE field.
	BITSCRAMBLER_SYS_LOOP_MODE_Pos = 0x0
	// Bit mask of LOOP_MODE field.
	BITSCRAMBLER_SYS_LOOP_MODE_Msk = 0x1
	// Bit LOOP_MODE.
	BITSCRAMBLER_SYS_LOOP_MODE = 0x1
	// Position of CLK_EN field.
	BITSCRAMBLER_SYS_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	BITSCRAMBLER_SYS_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	BITSCRAMBLER_SYS_CLK_EN = 0x80000000

	// VERSION: Control and configuration registers
	// Position of BITSCRAMBLER_VER field.
	BITSCRAMBLER_VERSION_BITSCRAMBLER_VER_Pos = 0x0
	// Bit mask of BITSCRAMBLER_VER field.
	BITSCRAMBLER_VERSION_BITSCRAMBLER_VER_Msk = 0xfffffff
)

// Constants for CACHE: CACHE Peripheral
const (
	// L1_ICACHE_CTRL: L1 instruction Cache(L1-ICache) control register
	// Position of L1_ICACHE_SHUT_IBUS0 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0_Pos = 0x0
	// Bit mask of L1_ICACHE_SHUT_IBUS0 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0_Msk = 0x1
	// Bit L1_ICACHE_SHUT_IBUS0.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS0 = 0x1
	// Position of L1_ICACHE_SHUT_IBUS1 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1_Pos = 0x1
	// Bit mask of L1_ICACHE_SHUT_IBUS1 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1_Msk = 0x2
	// Bit L1_ICACHE_SHUT_IBUS1.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS1 = 0x2
	// Position of L1_ICACHE_SHUT_IBUS2 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2_Pos = 0x2
	// Bit mask of L1_ICACHE_SHUT_IBUS2 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2_Msk = 0x4
	// Bit L1_ICACHE_SHUT_IBUS2.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS2 = 0x4
	// Position of L1_ICACHE_SHUT_IBUS3 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3_Pos = 0x3
	// Bit mask of L1_ICACHE_SHUT_IBUS3 field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3_Msk = 0x8
	// Bit L1_ICACHE_SHUT_IBUS3.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_SHUT_IBUS3 = 0x8
	// Position of L1_ICACHE_UNDEF_OP field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP_Pos = 0x8
	// Bit mask of L1_ICACHE_UNDEF_OP field.
	CACHE_L1_ICACHE_CTRL_L1_ICACHE_UNDEF_OP_Msk = 0xff00

	// L1_DCACHE_CTRL: L1 data Cache(L1-DCache) control register
	// Position of L1_DCACHE_SHUT_DBUS0 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS0_Pos = 0x0
	// Bit mask of L1_DCACHE_SHUT_DBUS0 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS0_Msk = 0x1
	// Bit L1_DCACHE_SHUT_DBUS0.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS0 = 0x1
	// Position of L1_DCACHE_SHUT_DBUS1 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS1_Pos = 0x1
	// Bit mask of L1_DCACHE_SHUT_DBUS1 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS1_Msk = 0x2
	// Bit L1_DCACHE_SHUT_DBUS1.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS1 = 0x2
	// Position of L1_DCACHE_SHUT_DBUS2 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS2_Pos = 0x2
	// Bit mask of L1_DCACHE_SHUT_DBUS2 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS2_Msk = 0x4
	// Bit L1_DCACHE_SHUT_DBUS2.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS2 = 0x4
	// Position of L1_DCACHE_SHUT_DBUS3 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS3_Pos = 0x3
	// Bit mask of L1_DCACHE_SHUT_DBUS3 field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS3_Msk = 0x8
	// Bit L1_DCACHE_SHUT_DBUS3.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DBUS3 = 0x8
	// Position of L1_DCACHE_SHUT_DMA field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DMA_Pos = 0x4
	// Bit mask of L1_DCACHE_SHUT_DMA field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DMA_Msk = 0x10
	// Bit L1_DCACHE_SHUT_DMA.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_SHUT_DMA = 0x10
	// Position of L1_DCACHE_UNDEF_OP field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_UNDEF_OP_Pos = 0x8
	// Bit mask of L1_DCACHE_UNDEF_OP field.
	CACHE_L1_DCACHE_CTRL_L1_DCACHE_UNDEF_OP_Msk = 0xff00

	// L1_BYPASS_CACHE_CONF: Bypass Cache configure register
	// Position of BYPASS_L1_ICACHE0_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN_Pos = 0x0
	// Bit mask of BYPASS_L1_ICACHE0_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN_Msk = 0x1
	// Bit BYPASS_L1_ICACHE0_EN.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE0_EN = 0x1
	// Position of BYPASS_L1_ICACHE1_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN_Pos = 0x1
	// Bit mask of BYPASS_L1_ICACHE1_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN_Msk = 0x2
	// Bit BYPASS_L1_ICACHE1_EN.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE1_EN = 0x2
	// Position of BYPASS_L1_ICACHE2_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN_Pos = 0x2
	// Bit mask of BYPASS_L1_ICACHE2_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN_Msk = 0x4
	// Bit BYPASS_L1_ICACHE2_EN.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE2_EN = 0x4
	// Position of BYPASS_L1_ICACHE3_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN_Pos = 0x3
	// Bit mask of BYPASS_L1_ICACHE3_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN_Msk = 0x8
	// Bit BYPASS_L1_ICACHE3_EN.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_ICACHE3_EN = 0x8
	// Position of BYPASS_L1_DCACHE_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN_Pos = 0x4
	// Bit mask of BYPASS_L1_DCACHE_EN field.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN_Msk = 0x10
	// Bit BYPASS_L1_DCACHE_EN.
	CACHE_L1_BYPASS_CACHE_CONF_BYPASS_L1_DCACHE_EN = 0x10

	// L1_CACHE_ATOMIC_CONF: L1 Cache atomic feature configure register
	// Position of L1_DCACHE_ATOMIC_EN field.
	CACHE_L1_CACHE_ATOMIC_CONF_L1_DCACHE_ATOMIC_EN_Pos = 0x0
	// Bit mask of L1_DCACHE_ATOMIC_EN field.
	CACHE_L1_CACHE_ATOMIC_CONF_L1_DCACHE_ATOMIC_EN_Msk = 0x1
	// Bit L1_DCACHE_ATOMIC_EN.
	CACHE_L1_CACHE_ATOMIC_CONF_L1_DCACHE_ATOMIC_EN = 0x1

	// L1_ICACHE_CACHESIZE_CONF: L1 instruction Cache CacheSize mode configure register
	// Position of L1_ICACHE_CACHESIZE_256 field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256_Pos = 0x0
	// Bit mask of L1_ICACHE_CACHESIZE_256 field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256_Msk = 0x1
	// Bit L1_ICACHE_CACHESIZE_256.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256 = 0x1
	// Position of L1_ICACHE_CACHESIZE_512 field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512_Pos = 0x1
	// Bit mask of L1_ICACHE_CACHESIZE_512 field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512_Msk = 0x2
	// Bit L1_ICACHE_CACHESIZE_512.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512 = 0x2
	// Position of L1_ICACHE_CACHESIZE_1K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K_Pos = 0x2
	// Bit mask of L1_ICACHE_CACHESIZE_1K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K_Msk = 0x4
	// Bit L1_ICACHE_CACHESIZE_1K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1K = 0x4
	// Position of L1_ICACHE_CACHESIZE_2K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K_Pos = 0x3
	// Bit mask of L1_ICACHE_CACHESIZE_2K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K_Msk = 0x8
	// Bit L1_ICACHE_CACHESIZE_2K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_2K = 0x8
	// Position of L1_ICACHE_CACHESIZE_4K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K_Pos = 0x4
	// Bit mask of L1_ICACHE_CACHESIZE_4K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K_Msk = 0x10
	// Bit L1_ICACHE_CACHESIZE_4K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_4K = 0x10
	// Position of L1_ICACHE_CACHESIZE_8K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K_Pos = 0x5
	// Bit mask of L1_ICACHE_CACHESIZE_8K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K_Msk = 0x20
	// Bit L1_ICACHE_CACHESIZE_8K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_8K = 0x20
	// Position of L1_ICACHE_CACHESIZE_16K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K_Pos = 0x6
	// Bit mask of L1_ICACHE_CACHESIZE_16K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K_Msk = 0x40
	// Bit L1_ICACHE_CACHESIZE_16K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_16K = 0x40
	// Position of L1_ICACHE_CACHESIZE_32K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K_Pos = 0x7
	// Bit mask of L1_ICACHE_CACHESIZE_32K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K_Msk = 0x80
	// Bit L1_ICACHE_CACHESIZE_32K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_32K = 0x80
	// Position of L1_ICACHE_CACHESIZE_64K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K_Pos = 0x8
	// Bit mask of L1_ICACHE_CACHESIZE_64K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K_Msk = 0x100
	// Bit L1_ICACHE_CACHESIZE_64K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_64K = 0x100
	// Position of L1_ICACHE_CACHESIZE_128K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K_Pos = 0x9
	// Bit mask of L1_ICACHE_CACHESIZE_128K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K_Msk = 0x200
	// Bit L1_ICACHE_CACHESIZE_128K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_128K = 0x200
	// Position of L1_ICACHE_CACHESIZE_256K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K_Pos = 0xa
	// Bit mask of L1_ICACHE_CACHESIZE_256K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K_Msk = 0x400
	// Bit L1_ICACHE_CACHESIZE_256K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_256K = 0x400
	// Position of L1_ICACHE_CACHESIZE_512K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K_Pos = 0xb
	// Bit mask of L1_ICACHE_CACHESIZE_512K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K_Msk = 0x800
	// Bit L1_ICACHE_CACHESIZE_512K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_512K = 0x800
	// Position of L1_ICACHE_CACHESIZE_1024K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K_Pos = 0xc
	// Bit mask of L1_ICACHE_CACHESIZE_1024K field.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K_Msk = 0x1000
	// Bit L1_ICACHE_CACHESIZE_1024K.
	CACHE_L1_ICACHE_CACHESIZE_CONF_L1_ICACHE_CACHESIZE_1024K = 0x1000

	// L1_ICACHE_BLOCKSIZE_CONF: L1 instruction Cache BlockSize mode configure register
	// Position of L1_ICACHE_BLOCKSIZE_8 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8_Pos = 0x0
	// Bit mask of L1_ICACHE_BLOCKSIZE_8 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8_Msk = 0x1
	// Bit L1_ICACHE_BLOCKSIZE_8.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_8 = 0x1
	// Position of L1_ICACHE_BLOCKSIZE_16 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16_Pos = 0x1
	// Bit mask of L1_ICACHE_BLOCKSIZE_16 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16_Msk = 0x2
	// Bit L1_ICACHE_BLOCKSIZE_16.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_16 = 0x2
	// Position of L1_ICACHE_BLOCKSIZE_32 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32_Pos = 0x2
	// Bit mask of L1_ICACHE_BLOCKSIZE_32 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32_Msk = 0x4
	// Bit L1_ICACHE_BLOCKSIZE_32.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_32 = 0x4
	// Position of L1_ICACHE_BLOCKSIZE_64 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64_Pos = 0x3
	// Bit mask of L1_ICACHE_BLOCKSIZE_64 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64_Msk = 0x8
	// Bit L1_ICACHE_BLOCKSIZE_64.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_64 = 0x8
	// Position of L1_ICACHE_BLOCKSIZE_128 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128_Pos = 0x4
	// Bit mask of L1_ICACHE_BLOCKSIZE_128 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128_Msk = 0x10
	// Bit L1_ICACHE_BLOCKSIZE_128.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_128 = 0x10
	// Position of L1_ICACHE_BLOCKSIZE_256 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256_Pos = 0x5
	// Bit mask of L1_ICACHE_BLOCKSIZE_256 field.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256_Msk = 0x20
	// Bit L1_ICACHE_BLOCKSIZE_256.
	CACHE_L1_ICACHE_BLOCKSIZE_CONF_L1_ICACHE_BLOCKSIZE_256 = 0x20

	// L1_DCACHE_CACHESIZE_CONF: L1 data Cache CacheSize mode configure register
	// Position of L1_DCACHE_CACHESIZE_256 field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256_Pos = 0x0
	// Bit mask of L1_DCACHE_CACHESIZE_256 field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256_Msk = 0x1
	// Bit L1_DCACHE_CACHESIZE_256.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256 = 0x1
	// Position of L1_DCACHE_CACHESIZE_512 field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512_Pos = 0x1
	// Bit mask of L1_DCACHE_CACHESIZE_512 field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512_Msk = 0x2
	// Bit L1_DCACHE_CACHESIZE_512.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512 = 0x2
	// Position of L1_DCACHE_CACHESIZE_1K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1K_Pos = 0x2
	// Bit mask of L1_DCACHE_CACHESIZE_1K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1K_Msk = 0x4
	// Bit L1_DCACHE_CACHESIZE_1K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1K = 0x4
	// Position of L1_DCACHE_CACHESIZE_2K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_2K_Pos = 0x3
	// Bit mask of L1_DCACHE_CACHESIZE_2K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_2K_Msk = 0x8
	// Bit L1_DCACHE_CACHESIZE_2K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_2K = 0x8
	// Position of L1_DCACHE_CACHESIZE_4K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_4K_Pos = 0x4
	// Bit mask of L1_DCACHE_CACHESIZE_4K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_4K_Msk = 0x10
	// Bit L1_DCACHE_CACHESIZE_4K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_4K = 0x10
	// Position of L1_DCACHE_CACHESIZE_8K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_8K_Pos = 0x5
	// Bit mask of L1_DCACHE_CACHESIZE_8K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_8K_Msk = 0x20
	// Bit L1_DCACHE_CACHESIZE_8K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_8K = 0x20
	// Position of L1_DCACHE_CACHESIZE_16K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_16K_Pos = 0x6
	// Bit mask of L1_DCACHE_CACHESIZE_16K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_16K_Msk = 0x40
	// Bit L1_DCACHE_CACHESIZE_16K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_16K = 0x40
	// Position of L1_DCACHE_CACHESIZE_32K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_32K_Pos = 0x7
	// Bit mask of L1_DCACHE_CACHESIZE_32K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_32K_Msk = 0x80
	// Bit L1_DCACHE_CACHESIZE_32K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_32K = 0x80
	// Position of L1_DCACHE_CACHESIZE_64K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_64K_Pos = 0x8
	// Bit mask of L1_DCACHE_CACHESIZE_64K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_64K_Msk = 0x100
	// Bit L1_DCACHE_CACHESIZE_64K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_64K = 0x100
	// Position of L1_DCACHE_CACHESIZE_128K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_128K_Pos = 0x9
	// Bit mask of L1_DCACHE_CACHESIZE_128K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_128K_Msk = 0x200
	// Bit L1_DCACHE_CACHESIZE_128K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_128K = 0x200
	// Position of L1_DCACHE_CACHESIZE_256K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256K_Pos = 0xa
	// Bit mask of L1_DCACHE_CACHESIZE_256K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256K_Msk = 0x400
	// Bit L1_DCACHE_CACHESIZE_256K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_256K = 0x400
	// Position of L1_DCACHE_CACHESIZE_512K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512K_Pos = 0xb
	// Bit mask of L1_DCACHE_CACHESIZE_512K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512K_Msk = 0x800
	// Bit L1_DCACHE_CACHESIZE_512K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_512K = 0x800
	// Position of L1_DCACHE_CACHESIZE_1024K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1024K_Pos = 0xc
	// Bit mask of L1_DCACHE_CACHESIZE_1024K field.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1024K_Msk = 0x1000
	// Bit L1_DCACHE_CACHESIZE_1024K.
	CACHE_L1_DCACHE_CACHESIZE_CONF_L1_DCACHE_CACHESIZE_1024K = 0x1000

	// L1_DCACHE_BLOCKSIZE_CONF: L1 data Cache BlockSize mode configure register
	// Position of L1_DCACHE_BLOCKSIZE_8 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_8_Pos = 0x0
	// Bit mask of L1_DCACHE_BLOCKSIZE_8 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_8_Msk = 0x1
	// Bit L1_DCACHE_BLOCKSIZE_8.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_8 = 0x1
	// Position of L1_DCACHE_BLOCKSIZE_16 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_16_Pos = 0x1
	// Bit mask of L1_DCACHE_BLOCKSIZE_16 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_16_Msk = 0x2
	// Bit L1_DCACHE_BLOCKSIZE_16.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_16 = 0x2
	// Position of L1_DCACHE_BLOCKSIZE_32 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_32_Pos = 0x2
	// Bit mask of L1_DCACHE_BLOCKSIZE_32 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_32_Msk = 0x4
	// Bit L1_DCACHE_BLOCKSIZE_32.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_32 = 0x4
	// Position of L1_DCACHE_BLOCKSIZE_64 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_64_Pos = 0x3
	// Bit mask of L1_DCACHE_BLOCKSIZE_64 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_64_Msk = 0x8
	// Bit L1_DCACHE_BLOCKSIZE_64.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_64 = 0x8
	// Position of L1_DCACHE_BLOCKSIZE_128 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_128_Pos = 0x4
	// Bit mask of L1_DCACHE_BLOCKSIZE_128 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_128_Msk = 0x10
	// Bit L1_DCACHE_BLOCKSIZE_128.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_128 = 0x10
	// Position of L1_DCACHE_BLOCKSIZE_256 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_256_Pos = 0x5
	// Bit mask of L1_DCACHE_BLOCKSIZE_256 field.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_256_Msk = 0x20
	// Bit L1_DCACHE_BLOCKSIZE_256.
	CACHE_L1_DCACHE_BLOCKSIZE_CONF_L1_DCACHE_BLOCKSIZE_256 = 0x20

	// L1_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register
	// Position of L1_ICACHE0_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP_Pos = 0x0
	// Bit mask of L1_ICACHE0_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP_Msk = 0x1
	// Bit L1_ICACHE0_WRAP.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE0_WRAP = 0x1
	// Position of L1_ICACHE1_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP_Pos = 0x1
	// Bit mask of L1_ICACHE1_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP_Msk = 0x2
	// Bit L1_ICACHE1_WRAP.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE1_WRAP = 0x2
	// Position of L1_ICACHE2_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP_Pos = 0x2
	// Bit mask of L1_ICACHE2_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP_Msk = 0x4
	// Bit L1_ICACHE2_WRAP.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE2_WRAP = 0x4
	// Position of L1_ICACHE3_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP_Pos = 0x3
	// Bit mask of L1_ICACHE3_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP_Msk = 0x8
	// Bit L1_ICACHE3_WRAP.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_ICACHE3_WRAP = 0x8
	// Position of L1_DCACHE_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_DCACHE_WRAP_Pos = 0x4
	// Bit mask of L1_DCACHE_WRAP field.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_DCACHE_WRAP_Msk = 0x10
	// Bit L1_DCACHE_WRAP.
	CACHE_L1_CACHE_WRAP_AROUND_CTRL_L1_DCACHE_WRAP = 0x10

	// L1_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register
	// Position of L1_ICACHE0_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON_Pos = 0x0
	// Bit mask of L1_ICACHE0_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON_Msk = 0x1
	// Bit L1_ICACHE0_TAG_MEM_FORCE_ON.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_ON = 0x1
	// Position of L1_ICACHE0_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD_Pos = 0x1
	// Bit mask of L1_ICACHE0_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD_Msk = 0x2
	// Bit L1_ICACHE0_TAG_MEM_FORCE_PD.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PD = 0x2
	// Position of L1_ICACHE0_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU_Pos = 0x2
	// Bit mask of L1_ICACHE0_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU_Msk = 0x4
	// Bit L1_ICACHE0_TAG_MEM_FORCE_PU.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE0_TAG_MEM_FORCE_PU = 0x4
	// Position of L1_ICACHE1_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON_Pos = 0x4
	// Bit mask of L1_ICACHE1_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON_Msk = 0x10
	// Bit L1_ICACHE1_TAG_MEM_FORCE_ON.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_ON = 0x10
	// Position of L1_ICACHE1_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD_Pos = 0x5
	// Bit mask of L1_ICACHE1_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD_Msk = 0x20
	// Bit L1_ICACHE1_TAG_MEM_FORCE_PD.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PD = 0x20
	// Position of L1_ICACHE1_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU_Pos = 0x6
	// Bit mask of L1_ICACHE1_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU_Msk = 0x40
	// Bit L1_ICACHE1_TAG_MEM_FORCE_PU.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE1_TAG_MEM_FORCE_PU = 0x40
	// Position of L1_ICACHE2_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON_Pos = 0x8
	// Bit mask of L1_ICACHE2_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON_Msk = 0x100
	// Bit L1_ICACHE2_TAG_MEM_FORCE_ON.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_ON = 0x100
	// Position of L1_ICACHE2_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD_Pos = 0x9
	// Bit mask of L1_ICACHE2_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD_Msk = 0x200
	// Bit L1_ICACHE2_TAG_MEM_FORCE_PD.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PD = 0x200
	// Position of L1_ICACHE2_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU_Pos = 0xa
	// Bit mask of L1_ICACHE2_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU_Msk = 0x400
	// Bit L1_ICACHE2_TAG_MEM_FORCE_PU.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE2_TAG_MEM_FORCE_PU = 0x400
	// Position of L1_ICACHE3_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON_Pos = 0xc
	// Bit mask of L1_ICACHE3_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON_Msk = 0x1000
	// Bit L1_ICACHE3_TAG_MEM_FORCE_ON.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_ON = 0x1000
	// Position of L1_ICACHE3_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD_Pos = 0xd
	// Bit mask of L1_ICACHE3_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD_Msk = 0x2000
	// Bit L1_ICACHE3_TAG_MEM_FORCE_PD.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PD = 0x2000
	// Position of L1_ICACHE3_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU_Pos = 0xe
	// Bit mask of L1_ICACHE3_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU_Msk = 0x4000
	// Bit L1_ICACHE3_TAG_MEM_FORCE_PU.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_ICACHE3_TAG_MEM_FORCE_PU = 0x4000
	// Position of L1_DCACHE_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_ON_Pos = 0x10
	// Bit mask of L1_DCACHE_TAG_MEM_FORCE_ON field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_ON_Msk = 0x10000
	// Bit L1_DCACHE_TAG_MEM_FORCE_ON.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_ON = 0x10000
	// Position of L1_DCACHE_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PD_Pos = 0x11
	// Bit mask of L1_DCACHE_TAG_MEM_FORCE_PD field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PD_Msk = 0x20000
	// Bit L1_DCACHE_TAG_MEM_FORCE_PD.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PD = 0x20000
	// Position of L1_DCACHE_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PU_Pos = 0x12
	// Bit mask of L1_DCACHE_TAG_MEM_FORCE_PU field.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PU_Msk = 0x40000
	// Bit L1_DCACHE_TAG_MEM_FORCE_PU.
	CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_L1_DCACHE_TAG_MEM_FORCE_PU = 0x40000

	// L1_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register
	// Position of L1_ICACHE0_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON_Pos = 0x0
	// Bit mask of L1_ICACHE0_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON_Msk = 0x1
	// Bit L1_ICACHE0_DATA_MEM_FORCE_ON.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_ON = 0x1
	// Position of L1_ICACHE0_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD_Pos = 0x1
	// Bit mask of L1_ICACHE0_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD_Msk = 0x2
	// Bit L1_ICACHE0_DATA_MEM_FORCE_PD.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PD = 0x2
	// Position of L1_ICACHE0_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU_Pos = 0x2
	// Bit mask of L1_ICACHE0_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU_Msk = 0x4
	// Bit L1_ICACHE0_DATA_MEM_FORCE_PU.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE0_DATA_MEM_FORCE_PU = 0x4
	// Position of L1_ICACHE1_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON_Pos = 0x4
	// Bit mask of L1_ICACHE1_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON_Msk = 0x10
	// Bit L1_ICACHE1_DATA_MEM_FORCE_ON.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_ON = 0x10
	// Position of L1_ICACHE1_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD_Pos = 0x5
	// Bit mask of L1_ICACHE1_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD_Msk = 0x20
	// Bit L1_ICACHE1_DATA_MEM_FORCE_PD.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PD = 0x20
	// Position of L1_ICACHE1_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU_Pos = 0x6
	// Bit mask of L1_ICACHE1_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU_Msk = 0x40
	// Bit L1_ICACHE1_DATA_MEM_FORCE_PU.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE1_DATA_MEM_FORCE_PU = 0x40
	// Position of L1_ICACHE2_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON_Pos = 0x8
	// Bit mask of L1_ICACHE2_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON_Msk = 0x100
	// Bit L1_ICACHE2_DATA_MEM_FORCE_ON.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_ON = 0x100
	// Position of L1_ICACHE2_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD_Pos = 0x9
	// Bit mask of L1_ICACHE2_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD_Msk = 0x200
	// Bit L1_ICACHE2_DATA_MEM_FORCE_PD.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PD = 0x200
	// Position of L1_ICACHE2_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU_Pos = 0xa
	// Bit mask of L1_ICACHE2_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU_Msk = 0x400
	// Bit L1_ICACHE2_DATA_MEM_FORCE_PU.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE2_DATA_MEM_FORCE_PU = 0x400
	// Position of L1_ICACHE3_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON_Pos = 0xc
	// Bit mask of L1_ICACHE3_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON_Msk = 0x1000
	// Bit L1_ICACHE3_DATA_MEM_FORCE_ON.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_ON = 0x1000
	// Position of L1_ICACHE3_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD_Pos = 0xd
	// Bit mask of L1_ICACHE3_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD_Msk = 0x2000
	// Bit L1_ICACHE3_DATA_MEM_FORCE_PD.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PD = 0x2000
	// Position of L1_ICACHE3_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU_Pos = 0xe
	// Bit mask of L1_ICACHE3_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU_Msk = 0x4000
	// Bit L1_ICACHE3_DATA_MEM_FORCE_PU.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_ICACHE3_DATA_MEM_FORCE_PU = 0x4000
	// Position of L1_DCACHE_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_ON_Pos = 0x10
	// Bit mask of L1_DCACHE_DATA_MEM_FORCE_ON field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_ON_Msk = 0x10000
	// Bit L1_DCACHE_DATA_MEM_FORCE_ON.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_ON = 0x10000
	// Position of L1_DCACHE_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PD_Pos = 0x11
	// Bit mask of L1_DCACHE_DATA_MEM_FORCE_PD field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PD_Msk = 0x20000
	// Bit L1_DCACHE_DATA_MEM_FORCE_PD.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PD = 0x20000
	// Position of L1_DCACHE_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PU_Pos = 0x12
	// Bit mask of L1_DCACHE_DATA_MEM_FORCE_PU field.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PU_Msk = 0x40000
	// Bit L1_DCACHE_DATA_MEM_FORCE_PU.
	CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_L1_DCACHE_DATA_MEM_FORCE_PU = 0x40000

	// L1_CACHE_FREEZE_CTRL: Cache Freeze control register
	// Position of L1_ICACHE0_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN_Pos = 0x0
	// Bit mask of L1_ICACHE0_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN_Msk = 0x1
	// Bit L1_ICACHE0_FREEZE_EN.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_EN = 0x1
	// Position of L1_ICACHE0_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE_Pos = 0x1
	// Bit mask of L1_ICACHE0_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE_Msk = 0x2
	// Bit L1_ICACHE0_FREEZE_MODE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_MODE = 0x2
	// Position of L1_ICACHE0_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE_Pos = 0x2
	// Bit mask of L1_ICACHE0_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE_Msk = 0x4
	// Bit L1_ICACHE0_FREEZE_DONE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE0_FREEZE_DONE = 0x4
	// Position of L1_ICACHE1_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN_Pos = 0x4
	// Bit mask of L1_ICACHE1_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN_Msk = 0x10
	// Bit L1_ICACHE1_FREEZE_EN.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_EN = 0x10
	// Position of L1_ICACHE1_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE_Pos = 0x5
	// Bit mask of L1_ICACHE1_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE_Msk = 0x20
	// Bit L1_ICACHE1_FREEZE_MODE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_MODE = 0x20
	// Position of L1_ICACHE1_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE_Pos = 0x6
	// Bit mask of L1_ICACHE1_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE_Msk = 0x40
	// Bit L1_ICACHE1_FREEZE_DONE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE1_FREEZE_DONE = 0x40
	// Position of L1_ICACHE2_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN_Pos = 0x8
	// Bit mask of L1_ICACHE2_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN_Msk = 0x100
	// Bit L1_ICACHE2_FREEZE_EN.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_EN = 0x100
	// Position of L1_ICACHE2_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE_Pos = 0x9
	// Bit mask of L1_ICACHE2_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE_Msk = 0x200
	// Bit L1_ICACHE2_FREEZE_MODE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_MODE = 0x200
	// Position of L1_ICACHE2_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE_Pos = 0xa
	// Bit mask of L1_ICACHE2_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE_Msk = 0x400
	// Bit L1_ICACHE2_FREEZE_DONE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE2_FREEZE_DONE = 0x400
	// Position of L1_ICACHE3_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN_Pos = 0xc
	// Bit mask of L1_ICACHE3_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN_Msk = 0x1000
	// Bit L1_ICACHE3_FREEZE_EN.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_EN = 0x1000
	// Position of L1_ICACHE3_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE_Pos = 0xd
	// Bit mask of L1_ICACHE3_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE_Msk = 0x2000
	// Bit L1_ICACHE3_FREEZE_MODE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_MODE = 0x2000
	// Position of L1_ICACHE3_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE_Pos = 0xe
	// Bit mask of L1_ICACHE3_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE_Msk = 0x4000
	// Bit L1_ICACHE3_FREEZE_DONE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_ICACHE3_FREEZE_DONE = 0x4000
	// Position of L1_DCACHE_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_EN_Pos = 0x10
	// Bit mask of L1_DCACHE_FREEZE_EN field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_EN_Msk = 0x10000
	// Bit L1_DCACHE_FREEZE_EN.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_EN = 0x10000
	// Position of L1_DCACHE_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_MODE_Pos = 0x11
	// Bit mask of L1_DCACHE_FREEZE_MODE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_MODE_Msk = 0x20000
	// Bit L1_DCACHE_FREEZE_MODE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_MODE = 0x20000
	// Position of L1_DCACHE_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_DONE_Pos = 0x12
	// Bit mask of L1_DCACHE_FREEZE_DONE field.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_DONE_Msk = 0x40000
	// Bit L1_DCACHE_FREEZE_DONE.
	CACHE_L1_CACHE_FREEZE_CTRL_L1_DCACHE_FREEZE_DONE = 0x40000

	// L1_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register
	// Position of L1_ICACHE0_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN_Pos = 0x0
	// Bit mask of L1_ICACHE0_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN_Msk = 0x1
	// Bit L1_ICACHE0_DATA_MEM_RD_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_RD_EN = 0x1
	// Position of L1_ICACHE0_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN_Pos = 0x1
	// Bit mask of L1_ICACHE0_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN_Msk = 0x2
	// Bit L1_ICACHE0_DATA_MEM_WR_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE0_DATA_MEM_WR_EN = 0x2
	// Position of L1_ICACHE1_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN_Pos = 0x4
	// Bit mask of L1_ICACHE1_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN_Msk = 0x10
	// Bit L1_ICACHE1_DATA_MEM_RD_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_RD_EN = 0x10
	// Position of L1_ICACHE1_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN_Pos = 0x5
	// Bit mask of L1_ICACHE1_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN_Msk = 0x20
	// Bit L1_ICACHE1_DATA_MEM_WR_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE1_DATA_MEM_WR_EN = 0x20
	// Position of L1_ICACHE2_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN_Pos = 0x8
	// Bit mask of L1_ICACHE2_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN_Msk = 0x100
	// Bit L1_ICACHE2_DATA_MEM_RD_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_RD_EN = 0x100
	// Position of L1_ICACHE2_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN_Pos = 0x9
	// Bit mask of L1_ICACHE2_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN_Msk = 0x200
	// Bit L1_ICACHE2_DATA_MEM_WR_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE2_DATA_MEM_WR_EN = 0x200
	// Position of L1_ICACHE3_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN_Pos = 0xc
	// Bit mask of L1_ICACHE3_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN_Msk = 0x1000
	// Bit L1_ICACHE3_DATA_MEM_RD_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_RD_EN = 0x1000
	// Position of L1_ICACHE3_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN_Pos = 0xd
	// Bit mask of L1_ICACHE3_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN_Msk = 0x2000
	// Bit L1_ICACHE3_DATA_MEM_WR_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_ICACHE3_DATA_MEM_WR_EN = 0x2000
	// Position of L1_DCACHE_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_RD_EN_Pos = 0x10
	// Bit mask of L1_DCACHE_DATA_MEM_RD_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_RD_EN_Msk = 0x10000
	// Bit L1_DCACHE_DATA_MEM_RD_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_RD_EN = 0x10000
	// Position of L1_DCACHE_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_WR_EN_Pos = 0x11
	// Bit mask of L1_DCACHE_DATA_MEM_WR_EN field.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_WR_EN_Msk = 0x20000
	// Bit L1_DCACHE_DATA_MEM_WR_EN.
	CACHE_L1_CACHE_DATA_MEM_ACS_CONF_L1_DCACHE_DATA_MEM_WR_EN = 0x20000

	// L1_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register
	// Position of L1_ICACHE0_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN_Pos = 0x0
	// Bit mask of L1_ICACHE0_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN_Msk = 0x1
	// Bit L1_ICACHE0_TAG_MEM_RD_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_RD_EN = 0x1
	// Position of L1_ICACHE0_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN_Pos = 0x1
	// Bit mask of L1_ICACHE0_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN_Msk = 0x2
	// Bit L1_ICACHE0_TAG_MEM_WR_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE0_TAG_MEM_WR_EN = 0x2
	// Position of L1_ICACHE1_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN_Pos = 0x4
	// Bit mask of L1_ICACHE1_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN_Msk = 0x10
	// Bit L1_ICACHE1_TAG_MEM_RD_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_RD_EN = 0x10
	// Position of L1_ICACHE1_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN_Pos = 0x5
	// Bit mask of L1_ICACHE1_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN_Msk = 0x20
	// Bit L1_ICACHE1_TAG_MEM_WR_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE1_TAG_MEM_WR_EN = 0x20
	// Position of L1_ICACHE2_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN_Pos = 0x8
	// Bit mask of L1_ICACHE2_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN_Msk = 0x100
	// Bit L1_ICACHE2_TAG_MEM_RD_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_RD_EN = 0x100
	// Position of L1_ICACHE2_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN_Pos = 0x9
	// Bit mask of L1_ICACHE2_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN_Msk = 0x200
	// Bit L1_ICACHE2_TAG_MEM_WR_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE2_TAG_MEM_WR_EN = 0x200
	// Position of L1_ICACHE3_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN_Pos = 0xc
	// Bit mask of L1_ICACHE3_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN_Msk = 0x1000
	// Bit L1_ICACHE3_TAG_MEM_RD_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_RD_EN = 0x1000
	// Position of L1_ICACHE3_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN_Pos = 0xd
	// Bit mask of L1_ICACHE3_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN_Msk = 0x2000
	// Bit L1_ICACHE3_TAG_MEM_WR_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_ICACHE3_TAG_MEM_WR_EN = 0x2000
	// Position of L1_DCACHE_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_RD_EN_Pos = 0x10
	// Bit mask of L1_DCACHE_TAG_MEM_RD_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_RD_EN_Msk = 0x10000
	// Bit L1_DCACHE_TAG_MEM_RD_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_RD_EN = 0x10000
	// Position of L1_DCACHE_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_WR_EN_Pos = 0x11
	// Bit mask of L1_DCACHE_TAG_MEM_WR_EN field.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_WR_EN_Msk = 0x20000
	// Bit L1_DCACHE_TAG_MEM_WR_EN.
	CACHE_L1_CACHE_TAG_MEM_ACS_CONF_L1_DCACHE_TAG_MEM_WR_EN = 0x20000

	// L1_ICACHE0_PRELOCK_CONF: L1 instruction Cache 0 prelock configure register
	// Position of L1_ICACHE0_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN_Pos = 0x0
	// Bit mask of L1_ICACHE0_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN_Msk = 0x1
	// Bit L1_ICACHE0_PRELOCK_SCT0_EN.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT0_EN = 0x1
	// Position of L1_ICACHE0_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN_Pos = 0x1
	// Bit mask of L1_ICACHE0_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN_Msk = 0x2
	// Bit L1_ICACHE0_PRELOCK_SCT1_EN.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_SCT1_EN = 0x2
	// Position of L1_ICACHE0_PRELOCK_RGID field.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID_Pos = 0x2
	// Bit mask of L1_ICACHE0_PRELOCK_RGID field.
	CACHE_L1_ICACHE0_PRELOCK_CONF_L1_ICACHE0_PRELOCK_RGID_Msk = 0x3c

	// L1_ICACHE0_PRELOCK_SCT0_ADDR: L1 instruction Cache 0 prelock section0 address configure register
	// Position of L1_ICACHE0_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_L1_ICACHE0_PRELOCK_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE0_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_L1_ICACHE0_PRELOCK_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE0_PRELOCK_SCT1_ADDR: L1 instruction Cache 0 prelock section1 address configure register
	// Position of L1_ICACHE0_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_L1_ICACHE0_PRELOCK_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE0_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_L1_ICACHE0_PRELOCK_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE0_PRELOCK_SCT_SIZE: L1 instruction Cache 0 prelock section size configure register
	// Position of L1_ICACHE0_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE0_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT0_SIZE_Msk = 0x3fff
	// Position of L1_ICACHE0_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE_Pos = 0x10
	// Bit mask of L1_ICACHE0_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_L1_ICACHE0_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000

	// L1_ICACHE1_PRELOCK_CONF: L1 instruction Cache 1 prelock configure register
	// Position of L1_ICACHE1_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN_Pos = 0x0
	// Bit mask of L1_ICACHE1_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN_Msk = 0x1
	// Bit L1_ICACHE1_PRELOCK_SCT0_EN.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT0_EN = 0x1
	// Position of L1_ICACHE1_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN_Pos = 0x1
	// Bit mask of L1_ICACHE1_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN_Msk = 0x2
	// Bit L1_ICACHE1_PRELOCK_SCT1_EN.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_SCT1_EN = 0x2
	// Position of L1_ICACHE1_PRELOCK_RGID field.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID_Pos = 0x2
	// Bit mask of L1_ICACHE1_PRELOCK_RGID field.
	CACHE_L1_ICACHE1_PRELOCK_CONF_L1_ICACHE1_PRELOCK_RGID_Msk = 0x3c

	// L1_ICACHE1_PRELOCK_SCT0_ADDR: L1 instruction Cache 1 prelock section0 address configure register
	// Position of L1_ICACHE1_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_L1_ICACHE1_PRELOCK_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE1_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_L1_ICACHE1_PRELOCK_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE1_PRELOCK_SCT1_ADDR: L1 instruction Cache 1 prelock section1 address configure register
	// Position of L1_ICACHE1_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_L1_ICACHE1_PRELOCK_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE1_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_L1_ICACHE1_PRELOCK_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE1_PRELOCK_SCT_SIZE: L1 instruction Cache 1 prelock section size configure register
	// Position of L1_ICACHE1_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE1_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT0_SIZE_Msk = 0x3fff
	// Position of L1_ICACHE1_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE_Pos = 0x10
	// Bit mask of L1_ICACHE1_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_L1_ICACHE1_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000

	// L1_ICACHE2_PRELOCK_CONF: L1 instruction Cache 2 prelock configure register
	// Position of L1_ICACHE2_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN_Pos = 0x0
	// Bit mask of L1_ICACHE2_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN_Msk = 0x1
	// Bit L1_ICACHE2_PRELOCK_SCT0_EN.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT0_EN = 0x1
	// Position of L1_ICACHE2_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN_Pos = 0x1
	// Bit mask of L1_ICACHE2_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN_Msk = 0x2
	// Bit L1_ICACHE2_PRELOCK_SCT1_EN.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_SCT1_EN = 0x2
	// Position of L1_ICACHE2_PRELOCK_RGID field.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID_Pos = 0x2
	// Bit mask of L1_ICACHE2_PRELOCK_RGID field.
	CACHE_L1_ICACHE2_PRELOCK_CONF_L1_ICACHE2_PRELOCK_RGID_Msk = 0x3c

	// L1_ICACHE2_PRELOCK_SCT0_ADDR: L1 instruction Cache 2 prelock section0 address configure register
	// Position of L1_ICACHE2_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_L1_ICACHE2_PRELOCK_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE2_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_L1_ICACHE2_PRELOCK_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE2_PRELOCK_SCT1_ADDR: L1 instruction Cache 2 prelock section1 address configure register
	// Position of L1_ICACHE2_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_L1_ICACHE2_PRELOCK_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE2_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_L1_ICACHE2_PRELOCK_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE2_PRELOCK_SCT_SIZE: L1 instruction Cache 2 prelock section size configure register
	// Position of L1_ICACHE2_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE2_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT0_SIZE_Msk = 0x3fff
	// Position of L1_ICACHE2_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE_Pos = 0x10
	// Bit mask of L1_ICACHE2_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_L1_ICACHE2_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000

	// L1_ICACHE3_PRELOCK_CONF: L1 instruction Cache 3 prelock configure register
	// Position of L1_ICACHE3_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN_Pos = 0x0
	// Bit mask of L1_ICACHE3_PRELOCK_SCT0_EN field.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN_Msk = 0x1
	// Bit L1_ICACHE3_PRELOCK_SCT0_EN.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT0_EN = 0x1
	// Position of L1_ICACHE3_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN_Pos = 0x1
	// Bit mask of L1_ICACHE3_PRELOCK_SCT1_EN field.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN_Msk = 0x2
	// Bit L1_ICACHE3_PRELOCK_SCT1_EN.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_SCT1_EN = 0x2
	// Position of L1_ICACHE3_PRELOCK_RGID field.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID_Pos = 0x2
	// Bit mask of L1_ICACHE3_PRELOCK_RGID field.
	CACHE_L1_ICACHE3_PRELOCK_CONF_L1_ICACHE3_PRELOCK_RGID_Msk = 0x3c

	// L1_ICACHE3_PRELOCK_SCT0_ADDR: L1 instruction Cache 3 prelock section0 address configure register
	// Position of L1_ICACHE3_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_L1_ICACHE3_PRELOCK_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE3_PRELOCK_SCT0_ADDR field.
	CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_L1_ICACHE3_PRELOCK_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE3_PRELOCK_SCT1_ADDR: L1 instruction Cache 3 prelock section1 address configure register
	// Position of L1_ICACHE3_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_L1_ICACHE3_PRELOCK_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE3_PRELOCK_SCT1_ADDR field.
	CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_L1_ICACHE3_PRELOCK_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE3_PRELOCK_SCT_SIZE: L1 instruction Cache 3 prelock section size configure register
	// Position of L1_ICACHE3_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE3_PRELOCK_SCT0_SIZE field.
	CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT0_SIZE_Msk = 0x3fff
	// Position of L1_ICACHE3_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE_Pos = 0x10
	// Bit mask of L1_ICACHE3_PRELOCK_SCT1_SIZE field.
	CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_L1_ICACHE3_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000

	// L1_DCACHE_PRELOCK_CONF: L1 data Cache prelock configure register
	// Position of L1_DCACHE_PRELOCK_SCT0_EN field.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT0_EN_Pos = 0x0
	// Bit mask of L1_DCACHE_PRELOCK_SCT0_EN field.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT0_EN_Msk = 0x1
	// Bit L1_DCACHE_PRELOCK_SCT0_EN.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT0_EN = 0x1
	// Position of L1_DCACHE_PRELOCK_SCT1_EN field.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT1_EN_Pos = 0x1
	// Bit mask of L1_DCACHE_PRELOCK_SCT1_EN field.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT1_EN_Msk = 0x2
	// Bit L1_DCACHE_PRELOCK_SCT1_EN.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_SCT1_EN = 0x2
	// Position of L1_DCACHE_PRELOCK_RGID field.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_RGID_Pos = 0x2
	// Bit mask of L1_DCACHE_PRELOCK_RGID field.
	CACHE_L1_DCACHE_PRELOCK_CONF_L1_DCACHE_PRELOCK_RGID_Msk = 0x3c

	// L1_DCACHE_PRELOCK_SCT0_ADDR: L1 data Cache prelock section0 address configure register
	// Position of L1_DCACHE_PRELOCK_SCT0_ADDR field.
	CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_L1_DCACHE_PRELOCK_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_PRELOCK_SCT0_ADDR field.
	CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_L1_DCACHE_PRELOCK_SCT0_ADDR_Msk = 0xffffffff

	// L1_DCACHE_PRELOCK_SCT1_ADDR: L1 data Cache prelock section1 address configure register
	// Position of L1_DCACHE_PRELOCK_SCT1_ADDR field.
	CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_L1_DCACHE_PRELOCK_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_PRELOCK_SCT1_ADDR field.
	CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_L1_DCACHE_PRELOCK_SCT1_ADDR_Msk = 0xffffffff

	// L1_DCACHE_PRELOCK_SCT_SIZE: L1 data Cache prelock section size configure register
	// Position of L1_DCACHE_PRELOCK_SCT0_SIZE field.
	CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_DCACHE_PRELOCK_SCT0_SIZE field.
	CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT0_SIZE_Msk = 0x3fff
	// Position of L1_DCACHE_PRELOCK_SCT1_SIZE field.
	CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT1_SIZE_Pos = 0x10
	// Bit mask of L1_DCACHE_PRELOCK_SCT1_SIZE field.
	CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_L1_DCACHE_PRELOCK_SCT1_SIZE_Msk = 0x3fff0000

	// LOCK_CTRL: Lock-class (manual lock) operation control register
	// Position of LOCK_ENA field.
	CACHE_LOCK_CTRL_LOCK_ENA_Pos = 0x0
	// Bit mask of LOCK_ENA field.
	CACHE_LOCK_CTRL_LOCK_ENA_Msk = 0x1
	// Bit LOCK_ENA.
	CACHE_LOCK_CTRL_LOCK_ENA = 0x1
	// Position of UNLOCK_ENA field.
	CACHE_LOCK_CTRL_UNLOCK_ENA_Pos = 0x1
	// Bit mask of UNLOCK_ENA field.
	CACHE_LOCK_CTRL_UNLOCK_ENA_Msk = 0x2
	// Bit UNLOCK_ENA.
	CACHE_LOCK_CTRL_UNLOCK_ENA = 0x2
	// Position of LOCK_DONE field.
	CACHE_LOCK_CTRL_LOCK_DONE_Pos = 0x2
	// Bit mask of LOCK_DONE field.
	CACHE_LOCK_CTRL_LOCK_DONE_Msk = 0x4
	// Bit LOCK_DONE.
	CACHE_LOCK_CTRL_LOCK_DONE = 0x4
	// Position of LOCK_RGID field.
	CACHE_LOCK_CTRL_LOCK_RGID_Pos = 0x3
	// Bit mask of LOCK_RGID field.
	CACHE_LOCK_CTRL_LOCK_RGID_Msk = 0x78

	// LOCK_MAP: Lock (manual lock) map configure register
	// Position of LOCK_MAP field.
	CACHE_LOCK_MAP_LOCK_MAP_Pos = 0x0
	// Bit mask of LOCK_MAP field.
	CACHE_LOCK_MAP_LOCK_MAP_Msk = 0x3f

	// LOCK_ADDR: Lock (manual lock) address configure register
	// Position of LOCK_ADDR field.
	CACHE_LOCK_ADDR_LOCK_ADDR_Pos = 0x0
	// Bit mask of LOCK_ADDR field.
	CACHE_LOCK_ADDR_LOCK_ADDR_Msk = 0xffffffff

	// LOCK_SIZE: Lock (manual lock) size configure register
	// Position of LOCK_SIZE field.
	CACHE_LOCK_SIZE_LOCK_SIZE_Pos = 0x0
	// Bit mask of LOCK_SIZE field.
	CACHE_LOCK_SIZE_LOCK_SIZE_Msk = 0xffff

	// SYNC_CTRL: Sync-class operation control register
	// Position of INVALIDATE_ENA field.
	CACHE_SYNC_CTRL_INVALIDATE_ENA_Pos = 0x0
	// Bit mask of INVALIDATE_ENA field.
	CACHE_SYNC_CTRL_INVALIDATE_ENA_Msk = 0x1
	// Bit INVALIDATE_ENA.
	CACHE_SYNC_CTRL_INVALIDATE_ENA = 0x1
	// Position of CLEAN_ENA field.
	CACHE_SYNC_CTRL_CLEAN_ENA_Pos = 0x1
	// Bit mask of CLEAN_ENA field.
	CACHE_SYNC_CTRL_CLEAN_ENA_Msk = 0x2
	// Bit CLEAN_ENA.
	CACHE_SYNC_CTRL_CLEAN_ENA = 0x2
	// Position of WRITEBACK_ENA field.
	CACHE_SYNC_CTRL_WRITEBACK_ENA_Pos = 0x2
	// Bit mask of WRITEBACK_ENA field.
	CACHE_SYNC_CTRL_WRITEBACK_ENA_Msk = 0x4
	// Bit WRITEBACK_ENA.
	CACHE_SYNC_CTRL_WRITEBACK_ENA = 0x4
	// Position of WRITEBACK_INVALIDATE_ENA field.
	CACHE_SYNC_CTRL_WRITEBACK_INVALIDATE_ENA_Pos = 0x3
	// Bit mask of WRITEBACK_INVALIDATE_ENA field.
	CACHE_SYNC_CTRL_WRITEBACK_INVALIDATE_ENA_Msk = 0x8
	// Bit WRITEBACK_INVALIDATE_ENA.
	CACHE_SYNC_CTRL_WRITEBACK_INVALIDATE_ENA = 0x8
	// Position of SYNC_DONE field.
	CACHE_SYNC_CTRL_SYNC_DONE_Pos = 0x4
	// Bit mask of SYNC_DONE field.
	CACHE_SYNC_CTRL_SYNC_DONE_Msk = 0x10
	// Bit SYNC_DONE.
	CACHE_SYNC_CTRL_SYNC_DONE = 0x10
	// Position of SYNC_RGID field.
	CACHE_SYNC_CTRL_SYNC_RGID_Pos = 0x5
	// Bit mask of SYNC_RGID field.
	CACHE_SYNC_CTRL_SYNC_RGID_Msk = 0x1e0

	// SYNC_MAP: Sync map configure register
	// Position of SYNC_MAP field.
	CACHE_SYNC_MAP_SYNC_MAP_Pos = 0x0
	// Bit mask of SYNC_MAP field.
	CACHE_SYNC_MAP_SYNC_MAP_Msk = 0x3f

	// SYNC_ADDR: Sync address configure register
	// Position of SYNC_ADDR field.
	CACHE_SYNC_ADDR_SYNC_ADDR_Pos = 0x0
	// Bit mask of SYNC_ADDR field.
	CACHE_SYNC_ADDR_SYNC_ADDR_Msk = 0xffffffff

	// SYNC_SIZE: Sync size configure register
	// Position of SYNC_SIZE field.
	CACHE_SYNC_SIZE_SYNC_SIZE_Pos = 0x0
	// Bit mask of SYNC_SIZE field.
	CACHE_SYNC_SIZE_SYNC_SIZE_Msk = 0xfffffff

	// L1_ICACHE0_PRELOAD_CTRL: L1 instruction Cache 0 preload-operation control register
	// Position of L1_ICACHE0_PRELOAD_ENA field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE0_PRELOAD_ENA field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE0_PRELOAD_ENA.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ENA = 0x1
	// Position of L1_ICACHE0_PRELOAD_DONE field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE0_PRELOAD_DONE field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE0_PRELOAD_DONE.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_DONE = 0x2
	// Position of L1_ICACHE0_PRELOAD_ORDER field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE0_PRELOAD_ORDER field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE0_PRELOAD_ORDER.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_ORDER = 0x4
	// Position of L1_ICACHE0_PRELOAD_RGID field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID_Pos = 0x3
	// Bit mask of L1_ICACHE0_PRELOAD_RGID field.
	CACHE_L1_ICACHE0_PRELOAD_CTRL_L1_ICACHE0_PRELOAD_RGID_Msk = 0x78

	// L1_ICACHE0_PRELOAD_ADDR: L1 instruction Cache 0 preload address configure register
	// Position of L1_ICACHE0_PRELOAD_ADDR field.
	CACHE_L1_ICACHE0_PRELOAD_ADDR_L1_ICACHE0_PRELOAD_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE0_PRELOAD_ADDR field.
	CACHE_L1_ICACHE0_PRELOAD_ADDR_L1_ICACHE0_PRELOAD_ADDR_Msk = 0xffffffff

	// L1_ICACHE0_PRELOAD_SIZE: L1 instruction Cache 0 preload size configure register
	// Position of L1_ICACHE0_PRELOAD_SIZE field.
	CACHE_L1_ICACHE0_PRELOAD_SIZE_L1_ICACHE0_PRELOAD_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE0_PRELOAD_SIZE field.
	CACHE_L1_ICACHE0_PRELOAD_SIZE_L1_ICACHE0_PRELOAD_SIZE_Msk = 0x3fff

	// L1_ICACHE1_PRELOAD_CTRL: L1 instruction Cache 1 preload-operation control register
	// Position of L1_ICACHE1_PRELOAD_ENA field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE1_PRELOAD_ENA field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE1_PRELOAD_ENA.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ENA = 0x1
	// Position of L1_ICACHE1_PRELOAD_DONE field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE1_PRELOAD_DONE field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE1_PRELOAD_DONE.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_DONE = 0x2
	// Position of L1_ICACHE1_PRELOAD_ORDER field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE1_PRELOAD_ORDER field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE1_PRELOAD_ORDER.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_ORDER = 0x4
	// Position of L1_ICACHE1_PRELOAD_RGID field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID_Pos = 0x3
	// Bit mask of L1_ICACHE1_PRELOAD_RGID field.
	CACHE_L1_ICACHE1_PRELOAD_CTRL_L1_ICACHE1_PRELOAD_RGID_Msk = 0x78

	// L1_ICACHE1_PRELOAD_ADDR: L1 instruction Cache 1 preload address configure register
	// Position of L1_ICACHE1_PRELOAD_ADDR field.
	CACHE_L1_ICACHE1_PRELOAD_ADDR_L1_ICACHE1_PRELOAD_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE1_PRELOAD_ADDR field.
	CACHE_L1_ICACHE1_PRELOAD_ADDR_L1_ICACHE1_PRELOAD_ADDR_Msk = 0xffffffff

	// L1_ICACHE1_PRELOAD_SIZE: L1 instruction Cache 1 preload size configure register
	// Position of L1_ICACHE1_PRELOAD_SIZE field.
	CACHE_L1_ICACHE1_PRELOAD_SIZE_L1_ICACHE1_PRELOAD_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE1_PRELOAD_SIZE field.
	CACHE_L1_ICACHE1_PRELOAD_SIZE_L1_ICACHE1_PRELOAD_SIZE_Msk = 0x3fff

	// L1_ICACHE2_PRELOAD_CTRL: L1 instruction Cache 2 preload-operation control register
	// Position of L1_ICACHE2_PRELOAD_ENA field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE2_PRELOAD_ENA field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE2_PRELOAD_ENA.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ENA = 0x1
	// Position of L1_ICACHE2_PRELOAD_DONE field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE2_PRELOAD_DONE field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE2_PRELOAD_DONE.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_DONE = 0x2
	// Position of L1_ICACHE2_PRELOAD_ORDER field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE2_PRELOAD_ORDER field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE2_PRELOAD_ORDER.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_ORDER = 0x4
	// Position of L1_ICACHE2_PRELOAD_RGID field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID_Pos = 0x3
	// Bit mask of L1_ICACHE2_PRELOAD_RGID field.
	CACHE_L1_ICACHE2_PRELOAD_CTRL_L1_ICACHE2_PRELOAD_RGID_Msk = 0x78

	// L1_ICACHE2_PRELOAD_ADDR: L1 instruction Cache 2 preload address configure register
	// Position of L1_ICACHE2_PRELOAD_ADDR field.
	CACHE_L1_ICACHE2_PRELOAD_ADDR_L1_ICACHE2_PRELOAD_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE2_PRELOAD_ADDR field.
	CACHE_L1_ICACHE2_PRELOAD_ADDR_L1_ICACHE2_PRELOAD_ADDR_Msk = 0xffffffff

	// L1_ICACHE2_PRELOAD_SIZE: L1 instruction Cache 2 preload size configure register
	// Position of L1_ICACHE2_PRELOAD_SIZE field.
	CACHE_L1_ICACHE2_PRELOAD_SIZE_L1_ICACHE2_PRELOAD_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE2_PRELOAD_SIZE field.
	CACHE_L1_ICACHE2_PRELOAD_SIZE_L1_ICACHE2_PRELOAD_SIZE_Msk = 0x3fff

	// L1_ICACHE3_PRELOAD_CTRL: L1 instruction Cache 3 preload-operation control register
	// Position of L1_ICACHE3_PRELOAD_ENA field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE3_PRELOAD_ENA field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE3_PRELOAD_ENA.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ENA = 0x1
	// Position of L1_ICACHE3_PRELOAD_DONE field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE3_PRELOAD_DONE field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE3_PRELOAD_DONE.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_DONE = 0x2
	// Position of L1_ICACHE3_PRELOAD_ORDER field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE3_PRELOAD_ORDER field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE3_PRELOAD_ORDER.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_ORDER = 0x4
	// Position of L1_ICACHE3_PRELOAD_RGID field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID_Pos = 0x3
	// Bit mask of L1_ICACHE3_PRELOAD_RGID field.
	CACHE_L1_ICACHE3_PRELOAD_CTRL_L1_ICACHE3_PRELOAD_RGID_Msk = 0x78

	// L1_ICACHE3_PRELOAD_ADDR: L1 instruction Cache 3 preload address configure register
	// Position of L1_ICACHE3_PRELOAD_ADDR field.
	CACHE_L1_ICACHE3_PRELOAD_ADDR_L1_ICACHE3_PRELOAD_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE3_PRELOAD_ADDR field.
	CACHE_L1_ICACHE3_PRELOAD_ADDR_L1_ICACHE3_PRELOAD_ADDR_Msk = 0xffffffff

	// L1_ICACHE3_PRELOAD_SIZE: L1 instruction Cache 3 preload size configure register
	// Position of L1_ICACHE3_PRELOAD_SIZE field.
	CACHE_L1_ICACHE3_PRELOAD_SIZE_L1_ICACHE3_PRELOAD_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE3_PRELOAD_SIZE field.
	CACHE_L1_ICACHE3_PRELOAD_SIZE_L1_ICACHE3_PRELOAD_SIZE_Msk = 0x3fff

	// L1_DCACHE_PRELOAD_CTRL: L1 data Cache preload-operation control register
	// Position of L1_DCACHE_PRELOAD_ENA field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ENA_Pos = 0x0
	// Bit mask of L1_DCACHE_PRELOAD_ENA field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ENA_Msk = 0x1
	// Bit L1_DCACHE_PRELOAD_ENA.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ENA = 0x1
	// Position of L1_DCACHE_PRELOAD_DONE field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_DONE_Pos = 0x1
	// Bit mask of L1_DCACHE_PRELOAD_DONE field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_DONE_Msk = 0x2
	// Bit L1_DCACHE_PRELOAD_DONE.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_DONE = 0x2
	// Position of L1_DCACHE_PRELOAD_ORDER field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ORDER_Pos = 0x2
	// Bit mask of L1_DCACHE_PRELOAD_ORDER field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ORDER_Msk = 0x4
	// Bit L1_DCACHE_PRELOAD_ORDER.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_ORDER = 0x4
	// Position of L1_DCACHE_PRELOAD_RGID field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_RGID_Pos = 0x3
	// Bit mask of L1_DCACHE_PRELOAD_RGID field.
	CACHE_L1_DCACHE_PRELOAD_CTRL_L1_DCACHE_PRELOAD_RGID_Msk = 0x78

	// L1_DCACHE_PRELOAD_ADDR: L1 data Cache preload address configure register
	// Position of L1_DCACHE_PRELOAD_ADDR field.
	CACHE_L1_DCACHE_PRELOAD_ADDR_L1_DCACHE_PRELOAD_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_PRELOAD_ADDR field.
	CACHE_L1_DCACHE_PRELOAD_ADDR_L1_DCACHE_PRELOAD_ADDR_Msk = 0xffffffff

	// L1_DCACHE_PRELOAD_SIZE: L1 data Cache preload size configure register
	// Position of L1_DCACHE_PRELOAD_SIZE field.
	CACHE_L1_DCACHE_PRELOAD_SIZE_L1_DCACHE_PRELOAD_SIZE_Pos = 0x0
	// Bit mask of L1_DCACHE_PRELOAD_SIZE field.
	CACHE_L1_DCACHE_PRELOAD_SIZE_L1_DCACHE_PRELOAD_SIZE_Msk = 0x3fff

	// L1_ICACHE0_AUTOLOAD_CTRL: L1 instruction Cache 0 autoload-operation control register
	// Position of L1_ICACHE0_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE0_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE0_AUTOLOAD_ENA.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ENA = 0x1
	// Position of L1_ICACHE0_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE0_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE0_AUTOLOAD_DONE.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_DONE = 0x2
	// Position of L1_ICACHE0_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE0_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE0_AUTOLOAD_ORDER.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_ORDER = 0x4
	// Position of L1_ICACHE0_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_Pos = 0x3
	// Bit mask of L1_ICACHE0_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_Msk = 0x18
	// Position of L1_ICACHE0_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA_Pos = 0x8
	// Bit mask of L1_ICACHE0_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA_Msk = 0x100
	// Bit L1_ICACHE0_AUTOLOAD_SCT0_ENA.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT0_ENA = 0x100
	// Position of L1_ICACHE0_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA_Pos = 0x9
	// Bit mask of L1_ICACHE0_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA_Msk = 0x200
	// Bit L1_ICACHE0_AUTOLOAD_SCT1_ENA.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_SCT1_ENA = 0x200
	// Position of L1_ICACHE0_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID_Pos = 0xa
	// Bit mask of L1_ICACHE0_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE0_AUTOLOAD_CTRL_L1_ICACHE0_AUTOLOAD_RGID_Msk = 0x3c00

	// L1_ICACHE0_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 0 autoload section 0 address configure register
	// Position of L1_ICACHE0_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE0_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE0_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 0 autoload section 0 size configure register
	// Position of L1_ICACHE0_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE0_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff

	// L1_ICACHE0_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 0 autoload section 1 address configure register
	// Position of L1_ICACHE0_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE0_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE0_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 0 autoload section 1 size configure register
	// Position of L1_ICACHE0_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE0_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff

	// L1_ICACHE1_AUTOLOAD_CTRL: L1 instruction Cache 1 autoload-operation control register
	// Position of L1_ICACHE1_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE1_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE1_AUTOLOAD_ENA.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ENA = 0x1
	// Position of L1_ICACHE1_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE1_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE1_AUTOLOAD_DONE.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_DONE = 0x2
	// Position of L1_ICACHE1_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE1_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE1_AUTOLOAD_ORDER.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_ORDER = 0x4
	// Position of L1_ICACHE1_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_Pos = 0x3
	// Bit mask of L1_ICACHE1_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_Msk = 0x18
	// Position of L1_ICACHE1_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA_Pos = 0x8
	// Bit mask of L1_ICACHE1_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA_Msk = 0x100
	// Bit L1_ICACHE1_AUTOLOAD_SCT0_ENA.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT0_ENA = 0x100
	// Position of L1_ICACHE1_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA_Pos = 0x9
	// Bit mask of L1_ICACHE1_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA_Msk = 0x200
	// Bit L1_ICACHE1_AUTOLOAD_SCT1_ENA.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_SCT1_ENA = 0x200
	// Position of L1_ICACHE1_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID_Pos = 0xa
	// Bit mask of L1_ICACHE1_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE1_AUTOLOAD_CTRL_L1_ICACHE1_AUTOLOAD_RGID_Msk = 0x3c00

	// L1_ICACHE1_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 1 autoload section 0 address configure register
	// Position of L1_ICACHE1_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE1_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE1_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 1 autoload section 0 size configure register
	// Position of L1_ICACHE1_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE1_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff

	// L1_ICACHE1_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 1 autoload section 1 address configure register
	// Position of L1_ICACHE1_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE1_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE1_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 1 autoload section 1 size configure register
	// Position of L1_ICACHE1_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE1_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff

	// L1_ICACHE2_AUTOLOAD_CTRL: L1 instruction Cache 2 autoload-operation control register
	// Position of L1_ICACHE2_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE2_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE2_AUTOLOAD_ENA.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ENA = 0x1
	// Position of L1_ICACHE2_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE2_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE2_AUTOLOAD_DONE.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_DONE = 0x2
	// Position of L1_ICACHE2_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE2_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE2_AUTOLOAD_ORDER.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_ORDER = 0x4
	// Position of L1_ICACHE2_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_Pos = 0x3
	// Bit mask of L1_ICACHE2_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_Msk = 0x18
	// Position of L1_ICACHE2_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA_Pos = 0x8
	// Bit mask of L1_ICACHE2_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA_Msk = 0x100
	// Bit L1_ICACHE2_AUTOLOAD_SCT0_ENA.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT0_ENA = 0x100
	// Position of L1_ICACHE2_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA_Pos = 0x9
	// Bit mask of L1_ICACHE2_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA_Msk = 0x200
	// Bit L1_ICACHE2_AUTOLOAD_SCT1_ENA.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_SCT1_ENA = 0x200
	// Position of L1_ICACHE2_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID_Pos = 0xa
	// Bit mask of L1_ICACHE2_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE2_AUTOLOAD_CTRL_L1_ICACHE2_AUTOLOAD_RGID_Msk = 0x3c00

	// L1_ICACHE2_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 2 autoload section 0 address configure register
	// Position of L1_ICACHE2_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE2_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE2_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 2 autoload section 0 size configure register
	// Position of L1_ICACHE2_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE2_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff

	// L1_ICACHE2_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 2 autoload section 1 address configure register
	// Position of L1_ICACHE2_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE2_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE2_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 2 autoload section 1 size configure register
	// Position of L1_ICACHE2_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE2_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff

	// L1_ICACHE3_AUTOLOAD_CTRL: L1 instruction Cache 3 autoload-operation control register
	// Position of L1_ICACHE3_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE3_AUTOLOAD_ENA field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA_Msk = 0x1
	// Bit L1_ICACHE3_AUTOLOAD_ENA.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ENA = 0x1
	// Position of L1_ICACHE3_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE_Pos = 0x1
	// Bit mask of L1_ICACHE3_AUTOLOAD_DONE field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE_Msk = 0x2
	// Bit L1_ICACHE3_AUTOLOAD_DONE.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_DONE = 0x2
	// Position of L1_ICACHE3_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER_Pos = 0x2
	// Bit mask of L1_ICACHE3_AUTOLOAD_ORDER field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER_Msk = 0x4
	// Bit L1_ICACHE3_AUTOLOAD_ORDER.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_ORDER = 0x4
	// Position of L1_ICACHE3_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_Pos = 0x3
	// Bit mask of L1_ICACHE3_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_Msk = 0x18
	// Position of L1_ICACHE3_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA_Pos = 0x8
	// Bit mask of L1_ICACHE3_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA_Msk = 0x100
	// Bit L1_ICACHE3_AUTOLOAD_SCT0_ENA.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT0_ENA = 0x100
	// Position of L1_ICACHE3_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA_Pos = 0x9
	// Bit mask of L1_ICACHE3_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA_Msk = 0x200
	// Bit L1_ICACHE3_AUTOLOAD_SCT1_ENA.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_SCT1_ENA = 0x200
	// Position of L1_ICACHE3_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID_Pos = 0xa
	// Bit mask of L1_ICACHE3_AUTOLOAD_RGID field.
	CACHE_L1_ICACHE3_AUTOLOAD_CTRL_L1_ICACHE3_AUTOLOAD_RGID_Msk = 0x3c00

	// L1_ICACHE3_AUTOLOAD_SCT0_ADDR: L1 instruction Cache 3 autoload section 0 address configure register
	// Position of L1_ICACHE3_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE3_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff

	// L1_ICACHE3_AUTOLOAD_SCT0_SIZE: L1 instruction Cache 3 autoload section 0 size configure register
	// Position of L1_ICACHE3_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE3_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff

	// L1_ICACHE3_AUTOLOAD_SCT1_ADDR: L1 instruction Cache 3 autoload section 1 address configure register
	// Position of L1_ICACHE3_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE3_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff

	// L1_ICACHE3_AUTOLOAD_SCT1_SIZE: L1 instruction Cache 3 autoload section 1 size configure register
	// Position of L1_ICACHE3_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_Pos = 0x0
	// Bit mask of L1_ICACHE3_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff

	// L1_DCACHE_AUTOLOAD_CTRL: L1 data Cache autoload-operation control register
	// Position of L1_DCACHE_AUTOLOAD_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ENA_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ENA_Msk = 0x1
	// Bit L1_DCACHE_AUTOLOAD_ENA.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ENA = 0x1
	// Position of L1_DCACHE_AUTOLOAD_DONE field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_DONE_Pos = 0x1
	// Bit mask of L1_DCACHE_AUTOLOAD_DONE field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_DONE_Msk = 0x2
	// Bit L1_DCACHE_AUTOLOAD_DONE.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_DONE = 0x2
	// Position of L1_DCACHE_AUTOLOAD_ORDER field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ORDER_Pos = 0x2
	// Bit mask of L1_DCACHE_AUTOLOAD_ORDER field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ORDER_Msk = 0x4
	// Bit L1_DCACHE_AUTOLOAD_ORDER.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_ORDER = 0x4
	// Position of L1_DCACHE_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_Pos = 0x3
	// Bit mask of L1_DCACHE_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_Msk = 0x18
	// Position of L1_DCACHE_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT0_ENA_Pos = 0x8
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT0_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT0_ENA_Msk = 0x100
	// Bit L1_DCACHE_AUTOLOAD_SCT0_ENA.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT0_ENA = 0x100
	// Position of L1_DCACHE_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT1_ENA_Pos = 0x9
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT1_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT1_ENA_Msk = 0x200
	// Bit L1_DCACHE_AUTOLOAD_SCT1_ENA.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT1_ENA = 0x200
	// Position of L1_DCACHE_AUTOLOAD_SCT2_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT2_ENA_Pos = 0xa
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT2_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT2_ENA_Msk = 0x400
	// Bit L1_DCACHE_AUTOLOAD_SCT2_ENA.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT2_ENA = 0x400
	// Position of L1_DCACHE_AUTOLOAD_SCT3_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT3_ENA_Pos = 0xb
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT3_ENA field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT3_ENA_Msk = 0x800
	// Bit L1_DCACHE_AUTOLOAD_SCT3_ENA.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_SCT3_ENA = 0x800
	// Position of L1_DCACHE_AUTOLOAD_RGID field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_RGID_Pos = 0xc
	// Bit mask of L1_DCACHE_AUTOLOAD_RGID field.
	CACHE_L1_DCACHE_AUTOLOAD_CTRL_L1_DCACHE_AUTOLOAD_RGID_Msk = 0xf000

	// L1_DCACHE_AUTOLOAD_SCT0_ADDR: L1 data Cache autoload section 0 address configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_L1_DCACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT0_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_L1_DCACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff

	// L1_DCACHE_AUTOLOAD_SCT0_SIZE: L1 data Cache autoload section 0 size configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT0_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff

	// L1_DCACHE_AUTOLOAD_SCT1_ADDR: L1 data Cache autoload section 1 address configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_L1_DCACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT1_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_L1_DCACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff

	// L1_DCACHE_AUTOLOAD_SCT1_SIZE: L1 data Cache autoload section 1 size configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT1_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff

	// L1_DCACHE_AUTOLOAD_SCT2_ADDR: L1 data Cache autoload section 2 address configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT2_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_L1_DCACHE_AUTOLOAD_SCT2_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT2_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_L1_DCACHE_AUTOLOAD_SCT2_ADDR_Msk = 0xffffffff

	// L1_DCACHE_AUTOLOAD_SCT2_SIZE: L1 data Cache autoload section 2 size configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT2_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT2_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_Msk = 0xfffffff

	// L1_DCACHE_AUTOLOAD_SCT3_ADDR: L1 data Cache autoload section 1 address configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT3_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_L1_DCACHE_AUTOLOAD_SCT3_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT3_ADDR field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_L1_DCACHE_AUTOLOAD_SCT3_ADDR_Msk = 0xffffffff

	// L1_DCACHE_AUTOLOAD_SCT3_SIZE: L1 data Cache autoload section 1 size configure register
	// Position of L1_DCACHE_AUTOLOAD_SCT3_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_Pos = 0x0
	// Bit mask of L1_DCACHE_AUTOLOAD_SCT3_SIZE field.
	CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_Msk = 0xfffffff

	// L1_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register
	// Position of L1_IBUS0_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA_Pos = 0x0
	// Bit mask of L1_IBUS0_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA_Msk = 0x1
	// Bit L1_IBUS0_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS0_OVF_INT_ENA = 0x1
	// Position of L1_IBUS1_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA_Pos = 0x1
	// Bit mask of L1_IBUS1_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA_Msk = 0x2
	// Bit L1_IBUS1_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS1_OVF_INT_ENA = 0x2
	// Position of L1_IBUS2_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA_Pos = 0x2
	// Bit mask of L1_IBUS2_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA_Msk = 0x4
	// Bit L1_IBUS2_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS2_OVF_INT_ENA = 0x4
	// Position of L1_IBUS3_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA_Pos = 0x3
	// Bit mask of L1_IBUS3_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA_Msk = 0x8
	// Bit L1_IBUS3_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_IBUS3_OVF_INT_ENA = 0x8
	// Position of L1_DBUS0_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS0_OVF_INT_ENA_Pos = 0x4
	// Bit mask of L1_DBUS0_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS0_OVF_INT_ENA_Msk = 0x10
	// Bit L1_DBUS0_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS0_OVF_INT_ENA = 0x10
	// Position of L1_DBUS1_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS1_OVF_INT_ENA_Pos = 0x5
	// Bit mask of L1_DBUS1_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS1_OVF_INT_ENA_Msk = 0x20
	// Bit L1_DBUS1_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS1_OVF_INT_ENA = 0x20
	// Position of L1_DBUS2_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA_Pos = 0x6
	// Bit mask of L1_DBUS2_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA_Msk = 0x40
	// Bit L1_DBUS2_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS2_OVF_INT_ENA = 0x40
	// Position of L1_DBUS3_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA_Pos = 0x7
	// Bit mask of L1_DBUS3_OVF_INT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA_Msk = 0x80
	// Bit L1_DBUS3_OVF_INT_ENA.
	CACHE_L1_CACHE_ACS_CNT_INT_ENA_L1_DBUS3_OVF_INT_ENA = 0x80

	// L1_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register
	// Position of L1_IBUS0_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR_Pos = 0x0
	// Bit mask of L1_IBUS0_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR_Msk = 0x1
	// Bit L1_IBUS0_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS0_OVF_INT_CLR = 0x1
	// Position of L1_IBUS1_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR_Pos = 0x1
	// Bit mask of L1_IBUS1_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR_Msk = 0x2
	// Bit L1_IBUS1_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS1_OVF_INT_CLR = 0x2
	// Position of L1_IBUS2_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR_Pos = 0x2
	// Bit mask of L1_IBUS2_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR_Msk = 0x4
	// Bit L1_IBUS2_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS2_OVF_INT_CLR = 0x4
	// Position of L1_IBUS3_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR_Pos = 0x3
	// Bit mask of L1_IBUS3_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR_Msk = 0x8
	// Bit L1_IBUS3_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_IBUS3_OVF_INT_CLR = 0x8
	// Position of L1_DBUS0_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS0_OVF_INT_CLR_Pos = 0x4
	// Bit mask of L1_DBUS0_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS0_OVF_INT_CLR_Msk = 0x10
	// Bit L1_DBUS0_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS0_OVF_INT_CLR = 0x10
	// Position of L1_DBUS1_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS1_OVF_INT_CLR_Pos = 0x5
	// Bit mask of L1_DBUS1_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS1_OVF_INT_CLR_Msk = 0x20
	// Bit L1_DBUS1_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS1_OVF_INT_CLR = 0x20
	// Position of L1_DBUS2_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR_Pos = 0x6
	// Bit mask of L1_DBUS2_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR_Msk = 0x40
	// Bit L1_DBUS2_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS2_OVF_INT_CLR = 0x40
	// Position of L1_DBUS3_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR_Pos = 0x7
	// Bit mask of L1_DBUS3_OVF_INT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR_Msk = 0x80
	// Bit L1_DBUS3_OVF_INT_CLR.
	CACHE_L1_CACHE_ACS_CNT_INT_CLR_L1_DBUS3_OVF_INT_CLR = 0x80

	// L1_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register
	// Position of L1_IBUS0_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW_Pos = 0x0
	// Bit mask of L1_IBUS0_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW_Msk = 0x1
	// Bit L1_IBUS0_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS0_OVF_INT_RAW = 0x1
	// Position of L1_IBUS1_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW_Pos = 0x1
	// Bit mask of L1_IBUS1_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW_Msk = 0x2
	// Bit L1_IBUS1_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS1_OVF_INT_RAW = 0x2
	// Position of L1_IBUS2_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW_Pos = 0x2
	// Bit mask of L1_IBUS2_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW_Msk = 0x4
	// Bit L1_IBUS2_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS2_OVF_INT_RAW = 0x4
	// Position of L1_IBUS3_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW_Pos = 0x3
	// Bit mask of L1_IBUS3_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW_Msk = 0x8
	// Bit L1_IBUS3_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_IBUS3_OVF_INT_RAW = 0x8
	// Position of L1_DBUS0_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS0_OVF_INT_RAW_Pos = 0x4
	// Bit mask of L1_DBUS0_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS0_OVF_INT_RAW_Msk = 0x10
	// Bit L1_DBUS0_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS0_OVF_INT_RAW = 0x10
	// Position of L1_DBUS1_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS1_OVF_INT_RAW_Pos = 0x5
	// Bit mask of L1_DBUS1_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS1_OVF_INT_RAW_Msk = 0x20
	// Bit L1_DBUS1_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS1_OVF_INT_RAW = 0x20
	// Position of L1_DBUS2_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW_Pos = 0x6
	// Bit mask of L1_DBUS2_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW_Msk = 0x40
	// Bit L1_DBUS2_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS2_OVF_INT_RAW = 0x40
	// Position of L1_DBUS3_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW_Pos = 0x7
	// Bit mask of L1_DBUS3_OVF_INT_RAW field.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW_Msk = 0x80
	// Bit L1_DBUS3_OVF_INT_RAW.
	CACHE_L1_CACHE_ACS_CNT_INT_RAW_L1_DBUS3_OVF_INT_RAW = 0x80

	// L1_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register
	// Position of L1_IBUS0_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST_Pos = 0x0
	// Bit mask of L1_IBUS0_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST_Msk = 0x1
	// Bit L1_IBUS0_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS0_OVF_INT_ST = 0x1
	// Position of L1_IBUS1_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST_Pos = 0x1
	// Bit mask of L1_IBUS1_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST_Msk = 0x2
	// Bit L1_IBUS1_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS1_OVF_INT_ST = 0x2
	// Position of L1_IBUS2_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST_Pos = 0x2
	// Bit mask of L1_IBUS2_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST_Msk = 0x4
	// Bit L1_IBUS2_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS2_OVF_INT_ST = 0x4
	// Position of L1_IBUS3_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST_Pos = 0x3
	// Bit mask of L1_IBUS3_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST_Msk = 0x8
	// Bit L1_IBUS3_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_IBUS3_OVF_INT_ST = 0x8
	// Position of L1_DBUS0_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS0_OVF_INT_ST_Pos = 0x4
	// Bit mask of L1_DBUS0_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS0_OVF_INT_ST_Msk = 0x10
	// Bit L1_DBUS0_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS0_OVF_INT_ST = 0x10
	// Position of L1_DBUS1_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS1_OVF_INT_ST_Pos = 0x5
	// Bit mask of L1_DBUS1_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS1_OVF_INT_ST_Msk = 0x20
	// Bit L1_DBUS1_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS1_OVF_INT_ST = 0x20
	// Position of L1_DBUS2_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST_Pos = 0x6
	// Bit mask of L1_DBUS2_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST_Msk = 0x40
	// Bit L1_DBUS2_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS2_OVF_INT_ST = 0x40
	// Position of L1_DBUS3_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST_Pos = 0x7
	// Bit mask of L1_DBUS3_OVF_INT_ST field.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST_Msk = 0x80
	// Bit L1_DBUS3_OVF_INT_ST.
	CACHE_L1_CACHE_ACS_CNT_INT_ST_L1_DBUS3_OVF_INT_ST = 0x80

	// L1_CACHE_ACS_FAIL_CTRL: Cache Access Fail Configuration register
	// Position of L1_ICACHE0_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE0_ACS_FAIL_CHECK_MODE_Pos = 0x0
	// Bit mask of L1_ICACHE0_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE0_ACS_FAIL_CHECK_MODE_Msk = 0x1
	// Bit L1_ICACHE0_ACS_FAIL_CHECK_MODE.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE0_ACS_FAIL_CHECK_MODE = 0x1
	// Position of L1_ICACHE1_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE1_ACS_FAIL_CHECK_MODE_Pos = 0x1
	// Bit mask of L1_ICACHE1_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE1_ACS_FAIL_CHECK_MODE_Msk = 0x2
	// Bit L1_ICACHE1_ACS_FAIL_CHECK_MODE.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE1_ACS_FAIL_CHECK_MODE = 0x2
	// Position of L1_ICACHE2_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE2_ACS_FAIL_CHECK_MODE_Pos = 0x2
	// Bit mask of L1_ICACHE2_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE2_ACS_FAIL_CHECK_MODE_Msk = 0x4
	// Bit L1_ICACHE2_ACS_FAIL_CHECK_MODE.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE2_ACS_FAIL_CHECK_MODE = 0x4
	// Position of L1_ICACHE3_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE3_ACS_FAIL_CHECK_MODE_Pos = 0x3
	// Bit mask of L1_ICACHE3_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE3_ACS_FAIL_CHECK_MODE_Msk = 0x8
	// Bit L1_ICACHE3_ACS_FAIL_CHECK_MODE.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_ICACHE3_ACS_FAIL_CHECK_MODE = 0x8
	// Position of L1_DCACHE_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_DCACHE_ACS_FAIL_CHECK_MODE_Pos = 0x4
	// Bit mask of L1_DCACHE_ACS_FAIL_CHECK_MODE field.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_DCACHE_ACS_FAIL_CHECK_MODE_Msk = 0x10
	// Bit L1_DCACHE_ACS_FAIL_CHECK_MODE.
	CACHE_L1_CACHE_ACS_FAIL_CTRL_L1_DCACHE_ACS_FAIL_CHECK_MODE = 0x10

	// L1_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register
	// Position of L1_ICACHE0_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE0_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA_Msk = 0x1
	// Bit L1_ICACHE0_FAIL_INT_ENA.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE0_FAIL_INT_ENA = 0x1
	// Position of L1_ICACHE1_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA_Pos = 0x1
	// Bit mask of L1_ICACHE1_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA_Msk = 0x2
	// Bit L1_ICACHE1_FAIL_INT_ENA.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE1_FAIL_INT_ENA = 0x2
	// Position of L1_ICACHE2_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA_Pos = 0x2
	// Bit mask of L1_ICACHE2_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA_Msk = 0x4
	// Bit L1_ICACHE2_FAIL_INT_ENA.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE2_FAIL_INT_ENA = 0x4
	// Position of L1_ICACHE3_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA_Pos = 0x3
	// Bit mask of L1_ICACHE3_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA_Msk = 0x8
	// Bit L1_ICACHE3_FAIL_INT_ENA.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_ICACHE3_FAIL_INT_ENA = 0x8
	// Position of L1_DCACHE_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_DCACHE_FAIL_INT_ENA_Pos = 0x4
	// Bit mask of L1_DCACHE_FAIL_INT_ENA field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_DCACHE_FAIL_INT_ENA_Msk = 0x10
	// Bit L1_DCACHE_FAIL_INT_ENA.
	CACHE_L1_CACHE_ACS_FAIL_INT_ENA_L1_DCACHE_FAIL_INT_ENA = 0x10

	// L1_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register
	// Position of L1_ICACHE0_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR_Pos = 0x0
	// Bit mask of L1_ICACHE0_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR_Msk = 0x1
	// Bit L1_ICACHE0_FAIL_INT_CLR.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE0_FAIL_INT_CLR = 0x1
	// Position of L1_ICACHE1_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR_Pos = 0x1
	// Bit mask of L1_ICACHE1_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR_Msk = 0x2
	// Bit L1_ICACHE1_FAIL_INT_CLR.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE1_FAIL_INT_CLR = 0x2
	// Position of L1_ICACHE2_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR_Pos = 0x2
	// Bit mask of L1_ICACHE2_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR_Msk = 0x4
	// Bit L1_ICACHE2_FAIL_INT_CLR.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE2_FAIL_INT_CLR = 0x4
	// Position of L1_ICACHE3_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR_Pos = 0x3
	// Bit mask of L1_ICACHE3_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR_Msk = 0x8
	// Bit L1_ICACHE3_FAIL_INT_CLR.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_ICACHE3_FAIL_INT_CLR = 0x8
	// Position of L1_DCACHE_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_DCACHE_FAIL_INT_CLR_Pos = 0x4
	// Bit mask of L1_DCACHE_FAIL_INT_CLR field.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_DCACHE_FAIL_INT_CLR_Msk = 0x10
	// Bit L1_DCACHE_FAIL_INT_CLR.
	CACHE_L1_CACHE_ACS_FAIL_INT_CLR_L1_DCACHE_FAIL_INT_CLR = 0x10

	// L1_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register
	// Position of L1_ICACHE0_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW_Pos = 0x0
	// Bit mask of L1_ICACHE0_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW_Msk = 0x1
	// Bit L1_ICACHE0_FAIL_INT_RAW.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE0_FAIL_INT_RAW = 0x1
	// Position of L1_ICACHE1_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW_Pos = 0x1
	// Bit mask of L1_ICACHE1_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW_Msk = 0x2
	// Bit L1_ICACHE1_FAIL_INT_RAW.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE1_FAIL_INT_RAW = 0x2
	// Position of L1_ICACHE2_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW_Pos = 0x2
	// Bit mask of L1_ICACHE2_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW_Msk = 0x4
	// Bit L1_ICACHE2_FAIL_INT_RAW.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE2_FAIL_INT_RAW = 0x4
	// Position of L1_ICACHE3_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW_Pos = 0x3
	// Bit mask of L1_ICACHE3_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW_Msk = 0x8
	// Bit L1_ICACHE3_FAIL_INT_RAW.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_ICACHE3_FAIL_INT_RAW = 0x8
	// Position of L1_DCACHE_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_DCACHE_FAIL_INT_RAW_Pos = 0x4
	// Bit mask of L1_DCACHE_FAIL_INT_RAW field.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_DCACHE_FAIL_INT_RAW_Msk = 0x10
	// Bit L1_DCACHE_FAIL_INT_RAW.
	CACHE_L1_CACHE_ACS_FAIL_INT_RAW_L1_DCACHE_FAIL_INT_RAW = 0x10

	// L1_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register
	// Position of L1_ICACHE0_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST_Pos = 0x0
	// Bit mask of L1_ICACHE0_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST_Msk = 0x1
	// Bit L1_ICACHE0_FAIL_INT_ST.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE0_FAIL_INT_ST = 0x1
	// Position of L1_ICACHE1_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST_Pos = 0x1
	// Bit mask of L1_ICACHE1_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST_Msk = 0x2
	// Bit L1_ICACHE1_FAIL_INT_ST.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE1_FAIL_INT_ST = 0x2
	// Position of L1_ICACHE2_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST_Pos = 0x2
	// Bit mask of L1_ICACHE2_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST_Msk = 0x4
	// Bit L1_ICACHE2_FAIL_INT_ST.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE2_FAIL_INT_ST = 0x4
	// Position of L1_ICACHE3_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST_Pos = 0x3
	// Bit mask of L1_ICACHE3_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST_Msk = 0x8
	// Bit L1_ICACHE3_FAIL_INT_ST.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_ICACHE3_FAIL_INT_ST = 0x8
	// Position of L1_DCACHE_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_DCACHE_FAIL_INT_ST_Pos = 0x4
	// Bit mask of L1_DCACHE_FAIL_INT_ST field.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_DCACHE_FAIL_INT_ST_Msk = 0x10
	// Bit L1_DCACHE_FAIL_INT_ST.
	CACHE_L1_CACHE_ACS_FAIL_INT_ST_L1_DCACHE_FAIL_INT_ST = 0x10

	// L1_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register
	// Position of L1_IBUS0_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA_Pos = 0x0
	// Bit mask of L1_IBUS0_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA_Msk = 0x1
	// Bit L1_IBUS0_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_ENA = 0x1
	// Position of L1_IBUS1_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA_Pos = 0x1
	// Bit mask of L1_IBUS1_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA_Msk = 0x2
	// Bit L1_IBUS1_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_ENA = 0x2
	// Position of L1_IBUS2_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA_Pos = 0x2
	// Bit mask of L1_IBUS2_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA_Msk = 0x4
	// Bit L1_IBUS2_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_ENA = 0x4
	// Position of L1_IBUS3_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA_Pos = 0x3
	// Bit mask of L1_IBUS3_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA_Msk = 0x8
	// Bit L1_IBUS3_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_ENA = 0x8
	// Position of L1_DBUS0_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_ENA_Pos = 0x4
	// Bit mask of L1_DBUS0_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_ENA_Msk = 0x10
	// Bit L1_DBUS0_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_ENA = 0x10
	// Position of L1_DBUS1_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_ENA_Pos = 0x5
	// Bit mask of L1_DBUS1_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_ENA_Msk = 0x20
	// Bit L1_DBUS1_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_ENA = 0x20
	// Position of L1_DBUS2_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA_Pos = 0x6
	// Bit mask of L1_DBUS2_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA_Msk = 0x40
	// Bit L1_DBUS2_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_ENA = 0x40
	// Position of L1_DBUS3_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA_Pos = 0x7
	// Bit mask of L1_DBUS3_CNT_ENA field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA_Msk = 0x80
	// Bit L1_DBUS3_CNT_ENA.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_ENA = 0x80
	// Position of L1_IBUS0_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR_Pos = 0x10
	// Bit mask of L1_IBUS0_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR_Msk = 0x10000
	// Bit L1_IBUS0_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS0_CNT_CLR = 0x10000
	// Position of L1_IBUS1_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR_Pos = 0x11
	// Bit mask of L1_IBUS1_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR_Msk = 0x20000
	// Bit L1_IBUS1_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS1_CNT_CLR = 0x20000
	// Position of L1_IBUS2_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR_Pos = 0x12
	// Bit mask of L1_IBUS2_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR_Msk = 0x40000
	// Bit L1_IBUS2_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS2_CNT_CLR = 0x40000
	// Position of L1_IBUS3_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR_Pos = 0x13
	// Bit mask of L1_IBUS3_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR_Msk = 0x80000
	// Bit L1_IBUS3_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_IBUS3_CNT_CLR = 0x80000
	// Position of L1_DBUS0_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_CLR_Pos = 0x14
	// Bit mask of L1_DBUS0_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_CLR_Msk = 0x100000
	// Bit L1_DBUS0_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS0_CNT_CLR = 0x100000
	// Position of L1_DBUS1_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_CLR_Pos = 0x15
	// Bit mask of L1_DBUS1_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_CLR_Msk = 0x200000
	// Bit L1_DBUS1_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS1_CNT_CLR = 0x200000
	// Position of L1_DBUS2_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR_Pos = 0x16
	// Bit mask of L1_DBUS2_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR_Msk = 0x400000
	// Bit L1_DBUS2_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS2_CNT_CLR = 0x400000
	// Position of L1_DBUS3_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR_Pos = 0x17
	// Bit mask of L1_DBUS3_CNT_CLR field.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR_Msk = 0x800000
	// Bit L1_DBUS3_CNT_CLR.
	CACHE_L1_CACHE_ACS_CNT_CTRL_L1_DBUS3_CNT_CLR = 0x800000

	// L1_IBUS0_ACS_HIT_CNT: L1-ICache bus0 Hit-Access Counter register
	// Position of L1_IBUS0_HIT_CNT field.
	CACHE_L1_IBUS0_ACS_HIT_CNT_L1_IBUS0_HIT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS0_HIT_CNT field.
	CACHE_L1_IBUS0_ACS_HIT_CNT_L1_IBUS0_HIT_CNT_Msk = 0xffffffff

	// L1_IBUS0_ACS_MISS_CNT: L1-ICache bus0 Miss-Access Counter register
	// Position of L1_IBUS0_MISS_CNT field.
	CACHE_L1_IBUS0_ACS_MISS_CNT_L1_IBUS0_MISS_CNT_Pos = 0x0
	// Bit mask of L1_IBUS0_MISS_CNT field.
	CACHE_L1_IBUS0_ACS_MISS_CNT_L1_IBUS0_MISS_CNT_Msk = 0xffffffff

	// L1_IBUS0_ACS_CONFLICT_CNT: L1-ICache bus0 Conflict-Access Counter register
	// Position of L1_IBUS0_CONFLICT_CNT field.
	CACHE_L1_IBUS0_ACS_CONFLICT_CNT_L1_IBUS0_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS0_CONFLICT_CNT field.
	CACHE_L1_IBUS0_ACS_CONFLICT_CNT_L1_IBUS0_CONFLICT_CNT_Msk = 0xffffffff

	// L1_IBUS0_ACS_NXTLVL_RD_CNT: L1-ICache bus0 Next-Level-Access Counter register
	// Position of L1_IBUS0_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_L1_IBUS0_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_IBUS0_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_L1_IBUS0_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_IBUS1_ACS_HIT_CNT: L1-ICache bus1 Hit-Access Counter register
	// Position of L1_IBUS1_HIT_CNT field.
	CACHE_L1_IBUS1_ACS_HIT_CNT_L1_IBUS1_HIT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS1_HIT_CNT field.
	CACHE_L1_IBUS1_ACS_HIT_CNT_L1_IBUS1_HIT_CNT_Msk = 0xffffffff

	// L1_IBUS1_ACS_MISS_CNT: L1-ICache bus1 Miss-Access Counter register
	// Position of L1_IBUS1_MISS_CNT field.
	CACHE_L1_IBUS1_ACS_MISS_CNT_L1_IBUS1_MISS_CNT_Pos = 0x0
	// Bit mask of L1_IBUS1_MISS_CNT field.
	CACHE_L1_IBUS1_ACS_MISS_CNT_L1_IBUS1_MISS_CNT_Msk = 0xffffffff

	// L1_IBUS1_ACS_CONFLICT_CNT: L1-ICache bus1 Conflict-Access Counter register
	// Position of L1_IBUS1_CONFLICT_CNT field.
	CACHE_L1_IBUS1_ACS_CONFLICT_CNT_L1_IBUS1_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS1_CONFLICT_CNT field.
	CACHE_L1_IBUS1_ACS_CONFLICT_CNT_L1_IBUS1_CONFLICT_CNT_Msk = 0xffffffff

	// L1_IBUS1_ACS_NXTLVL_RD_CNT: L1-ICache bus1 Next-Level-Access Counter register
	// Position of L1_IBUS1_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_L1_IBUS1_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_IBUS1_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_L1_IBUS1_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_IBUS2_ACS_HIT_CNT: L1-ICache bus2 Hit-Access Counter register
	// Position of L1_IBUS2_HIT_CNT field.
	CACHE_L1_IBUS2_ACS_HIT_CNT_L1_IBUS2_HIT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS2_HIT_CNT field.
	CACHE_L1_IBUS2_ACS_HIT_CNT_L1_IBUS2_HIT_CNT_Msk = 0xffffffff

	// L1_IBUS2_ACS_MISS_CNT: L1-ICache bus2 Miss-Access Counter register
	// Position of L1_IBUS2_MISS_CNT field.
	CACHE_L1_IBUS2_ACS_MISS_CNT_L1_IBUS2_MISS_CNT_Pos = 0x0
	// Bit mask of L1_IBUS2_MISS_CNT field.
	CACHE_L1_IBUS2_ACS_MISS_CNT_L1_IBUS2_MISS_CNT_Msk = 0xffffffff

	// L1_IBUS2_ACS_CONFLICT_CNT: L1-ICache bus2 Conflict-Access Counter register
	// Position of L1_IBUS2_CONFLICT_CNT field.
	CACHE_L1_IBUS2_ACS_CONFLICT_CNT_L1_IBUS2_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS2_CONFLICT_CNT field.
	CACHE_L1_IBUS2_ACS_CONFLICT_CNT_L1_IBUS2_CONFLICT_CNT_Msk = 0xffffffff

	// L1_IBUS2_ACS_NXTLVL_RD_CNT: L1-ICache bus2 Next-Level-Access Counter register
	// Position of L1_IBUS2_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_L1_IBUS2_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_IBUS2_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_L1_IBUS2_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_IBUS3_ACS_HIT_CNT: L1-ICache bus3 Hit-Access Counter register
	// Position of L1_IBUS3_HIT_CNT field.
	CACHE_L1_IBUS3_ACS_HIT_CNT_L1_IBUS3_HIT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS3_HIT_CNT field.
	CACHE_L1_IBUS3_ACS_HIT_CNT_L1_IBUS3_HIT_CNT_Msk = 0xffffffff

	// L1_IBUS3_ACS_MISS_CNT: L1-ICache bus3 Miss-Access Counter register
	// Position of L1_IBUS3_MISS_CNT field.
	CACHE_L1_IBUS3_ACS_MISS_CNT_L1_IBUS3_MISS_CNT_Pos = 0x0
	// Bit mask of L1_IBUS3_MISS_CNT field.
	CACHE_L1_IBUS3_ACS_MISS_CNT_L1_IBUS3_MISS_CNT_Msk = 0xffffffff

	// L1_IBUS3_ACS_CONFLICT_CNT: L1-ICache bus3 Conflict-Access Counter register
	// Position of L1_IBUS3_CONFLICT_CNT field.
	CACHE_L1_IBUS3_ACS_CONFLICT_CNT_L1_IBUS3_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_IBUS3_CONFLICT_CNT field.
	CACHE_L1_IBUS3_ACS_CONFLICT_CNT_L1_IBUS3_CONFLICT_CNT_Msk = 0xffffffff

	// L1_IBUS3_ACS_NXTLVL_RD_CNT: L1-ICache bus3 Next-Level-Access Counter register
	// Position of L1_IBUS3_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_L1_IBUS3_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_IBUS3_NXTLVL_RD_CNT field.
	CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_L1_IBUS3_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_DBUS0_ACS_HIT_CNT: L1-DCache bus0 Hit-Access Counter register
	// Position of L1_DBUS0_HIT_CNT field.
	CACHE_L1_DBUS0_ACS_HIT_CNT_L1_DBUS0_HIT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS0_HIT_CNT field.
	CACHE_L1_DBUS0_ACS_HIT_CNT_L1_DBUS0_HIT_CNT_Msk = 0xffffffff

	// L1_DBUS0_ACS_MISS_CNT: L1-DCache bus0 Miss-Access Counter register
	// Position of L1_DBUS0_MISS_CNT field.
	CACHE_L1_DBUS0_ACS_MISS_CNT_L1_DBUS0_MISS_CNT_Pos = 0x0
	// Bit mask of L1_DBUS0_MISS_CNT field.
	CACHE_L1_DBUS0_ACS_MISS_CNT_L1_DBUS0_MISS_CNT_Msk = 0xffffffff

	// L1_DBUS0_ACS_CONFLICT_CNT: L1-DCache bus0 Conflict-Access Counter register
	// Position of L1_DBUS0_CONFLICT_CNT field.
	CACHE_L1_DBUS0_ACS_CONFLICT_CNT_L1_DBUS0_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS0_CONFLICT_CNT field.
	CACHE_L1_DBUS0_ACS_CONFLICT_CNT_L1_DBUS0_CONFLICT_CNT_Msk = 0xffffffff

	// L1_DBUS0_ACS_NXTLVL_RD_CNT: L1-DCache bus0 Next-Level-Access Counter register
	// Position of L1_DBUS0_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_L1_DBUS0_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_DBUS0_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_L1_DBUS0_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_DBUS0_ACS_NXTLVL_WR_CNT: L1-DCache bus0 WB-Access Counter register
	// Position of L1_DBUS0_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_L1_DBUS0_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L1_DBUS0_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_L1_DBUS0_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L1_DBUS1_ACS_HIT_CNT: L1-DCache bus1 Hit-Access Counter register
	// Position of L1_DBUS1_HIT_CNT field.
	CACHE_L1_DBUS1_ACS_HIT_CNT_L1_DBUS1_HIT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS1_HIT_CNT field.
	CACHE_L1_DBUS1_ACS_HIT_CNT_L1_DBUS1_HIT_CNT_Msk = 0xffffffff

	// L1_DBUS1_ACS_MISS_CNT: L1-DCache bus1 Miss-Access Counter register
	// Position of L1_DBUS1_MISS_CNT field.
	CACHE_L1_DBUS1_ACS_MISS_CNT_L1_DBUS1_MISS_CNT_Pos = 0x0
	// Bit mask of L1_DBUS1_MISS_CNT field.
	CACHE_L1_DBUS1_ACS_MISS_CNT_L1_DBUS1_MISS_CNT_Msk = 0xffffffff

	// L1_DBUS1_ACS_CONFLICT_CNT: L1-DCache bus1 Conflict-Access Counter register
	// Position of L1_DBUS1_CONFLICT_CNT field.
	CACHE_L1_DBUS1_ACS_CONFLICT_CNT_L1_DBUS1_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS1_CONFLICT_CNT field.
	CACHE_L1_DBUS1_ACS_CONFLICT_CNT_L1_DBUS1_CONFLICT_CNT_Msk = 0xffffffff

	// L1_DBUS1_ACS_NXTLVL_RD_CNT: L1-DCache bus1 Next-Level-Access Counter register
	// Position of L1_DBUS1_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_L1_DBUS1_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_DBUS1_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_L1_DBUS1_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_DBUS1_ACS_NXTLVL_WR_CNT: L1-DCache bus1 WB-Access Counter register
	// Position of L1_DBUS1_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_L1_DBUS1_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L1_DBUS1_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_L1_DBUS1_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L1_DBUS2_ACS_HIT_CNT: L1-DCache bus2 Hit-Access Counter register
	// Position of L1_DBUS2_HIT_CNT field.
	CACHE_L1_DBUS2_ACS_HIT_CNT_L1_DBUS2_HIT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS2_HIT_CNT field.
	CACHE_L1_DBUS2_ACS_HIT_CNT_L1_DBUS2_HIT_CNT_Msk = 0xffffffff

	// L1_DBUS2_ACS_MISS_CNT: L1-DCache bus2 Miss-Access Counter register
	// Position of L1_DBUS2_MISS_CNT field.
	CACHE_L1_DBUS2_ACS_MISS_CNT_L1_DBUS2_MISS_CNT_Pos = 0x0
	// Bit mask of L1_DBUS2_MISS_CNT field.
	CACHE_L1_DBUS2_ACS_MISS_CNT_L1_DBUS2_MISS_CNT_Msk = 0xffffffff

	// L1_DBUS2_ACS_CONFLICT_CNT: L1-DCache bus2 Conflict-Access Counter register
	// Position of L1_DBUS2_CONFLICT_CNT field.
	CACHE_L1_DBUS2_ACS_CONFLICT_CNT_L1_DBUS2_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS2_CONFLICT_CNT field.
	CACHE_L1_DBUS2_ACS_CONFLICT_CNT_L1_DBUS2_CONFLICT_CNT_Msk = 0xffffffff

	// L1_DBUS2_ACS_NXTLVL_RD_CNT: L1-DCache bus2 Next-Level-Access Counter register
	// Position of L1_DBUS2_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_L1_DBUS2_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_DBUS2_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_L1_DBUS2_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_DBUS2_ACS_NXTLVL_WR_CNT: L1-DCache bus2 WB-Access Counter register
	// Position of L1_DBUS2_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_L1_DBUS2_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L1_DBUS2_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_L1_DBUS2_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L1_DBUS3_ACS_HIT_CNT: L1-DCache bus3 Hit-Access Counter register
	// Position of L1_DBUS3_HIT_CNT field.
	CACHE_L1_DBUS3_ACS_HIT_CNT_L1_DBUS3_HIT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS3_HIT_CNT field.
	CACHE_L1_DBUS3_ACS_HIT_CNT_L1_DBUS3_HIT_CNT_Msk = 0xffffffff

	// L1_DBUS3_ACS_MISS_CNT: L1-DCache bus3 Miss-Access Counter register
	// Position of L1_DBUS3_MISS_CNT field.
	CACHE_L1_DBUS3_ACS_MISS_CNT_L1_DBUS3_MISS_CNT_Pos = 0x0
	// Bit mask of L1_DBUS3_MISS_CNT field.
	CACHE_L1_DBUS3_ACS_MISS_CNT_L1_DBUS3_MISS_CNT_Msk = 0xffffffff

	// L1_DBUS3_ACS_CONFLICT_CNT: L1-DCache bus3 Conflict-Access Counter register
	// Position of L1_DBUS3_CONFLICT_CNT field.
	CACHE_L1_DBUS3_ACS_CONFLICT_CNT_L1_DBUS3_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L1_DBUS3_CONFLICT_CNT field.
	CACHE_L1_DBUS3_ACS_CONFLICT_CNT_L1_DBUS3_CONFLICT_CNT_Msk = 0xffffffff

	// L1_DBUS3_ACS_NXTLVL_RD_CNT: L1-DCache bus3 Next-Level-Access Counter register
	// Position of L1_DBUS3_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_L1_DBUS3_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L1_DBUS3_NXTLVL_RD_CNT field.
	CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_L1_DBUS3_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L1_DBUS3_ACS_NXTLVL_WR_CNT: L1-DCache bus3 WB-Access Counter register
	// Position of L1_DBUS3_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_L1_DBUS3_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L1_DBUS3_NXTLVL_WR_CNT field.
	CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_L1_DBUS3_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L1_ICACHE0_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
	// Position of L1_ICACHE0_FAIL_ID field.
	CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID_Pos = 0x0
	// Bit mask of L1_ICACHE0_FAIL_ID field.
	CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ID_Msk = 0xffff
	// Position of L1_ICACHE0_FAIL_ATTR field.
	CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR_Pos = 0x10
	// Bit mask of L1_ICACHE0_FAIL_ATTR field.
	CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_L1_ICACHE0_FAIL_ATTR_Msk = 0xffff0000

	// L1_ICACHE0_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
	// Position of L1_ICACHE0_FAIL_ADDR field.
	CACHE_L1_ICACHE0_ACS_FAIL_ADDR_L1_ICACHE0_FAIL_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE0_FAIL_ADDR field.
	CACHE_L1_ICACHE0_ACS_FAIL_ADDR_L1_ICACHE0_FAIL_ADDR_Msk = 0xffffffff

	// L1_ICACHE1_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
	// Position of L1_ICACHE1_FAIL_ID field.
	CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID_Pos = 0x0
	// Bit mask of L1_ICACHE1_FAIL_ID field.
	CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ID_Msk = 0xffff
	// Position of L1_ICACHE1_FAIL_ATTR field.
	CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR_Pos = 0x10
	// Bit mask of L1_ICACHE1_FAIL_ATTR field.
	CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_L1_ICACHE1_FAIL_ATTR_Msk = 0xffff0000

	// L1_ICACHE1_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
	// Position of L1_ICACHE1_FAIL_ADDR field.
	CACHE_L1_ICACHE1_ACS_FAIL_ADDR_L1_ICACHE1_FAIL_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE1_FAIL_ADDR field.
	CACHE_L1_ICACHE1_ACS_FAIL_ADDR_L1_ICACHE1_FAIL_ADDR_Msk = 0xffffffff

	// L1_ICACHE2_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
	// Position of L1_ICACHE2_FAIL_ID field.
	CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID_Pos = 0x0
	// Bit mask of L1_ICACHE2_FAIL_ID field.
	CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ID_Msk = 0xffff
	// Position of L1_ICACHE2_FAIL_ATTR field.
	CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR_Pos = 0x10
	// Bit mask of L1_ICACHE2_FAIL_ATTR field.
	CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_L1_ICACHE2_FAIL_ATTR_Msk = 0xffff0000

	// L1_ICACHE2_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
	// Position of L1_ICACHE2_FAIL_ADDR field.
	CACHE_L1_ICACHE2_ACS_FAIL_ADDR_L1_ICACHE2_FAIL_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE2_FAIL_ADDR field.
	CACHE_L1_ICACHE2_ACS_FAIL_ADDR_L1_ICACHE2_FAIL_ADDR_Msk = 0xffffffff

	// L1_ICACHE3_ACS_FAIL_ID_ATTR: L1-ICache0 Access Fail ID/attribution information register
	// Position of L1_ICACHE3_FAIL_ID field.
	CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID_Pos = 0x0
	// Bit mask of L1_ICACHE3_FAIL_ID field.
	CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ID_Msk = 0xffff
	// Position of L1_ICACHE3_FAIL_ATTR field.
	CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR_Pos = 0x10
	// Bit mask of L1_ICACHE3_FAIL_ATTR field.
	CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_L1_ICACHE3_FAIL_ATTR_Msk = 0xffff0000

	// L1_ICACHE3_ACS_FAIL_ADDR: L1-ICache0 Access Fail Address information register
	// Position of L1_ICACHE3_FAIL_ADDR field.
	CACHE_L1_ICACHE3_ACS_FAIL_ADDR_L1_ICACHE3_FAIL_ADDR_Pos = 0x0
	// Bit mask of L1_ICACHE3_FAIL_ADDR field.
	CACHE_L1_ICACHE3_ACS_FAIL_ADDR_L1_ICACHE3_FAIL_ADDR_Msk = 0xffffffff

	// L1_DCACHE_ACS_FAIL_ID_ATTR: L1-DCache Access Fail ID/attribution information register
	// Position of L1_DCACHE_FAIL_ID field.
	CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ID_Pos = 0x0
	// Bit mask of L1_DCACHE_FAIL_ID field.
	CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ID_Msk = 0xffff
	// Position of L1_DCACHE_FAIL_ATTR field.
	CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ATTR_Pos = 0x10
	// Bit mask of L1_DCACHE_FAIL_ATTR field.
	CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_L1_DCACHE_FAIL_ATTR_Msk = 0xffff0000

	// L1_DCACHE_ACS_FAIL_ADDR: L1-DCache Access Fail Address information register
	// Position of L1_DCACHE_FAIL_ADDR field.
	CACHE_L1_DCACHE_ACS_FAIL_ADDR_L1_DCACHE_FAIL_ADDR_Pos = 0x0
	// Bit mask of L1_DCACHE_FAIL_ADDR field.
	CACHE_L1_DCACHE_ACS_FAIL_ADDR_L1_DCACHE_FAIL_ADDR_Msk = 0xffffffff

	// SYNC_L1_CACHE_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register
	// Position of L1_ICACHE0_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA_Pos = 0x0
	// Bit mask of L1_ICACHE0_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA_Msk = 0x1
	// Bit L1_ICACHE0_PLD_DONE_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_DONE_INT_ENA = 0x1
	// Position of L1_ICACHE1_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA_Pos = 0x1
	// Bit mask of L1_ICACHE1_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA_Msk = 0x2
	// Bit L1_ICACHE1_PLD_DONE_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_DONE_INT_ENA = 0x2
	// Position of L1_ICACHE2_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA_Pos = 0x2
	// Bit mask of L1_ICACHE2_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA_Msk = 0x4
	// Bit L1_ICACHE2_PLD_DONE_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_DONE_INT_ENA = 0x4
	// Position of L1_ICACHE3_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA_Pos = 0x3
	// Bit mask of L1_ICACHE3_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA_Msk = 0x8
	// Bit L1_ICACHE3_PLD_DONE_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_DONE_INT_ENA = 0x8
	// Position of L1_DCACHE_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_DONE_INT_ENA_Pos = 0x4
	// Bit mask of L1_DCACHE_PLD_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_DONE_INT_ENA_Msk = 0x10
	// Bit L1_DCACHE_PLD_DONE_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_DONE_INT_ENA = 0x10
	// Position of SYNC_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_DONE_INT_ENA_Pos = 0x6
	// Bit mask of SYNC_DONE_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_DONE_INT_ENA_Msk = 0x40
	// Bit SYNC_DONE_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_DONE_INT_ENA = 0x40
	// Position of L1_ICACHE0_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA_Pos = 0x7
	// Bit mask of L1_ICACHE0_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA_Msk = 0x80
	// Bit L1_ICACHE0_PLD_ERR_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE0_PLD_ERR_INT_ENA = 0x80
	// Position of L1_ICACHE1_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA_Pos = 0x8
	// Bit mask of L1_ICACHE1_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA_Msk = 0x100
	// Bit L1_ICACHE1_PLD_ERR_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE1_PLD_ERR_INT_ENA = 0x100
	// Position of L1_ICACHE2_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA_Pos = 0x9
	// Bit mask of L1_ICACHE2_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA_Msk = 0x200
	// Bit L1_ICACHE2_PLD_ERR_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE2_PLD_ERR_INT_ENA = 0x200
	// Position of L1_ICACHE3_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA_Pos = 0xa
	// Bit mask of L1_ICACHE3_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA_Msk = 0x400
	// Bit L1_ICACHE3_PLD_ERR_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_ICACHE3_PLD_ERR_INT_ENA = 0x400
	// Position of L1_DCACHE_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_ERR_INT_ENA_Pos = 0xb
	// Bit mask of L1_DCACHE_PLD_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_ERR_INT_ENA_Msk = 0x800
	// Bit L1_DCACHE_PLD_ERR_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_L1_DCACHE_PLD_ERR_INT_ENA = 0x800
	// Position of SYNC_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_ERR_INT_ENA_Pos = 0xd
	// Bit mask of SYNC_ERR_INT_ENA field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_ERR_INT_ENA_Msk = 0x2000
	// Bit SYNC_ERR_INT_ENA.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_SYNC_ERR_INT_ENA = 0x2000

	// SYNC_L1_CACHE_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register
	// Position of L1_ICACHE0_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR_Pos = 0x0
	// Bit mask of L1_ICACHE0_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR_Msk = 0x1
	// Bit L1_ICACHE0_PLD_DONE_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_DONE_INT_CLR = 0x1
	// Position of L1_ICACHE1_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR_Pos = 0x1
	// Bit mask of L1_ICACHE1_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR_Msk = 0x2
	// Bit L1_ICACHE1_PLD_DONE_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_DONE_INT_CLR = 0x2
	// Position of L1_ICACHE2_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR_Pos = 0x2
	// Bit mask of L1_ICACHE2_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR_Msk = 0x4
	// Bit L1_ICACHE2_PLD_DONE_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_DONE_INT_CLR = 0x4
	// Position of L1_ICACHE3_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR_Pos = 0x3
	// Bit mask of L1_ICACHE3_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR_Msk = 0x8
	// Bit L1_ICACHE3_PLD_DONE_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_DONE_INT_CLR = 0x8
	// Position of L1_DCACHE_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_DONE_INT_CLR_Pos = 0x4
	// Bit mask of L1_DCACHE_PLD_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_DONE_INT_CLR_Msk = 0x10
	// Bit L1_DCACHE_PLD_DONE_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_DONE_INT_CLR = 0x10
	// Position of SYNC_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_DONE_INT_CLR_Pos = 0x6
	// Bit mask of SYNC_DONE_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_DONE_INT_CLR_Msk = 0x40
	// Bit SYNC_DONE_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_DONE_INT_CLR = 0x40
	// Position of L1_ICACHE0_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR_Pos = 0x7
	// Bit mask of L1_ICACHE0_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR_Msk = 0x80
	// Bit L1_ICACHE0_PLD_ERR_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE0_PLD_ERR_INT_CLR = 0x80
	// Position of L1_ICACHE1_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR_Pos = 0x8
	// Bit mask of L1_ICACHE1_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR_Msk = 0x100
	// Bit L1_ICACHE1_PLD_ERR_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE1_PLD_ERR_INT_CLR = 0x100
	// Position of L1_ICACHE2_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR_Pos = 0x9
	// Bit mask of L1_ICACHE2_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR_Msk = 0x200
	// Bit L1_ICACHE2_PLD_ERR_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE2_PLD_ERR_INT_CLR = 0x200
	// Position of L1_ICACHE3_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR_Pos = 0xa
	// Bit mask of L1_ICACHE3_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR_Msk = 0x400
	// Bit L1_ICACHE3_PLD_ERR_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_ICACHE3_PLD_ERR_INT_CLR = 0x400
	// Position of L1_DCACHE_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_ERR_INT_CLR_Pos = 0xb
	// Bit mask of L1_DCACHE_PLD_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_ERR_INT_CLR_Msk = 0x800
	// Bit L1_DCACHE_PLD_ERR_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_L1_DCACHE_PLD_ERR_INT_CLR = 0x800
	// Position of SYNC_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_ERR_INT_CLR_Pos = 0xd
	// Bit mask of SYNC_ERR_INT_CLR field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_ERR_INT_CLR_Msk = 0x2000
	// Bit SYNC_ERR_INT_CLR.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_SYNC_ERR_INT_CLR = 0x2000

	// SYNC_L1_CACHE_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register
	// Position of L1_ICACHE0_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW_Pos = 0x0
	// Bit mask of L1_ICACHE0_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW_Msk = 0x1
	// Bit L1_ICACHE0_PLD_DONE_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_DONE_INT_RAW = 0x1
	// Position of L1_ICACHE1_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW_Pos = 0x1
	// Bit mask of L1_ICACHE1_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW_Msk = 0x2
	// Bit L1_ICACHE1_PLD_DONE_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_DONE_INT_RAW = 0x2
	// Position of L1_ICACHE2_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW_Pos = 0x2
	// Bit mask of L1_ICACHE2_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW_Msk = 0x4
	// Bit L1_ICACHE2_PLD_DONE_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_DONE_INT_RAW = 0x4
	// Position of L1_ICACHE3_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW_Pos = 0x3
	// Bit mask of L1_ICACHE3_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW_Msk = 0x8
	// Bit L1_ICACHE3_PLD_DONE_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_DONE_INT_RAW = 0x8
	// Position of L1_DCACHE_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_DONE_INT_RAW_Pos = 0x4
	// Bit mask of L1_DCACHE_PLD_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_DONE_INT_RAW_Msk = 0x10
	// Bit L1_DCACHE_PLD_DONE_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_DONE_INT_RAW = 0x10
	// Position of SYNC_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_DONE_INT_RAW_Pos = 0x6
	// Bit mask of SYNC_DONE_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_DONE_INT_RAW_Msk = 0x40
	// Bit SYNC_DONE_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_DONE_INT_RAW = 0x40
	// Position of L1_ICACHE0_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW_Pos = 0x7
	// Bit mask of L1_ICACHE0_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW_Msk = 0x80
	// Bit L1_ICACHE0_PLD_ERR_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE0_PLD_ERR_INT_RAW = 0x80
	// Position of L1_ICACHE1_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW_Pos = 0x8
	// Bit mask of L1_ICACHE1_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW_Msk = 0x100
	// Bit L1_ICACHE1_PLD_ERR_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE1_PLD_ERR_INT_RAW = 0x100
	// Position of L1_ICACHE2_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW_Pos = 0x9
	// Bit mask of L1_ICACHE2_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW_Msk = 0x200
	// Bit L1_ICACHE2_PLD_ERR_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE2_PLD_ERR_INT_RAW = 0x200
	// Position of L1_ICACHE3_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW_Pos = 0xa
	// Bit mask of L1_ICACHE3_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW_Msk = 0x400
	// Bit L1_ICACHE3_PLD_ERR_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_ICACHE3_PLD_ERR_INT_RAW = 0x400
	// Position of L1_DCACHE_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_ERR_INT_RAW_Pos = 0xb
	// Bit mask of L1_DCACHE_PLD_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_ERR_INT_RAW_Msk = 0x800
	// Bit L1_DCACHE_PLD_ERR_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_L1_DCACHE_PLD_ERR_INT_RAW = 0x800
	// Position of SYNC_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_ERR_INT_RAW_Pos = 0xd
	// Bit mask of SYNC_ERR_INT_RAW field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_ERR_INT_RAW_Msk = 0x2000
	// Bit SYNC_ERR_INT_RAW.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_SYNC_ERR_INT_RAW = 0x2000

	// SYNC_L1_CACHE_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register
	// Position of L1_ICACHE0_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST_Pos = 0x0
	// Bit mask of L1_ICACHE0_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST_Msk = 0x1
	// Bit L1_ICACHE0_PLD_DONE_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_DONE_INT_ST = 0x1
	// Position of L1_ICACHE1_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST_Pos = 0x1
	// Bit mask of L1_ICACHE1_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST_Msk = 0x2
	// Bit L1_ICACHE1_PLD_DONE_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_DONE_INT_ST = 0x2
	// Position of L1_ICACHE2_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST_Pos = 0x2
	// Bit mask of L1_ICACHE2_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST_Msk = 0x4
	// Bit L1_ICACHE2_PLD_DONE_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_DONE_INT_ST = 0x4
	// Position of L1_ICACHE3_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST_Pos = 0x3
	// Bit mask of L1_ICACHE3_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST_Msk = 0x8
	// Bit L1_ICACHE3_PLD_DONE_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_DONE_INT_ST = 0x8
	// Position of L1_DCACHE_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_DONE_INT_ST_Pos = 0x4
	// Bit mask of L1_DCACHE_PLD_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_DONE_INT_ST_Msk = 0x10
	// Bit L1_DCACHE_PLD_DONE_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_DONE_INT_ST = 0x10
	// Position of SYNC_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_DONE_INT_ST_Pos = 0x6
	// Bit mask of SYNC_DONE_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_DONE_INT_ST_Msk = 0x40
	// Bit SYNC_DONE_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_DONE_INT_ST = 0x40
	// Position of L1_ICACHE0_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST_Pos = 0x7
	// Bit mask of L1_ICACHE0_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST_Msk = 0x80
	// Bit L1_ICACHE0_PLD_ERR_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE0_PLD_ERR_INT_ST = 0x80
	// Position of L1_ICACHE1_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST_Pos = 0x8
	// Bit mask of L1_ICACHE1_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST_Msk = 0x100
	// Bit L1_ICACHE1_PLD_ERR_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE1_PLD_ERR_INT_ST = 0x100
	// Position of L1_ICACHE2_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST_Pos = 0x9
	// Bit mask of L1_ICACHE2_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST_Msk = 0x200
	// Bit L1_ICACHE2_PLD_ERR_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE2_PLD_ERR_INT_ST = 0x200
	// Position of L1_ICACHE3_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST_Pos = 0xa
	// Bit mask of L1_ICACHE3_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST_Msk = 0x400
	// Bit L1_ICACHE3_PLD_ERR_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_ICACHE3_PLD_ERR_INT_ST = 0x400
	// Position of L1_DCACHE_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_ERR_INT_ST_Pos = 0xb
	// Bit mask of L1_DCACHE_PLD_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_ERR_INT_ST_Msk = 0x800
	// Bit L1_DCACHE_PLD_ERR_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_L1_DCACHE_PLD_ERR_INT_ST = 0x800
	// Position of SYNC_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_ERR_INT_ST_Pos = 0xd
	// Bit mask of SYNC_ERR_INT_ST field.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_ERR_INT_ST_Msk = 0x2000
	// Bit SYNC_ERR_INT_ST.
	CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_SYNC_ERR_INT_ST = 0x2000

	// SYNC_L1_CACHE_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register
	// Position of L1_ICACHE0_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE_Pos = 0x0
	// Bit mask of L1_ICACHE0_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE0_PLD_ERR_CODE_Msk = 0x3
	// Position of L1_ICACHE1_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE_Pos = 0x2
	// Bit mask of L1_ICACHE1_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE1_PLD_ERR_CODE_Msk = 0xc
	// Position of L1_ICACHE2_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE_Pos = 0x4
	// Bit mask of L1_ICACHE2_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE2_PLD_ERR_CODE_Msk = 0x30
	// Position of L1_ICACHE3_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE_Pos = 0x6
	// Bit mask of L1_ICACHE3_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_ICACHE3_PLD_ERR_CODE_Msk = 0xc0
	// Position of L1_DCACHE_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_DCACHE_PLD_ERR_CODE_Pos = 0x8
	// Bit mask of L1_DCACHE_PLD_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_L1_DCACHE_PLD_ERR_CODE_Msk = 0x300
	// Position of SYNC_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_SYNC_ERR_CODE_Pos = 0xc
	// Bit mask of SYNC_ERR_CODE field.
	CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_SYNC_ERR_CODE_Msk = 0x3000

	// L1_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register
	// Position of L1_ICACHE0_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST_Pos = 0x0
	// Bit mask of L1_ICACHE0_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST_Msk = 0x1
	// Bit L1_ICACHE0_SYNC_RST.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE0_SYNC_RST = 0x1
	// Position of L1_ICACHE1_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST_Pos = 0x1
	// Bit mask of L1_ICACHE1_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST_Msk = 0x2
	// Bit L1_ICACHE1_SYNC_RST.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE1_SYNC_RST = 0x2
	// Position of L1_ICACHE2_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST_Pos = 0x2
	// Bit mask of L1_ICACHE2_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST_Msk = 0x4
	// Bit L1_ICACHE2_SYNC_RST.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE2_SYNC_RST = 0x4
	// Position of L1_ICACHE3_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST_Pos = 0x3
	// Bit mask of L1_ICACHE3_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST_Msk = 0x8
	// Bit L1_ICACHE3_SYNC_RST.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_ICACHE3_SYNC_RST = 0x8
	// Position of L1_DCACHE_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_DCACHE_SYNC_RST_Pos = 0x4
	// Bit mask of L1_DCACHE_SYNC_RST field.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_DCACHE_SYNC_RST_Msk = 0x10
	// Bit L1_DCACHE_SYNC_RST.
	CACHE_L1_CACHE_SYNC_RST_CTRL_L1_DCACHE_SYNC_RST = 0x10

	// L1_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register
	// Position of L1_ICACHE0_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST_Pos = 0x0
	// Bit mask of L1_ICACHE0_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST_Msk = 0x1
	// Bit L1_ICACHE0_PLD_RST.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE0_PLD_RST = 0x1
	// Position of L1_ICACHE1_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST_Pos = 0x1
	// Bit mask of L1_ICACHE1_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST_Msk = 0x2
	// Bit L1_ICACHE1_PLD_RST.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE1_PLD_RST = 0x2
	// Position of L1_ICACHE2_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST_Pos = 0x2
	// Bit mask of L1_ICACHE2_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST_Msk = 0x4
	// Bit L1_ICACHE2_PLD_RST.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE2_PLD_RST = 0x4
	// Position of L1_ICACHE3_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST_Pos = 0x3
	// Bit mask of L1_ICACHE3_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST_Msk = 0x8
	// Bit L1_ICACHE3_PLD_RST.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_ICACHE3_PLD_RST = 0x8
	// Position of L1_DCACHE_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_DCACHE_PLD_RST_Pos = 0x4
	// Bit mask of L1_DCACHE_PLD_RST field.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_DCACHE_PLD_RST_Msk = 0x10
	// Bit L1_DCACHE_PLD_RST.
	CACHE_L1_CACHE_PRELOAD_RST_CTRL_L1_DCACHE_PLD_RST = 0x10

	// L1_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register
	// Position of L1_ICACHE0_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR_Pos = 0x0
	// Bit mask of L1_ICACHE0_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR_Msk = 0x1
	// Bit L1_ICACHE0_ALD_BUF_CLR.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE0_ALD_BUF_CLR = 0x1
	// Position of L1_ICACHE1_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR_Pos = 0x1
	// Bit mask of L1_ICACHE1_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR_Msk = 0x2
	// Bit L1_ICACHE1_ALD_BUF_CLR.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE1_ALD_BUF_CLR = 0x2
	// Position of L1_ICACHE2_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR_Pos = 0x2
	// Bit mask of L1_ICACHE2_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR_Msk = 0x4
	// Bit L1_ICACHE2_ALD_BUF_CLR.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE2_ALD_BUF_CLR = 0x4
	// Position of L1_ICACHE3_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR_Pos = 0x3
	// Bit mask of L1_ICACHE3_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR_Msk = 0x8
	// Bit L1_ICACHE3_ALD_BUF_CLR.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_ICACHE3_ALD_BUF_CLR = 0x8
	// Position of L1_DCACHE_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_DCACHE_ALD_BUF_CLR_Pos = 0x4
	// Bit mask of L1_DCACHE_ALD_BUF_CLR field.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_DCACHE_ALD_BUF_CLR_Msk = 0x10
	// Bit L1_DCACHE_ALD_BUF_CLR.
	CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_L1_DCACHE_ALD_BUF_CLR = 0x10

	// L1_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers
	// Position of L1_ICACHE0_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR_Pos = 0x0
	// Bit mask of L1_ICACHE0_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR_Msk = 0x1
	// Bit L1_ICACHE0_UNALLOC_CLR.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE0_UNALLOC_CLR = 0x1
	// Position of L1_ICACHE1_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR_Pos = 0x1
	// Bit mask of L1_ICACHE1_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR_Msk = 0x2
	// Bit L1_ICACHE1_UNALLOC_CLR.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE1_UNALLOC_CLR = 0x2
	// Position of L1_ICACHE2_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR_Pos = 0x2
	// Bit mask of L1_ICACHE2_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR_Msk = 0x4
	// Bit L1_ICACHE2_UNALLOC_CLR.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE2_UNALLOC_CLR = 0x4
	// Position of L1_ICACHE3_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR_Pos = 0x3
	// Bit mask of L1_ICACHE3_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR_Msk = 0x8
	// Bit L1_ICACHE3_UNALLOC_CLR.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_ICACHE3_UNALLOC_CLR = 0x8
	// Position of L1_DCACHE_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_DCACHE_UNALLOC_CLR_Pos = 0x4
	// Bit mask of L1_DCACHE_UNALLOC_CLR field.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_DCACHE_UNALLOC_CLR_Msk = 0x10
	// Bit L1_DCACHE_UNALLOC_CLR.
	CACHE_L1_UNALLOCATE_BUFFER_CLEAR_L1_DCACHE_UNALLOC_CLR = 0x10

	// L1_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register
	// Position of L1_ICACHE0_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT_Pos = 0x0
	// Bit mask of L1_ICACHE0_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT_Msk = 0x1
	// Bit L1_ICACHE0_TAG_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_TAG_OBJECT = 0x1
	// Position of L1_ICACHE1_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT_Pos = 0x1
	// Bit mask of L1_ICACHE1_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT_Msk = 0x2
	// Bit L1_ICACHE1_TAG_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_TAG_OBJECT = 0x2
	// Position of L1_ICACHE2_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT_Pos = 0x2
	// Bit mask of L1_ICACHE2_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT_Msk = 0x4
	// Bit L1_ICACHE2_TAG_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_TAG_OBJECT = 0x4
	// Position of L1_ICACHE3_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT_Pos = 0x3
	// Bit mask of L1_ICACHE3_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT_Msk = 0x8
	// Bit L1_ICACHE3_TAG_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_TAG_OBJECT = 0x8
	// Position of L1_DCACHE_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_DCACHE_TAG_OBJECT_Pos = 0x4
	// Bit mask of L1_DCACHE_TAG_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_DCACHE_TAG_OBJECT_Msk = 0x10
	// Bit L1_DCACHE_TAG_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_DCACHE_TAG_OBJECT = 0x10
	// Position of L1_ICACHE0_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT_Pos = 0x6
	// Bit mask of L1_ICACHE0_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT_Msk = 0x40
	// Bit L1_ICACHE0_MEM_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE0_MEM_OBJECT = 0x40
	// Position of L1_ICACHE1_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT_Pos = 0x7
	// Bit mask of L1_ICACHE1_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT_Msk = 0x80
	// Bit L1_ICACHE1_MEM_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE1_MEM_OBJECT = 0x80
	// Position of L1_ICACHE2_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT_Pos = 0x8
	// Bit mask of L1_ICACHE2_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT_Msk = 0x100
	// Bit L1_ICACHE2_MEM_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE2_MEM_OBJECT = 0x100
	// Position of L1_ICACHE3_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT_Pos = 0x9
	// Bit mask of L1_ICACHE3_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT_Msk = 0x200
	// Bit L1_ICACHE3_MEM_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_ICACHE3_MEM_OBJECT = 0x200
	// Position of L1_DCACHE_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_DCACHE_MEM_OBJECT_Pos = 0xa
	// Bit mask of L1_DCACHE_MEM_OBJECT field.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_DCACHE_MEM_OBJECT_Msk = 0x400
	// Bit L1_DCACHE_MEM_OBJECT.
	CACHE_L1_CACHE_OBJECT_CTRL_L1_DCACHE_MEM_OBJECT = 0x400

	// L1_CACHE_WAY_OBJECT: Cache Tag and Data memory way register
	// Position of L1_CACHE_WAY_OBJECT field.
	CACHE_L1_CACHE_WAY_OBJECT_L1_CACHE_WAY_OBJECT_Pos = 0x0
	// Bit mask of L1_CACHE_WAY_OBJECT field.
	CACHE_L1_CACHE_WAY_OBJECT_L1_CACHE_WAY_OBJECT_Msk = 0x7

	// L1_CACHE_VADDR: Cache Vaddr register
	// Position of L1_CACHE_VADDR field.
	CACHE_L1_CACHE_VADDR_L1_CACHE_VADDR_Pos = 0x0
	// Bit mask of L1_CACHE_VADDR field.
	CACHE_L1_CACHE_VADDR_L1_CACHE_VADDR_Msk = 0xffffffff

	// L1_CACHE_DEBUG_BUS: Cache Tag/data memory content register
	// Position of L1_CACHE_DEBUG_BUS field.
	CACHE_L1_CACHE_DEBUG_BUS_L1_CACHE_DEBUG_BUS_Pos = 0x0
	// Bit mask of L1_CACHE_DEBUG_BUS field.
	CACHE_L1_CACHE_DEBUG_BUS_L1_CACHE_DEBUG_BUS_Msk = 0xffffffff

	// LEVEL_SPLIT0: USED TO SPLIT L1 CACHE AND L2 CACHE
	// Position of LEVEL_SPLIT0 field.
	CACHE_LEVEL_SPLIT0_LEVEL_SPLIT0_Pos = 0x0
	// Bit mask of LEVEL_SPLIT0 field.
	CACHE_LEVEL_SPLIT0_LEVEL_SPLIT0_Msk = 0xffffffff

	// L2_CACHE_CTRL: L2 Cache(L2-Cache) control register
	// Position of L2_CACHE_SHUT_DMA field.
	CACHE_L2_CACHE_CTRL_L2_CACHE_SHUT_DMA_Pos = 0x4
	// Bit mask of L2_CACHE_SHUT_DMA field.
	CACHE_L2_CACHE_CTRL_L2_CACHE_SHUT_DMA_Msk = 0x10
	// Bit L2_CACHE_SHUT_DMA.
	CACHE_L2_CACHE_CTRL_L2_CACHE_SHUT_DMA = 0x10
	// Position of L2_CACHE_UNDEF_OP field.
	CACHE_L2_CACHE_CTRL_L2_CACHE_UNDEF_OP_Pos = 0x8
	// Bit mask of L2_CACHE_UNDEF_OP field.
	CACHE_L2_CACHE_CTRL_L2_CACHE_UNDEF_OP_Msk = 0xff00

	// L2_BYPASS_CACHE_CONF: Bypass Cache configure register
	// Position of BYPASS_L2_CACHE_EN field.
	CACHE_L2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN_Pos = 0x5
	// Bit mask of BYPASS_L2_CACHE_EN field.
	CACHE_L2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN_Msk = 0x20
	// Bit BYPASS_L2_CACHE_EN.
	CACHE_L2_BYPASS_CACHE_CONF_BYPASS_L2_CACHE_EN = 0x20

	// L2_CACHE_CACHESIZE_CONF: L2 Cache CacheSize mode configure register
	// Position of L2_CACHE_CACHESIZE_256 field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256_Pos = 0x0
	// Bit mask of L2_CACHE_CACHESIZE_256 field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256_Msk = 0x1
	// Bit L2_CACHE_CACHESIZE_256.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256 = 0x1
	// Position of L2_CACHE_CACHESIZE_512 field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512_Pos = 0x1
	// Bit mask of L2_CACHE_CACHESIZE_512 field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512_Msk = 0x2
	// Bit L2_CACHE_CACHESIZE_512.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512 = 0x2
	// Position of L2_CACHE_CACHESIZE_1K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K_Pos = 0x2
	// Bit mask of L2_CACHE_CACHESIZE_1K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K_Msk = 0x4
	// Bit L2_CACHE_CACHESIZE_1K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1K = 0x4
	// Position of L2_CACHE_CACHESIZE_2K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K_Pos = 0x3
	// Bit mask of L2_CACHE_CACHESIZE_2K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K_Msk = 0x8
	// Bit L2_CACHE_CACHESIZE_2K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_2K = 0x8
	// Position of L2_CACHE_CACHESIZE_4K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K_Pos = 0x4
	// Bit mask of L2_CACHE_CACHESIZE_4K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K_Msk = 0x10
	// Bit L2_CACHE_CACHESIZE_4K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_4K = 0x10
	// Position of L2_CACHE_CACHESIZE_8K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K_Pos = 0x5
	// Bit mask of L2_CACHE_CACHESIZE_8K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K_Msk = 0x20
	// Bit L2_CACHE_CACHESIZE_8K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_8K = 0x20
	// Position of L2_CACHE_CACHESIZE_16K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K_Pos = 0x6
	// Bit mask of L2_CACHE_CACHESIZE_16K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K_Msk = 0x40
	// Bit L2_CACHE_CACHESIZE_16K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_16K = 0x40
	// Position of L2_CACHE_CACHESIZE_32K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K_Pos = 0x7
	// Bit mask of L2_CACHE_CACHESIZE_32K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K_Msk = 0x80
	// Bit L2_CACHE_CACHESIZE_32K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_32K = 0x80
	// Position of L2_CACHE_CACHESIZE_64K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K_Pos = 0x8
	// Bit mask of L2_CACHE_CACHESIZE_64K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K_Msk = 0x100
	// Bit L2_CACHE_CACHESIZE_64K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_64K = 0x100
	// Position of L2_CACHE_CACHESIZE_128K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K_Pos = 0x9
	// Bit mask of L2_CACHE_CACHESIZE_128K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K_Msk = 0x200
	// Bit L2_CACHE_CACHESIZE_128K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_128K = 0x200
	// Position of L2_CACHE_CACHESIZE_256K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K_Pos = 0xa
	// Bit mask of L2_CACHE_CACHESIZE_256K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K_Msk = 0x400
	// Bit L2_CACHE_CACHESIZE_256K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_256K = 0x400
	// Position of L2_CACHE_CACHESIZE_512K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K_Pos = 0xb
	// Bit mask of L2_CACHE_CACHESIZE_512K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K_Msk = 0x800
	// Bit L2_CACHE_CACHESIZE_512K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_512K = 0x800
	// Position of L2_CACHE_CACHESIZE_1024K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K_Pos = 0xc
	// Bit mask of L2_CACHE_CACHESIZE_1024K field.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K_Msk = 0x1000
	// Bit L2_CACHE_CACHESIZE_1024K.
	CACHE_L2_CACHE_CACHESIZE_CONF_L2_CACHE_CACHESIZE_1024K = 0x1000

	// L2_CACHE_BLOCKSIZE_CONF: L2 Cache BlockSize mode configure register
	// Position of L2_CACHE_BLOCKSIZE_8 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8_Pos = 0x0
	// Bit mask of L2_CACHE_BLOCKSIZE_8 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8_Msk = 0x1
	// Bit L2_CACHE_BLOCKSIZE_8.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_8 = 0x1
	// Position of L2_CACHE_BLOCKSIZE_16 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16_Pos = 0x1
	// Bit mask of L2_CACHE_BLOCKSIZE_16 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16_Msk = 0x2
	// Bit L2_CACHE_BLOCKSIZE_16.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_16 = 0x2
	// Position of L2_CACHE_BLOCKSIZE_32 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32_Pos = 0x2
	// Bit mask of L2_CACHE_BLOCKSIZE_32 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32_Msk = 0x4
	// Bit L2_CACHE_BLOCKSIZE_32.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_32 = 0x4
	// Position of L2_CACHE_BLOCKSIZE_64 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64_Pos = 0x3
	// Bit mask of L2_CACHE_BLOCKSIZE_64 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64_Msk = 0x8
	// Bit L2_CACHE_BLOCKSIZE_64.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_64 = 0x8
	// Position of L2_CACHE_BLOCKSIZE_128 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128_Pos = 0x4
	// Bit mask of L2_CACHE_BLOCKSIZE_128 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128_Msk = 0x10
	// Bit L2_CACHE_BLOCKSIZE_128.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_128 = 0x10
	// Position of L2_CACHE_BLOCKSIZE_256 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256_Pos = 0x5
	// Bit mask of L2_CACHE_BLOCKSIZE_256 field.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256_Msk = 0x20
	// Bit L2_CACHE_BLOCKSIZE_256.
	CACHE_L2_CACHE_BLOCKSIZE_CONF_L2_CACHE_BLOCKSIZE_256 = 0x20

	// L2_CACHE_WRAP_AROUND_CTRL: Cache wrap around control register
	// Position of L2_CACHE_WRAP field.
	CACHE_L2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP_Pos = 0x5
	// Bit mask of L2_CACHE_WRAP field.
	CACHE_L2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP_Msk = 0x20
	// Bit L2_CACHE_WRAP.
	CACHE_L2_CACHE_WRAP_AROUND_CTRL_L2_CACHE_WRAP = 0x20

	// L2_CACHE_TAG_MEM_POWER_CTRL: Cache tag memory power control register
	// Position of L2_CACHE_TAG_MEM_FORCE_ON field.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON_Pos = 0x14
	// Bit mask of L2_CACHE_TAG_MEM_FORCE_ON field.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON_Msk = 0x100000
	// Bit L2_CACHE_TAG_MEM_FORCE_ON.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_ON = 0x100000
	// Position of L2_CACHE_TAG_MEM_FORCE_PD field.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD_Pos = 0x15
	// Bit mask of L2_CACHE_TAG_MEM_FORCE_PD field.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD_Msk = 0x200000
	// Bit L2_CACHE_TAG_MEM_FORCE_PD.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PD = 0x200000
	// Position of L2_CACHE_TAG_MEM_FORCE_PU field.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU_Pos = 0x16
	// Bit mask of L2_CACHE_TAG_MEM_FORCE_PU field.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU_Msk = 0x400000
	// Bit L2_CACHE_TAG_MEM_FORCE_PU.
	CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_L2_CACHE_TAG_MEM_FORCE_PU = 0x400000

	// L2_CACHE_DATA_MEM_POWER_CTRL: Cache data memory power control register
	// Position of L2_CACHE_DATA_MEM_FORCE_ON field.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON_Pos = 0x14
	// Bit mask of L2_CACHE_DATA_MEM_FORCE_ON field.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON_Msk = 0x100000
	// Bit L2_CACHE_DATA_MEM_FORCE_ON.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_ON = 0x100000
	// Position of L2_CACHE_DATA_MEM_FORCE_PD field.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD_Pos = 0x15
	// Bit mask of L2_CACHE_DATA_MEM_FORCE_PD field.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD_Msk = 0x200000
	// Bit L2_CACHE_DATA_MEM_FORCE_PD.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PD = 0x200000
	// Position of L2_CACHE_DATA_MEM_FORCE_PU field.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU_Pos = 0x16
	// Bit mask of L2_CACHE_DATA_MEM_FORCE_PU field.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU_Msk = 0x400000
	// Bit L2_CACHE_DATA_MEM_FORCE_PU.
	CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_L2_CACHE_DATA_MEM_FORCE_PU = 0x400000

	// L2_CACHE_FREEZE_CTRL: Cache Freeze control register
	// Position of L2_CACHE_FREEZE_EN field.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN_Pos = 0x14
	// Bit mask of L2_CACHE_FREEZE_EN field.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN_Msk = 0x100000
	// Bit L2_CACHE_FREEZE_EN.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_EN = 0x100000
	// Position of L2_CACHE_FREEZE_MODE field.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE_Pos = 0x15
	// Bit mask of L2_CACHE_FREEZE_MODE field.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE_Msk = 0x200000
	// Bit L2_CACHE_FREEZE_MODE.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_MODE = 0x200000
	// Position of L2_CACHE_FREEZE_DONE field.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE_Pos = 0x16
	// Bit mask of L2_CACHE_FREEZE_DONE field.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE_Msk = 0x400000
	// Bit L2_CACHE_FREEZE_DONE.
	CACHE_L2_CACHE_FREEZE_CTRL_L2_CACHE_FREEZE_DONE = 0x400000

	// L2_CACHE_DATA_MEM_ACS_CONF: Cache data memory access configure register
	// Position of L2_CACHE_DATA_MEM_RD_EN field.
	CACHE_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN_Pos = 0x14
	// Bit mask of L2_CACHE_DATA_MEM_RD_EN field.
	CACHE_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN_Msk = 0x100000
	// Bit L2_CACHE_DATA_MEM_RD_EN.
	CACHE_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_RD_EN = 0x100000
	// Position of L2_CACHE_DATA_MEM_WR_EN field.
	CACHE_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN_Pos = 0x15
	// Bit mask of L2_CACHE_DATA_MEM_WR_EN field.
	CACHE_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN_Msk = 0x200000
	// Bit L2_CACHE_DATA_MEM_WR_EN.
	CACHE_L2_CACHE_DATA_MEM_ACS_CONF_L2_CACHE_DATA_MEM_WR_EN = 0x200000

	// L2_CACHE_TAG_MEM_ACS_CONF: Cache tag memory access configure register
	// Position of L2_CACHE_TAG_MEM_RD_EN field.
	CACHE_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN_Pos = 0x14
	// Bit mask of L2_CACHE_TAG_MEM_RD_EN field.
	CACHE_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN_Msk = 0x100000
	// Bit L2_CACHE_TAG_MEM_RD_EN.
	CACHE_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_RD_EN = 0x100000
	// Position of L2_CACHE_TAG_MEM_WR_EN field.
	CACHE_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN_Pos = 0x15
	// Bit mask of L2_CACHE_TAG_MEM_WR_EN field.
	CACHE_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN_Msk = 0x200000
	// Bit L2_CACHE_TAG_MEM_WR_EN.
	CACHE_L2_CACHE_TAG_MEM_ACS_CONF_L2_CACHE_TAG_MEM_WR_EN = 0x200000

	// L2_CACHE_PRELOCK_CONF: L2 Cache prelock configure register
	// Position of L2_CACHE_PRELOCK_SCT0_EN field.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN_Pos = 0x0
	// Bit mask of L2_CACHE_PRELOCK_SCT0_EN field.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN_Msk = 0x1
	// Bit L2_CACHE_PRELOCK_SCT0_EN.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT0_EN = 0x1
	// Position of L2_CACHE_PRELOCK_SCT1_EN field.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN_Pos = 0x1
	// Bit mask of L2_CACHE_PRELOCK_SCT1_EN field.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN_Msk = 0x2
	// Bit L2_CACHE_PRELOCK_SCT1_EN.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_SCT1_EN = 0x2
	// Position of L2_CACHE_PRELOCK_RGID field.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID_Pos = 0x2
	// Bit mask of L2_CACHE_PRELOCK_RGID field.
	CACHE_L2_CACHE_PRELOCK_CONF_L2_CACHE_PRELOCK_RGID_Msk = 0x3c

	// L2_CACHE_PRELOCK_SCT0_ADDR: L2 Cache prelock section0 address configure register
	// Position of L2_CACHE_PRELOCK_SCT0_ADDR field.
	CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_L2_CACHE_PRELOCK_SCT0_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_PRELOCK_SCT0_ADDR field.
	CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_L2_CACHE_PRELOCK_SCT0_ADDR_Msk = 0xffffffff

	// L2_CACHE_PRELOCK_SCT1_ADDR: L2 Cache prelock section1 address configure register
	// Position of L2_CACHE_PRELOCK_SCT1_ADDR field.
	CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_L2_CACHE_PRELOCK_SCT1_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_PRELOCK_SCT1_ADDR field.
	CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_L2_CACHE_PRELOCK_SCT1_ADDR_Msk = 0xffffffff

	// L2_CACHE_PRELOCK_SCT_SIZE: L2 Cache prelock section size configure register
	// Position of L2_CACHE_PRELOCK_SCT0_SIZE field.
	CACHE_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE_Pos = 0x0
	// Bit mask of L2_CACHE_PRELOCK_SCT0_SIZE field.
	CACHE_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT0_SIZE_Msk = 0xffff
	// Position of L2_CACHE_PRELOCK_SCT1_SIZE field.
	CACHE_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE_Pos = 0x10
	// Bit mask of L2_CACHE_PRELOCK_SCT1_SIZE field.
	CACHE_L2_CACHE_PRELOCK_SCT_SIZE_L2_CACHE_PRELOCK_SCT1_SIZE_Msk = 0xffff0000

	// L2_CACHE_PRELOAD_CTRL: L2 Cache preload-operation control register
	// Position of L2_CACHE_PRELOAD_ENA field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA_Pos = 0x0
	// Bit mask of L2_CACHE_PRELOAD_ENA field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA_Msk = 0x1
	// Bit L2_CACHE_PRELOAD_ENA.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ENA = 0x1
	// Position of L2_CACHE_PRELOAD_DONE field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE_Pos = 0x1
	// Bit mask of L2_CACHE_PRELOAD_DONE field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE_Msk = 0x2
	// Bit L2_CACHE_PRELOAD_DONE.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_DONE = 0x2
	// Position of L2_CACHE_PRELOAD_ORDER field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER_Pos = 0x2
	// Bit mask of L2_CACHE_PRELOAD_ORDER field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER_Msk = 0x4
	// Bit L2_CACHE_PRELOAD_ORDER.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_ORDER = 0x4
	// Position of L2_CACHE_PRELOAD_RGID field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID_Pos = 0x3
	// Bit mask of L2_CACHE_PRELOAD_RGID field.
	CACHE_L2_CACHE_PRELOAD_CTRL_L2_CACHE_PRELOAD_RGID_Msk = 0x78

	// L2_CACHE_PRELOAD_ADDR: L2 Cache preload address configure register
	// Position of L2_CACHE_PRELOAD_ADDR field.
	CACHE_L2_CACHE_PRELOAD_ADDR_L2_CACHE_PRELOAD_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_PRELOAD_ADDR field.
	CACHE_L2_CACHE_PRELOAD_ADDR_L2_CACHE_PRELOAD_ADDR_Msk = 0xffffffff

	// L2_CACHE_PRELOAD_SIZE: L2 Cache preload size configure register
	// Position of L2_CACHE_PRELOAD_SIZE field.
	CACHE_L2_CACHE_PRELOAD_SIZE_L2_CACHE_PRELOAD_SIZE_Pos = 0x0
	// Bit mask of L2_CACHE_PRELOAD_SIZE field.
	CACHE_L2_CACHE_PRELOAD_SIZE_L2_CACHE_PRELOAD_SIZE_Msk = 0xffff

	// L2_CACHE_AUTOLOAD_CTRL: L2 Cache autoload-operation control register
	// Position of L2_CACHE_AUTOLOAD_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA_Msk = 0x1
	// Bit L2_CACHE_AUTOLOAD_ENA.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ENA = 0x1
	// Position of L2_CACHE_AUTOLOAD_DONE field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE_Pos = 0x1
	// Bit mask of L2_CACHE_AUTOLOAD_DONE field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE_Msk = 0x2
	// Bit L2_CACHE_AUTOLOAD_DONE.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_DONE = 0x2
	// Position of L2_CACHE_AUTOLOAD_ORDER field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER_Pos = 0x2
	// Bit mask of L2_CACHE_AUTOLOAD_ORDER field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER_Msk = 0x4
	// Bit L2_CACHE_AUTOLOAD_ORDER.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_ORDER = 0x4
	// Position of L2_CACHE_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE_Pos = 0x3
	// Bit mask of L2_CACHE_AUTOLOAD_TRIGGER_MODE field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_TRIGGER_MODE_Msk = 0x18
	// Position of L2_CACHE_AUTOLOAD_SCT0_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA_Pos = 0x8
	// Bit mask of L2_CACHE_AUTOLOAD_SCT0_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA_Msk = 0x100
	// Bit L2_CACHE_AUTOLOAD_SCT0_ENA.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT0_ENA = 0x100
	// Position of L2_CACHE_AUTOLOAD_SCT1_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA_Pos = 0x9
	// Bit mask of L2_CACHE_AUTOLOAD_SCT1_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA_Msk = 0x200
	// Bit L2_CACHE_AUTOLOAD_SCT1_ENA.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT1_ENA = 0x200
	// Position of L2_CACHE_AUTOLOAD_SCT2_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA_Pos = 0xa
	// Bit mask of L2_CACHE_AUTOLOAD_SCT2_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA_Msk = 0x400
	// Bit L2_CACHE_AUTOLOAD_SCT2_ENA.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT2_ENA = 0x400
	// Position of L2_CACHE_AUTOLOAD_SCT3_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA_Pos = 0xb
	// Bit mask of L2_CACHE_AUTOLOAD_SCT3_ENA field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA_Msk = 0x800
	// Bit L2_CACHE_AUTOLOAD_SCT3_ENA.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_SCT3_ENA = 0x800
	// Position of L2_CACHE_AUTOLOAD_RGID field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID_Pos = 0xc
	// Bit mask of L2_CACHE_AUTOLOAD_RGID field.
	CACHE_L2_CACHE_AUTOLOAD_CTRL_L2_CACHE_AUTOLOAD_RGID_Msk = 0xf000

	// L2_CACHE_AUTOLOAD_SCT0_ADDR: L2 Cache autoload section 0 address configure register
	// Position of L2_CACHE_AUTOLOAD_SCT0_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_L2_CACHE_AUTOLOAD_SCT0_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT0_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_L2_CACHE_AUTOLOAD_SCT0_ADDR_Msk = 0xffffffff

	// L2_CACHE_AUTOLOAD_SCT0_SIZE: L2 Cache autoload section 0 size configure register
	// Position of L2_CACHE_AUTOLOAD_SCT0_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_L2_CACHE_AUTOLOAD_SCT0_SIZE_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT0_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_L2_CACHE_AUTOLOAD_SCT0_SIZE_Msk = 0xfffffff

	// L2_CACHE_AUTOLOAD_SCT1_ADDR: L2 Cache autoload section 1 address configure register
	// Position of L2_CACHE_AUTOLOAD_SCT1_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_L2_CACHE_AUTOLOAD_SCT1_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT1_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_L2_CACHE_AUTOLOAD_SCT1_ADDR_Msk = 0xffffffff

	// L2_CACHE_AUTOLOAD_SCT1_SIZE: L2 Cache autoload section 1 size configure register
	// Position of L2_CACHE_AUTOLOAD_SCT1_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_L2_CACHE_AUTOLOAD_SCT1_SIZE_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT1_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_L2_CACHE_AUTOLOAD_SCT1_SIZE_Msk = 0xfffffff

	// L2_CACHE_AUTOLOAD_SCT2_ADDR: L2 Cache autoload section 2 address configure register
	// Position of L2_CACHE_AUTOLOAD_SCT2_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_L2_CACHE_AUTOLOAD_SCT2_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT2_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_L2_CACHE_AUTOLOAD_SCT2_ADDR_Msk = 0xffffffff

	// L2_CACHE_AUTOLOAD_SCT2_SIZE: L2 Cache autoload section 2 size configure register
	// Position of L2_CACHE_AUTOLOAD_SCT2_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_L2_CACHE_AUTOLOAD_SCT2_SIZE_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT2_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_L2_CACHE_AUTOLOAD_SCT2_SIZE_Msk = 0xfffffff

	// L2_CACHE_AUTOLOAD_SCT3_ADDR: L2 Cache autoload section 3 address configure register
	// Position of L2_CACHE_AUTOLOAD_SCT3_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_L2_CACHE_AUTOLOAD_SCT3_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT3_ADDR field.
	CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_L2_CACHE_AUTOLOAD_SCT3_ADDR_Msk = 0xffffffff

	// L2_CACHE_AUTOLOAD_SCT3_SIZE: L2 Cache autoload section 3 size configure register
	// Position of L2_CACHE_AUTOLOAD_SCT3_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_L2_CACHE_AUTOLOAD_SCT3_SIZE_Pos = 0x0
	// Bit mask of L2_CACHE_AUTOLOAD_SCT3_SIZE field.
	CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_L2_CACHE_AUTOLOAD_SCT3_SIZE_Msk = 0xfffffff

	// L2_CACHE_ACS_CNT_INT_ENA: Cache Access Counter Interrupt enable register
	// Position of L2_IBUS0_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA_Pos = 0x8
	// Bit mask of L2_IBUS0_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA_Msk = 0x100
	// Bit L2_IBUS0_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS0_OVF_INT_ENA = 0x100
	// Position of L2_IBUS1_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA_Pos = 0x9
	// Bit mask of L2_IBUS1_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA_Msk = 0x200
	// Bit L2_IBUS1_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS1_OVF_INT_ENA = 0x200
	// Position of L2_IBUS2_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA_Pos = 0xa
	// Bit mask of L2_IBUS2_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA_Msk = 0x400
	// Bit L2_IBUS2_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS2_OVF_INT_ENA = 0x400
	// Position of L2_IBUS3_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA_Pos = 0xb
	// Bit mask of L2_IBUS3_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA_Msk = 0x800
	// Bit L2_IBUS3_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_IBUS3_OVF_INT_ENA = 0x800
	// Position of L2_DBUS0_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA_Pos = 0xc
	// Bit mask of L2_DBUS0_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA_Msk = 0x1000
	// Bit L2_DBUS0_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS0_OVF_INT_ENA = 0x1000
	// Position of L2_DBUS1_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA_Pos = 0xd
	// Bit mask of L2_DBUS1_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA_Msk = 0x2000
	// Bit L2_DBUS1_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS1_OVF_INT_ENA = 0x2000
	// Position of L2_DBUS2_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA_Pos = 0xe
	// Bit mask of L2_DBUS2_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA_Msk = 0x4000
	// Bit L2_DBUS2_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS2_OVF_INT_ENA = 0x4000
	// Position of L2_DBUS3_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA_Pos = 0xf
	// Bit mask of L2_DBUS3_OVF_INT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA_Msk = 0x8000
	// Bit L2_DBUS3_OVF_INT_ENA.
	CACHE_L2_CACHE_ACS_CNT_INT_ENA_L2_DBUS3_OVF_INT_ENA = 0x8000

	// L2_CACHE_ACS_CNT_INT_CLR: Cache Access Counter Interrupt clear register
	// Position of L2_IBUS0_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR_Pos = 0x8
	// Bit mask of L2_IBUS0_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR_Msk = 0x100
	// Bit L2_IBUS0_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS0_OVF_INT_CLR = 0x100
	// Position of L2_IBUS1_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR_Pos = 0x9
	// Bit mask of L2_IBUS1_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR_Msk = 0x200
	// Bit L2_IBUS1_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS1_OVF_INT_CLR = 0x200
	// Position of L2_IBUS2_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR_Pos = 0xa
	// Bit mask of L2_IBUS2_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR_Msk = 0x400
	// Bit L2_IBUS2_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS2_OVF_INT_CLR = 0x400
	// Position of L2_IBUS3_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR_Pos = 0xb
	// Bit mask of L2_IBUS3_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR_Msk = 0x800
	// Bit L2_IBUS3_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_IBUS3_OVF_INT_CLR = 0x800
	// Position of L2_DBUS0_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR_Pos = 0xc
	// Bit mask of L2_DBUS0_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR_Msk = 0x1000
	// Bit L2_DBUS0_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS0_OVF_INT_CLR = 0x1000
	// Position of L2_DBUS1_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR_Pos = 0xd
	// Bit mask of L2_DBUS1_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR_Msk = 0x2000
	// Bit L2_DBUS1_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS1_OVF_INT_CLR = 0x2000
	// Position of L2_DBUS2_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR_Pos = 0xe
	// Bit mask of L2_DBUS2_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR_Msk = 0x4000
	// Bit L2_DBUS2_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS2_OVF_INT_CLR = 0x4000
	// Position of L2_DBUS3_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR_Pos = 0xf
	// Bit mask of L2_DBUS3_OVF_INT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR_Msk = 0x8000
	// Bit L2_DBUS3_OVF_INT_CLR.
	CACHE_L2_CACHE_ACS_CNT_INT_CLR_L2_DBUS3_OVF_INT_CLR = 0x8000

	// L2_CACHE_ACS_CNT_INT_RAW: Cache Access Counter Interrupt raw register
	// Position of L2_IBUS0_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW_Pos = 0x8
	// Bit mask of L2_IBUS0_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW_Msk = 0x100
	// Bit L2_IBUS0_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS0_OVF_INT_RAW = 0x100
	// Position of L2_IBUS1_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW_Pos = 0x9
	// Bit mask of L2_IBUS1_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW_Msk = 0x200
	// Bit L2_IBUS1_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS1_OVF_INT_RAW = 0x200
	// Position of L2_IBUS2_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW_Pos = 0xa
	// Bit mask of L2_IBUS2_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW_Msk = 0x400
	// Bit L2_IBUS2_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS2_OVF_INT_RAW = 0x400
	// Position of L2_IBUS3_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW_Pos = 0xb
	// Bit mask of L2_IBUS3_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW_Msk = 0x800
	// Bit L2_IBUS3_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_IBUS3_OVF_INT_RAW = 0x800
	// Position of L2_DBUS0_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW_Pos = 0xc
	// Bit mask of L2_DBUS0_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW_Msk = 0x1000
	// Bit L2_DBUS0_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS0_OVF_INT_RAW = 0x1000
	// Position of L2_DBUS1_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW_Pos = 0xd
	// Bit mask of L2_DBUS1_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW_Msk = 0x2000
	// Bit L2_DBUS1_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS1_OVF_INT_RAW = 0x2000
	// Position of L2_DBUS2_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW_Pos = 0xe
	// Bit mask of L2_DBUS2_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW_Msk = 0x4000
	// Bit L2_DBUS2_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS2_OVF_INT_RAW = 0x4000
	// Position of L2_DBUS3_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW_Pos = 0xf
	// Bit mask of L2_DBUS3_OVF_INT_RAW field.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW_Msk = 0x8000
	// Bit L2_DBUS3_OVF_INT_RAW.
	CACHE_L2_CACHE_ACS_CNT_INT_RAW_L2_DBUS3_OVF_INT_RAW = 0x8000

	// L2_CACHE_ACS_CNT_INT_ST: Cache Access Counter Interrupt status register
	// Position of L2_IBUS0_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST_Pos = 0x8
	// Bit mask of L2_IBUS0_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST_Msk = 0x100
	// Bit L2_IBUS0_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS0_OVF_INT_ST = 0x100
	// Position of L2_IBUS1_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST_Pos = 0x9
	// Bit mask of L2_IBUS1_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST_Msk = 0x200
	// Bit L2_IBUS1_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS1_OVF_INT_ST = 0x200
	// Position of L2_IBUS2_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST_Pos = 0xa
	// Bit mask of L2_IBUS2_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST_Msk = 0x400
	// Bit L2_IBUS2_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS2_OVF_INT_ST = 0x400
	// Position of L2_IBUS3_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST_Pos = 0xb
	// Bit mask of L2_IBUS3_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST_Msk = 0x800
	// Bit L2_IBUS3_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_IBUS3_OVF_INT_ST = 0x800
	// Position of L2_DBUS0_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST_Pos = 0xc
	// Bit mask of L2_DBUS0_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST_Msk = 0x1000
	// Bit L2_DBUS0_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS0_OVF_INT_ST = 0x1000
	// Position of L2_DBUS1_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST_Pos = 0xd
	// Bit mask of L2_DBUS1_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST_Msk = 0x2000
	// Bit L2_DBUS1_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS1_OVF_INT_ST = 0x2000
	// Position of L2_DBUS2_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST_Pos = 0xe
	// Bit mask of L2_DBUS2_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST_Msk = 0x4000
	// Bit L2_DBUS2_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS2_OVF_INT_ST = 0x4000
	// Position of L2_DBUS3_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST_Pos = 0xf
	// Bit mask of L2_DBUS3_OVF_INT_ST field.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST_Msk = 0x8000
	// Bit L2_DBUS3_OVF_INT_ST.
	CACHE_L2_CACHE_ACS_CNT_INT_ST_L2_DBUS3_OVF_INT_ST = 0x8000

	// L2_CACHE_ACS_FAIL_CTRL: Cache Access Fail Configuration register
	// Position of L2_CACHE_ACS_FAIL_CHECK_MODE field.
	CACHE_L2_CACHE_ACS_FAIL_CTRL_L2_CACHE_ACS_FAIL_CHECK_MODE_Pos = 0x0
	// Bit mask of L2_CACHE_ACS_FAIL_CHECK_MODE field.
	CACHE_L2_CACHE_ACS_FAIL_CTRL_L2_CACHE_ACS_FAIL_CHECK_MODE_Msk = 0x1
	// Bit L2_CACHE_ACS_FAIL_CHECK_MODE.
	CACHE_L2_CACHE_ACS_FAIL_CTRL_L2_CACHE_ACS_FAIL_CHECK_MODE = 0x1

	// L2_CACHE_ACS_FAIL_INT_ENA: Cache Access Fail Interrupt enable register
	// Position of L2_CACHE_FAIL_INT_ENA field.
	CACHE_L2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA_Pos = 0x5
	// Bit mask of L2_CACHE_FAIL_INT_ENA field.
	CACHE_L2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA_Msk = 0x20
	// Bit L2_CACHE_FAIL_INT_ENA.
	CACHE_L2_CACHE_ACS_FAIL_INT_ENA_L2_CACHE_FAIL_INT_ENA = 0x20

	// L2_CACHE_ACS_FAIL_INT_CLR: L1-Cache Access Fail Interrupt clear register
	// Position of L2_CACHE_FAIL_INT_CLR field.
	CACHE_L2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR_Pos = 0x5
	// Bit mask of L2_CACHE_FAIL_INT_CLR field.
	CACHE_L2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR_Msk = 0x20
	// Bit L2_CACHE_FAIL_INT_CLR.
	CACHE_L2_CACHE_ACS_FAIL_INT_CLR_L2_CACHE_FAIL_INT_CLR = 0x20

	// L2_CACHE_ACS_FAIL_INT_RAW: Cache Access Fail Interrupt raw register
	// Position of L2_CACHE_FAIL_INT_RAW field.
	CACHE_L2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW_Pos = 0x5
	// Bit mask of L2_CACHE_FAIL_INT_RAW field.
	CACHE_L2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW_Msk = 0x20
	// Bit L2_CACHE_FAIL_INT_RAW.
	CACHE_L2_CACHE_ACS_FAIL_INT_RAW_L2_CACHE_FAIL_INT_RAW = 0x20

	// L2_CACHE_ACS_FAIL_INT_ST: Cache Access Fail Interrupt status register
	// Position of L2_CACHE_FAIL_INT_ST field.
	CACHE_L2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST_Pos = 0x5
	// Bit mask of L2_CACHE_FAIL_INT_ST field.
	CACHE_L2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST_Msk = 0x20
	// Bit L2_CACHE_FAIL_INT_ST.
	CACHE_L2_CACHE_ACS_FAIL_INT_ST_L2_CACHE_FAIL_INT_ST = 0x20

	// L2_CACHE_ACS_CNT_CTRL: Cache Access Counter enable and clear register
	// Position of L2_IBUS0_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA_Pos = 0x8
	// Bit mask of L2_IBUS0_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA_Msk = 0x100
	// Bit L2_IBUS0_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_ENA = 0x100
	// Position of L2_IBUS1_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA_Pos = 0x9
	// Bit mask of L2_IBUS1_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA_Msk = 0x200
	// Bit L2_IBUS1_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_ENA = 0x200
	// Position of L2_IBUS2_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA_Pos = 0xa
	// Bit mask of L2_IBUS2_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA_Msk = 0x400
	// Bit L2_IBUS2_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_ENA = 0x400
	// Position of L2_IBUS3_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA_Pos = 0xb
	// Bit mask of L2_IBUS3_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA_Msk = 0x800
	// Bit L2_IBUS3_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_ENA = 0x800
	// Position of L2_DBUS0_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA_Pos = 0xc
	// Bit mask of L2_DBUS0_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA_Msk = 0x1000
	// Bit L2_DBUS0_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_ENA = 0x1000
	// Position of L2_DBUS1_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA_Pos = 0xd
	// Bit mask of L2_DBUS1_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA_Msk = 0x2000
	// Bit L2_DBUS1_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_ENA = 0x2000
	// Position of L2_DBUS2_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA_Pos = 0xe
	// Bit mask of L2_DBUS2_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA_Msk = 0x4000
	// Bit L2_DBUS2_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_ENA = 0x4000
	// Position of L2_DBUS3_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA_Pos = 0xf
	// Bit mask of L2_DBUS3_CNT_ENA field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA_Msk = 0x8000
	// Bit L2_DBUS3_CNT_ENA.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_ENA = 0x8000
	// Position of L2_IBUS0_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR_Pos = 0x18
	// Bit mask of L2_IBUS0_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR_Msk = 0x1000000
	// Bit L2_IBUS0_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS0_CNT_CLR = 0x1000000
	// Position of L2_IBUS1_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR_Pos = 0x19
	// Bit mask of L2_IBUS1_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR_Msk = 0x2000000
	// Bit L2_IBUS1_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS1_CNT_CLR = 0x2000000
	// Position of L2_IBUS2_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR_Pos = 0x1a
	// Bit mask of L2_IBUS2_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR_Msk = 0x4000000
	// Bit L2_IBUS2_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS2_CNT_CLR = 0x4000000
	// Position of L2_IBUS3_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR_Pos = 0x1b
	// Bit mask of L2_IBUS3_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR_Msk = 0x8000000
	// Bit L2_IBUS3_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_IBUS3_CNT_CLR = 0x8000000
	// Position of L2_DBUS0_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR_Pos = 0x1c
	// Bit mask of L2_DBUS0_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR_Msk = 0x10000000
	// Bit L2_DBUS0_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS0_CNT_CLR = 0x10000000
	// Position of L2_DBUS1_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR_Pos = 0x1d
	// Bit mask of L2_DBUS1_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR_Msk = 0x20000000
	// Bit L2_DBUS1_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS1_CNT_CLR = 0x20000000
	// Position of L2_DBUS2_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR_Pos = 0x1e
	// Bit mask of L2_DBUS2_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR_Msk = 0x40000000
	// Bit L2_DBUS2_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS2_CNT_CLR = 0x40000000
	// Position of L2_DBUS3_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR_Pos = 0x1f
	// Bit mask of L2_DBUS3_CNT_CLR field.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR_Msk = 0x80000000
	// Bit L2_DBUS3_CNT_CLR.
	CACHE_L2_CACHE_ACS_CNT_CTRL_L2_DBUS3_CNT_CLR = 0x80000000

	// L2_IBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register
	// Position of L2_IBUS0_HIT_CNT field.
	CACHE_L2_IBUS0_ACS_HIT_CNT_L2_IBUS0_HIT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS0_HIT_CNT field.
	CACHE_L2_IBUS0_ACS_HIT_CNT_L2_IBUS0_HIT_CNT_Msk = 0xffffffff

	// L2_IBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register
	// Position of L2_IBUS0_MISS_CNT field.
	CACHE_L2_IBUS0_ACS_MISS_CNT_L2_IBUS0_MISS_CNT_Pos = 0x0
	// Bit mask of L2_IBUS0_MISS_CNT field.
	CACHE_L2_IBUS0_ACS_MISS_CNT_L2_IBUS0_MISS_CNT_Msk = 0xffffffff

	// L2_IBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register
	// Position of L2_IBUS0_CONFLICT_CNT field.
	CACHE_L2_IBUS0_ACS_CONFLICT_CNT_L2_IBUS0_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS0_CONFLICT_CNT field.
	CACHE_L2_IBUS0_ACS_CONFLICT_CNT_L2_IBUS0_CONFLICT_CNT_Msk = 0xffffffff

	// L2_IBUS0_ACS_NXTLVL_RD_CNT: L2-Cache bus0 Next-Level-Access Counter register
	// Position of L2_IBUS0_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_L2_IBUS0_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_IBUS0_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_L2_IBUS0_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_IBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register
	// Position of L2_IBUS1_HIT_CNT field.
	CACHE_L2_IBUS1_ACS_HIT_CNT_L2_IBUS1_HIT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS1_HIT_CNT field.
	CACHE_L2_IBUS1_ACS_HIT_CNT_L2_IBUS1_HIT_CNT_Msk = 0xffffffff

	// L2_IBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register
	// Position of L2_IBUS1_MISS_CNT field.
	CACHE_L2_IBUS1_ACS_MISS_CNT_L2_IBUS1_MISS_CNT_Pos = 0x0
	// Bit mask of L2_IBUS1_MISS_CNT field.
	CACHE_L2_IBUS1_ACS_MISS_CNT_L2_IBUS1_MISS_CNT_Msk = 0xffffffff

	// L2_IBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register
	// Position of L2_IBUS1_CONFLICT_CNT field.
	CACHE_L2_IBUS1_ACS_CONFLICT_CNT_L2_IBUS1_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS1_CONFLICT_CNT field.
	CACHE_L2_IBUS1_ACS_CONFLICT_CNT_L2_IBUS1_CONFLICT_CNT_Msk = 0xffffffff

	// L2_IBUS1_ACS_NXTLVL_RD_CNT: L2-Cache bus1 Next-Level-Access Counter register
	// Position of L2_IBUS1_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_L2_IBUS1_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_IBUS1_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_L2_IBUS1_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_IBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register
	// Position of L2_IBUS2_HIT_CNT field.
	CACHE_L2_IBUS2_ACS_HIT_CNT_L2_IBUS2_HIT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS2_HIT_CNT field.
	CACHE_L2_IBUS2_ACS_HIT_CNT_L2_IBUS2_HIT_CNT_Msk = 0xffffffff

	// L2_IBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register
	// Position of L2_IBUS2_MISS_CNT field.
	CACHE_L2_IBUS2_ACS_MISS_CNT_L2_IBUS2_MISS_CNT_Pos = 0x0
	// Bit mask of L2_IBUS2_MISS_CNT field.
	CACHE_L2_IBUS2_ACS_MISS_CNT_L2_IBUS2_MISS_CNT_Msk = 0xffffffff

	// L2_IBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register
	// Position of L2_IBUS2_CONFLICT_CNT field.
	CACHE_L2_IBUS2_ACS_CONFLICT_CNT_L2_IBUS2_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS2_CONFLICT_CNT field.
	CACHE_L2_IBUS2_ACS_CONFLICT_CNT_L2_IBUS2_CONFLICT_CNT_Msk = 0xffffffff

	// L2_IBUS2_ACS_NXTLVL_RD_CNT: L2-Cache bus2 Next-Level-Access Counter register
	// Position of L2_IBUS2_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_L2_IBUS2_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_IBUS2_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_L2_IBUS2_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_IBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register
	// Position of L2_IBUS3_HIT_CNT field.
	CACHE_L2_IBUS3_ACS_HIT_CNT_L2_IBUS3_HIT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS3_HIT_CNT field.
	CACHE_L2_IBUS3_ACS_HIT_CNT_L2_IBUS3_HIT_CNT_Msk = 0xffffffff

	// L2_IBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register
	// Position of L2_IBUS3_MISS_CNT field.
	CACHE_L2_IBUS3_ACS_MISS_CNT_L2_IBUS3_MISS_CNT_Pos = 0x0
	// Bit mask of L2_IBUS3_MISS_CNT field.
	CACHE_L2_IBUS3_ACS_MISS_CNT_L2_IBUS3_MISS_CNT_Msk = 0xffffffff

	// L2_IBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register
	// Position of L2_IBUS3_CONFLICT_CNT field.
	CACHE_L2_IBUS3_ACS_CONFLICT_CNT_L2_IBUS3_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_IBUS3_CONFLICT_CNT field.
	CACHE_L2_IBUS3_ACS_CONFLICT_CNT_L2_IBUS3_CONFLICT_CNT_Msk = 0xffffffff

	// L2_IBUS3_ACS_NXTLVL_RD_CNT: L2-Cache bus3 Next-Level-Access Counter register
	// Position of L2_IBUS3_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_L2_IBUS3_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_IBUS3_NXTLVL_RD_CNT field.
	CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_L2_IBUS3_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_DBUS0_ACS_HIT_CNT: L2-Cache bus0 Hit-Access Counter register
	// Position of L2_DBUS0_HIT_CNT field.
	CACHE_L2_DBUS0_ACS_HIT_CNT_L2_DBUS0_HIT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS0_HIT_CNT field.
	CACHE_L2_DBUS0_ACS_HIT_CNT_L2_DBUS0_HIT_CNT_Msk = 0xffffffff

	// L2_DBUS0_ACS_MISS_CNT: L2-Cache bus0 Miss-Access Counter register
	// Position of L2_DBUS0_MISS_CNT field.
	CACHE_L2_DBUS0_ACS_MISS_CNT_L2_DBUS0_MISS_CNT_Pos = 0x0
	// Bit mask of L2_DBUS0_MISS_CNT field.
	CACHE_L2_DBUS0_ACS_MISS_CNT_L2_DBUS0_MISS_CNT_Msk = 0xffffffff

	// L2_DBUS0_ACS_CONFLICT_CNT: L2-Cache bus0 Conflict-Access Counter register
	// Position of L2_DBUS0_CONFLICT_CNT field.
	CACHE_L2_DBUS0_ACS_CONFLICT_CNT_L2_DBUS0_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS0_CONFLICT_CNT field.
	CACHE_L2_DBUS0_ACS_CONFLICT_CNT_L2_DBUS0_CONFLICT_CNT_Msk = 0xffffffff

	// L2_DBUS0_ACS_NXTLVL_RD_CNT: L2-Cache bus0 Next-Level-Access Counter register
	// Position of L2_DBUS0_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_L2_DBUS0_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_DBUS0_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_L2_DBUS0_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_DBUS0_ACS_NXTLVL_WR_CNT: L2-Cache bus0 WB-Access Counter register
	// Position of L2_DBUS0_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_L2_DBUS0_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L2_DBUS0_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_L2_DBUS0_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L2_DBUS1_ACS_HIT_CNT: L2-Cache bus1 Hit-Access Counter register
	// Position of L2_DBUS1_HIT_CNT field.
	CACHE_L2_DBUS1_ACS_HIT_CNT_L2_DBUS1_HIT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS1_HIT_CNT field.
	CACHE_L2_DBUS1_ACS_HIT_CNT_L2_DBUS1_HIT_CNT_Msk = 0xffffffff

	// L2_DBUS1_ACS_MISS_CNT: L2-Cache bus1 Miss-Access Counter register
	// Position of L2_DBUS1_MISS_CNT field.
	CACHE_L2_DBUS1_ACS_MISS_CNT_L2_DBUS1_MISS_CNT_Pos = 0x0
	// Bit mask of L2_DBUS1_MISS_CNT field.
	CACHE_L2_DBUS1_ACS_MISS_CNT_L2_DBUS1_MISS_CNT_Msk = 0xffffffff

	// L2_DBUS1_ACS_CONFLICT_CNT: L2-Cache bus1 Conflict-Access Counter register
	// Position of L2_DBUS1_CONFLICT_CNT field.
	CACHE_L2_DBUS1_ACS_CONFLICT_CNT_L2_DBUS1_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS1_CONFLICT_CNT field.
	CACHE_L2_DBUS1_ACS_CONFLICT_CNT_L2_DBUS1_CONFLICT_CNT_Msk = 0xffffffff

	// L2_DBUS1_ACS_NXTLVL_RD_CNT: L2-Cache bus1 Next-Level-Access Counter register
	// Position of L2_DBUS1_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_L2_DBUS1_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_DBUS1_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_L2_DBUS1_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_DBUS1_ACS_NXTLVL_WR_CNT: L2-Cache bus1 WB-Access Counter register
	// Position of L2_DBUS1_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_L2_DBUS1_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L2_DBUS1_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_L2_DBUS1_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L2_DBUS2_ACS_HIT_CNT: L2-Cache bus2 Hit-Access Counter register
	// Position of L2_DBUS2_HIT_CNT field.
	CACHE_L2_DBUS2_ACS_HIT_CNT_L2_DBUS2_HIT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS2_HIT_CNT field.
	CACHE_L2_DBUS2_ACS_HIT_CNT_L2_DBUS2_HIT_CNT_Msk = 0xffffffff

	// L2_DBUS2_ACS_MISS_CNT: L2-Cache bus2 Miss-Access Counter register
	// Position of L2_DBUS2_MISS_CNT field.
	CACHE_L2_DBUS2_ACS_MISS_CNT_L2_DBUS2_MISS_CNT_Pos = 0x0
	// Bit mask of L2_DBUS2_MISS_CNT field.
	CACHE_L2_DBUS2_ACS_MISS_CNT_L2_DBUS2_MISS_CNT_Msk = 0xffffffff

	// L2_DBUS2_ACS_CONFLICT_CNT: L2-Cache bus2 Conflict-Access Counter register
	// Position of L2_DBUS2_CONFLICT_CNT field.
	CACHE_L2_DBUS2_ACS_CONFLICT_CNT_L2_DBUS2_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS2_CONFLICT_CNT field.
	CACHE_L2_DBUS2_ACS_CONFLICT_CNT_L2_DBUS2_CONFLICT_CNT_Msk = 0xffffffff

	// L2_DBUS2_ACS_NXTLVL_RD_CNT: L2-Cache bus2 Next-Level-Access Counter register
	// Position of L2_DBUS2_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_L2_DBUS2_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_DBUS2_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_L2_DBUS2_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_DBUS2_ACS_NXTLVL_WR_CNT: L2-Cache bus2 WB-Access Counter register
	// Position of L2_DBUS2_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_L2_DBUS2_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L2_DBUS2_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_L2_DBUS2_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L2_DBUS3_ACS_HIT_CNT: L2-Cache bus3 Hit-Access Counter register
	// Position of L2_DBUS3_HIT_CNT field.
	CACHE_L2_DBUS3_ACS_HIT_CNT_L2_DBUS3_HIT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS3_HIT_CNT field.
	CACHE_L2_DBUS3_ACS_HIT_CNT_L2_DBUS3_HIT_CNT_Msk = 0xffffffff

	// L2_DBUS3_ACS_MISS_CNT: L2-Cache bus3 Miss-Access Counter register
	// Position of L2_DBUS3_MISS_CNT field.
	CACHE_L2_DBUS3_ACS_MISS_CNT_L2_DBUS3_MISS_CNT_Pos = 0x0
	// Bit mask of L2_DBUS3_MISS_CNT field.
	CACHE_L2_DBUS3_ACS_MISS_CNT_L2_DBUS3_MISS_CNT_Msk = 0xffffffff

	// L2_DBUS3_ACS_CONFLICT_CNT: L2-Cache bus3 Conflict-Access Counter register
	// Position of L2_DBUS3_CONFLICT_CNT field.
	CACHE_L2_DBUS3_ACS_CONFLICT_CNT_L2_DBUS3_CONFLICT_CNT_Pos = 0x0
	// Bit mask of L2_DBUS3_CONFLICT_CNT field.
	CACHE_L2_DBUS3_ACS_CONFLICT_CNT_L2_DBUS3_CONFLICT_CNT_Msk = 0xffffffff

	// L2_DBUS3_ACS_NXTLVL_RD_CNT: L2-Cache bus3 Next-Level-Access Counter register
	// Position of L2_DBUS3_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_L2_DBUS3_NXTLVL_RD_CNT_Pos = 0x0
	// Bit mask of L2_DBUS3_NXTLVL_RD_CNT field.
	CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_L2_DBUS3_NXTLVL_RD_CNT_Msk = 0xffffffff

	// L2_DBUS3_ACS_NXTLVL_WR_CNT: L2-Cache bus3 WB-Access Counter register
	// Position of L2_DBUS3_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_L2_DBUS3_NXTLVL_WR_CNT_Pos = 0x0
	// Bit mask of L2_DBUS3_NXTLVL_WR_CNT field.
	CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_L2_DBUS3_NXTLVL_WR_CNT_Msk = 0xffffffff

	// L2_CACHE_ACS_FAIL_ID_ATTR: L2-Cache Access Fail ID/attribution information register
	// Position of L2_CACHE_FAIL_ID field.
	CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID_Pos = 0x0
	// Bit mask of L2_CACHE_FAIL_ID field.
	CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ID_Msk = 0xffff
	// Position of L2_CACHE_FAIL_ATTR field.
	CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR_Pos = 0x10
	// Bit mask of L2_CACHE_FAIL_ATTR field.
	CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_L2_CACHE_FAIL_ATTR_Msk = 0xffff0000

	// L2_CACHE_ACS_FAIL_ADDR: L2-Cache Access Fail Address information register
	// Position of L2_CACHE_FAIL_ADDR field.
	CACHE_L2_CACHE_ACS_FAIL_ADDR_L2_CACHE_FAIL_ADDR_Pos = 0x0
	// Bit mask of L2_CACHE_FAIL_ADDR field.
	CACHE_L2_CACHE_ACS_FAIL_ADDR_L2_CACHE_FAIL_ADDR_Msk = 0xffffffff

	// L2_CACHE_SYNC_PRELOAD_INT_ENA: L1-Cache Access Fail Interrupt enable register
	// Position of L2_CACHE_PLD_DONE_INT_ENA field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA_Pos = 0x5
	// Bit mask of L2_CACHE_PLD_DONE_INT_ENA field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA_Msk = 0x20
	// Bit L2_CACHE_PLD_DONE_INT_ENA.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_DONE_INT_ENA = 0x20
	// Position of L2_CACHE_PLD_ERR_INT_ENA field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA_Pos = 0xc
	// Bit mask of L2_CACHE_PLD_ERR_INT_ENA field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA_Msk = 0x1000
	// Bit L2_CACHE_PLD_ERR_INT_ENA.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_L2_CACHE_PLD_ERR_INT_ENA = 0x1000

	// L2_CACHE_SYNC_PRELOAD_INT_CLR: Sync Preload operation Interrupt clear register
	// Position of L2_CACHE_PLD_DONE_INT_CLR field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR_Pos = 0x5
	// Bit mask of L2_CACHE_PLD_DONE_INT_CLR field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR_Msk = 0x20
	// Bit L2_CACHE_PLD_DONE_INT_CLR.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_DONE_INT_CLR = 0x20
	// Position of L2_CACHE_PLD_ERR_INT_CLR field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR_Pos = 0xc
	// Bit mask of L2_CACHE_PLD_ERR_INT_CLR field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR_Msk = 0x1000
	// Bit L2_CACHE_PLD_ERR_INT_CLR.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_L2_CACHE_PLD_ERR_INT_CLR = 0x1000

	// L2_CACHE_SYNC_PRELOAD_INT_RAW: Sync Preload operation Interrupt raw register
	// Position of L2_CACHE_PLD_DONE_INT_RAW field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW_Pos = 0x5
	// Bit mask of L2_CACHE_PLD_DONE_INT_RAW field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW_Msk = 0x20
	// Bit L2_CACHE_PLD_DONE_INT_RAW.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_DONE_INT_RAW = 0x20
	// Position of L2_CACHE_PLD_ERR_INT_RAW field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW_Pos = 0xc
	// Bit mask of L2_CACHE_PLD_ERR_INT_RAW field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW_Msk = 0x1000
	// Bit L2_CACHE_PLD_ERR_INT_RAW.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_L2_CACHE_PLD_ERR_INT_RAW = 0x1000

	// L2_CACHE_SYNC_PRELOAD_INT_ST: L1-Cache Access Fail Interrupt status register
	// Position of L2_CACHE_PLD_DONE_INT_ST field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST_Pos = 0x5
	// Bit mask of L2_CACHE_PLD_DONE_INT_ST field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST_Msk = 0x20
	// Bit L2_CACHE_PLD_DONE_INT_ST.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_DONE_INT_ST = 0x20
	// Position of L2_CACHE_PLD_ERR_INT_ST field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST_Pos = 0xc
	// Bit mask of L2_CACHE_PLD_ERR_INT_ST field.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST_Msk = 0x1000
	// Bit L2_CACHE_PLD_ERR_INT_ST.
	CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_L2_CACHE_PLD_ERR_INT_ST = 0x1000

	// L2_CACHE_SYNC_PRELOAD_EXCEPTION: Cache Sync/Preload Operation exception register
	// Position of L2_CACHE_PLD_ERR_CODE field.
	CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE_Pos = 0xa
	// Bit mask of L2_CACHE_PLD_ERR_CODE field.
	CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_L2_CACHE_PLD_ERR_CODE_Msk = 0xc00

	// L2_CACHE_SYNC_RST_CTRL: Cache Sync Reset control register
	// Position of L2_CACHE_SYNC_RST field.
	CACHE_L2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST_Pos = 0x5
	// Bit mask of L2_CACHE_SYNC_RST field.
	CACHE_L2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST_Msk = 0x20
	// Bit L2_CACHE_SYNC_RST.
	CACHE_L2_CACHE_SYNC_RST_CTRL_L2_CACHE_SYNC_RST = 0x20

	// L2_CACHE_PRELOAD_RST_CTRL: Cache Preload Reset control register
	// Position of L2_CACHE_PLD_RST field.
	CACHE_L2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST_Pos = 0x5
	// Bit mask of L2_CACHE_PLD_RST field.
	CACHE_L2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST_Msk = 0x20
	// Bit L2_CACHE_PLD_RST.
	CACHE_L2_CACHE_PRELOAD_RST_CTRL_L2_CACHE_PLD_RST = 0x20

	// L2_CACHE_AUTOLOAD_BUF_CLR_CTRL: Cache Autoload buffer clear control register
	// Position of L2_CACHE_ALD_BUF_CLR field.
	CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR_Pos = 0x5
	// Bit mask of L2_CACHE_ALD_BUF_CLR field.
	CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR_Msk = 0x20
	// Bit L2_CACHE_ALD_BUF_CLR.
	CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_L2_CACHE_ALD_BUF_CLR = 0x20

	// L2_UNALLOCATE_BUFFER_CLEAR: Unallocate request buffer clear registers
	// Position of L2_CACHE_UNALLOC_CLR field.
	CACHE_L2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR_Pos = 0x5
	// Bit mask of L2_CACHE_UNALLOC_CLR field.
	CACHE_L2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR_Msk = 0x20
	// Bit L2_CACHE_UNALLOC_CLR.
	CACHE_L2_UNALLOCATE_BUFFER_CLEAR_L2_CACHE_UNALLOC_CLR = 0x20

	// L2_CACHE_ACCESS_ATTR_CTRL: L2 cache access attribute control register
	// Position of L2_CACHE_ACCESS_FORCE_CC field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC_Pos = 0x0
	// Bit mask of L2_CACHE_ACCESS_FORCE_CC field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC_Msk = 0x1
	// Bit L2_CACHE_ACCESS_FORCE_CC.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_CC = 0x1
	// Position of L2_CACHE_ACCESS_FORCE_WB field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB_Pos = 0x1
	// Bit mask of L2_CACHE_ACCESS_FORCE_WB field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB_Msk = 0x2
	// Bit L2_CACHE_ACCESS_FORCE_WB.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WB = 0x2
	// Position of L2_CACHE_ACCESS_FORCE_WMA field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA_Pos = 0x2
	// Bit mask of L2_CACHE_ACCESS_FORCE_WMA field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA_Msk = 0x4
	// Bit L2_CACHE_ACCESS_FORCE_WMA.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_WMA = 0x4
	// Position of L2_CACHE_ACCESS_FORCE_RMA field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA_Pos = 0x3
	// Bit mask of L2_CACHE_ACCESS_FORCE_RMA field.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA_Msk = 0x8
	// Bit L2_CACHE_ACCESS_FORCE_RMA.
	CACHE_L2_CACHE_ACCESS_ATTR_CTRL_L2_CACHE_ACCESS_FORCE_RMA = 0x8

	// L2_CACHE_OBJECT_CTRL: Cache Tag and Data memory Object control register
	// Position of L2_CACHE_TAG_OBJECT field.
	CACHE_L2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT_Pos = 0x5
	// Bit mask of L2_CACHE_TAG_OBJECT field.
	CACHE_L2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT_Msk = 0x20
	// Bit L2_CACHE_TAG_OBJECT.
	CACHE_L2_CACHE_OBJECT_CTRL_L2_CACHE_TAG_OBJECT = 0x20
	// Position of L2_CACHE_MEM_OBJECT field.
	CACHE_L2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT_Pos = 0xb
	// Bit mask of L2_CACHE_MEM_OBJECT field.
	CACHE_L2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT_Msk = 0x800
	// Bit L2_CACHE_MEM_OBJECT.
	CACHE_L2_CACHE_OBJECT_CTRL_L2_CACHE_MEM_OBJECT = 0x800

	// L2_CACHE_WAY_OBJECT: Cache Tag and Data memory way register
	// Position of L2_CACHE_WAY_OBJECT field.
	CACHE_L2_CACHE_WAY_OBJECT_L2_CACHE_WAY_OBJECT_Pos = 0x0
	// Bit mask of L2_CACHE_WAY_OBJECT field.
	CACHE_L2_CACHE_WAY_OBJECT_L2_CACHE_WAY_OBJECT_Msk = 0x7

	// L2_CACHE_VADDR: Cache Vaddr register
	// Position of L2_CACHE_VADDR field.
	CACHE_L2_CACHE_VADDR_L2_CACHE_VADDR_Pos = 0x0
	// Bit mask of L2_CACHE_VADDR field.
	CACHE_L2_CACHE_VADDR_L2_CACHE_VADDR_Msk = 0xffffffff

	// L2_CACHE_DEBUG_BUS: Cache Tag/data memory content register
	// Position of L2_CACHE_DEBUG_BUS field.
	CACHE_L2_CACHE_DEBUG_BUS_L2_CACHE_DEBUG_BUS_Pos = 0x0
	// Bit mask of L2_CACHE_DEBUG_BUS field.
	CACHE_L2_CACHE_DEBUG_BUS_L2_CACHE_DEBUG_BUS_Msk = 0xffffffff

	// LEVEL_SPLIT1: USED TO SPLIT L1 CACHE AND L2 CACHE
	// Position of LEVEL_SPLIT1 field.
	CACHE_LEVEL_SPLIT1_LEVEL_SPLIT1_Pos = 0x0
	// Bit mask of LEVEL_SPLIT1 field.
	CACHE_LEVEL_SPLIT1_LEVEL_SPLIT1_Msk = 0xffffffff

	// CLOCK_GATE: Clock gate control register
	// Position of CLK_EN field.
	CACHE_CLOCK_GATE_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	CACHE_CLOCK_GATE_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	CACHE_CLOCK_GATE_CLK_EN = 0x1

	// REDUNDANCY_SIG0: Cache redundancy signal 0 register
	// Position of REDCY_SIG0 field.
	CACHE_REDUNDANCY_SIG0_REDCY_SIG0_Pos = 0x0
	// Bit mask of REDCY_SIG0 field.
	CACHE_REDUNDANCY_SIG0_REDCY_SIG0_Msk = 0xffffffff

	// REDUNDANCY_SIG1: Cache redundancy signal 1 register
	// Position of REDCY_SIG1 field.
	CACHE_REDUNDANCY_SIG1_REDCY_SIG1_Pos = 0x0
	// Bit mask of REDCY_SIG1 field.
	CACHE_REDUNDANCY_SIG1_REDCY_SIG1_Msk = 0xffffffff

	// REDUNDANCY_SIG2: Cache redundancy signal 2 register
	// Position of REDCY_SIG2 field.
	CACHE_REDUNDANCY_SIG2_REDCY_SIG2_Pos = 0x0
	// Bit mask of REDCY_SIG2 field.
	CACHE_REDUNDANCY_SIG2_REDCY_SIG2_Msk = 0xffffffff

	// REDUNDANCY_SIG3: Cache redundancy signal 3 register
	// Position of REDCY_SIG3 field.
	CACHE_REDUNDANCY_SIG3_REDCY_SIG3_Pos = 0x0
	// Bit mask of REDCY_SIG3 field.
	CACHE_REDUNDANCY_SIG3_REDCY_SIG3_Msk = 0xffffffff

	// REDUNDANCY_SIG4: Cache redundancy signal 0 register
	// Position of REDCY_SIG4 field.
	CACHE_REDUNDANCY_SIG4_REDCY_SIG4_Pos = 0x0
	// Bit mask of REDCY_SIG4 field.
	CACHE_REDUNDANCY_SIG4_REDCY_SIG4_Msk = 0xf

	// DATE: Version control register
	// Position of DATE field.
	CACHE_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	CACHE_DATE_DATE_Msk = 0xfffffff
)

// Constants for INTERRUPT_CORE0: Interrupt Controller (Core 0)
const (
	// LP_RTC_INT_MAP: NA
	// Position of CORE0_LP_RTC_INT_MAP field.
	CORE0_LP_RTC_INT_MAP_CORE0_LP_RTC_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_RTC_INT_MAP field.
	CORE0_LP_RTC_INT_MAP_CORE0_LP_RTC_INT_MAP_Msk = 0x3f

	// LP_WDT_INT_MAP: NA
	// Position of CORE0_LP_WDT_INT_MAP field.
	CORE0_LP_WDT_INT_MAP_CORE0_LP_WDT_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_WDT_INT_MAP field.
	CORE0_LP_WDT_INT_MAP_CORE0_LP_WDT_INT_MAP_Msk = 0x3f

	// LP_TIMER_REG_0_INT_MAP: NA
	// Position of CORE0_LP_TIMER_REG_0_INT_MAP field.
	CORE0_LP_TIMER_REG_0_INT_MAP_CORE0_LP_TIMER_REG_0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_TIMER_REG_0_INT_MAP field.
	CORE0_LP_TIMER_REG_0_INT_MAP_CORE0_LP_TIMER_REG_0_INT_MAP_Msk = 0x3f

	// LP_TIMER_REG_1_INT_MAP: NA
	// Position of CORE0_LP_TIMER_REG_1_INT_MAP field.
	CORE0_LP_TIMER_REG_1_INT_MAP_CORE0_LP_TIMER_REG_1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_TIMER_REG_1_INT_MAP field.
	CORE0_LP_TIMER_REG_1_INT_MAP_CORE0_LP_TIMER_REG_1_INT_MAP_Msk = 0x3f

	// MB_HP_INT_MAP: NA
	// Position of CORE0_MB_HP_INT_MAP field.
	CORE0_MB_HP_INT_MAP_CORE0_MB_HP_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_MB_HP_INT_MAP field.
	CORE0_MB_HP_INT_MAP_CORE0_MB_HP_INT_MAP_Msk = 0x3f

	// MB_LP_INT_MAP: NA
	// Position of CORE0_MB_LP_INT_MAP field.
	CORE0_MB_LP_INT_MAP_CORE0_MB_LP_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_MB_LP_INT_MAP field.
	CORE0_MB_LP_INT_MAP_CORE0_MB_LP_INT_MAP_Msk = 0x3f

	// PMU_REG_0_INT_MAP: NA
	// Position of CORE0_PMU_REG_0_INT_MAP field.
	CORE0_PMU_REG_0_INT_MAP_CORE0_PMU_REG_0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PMU_REG_0_INT_MAP field.
	CORE0_PMU_REG_0_INT_MAP_CORE0_PMU_REG_0_INT_MAP_Msk = 0x3f

	// PMU_REG_1_INT_MAP: NA
	// Position of CORE0_PMU_REG_1_INT_MAP field.
	CORE0_PMU_REG_1_INT_MAP_CORE0_PMU_REG_1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PMU_REG_1_INT_MAP field.
	CORE0_PMU_REG_1_INT_MAP_CORE0_PMU_REG_1_INT_MAP_Msk = 0x3f

	// LP_ANAPERI_INT_MAP: NA
	// Position of CORE0_LP_ANAPERI_INT_MAP field.
	CORE0_LP_ANAPERI_INT_MAP_CORE0_LP_ANAPERI_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_ANAPERI_INT_MAP field.
	CORE0_LP_ANAPERI_INT_MAP_CORE0_LP_ANAPERI_INT_MAP_Msk = 0x3f

	// LP_ADC_INT_MAP: NA
	// Position of CORE0_LP_ADC_INT_MAP field.
	CORE0_LP_ADC_INT_MAP_CORE0_LP_ADC_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_ADC_INT_MAP field.
	CORE0_LP_ADC_INT_MAP_CORE0_LP_ADC_INT_MAP_Msk = 0x3f

	// LP_GPIO_INT_MAP: NA
	// Position of CORE0_LP_GPIO_INT_MAP field.
	CORE0_LP_GPIO_INT_MAP_CORE0_LP_GPIO_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_GPIO_INT_MAP field.
	CORE0_LP_GPIO_INT_MAP_CORE0_LP_GPIO_INT_MAP_Msk = 0x3f

	// LP_I2C_INT_MAP: NA
	// Position of CORE0_LP_I2C_INT_MAP field.
	CORE0_LP_I2C_INT_MAP_CORE0_LP_I2C_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_I2C_INT_MAP field.
	CORE0_LP_I2C_INT_MAP_CORE0_LP_I2C_INT_MAP_Msk = 0x3f

	// LP_I2S_INT_MAP: NA
	// Position of CORE0_LP_I2S_INT_MAP field.
	CORE0_LP_I2S_INT_MAP_CORE0_LP_I2S_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_I2S_INT_MAP field.
	CORE0_LP_I2S_INT_MAP_CORE0_LP_I2S_INT_MAP_Msk = 0x3f

	// LP_SPI_INT_MAP: NA
	// Position of CORE0_LP_SPI_INT_MAP field.
	CORE0_LP_SPI_INT_MAP_CORE0_LP_SPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_SPI_INT_MAP field.
	CORE0_LP_SPI_INT_MAP_CORE0_LP_SPI_INT_MAP_Msk = 0x3f

	// LP_TOUCH_INT_MAP: NA
	// Position of CORE0_LP_TOUCH_INT_MAP field.
	CORE0_LP_TOUCH_INT_MAP_CORE0_LP_TOUCH_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_TOUCH_INT_MAP field.
	CORE0_LP_TOUCH_INT_MAP_CORE0_LP_TOUCH_INT_MAP_Msk = 0x3f

	// LP_TSENS_INT_MAP: NA
	// Position of CORE0_LP_TSENS_INT_MAP field.
	CORE0_LP_TSENS_INT_MAP_CORE0_LP_TSENS_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_TSENS_INT_MAP field.
	CORE0_LP_TSENS_INT_MAP_CORE0_LP_TSENS_INT_MAP_Msk = 0x3f

	// LP_UART_INT_MAP: NA
	// Position of CORE0_LP_UART_INT_MAP field.
	CORE0_LP_UART_INT_MAP_CORE0_LP_UART_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_UART_INT_MAP field.
	CORE0_LP_UART_INT_MAP_CORE0_LP_UART_INT_MAP_Msk = 0x3f

	// LP_EFUSE_INT_MAP: NA
	// Position of CORE0_LP_EFUSE_INT_MAP field.
	CORE0_LP_EFUSE_INT_MAP_CORE0_LP_EFUSE_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_EFUSE_INT_MAP field.
	CORE0_LP_EFUSE_INT_MAP_CORE0_LP_EFUSE_INT_MAP_Msk = 0x3f

	// LP_SW_INT_MAP: NA
	// Position of CORE0_LP_SW_INT_MAP field.
	CORE0_LP_SW_INT_MAP_CORE0_LP_SW_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_SW_INT_MAP field.
	CORE0_LP_SW_INT_MAP_CORE0_LP_SW_INT_MAP_Msk = 0x3f

	// LP_SYSREG_INT_MAP: NA
	// Position of CORE0_LP_SYSREG_INT_MAP field.
	CORE0_LP_SYSREG_INT_MAP_CORE0_LP_SYSREG_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_SYSREG_INT_MAP field.
	CORE0_LP_SYSREG_INT_MAP_CORE0_LP_SYSREG_INT_MAP_Msk = 0x3f

	// LP_HUK_INT_MAP: NA
	// Position of CORE0_LP_HUK_INT_MAP field.
	CORE0_LP_HUK_INT_MAP_CORE0_LP_HUK_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LP_HUK_INT_MAP field.
	CORE0_LP_HUK_INT_MAP_CORE0_LP_HUK_INT_MAP_Msk = 0x3f

	// SYS_ICM_INT_MAP: NA
	// Position of CORE0_SYS_ICM_INT_MAP field.
	CORE0_SYS_ICM_INT_MAP_CORE0_SYS_ICM_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SYS_ICM_INT_MAP field.
	CORE0_SYS_ICM_INT_MAP_CORE0_SYS_ICM_INT_MAP_Msk = 0x3f

	// USB_DEVICE_INT_MAP: NA
	// Position of CORE0_USB_DEVICE_INT_MAP field.
	CORE0_USB_DEVICE_INT_MAP_CORE0_USB_DEVICE_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_USB_DEVICE_INT_MAP field.
	CORE0_USB_DEVICE_INT_MAP_CORE0_USB_DEVICE_INT_MAP_Msk = 0x3f

	// SDIO_HOST_INT_MAP: NA
	// Position of CORE0_SDIO_HOST_INT_MAP field.
	CORE0_SDIO_HOST_INT_MAP_CORE0_SDIO_HOST_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SDIO_HOST_INT_MAP field.
	CORE0_SDIO_HOST_INT_MAP_CORE0_SDIO_HOST_INT_MAP_Msk = 0x3f

	// GDMA_INT_MAP: NA
	// Position of CORE0_GDMA_INT_MAP field.
	CORE0_GDMA_INT_MAP_CORE0_GDMA_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_GDMA_INT_MAP field.
	CORE0_GDMA_INT_MAP_CORE0_GDMA_INT_MAP_Msk = 0x3f

	// SPI2_INT_MAP: NA
	// Position of CORE0_SPI2_INT_MAP field.
	CORE0_SPI2_INT_MAP_CORE0_SPI2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SPI2_INT_MAP field.
	CORE0_SPI2_INT_MAP_CORE0_SPI2_INT_MAP_Msk = 0x3f

	// SPI3_INT_MAP: NA
	// Position of CORE0_SPI3_INT_MAP field.
	CORE0_SPI3_INT_MAP_CORE0_SPI3_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SPI3_INT_MAP field.
	CORE0_SPI3_INT_MAP_CORE0_SPI3_INT_MAP_Msk = 0x3f

	// I2S0_INT_MAP: NA
	// Position of CORE0_I2S0_INT_MAP field.
	CORE0_I2S0_INT_MAP_CORE0_I2S0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_I2S0_INT_MAP field.
	CORE0_I2S0_INT_MAP_CORE0_I2S0_INT_MAP_Msk = 0x3f

	// I2S1_INT_MAP: NA
	// Position of CORE0_I2S1_INT_MAP field.
	CORE0_I2S1_INT_MAP_CORE0_I2S1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_I2S1_INT_MAP field.
	CORE0_I2S1_INT_MAP_CORE0_I2S1_INT_MAP_Msk = 0x3f

	// I2S2_INT_MAP: NA
	// Position of CORE0_I2S2_INT_MAP field.
	CORE0_I2S2_INT_MAP_CORE0_I2S2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_I2S2_INT_MAP field.
	CORE0_I2S2_INT_MAP_CORE0_I2S2_INT_MAP_Msk = 0x3f

	// UHCI0_INT_MAP: NA
	// Position of CORE0_UHCI0_INT_MAP field.
	CORE0_UHCI0_INT_MAP_CORE0_UHCI0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_UHCI0_INT_MAP field.
	CORE0_UHCI0_INT_MAP_CORE0_UHCI0_INT_MAP_Msk = 0x3f

	// UART0_INT_MAP: NA
	// Position of CORE0_UART0_INT_MAP field.
	CORE0_UART0_INT_MAP_CORE0_UART0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_UART0_INT_MAP field.
	CORE0_UART0_INT_MAP_CORE0_UART0_INT_MAP_Msk = 0x3f

	// UART1_INT_MAP: NA
	// Position of CORE0_UART1_INT_MAP field.
	CORE0_UART1_INT_MAP_CORE0_UART1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_UART1_INT_MAP field.
	CORE0_UART1_INT_MAP_CORE0_UART1_INT_MAP_Msk = 0x3f

	// UART2_INT_MAP: NA
	// Position of CORE0_UART2_INT_MAP field.
	CORE0_UART2_INT_MAP_CORE0_UART2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_UART2_INT_MAP field.
	CORE0_UART2_INT_MAP_CORE0_UART2_INT_MAP_Msk = 0x3f

	// UART3_INT_MAP: NA
	// Position of CORE0_UART3_INT_MAP field.
	CORE0_UART3_INT_MAP_CORE0_UART3_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_UART3_INT_MAP field.
	CORE0_UART3_INT_MAP_CORE0_UART3_INT_MAP_Msk = 0x3f

	// UART4_INT_MAP: NA
	// Position of CORE0_UART4_INT_MAP field.
	CORE0_UART4_INT_MAP_CORE0_UART4_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_UART4_INT_MAP field.
	CORE0_UART4_INT_MAP_CORE0_UART4_INT_MAP_Msk = 0x3f

	// LCD_CAM_INT_MAP: NA
	// Position of CORE0_LCD_CAM_INT_MAP field.
	CORE0_LCD_CAM_INT_MAP_CORE0_LCD_CAM_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LCD_CAM_INT_MAP field.
	CORE0_LCD_CAM_INT_MAP_CORE0_LCD_CAM_INT_MAP_Msk = 0x3f

	// ADC_INT_MAP: NA
	// Position of CORE0_ADC_INT_MAP field.
	CORE0_ADC_INT_MAP_CORE0_ADC_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_ADC_INT_MAP field.
	CORE0_ADC_INT_MAP_CORE0_ADC_INT_MAP_Msk = 0x3f

	// PWM0_INT_MAP: NA
	// Position of CORE0_PWM0_INT_MAP field.
	CORE0_PWM0_INT_MAP_CORE0_PWM0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PWM0_INT_MAP field.
	CORE0_PWM0_INT_MAP_CORE0_PWM0_INT_MAP_Msk = 0x3f

	// PWM1_INT_MAP: NA
	// Position of CORE0_PWM1_INT_MAP field.
	CORE0_PWM1_INT_MAP_CORE0_PWM1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PWM1_INT_MAP field.
	CORE0_PWM1_INT_MAP_CORE0_PWM1_INT_MAP_Msk = 0x3f

	// CAN0_INT_MAP: NA
	// Position of CORE0_CAN0_INT_MAP field.
	CORE0_CAN0_INT_MAP_CORE0_CAN0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CAN0_INT_MAP field.
	CORE0_CAN0_INT_MAP_CORE0_CAN0_INT_MAP_Msk = 0x3f

	// CAN1_INT_MAP: NA
	// Position of CORE0_CAN1_INT_MAP field.
	CORE0_CAN1_INT_MAP_CORE0_CAN1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CAN1_INT_MAP field.
	CORE0_CAN1_INT_MAP_CORE0_CAN1_INT_MAP_Msk = 0x3f

	// CAN2_INT_MAP: NA
	// Position of CORE0_CAN2_INT_MAP field.
	CORE0_CAN2_INT_MAP_CORE0_CAN2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CAN2_INT_MAP field.
	CORE0_CAN2_INT_MAP_CORE0_CAN2_INT_MAP_Msk = 0x3f

	// RMT_INT_MAP: NA
	// Position of CORE0_RMT_INT_MAP field.
	CORE0_RMT_INT_MAP_CORE0_RMT_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_RMT_INT_MAP field.
	CORE0_RMT_INT_MAP_CORE0_RMT_INT_MAP_Msk = 0x3f

	// I2C0_INT_MAP: NA
	// Position of CORE0_I2C0_INT_MAP field.
	CORE0_I2C0_INT_MAP_CORE0_I2C0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_I2C0_INT_MAP field.
	CORE0_I2C0_INT_MAP_CORE0_I2C0_INT_MAP_Msk = 0x3f

	// I2C1_INT_MAP: NA
	// Position of CORE0_I2C1_INT_MAP field.
	CORE0_I2C1_INT_MAP_CORE0_I2C1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_I2C1_INT_MAP field.
	CORE0_I2C1_INT_MAP_CORE0_I2C1_INT_MAP_Msk = 0x3f

	// TIMERGRP0_T0_INT_MAP: NA
	// Position of CORE0_TIMERGRP0_T0_INT_MAP field.
	CORE0_TIMERGRP0_T0_INT_MAP_CORE0_TIMERGRP0_T0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_TIMERGRP0_T0_INT_MAP field.
	CORE0_TIMERGRP0_T0_INT_MAP_CORE0_TIMERGRP0_T0_INT_MAP_Msk = 0x3f

	// TIMERGRP0_T1_INT_MAP: NA
	// Position of CORE0_TIMERGRP0_T1_INT_MAP field.
	CORE0_TIMERGRP0_T1_INT_MAP_CORE0_TIMERGRP0_T1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_TIMERGRP0_T1_INT_MAP field.
	CORE0_TIMERGRP0_T1_INT_MAP_CORE0_TIMERGRP0_T1_INT_MAP_Msk = 0x3f

	// TIMERGRP0_WDT_INT_MAP: NA
	// Position of CORE0_TIMERGRP0_WDT_INT_MAP field.
	CORE0_TIMERGRP0_WDT_INT_MAP_CORE0_TIMERGRP0_WDT_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_TIMERGRP0_WDT_INT_MAP field.
	CORE0_TIMERGRP0_WDT_INT_MAP_CORE0_TIMERGRP0_WDT_INT_MAP_Msk = 0x3f

	// TIMERGRP1_T0_INT_MAP: NA
	// Position of CORE0_TIMERGRP1_T0_INT_MAP field.
	CORE0_TIMERGRP1_T0_INT_MAP_CORE0_TIMERGRP1_T0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_TIMERGRP1_T0_INT_MAP field.
	CORE0_TIMERGRP1_T0_INT_MAP_CORE0_TIMERGRP1_T0_INT_MAP_Msk = 0x3f

	// TIMERGRP1_T1_INT_MAP: NA
	// Position of CORE0_TIMERGRP1_T1_INT_MAP field.
	CORE0_TIMERGRP1_T1_INT_MAP_CORE0_TIMERGRP1_T1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_TIMERGRP1_T1_INT_MAP field.
	CORE0_TIMERGRP1_T1_INT_MAP_CORE0_TIMERGRP1_T1_INT_MAP_Msk = 0x3f

	// TIMERGRP1_WDT_INT_MAP: NA
	// Position of CORE0_TIMERGRP1_WDT_INT_MAP field.
	CORE0_TIMERGRP1_WDT_INT_MAP_CORE0_TIMERGRP1_WDT_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_TIMERGRP1_WDT_INT_MAP field.
	CORE0_TIMERGRP1_WDT_INT_MAP_CORE0_TIMERGRP1_WDT_INT_MAP_Msk = 0x3f

	// LEDC_INT_MAP: NA
	// Position of CORE0_LEDC_INT_MAP field.
	CORE0_LEDC_INT_MAP_CORE0_LEDC_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LEDC_INT_MAP field.
	CORE0_LEDC_INT_MAP_CORE0_LEDC_INT_MAP_Msk = 0x3f

	// SYSTIMER_TARGET0_INT_MAP: NA
	// Position of CORE0_SYSTIMER_TARGET0_INT_MAP field.
	CORE0_SYSTIMER_TARGET0_INT_MAP_CORE0_SYSTIMER_TARGET0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SYSTIMER_TARGET0_INT_MAP field.
	CORE0_SYSTIMER_TARGET0_INT_MAP_CORE0_SYSTIMER_TARGET0_INT_MAP_Msk = 0x3f

	// SYSTIMER_TARGET1_INT_MAP: NA
	// Position of CORE0_SYSTIMER_TARGET1_INT_MAP field.
	CORE0_SYSTIMER_TARGET1_INT_MAP_CORE0_SYSTIMER_TARGET1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SYSTIMER_TARGET1_INT_MAP field.
	CORE0_SYSTIMER_TARGET1_INT_MAP_CORE0_SYSTIMER_TARGET1_INT_MAP_Msk = 0x3f

	// SYSTIMER_TARGET2_INT_MAP: NA
	// Position of CORE0_SYSTIMER_TARGET2_INT_MAP field.
	CORE0_SYSTIMER_TARGET2_INT_MAP_CORE0_SYSTIMER_TARGET2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SYSTIMER_TARGET2_INT_MAP field.
	CORE0_SYSTIMER_TARGET2_INT_MAP_CORE0_SYSTIMER_TARGET2_INT_MAP_Msk = 0x3f

	// AHB_PDMA_IN_CH0_INT_MAP: NA
	// Position of CORE0_AHB_PDMA_IN_CH0_INT_MAP field.
	CORE0_AHB_PDMA_IN_CH0_INT_MAP_CORE0_AHB_PDMA_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AHB_PDMA_IN_CH0_INT_MAP field.
	CORE0_AHB_PDMA_IN_CH0_INT_MAP_CORE0_AHB_PDMA_IN_CH0_INT_MAP_Msk = 0x3f

	// AHB_PDMA_IN_CH1_INT_MAP: NA
	// Position of CORE0_AHB_PDMA_IN_CH1_INT_MAP field.
	CORE0_AHB_PDMA_IN_CH1_INT_MAP_CORE0_AHB_PDMA_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AHB_PDMA_IN_CH1_INT_MAP field.
	CORE0_AHB_PDMA_IN_CH1_INT_MAP_CORE0_AHB_PDMA_IN_CH1_INT_MAP_Msk = 0x3f

	// AHB_PDMA_IN_CH2_INT_MAP: NA
	// Position of CORE0_AHB_PDMA_IN_CH2_INT_MAP field.
	CORE0_AHB_PDMA_IN_CH2_INT_MAP_CORE0_AHB_PDMA_IN_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AHB_PDMA_IN_CH2_INT_MAP field.
	CORE0_AHB_PDMA_IN_CH2_INT_MAP_CORE0_AHB_PDMA_IN_CH2_INT_MAP_Msk = 0x3f

	// AHB_PDMA_OUT_CH0_INT_MAP: NA
	// Position of CORE0_AHB_PDMA_OUT_CH0_INT_MAP field.
	CORE0_AHB_PDMA_OUT_CH0_INT_MAP_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AHB_PDMA_OUT_CH0_INT_MAP field.
	CORE0_AHB_PDMA_OUT_CH0_INT_MAP_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_Msk = 0x3f

	// AHB_PDMA_OUT_CH1_INT_MAP: NA
	// Position of CORE0_AHB_PDMA_OUT_CH1_INT_MAP field.
	CORE0_AHB_PDMA_OUT_CH1_INT_MAP_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AHB_PDMA_OUT_CH1_INT_MAP field.
	CORE0_AHB_PDMA_OUT_CH1_INT_MAP_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_Msk = 0x3f

	// AHB_PDMA_OUT_CH2_INT_MAP: NA
	// Position of CORE0_AHB_PDMA_OUT_CH2_INT_MAP field.
	CORE0_AHB_PDMA_OUT_CH2_INT_MAP_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AHB_PDMA_OUT_CH2_INT_MAP field.
	CORE0_AHB_PDMA_OUT_CH2_INT_MAP_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_Msk = 0x3f

	// AXI_PDMA_IN_CH0_INT_MAP: NA
	// Position of CORE0_AXI_PDMA_IN_CH0_INT_MAP field.
	CORE0_AXI_PDMA_IN_CH0_INT_MAP_CORE0_AXI_PDMA_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AXI_PDMA_IN_CH0_INT_MAP field.
	CORE0_AXI_PDMA_IN_CH0_INT_MAP_CORE0_AXI_PDMA_IN_CH0_INT_MAP_Msk = 0x3f

	// AXI_PDMA_IN_CH1_INT_MAP: NA
	// Position of CORE0_AXI_PDMA_IN_CH1_INT_MAP field.
	CORE0_AXI_PDMA_IN_CH1_INT_MAP_CORE0_AXI_PDMA_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AXI_PDMA_IN_CH1_INT_MAP field.
	CORE0_AXI_PDMA_IN_CH1_INT_MAP_CORE0_AXI_PDMA_IN_CH1_INT_MAP_Msk = 0x3f

	// AXI_PDMA_IN_CH2_INT_MAP: NA
	// Position of CORE0_AXI_PDMA_IN_CH2_INT_MAP field.
	CORE0_AXI_PDMA_IN_CH2_INT_MAP_CORE0_AXI_PDMA_IN_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AXI_PDMA_IN_CH2_INT_MAP field.
	CORE0_AXI_PDMA_IN_CH2_INT_MAP_CORE0_AXI_PDMA_IN_CH2_INT_MAP_Msk = 0x3f

	// AXI_PDMA_OUT_CH0_INT_MAP: NA
	// Position of CORE0_AXI_PDMA_OUT_CH0_INT_MAP field.
	CORE0_AXI_PDMA_OUT_CH0_INT_MAP_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AXI_PDMA_OUT_CH0_INT_MAP field.
	CORE0_AXI_PDMA_OUT_CH0_INT_MAP_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_Msk = 0x3f

	// AXI_PDMA_OUT_CH1_INT_MAP: NA
	// Position of CORE0_AXI_PDMA_OUT_CH1_INT_MAP field.
	CORE0_AXI_PDMA_OUT_CH1_INT_MAP_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AXI_PDMA_OUT_CH1_INT_MAP field.
	CORE0_AXI_PDMA_OUT_CH1_INT_MAP_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_Msk = 0x3f

	// AXI_PDMA_OUT_CH2_INT_MAP: NA
	// Position of CORE0_AXI_PDMA_OUT_CH2_INT_MAP field.
	CORE0_AXI_PDMA_OUT_CH2_INT_MAP_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AXI_PDMA_OUT_CH2_INT_MAP field.
	CORE0_AXI_PDMA_OUT_CH2_INT_MAP_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_Msk = 0x3f

	// RSA_INT_MAP: NA
	// Position of CORE0_RSA_INT_MAP field.
	CORE0_RSA_INT_MAP_CORE0_RSA_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_RSA_INT_MAP field.
	CORE0_RSA_INT_MAP_CORE0_RSA_INT_MAP_Msk = 0x3f

	// AES_INT_MAP: NA
	// Position of CORE0_AES_INT_MAP field.
	CORE0_AES_INT_MAP_CORE0_AES_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_AES_INT_MAP field.
	CORE0_AES_INT_MAP_CORE0_AES_INT_MAP_Msk = 0x3f

	// SHA_INT_MAP: NA
	// Position of CORE0_SHA_INT_MAP field.
	CORE0_SHA_INT_MAP_CORE0_SHA_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SHA_INT_MAP field.
	CORE0_SHA_INT_MAP_CORE0_SHA_INT_MAP_Msk = 0x3f

	// ECC_INT_MAP: NA
	// Position of CORE0_ECC_INT_MAP field.
	CORE0_ECC_INT_MAP_CORE0_ECC_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_ECC_INT_MAP field.
	CORE0_ECC_INT_MAP_CORE0_ECC_INT_MAP_Msk = 0x3f

	// ECDSA_INT_MAP: NA
	// Position of CORE0_ECDSA_INT_MAP field.
	CORE0_ECDSA_INT_MAP_CORE0_ECDSA_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_ECDSA_INT_MAP field.
	CORE0_ECDSA_INT_MAP_CORE0_ECDSA_INT_MAP_Msk = 0x3f

	// KM_INT_MAP: NA
	// Position of CORE0_KM_INT_MAP field.
	CORE0_KM_INT_MAP_CORE0_KM_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_KM_INT_MAP field.
	CORE0_KM_INT_MAP_CORE0_KM_INT_MAP_Msk = 0x3f

	// GPIO_INT0_MAP: NA
	// Position of CORE0_GPIO_INT0_MAP field.
	CORE0_GPIO_INT0_MAP_CORE0_GPIO_INT0_MAP_Pos = 0x0
	// Bit mask of CORE0_GPIO_INT0_MAP field.
	CORE0_GPIO_INT0_MAP_CORE0_GPIO_INT0_MAP_Msk = 0x3f

	// GPIO_INT1_MAP: NA
	// Position of CORE0_GPIO_INT1_MAP field.
	CORE0_GPIO_INT1_MAP_CORE0_GPIO_INT1_MAP_Pos = 0x0
	// Bit mask of CORE0_GPIO_INT1_MAP field.
	CORE0_GPIO_INT1_MAP_CORE0_GPIO_INT1_MAP_Msk = 0x3f

	// GPIO_INT2_MAP: NA
	// Position of CORE0_GPIO_INT2_MAP field.
	CORE0_GPIO_INT2_MAP_CORE0_GPIO_INT2_MAP_Pos = 0x0
	// Bit mask of CORE0_GPIO_INT2_MAP field.
	CORE0_GPIO_INT2_MAP_CORE0_GPIO_INT2_MAP_Msk = 0x3f

	// GPIO_INT3_MAP: NA
	// Position of CORE0_GPIO_INT3_MAP field.
	CORE0_GPIO_INT3_MAP_CORE0_GPIO_INT3_MAP_Pos = 0x0
	// Bit mask of CORE0_GPIO_INT3_MAP field.
	CORE0_GPIO_INT3_MAP_CORE0_GPIO_INT3_MAP_Msk = 0x3f

	// GPIO_PAD_COMP_INT_MAP: NA
	// Position of CORE0_GPIO_PAD_COMP_INT_MAP field.
	CORE0_GPIO_PAD_COMP_INT_MAP_CORE0_GPIO_PAD_COMP_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_GPIO_PAD_COMP_INT_MAP field.
	CORE0_GPIO_PAD_COMP_INT_MAP_CORE0_GPIO_PAD_COMP_INT_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_0_MAP: NA
	// Position of CORE0_CPU_INT_FROM_CPU_0_MAP field.
	CORE0_CPU_INT_FROM_CPU_0_MAP_CORE0_CPU_INT_FROM_CPU_0_MAP_Pos = 0x0
	// Bit mask of CORE0_CPU_INT_FROM_CPU_0_MAP field.
	CORE0_CPU_INT_FROM_CPU_0_MAP_CORE0_CPU_INT_FROM_CPU_0_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_1_MAP: NA
	// Position of CORE0_CPU_INT_FROM_CPU_1_MAP field.
	CORE0_CPU_INT_FROM_CPU_1_MAP_CORE0_CPU_INT_FROM_CPU_1_MAP_Pos = 0x0
	// Bit mask of CORE0_CPU_INT_FROM_CPU_1_MAP field.
	CORE0_CPU_INT_FROM_CPU_1_MAP_CORE0_CPU_INT_FROM_CPU_1_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_2_MAP: NA
	// Position of CORE0_CPU_INT_FROM_CPU_2_MAP field.
	CORE0_CPU_INT_FROM_CPU_2_MAP_CORE0_CPU_INT_FROM_CPU_2_MAP_Pos = 0x0
	// Bit mask of CORE0_CPU_INT_FROM_CPU_2_MAP field.
	CORE0_CPU_INT_FROM_CPU_2_MAP_CORE0_CPU_INT_FROM_CPU_2_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_3_MAP: NA
	// Position of CORE0_CPU_INT_FROM_CPU_3_MAP field.
	CORE0_CPU_INT_FROM_CPU_3_MAP_CORE0_CPU_INT_FROM_CPU_3_MAP_Pos = 0x0
	// Bit mask of CORE0_CPU_INT_FROM_CPU_3_MAP field.
	CORE0_CPU_INT_FROM_CPU_3_MAP_CORE0_CPU_INT_FROM_CPU_3_MAP_Msk = 0x3f

	// CACHE_INT_MAP: NA
	// Position of CORE0_CACHE_INT_MAP field.
	CORE0_CACHE_INT_MAP_CORE0_CACHE_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CACHE_INT_MAP field.
	CORE0_CACHE_INT_MAP_CORE0_CACHE_INT_MAP_Msk = 0x3f

	// FLASH_MSPI_INT_MAP: NA
	// Position of CORE0_FLASH_MSPI_INT_MAP field.
	CORE0_FLASH_MSPI_INT_MAP_CORE0_FLASH_MSPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_FLASH_MSPI_INT_MAP field.
	CORE0_FLASH_MSPI_INT_MAP_CORE0_FLASH_MSPI_INT_MAP_Msk = 0x3f

	// CSI_BRIDGE_INT_MAP: NA
	// Position of CORE0_CSI_BRIDGE_INT_MAP field.
	CORE0_CSI_BRIDGE_INT_MAP_CORE0_CSI_BRIDGE_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CSI_BRIDGE_INT_MAP field.
	CORE0_CSI_BRIDGE_INT_MAP_CORE0_CSI_BRIDGE_INT_MAP_Msk = 0x3f

	// DSI_BRIDGE_INT_MAP: NA
	// Position of CORE0_DSI_BRIDGE_INT_MAP field.
	CORE0_DSI_BRIDGE_INT_MAP_CORE0_DSI_BRIDGE_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_DSI_BRIDGE_INT_MAP field.
	CORE0_DSI_BRIDGE_INT_MAP_CORE0_DSI_BRIDGE_INT_MAP_Msk = 0x3f

	// CSI_INT_MAP: NA
	// Position of CORE0_CSI_INT_MAP field.
	CORE0_CSI_INT_MAP_CORE0_CSI_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CSI_INT_MAP field.
	CORE0_CSI_INT_MAP_CORE0_CSI_INT_MAP_Msk = 0x3f

	// DSI_INT_MAP: NA
	// Position of CORE0_DSI_INT_MAP field.
	CORE0_DSI_INT_MAP_CORE0_DSI_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_DSI_INT_MAP field.
	CORE0_DSI_INT_MAP_CORE0_DSI_INT_MAP_Msk = 0x3f

	// GMII_PHY_INT_MAP: NA
	// Position of CORE0_GMII_PHY_INT_MAP field.
	CORE0_GMII_PHY_INT_MAP_CORE0_GMII_PHY_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_GMII_PHY_INT_MAP field.
	CORE0_GMII_PHY_INT_MAP_CORE0_GMII_PHY_INT_MAP_Msk = 0x3f

	// LPI_INT_MAP: NA
	// Position of CORE0_LPI_INT_MAP field.
	CORE0_LPI_INT_MAP_CORE0_LPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_LPI_INT_MAP field.
	CORE0_LPI_INT_MAP_CORE0_LPI_INT_MAP_Msk = 0x3f

	// PMT_INT_MAP: NA
	// Position of CORE0_PMT_INT_MAP field.
	CORE0_PMT_INT_MAP_CORE0_PMT_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PMT_INT_MAP field.
	CORE0_PMT_INT_MAP_CORE0_PMT_INT_MAP_Msk = 0x3f

	// SBD_INT_MAP: NA
	// Position of CORE0_SBD_INT_MAP field.
	CORE0_SBD_INT_MAP_CORE0_SBD_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_SBD_INT_MAP field.
	CORE0_SBD_INT_MAP_CORE0_SBD_INT_MAP_Msk = 0x3f

	// USB_OTG_INT_MAP: NA
	// Position of CORE0_USB_OTG_INT_MAP field.
	CORE0_USB_OTG_INT_MAP_CORE0_USB_OTG_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_USB_OTG_INT_MAP field.
	CORE0_USB_OTG_INT_MAP_CORE0_USB_OTG_INT_MAP_Msk = 0x3f

	// USB_OTG_ENDP_MULTI_PROC_INT_MAP: NA
	// Position of CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP field.
	CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP field.
	CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_Msk = 0x3f

	// JPEG_INT_MAP: NA
	// Position of CORE0_JPEG_INT_MAP field.
	CORE0_JPEG_INT_MAP_CORE0_JPEG_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_JPEG_INT_MAP field.
	CORE0_JPEG_INT_MAP_CORE0_JPEG_INT_MAP_Msk = 0x3f

	// PPA_INT_MAP: NA
	// Position of CORE0_PPA_INT_MAP field.
	CORE0_PPA_INT_MAP_CORE0_PPA_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PPA_INT_MAP field.
	CORE0_PPA_INT_MAP_CORE0_PPA_INT_MAP_Msk = 0x3f

	// CORE0_TRACE_INT_MAP: NA
	// Position of CORE0_CORE0_TRACE_INT_MAP field.
	CORE0_CORE0_TRACE_INT_MAP_CORE0_CORE0_TRACE_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CORE0_TRACE_INT_MAP field.
	CORE0_CORE0_TRACE_INT_MAP_CORE0_CORE0_TRACE_INT_MAP_Msk = 0x3f

	// CORE1_TRACE_INT_MAP: NA
	// Position of CORE0_CORE1_TRACE_INT_MAP field.
	CORE0_CORE1_TRACE_INT_MAP_CORE0_CORE1_TRACE_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_CORE1_TRACE_INT_MAP field.
	CORE0_CORE1_TRACE_INT_MAP_CORE0_CORE1_TRACE_INT_MAP_Msk = 0x3f

	// HP_CORE_CTRL_INT_MAP: NA
	// Position of CORE0_HP_CORE_CTRL_INT_MAP field.
	CORE0_HP_CORE_CTRL_INT_MAP_CORE0_HP_CORE_CTRL_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_HP_CORE_CTRL_INT_MAP field.
	CORE0_HP_CORE_CTRL_INT_MAP_CORE0_HP_CORE_CTRL_INT_MAP_Msk = 0x3f

	// ISP_INT_MAP: NA
	// Position of CORE0_ISP_INT_MAP field.
	CORE0_ISP_INT_MAP_CORE0_ISP_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_ISP_INT_MAP field.
	CORE0_ISP_INT_MAP_CORE0_ISP_INT_MAP_Msk = 0x3f

	// I3C_MST_INT_MAP: NA
	// Position of CORE0_I3C_MST_INT_MAP field.
	CORE0_I3C_MST_INT_MAP_CORE0_I3C_MST_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_I3C_MST_INT_MAP field.
	CORE0_I3C_MST_INT_MAP_CORE0_I3C_MST_INT_MAP_Msk = 0x3f

	// I3C_SLV_INT_MAP: NA
	// Position of CORE0_I3C_SLV_INT_MAP field.
	CORE0_I3C_SLV_INT_MAP_CORE0_I3C_SLV_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_I3C_SLV_INT_MAP field.
	CORE0_I3C_SLV_INT_MAP_CORE0_I3C_SLV_INT_MAP_Msk = 0x3f

	// USB_OTG11_INT_MAP: NA
	// Position of CORE0_USB_OTG11_INT_MAP field.
	CORE0_USB_OTG11_INT_MAP_CORE0_USB_OTG11_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_USB_OTG11_INT_MAP field.
	CORE0_USB_OTG11_INT_MAP_CORE0_USB_OTG11_INT_MAP_Msk = 0x3f

	// DMA2D_IN_CH0_INT_MAP: NA
	// Position of CORE0_DMA2D_IN_CH0_INT_MAP field.
	CORE0_DMA2D_IN_CH0_INT_MAP_CORE0_DMA2D_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_DMA2D_IN_CH0_INT_MAP field.
	CORE0_DMA2D_IN_CH0_INT_MAP_CORE0_DMA2D_IN_CH0_INT_MAP_Msk = 0x3f

	// DMA2D_IN_CH1_INT_MAP: NA
	// Position of CORE0_DMA2D_IN_CH1_INT_MAP field.
	CORE0_DMA2D_IN_CH1_INT_MAP_CORE0_DMA2D_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_DMA2D_IN_CH1_INT_MAP field.
	CORE0_DMA2D_IN_CH1_INT_MAP_CORE0_DMA2D_IN_CH1_INT_MAP_Msk = 0x3f

	// DMA2D_OUT_CH0_INT_MAP: NA
	// Position of CORE0_DMA2D_OUT_CH0_INT_MAP field.
	CORE0_DMA2D_OUT_CH0_INT_MAP_CORE0_DMA2D_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_DMA2D_OUT_CH0_INT_MAP field.
	CORE0_DMA2D_OUT_CH0_INT_MAP_CORE0_DMA2D_OUT_CH0_INT_MAP_Msk = 0x3f

	// DMA2D_OUT_CH1_INT_MAP: NA
	// Position of CORE0_DMA2D_OUT_CH1_INT_MAP field.
	CORE0_DMA2D_OUT_CH1_INT_MAP_CORE0_DMA2D_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_DMA2D_OUT_CH1_INT_MAP field.
	CORE0_DMA2D_OUT_CH1_INT_MAP_CORE0_DMA2D_OUT_CH1_INT_MAP_Msk = 0x3f

	// DMA2D_OUT_CH2_INT_MAP: NA
	// Position of CORE0_DMA2D_OUT_CH2_INT_MAP field.
	CORE0_DMA2D_OUT_CH2_INT_MAP_CORE0_DMA2D_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_DMA2D_OUT_CH2_INT_MAP field.
	CORE0_DMA2D_OUT_CH2_INT_MAP_CORE0_DMA2D_OUT_CH2_INT_MAP_Msk = 0x3f

	// PSRAM_MSPI_INT_MAP: NA
	// Position of CORE0_PSRAM_MSPI_INT_MAP field.
	CORE0_PSRAM_MSPI_INT_MAP_CORE0_PSRAM_MSPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PSRAM_MSPI_INT_MAP field.
	CORE0_PSRAM_MSPI_INT_MAP_CORE0_PSRAM_MSPI_INT_MAP_Msk = 0x3f

	// HP_SYSREG_INT_MAP: NA
	// Position of CORE0_HP_SYSREG_INT_MAP field.
	CORE0_HP_SYSREG_INT_MAP_CORE0_HP_SYSREG_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_HP_SYSREG_INT_MAP field.
	CORE0_HP_SYSREG_INT_MAP_CORE0_HP_SYSREG_INT_MAP_Msk = 0x3f

	// PCNT_INT_MAP: NA
	// Position of CORE0_PCNT_INT_MAP field.
	CORE0_PCNT_INT_MAP_CORE0_PCNT_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_PCNT_INT_MAP field.
	CORE0_PCNT_INT_MAP_CORE0_PCNT_INT_MAP_Msk = 0x3f

	// HP_PAU_INT_MAP: NA
	// Position of CORE0_HP_PAU_INT_MAP field.
	CORE0_HP_PAU_INT_MAP_CORE0_HP_PAU_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_HP_PAU_INT_MAP field.
	CORE0_HP_PAU_INT_MAP_CORE0_HP_PAU_INT_MAP_Msk = 0x3f

	// HP_PARLIO_RX_INT_MAP: NA
	// Position of CORE0_HP_PARLIO_RX_INT_MAP field.
	CORE0_HP_PARLIO_RX_INT_MAP_CORE0_HP_PARLIO_RX_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_HP_PARLIO_RX_INT_MAP field.
	CORE0_HP_PARLIO_RX_INT_MAP_CORE0_HP_PARLIO_RX_INT_MAP_Msk = 0x3f

	// HP_PARLIO_TX_INT_MAP: NA
	// Position of CORE0_HP_PARLIO_TX_INT_MAP field.
	CORE0_HP_PARLIO_TX_INT_MAP_CORE0_HP_PARLIO_TX_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_HP_PARLIO_TX_INT_MAP field.
	CORE0_HP_PARLIO_TX_INT_MAP_CORE0_HP_PARLIO_TX_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH0_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_OUT_CH0_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH0_INT_MAP_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_OUT_CH0_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH0_INT_MAP_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH1_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_OUT_CH1_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH1_INT_MAP_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_OUT_CH1_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH1_INT_MAP_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH2_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_OUT_CH2_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH2_INT_MAP_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_OUT_CH2_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH2_INT_MAP_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH3_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_OUT_CH3_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH3_INT_MAP_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_OUT_CH3_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH3_INT_MAP_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH4_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_OUT_CH4_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH4_INT_MAP_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_OUT_CH4_INT_MAP field.
	CORE0_H264_DMA2D_OUT_CH4_INT_MAP_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH0_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_IN_CH0_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH0_INT_MAP_CORE0_H264_DMA2D_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_IN_CH0_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH0_INT_MAP_CORE0_H264_DMA2D_IN_CH0_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH1_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_IN_CH1_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH1_INT_MAP_CORE0_H264_DMA2D_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_IN_CH1_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH1_INT_MAP_CORE0_H264_DMA2D_IN_CH1_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH2_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_IN_CH2_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH2_INT_MAP_CORE0_H264_DMA2D_IN_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_IN_CH2_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH2_INT_MAP_CORE0_H264_DMA2D_IN_CH2_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH3_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_IN_CH3_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH3_INT_MAP_CORE0_H264_DMA2D_IN_CH3_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_IN_CH3_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH3_INT_MAP_CORE0_H264_DMA2D_IN_CH3_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH4_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_IN_CH4_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH4_INT_MAP_CORE0_H264_DMA2D_IN_CH4_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_IN_CH4_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH4_INT_MAP_CORE0_H264_DMA2D_IN_CH4_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH5_INT_MAP: NA
	// Position of CORE0_H264_DMA2D_IN_CH5_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH5_INT_MAP_CORE0_H264_DMA2D_IN_CH5_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_DMA2D_IN_CH5_INT_MAP field.
	CORE0_H264_DMA2D_IN_CH5_INT_MAP_CORE0_H264_DMA2D_IN_CH5_INT_MAP_Msk = 0x3f

	// H264_REG_INT_MAP: NA
	// Position of CORE0_H264_REG_INT_MAP field.
	CORE0_H264_REG_INT_MAP_CORE0_H264_REG_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_H264_REG_INT_MAP field.
	CORE0_H264_REG_INT_MAP_CORE0_H264_REG_INT_MAP_Msk = 0x3f

	// ASSIST_DEBUG_INT_MAP: NA
	// Position of CORE0_ASSIST_DEBUG_INT_MAP field.
	CORE0_ASSIST_DEBUG_INT_MAP_CORE0_ASSIST_DEBUG_INT_MAP_Pos = 0x0
	// Bit mask of CORE0_ASSIST_DEBUG_INT_MAP field.
	CORE0_ASSIST_DEBUG_INT_MAP_CORE0_ASSIST_DEBUG_INT_MAP_Msk = 0x3f

	// INTR_STATUS_REG_0: NA
	// Position of CORE0_INTR_STATUS_0 field.
	CORE0_INTR_STATUS_REG_0_CORE0_INTR_STATUS_0_Pos = 0x0
	// Bit mask of CORE0_INTR_STATUS_0 field.
	CORE0_INTR_STATUS_REG_0_CORE0_INTR_STATUS_0_Msk = 0xffffffff

	// INTR_STATUS_REG_1: NA
	// Position of CORE0_INTR_STATUS_1 field.
	CORE0_INTR_STATUS_REG_1_CORE0_INTR_STATUS_1_Pos = 0x0
	// Bit mask of CORE0_INTR_STATUS_1 field.
	CORE0_INTR_STATUS_REG_1_CORE0_INTR_STATUS_1_Msk = 0xffffffff

	// INTR_STATUS_REG_2: NA
	// Position of CORE0_INTR_STATUS_2 field.
	CORE0_INTR_STATUS_REG_2_CORE0_INTR_STATUS_2_Pos = 0x0
	// Bit mask of CORE0_INTR_STATUS_2 field.
	CORE0_INTR_STATUS_REG_2_CORE0_INTR_STATUS_2_Msk = 0xffffffff

	// INTR_STATUS_REG_3: NA
	// Position of CORE0_INTR_STATUS_3 field.
	CORE0_INTR_STATUS_REG_3_CORE0_INTR_STATUS_3_Pos = 0x0
	// Bit mask of CORE0_INTR_STATUS_3 field.
	CORE0_INTR_STATUS_REG_3_CORE0_INTR_STATUS_3_Msk = 0xffffffff

	// CLOCK_GATE: NA
	// Position of CORE0_REG_CLK_EN field.
	CORE0_CLOCK_GATE_CORE0_REG_CLK_EN_Pos = 0x0
	// Bit mask of CORE0_REG_CLK_EN field.
	CORE0_CLOCK_GATE_CORE0_REG_CLK_EN_Msk = 0x1
	// Bit CORE0_REG_CLK_EN.
	CORE0_CLOCK_GATE_CORE0_REG_CLK_EN = 0x1

	// INTERRUPT_REG_DATE: NA
	// Position of CORE0_INTERRUPT_REG_DATE field.
	CORE0_INTERRUPT_REG_DATE_CORE0_INTERRUPT_REG_DATE_Pos = 0x0
	// Bit mask of CORE0_INTERRUPT_REG_DATE field.
	CORE0_INTERRUPT_REG_DATE_CORE0_INTERRUPT_REG_DATE_Msk = 0xfffffff
)

// Constants for INTERRUPT_CORE1: Interrupt Controller (Core 1)
const (
	// LP_RTC_INT_MAP: NA
	// Position of CORE1_LP_RTC_INT_MAP field.
	CORE1_LP_RTC_INT_MAP_CORE1_LP_RTC_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_RTC_INT_MAP field.
	CORE1_LP_RTC_INT_MAP_CORE1_LP_RTC_INT_MAP_Msk = 0x3f

	// LP_WDT_INT_MAP: NA
	// Position of CORE1_LP_WDT_INT_MAP field.
	CORE1_LP_WDT_INT_MAP_CORE1_LP_WDT_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_WDT_INT_MAP field.
	CORE1_LP_WDT_INT_MAP_CORE1_LP_WDT_INT_MAP_Msk = 0x3f

	// LP_TIMER_REG_0_INT_MAP: NA
	// Position of CORE1_LP_TIMER_REG_0_INT_MAP field.
	CORE1_LP_TIMER_REG_0_INT_MAP_CORE1_LP_TIMER_REG_0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_TIMER_REG_0_INT_MAP field.
	CORE1_LP_TIMER_REG_0_INT_MAP_CORE1_LP_TIMER_REG_0_INT_MAP_Msk = 0x3f

	// LP_TIMER_REG_1_INT_MAP: NA
	// Position of CORE1_LP_TIMER_REG_1_INT_MAP field.
	CORE1_LP_TIMER_REG_1_INT_MAP_CORE1_LP_TIMER_REG_1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_TIMER_REG_1_INT_MAP field.
	CORE1_LP_TIMER_REG_1_INT_MAP_CORE1_LP_TIMER_REG_1_INT_MAP_Msk = 0x3f

	// MB_HP_INT_MAP: NA
	// Position of CORE1_MB_HP_INT_MAP field.
	CORE1_MB_HP_INT_MAP_CORE1_MB_HP_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_MB_HP_INT_MAP field.
	CORE1_MB_HP_INT_MAP_CORE1_MB_HP_INT_MAP_Msk = 0x3f

	// MB_LP_INT_MAP: NA
	// Position of CORE1_MB_LP_INT_MAP field.
	CORE1_MB_LP_INT_MAP_CORE1_MB_LP_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_MB_LP_INT_MAP field.
	CORE1_MB_LP_INT_MAP_CORE1_MB_LP_INT_MAP_Msk = 0x3f

	// PMU_REG_0_INT_MAP: NA
	// Position of CORE1_PMU_REG_0_INT_MAP field.
	CORE1_PMU_REG_0_INT_MAP_CORE1_PMU_REG_0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PMU_REG_0_INT_MAP field.
	CORE1_PMU_REG_0_INT_MAP_CORE1_PMU_REG_0_INT_MAP_Msk = 0x3f

	// PMU_REG_1_INT_MAP: NA
	// Position of CORE1_PMU_REG_1_INT_MAP field.
	CORE1_PMU_REG_1_INT_MAP_CORE1_PMU_REG_1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PMU_REG_1_INT_MAP field.
	CORE1_PMU_REG_1_INT_MAP_CORE1_PMU_REG_1_INT_MAP_Msk = 0x3f

	// LP_ANAPERI_INT_MAP: NA
	// Position of CORE1_LP_ANAPERI_INT_MAP field.
	CORE1_LP_ANAPERI_INT_MAP_CORE1_LP_ANAPERI_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_ANAPERI_INT_MAP field.
	CORE1_LP_ANAPERI_INT_MAP_CORE1_LP_ANAPERI_INT_MAP_Msk = 0x3f

	// LP_ADC_INT_MAP: NA
	// Position of CORE1_LP_ADC_INT_MAP field.
	CORE1_LP_ADC_INT_MAP_CORE1_LP_ADC_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_ADC_INT_MAP field.
	CORE1_LP_ADC_INT_MAP_CORE1_LP_ADC_INT_MAP_Msk = 0x3f

	// LP_GPIO_INT_MAP: NA
	// Position of CORE1_LP_GPIO_INT_MAP field.
	CORE1_LP_GPIO_INT_MAP_CORE1_LP_GPIO_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_GPIO_INT_MAP field.
	CORE1_LP_GPIO_INT_MAP_CORE1_LP_GPIO_INT_MAP_Msk = 0x3f

	// LP_I2C_INT_MAP: NA
	// Position of CORE1_LP_I2C_INT_MAP field.
	CORE1_LP_I2C_INT_MAP_CORE1_LP_I2C_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_I2C_INT_MAP field.
	CORE1_LP_I2C_INT_MAP_CORE1_LP_I2C_INT_MAP_Msk = 0x3f

	// LP_I2S_INT_MAP: NA
	// Position of CORE1_LP_I2S_INT_MAP field.
	CORE1_LP_I2S_INT_MAP_CORE1_LP_I2S_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_I2S_INT_MAP field.
	CORE1_LP_I2S_INT_MAP_CORE1_LP_I2S_INT_MAP_Msk = 0x3f

	// LP_SPI_INT_MAP: NA
	// Position of CORE1_LP_SPI_INT_MAP field.
	CORE1_LP_SPI_INT_MAP_CORE1_LP_SPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_SPI_INT_MAP field.
	CORE1_LP_SPI_INT_MAP_CORE1_LP_SPI_INT_MAP_Msk = 0x3f

	// LP_TOUCH_INT_MAP: NA
	// Position of CORE1_LP_TOUCH_INT_MAP field.
	CORE1_LP_TOUCH_INT_MAP_CORE1_LP_TOUCH_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_TOUCH_INT_MAP field.
	CORE1_LP_TOUCH_INT_MAP_CORE1_LP_TOUCH_INT_MAP_Msk = 0x3f

	// LP_TSENS_INT_MAP: NA
	// Position of CORE1_LP_TSENS_INT_MAP field.
	CORE1_LP_TSENS_INT_MAP_CORE1_LP_TSENS_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_TSENS_INT_MAP field.
	CORE1_LP_TSENS_INT_MAP_CORE1_LP_TSENS_INT_MAP_Msk = 0x3f

	// LP_UART_INT_MAP: NA
	// Position of CORE1_LP_UART_INT_MAP field.
	CORE1_LP_UART_INT_MAP_CORE1_LP_UART_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_UART_INT_MAP field.
	CORE1_LP_UART_INT_MAP_CORE1_LP_UART_INT_MAP_Msk = 0x3f

	// LP_EFUSE_INT_MAP: NA
	// Position of CORE1_LP_EFUSE_INT_MAP field.
	CORE1_LP_EFUSE_INT_MAP_CORE1_LP_EFUSE_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_EFUSE_INT_MAP field.
	CORE1_LP_EFUSE_INT_MAP_CORE1_LP_EFUSE_INT_MAP_Msk = 0x3f

	// LP_SW_INT_MAP: NA
	// Position of CORE1_LP_SW_INT_MAP field.
	CORE1_LP_SW_INT_MAP_CORE1_LP_SW_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_SW_INT_MAP field.
	CORE1_LP_SW_INT_MAP_CORE1_LP_SW_INT_MAP_Msk = 0x3f

	// LP_SYSREG_INT_MAP: NA
	// Position of CORE1_LP_SYSREG_INT_MAP field.
	CORE1_LP_SYSREG_INT_MAP_CORE1_LP_SYSREG_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_SYSREG_INT_MAP field.
	CORE1_LP_SYSREG_INT_MAP_CORE1_LP_SYSREG_INT_MAP_Msk = 0x3f

	// LP_HUK_INT_MAP: NA
	// Position of CORE1_LP_HUK_INT_MAP field.
	CORE1_LP_HUK_INT_MAP_CORE1_LP_HUK_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LP_HUK_INT_MAP field.
	CORE1_LP_HUK_INT_MAP_CORE1_LP_HUK_INT_MAP_Msk = 0x3f

	// SYS_ICM_INT_MAP: NA
	// Position of CORE1_SYS_ICM_INT_MAP field.
	CORE1_SYS_ICM_INT_MAP_CORE1_SYS_ICM_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SYS_ICM_INT_MAP field.
	CORE1_SYS_ICM_INT_MAP_CORE1_SYS_ICM_INT_MAP_Msk = 0x3f

	// USB_DEVICE_INT_MAP: NA
	// Position of CORE1_USB_DEVICE_INT_MAP field.
	CORE1_USB_DEVICE_INT_MAP_CORE1_USB_DEVICE_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_USB_DEVICE_INT_MAP field.
	CORE1_USB_DEVICE_INT_MAP_CORE1_USB_DEVICE_INT_MAP_Msk = 0x3f

	// SDIO_HOST_INT_MAP: NA
	// Position of CORE1_SDIO_HOST_INT_MAP field.
	CORE1_SDIO_HOST_INT_MAP_CORE1_SDIO_HOST_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SDIO_HOST_INT_MAP field.
	CORE1_SDIO_HOST_INT_MAP_CORE1_SDIO_HOST_INT_MAP_Msk = 0x3f

	// GDMA_INT_MAP: NA
	// Position of CORE1_GDMA_INT_MAP field.
	CORE1_GDMA_INT_MAP_CORE1_GDMA_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_GDMA_INT_MAP field.
	CORE1_GDMA_INT_MAP_CORE1_GDMA_INT_MAP_Msk = 0x3f

	// SPI2_INT_MAP: NA
	// Position of CORE1_SPI2_INT_MAP field.
	CORE1_SPI2_INT_MAP_CORE1_SPI2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SPI2_INT_MAP field.
	CORE1_SPI2_INT_MAP_CORE1_SPI2_INT_MAP_Msk = 0x3f

	// SPI3_INT_MAP: NA
	// Position of CORE1_SPI3_INT_MAP field.
	CORE1_SPI3_INT_MAP_CORE1_SPI3_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SPI3_INT_MAP field.
	CORE1_SPI3_INT_MAP_CORE1_SPI3_INT_MAP_Msk = 0x3f

	// I2S0_INT_MAP: NA
	// Position of CORE1_I2S0_INT_MAP field.
	CORE1_I2S0_INT_MAP_CORE1_I2S0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_I2S0_INT_MAP field.
	CORE1_I2S0_INT_MAP_CORE1_I2S0_INT_MAP_Msk = 0x3f

	// I2S1_INT_MAP: NA
	// Position of CORE1_I2S1_INT_MAP field.
	CORE1_I2S1_INT_MAP_CORE1_I2S1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_I2S1_INT_MAP field.
	CORE1_I2S1_INT_MAP_CORE1_I2S1_INT_MAP_Msk = 0x3f

	// I2S2_INT_MAP: NA
	// Position of CORE1_I2S2_INT_MAP field.
	CORE1_I2S2_INT_MAP_CORE1_I2S2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_I2S2_INT_MAP field.
	CORE1_I2S2_INT_MAP_CORE1_I2S2_INT_MAP_Msk = 0x3f

	// UHCI0_INT_MAP: NA
	// Position of CORE1_UHCI0_INT_MAP field.
	CORE1_UHCI0_INT_MAP_CORE1_UHCI0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_UHCI0_INT_MAP field.
	CORE1_UHCI0_INT_MAP_CORE1_UHCI0_INT_MAP_Msk = 0x3f

	// UART0_INT_MAP: NA
	// Position of CORE1_UART0_INT_MAP field.
	CORE1_UART0_INT_MAP_CORE1_UART0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_UART0_INT_MAP field.
	CORE1_UART0_INT_MAP_CORE1_UART0_INT_MAP_Msk = 0x3f

	// UART1_INT_MAP: NA
	// Position of CORE1_UART1_INT_MAP field.
	CORE1_UART1_INT_MAP_CORE1_UART1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_UART1_INT_MAP field.
	CORE1_UART1_INT_MAP_CORE1_UART1_INT_MAP_Msk = 0x3f

	// UART2_INT_MAP: NA
	// Position of CORE1_UART2_INT_MAP field.
	CORE1_UART2_INT_MAP_CORE1_UART2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_UART2_INT_MAP field.
	CORE1_UART2_INT_MAP_CORE1_UART2_INT_MAP_Msk = 0x3f

	// UART3_INT_MAP: NA
	// Position of CORE1_UART3_INT_MAP field.
	CORE1_UART3_INT_MAP_CORE1_UART3_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_UART3_INT_MAP field.
	CORE1_UART3_INT_MAP_CORE1_UART3_INT_MAP_Msk = 0x3f

	// UART4_INT_MAP: NA
	// Position of CORE1_UART4_INT_MAP field.
	CORE1_UART4_INT_MAP_CORE1_UART4_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_UART4_INT_MAP field.
	CORE1_UART4_INT_MAP_CORE1_UART4_INT_MAP_Msk = 0x3f

	// LCD_CAM_INT_MAP: NA
	// Position of CORE1_LCD_CAM_INT_MAP field.
	CORE1_LCD_CAM_INT_MAP_CORE1_LCD_CAM_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LCD_CAM_INT_MAP field.
	CORE1_LCD_CAM_INT_MAP_CORE1_LCD_CAM_INT_MAP_Msk = 0x3f

	// ADC_INT_MAP: NA
	// Position of CORE1_ADC_INT_MAP field.
	CORE1_ADC_INT_MAP_CORE1_ADC_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_ADC_INT_MAP field.
	CORE1_ADC_INT_MAP_CORE1_ADC_INT_MAP_Msk = 0x3f

	// PWM0_INT_MAP: NA
	// Position of CORE1_PWM0_INT_MAP field.
	CORE1_PWM0_INT_MAP_CORE1_PWM0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PWM0_INT_MAP field.
	CORE1_PWM0_INT_MAP_CORE1_PWM0_INT_MAP_Msk = 0x3f

	// PWM1_INT_MAP: NA
	// Position of CORE1_PWM1_INT_MAP field.
	CORE1_PWM1_INT_MAP_CORE1_PWM1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PWM1_INT_MAP field.
	CORE1_PWM1_INT_MAP_CORE1_PWM1_INT_MAP_Msk = 0x3f

	// CAN0_INT_MAP: NA
	// Position of CORE1_CAN0_INT_MAP field.
	CORE1_CAN0_INT_MAP_CORE1_CAN0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CAN0_INT_MAP field.
	CORE1_CAN0_INT_MAP_CORE1_CAN0_INT_MAP_Msk = 0x3f

	// CAN1_INT_MAP: NA
	// Position of CORE1_CAN1_INT_MAP field.
	CORE1_CAN1_INT_MAP_CORE1_CAN1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CAN1_INT_MAP field.
	CORE1_CAN1_INT_MAP_CORE1_CAN1_INT_MAP_Msk = 0x3f

	// CAN2_INT_MAP: NA
	// Position of CORE1_CAN2_INT_MAP field.
	CORE1_CAN2_INT_MAP_CORE1_CAN2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CAN2_INT_MAP field.
	CORE1_CAN2_INT_MAP_CORE1_CAN2_INT_MAP_Msk = 0x3f

	// RMT_INT_MAP: NA
	// Position of CORE1_RMT_INT_MAP field.
	CORE1_RMT_INT_MAP_CORE1_RMT_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_RMT_INT_MAP field.
	CORE1_RMT_INT_MAP_CORE1_RMT_INT_MAP_Msk = 0x3f

	// I2C0_INT_MAP: NA
	// Position of CORE1_I2C0_INT_MAP field.
	CORE1_I2C0_INT_MAP_CORE1_I2C0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_I2C0_INT_MAP field.
	CORE1_I2C0_INT_MAP_CORE1_I2C0_INT_MAP_Msk = 0x3f

	// I2C1_INT_MAP: NA
	// Position of CORE1_I2C1_INT_MAP field.
	CORE1_I2C1_INT_MAP_CORE1_I2C1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_I2C1_INT_MAP field.
	CORE1_I2C1_INT_MAP_CORE1_I2C1_INT_MAP_Msk = 0x3f

	// TIMERGRP0_T0_INT_MAP: NA
	// Position of CORE1_TIMERGRP0_T0_INT_MAP field.
	CORE1_TIMERGRP0_T0_INT_MAP_CORE1_TIMERGRP0_T0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_TIMERGRP0_T0_INT_MAP field.
	CORE1_TIMERGRP0_T0_INT_MAP_CORE1_TIMERGRP0_T0_INT_MAP_Msk = 0x3f

	// TIMERGRP0_T1_INT_MAP: NA
	// Position of CORE1_TIMERGRP0_T1_INT_MAP field.
	CORE1_TIMERGRP0_T1_INT_MAP_CORE1_TIMERGRP0_T1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_TIMERGRP0_T1_INT_MAP field.
	CORE1_TIMERGRP0_T1_INT_MAP_CORE1_TIMERGRP0_T1_INT_MAP_Msk = 0x3f

	// TIMERGRP0_WDT_INT_MAP: NA
	// Position of CORE1_TIMERGRP0_WDT_INT_MAP field.
	CORE1_TIMERGRP0_WDT_INT_MAP_CORE1_TIMERGRP0_WDT_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_TIMERGRP0_WDT_INT_MAP field.
	CORE1_TIMERGRP0_WDT_INT_MAP_CORE1_TIMERGRP0_WDT_INT_MAP_Msk = 0x3f

	// TIMERGRP1_T0_INT_MAP: NA
	// Position of CORE1_TIMERGRP1_T0_INT_MAP field.
	CORE1_TIMERGRP1_T0_INT_MAP_CORE1_TIMERGRP1_T0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_TIMERGRP1_T0_INT_MAP field.
	CORE1_TIMERGRP1_T0_INT_MAP_CORE1_TIMERGRP1_T0_INT_MAP_Msk = 0x3f

	// TIMERGRP1_T1_INT_MAP: NA
	// Position of CORE1_TIMERGRP1_T1_INT_MAP field.
	CORE1_TIMERGRP1_T1_INT_MAP_CORE1_TIMERGRP1_T1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_TIMERGRP1_T1_INT_MAP field.
	CORE1_TIMERGRP1_T1_INT_MAP_CORE1_TIMERGRP1_T1_INT_MAP_Msk = 0x3f

	// TIMERGRP1_WDT_INT_MAP: NA
	// Position of CORE1_TIMERGRP1_WDT_INT_MAP field.
	CORE1_TIMERGRP1_WDT_INT_MAP_CORE1_TIMERGRP1_WDT_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_TIMERGRP1_WDT_INT_MAP field.
	CORE1_TIMERGRP1_WDT_INT_MAP_CORE1_TIMERGRP1_WDT_INT_MAP_Msk = 0x3f

	// LEDC_INT_MAP: NA
	// Position of CORE1_LEDC_INT_MAP field.
	CORE1_LEDC_INT_MAP_CORE1_LEDC_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LEDC_INT_MAP field.
	CORE1_LEDC_INT_MAP_CORE1_LEDC_INT_MAP_Msk = 0x3f

	// SYSTIMER_TARGET0_INT_MAP: NA
	// Position of CORE1_SYSTIMER_TARGET0_INT_MAP field.
	CORE1_SYSTIMER_TARGET0_INT_MAP_CORE1_SYSTIMER_TARGET0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SYSTIMER_TARGET0_INT_MAP field.
	CORE1_SYSTIMER_TARGET0_INT_MAP_CORE1_SYSTIMER_TARGET0_INT_MAP_Msk = 0x3f

	// SYSTIMER_TARGET1_INT_MAP: NA
	// Position of CORE1_SYSTIMER_TARGET1_INT_MAP field.
	CORE1_SYSTIMER_TARGET1_INT_MAP_CORE1_SYSTIMER_TARGET1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SYSTIMER_TARGET1_INT_MAP field.
	CORE1_SYSTIMER_TARGET1_INT_MAP_CORE1_SYSTIMER_TARGET1_INT_MAP_Msk = 0x3f

	// SYSTIMER_TARGET2_INT_MAP: NA
	// Position of CORE1_SYSTIMER_TARGET2_INT_MAP field.
	CORE1_SYSTIMER_TARGET2_INT_MAP_CORE1_SYSTIMER_TARGET2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SYSTIMER_TARGET2_INT_MAP field.
	CORE1_SYSTIMER_TARGET2_INT_MAP_CORE1_SYSTIMER_TARGET2_INT_MAP_Msk = 0x3f

	// AHB_PDMA_IN_CH0_INT_MAP: NA
	// Position of CORE1_AHB_PDMA_IN_CH0_INT_MAP field.
	CORE1_AHB_PDMA_IN_CH0_INT_MAP_CORE1_AHB_PDMA_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AHB_PDMA_IN_CH0_INT_MAP field.
	CORE1_AHB_PDMA_IN_CH0_INT_MAP_CORE1_AHB_PDMA_IN_CH0_INT_MAP_Msk = 0x3f

	// AHB_PDMA_IN_CH1_INT_MAP: NA
	// Position of CORE1_AHB_PDMA_IN_CH1_INT_MAP field.
	CORE1_AHB_PDMA_IN_CH1_INT_MAP_CORE1_AHB_PDMA_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AHB_PDMA_IN_CH1_INT_MAP field.
	CORE1_AHB_PDMA_IN_CH1_INT_MAP_CORE1_AHB_PDMA_IN_CH1_INT_MAP_Msk = 0x3f

	// AHB_PDMA_IN_CH2_INT_MAP: NA
	// Position of CORE1_AHB_PDMA_IN_CH2_INT_MAP field.
	CORE1_AHB_PDMA_IN_CH2_INT_MAP_CORE1_AHB_PDMA_IN_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AHB_PDMA_IN_CH2_INT_MAP field.
	CORE1_AHB_PDMA_IN_CH2_INT_MAP_CORE1_AHB_PDMA_IN_CH2_INT_MAP_Msk = 0x3f

	// AHB_PDMA_OUT_CH0_INT_MAP: NA
	// Position of CORE1_AHB_PDMA_OUT_CH0_INT_MAP field.
	CORE1_AHB_PDMA_OUT_CH0_INT_MAP_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AHB_PDMA_OUT_CH0_INT_MAP field.
	CORE1_AHB_PDMA_OUT_CH0_INT_MAP_CORE1_AHB_PDMA_OUT_CH0_INT_MAP_Msk = 0x3f

	// AHB_PDMA_OUT_CH1_INT_MAP: NA
	// Position of CORE1_AHB_PDMA_OUT_CH1_INT_MAP field.
	CORE1_AHB_PDMA_OUT_CH1_INT_MAP_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AHB_PDMA_OUT_CH1_INT_MAP field.
	CORE1_AHB_PDMA_OUT_CH1_INT_MAP_CORE1_AHB_PDMA_OUT_CH1_INT_MAP_Msk = 0x3f

	// AHB_PDMA_OUT_CH2_INT_MAP: NA
	// Position of CORE1_AHB_PDMA_OUT_CH2_INT_MAP field.
	CORE1_AHB_PDMA_OUT_CH2_INT_MAP_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AHB_PDMA_OUT_CH2_INT_MAP field.
	CORE1_AHB_PDMA_OUT_CH2_INT_MAP_CORE1_AHB_PDMA_OUT_CH2_INT_MAP_Msk = 0x3f

	// AXI_PDMA_IN_CH0_INT_MAP: NA
	// Position of CORE1_AXI_PDMA_IN_CH0_INT_MAP field.
	CORE1_AXI_PDMA_IN_CH0_INT_MAP_CORE1_AXI_PDMA_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AXI_PDMA_IN_CH0_INT_MAP field.
	CORE1_AXI_PDMA_IN_CH0_INT_MAP_CORE1_AXI_PDMA_IN_CH0_INT_MAP_Msk = 0x3f

	// AXI_PDMA_IN_CH1_INT_MAP: NA
	// Position of CORE1_AXI_PDMA_IN_CH1_INT_MAP field.
	CORE1_AXI_PDMA_IN_CH1_INT_MAP_CORE1_AXI_PDMA_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AXI_PDMA_IN_CH1_INT_MAP field.
	CORE1_AXI_PDMA_IN_CH1_INT_MAP_CORE1_AXI_PDMA_IN_CH1_INT_MAP_Msk = 0x3f

	// AXI_PDMA_IN_CH2_INT_MAP: NA
	// Position of CORE1_AXI_PDMA_IN_CH2_INT_MAP field.
	CORE1_AXI_PDMA_IN_CH2_INT_MAP_CORE1_AXI_PDMA_IN_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AXI_PDMA_IN_CH2_INT_MAP field.
	CORE1_AXI_PDMA_IN_CH2_INT_MAP_CORE1_AXI_PDMA_IN_CH2_INT_MAP_Msk = 0x3f

	// AXI_PDMA_OUT_CH0_INT_MAP: NA
	// Position of CORE1_AXI_PDMA_OUT_CH0_INT_MAP field.
	CORE1_AXI_PDMA_OUT_CH0_INT_MAP_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AXI_PDMA_OUT_CH0_INT_MAP field.
	CORE1_AXI_PDMA_OUT_CH0_INT_MAP_CORE1_AXI_PDMA_OUT_CH0_INT_MAP_Msk = 0x3f

	// AXI_PDMA_OUT_CH1_INT_MAP: NA
	// Position of CORE1_AXI_PDMA_OUT_CH1_INT_MAP field.
	CORE1_AXI_PDMA_OUT_CH1_INT_MAP_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AXI_PDMA_OUT_CH1_INT_MAP field.
	CORE1_AXI_PDMA_OUT_CH1_INT_MAP_CORE1_AXI_PDMA_OUT_CH1_INT_MAP_Msk = 0x3f

	// AXI_PDMA_OUT_CH2_INT_MAP: NA
	// Position of CORE1_AXI_PDMA_OUT_CH2_INT_MAP field.
	CORE1_AXI_PDMA_OUT_CH2_INT_MAP_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AXI_PDMA_OUT_CH2_INT_MAP field.
	CORE1_AXI_PDMA_OUT_CH2_INT_MAP_CORE1_AXI_PDMA_OUT_CH2_INT_MAP_Msk = 0x3f

	// RSA_INT_MAP: NA
	// Position of CORE1_RSA_INT_MAP field.
	CORE1_RSA_INT_MAP_CORE1_RSA_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_RSA_INT_MAP field.
	CORE1_RSA_INT_MAP_CORE1_RSA_INT_MAP_Msk = 0x3f

	// AES_INT_MAP: NA
	// Position of CORE1_AES_INT_MAP field.
	CORE1_AES_INT_MAP_CORE1_AES_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_AES_INT_MAP field.
	CORE1_AES_INT_MAP_CORE1_AES_INT_MAP_Msk = 0x3f

	// SHA_INT_MAP: NA
	// Position of CORE1_SHA_INT_MAP field.
	CORE1_SHA_INT_MAP_CORE1_SHA_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SHA_INT_MAP field.
	CORE1_SHA_INT_MAP_CORE1_SHA_INT_MAP_Msk = 0x3f

	// ECC_INT_MAP: NA
	// Position of CORE1_ECC_INT_MAP field.
	CORE1_ECC_INT_MAP_CORE1_ECC_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_ECC_INT_MAP field.
	CORE1_ECC_INT_MAP_CORE1_ECC_INT_MAP_Msk = 0x3f

	// ECDSA_INT_MAP: NA
	// Position of CORE1_ECDSA_INT_MAP field.
	CORE1_ECDSA_INT_MAP_CORE1_ECDSA_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_ECDSA_INT_MAP field.
	CORE1_ECDSA_INT_MAP_CORE1_ECDSA_INT_MAP_Msk = 0x3f

	// KM_INT_MAP: NA
	// Position of CORE1_KM_INT_MAP field.
	CORE1_KM_INT_MAP_CORE1_KM_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_KM_INT_MAP field.
	CORE1_KM_INT_MAP_CORE1_KM_INT_MAP_Msk = 0x3f

	// GPIO_INT0_MAP: NA
	// Position of CORE1_GPIO_INT0_MAP field.
	CORE1_GPIO_INT0_MAP_CORE1_GPIO_INT0_MAP_Pos = 0x0
	// Bit mask of CORE1_GPIO_INT0_MAP field.
	CORE1_GPIO_INT0_MAP_CORE1_GPIO_INT0_MAP_Msk = 0x3f

	// GPIO_INT1_MAP: NA
	// Position of CORE1_GPIO_INT1_MAP field.
	CORE1_GPIO_INT1_MAP_CORE1_GPIO_INT1_MAP_Pos = 0x0
	// Bit mask of CORE1_GPIO_INT1_MAP field.
	CORE1_GPIO_INT1_MAP_CORE1_GPIO_INT1_MAP_Msk = 0x3f

	// GPIO_INT2_MAP: NA
	// Position of CORE1_GPIO_INT2_MAP field.
	CORE1_GPIO_INT2_MAP_CORE1_GPIO_INT2_MAP_Pos = 0x0
	// Bit mask of CORE1_GPIO_INT2_MAP field.
	CORE1_GPIO_INT2_MAP_CORE1_GPIO_INT2_MAP_Msk = 0x3f

	// GPIO_INT3_MAP: NA
	// Position of CORE1_GPIO_INT3_MAP field.
	CORE1_GPIO_INT3_MAP_CORE1_GPIO_INT3_MAP_Pos = 0x0
	// Bit mask of CORE1_GPIO_INT3_MAP field.
	CORE1_GPIO_INT3_MAP_CORE1_GPIO_INT3_MAP_Msk = 0x3f

	// GPIO_PAD_COMP_INT_MAP: NA
	// Position of CORE1_GPIO_PAD_COMP_INT_MAP field.
	CORE1_GPIO_PAD_COMP_INT_MAP_CORE1_GPIO_PAD_COMP_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_GPIO_PAD_COMP_INT_MAP field.
	CORE1_GPIO_PAD_COMP_INT_MAP_CORE1_GPIO_PAD_COMP_INT_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_0_MAP: NA
	// Position of CORE1_CPU_INT_FROM_CPU_0_MAP field.
	CORE1_CPU_INT_FROM_CPU_0_MAP_CORE1_CPU_INT_FROM_CPU_0_MAP_Pos = 0x0
	// Bit mask of CORE1_CPU_INT_FROM_CPU_0_MAP field.
	CORE1_CPU_INT_FROM_CPU_0_MAP_CORE1_CPU_INT_FROM_CPU_0_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_1_MAP: NA
	// Position of CORE1_CPU_INT_FROM_CPU_1_MAP field.
	CORE1_CPU_INT_FROM_CPU_1_MAP_CORE1_CPU_INT_FROM_CPU_1_MAP_Pos = 0x0
	// Bit mask of CORE1_CPU_INT_FROM_CPU_1_MAP field.
	CORE1_CPU_INT_FROM_CPU_1_MAP_CORE1_CPU_INT_FROM_CPU_1_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_2_MAP: NA
	// Position of CORE1_CPU_INT_FROM_CPU_2_MAP field.
	CORE1_CPU_INT_FROM_CPU_2_MAP_CORE1_CPU_INT_FROM_CPU_2_MAP_Pos = 0x0
	// Bit mask of CORE1_CPU_INT_FROM_CPU_2_MAP field.
	CORE1_CPU_INT_FROM_CPU_2_MAP_CORE1_CPU_INT_FROM_CPU_2_MAP_Msk = 0x3f

	// CPU_INT_FROM_CPU_3_MAP: NA
	// Position of CORE1_CPU_INT_FROM_CPU_3_MAP field.
	CORE1_CPU_INT_FROM_CPU_3_MAP_CORE1_CPU_INT_FROM_CPU_3_MAP_Pos = 0x0
	// Bit mask of CORE1_CPU_INT_FROM_CPU_3_MAP field.
	CORE1_CPU_INT_FROM_CPU_3_MAP_CORE1_CPU_INT_FROM_CPU_3_MAP_Msk = 0x3f

	// CACHE_INT_MAP: NA
	// Position of CORE1_CACHE_INT_MAP field.
	CORE1_CACHE_INT_MAP_CORE1_CACHE_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CACHE_INT_MAP field.
	CORE1_CACHE_INT_MAP_CORE1_CACHE_INT_MAP_Msk = 0x3f

	// FLASH_MSPI_INT_MAP: NA
	// Position of CORE1_FLASH_MSPI_INT_MAP field.
	CORE1_FLASH_MSPI_INT_MAP_CORE1_FLASH_MSPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_FLASH_MSPI_INT_MAP field.
	CORE1_FLASH_MSPI_INT_MAP_CORE1_FLASH_MSPI_INT_MAP_Msk = 0x3f

	// CSI_BRIDGE_INT_MAP: NA
	// Position of CORE1_CSI_BRIDGE_INT_MAP field.
	CORE1_CSI_BRIDGE_INT_MAP_CORE1_CSI_BRIDGE_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CSI_BRIDGE_INT_MAP field.
	CORE1_CSI_BRIDGE_INT_MAP_CORE1_CSI_BRIDGE_INT_MAP_Msk = 0x3f

	// DSI_BRIDGE_INT_MAP: NA
	// Position of CORE1_DSI_BRIDGE_INT_MAP field.
	CORE1_DSI_BRIDGE_INT_MAP_CORE1_DSI_BRIDGE_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_DSI_BRIDGE_INT_MAP field.
	CORE1_DSI_BRIDGE_INT_MAP_CORE1_DSI_BRIDGE_INT_MAP_Msk = 0x3f

	// CSI_INT_MAP: NA
	// Position of CORE1_CSI_INT_MAP field.
	CORE1_CSI_INT_MAP_CORE1_CSI_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CSI_INT_MAP field.
	CORE1_CSI_INT_MAP_CORE1_CSI_INT_MAP_Msk = 0x3f

	// DSI_INT_MAP: NA
	// Position of CORE1_DSI_INT_MAP field.
	CORE1_DSI_INT_MAP_CORE1_DSI_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_DSI_INT_MAP field.
	CORE1_DSI_INT_MAP_CORE1_DSI_INT_MAP_Msk = 0x3f

	// GMII_PHY_INT_MAP: NA
	// Position of CORE1_GMII_PHY_INT_MAP field.
	CORE1_GMII_PHY_INT_MAP_CORE1_GMII_PHY_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_GMII_PHY_INT_MAP field.
	CORE1_GMII_PHY_INT_MAP_CORE1_GMII_PHY_INT_MAP_Msk = 0x3f

	// LPI_INT_MAP: NA
	// Position of CORE1_LPI_INT_MAP field.
	CORE1_LPI_INT_MAP_CORE1_LPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_LPI_INT_MAP field.
	CORE1_LPI_INT_MAP_CORE1_LPI_INT_MAP_Msk = 0x3f

	// PMT_INT_MAP: NA
	// Position of CORE1_PMT_INT_MAP field.
	CORE1_PMT_INT_MAP_CORE1_PMT_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PMT_INT_MAP field.
	CORE1_PMT_INT_MAP_CORE1_PMT_INT_MAP_Msk = 0x3f

	// SBD_INT_MAP: NA
	// Position of CORE1_SBD_INT_MAP field.
	CORE1_SBD_INT_MAP_CORE1_SBD_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_SBD_INT_MAP field.
	CORE1_SBD_INT_MAP_CORE1_SBD_INT_MAP_Msk = 0x3f

	// USB_OTG_INT_MAP: NA
	// Position of CORE1_USB_OTG_INT_MAP field.
	CORE1_USB_OTG_INT_MAP_CORE1_USB_OTG_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_USB_OTG_INT_MAP field.
	CORE1_USB_OTG_INT_MAP_CORE1_USB_OTG_INT_MAP_Msk = 0x3f

	// USB_OTG_ENDP_MULTI_PROC_INT_MAP: NA
	// Position of CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP field.
	CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP field.
	CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_Msk = 0x3f

	// JPEG_INT_MAP: NA
	// Position of CORE1_JPEG_INT_MAP field.
	CORE1_JPEG_INT_MAP_CORE1_JPEG_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_JPEG_INT_MAP field.
	CORE1_JPEG_INT_MAP_CORE1_JPEG_INT_MAP_Msk = 0x3f

	// PPA_INT_MAP: NA
	// Position of CORE1_PPA_INT_MAP field.
	CORE1_PPA_INT_MAP_CORE1_PPA_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PPA_INT_MAP field.
	CORE1_PPA_INT_MAP_CORE1_PPA_INT_MAP_Msk = 0x3f

	// CORE0_TRACE_INT_MAP: NA
	// Position of CORE1_CORE0_TRACE_INT_MAP field.
	CORE1_CORE0_TRACE_INT_MAP_CORE1_CORE0_TRACE_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CORE0_TRACE_INT_MAP field.
	CORE1_CORE0_TRACE_INT_MAP_CORE1_CORE0_TRACE_INT_MAP_Msk = 0x3f

	// CORE1_TRACE_INT_MAP: NA
	// Position of CORE1_CORE1_TRACE_INT_MAP field.
	CORE1_CORE1_TRACE_INT_MAP_CORE1_CORE1_TRACE_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_CORE1_TRACE_INT_MAP field.
	CORE1_CORE1_TRACE_INT_MAP_CORE1_CORE1_TRACE_INT_MAP_Msk = 0x3f

	// HP_CORE_CTRL_INT_MAP: NA
	// Position of CORE1_HP_CORE_CTRL_INT_MAP field.
	CORE1_HP_CORE_CTRL_INT_MAP_CORE1_HP_CORE_CTRL_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_HP_CORE_CTRL_INT_MAP field.
	CORE1_HP_CORE_CTRL_INT_MAP_CORE1_HP_CORE_CTRL_INT_MAP_Msk = 0x3f

	// ISP_INT_MAP: NA
	// Position of CORE1_ISP_INT_MAP field.
	CORE1_ISP_INT_MAP_CORE1_ISP_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_ISP_INT_MAP field.
	CORE1_ISP_INT_MAP_CORE1_ISP_INT_MAP_Msk = 0x3f

	// I3C_MST_INT_MAP: NA
	// Position of CORE1_I3C_MST_INT_MAP field.
	CORE1_I3C_MST_INT_MAP_CORE1_I3C_MST_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_I3C_MST_INT_MAP field.
	CORE1_I3C_MST_INT_MAP_CORE1_I3C_MST_INT_MAP_Msk = 0x3f

	// I3C_SLV_INT_MAP: NA
	// Position of CORE1_I3C_SLV_INT_MAP field.
	CORE1_I3C_SLV_INT_MAP_CORE1_I3C_SLV_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_I3C_SLV_INT_MAP field.
	CORE1_I3C_SLV_INT_MAP_CORE1_I3C_SLV_INT_MAP_Msk = 0x3f

	// USB_OTG11_INT_MAP: NA
	// Position of CORE1_USB_OTG11_INT_MAP field.
	CORE1_USB_OTG11_INT_MAP_CORE1_USB_OTG11_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_USB_OTG11_INT_MAP field.
	CORE1_USB_OTG11_INT_MAP_CORE1_USB_OTG11_INT_MAP_Msk = 0x3f

	// DMA2D_IN_CH0_INT_MAP: NA
	// Position of CORE1_DMA2D_IN_CH0_INT_MAP field.
	CORE1_DMA2D_IN_CH0_INT_MAP_CORE1_DMA2D_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_DMA2D_IN_CH0_INT_MAP field.
	CORE1_DMA2D_IN_CH0_INT_MAP_CORE1_DMA2D_IN_CH0_INT_MAP_Msk = 0x3f

	// DMA2D_IN_CH1_INT_MAP: NA
	// Position of CORE1_DMA2D_IN_CH1_INT_MAP field.
	CORE1_DMA2D_IN_CH1_INT_MAP_CORE1_DMA2D_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_DMA2D_IN_CH1_INT_MAP field.
	CORE1_DMA2D_IN_CH1_INT_MAP_CORE1_DMA2D_IN_CH1_INT_MAP_Msk = 0x3f

	// DMA2D_OUT_CH0_INT_MAP: NA
	// Position of CORE1_DMA2D_OUT_CH0_INT_MAP field.
	CORE1_DMA2D_OUT_CH0_INT_MAP_CORE1_DMA2D_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_DMA2D_OUT_CH0_INT_MAP field.
	CORE1_DMA2D_OUT_CH0_INT_MAP_CORE1_DMA2D_OUT_CH0_INT_MAP_Msk = 0x3f

	// DMA2D_OUT_CH1_INT_MAP: NA
	// Position of CORE1_DMA2D_OUT_CH1_INT_MAP field.
	CORE1_DMA2D_OUT_CH1_INT_MAP_CORE1_DMA2D_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_DMA2D_OUT_CH1_INT_MAP field.
	CORE1_DMA2D_OUT_CH1_INT_MAP_CORE1_DMA2D_OUT_CH1_INT_MAP_Msk = 0x3f

	// DMA2D_OUT_CH2_INT_MAP: NA
	// Position of CORE1_DMA2D_OUT_CH2_INT_MAP field.
	CORE1_DMA2D_OUT_CH2_INT_MAP_CORE1_DMA2D_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_DMA2D_OUT_CH2_INT_MAP field.
	CORE1_DMA2D_OUT_CH2_INT_MAP_CORE1_DMA2D_OUT_CH2_INT_MAP_Msk = 0x3f

	// PSRAM_MSPI_INT_MAP: NA
	// Position of CORE1_PSRAM_MSPI_INT_MAP field.
	CORE1_PSRAM_MSPI_INT_MAP_CORE1_PSRAM_MSPI_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PSRAM_MSPI_INT_MAP field.
	CORE1_PSRAM_MSPI_INT_MAP_CORE1_PSRAM_MSPI_INT_MAP_Msk = 0x3f

	// HP_SYSREG_INT_MAP: NA
	// Position of CORE1_HP_SYSREG_INT_MAP field.
	CORE1_HP_SYSREG_INT_MAP_CORE1_HP_SYSREG_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_HP_SYSREG_INT_MAP field.
	CORE1_HP_SYSREG_INT_MAP_CORE1_HP_SYSREG_INT_MAP_Msk = 0x3f

	// PCNT_INT_MAP: NA
	// Position of CORE1_PCNT_INT_MAP field.
	CORE1_PCNT_INT_MAP_CORE1_PCNT_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_PCNT_INT_MAP field.
	CORE1_PCNT_INT_MAP_CORE1_PCNT_INT_MAP_Msk = 0x3f

	// HP_PAU_INT_MAP: NA
	// Position of CORE1_HP_PAU_INT_MAP field.
	CORE1_HP_PAU_INT_MAP_CORE1_HP_PAU_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_HP_PAU_INT_MAP field.
	CORE1_HP_PAU_INT_MAP_CORE1_HP_PAU_INT_MAP_Msk = 0x3f

	// HP_PARLIO_RX_INT_MAP: NA
	// Position of CORE1_HP_PARLIO_RX_INT_MAP field.
	CORE1_HP_PARLIO_RX_INT_MAP_CORE1_HP_PARLIO_RX_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_HP_PARLIO_RX_INT_MAP field.
	CORE1_HP_PARLIO_RX_INT_MAP_CORE1_HP_PARLIO_RX_INT_MAP_Msk = 0x3f

	// HP_PARLIO_TX_INT_MAP: NA
	// Position of CORE1_HP_PARLIO_TX_INT_MAP field.
	CORE1_HP_PARLIO_TX_INT_MAP_CORE1_HP_PARLIO_TX_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_HP_PARLIO_TX_INT_MAP field.
	CORE1_HP_PARLIO_TX_INT_MAP_CORE1_HP_PARLIO_TX_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH0_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_OUT_CH0_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH0_INT_MAP_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_OUT_CH0_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH0_INT_MAP_CORE1_H264_DMA2D_OUT_CH0_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH1_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_OUT_CH1_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH1_INT_MAP_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_OUT_CH1_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH1_INT_MAP_CORE1_H264_DMA2D_OUT_CH1_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH2_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_OUT_CH2_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH2_INT_MAP_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_OUT_CH2_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH2_INT_MAP_CORE1_H264_DMA2D_OUT_CH2_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH3_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_OUT_CH3_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH3_INT_MAP_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_OUT_CH3_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH3_INT_MAP_CORE1_H264_DMA2D_OUT_CH3_INT_MAP_Msk = 0x3f

	// H264_DMA2D_OUT_CH4_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_OUT_CH4_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH4_INT_MAP_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_OUT_CH4_INT_MAP field.
	CORE1_H264_DMA2D_OUT_CH4_INT_MAP_CORE1_H264_DMA2D_OUT_CH4_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH0_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_IN_CH0_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH0_INT_MAP_CORE1_H264_DMA2D_IN_CH0_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_IN_CH0_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH0_INT_MAP_CORE1_H264_DMA2D_IN_CH0_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH1_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_IN_CH1_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH1_INT_MAP_CORE1_H264_DMA2D_IN_CH1_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_IN_CH1_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH1_INT_MAP_CORE1_H264_DMA2D_IN_CH1_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH2_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_IN_CH2_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH2_INT_MAP_CORE1_H264_DMA2D_IN_CH2_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_IN_CH2_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH2_INT_MAP_CORE1_H264_DMA2D_IN_CH2_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH3_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_IN_CH3_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH3_INT_MAP_CORE1_H264_DMA2D_IN_CH3_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_IN_CH3_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH3_INT_MAP_CORE1_H264_DMA2D_IN_CH3_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH4_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_IN_CH4_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH4_INT_MAP_CORE1_H264_DMA2D_IN_CH4_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_IN_CH4_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH4_INT_MAP_CORE1_H264_DMA2D_IN_CH4_INT_MAP_Msk = 0x3f

	// H264_DMA2D_IN_CH5_INT_MAP: NA
	// Position of CORE1_H264_DMA2D_IN_CH5_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH5_INT_MAP_CORE1_H264_DMA2D_IN_CH5_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_DMA2D_IN_CH5_INT_MAP field.
	CORE1_H264_DMA2D_IN_CH5_INT_MAP_CORE1_H264_DMA2D_IN_CH5_INT_MAP_Msk = 0x3f

	// H264_REG_INT_MAP: NA
	// Position of CORE1_H264_REG_INT_MAP field.
	CORE1_H264_REG_INT_MAP_CORE1_H264_REG_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_H264_REG_INT_MAP field.
	CORE1_H264_REG_INT_MAP_CORE1_H264_REG_INT_MAP_Msk = 0x3f

	// ASSIST_DEBUG_INT_MAP: NA
	// Position of CORE1_ASSIST_DEBUG_INT_MAP field.
	CORE1_ASSIST_DEBUG_INT_MAP_CORE1_ASSIST_DEBUG_INT_MAP_Pos = 0x0
	// Bit mask of CORE1_ASSIST_DEBUG_INT_MAP field.
	CORE1_ASSIST_DEBUG_INT_MAP_CORE1_ASSIST_DEBUG_INT_MAP_Msk = 0x3f

	// INTR_STATUS_REG_0: NA
	// Position of CORE1_INTR_STATUS_0 field.
	CORE1_INTR_STATUS_REG_0_CORE1_INTR_STATUS_0_Pos = 0x0
	// Bit mask of CORE1_INTR_STATUS_0 field.
	CORE1_INTR_STATUS_REG_0_CORE1_INTR_STATUS_0_Msk = 0xffffffff

	// INTR_STATUS_REG_1: NA
	// Position of CORE1_INTR_STATUS_1 field.
	CORE1_INTR_STATUS_REG_1_CORE1_INTR_STATUS_1_Pos = 0x0
	// Bit mask of CORE1_INTR_STATUS_1 field.
	CORE1_INTR_STATUS_REG_1_CORE1_INTR_STATUS_1_Msk = 0xffffffff

	// INTR_STATUS_REG_2: NA
	// Position of CORE1_INTR_STATUS_2 field.
	CORE1_INTR_STATUS_REG_2_CORE1_INTR_STATUS_2_Pos = 0x0
	// Bit mask of CORE1_INTR_STATUS_2 field.
	CORE1_INTR_STATUS_REG_2_CORE1_INTR_STATUS_2_Msk = 0xffffffff

	// INTR_STATUS_REG_3: NA
	// Position of CORE1_INTR_STATUS_3 field.
	CORE1_INTR_STATUS_REG_3_CORE1_INTR_STATUS_3_Pos = 0x0
	// Bit mask of CORE1_INTR_STATUS_3 field.
	CORE1_INTR_STATUS_REG_3_CORE1_INTR_STATUS_3_Msk = 0xffffffff

	// CLOCK_GATE: NA
	// Position of CORE1_REG_CLK_EN field.
	CORE1_CLOCK_GATE_CORE1_REG_CLK_EN_Pos = 0x0
	// Bit mask of CORE1_REG_CLK_EN field.
	CORE1_CLOCK_GATE_CORE1_REG_CLK_EN_Msk = 0x1
	// Bit CORE1_REG_CLK_EN.
	CORE1_CLOCK_GATE_CORE1_REG_CLK_EN = 0x1

	// INTERRUPT_REG_DATE: NA
	// Position of CORE1_INTERRUPT_REG_DATE field.
	CORE1_INTERRUPT_REG_DATE_CORE1_INTERRUPT_REG_DATE_Pos = 0x0
	// Bit mask of CORE1_INTERRUPT_REG_DATE field.
	CORE1_INTERRUPT_REG_DATE_CORE1_INTERRUPT_REG_DATE_Msk = 0xfffffff
)

// Constants for MIPI_CSI_BRIDGE: MIPI Camera Interface Bridge
const (
	// CLK_EN: csi bridge register mapping unit clock gating.
	// Position of CLK_EN field.
	CSI_BRIG_CLK_EN_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	CSI_BRIG_CLK_EN_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	CSI_BRIG_CLK_EN_CLK_EN = 0x1

	// CSI_EN: csi bridge enable.
	// Position of CSI_BRIG_EN field.
	CSI_BRIG_CSI_EN_CSI_BRIG_EN_Pos = 0x0
	// Bit mask of CSI_BRIG_EN field.
	CSI_BRIG_CSI_EN_CSI_BRIG_EN_Msk = 0x1
	// Bit CSI_BRIG_EN.
	CSI_BRIG_CSI_EN_CSI_BRIG_EN = 0x1

	// DMA_REQ_CFG: dma request configuration.
	// Position of DMA_BURST_LEN field.
	CSI_BRIG_DMA_REQ_CFG_DMA_BURST_LEN_Pos = 0x0
	// Bit mask of DMA_BURST_LEN field.
	CSI_BRIG_DMA_REQ_CFG_DMA_BURST_LEN_Msk = 0xfff
	// Position of DMA_CFG_UPD_BY_BLK field.
	CSI_BRIG_DMA_REQ_CFG_DMA_CFG_UPD_BY_BLK_Pos = 0xc
	// Bit mask of DMA_CFG_UPD_BY_BLK field.
	CSI_BRIG_DMA_REQ_CFG_DMA_CFG_UPD_BY_BLK_Msk = 0x1000
	// Bit DMA_CFG_UPD_BY_BLK.
	CSI_BRIG_DMA_REQ_CFG_DMA_CFG_UPD_BY_BLK = 0x1000
	// Position of DMA_FORCE_RD_STATUS field.
	CSI_BRIG_DMA_REQ_CFG_DMA_FORCE_RD_STATUS_Pos = 0x10
	// Bit mask of DMA_FORCE_RD_STATUS field.
	CSI_BRIG_DMA_REQ_CFG_DMA_FORCE_RD_STATUS_Msk = 0x10000
	// Bit DMA_FORCE_RD_STATUS.
	CSI_BRIG_DMA_REQ_CFG_DMA_FORCE_RD_STATUS = 0x10000

	// BUF_FLOW_CTL: csi bridge buffer control.
	// Position of CSI_BUF_AFULL_THRD field.
	CSI_BRIG_BUF_FLOW_CTL_CSI_BUF_AFULL_THRD_Pos = 0x0
	// Bit mask of CSI_BUF_AFULL_THRD field.
	CSI_BRIG_BUF_FLOW_CTL_CSI_BUF_AFULL_THRD_Msk = 0x3fff
	// Position of CSI_BUF_DEPTH field.
	CSI_BRIG_BUF_FLOW_CTL_CSI_BUF_DEPTH_Pos = 0x10
	// Bit mask of CSI_BUF_DEPTH field.
	CSI_BRIG_BUF_FLOW_CTL_CSI_BUF_DEPTH_Msk = 0x3fff0000

	// DATA_TYPE_CFG: pixel data type configuration.
	// Position of DATA_TYPE_MIN field.
	CSI_BRIG_DATA_TYPE_CFG_DATA_TYPE_MIN_Pos = 0x0
	// Bit mask of DATA_TYPE_MIN field.
	CSI_BRIG_DATA_TYPE_CFG_DATA_TYPE_MIN_Msk = 0x3f
	// Position of DATA_TYPE_MAX field.
	CSI_BRIG_DATA_TYPE_CFG_DATA_TYPE_MAX_Pos = 0x8
	// Bit mask of DATA_TYPE_MAX field.
	CSI_BRIG_DATA_TYPE_CFG_DATA_TYPE_MAX_Msk = 0x3f00

	// FRAME_CFG: frame configuration.
	// Position of VADR_NUM field.
	CSI_BRIG_FRAME_CFG_VADR_NUM_Pos = 0x0
	// Bit mask of VADR_NUM field.
	CSI_BRIG_FRAME_CFG_VADR_NUM_Msk = 0xfff
	// Position of HADR_NUM field.
	CSI_BRIG_FRAME_CFG_HADR_NUM_Pos = 0xc
	// Bit mask of HADR_NUM field.
	CSI_BRIG_FRAME_CFG_HADR_NUM_Msk = 0xfff000
	// Position of HAS_HSYNC_E field.
	CSI_BRIG_FRAME_CFG_HAS_HSYNC_E_Pos = 0x18
	// Bit mask of HAS_HSYNC_E field.
	CSI_BRIG_FRAME_CFG_HAS_HSYNC_E_Msk = 0x1000000
	// Bit HAS_HSYNC_E.
	CSI_BRIG_FRAME_CFG_HAS_HSYNC_E = 0x1000000
	// Position of VADR_NUM_CHECK field.
	CSI_BRIG_FRAME_CFG_VADR_NUM_CHECK_Pos = 0x19
	// Bit mask of VADR_NUM_CHECK field.
	CSI_BRIG_FRAME_CFG_VADR_NUM_CHECK_Msk = 0x2000000
	// Bit VADR_NUM_CHECK.
	CSI_BRIG_FRAME_CFG_VADR_NUM_CHECK = 0x2000000

	// ENDIAN_MODE: data endianness order configuration.
	// Position of BYTE_ENDIAN_ORDER field.
	CSI_BRIG_ENDIAN_MODE_BYTE_ENDIAN_ORDER_Pos = 0x0
	// Bit mask of BYTE_ENDIAN_ORDER field.
	CSI_BRIG_ENDIAN_MODE_BYTE_ENDIAN_ORDER_Msk = 0x1
	// Bit BYTE_ENDIAN_ORDER.
	CSI_BRIG_ENDIAN_MODE_BYTE_ENDIAN_ORDER = 0x1
	// Position of BIT_ENDIAN_ORDER field.
	CSI_BRIG_ENDIAN_MODE_BIT_ENDIAN_ORDER_Pos = 0x1
	// Bit mask of BIT_ENDIAN_ORDER field.
	CSI_BRIG_ENDIAN_MODE_BIT_ENDIAN_ORDER_Msk = 0x2
	// Bit BIT_ENDIAN_ORDER.
	CSI_BRIG_ENDIAN_MODE_BIT_ENDIAN_ORDER = 0x2

	// INT_RAW: csi bridge interrupt raw.
	// Position of VADR_NUM_GT_INT_RAW field.
	CSI_BRIG_INT_RAW_VADR_NUM_GT_INT_RAW_Pos = 0x0
	// Bit mask of VADR_NUM_GT_INT_RAW field.
	CSI_BRIG_INT_RAW_VADR_NUM_GT_INT_RAW_Msk = 0x1
	// Bit VADR_NUM_GT_INT_RAW.
	CSI_BRIG_INT_RAW_VADR_NUM_GT_INT_RAW = 0x1
	// Position of VADR_NUM_LT_INT_RAW field.
	CSI_BRIG_INT_RAW_VADR_NUM_LT_INT_RAW_Pos = 0x1
	// Bit mask of VADR_NUM_LT_INT_RAW field.
	CSI_BRIG_INT_RAW_VADR_NUM_LT_INT_RAW_Msk = 0x2
	// Bit VADR_NUM_LT_INT_RAW.
	CSI_BRIG_INT_RAW_VADR_NUM_LT_INT_RAW = 0x2
	// Position of DISCARD_INT_RAW field.
	CSI_BRIG_INT_RAW_DISCARD_INT_RAW_Pos = 0x2
	// Bit mask of DISCARD_INT_RAW field.
	CSI_BRIG_INT_RAW_DISCARD_INT_RAW_Msk = 0x4
	// Bit DISCARD_INT_RAW.
	CSI_BRIG_INT_RAW_DISCARD_INT_RAW = 0x4
	// Position of CSI_BUF_OVERRUN_INT_RAW field.
	CSI_BRIG_INT_RAW_CSI_BUF_OVERRUN_INT_RAW_Pos = 0x3
	// Bit mask of CSI_BUF_OVERRUN_INT_RAW field.
	CSI_BRIG_INT_RAW_CSI_BUF_OVERRUN_INT_RAW_Msk = 0x8
	// Bit CSI_BUF_OVERRUN_INT_RAW.
	CSI_BRIG_INT_RAW_CSI_BUF_OVERRUN_INT_RAW = 0x8
	// Position of CSI_ASYNC_FIFO_OVF_INT_RAW field.
	CSI_BRIG_INT_RAW_CSI_ASYNC_FIFO_OVF_INT_RAW_Pos = 0x4
	// Bit mask of CSI_ASYNC_FIFO_OVF_INT_RAW field.
	CSI_BRIG_INT_RAW_CSI_ASYNC_FIFO_OVF_INT_RAW_Msk = 0x10
	// Bit CSI_ASYNC_FIFO_OVF_INT_RAW.
	CSI_BRIG_INT_RAW_CSI_ASYNC_FIFO_OVF_INT_RAW = 0x10
	// Position of DMA_CFG_HAS_UPDATED_INT_RAW field.
	CSI_BRIG_INT_RAW_DMA_CFG_HAS_UPDATED_INT_RAW_Pos = 0x5
	// Bit mask of DMA_CFG_HAS_UPDATED_INT_RAW field.
	CSI_BRIG_INT_RAW_DMA_CFG_HAS_UPDATED_INT_RAW_Msk = 0x20
	// Bit DMA_CFG_HAS_UPDATED_INT_RAW.
	CSI_BRIG_INT_RAW_DMA_CFG_HAS_UPDATED_INT_RAW = 0x20

	// INT_CLR: csi bridge interrupt clr.
	// Position of VADR_NUM_GT_REAL_INT_CLR field.
	CSI_BRIG_INT_CLR_VADR_NUM_GT_REAL_INT_CLR_Pos = 0x0
	// Bit mask of VADR_NUM_GT_REAL_INT_CLR field.
	CSI_BRIG_INT_CLR_VADR_NUM_GT_REAL_INT_CLR_Msk = 0x1
	// Bit VADR_NUM_GT_REAL_INT_CLR.
	CSI_BRIG_INT_CLR_VADR_NUM_GT_REAL_INT_CLR = 0x1
	// Position of VADR_NUM_LT_REAL_INT_CLR field.
	CSI_BRIG_INT_CLR_VADR_NUM_LT_REAL_INT_CLR_Pos = 0x1
	// Bit mask of VADR_NUM_LT_REAL_INT_CLR field.
	CSI_BRIG_INT_CLR_VADR_NUM_LT_REAL_INT_CLR_Msk = 0x2
	// Bit VADR_NUM_LT_REAL_INT_CLR.
	CSI_BRIG_INT_CLR_VADR_NUM_LT_REAL_INT_CLR = 0x2
	// Position of DISCARD_INT_CLR field.
	CSI_BRIG_INT_CLR_DISCARD_INT_CLR_Pos = 0x2
	// Bit mask of DISCARD_INT_CLR field.
	CSI_BRIG_INT_CLR_DISCARD_INT_CLR_Msk = 0x4
	// Bit DISCARD_INT_CLR.
	CSI_BRIG_INT_CLR_DISCARD_INT_CLR = 0x4
	// Position of CSI_BUF_OVERRUN_INT_CLR field.
	CSI_BRIG_INT_CLR_CSI_BUF_OVERRUN_INT_CLR_Pos = 0x3
	// Bit mask of CSI_BUF_OVERRUN_INT_CLR field.
	CSI_BRIG_INT_CLR_CSI_BUF_OVERRUN_INT_CLR_Msk = 0x8
	// Bit CSI_BUF_OVERRUN_INT_CLR.
	CSI_BRIG_INT_CLR_CSI_BUF_OVERRUN_INT_CLR = 0x8
	// Position of CSI_ASYNC_FIFO_OVF_INT_CLR field.
	CSI_BRIG_INT_CLR_CSI_ASYNC_FIFO_OVF_INT_CLR_Pos = 0x4
	// Bit mask of CSI_ASYNC_FIFO_OVF_INT_CLR field.
	CSI_BRIG_INT_CLR_CSI_ASYNC_FIFO_OVF_INT_CLR_Msk = 0x10
	// Bit CSI_ASYNC_FIFO_OVF_INT_CLR.
	CSI_BRIG_INT_CLR_CSI_ASYNC_FIFO_OVF_INT_CLR = 0x10
	// Position of DMA_CFG_HAS_UPDATED_INT_CLR field.
	CSI_BRIG_INT_CLR_DMA_CFG_HAS_UPDATED_INT_CLR_Pos = 0x5
	// Bit mask of DMA_CFG_HAS_UPDATED_INT_CLR field.
	CSI_BRIG_INT_CLR_DMA_CFG_HAS_UPDATED_INT_CLR_Msk = 0x20
	// Bit DMA_CFG_HAS_UPDATED_INT_CLR.
	CSI_BRIG_INT_CLR_DMA_CFG_HAS_UPDATED_INT_CLR = 0x20

	// INT_ST: csi bridge interrupt st.
	// Position of VADR_NUM_GT_INT_ST field.
	CSI_BRIG_INT_ST_VADR_NUM_GT_INT_ST_Pos = 0x0
	// Bit mask of VADR_NUM_GT_INT_ST field.
	CSI_BRIG_INT_ST_VADR_NUM_GT_INT_ST_Msk = 0x1
	// Bit VADR_NUM_GT_INT_ST.
	CSI_BRIG_INT_ST_VADR_NUM_GT_INT_ST = 0x1
	// Position of VADR_NUM_LT_INT_ST field.
	CSI_BRIG_INT_ST_VADR_NUM_LT_INT_ST_Pos = 0x1
	// Bit mask of VADR_NUM_LT_INT_ST field.
	CSI_BRIG_INT_ST_VADR_NUM_LT_INT_ST_Msk = 0x2
	// Bit VADR_NUM_LT_INT_ST.
	CSI_BRIG_INT_ST_VADR_NUM_LT_INT_ST = 0x2
	// Position of DISCARD_INT_ST field.
	CSI_BRIG_INT_ST_DISCARD_INT_ST_Pos = 0x2
	// Bit mask of DISCARD_INT_ST field.
	CSI_BRIG_INT_ST_DISCARD_INT_ST_Msk = 0x4
	// Bit DISCARD_INT_ST.
	CSI_BRIG_INT_ST_DISCARD_INT_ST = 0x4
	// Position of CSI_BUF_OVERRUN_INT_ST field.
	CSI_BRIG_INT_ST_CSI_BUF_OVERRUN_INT_ST_Pos = 0x3
	// Bit mask of CSI_BUF_OVERRUN_INT_ST field.
	CSI_BRIG_INT_ST_CSI_BUF_OVERRUN_INT_ST_Msk = 0x8
	// Bit CSI_BUF_OVERRUN_INT_ST.
	CSI_BRIG_INT_ST_CSI_BUF_OVERRUN_INT_ST = 0x8
	// Position of CSI_ASYNC_FIFO_OVF_INT_ST field.
	CSI_BRIG_INT_ST_CSI_ASYNC_FIFO_OVF_INT_ST_Pos = 0x4
	// Bit mask of CSI_ASYNC_FIFO_OVF_INT_ST field.
	CSI_BRIG_INT_ST_CSI_ASYNC_FIFO_OVF_INT_ST_Msk = 0x10
	// Bit CSI_ASYNC_FIFO_OVF_INT_ST.
	CSI_BRIG_INT_ST_CSI_ASYNC_FIFO_OVF_INT_ST = 0x10
	// Position of DMA_CFG_HAS_UPDATED_INT_ST field.
	CSI_BRIG_INT_ST_DMA_CFG_HAS_UPDATED_INT_ST_Pos = 0x5
	// Bit mask of DMA_CFG_HAS_UPDATED_INT_ST field.
	CSI_BRIG_INT_ST_DMA_CFG_HAS_UPDATED_INT_ST_Msk = 0x20
	// Bit DMA_CFG_HAS_UPDATED_INT_ST.
	CSI_BRIG_INT_ST_DMA_CFG_HAS_UPDATED_INT_ST = 0x20

	// INT_ENA: csi bridge interrupt enable.
	// Position of VADR_NUM_GT_INT_ENA field.
	CSI_BRIG_INT_ENA_VADR_NUM_GT_INT_ENA_Pos = 0x0
	// Bit mask of VADR_NUM_GT_INT_ENA field.
	CSI_BRIG_INT_ENA_VADR_NUM_GT_INT_ENA_Msk = 0x1
	// Bit VADR_NUM_GT_INT_ENA.
	CSI_BRIG_INT_ENA_VADR_NUM_GT_INT_ENA = 0x1
	// Position of VADR_NUM_LT_INT_ENA field.
	CSI_BRIG_INT_ENA_VADR_NUM_LT_INT_ENA_Pos = 0x1
	// Bit mask of VADR_NUM_LT_INT_ENA field.
	CSI_BRIG_INT_ENA_VADR_NUM_LT_INT_ENA_Msk = 0x2
	// Bit VADR_NUM_LT_INT_ENA.
	CSI_BRIG_INT_ENA_VADR_NUM_LT_INT_ENA = 0x2
	// Position of DISCARD_INT_ENA field.
	CSI_BRIG_INT_ENA_DISCARD_INT_ENA_Pos = 0x2
	// Bit mask of DISCARD_INT_ENA field.
	CSI_BRIG_INT_ENA_DISCARD_INT_ENA_Msk = 0x4
	// Bit DISCARD_INT_ENA.
	CSI_BRIG_INT_ENA_DISCARD_INT_ENA = 0x4
	// Position of CSI_BUF_OVERRUN_INT_ENA field.
	CSI_BRIG_INT_ENA_CSI_BUF_OVERRUN_INT_ENA_Pos = 0x3
	// Bit mask of CSI_BUF_OVERRUN_INT_ENA field.
	CSI_BRIG_INT_ENA_CSI_BUF_OVERRUN_INT_ENA_Msk = 0x8
	// Bit CSI_BUF_OVERRUN_INT_ENA.
	CSI_BRIG_INT_ENA_CSI_BUF_OVERRUN_INT_ENA = 0x8
	// Position of CSI_ASYNC_FIFO_OVF_INT_ENA field.
	CSI_BRIG_INT_ENA_CSI_ASYNC_FIFO_OVF_INT_ENA_Pos = 0x4
	// Bit mask of CSI_ASYNC_FIFO_OVF_INT_ENA field.
	CSI_BRIG_INT_ENA_CSI_ASYNC_FIFO_OVF_INT_ENA_Msk = 0x10
	// Bit CSI_ASYNC_FIFO_OVF_INT_ENA.
	CSI_BRIG_INT_ENA_CSI_ASYNC_FIFO_OVF_INT_ENA = 0x10
	// Position of DMA_CFG_HAS_UPDATED_INT_ENA field.
	CSI_BRIG_INT_ENA_DMA_CFG_HAS_UPDATED_INT_ENA_Pos = 0x5
	// Bit mask of DMA_CFG_HAS_UPDATED_INT_ENA field.
	CSI_BRIG_INT_ENA_DMA_CFG_HAS_UPDATED_INT_ENA_Msk = 0x20
	// Bit DMA_CFG_HAS_UPDATED_INT_ENA.
	CSI_BRIG_INT_ENA_DMA_CFG_HAS_UPDATED_INT_ENA = 0x20

	// DMA_REQ_INTERVAL: DMA interval configuration.
	// Position of DMA_REQ_INTERVAL field.
	CSI_BRIG_DMA_REQ_INTERVAL_DMA_REQ_INTERVAL_Pos = 0x0
	// Bit mask of DMA_REQ_INTERVAL field.
	CSI_BRIG_DMA_REQ_INTERVAL_DMA_REQ_INTERVAL_Msk = 0xffff

	// DMABLK_SIZE: DMA block size configuration.
	// Position of DMABLK_SIZE field.
	CSI_BRIG_DMABLK_SIZE_DMABLK_SIZE_Pos = 0x0
	// Bit mask of DMABLK_SIZE field.
	CSI_BRIG_DMABLK_SIZE_DMABLK_SIZE_Msk = 0x1fff

	// RDN_ECO_CS: N/A
	// Position of RDN_ECO_EN field.
	CSI_BRIG_RDN_ECO_CS_RDN_ECO_EN_Pos = 0x0
	// Bit mask of RDN_ECO_EN field.
	CSI_BRIG_RDN_ECO_CS_RDN_ECO_EN_Msk = 0x1
	// Bit RDN_ECO_EN.
	CSI_BRIG_RDN_ECO_CS_RDN_ECO_EN = 0x1
	// Position of RDN_ECO_RESULT field.
	CSI_BRIG_RDN_ECO_CS_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of RDN_ECO_RESULT field.
	CSI_BRIG_RDN_ECO_CS_RDN_ECO_RESULT_Msk = 0x2
	// Bit RDN_ECO_RESULT.
	CSI_BRIG_RDN_ECO_CS_RDN_ECO_RESULT = 0x2

	// RDN_ECO_LOW: N/A
	// Position of RDN_ECO_LOW field.
	CSI_BRIG_RDN_ECO_LOW_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of RDN_ECO_LOW field.
	CSI_BRIG_RDN_ECO_LOW_RDN_ECO_LOW_Msk = 0xffffffff

	// RDN_ECO_HIGH: N/A
	// Position of RDN_ECO_HIGH field.
	CSI_BRIG_RDN_ECO_HIGH_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of RDN_ECO_HIGH field.
	CSI_BRIG_RDN_ECO_HIGH_RDN_ECO_HIGH_Msk = 0xffffffff

	// HOST_CTRL: csi host control by csi bridge.
	// Position of CSI_ENABLECLK field.
	CSI_BRIG_HOST_CTRL_CSI_ENABLECLK_Pos = 0x0
	// Bit mask of CSI_ENABLECLK field.
	CSI_BRIG_HOST_CTRL_CSI_ENABLECLK_Msk = 0x1
	// Bit CSI_ENABLECLK.
	CSI_BRIG_HOST_CTRL_CSI_ENABLECLK = 0x1
	// Position of CSI_CFG_CLK_EN field.
	CSI_BRIG_HOST_CTRL_CSI_CFG_CLK_EN_Pos = 0x1
	// Bit mask of CSI_CFG_CLK_EN field.
	CSI_BRIG_HOST_CTRL_CSI_CFG_CLK_EN_Msk = 0x2
	// Bit CSI_CFG_CLK_EN.
	CSI_BRIG_HOST_CTRL_CSI_CFG_CLK_EN = 0x2
	// Position of LOOPBK_TEST_EN field.
	CSI_BRIG_HOST_CTRL_LOOPBK_TEST_EN_Pos = 0x2
	// Bit mask of LOOPBK_TEST_EN field.
	CSI_BRIG_HOST_CTRL_LOOPBK_TEST_EN_Msk = 0x4
	// Bit LOOPBK_TEST_EN.
	CSI_BRIG_HOST_CTRL_LOOPBK_TEST_EN = 0x4

	// MEM_CTRL: csi bridge buffer control.
	// Position of CSI_BRIDGE_MEM_CLK_FORCE_ON field.
	CSI_BRIG_MEM_CTRL_CSI_BRIDGE_MEM_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of CSI_BRIDGE_MEM_CLK_FORCE_ON field.
	CSI_BRIG_MEM_CTRL_CSI_BRIDGE_MEM_CLK_FORCE_ON_Msk = 0x1
	// Bit CSI_BRIDGE_MEM_CLK_FORCE_ON.
	CSI_BRIG_MEM_CTRL_CSI_BRIDGE_MEM_CLK_FORCE_ON = 0x1
	// Position of CSI_MEM_AUX_CTRL field.
	CSI_BRIG_MEM_CTRL_CSI_MEM_AUX_CTRL_Pos = 0x1
	// Bit mask of CSI_MEM_AUX_CTRL field.
	CSI_BRIG_MEM_CTRL_CSI_MEM_AUX_CTRL_Msk = 0x7ffe
)

// Constants for MIPI_CSI_HOST: MIPI Camera Interface Host
const (
	// VERSION: NA
	// Position of VERSION field.
	CSI_HOST_VERSION_VERSION_Pos = 0x0
	// Bit mask of VERSION field.
	CSI_HOST_VERSION_VERSION_Msk = 0xffffffff

	// N_LANES: NA
	// Position of N_LANES field.
	CSI_HOST_N_LANES_N_LANES_Pos = 0x0
	// Bit mask of N_LANES field.
	CSI_HOST_N_LANES_N_LANES_Msk = 0x7

	// CSI2_RESETN: NA
	// Position of CSI2_RESETN field.
	CSI_HOST_CSI2_RESETN_CSI2_RESETN_Pos = 0x0
	// Bit mask of CSI2_RESETN field.
	CSI_HOST_CSI2_RESETN_CSI2_RESETN_Msk = 0x1
	// Bit CSI2_RESETN.
	CSI_HOST_CSI2_RESETN_CSI2_RESETN = 0x1

	// INT_ST_MAIN: NA
	// Position of ST_STATUS_INT_PHY_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PHY_FATAL_Pos = 0x0
	// Bit mask of ST_STATUS_INT_PHY_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PHY_FATAL_Msk = 0x1
	// Bit ST_STATUS_INT_PHY_FATAL.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PHY_FATAL = 0x1
	// Position of ST_STATUS_INT_PKT_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PKT_FATAL_Pos = 0x1
	// Bit mask of ST_STATUS_INT_PKT_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PKT_FATAL_Msk = 0x2
	// Bit ST_STATUS_INT_PKT_FATAL.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PKT_FATAL = 0x2
	// Position of ST_STATUS_INT_BNDRY_FRAME_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_BNDRY_FRAME_FATAL_Pos = 0x2
	// Bit mask of ST_STATUS_INT_BNDRY_FRAME_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_BNDRY_FRAME_FATAL_Msk = 0x4
	// Bit ST_STATUS_INT_BNDRY_FRAME_FATAL.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_BNDRY_FRAME_FATAL = 0x4
	// Position of ST_STATUS_INT_SEQ_FRAME_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_SEQ_FRAME_FATAL_Pos = 0x3
	// Bit mask of ST_STATUS_INT_SEQ_FRAME_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_SEQ_FRAME_FATAL_Msk = 0x8
	// Bit ST_STATUS_INT_SEQ_FRAME_FATAL.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_SEQ_FRAME_FATAL = 0x8
	// Position of ST_STATUS_INT_CRC_FRAME_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_CRC_FRAME_FATAL_Pos = 0x4
	// Bit mask of ST_STATUS_INT_CRC_FRAME_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_CRC_FRAME_FATAL_Msk = 0x10
	// Bit ST_STATUS_INT_CRC_FRAME_FATAL.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_CRC_FRAME_FATAL = 0x10
	// Position of ST_STATUS_INT_PLD_CRC_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PLD_CRC_FATAL_Pos = 0x5
	// Bit mask of ST_STATUS_INT_PLD_CRC_FATAL field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PLD_CRC_FATAL_Msk = 0x20
	// Bit ST_STATUS_INT_PLD_CRC_FATAL.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PLD_CRC_FATAL = 0x20
	// Position of ST_STATUS_INT_DATA_ID field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_DATA_ID_Pos = 0x6
	// Bit mask of ST_STATUS_INT_DATA_ID field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_DATA_ID_Msk = 0x40
	// Bit ST_STATUS_INT_DATA_ID.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_DATA_ID = 0x40
	// Position of ST_STATUS_INT_ECC_CORRECTED field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_ECC_CORRECTED_Pos = 0x7
	// Bit mask of ST_STATUS_INT_ECC_CORRECTED field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_ECC_CORRECTED_Msk = 0x80
	// Bit ST_STATUS_INT_ECC_CORRECTED.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_ECC_CORRECTED = 0x80
	// Position of ST_STATUS_INT_PHY field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PHY_Pos = 0x10
	// Bit mask of ST_STATUS_INT_PHY field.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PHY_Msk = 0x10000
	// Bit ST_STATUS_INT_PHY.
	CSI_HOST_INT_ST_MAIN_ST_STATUS_INT_PHY = 0x10000

	// PHY_SHUTDOWNZ: NA
	// Position of PHY_SHUTDOWNZ field.
	CSI_HOST_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_Pos = 0x0
	// Bit mask of PHY_SHUTDOWNZ field.
	CSI_HOST_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_Msk = 0x1
	// Bit PHY_SHUTDOWNZ.
	CSI_HOST_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ = 0x1

	// DPHY_RSTZ: NA
	// Position of DPHY_RSTZ field.
	CSI_HOST_DPHY_RSTZ_DPHY_RSTZ_Pos = 0x0
	// Bit mask of DPHY_RSTZ field.
	CSI_HOST_DPHY_RSTZ_DPHY_RSTZ_Msk = 0x1
	// Bit DPHY_RSTZ.
	CSI_HOST_DPHY_RSTZ_DPHY_RSTZ = 0x1

	// PHY_RX: NA
	// Position of PHY_RXULPSESC_0 field.
	CSI_HOST_PHY_RX_PHY_RXULPSESC_0_Pos = 0x0
	// Bit mask of PHY_RXULPSESC_0 field.
	CSI_HOST_PHY_RX_PHY_RXULPSESC_0_Msk = 0x1
	// Bit PHY_RXULPSESC_0.
	CSI_HOST_PHY_RX_PHY_RXULPSESC_0 = 0x1
	// Position of PHY_RXULPSESC_1 field.
	CSI_HOST_PHY_RX_PHY_RXULPSESC_1_Pos = 0x1
	// Bit mask of PHY_RXULPSESC_1 field.
	CSI_HOST_PHY_RX_PHY_RXULPSESC_1_Msk = 0x2
	// Bit PHY_RXULPSESC_1.
	CSI_HOST_PHY_RX_PHY_RXULPSESC_1 = 0x2
	// Position of PHY_RXULPSCLKNOT field.
	CSI_HOST_PHY_RX_PHY_RXULPSCLKNOT_Pos = 0x10
	// Bit mask of PHY_RXULPSCLKNOT field.
	CSI_HOST_PHY_RX_PHY_RXULPSCLKNOT_Msk = 0x10000
	// Bit PHY_RXULPSCLKNOT.
	CSI_HOST_PHY_RX_PHY_RXULPSCLKNOT = 0x10000
	// Position of PHY_RXCLKACTIVEHS field.
	CSI_HOST_PHY_RX_PHY_RXCLKACTIVEHS_Pos = 0x11
	// Bit mask of PHY_RXCLKACTIVEHS field.
	CSI_HOST_PHY_RX_PHY_RXCLKACTIVEHS_Msk = 0x20000
	// Bit PHY_RXCLKACTIVEHS.
	CSI_HOST_PHY_RX_PHY_RXCLKACTIVEHS = 0x20000

	// PHY_STOPSTATE: NA
	// Position of PHY_STOPSTATEDATA_0 field.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_Pos = 0x0
	// Bit mask of PHY_STOPSTATEDATA_0 field.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_Msk = 0x1
	// Bit PHY_STOPSTATEDATA_0.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATEDATA_0 = 0x1
	// Position of PHY_STOPSTATEDATA_1 field.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_Pos = 0x1
	// Bit mask of PHY_STOPSTATEDATA_1 field.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_Msk = 0x2
	// Bit PHY_STOPSTATEDATA_1.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATEDATA_1 = 0x2
	// Position of PHY_STOPSTATECLK field.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATECLK_Pos = 0x10
	// Bit mask of PHY_STOPSTATECLK field.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATECLK_Msk = 0x10000
	// Bit PHY_STOPSTATECLK.
	CSI_HOST_PHY_STOPSTATE_PHY_STOPSTATECLK = 0x10000

	// PHY_TEST_CTRL0: NA
	// Position of PHY_TESTCLR field.
	CSI_HOST_PHY_TEST_CTRL0_PHY_TESTCLR_Pos = 0x0
	// Bit mask of PHY_TESTCLR field.
	CSI_HOST_PHY_TEST_CTRL0_PHY_TESTCLR_Msk = 0x1
	// Bit PHY_TESTCLR.
	CSI_HOST_PHY_TEST_CTRL0_PHY_TESTCLR = 0x1
	// Position of PHY_TESTCLK field.
	CSI_HOST_PHY_TEST_CTRL0_PHY_TESTCLK_Pos = 0x1
	// Bit mask of PHY_TESTCLK field.
	CSI_HOST_PHY_TEST_CTRL0_PHY_TESTCLK_Msk = 0x2
	// Bit PHY_TESTCLK.
	CSI_HOST_PHY_TEST_CTRL0_PHY_TESTCLK = 0x2

	// PHY_TEST_CTRL1: NA
	// Position of PHY_TESTDIN field.
	CSI_HOST_PHY_TEST_CTRL1_PHY_TESTDIN_Pos = 0x0
	// Bit mask of PHY_TESTDIN field.
	CSI_HOST_PHY_TEST_CTRL1_PHY_TESTDIN_Msk = 0xff
	// Position of PHY_TESTDOUT field.
	CSI_HOST_PHY_TEST_CTRL1_PHY_TESTDOUT_Pos = 0x8
	// Bit mask of PHY_TESTDOUT field.
	CSI_HOST_PHY_TEST_CTRL1_PHY_TESTDOUT_Msk = 0xff00
	// Position of PHY_TESTEN field.
	CSI_HOST_PHY_TEST_CTRL1_PHY_TESTEN_Pos = 0x10
	// Bit mask of PHY_TESTEN field.
	CSI_HOST_PHY_TEST_CTRL1_PHY_TESTEN_Msk = 0x10000
	// Bit PHY_TESTEN.
	CSI_HOST_PHY_TEST_CTRL1_PHY_TESTEN = 0x10000

	// VC_EXTENSION: NA
	// Position of VCX field.
	CSI_HOST_VC_EXTENSION_VCX_Pos = 0x0
	// Bit mask of VCX field.
	CSI_HOST_VC_EXTENSION_VCX_Msk = 0x1
	// Bit VCX.
	CSI_HOST_VC_EXTENSION_VCX = 0x1

	// PHY_CAL: NA
	// Position of RXSKEWCALHS field.
	CSI_HOST_PHY_CAL_RXSKEWCALHS_Pos = 0x0
	// Bit mask of RXSKEWCALHS field.
	CSI_HOST_PHY_CAL_RXSKEWCALHS_Msk = 0x1
	// Bit RXSKEWCALHS.
	CSI_HOST_PHY_CAL_RXSKEWCALHS = 0x1

	// INT_ST_PHY_FATAL: NA
	// Position of ST_PHY_ERRSOTSYNCHS_0 field.
	CSI_HOST_INT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_0_Pos = 0x0
	// Bit mask of ST_PHY_ERRSOTSYNCHS_0 field.
	CSI_HOST_INT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_0_Msk = 0x1
	// Bit ST_PHY_ERRSOTSYNCHS_0.
	CSI_HOST_INT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_0 = 0x1
	// Position of ST_PHY_ERRSOTSYNCHS_1 field.
	CSI_HOST_INT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_1_Pos = 0x1
	// Bit mask of ST_PHY_ERRSOTSYNCHS_1 field.
	CSI_HOST_INT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_1_Msk = 0x2
	// Bit ST_PHY_ERRSOTSYNCHS_1.
	CSI_HOST_INT_ST_PHY_FATAL_ST_PHY_ERRSOTSYNCHS_1 = 0x2

	// INT_MSK_PHY_FATAL: NA
	// Position of MASK_PHY_ERRSOTSYNCHS_0 field.
	CSI_HOST_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_Pos = 0x0
	// Bit mask of MASK_PHY_ERRSOTSYNCHS_0 field.
	CSI_HOST_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_Msk = 0x1
	// Bit MASK_PHY_ERRSOTSYNCHS_0.
	CSI_HOST_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0 = 0x1
	// Position of MASK_PHY_ERRSOTSYNCHS_1 field.
	CSI_HOST_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_Pos = 0x1
	// Bit mask of MASK_PHY_ERRSOTSYNCHS_1 field.
	CSI_HOST_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_Msk = 0x2
	// Bit MASK_PHY_ERRSOTSYNCHS_1.
	CSI_HOST_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1 = 0x2

	// INT_FORCE_PHY_FATAL: NA
	// Position of FORCE_PHY_ERRSOTSYNCHS_0 field.
	CSI_HOST_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_Pos = 0x0
	// Bit mask of FORCE_PHY_ERRSOTSYNCHS_0 field.
	CSI_HOST_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_Msk = 0x1
	// Bit FORCE_PHY_ERRSOTSYNCHS_0.
	CSI_HOST_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0 = 0x1
	// Position of FORCE_PHY_ERRSOTSYNCHS_1 field.
	CSI_HOST_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_Pos = 0x1
	// Bit mask of FORCE_PHY_ERRSOTSYNCHS_1 field.
	CSI_HOST_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_Msk = 0x2
	// Bit FORCE_PHY_ERRSOTSYNCHS_1.
	CSI_HOST_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1 = 0x2

	// INT_ST_PKT_FATAL: NA
	// Position of ST_ERR_ECC_DOUBLE field.
	CSI_HOST_INT_ST_PKT_FATAL_ST_ERR_ECC_DOUBLE_Pos = 0x0
	// Bit mask of ST_ERR_ECC_DOUBLE field.
	CSI_HOST_INT_ST_PKT_FATAL_ST_ERR_ECC_DOUBLE_Msk = 0x1
	// Bit ST_ERR_ECC_DOUBLE.
	CSI_HOST_INT_ST_PKT_FATAL_ST_ERR_ECC_DOUBLE = 0x1
	// Position of ST_SHORTER_PAYLOAD field.
	CSI_HOST_INT_ST_PKT_FATAL_ST_SHORTER_PAYLOAD_Pos = 0x1
	// Bit mask of ST_SHORTER_PAYLOAD field.
	CSI_HOST_INT_ST_PKT_FATAL_ST_SHORTER_PAYLOAD_Msk = 0x2
	// Bit ST_SHORTER_PAYLOAD.
	CSI_HOST_INT_ST_PKT_FATAL_ST_SHORTER_PAYLOAD = 0x2

	// INT_MSK_PKT_FATAL: NA
	// Position of MASK_ERR_ECC_DOUBLE field.
	CSI_HOST_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_Pos = 0x0
	// Bit mask of MASK_ERR_ECC_DOUBLE field.
	CSI_HOST_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_Msk = 0x1
	// Bit MASK_ERR_ECC_DOUBLE.
	CSI_HOST_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE = 0x1
	// Position of MASK_SHORTER_PAYLOAD field.
	CSI_HOST_INT_MSK_PKT_FATAL_MASK_SHORTER_PAYLOAD_Pos = 0x1
	// Bit mask of MASK_SHORTER_PAYLOAD field.
	CSI_HOST_INT_MSK_PKT_FATAL_MASK_SHORTER_PAYLOAD_Msk = 0x2
	// Bit MASK_SHORTER_PAYLOAD.
	CSI_HOST_INT_MSK_PKT_FATAL_MASK_SHORTER_PAYLOAD = 0x2

	// INT_FORCE_PKT_FATAL: NA
	// Position of FORCE_ERR_ECC_DOUBLE field.
	CSI_HOST_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_Pos = 0x0
	// Bit mask of FORCE_ERR_ECC_DOUBLE field.
	CSI_HOST_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_Msk = 0x1
	// Bit FORCE_ERR_ECC_DOUBLE.
	CSI_HOST_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE = 0x1
	// Position of FORCE_SHORTER_PAYLOAD field.
	CSI_HOST_INT_FORCE_PKT_FATAL_FORCE_SHORTER_PAYLOAD_Pos = 0x1
	// Bit mask of FORCE_SHORTER_PAYLOAD field.
	CSI_HOST_INT_FORCE_PKT_FATAL_FORCE_SHORTER_PAYLOAD_Msk = 0x2
	// Bit FORCE_SHORTER_PAYLOAD.
	CSI_HOST_INT_FORCE_PKT_FATAL_FORCE_SHORTER_PAYLOAD = 0x2

	// INT_ST_PHY: NA
	// Position of ST_PHY_ERRSOTHS_0 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRSOTHS_0_Pos = 0x0
	// Bit mask of ST_PHY_ERRSOTHS_0 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRSOTHS_0_Msk = 0x1
	// Bit ST_PHY_ERRSOTHS_0.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRSOTHS_0 = 0x1
	// Position of ST_PHY_ERRSOTHS_1 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRSOTHS_1_Pos = 0x1
	// Bit mask of ST_PHY_ERRSOTHS_1 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRSOTHS_1_Msk = 0x2
	// Bit ST_PHY_ERRSOTHS_1.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRSOTHS_1 = 0x2
	// Position of ST_PHY_ERRESC_0 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRESC_0_Pos = 0x10
	// Bit mask of ST_PHY_ERRESC_0 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRESC_0_Msk = 0x10000
	// Bit ST_PHY_ERRESC_0.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRESC_0 = 0x10000
	// Position of ST_PHY_ERRESC_1 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRESC_1_Pos = 0x11
	// Bit mask of ST_PHY_ERRESC_1 field.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRESC_1_Msk = 0x20000
	// Bit ST_PHY_ERRESC_1.
	CSI_HOST_INT_ST_PHY_ST_PHY_ERRESC_1 = 0x20000

	// INT_MSK_PHY: NA
	// Position of MASK_PHY_ERRSOTHS_0 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_Pos = 0x0
	// Bit mask of MASK_PHY_ERRSOTHS_0 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_Msk = 0x1
	// Bit MASK_PHY_ERRSOTHS_0.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0 = 0x1
	// Position of MASK_PHY_ERRSOTHS_1 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_Pos = 0x1
	// Bit mask of MASK_PHY_ERRSOTHS_1 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_Msk = 0x2
	// Bit MASK_PHY_ERRSOTHS_1.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1 = 0x2
	// Position of MASK_PHY_ERRESC_0 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRESC_0_Pos = 0x10
	// Bit mask of MASK_PHY_ERRESC_0 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRESC_0_Msk = 0x10000
	// Bit MASK_PHY_ERRESC_0.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRESC_0 = 0x10000
	// Position of MASK_PHY_ERRESC_1 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRESC_1_Pos = 0x11
	// Bit mask of MASK_PHY_ERRESC_1 field.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRESC_1_Msk = 0x20000
	// Bit MASK_PHY_ERRESC_1.
	CSI_HOST_INT_MSK_PHY_MASK_PHY_ERRESC_1 = 0x20000

	// INT_FORCE_PHY: NA
	// Position of FORCE_PHY_ERRSOTHS_0 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_Pos = 0x0
	// Bit mask of FORCE_PHY_ERRSOTHS_0 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_Msk = 0x1
	// Bit FORCE_PHY_ERRSOTHS_0.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0 = 0x1
	// Position of FORCE_PHY_ERRSOTHS_1 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_Pos = 0x1
	// Bit mask of FORCE_PHY_ERRSOTHS_1 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_Msk = 0x2
	// Bit FORCE_PHY_ERRSOTHS_1.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1 = 0x2
	// Position of FORCE_PHY_ERRESC_0 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_Pos = 0x10
	// Bit mask of FORCE_PHY_ERRESC_0 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_Msk = 0x10000
	// Bit FORCE_PHY_ERRESC_0.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRESC_0 = 0x10000
	// Position of FORCE_PHY_ERRESC_1 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_Pos = 0x11
	// Bit mask of FORCE_PHY_ERRESC_1 field.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_Msk = 0x20000
	// Bit FORCE_PHY_ERRESC_1.
	CSI_HOST_INT_FORCE_PHY_FORCE_PHY_ERRESC_1 = 0x20000

	// INT_ST_BNDRY_FRAME_FATAL: NA
	// Position of ST_ERR_F_BNDRY_MATCH_VC0 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC0_Pos = 0x0
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC0 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC0_Msk = 0x1
	// Bit ST_ERR_F_BNDRY_MATCH_VC0.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC0 = 0x1
	// Position of ST_ERR_F_BNDRY_MATCH_VC1 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC1_Pos = 0x1
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC1 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC1_Msk = 0x2
	// Bit ST_ERR_F_BNDRY_MATCH_VC1.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC1 = 0x2
	// Position of ST_ERR_F_BNDRY_MATCH_VC2 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC2_Pos = 0x2
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC2 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC2_Msk = 0x4
	// Bit ST_ERR_F_BNDRY_MATCH_VC2.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC2 = 0x4
	// Position of ST_ERR_F_BNDRY_MATCH_VC3 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC3_Pos = 0x3
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC3 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC3_Msk = 0x8
	// Bit ST_ERR_F_BNDRY_MATCH_VC3.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC3 = 0x8
	// Position of ST_ERR_F_BNDRY_MATCH_VC4 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC4_Pos = 0x4
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC4 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC4_Msk = 0x10
	// Bit ST_ERR_F_BNDRY_MATCH_VC4.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC4 = 0x10
	// Position of ST_ERR_F_BNDRY_MATCH_VC5 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC5_Pos = 0x5
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC5 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC5_Msk = 0x20
	// Bit ST_ERR_F_BNDRY_MATCH_VC5.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC5 = 0x20
	// Position of ST_ERR_F_BNDRY_MATCH_VC6 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC6_Pos = 0x6
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC6 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC6_Msk = 0x40
	// Bit ST_ERR_F_BNDRY_MATCH_VC6.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC6 = 0x40
	// Position of ST_ERR_F_BNDRY_MATCH_VC7 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC7_Pos = 0x7
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC7 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC7_Msk = 0x80
	// Bit ST_ERR_F_BNDRY_MATCH_VC7.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC7 = 0x80
	// Position of ST_ERR_F_BNDRY_MATCH_VC8 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC8_Pos = 0x8
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC8 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC8_Msk = 0x100
	// Bit ST_ERR_F_BNDRY_MATCH_VC8.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC8 = 0x100
	// Position of ST_ERR_F_BNDRY_MATCH_VC9 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC9_Pos = 0x9
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC9 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC9_Msk = 0x200
	// Bit ST_ERR_F_BNDRY_MATCH_VC9.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC9 = 0x200
	// Position of ST_ERR_F_BNDRY_MATCH_VC10 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC10_Pos = 0xa
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC10 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC10_Msk = 0x400
	// Bit ST_ERR_F_BNDRY_MATCH_VC10.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC10 = 0x400
	// Position of ST_ERR_F_BNDRY_MATCH_VC11 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC11_Pos = 0xb
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC11 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC11_Msk = 0x800
	// Bit ST_ERR_F_BNDRY_MATCH_VC11.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC11 = 0x800
	// Position of ST_ERR_F_BNDRY_MATCH_VC12 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC12_Pos = 0xc
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC12 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC12_Msk = 0x1000
	// Bit ST_ERR_F_BNDRY_MATCH_VC12.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC12 = 0x1000
	// Position of ST_ERR_F_BNDRY_MATCH_VC13 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC13_Pos = 0xd
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC13 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC13_Msk = 0x2000
	// Bit ST_ERR_F_BNDRY_MATCH_VC13.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC13 = 0x2000
	// Position of ST_ERR_F_BNDRY_MATCH_VC14 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC14_Pos = 0xe
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC14 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC14_Msk = 0x4000
	// Bit ST_ERR_F_BNDRY_MATCH_VC14.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC14 = 0x4000
	// Position of ST_ERR_F_BNDRY_MATCH_VC15 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC15_Pos = 0xf
	// Bit mask of ST_ERR_F_BNDRY_MATCH_VC15 field.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC15_Msk = 0x8000
	// Bit ST_ERR_F_BNDRY_MATCH_VC15.
	CSI_HOST_INT_ST_BNDRY_FRAME_FATAL_ST_ERR_F_BNDRY_MATCH_VC15 = 0x8000

	// INT_MSK_BNDRY_FRAME_FATAL: NA
	// Position of MASK_ERR_F_BNDRY_MATCH_VC0 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC0_Pos = 0x0
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC0 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC0_Msk = 0x1
	// Bit MASK_ERR_F_BNDRY_MATCH_VC0.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC0 = 0x1
	// Position of MASK_ERR_F_BNDRY_MATCH_VC1 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC1_Pos = 0x1
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC1 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC1_Msk = 0x2
	// Bit MASK_ERR_F_BNDRY_MATCH_VC1.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC1 = 0x2
	// Position of MASK_ERR_F_BNDRY_MATCH_VC2 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC2_Pos = 0x2
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC2 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC2_Msk = 0x4
	// Bit MASK_ERR_F_BNDRY_MATCH_VC2.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC2 = 0x4
	// Position of MASK_ERR_F_BNDRY_MATCH_VC3 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC3_Pos = 0x3
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC3 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC3_Msk = 0x8
	// Bit MASK_ERR_F_BNDRY_MATCH_VC3.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC3 = 0x8
	// Position of MASK_ERR_F_BNDRY_MATCH_VC4 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC4_Pos = 0x4
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC4 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC4_Msk = 0x10
	// Bit MASK_ERR_F_BNDRY_MATCH_VC4.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC4 = 0x10
	// Position of MASK_ERR_F_BNDRY_MATCH_VC5 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC5_Pos = 0x5
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC5 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC5_Msk = 0x20
	// Bit MASK_ERR_F_BNDRY_MATCH_VC5.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC5 = 0x20
	// Position of MASK_ERR_F_BNDRY_MATCH_VC6 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC6_Pos = 0x6
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC6 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC6_Msk = 0x40
	// Bit MASK_ERR_F_BNDRY_MATCH_VC6.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC6 = 0x40
	// Position of MASK_ERR_F_BNDRY_MATCH_VC7 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC7_Pos = 0x7
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC7 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC7_Msk = 0x80
	// Bit MASK_ERR_F_BNDRY_MATCH_VC7.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC7 = 0x80
	// Position of MASK_ERR_F_BNDRY_MATCH_VC8 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC8_Pos = 0x8
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC8 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC8_Msk = 0x100
	// Bit MASK_ERR_F_BNDRY_MATCH_VC8.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC8 = 0x100
	// Position of MASK_ERR_F_BNDRY_MATCH_VC9 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC9_Pos = 0x9
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC9 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC9_Msk = 0x200
	// Bit MASK_ERR_F_BNDRY_MATCH_VC9.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC9 = 0x200
	// Position of MASK_ERR_F_BNDRY_MATCH_VC10 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC10_Pos = 0xa
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC10 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC10_Msk = 0x400
	// Bit MASK_ERR_F_BNDRY_MATCH_VC10.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC10 = 0x400
	// Position of MASK_ERR_F_BNDRY_MATCH_VC11 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC11_Pos = 0xb
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC11 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC11_Msk = 0x800
	// Bit MASK_ERR_F_BNDRY_MATCH_VC11.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC11 = 0x800
	// Position of MASK_ERR_F_BNDRY_MATCH_VC12 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC12_Pos = 0xc
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC12 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC12_Msk = 0x1000
	// Bit MASK_ERR_F_BNDRY_MATCH_VC12.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC12 = 0x1000
	// Position of MASK_ERR_F_BNDRY_MATCH_VC13 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC13_Pos = 0xd
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC13 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC13_Msk = 0x2000
	// Bit MASK_ERR_F_BNDRY_MATCH_VC13.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC13 = 0x2000
	// Position of MASK_ERR_F_BNDRY_MATCH_VC14 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC14_Pos = 0xe
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC14 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC14_Msk = 0x4000
	// Bit MASK_ERR_F_BNDRY_MATCH_VC14.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC14 = 0x4000
	// Position of MASK_ERR_F_BNDRY_MATCH_VC15 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC15_Pos = 0xf
	// Bit mask of MASK_ERR_F_BNDRY_MATCH_VC15 field.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC15_Msk = 0x8000
	// Bit MASK_ERR_F_BNDRY_MATCH_VC15.
	CSI_HOST_INT_MSK_BNDRY_FRAME_FATAL_MASK_ERR_F_BNDRY_MATCH_VC15 = 0x8000

	// INT_FORCE_BNDRY_FRAME_FATAL: NA
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC0 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_Pos = 0x0
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC0 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_Msk = 0x1
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC0.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0 = 0x1
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC1 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_Pos = 0x1
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC1 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_Msk = 0x2
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC1.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1 = 0x2
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC2 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_Pos = 0x2
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC2 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_Msk = 0x4
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC2.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2 = 0x4
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC3 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_Pos = 0x3
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC3 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_Msk = 0x8
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC3.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3 = 0x8
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC4 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_Pos = 0x4
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC4 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_Msk = 0x10
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC4.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4 = 0x10
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC5 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_Pos = 0x5
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC5 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_Msk = 0x20
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC5.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5 = 0x20
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC6 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_Pos = 0x6
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC6 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_Msk = 0x40
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC6.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6 = 0x40
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC7 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_Pos = 0x7
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC7 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_Msk = 0x80
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC7.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7 = 0x80
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC8 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_Pos = 0x8
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC8 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_Msk = 0x100
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC8.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8 = 0x100
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC9 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_Pos = 0x9
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC9 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_Msk = 0x200
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC9.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9 = 0x200
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC10 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_Pos = 0xa
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC10 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_Msk = 0x400
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC10.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10 = 0x400
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC11 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_Pos = 0xb
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC11 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_Msk = 0x800
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC11.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11 = 0x800
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC12 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_Pos = 0xc
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC12 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_Msk = 0x1000
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC12.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12 = 0x1000
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC13 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_Pos = 0xd
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC13 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_Msk = 0x2000
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC13.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13 = 0x2000
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC14 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_Pos = 0xe
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC14 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_Msk = 0x4000
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC14.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14 = 0x4000
	// Position of FORCE_ERR_F_BNDRY_MATCH_VC15 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_Pos = 0xf
	// Bit mask of FORCE_ERR_F_BNDRY_MATCH_VC15 field.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_Msk = 0x8000
	// Bit FORCE_ERR_F_BNDRY_MATCH_VC15.
	CSI_HOST_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15 = 0x8000

	// INT_ST_SEQ_FRAME_FATAL: NA
	// Position of ST_ERR_F_SEQ_VC0 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC0_Pos = 0x0
	// Bit mask of ST_ERR_F_SEQ_VC0 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC0_Msk = 0x1
	// Bit ST_ERR_F_SEQ_VC0.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC0 = 0x1
	// Position of ST_ERR_F_SEQ_VC1 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC1_Pos = 0x1
	// Bit mask of ST_ERR_F_SEQ_VC1 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC1_Msk = 0x2
	// Bit ST_ERR_F_SEQ_VC1.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC1 = 0x2
	// Position of ST_ERR_F_SEQ_VC2 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC2_Pos = 0x2
	// Bit mask of ST_ERR_F_SEQ_VC2 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC2_Msk = 0x4
	// Bit ST_ERR_F_SEQ_VC2.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC2 = 0x4
	// Position of ST_ERR_F_SEQ_VC3 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC3_Pos = 0x3
	// Bit mask of ST_ERR_F_SEQ_VC3 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC3_Msk = 0x8
	// Bit ST_ERR_F_SEQ_VC3.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC3 = 0x8
	// Position of ST_ERR_F_SEQ_VC4 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC4_Pos = 0x4
	// Bit mask of ST_ERR_F_SEQ_VC4 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC4_Msk = 0x10
	// Bit ST_ERR_F_SEQ_VC4.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC4 = 0x10
	// Position of ST_ERR_F_SEQ_VC5 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC5_Pos = 0x5
	// Bit mask of ST_ERR_F_SEQ_VC5 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC5_Msk = 0x20
	// Bit ST_ERR_F_SEQ_VC5.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC5 = 0x20
	// Position of ST_ERR_F_SEQ_VC6 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC6_Pos = 0x6
	// Bit mask of ST_ERR_F_SEQ_VC6 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC6_Msk = 0x40
	// Bit ST_ERR_F_SEQ_VC6.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC6 = 0x40
	// Position of ST_ERR_F_SEQ_VC7 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC7_Pos = 0x7
	// Bit mask of ST_ERR_F_SEQ_VC7 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC7_Msk = 0x80
	// Bit ST_ERR_F_SEQ_VC7.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC7 = 0x80
	// Position of ST_ERR_F_SEQ_VC8 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC8_Pos = 0x8
	// Bit mask of ST_ERR_F_SEQ_VC8 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC8_Msk = 0x100
	// Bit ST_ERR_F_SEQ_VC8.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC8 = 0x100
	// Position of ST_ERR_F_SEQ_VC9 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC9_Pos = 0x9
	// Bit mask of ST_ERR_F_SEQ_VC9 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC9_Msk = 0x200
	// Bit ST_ERR_F_SEQ_VC9.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC9 = 0x200
	// Position of ST_ERR_F_SEQ_VC10 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC10_Pos = 0xa
	// Bit mask of ST_ERR_F_SEQ_VC10 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC10_Msk = 0x400
	// Bit ST_ERR_F_SEQ_VC10.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC10 = 0x400
	// Position of ST_ERR_F_SEQ_VC11 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC11_Pos = 0xb
	// Bit mask of ST_ERR_F_SEQ_VC11 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC11_Msk = 0x800
	// Bit ST_ERR_F_SEQ_VC11.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC11 = 0x800
	// Position of ST_ERR_F_SEQ_VC12 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC12_Pos = 0xc
	// Bit mask of ST_ERR_F_SEQ_VC12 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC12_Msk = 0x1000
	// Bit ST_ERR_F_SEQ_VC12.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC12 = 0x1000
	// Position of ST_ERR_F_SEQ_VC13 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC13_Pos = 0xd
	// Bit mask of ST_ERR_F_SEQ_VC13 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC13_Msk = 0x2000
	// Bit ST_ERR_F_SEQ_VC13.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC13 = 0x2000
	// Position of ST_ERR_F_SEQ_VC14 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC14_Pos = 0xe
	// Bit mask of ST_ERR_F_SEQ_VC14 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC14_Msk = 0x4000
	// Bit ST_ERR_F_SEQ_VC14.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC14 = 0x4000
	// Position of ST_ERR_F_SEQ_VC15 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC15_Pos = 0xf
	// Bit mask of ST_ERR_F_SEQ_VC15 field.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC15_Msk = 0x8000
	// Bit ST_ERR_F_SEQ_VC15.
	CSI_HOST_INT_ST_SEQ_FRAME_FATAL_ST_ERR_F_SEQ_VC15 = 0x8000

	// INT_MSK_SEQ_FRAME_FATAL: NA
	// Position of MASK_ERR_F_SEQ_VC0 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC0_Pos = 0x0
	// Bit mask of MASK_ERR_F_SEQ_VC0 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC0_Msk = 0x1
	// Bit MASK_ERR_F_SEQ_VC0.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC0 = 0x1
	// Position of MASK_ERR_F_SEQ_VC1 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC1_Pos = 0x1
	// Bit mask of MASK_ERR_F_SEQ_VC1 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC1_Msk = 0x2
	// Bit MASK_ERR_F_SEQ_VC1.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC1 = 0x2
	// Position of MASK_ERR_F_SEQ_VC2 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC2_Pos = 0x2
	// Bit mask of MASK_ERR_F_SEQ_VC2 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC2_Msk = 0x4
	// Bit MASK_ERR_F_SEQ_VC2.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC2 = 0x4
	// Position of MASK_ERR_F_SEQ_VC3 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC3_Pos = 0x3
	// Bit mask of MASK_ERR_F_SEQ_VC3 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC3_Msk = 0x8
	// Bit MASK_ERR_F_SEQ_VC3.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC3 = 0x8
	// Position of MASK_ERR_F_SEQ_VC4 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC4_Pos = 0x4
	// Bit mask of MASK_ERR_F_SEQ_VC4 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC4_Msk = 0x10
	// Bit MASK_ERR_F_SEQ_VC4.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC4 = 0x10
	// Position of MASK_ERR_F_SEQ_VC5 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC5_Pos = 0x5
	// Bit mask of MASK_ERR_F_SEQ_VC5 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC5_Msk = 0x20
	// Bit MASK_ERR_F_SEQ_VC5.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC5 = 0x20
	// Position of MASK_ERR_F_SEQ_VC6 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC6_Pos = 0x6
	// Bit mask of MASK_ERR_F_SEQ_VC6 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC6_Msk = 0x40
	// Bit MASK_ERR_F_SEQ_VC6.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC6 = 0x40
	// Position of MASK_ERR_F_SEQ_VC7 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC7_Pos = 0x7
	// Bit mask of MASK_ERR_F_SEQ_VC7 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC7_Msk = 0x80
	// Bit MASK_ERR_F_SEQ_VC7.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC7 = 0x80
	// Position of MASK_ERR_F_SEQ_VC8 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC8_Pos = 0x8
	// Bit mask of MASK_ERR_F_SEQ_VC8 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC8_Msk = 0x100
	// Bit MASK_ERR_F_SEQ_VC8.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC8 = 0x100
	// Position of MASK_ERR_F_SEQ_VC9 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC9_Pos = 0x9
	// Bit mask of MASK_ERR_F_SEQ_VC9 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC9_Msk = 0x200
	// Bit MASK_ERR_F_SEQ_VC9.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC9 = 0x200
	// Position of MASK_ERR_F_SEQ_VC10 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC10_Pos = 0xa
	// Bit mask of MASK_ERR_F_SEQ_VC10 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC10_Msk = 0x400
	// Bit MASK_ERR_F_SEQ_VC10.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC10 = 0x400
	// Position of MASK_ERR_F_SEQ_VC11 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC11_Pos = 0xb
	// Bit mask of MASK_ERR_F_SEQ_VC11 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC11_Msk = 0x800
	// Bit MASK_ERR_F_SEQ_VC11.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC11 = 0x800
	// Position of MASK_ERR_F_SEQ_VC12 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC12_Pos = 0xc
	// Bit mask of MASK_ERR_F_SEQ_VC12 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC12_Msk = 0x1000
	// Bit MASK_ERR_F_SEQ_VC12.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC12 = 0x1000
	// Position of MASK_ERR_F_SEQ_VC13 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC13_Pos = 0xd
	// Bit mask of MASK_ERR_F_SEQ_VC13 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC13_Msk = 0x2000
	// Bit MASK_ERR_F_SEQ_VC13.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC13 = 0x2000
	// Position of MASK_ERR_F_SEQ_VC14 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC14_Pos = 0xe
	// Bit mask of MASK_ERR_F_SEQ_VC14 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC14_Msk = 0x4000
	// Bit MASK_ERR_F_SEQ_VC14.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC14 = 0x4000
	// Position of MASK_ERR_F_SEQ_VC15 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC15_Pos = 0xf
	// Bit mask of MASK_ERR_F_SEQ_VC15 field.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC15_Msk = 0x8000
	// Bit MASK_ERR_F_SEQ_VC15.
	CSI_HOST_INT_MSK_SEQ_FRAME_FATAL_MASK_ERR_F_SEQ_VC15 = 0x8000

	// INT_FORCE_SEQ_FRAME_FATAL: NA
	// Position of FORCE_ERR_F_SEQ_VC0 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC0_Pos = 0x0
	// Bit mask of FORCE_ERR_F_SEQ_VC0 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC0_Msk = 0x1
	// Bit FORCE_ERR_F_SEQ_VC0.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC0 = 0x1
	// Position of FORCE_ERR_F_SEQ_VC1 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC1_Pos = 0x1
	// Bit mask of FORCE_ERR_F_SEQ_VC1 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC1_Msk = 0x2
	// Bit FORCE_ERR_F_SEQ_VC1.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC1 = 0x2
	// Position of FORCE_ERR_F_SEQ_VC2 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC2_Pos = 0x2
	// Bit mask of FORCE_ERR_F_SEQ_VC2 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC2_Msk = 0x4
	// Bit FORCE_ERR_F_SEQ_VC2.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC2 = 0x4
	// Position of FORCE_ERR_F_SEQ_VC3 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC3_Pos = 0x3
	// Bit mask of FORCE_ERR_F_SEQ_VC3 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC3_Msk = 0x8
	// Bit FORCE_ERR_F_SEQ_VC3.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC3 = 0x8
	// Position of FORCE_ERR_F_SEQ_VC4 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC4_Pos = 0x4
	// Bit mask of FORCE_ERR_F_SEQ_VC4 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC4_Msk = 0x10
	// Bit FORCE_ERR_F_SEQ_VC4.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC4 = 0x10
	// Position of FORCE_ERR_F_SEQ_VC5 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC5_Pos = 0x5
	// Bit mask of FORCE_ERR_F_SEQ_VC5 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC5_Msk = 0x20
	// Bit FORCE_ERR_F_SEQ_VC5.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC5 = 0x20
	// Position of FORCE_ERR_F_SEQ_VC6 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC6_Pos = 0x6
	// Bit mask of FORCE_ERR_F_SEQ_VC6 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC6_Msk = 0x40
	// Bit FORCE_ERR_F_SEQ_VC6.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC6 = 0x40
	// Position of FORCE_ERR_F_SEQ_VC7 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC7_Pos = 0x7
	// Bit mask of FORCE_ERR_F_SEQ_VC7 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC7_Msk = 0x80
	// Bit FORCE_ERR_F_SEQ_VC7.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC7 = 0x80
	// Position of FORCE_ERR_F_SEQ_VC8 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC8_Pos = 0x8
	// Bit mask of FORCE_ERR_F_SEQ_VC8 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC8_Msk = 0x100
	// Bit FORCE_ERR_F_SEQ_VC8.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC8 = 0x100
	// Position of FORCE_ERR_F_SEQ_VC9 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC9_Pos = 0x9
	// Bit mask of FORCE_ERR_F_SEQ_VC9 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC9_Msk = 0x200
	// Bit FORCE_ERR_F_SEQ_VC9.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC9 = 0x200
	// Position of FORCE_ERR_F_SEQ_VC10 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC10_Pos = 0xa
	// Bit mask of FORCE_ERR_F_SEQ_VC10 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC10_Msk = 0x400
	// Bit FORCE_ERR_F_SEQ_VC10.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC10 = 0x400
	// Position of FORCE_ERR_F_SEQ_VC11 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC11_Pos = 0xb
	// Bit mask of FORCE_ERR_F_SEQ_VC11 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC11_Msk = 0x800
	// Bit FORCE_ERR_F_SEQ_VC11.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC11 = 0x800
	// Position of FORCE_ERR_F_SEQ_VC12 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC12_Pos = 0xc
	// Bit mask of FORCE_ERR_F_SEQ_VC12 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC12_Msk = 0x1000
	// Bit FORCE_ERR_F_SEQ_VC12.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC12 = 0x1000
	// Position of FORCE_ERR_F_SEQ_VC13 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC13_Pos = 0xd
	// Bit mask of FORCE_ERR_F_SEQ_VC13 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC13_Msk = 0x2000
	// Bit FORCE_ERR_F_SEQ_VC13.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC13 = 0x2000
	// Position of FORCE_ERR_F_SEQ_VC14 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC14_Pos = 0xe
	// Bit mask of FORCE_ERR_F_SEQ_VC14 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC14_Msk = 0x4000
	// Bit FORCE_ERR_F_SEQ_VC14.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC14 = 0x4000
	// Position of FORCE_ERR_F_SEQ_VC15 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC15_Pos = 0xf
	// Bit mask of FORCE_ERR_F_SEQ_VC15 field.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC15_Msk = 0x8000
	// Bit FORCE_ERR_F_SEQ_VC15.
	CSI_HOST_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_VC15 = 0x8000

	// INT_ST_CRC_FRAME_FATAL: NA
	// Position of ST_ERR_FRAME_DATA_VC0 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC0_Pos = 0x0
	// Bit mask of ST_ERR_FRAME_DATA_VC0 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC0_Msk = 0x1
	// Bit ST_ERR_FRAME_DATA_VC0.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC0 = 0x1
	// Position of ST_ERR_FRAME_DATA_VC1 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC1_Pos = 0x1
	// Bit mask of ST_ERR_FRAME_DATA_VC1 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC1_Msk = 0x2
	// Bit ST_ERR_FRAME_DATA_VC1.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC1 = 0x2
	// Position of ST_ERR_FRAME_DATA_VC2 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC2_Pos = 0x2
	// Bit mask of ST_ERR_FRAME_DATA_VC2 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC2_Msk = 0x4
	// Bit ST_ERR_FRAME_DATA_VC2.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC2 = 0x4
	// Position of ST_ERR_FRAME_DATA_VC3 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC3_Pos = 0x3
	// Bit mask of ST_ERR_FRAME_DATA_VC3 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC3_Msk = 0x8
	// Bit ST_ERR_FRAME_DATA_VC3.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC3 = 0x8
	// Position of ST_ERR_FRAME_DATA_VC4 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC4_Pos = 0x4
	// Bit mask of ST_ERR_FRAME_DATA_VC4 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC4_Msk = 0x10
	// Bit ST_ERR_FRAME_DATA_VC4.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC4 = 0x10
	// Position of ST_ERR_FRAME_DATA_VC5 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC5_Pos = 0x5
	// Bit mask of ST_ERR_FRAME_DATA_VC5 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC5_Msk = 0x20
	// Bit ST_ERR_FRAME_DATA_VC5.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC5 = 0x20
	// Position of ST_ERR_FRAME_DATA_VC6 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC6_Pos = 0x6
	// Bit mask of ST_ERR_FRAME_DATA_VC6 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC6_Msk = 0x40
	// Bit ST_ERR_FRAME_DATA_VC6.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC6 = 0x40
	// Position of ST_ERR_FRAME_DATA_VC7 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC7_Pos = 0x7
	// Bit mask of ST_ERR_FRAME_DATA_VC7 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC7_Msk = 0x80
	// Bit ST_ERR_FRAME_DATA_VC7.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC7 = 0x80
	// Position of ST_ERR_FRAME_DATA_VC8 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC8_Pos = 0x8
	// Bit mask of ST_ERR_FRAME_DATA_VC8 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC8_Msk = 0x100
	// Bit ST_ERR_FRAME_DATA_VC8.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC8 = 0x100
	// Position of ST_ERR_FRAME_DATA_VC9 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC9_Pos = 0x9
	// Bit mask of ST_ERR_FRAME_DATA_VC9 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC9_Msk = 0x200
	// Bit ST_ERR_FRAME_DATA_VC9.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC9 = 0x200
	// Position of ST_ERR_FRAME_DATA_VC10 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC10_Pos = 0xa
	// Bit mask of ST_ERR_FRAME_DATA_VC10 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC10_Msk = 0x400
	// Bit ST_ERR_FRAME_DATA_VC10.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC10 = 0x400
	// Position of ST_ERR_FRAME_DATA_VC11 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC11_Pos = 0xb
	// Bit mask of ST_ERR_FRAME_DATA_VC11 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC11_Msk = 0x800
	// Bit ST_ERR_FRAME_DATA_VC11.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC11 = 0x800
	// Position of ST_ERR_FRAME_DATA_VC12 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC12_Pos = 0xc
	// Bit mask of ST_ERR_FRAME_DATA_VC12 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC12_Msk = 0x1000
	// Bit ST_ERR_FRAME_DATA_VC12.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC12 = 0x1000
	// Position of ST_ERR_FRAME_DATA_VC13 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC13_Pos = 0xd
	// Bit mask of ST_ERR_FRAME_DATA_VC13 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC13_Msk = 0x2000
	// Bit ST_ERR_FRAME_DATA_VC13.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC13 = 0x2000
	// Position of ST_ERR_FRAME_DATA_VC14 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC14_Pos = 0xe
	// Bit mask of ST_ERR_FRAME_DATA_VC14 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC14_Msk = 0x4000
	// Bit ST_ERR_FRAME_DATA_VC14.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC14 = 0x4000
	// Position of ST_ERR_FRAME_DATA_VC15 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC15_Pos = 0xf
	// Bit mask of ST_ERR_FRAME_DATA_VC15 field.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC15_Msk = 0x8000
	// Bit ST_ERR_FRAME_DATA_VC15.
	CSI_HOST_INT_ST_CRC_FRAME_FATAL_ST_ERR_FRAME_DATA_VC15 = 0x8000

	// INT_MSK_CRC_FRAME_FATAL: NA
	// Position of MASK_ERR_FRAME_DATA_VC0 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC0_Pos = 0x0
	// Bit mask of MASK_ERR_FRAME_DATA_VC0 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC0_Msk = 0x1
	// Bit MASK_ERR_FRAME_DATA_VC0.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC0 = 0x1
	// Position of MASK_ERR_FRAME_DATA_VC1 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC1_Pos = 0x1
	// Bit mask of MASK_ERR_FRAME_DATA_VC1 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC1_Msk = 0x2
	// Bit MASK_ERR_FRAME_DATA_VC1.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC1 = 0x2
	// Position of MASK_ERR_FRAME_DATA_VC2 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC2_Pos = 0x2
	// Bit mask of MASK_ERR_FRAME_DATA_VC2 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC2_Msk = 0x4
	// Bit MASK_ERR_FRAME_DATA_VC2.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC2 = 0x4
	// Position of MASK_ERR_FRAME_DATA_VC3 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC3_Pos = 0x3
	// Bit mask of MASK_ERR_FRAME_DATA_VC3 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC3_Msk = 0x8
	// Bit MASK_ERR_FRAME_DATA_VC3.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC3 = 0x8
	// Position of MASK_ERR_FRAME_DATA_VC4 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC4_Pos = 0x4
	// Bit mask of MASK_ERR_FRAME_DATA_VC4 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC4_Msk = 0x10
	// Bit MASK_ERR_FRAME_DATA_VC4.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC4 = 0x10
	// Position of MASK_ERR_FRAME_DATA_VC5 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC5_Pos = 0x5
	// Bit mask of MASK_ERR_FRAME_DATA_VC5 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC5_Msk = 0x20
	// Bit MASK_ERR_FRAME_DATA_VC5.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC5 = 0x20
	// Position of MASK_ERR_FRAME_DATA_VC6 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC6_Pos = 0x6
	// Bit mask of MASK_ERR_FRAME_DATA_VC6 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC6_Msk = 0x40
	// Bit MASK_ERR_FRAME_DATA_VC6.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC6 = 0x40
	// Position of MASK_ERR_FRAME_DATA_VC7 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC7_Pos = 0x7
	// Bit mask of MASK_ERR_FRAME_DATA_VC7 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC7_Msk = 0x80
	// Bit MASK_ERR_FRAME_DATA_VC7.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC7 = 0x80
	// Position of MASK_ERR_FRAME_DATA_VC8 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC8_Pos = 0x8
	// Bit mask of MASK_ERR_FRAME_DATA_VC8 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC8_Msk = 0x100
	// Bit MASK_ERR_FRAME_DATA_VC8.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC8 = 0x100
	// Position of MASK_ERR_FRAME_DATA_VC9 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC9_Pos = 0x9
	// Bit mask of MASK_ERR_FRAME_DATA_VC9 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC9_Msk = 0x200
	// Bit MASK_ERR_FRAME_DATA_VC9.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC9 = 0x200
	// Position of MASK_ERR_FRAME_DATA_VC10 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC10_Pos = 0xa
	// Bit mask of MASK_ERR_FRAME_DATA_VC10 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC10_Msk = 0x400
	// Bit MASK_ERR_FRAME_DATA_VC10.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC10 = 0x400
	// Position of MASK_ERR_FRAME_DATA_VC11 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC11_Pos = 0xb
	// Bit mask of MASK_ERR_FRAME_DATA_VC11 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC11_Msk = 0x800
	// Bit MASK_ERR_FRAME_DATA_VC11.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC11 = 0x800
	// Position of MASK_ERR_FRAME_DATA_VC12 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC12_Pos = 0xc
	// Bit mask of MASK_ERR_FRAME_DATA_VC12 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC12_Msk = 0x1000
	// Bit MASK_ERR_FRAME_DATA_VC12.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC12 = 0x1000
	// Position of MASK_ERR_FRAME_DATA_VC13 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC13_Pos = 0xd
	// Bit mask of MASK_ERR_FRAME_DATA_VC13 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC13_Msk = 0x2000
	// Bit MASK_ERR_FRAME_DATA_VC13.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC13 = 0x2000
	// Position of MASK_ERR_FRAME_DATA_VC14 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC14_Pos = 0xe
	// Bit mask of MASK_ERR_FRAME_DATA_VC14 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC14_Msk = 0x4000
	// Bit MASK_ERR_FRAME_DATA_VC14.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC14 = 0x4000
	// Position of MASK_ERR_FRAME_DATA_VC15 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC15_Pos = 0xf
	// Bit mask of MASK_ERR_FRAME_DATA_VC15 field.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC15_Msk = 0x8000
	// Bit MASK_ERR_FRAME_DATA_VC15.
	CSI_HOST_INT_MSK_CRC_FRAME_FATAL_MASK_ERR_FRAME_DATA_VC15 = 0x8000

	// INT_FORCE_CRC_FRAME_FATAL: NA
	// Position of FORCE_ERR_FRAME_DATA_VC0 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC0_Pos = 0x0
	// Bit mask of FORCE_ERR_FRAME_DATA_VC0 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC0_Msk = 0x1
	// Bit FORCE_ERR_FRAME_DATA_VC0.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC0 = 0x1
	// Position of FORCE_ERR_FRAME_DATA_VC1 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC1_Pos = 0x1
	// Bit mask of FORCE_ERR_FRAME_DATA_VC1 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC1_Msk = 0x2
	// Bit FORCE_ERR_FRAME_DATA_VC1.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC1 = 0x2
	// Position of FORCE_ERR_FRAME_DATA_VC2 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC2_Pos = 0x2
	// Bit mask of FORCE_ERR_FRAME_DATA_VC2 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC2_Msk = 0x4
	// Bit FORCE_ERR_FRAME_DATA_VC2.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC2 = 0x4
	// Position of FORCE_ERR_FRAME_DATA_VC3 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC3_Pos = 0x3
	// Bit mask of FORCE_ERR_FRAME_DATA_VC3 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC3_Msk = 0x8
	// Bit FORCE_ERR_FRAME_DATA_VC3.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC3 = 0x8
	// Position of FORCE_ERR_FRAME_DATA_VC4 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC4_Pos = 0x4
	// Bit mask of FORCE_ERR_FRAME_DATA_VC4 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC4_Msk = 0x10
	// Bit FORCE_ERR_FRAME_DATA_VC4.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC4 = 0x10
	// Position of FORCE_ERR_FRAME_DATA_VC5 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC5_Pos = 0x5
	// Bit mask of FORCE_ERR_FRAME_DATA_VC5 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC5_Msk = 0x20
	// Bit FORCE_ERR_FRAME_DATA_VC5.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC5 = 0x20
	// Position of FORCE_ERR_FRAME_DATA_VC6 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC6_Pos = 0x6
	// Bit mask of FORCE_ERR_FRAME_DATA_VC6 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC6_Msk = 0x40
	// Bit FORCE_ERR_FRAME_DATA_VC6.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC6 = 0x40
	// Position of FORCE_ERR_FRAME_DATA_VC7 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC7_Pos = 0x7
	// Bit mask of FORCE_ERR_FRAME_DATA_VC7 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC7_Msk = 0x80
	// Bit FORCE_ERR_FRAME_DATA_VC7.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC7 = 0x80
	// Position of FORCE_ERR_FRAME_DATA_VC8 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC8_Pos = 0x8
	// Bit mask of FORCE_ERR_FRAME_DATA_VC8 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC8_Msk = 0x100
	// Bit FORCE_ERR_FRAME_DATA_VC8.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC8 = 0x100
	// Position of FORCE_ERR_FRAME_DATA_VC9 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC9_Pos = 0x9
	// Bit mask of FORCE_ERR_FRAME_DATA_VC9 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC9_Msk = 0x200
	// Bit FORCE_ERR_FRAME_DATA_VC9.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC9 = 0x200
	// Position of FORCE_ERR_FRAME_DATA_VC10 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC10_Pos = 0xa
	// Bit mask of FORCE_ERR_FRAME_DATA_VC10 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC10_Msk = 0x400
	// Bit FORCE_ERR_FRAME_DATA_VC10.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC10 = 0x400
	// Position of FORCE_ERR_FRAME_DATA_VC11 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC11_Pos = 0xb
	// Bit mask of FORCE_ERR_FRAME_DATA_VC11 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC11_Msk = 0x800
	// Bit FORCE_ERR_FRAME_DATA_VC11.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC11 = 0x800
	// Position of FORCE_ERR_FRAME_DATA_VC12 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC12_Pos = 0xc
	// Bit mask of FORCE_ERR_FRAME_DATA_VC12 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC12_Msk = 0x1000
	// Bit FORCE_ERR_FRAME_DATA_VC12.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC12 = 0x1000
	// Position of FORCE_ERR_FRAME_DATA_VC13 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC13_Pos = 0xd
	// Bit mask of FORCE_ERR_FRAME_DATA_VC13 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC13_Msk = 0x2000
	// Bit FORCE_ERR_FRAME_DATA_VC13.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC13 = 0x2000
	// Position of FORCE_ERR_FRAME_DATA_VC14 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC14_Pos = 0xe
	// Bit mask of FORCE_ERR_FRAME_DATA_VC14 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC14_Msk = 0x4000
	// Bit FORCE_ERR_FRAME_DATA_VC14.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC14 = 0x4000
	// Position of FORCE_ERR_FRAME_DATA_VC15 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC15_Pos = 0xf
	// Bit mask of FORCE_ERR_FRAME_DATA_VC15 field.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC15_Msk = 0x8000
	// Bit FORCE_ERR_FRAME_DATA_VC15.
	CSI_HOST_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_FRAME_DATA_VC15 = 0x8000

	// INT_ST_PLD_CRC_FATAL: NA
	// Position of ST_ERR_CRC_VC0 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC0_Pos = 0x0
	// Bit mask of ST_ERR_CRC_VC0 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC0_Msk = 0x1
	// Bit ST_ERR_CRC_VC0.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC0 = 0x1
	// Position of ST_ERR_CRC_VC1 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC1_Pos = 0x1
	// Bit mask of ST_ERR_CRC_VC1 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC1_Msk = 0x2
	// Bit ST_ERR_CRC_VC1.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC1 = 0x2
	// Position of ST_ERR_CRC_VC2 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC2_Pos = 0x2
	// Bit mask of ST_ERR_CRC_VC2 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC2_Msk = 0x4
	// Bit ST_ERR_CRC_VC2.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC2 = 0x4
	// Position of ST_ERR_CRC_VC3 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC3_Pos = 0x3
	// Bit mask of ST_ERR_CRC_VC3 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC3_Msk = 0x8
	// Bit ST_ERR_CRC_VC3.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC3 = 0x8
	// Position of ST_ERR_CRC_VC4 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC4_Pos = 0x4
	// Bit mask of ST_ERR_CRC_VC4 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC4_Msk = 0x10
	// Bit ST_ERR_CRC_VC4.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC4 = 0x10
	// Position of ST_ERR_CRC_VC5 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC5_Pos = 0x5
	// Bit mask of ST_ERR_CRC_VC5 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC5_Msk = 0x20
	// Bit ST_ERR_CRC_VC5.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC5 = 0x20
	// Position of ST_ERR_CRC_VC6 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC6_Pos = 0x6
	// Bit mask of ST_ERR_CRC_VC6 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC6_Msk = 0x40
	// Bit ST_ERR_CRC_VC6.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC6 = 0x40
	// Position of ST_ERR_CRC_VC7 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC7_Pos = 0x7
	// Bit mask of ST_ERR_CRC_VC7 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC7_Msk = 0x80
	// Bit ST_ERR_CRC_VC7.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC7 = 0x80
	// Position of ST_ERR_CRC_VC8 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC8_Pos = 0x8
	// Bit mask of ST_ERR_CRC_VC8 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC8_Msk = 0x100
	// Bit ST_ERR_CRC_VC8.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC8 = 0x100
	// Position of ST_ERR_CRC_VC9 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC9_Pos = 0x9
	// Bit mask of ST_ERR_CRC_VC9 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC9_Msk = 0x200
	// Bit ST_ERR_CRC_VC9.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC9 = 0x200
	// Position of ST_ERR_CRC_VC10 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC10_Pos = 0xa
	// Bit mask of ST_ERR_CRC_VC10 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC10_Msk = 0x400
	// Bit ST_ERR_CRC_VC10.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC10 = 0x400
	// Position of ST_ERR_CRC_VC11 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC11_Pos = 0xb
	// Bit mask of ST_ERR_CRC_VC11 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC11_Msk = 0x800
	// Bit ST_ERR_CRC_VC11.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC11 = 0x800
	// Position of ST_ERR_CRC_VC12 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC12_Pos = 0xc
	// Bit mask of ST_ERR_CRC_VC12 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC12_Msk = 0x1000
	// Bit ST_ERR_CRC_VC12.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC12 = 0x1000
	// Position of ST_ERR_CRC_VC13 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC13_Pos = 0xd
	// Bit mask of ST_ERR_CRC_VC13 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC13_Msk = 0x2000
	// Bit ST_ERR_CRC_VC13.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC13 = 0x2000
	// Position of ST_ERR_CRC_VC14 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC14_Pos = 0xe
	// Bit mask of ST_ERR_CRC_VC14 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC14_Msk = 0x4000
	// Bit ST_ERR_CRC_VC14.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC14 = 0x4000
	// Position of ST_ERR_CRC_VC15 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC15_Pos = 0xf
	// Bit mask of ST_ERR_CRC_VC15 field.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC15_Msk = 0x8000
	// Bit ST_ERR_CRC_VC15.
	CSI_HOST_INT_ST_PLD_CRC_FATAL_ST_ERR_CRC_VC15 = 0x8000

	// INT_MSK_PLD_CRC_FATAL: NA
	// Position of MASK_ERR_CRC_VC0 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC0_Pos = 0x0
	// Bit mask of MASK_ERR_CRC_VC0 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC0_Msk = 0x1
	// Bit MASK_ERR_CRC_VC0.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC0 = 0x1
	// Position of MASK_ERR_CRC_VC1 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC1_Pos = 0x1
	// Bit mask of MASK_ERR_CRC_VC1 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC1_Msk = 0x2
	// Bit MASK_ERR_CRC_VC1.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC1 = 0x2
	// Position of MASK_ERR_CRC_VC2 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC2_Pos = 0x2
	// Bit mask of MASK_ERR_CRC_VC2 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC2_Msk = 0x4
	// Bit MASK_ERR_CRC_VC2.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC2 = 0x4
	// Position of MASK_ERR_CRC_VC3 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC3_Pos = 0x3
	// Bit mask of MASK_ERR_CRC_VC3 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC3_Msk = 0x8
	// Bit MASK_ERR_CRC_VC3.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC3 = 0x8
	// Position of MASK_ERR_CRC_VC4 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC4_Pos = 0x4
	// Bit mask of MASK_ERR_CRC_VC4 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC4_Msk = 0x10
	// Bit MASK_ERR_CRC_VC4.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC4 = 0x10
	// Position of MASK_ERR_CRC_VC5 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC5_Pos = 0x5
	// Bit mask of MASK_ERR_CRC_VC5 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC5_Msk = 0x20
	// Bit MASK_ERR_CRC_VC5.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC5 = 0x20
	// Position of MASK_ERR_CRC_VC6 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC6_Pos = 0x6
	// Bit mask of MASK_ERR_CRC_VC6 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC6_Msk = 0x40
	// Bit MASK_ERR_CRC_VC6.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC6 = 0x40
	// Position of MASK_ERR_CRC_VC7 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC7_Pos = 0x7
	// Bit mask of MASK_ERR_CRC_VC7 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC7_Msk = 0x80
	// Bit MASK_ERR_CRC_VC7.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC7 = 0x80
	// Position of MASK_ERR_CRC_VC8 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC8_Pos = 0x8
	// Bit mask of MASK_ERR_CRC_VC8 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC8_Msk = 0x100
	// Bit MASK_ERR_CRC_VC8.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC8 = 0x100
	// Position of MASK_ERR_CRC_VC9 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC9_Pos = 0x9
	// Bit mask of MASK_ERR_CRC_VC9 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC9_Msk = 0x200
	// Bit MASK_ERR_CRC_VC9.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC9 = 0x200
	// Position of MASK_ERR_CRC_VC10 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC10_Pos = 0xa
	// Bit mask of MASK_ERR_CRC_VC10 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC10_Msk = 0x400
	// Bit MASK_ERR_CRC_VC10.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC10 = 0x400
	// Position of MASK_ERR_CRC_VC11 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC11_Pos = 0xb
	// Bit mask of MASK_ERR_CRC_VC11 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC11_Msk = 0x800
	// Bit MASK_ERR_CRC_VC11.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC11 = 0x800
	// Position of MASK_ERR_CRC_VC12 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC12_Pos = 0xc
	// Bit mask of MASK_ERR_CRC_VC12 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC12_Msk = 0x1000
	// Bit MASK_ERR_CRC_VC12.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC12 = 0x1000
	// Position of MASK_ERR_CRC_VC13 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC13_Pos = 0xd
	// Bit mask of MASK_ERR_CRC_VC13 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC13_Msk = 0x2000
	// Bit MASK_ERR_CRC_VC13.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC13 = 0x2000
	// Position of MASK_ERR_CRC_VC14 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC14_Pos = 0xe
	// Bit mask of MASK_ERR_CRC_VC14 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC14_Msk = 0x4000
	// Bit MASK_ERR_CRC_VC14.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC14 = 0x4000
	// Position of MASK_ERR_CRC_VC15 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC15_Pos = 0xf
	// Bit mask of MASK_ERR_CRC_VC15 field.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC15_Msk = 0x8000
	// Bit MASK_ERR_CRC_VC15.
	CSI_HOST_INT_MSK_PLD_CRC_FATAL_MASK_ERR_CRC_VC15 = 0x8000

	// INT_FORCE_PLD_CRC_FATAL: NA
	// Position of FORCE_ERR_CRC_VC0 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC0_Pos = 0x0
	// Bit mask of FORCE_ERR_CRC_VC0 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC0_Msk = 0x1
	// Bit FORCE_ERR_CRC_VC0.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC0 = 0x1
	// Position of FORCE_ERR_CRC_VC1 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC1_Pos = 0x1
	// Bit mask of FORCE_ERR_CRC_VC1 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC1_Msk = 0x2
	// Bit FORCE_ERR_CRC_VC1.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC1 = 0x2
	// Position of FORCE_ERR_CRC_VC2 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC2_Pos = 0x2
	// Bit mask of FORCE_ERR_CRC_VC2 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC2_Msk = 0x4
	// Bit FORCE_ERR_CRC_VC2.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC2 = 0x4
	// Position of FORCE_ERR_CRC_VC3 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC3_Pos = 0x3
	// Bit mask of FORCE_ERR_CRC_VC3 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC3_Msk = 0x8
	// Bit FORCE_ERR_CRC_VC3.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC3 = 0x8
	// Position of FORCE_ERR_CRC_VC4 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC4_Pos = 0x4
	// Bit mask of FORCE_ERR_CRC_VC4 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC4_Msk = 0x10
	// Bit FORCE_ERR_CRC_VC4.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC4 = 0x10
	// Position of FORCE_ERR_CRC_VC5 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC5_Pos = 0x5
	// Bit mask of FORCE_ERR_CRC_VC5 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC5_Msk = 0x20
	// Bit FORCE_ERR_CRC_VC5.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC5 = 0x20
	// Position of FORCE_ERR_CRC_VC6 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC6_Pos = 0x6
	// Bit mask of FORCE_ERR_CRC_VC6 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC6_Msk = 0x40
	// Bit FORCE_ERR_CRC_VC6.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC6 = 0x40
	// Position of FORCE_ERR_CRC_VC7 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC7_Pos = 0x7
	// Bit mask of FORCE_ERR_CRC_VC7 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC7_Msk = 0x80
	// Bit FORCE_ERR_CRC_VC7.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC7 = 0x80
	// Position of FORCE_ERR_CRC_VC8 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC8_Pos = 0x8
	// Bit mask of FORCE_ERR_CRC_VC8 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC8_Msk = 0x100
	// Bit FORCE_ERR_CRC_VC8.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC8 = 0x100
	// Position of FORCE_ERR_CRC_VC9 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC9_Pos = 0x9
	// Bit mask of FORCE_ERR_CRC_VC9 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC9_Msk = 0x200
	// Bit FORCE_ERR_CRC_VC9.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC9 = 0x200
	// Position of FORCE_ERR_CRC_VC10 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC10_Pos = 0xa
	// Bit mask of FORCE_ERR_CRC_VC10 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC10_Msk = 0x400
	// Bit FORCE_ERR_CRC_VC10.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC10 = 0x400
	// Position of FORCE_ERR_CRC_VC11 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC11_Pos = 0xb
	// Bit mask of FORCE_ERR_CRC_VC11 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC11_Msk = 0x800
	// Bit FORCE_ERR_CRC_VC11.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC11 = 0x800
	// Position of FORCE_ERR_CRC_VC12 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC12_Pos = 0xc
	// Bit mask of FORCE_ERR_CRC_VC12 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC12_Msk = 0x1000
	// Bit FORCE_ERR_CRC_VC12.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC12 = 0x1000
	// Position of FORCE_ERR_CRC_VC13 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC13_Pos = 0xd
	// Bit mask of FORCE_ERR_CRC_VC13 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC13_Msk = 0x2000
	// Bit FORCE_ERR_CRC_VC13.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC13 = 0x2000
	// Position of FORCE_ERR_CRC_VC14 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC14_Pos = 0xe
	// Bit mask of FORCE_ERR_CRC_VC14 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC14_Msk = 0x4000
	// Bit FORCE_ERR_CRC_VC14.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC14 = 0x4000
	// Position of FORCE_ERR_CRC_VC15 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC15_Pos = 0xf
	// Bit mask of FORCE_ERR_CRC_VC15 field.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC15_Msk = 0x8000
	// Bit FORCE_ERR_CRC_VC15.
	CSI_HOST_INT_FORCE_PLD_CRC_FATAL_FORCE_ERR_CRC_VC15 = 0x8000

	// INT_ST_DATA_ID: NA
	// Position of ST_ERR_ID_VC0 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC0_Pos = 0x0
	// Bit mask of ST_ERR_ID_VC0 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC0_Msk = 0x1
	// Bit ST_ERR_ID_VC0.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC0 = 0x1
	// Position of ST_ERR_ID_VC1 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC1_Pos = 0x1
	// Bit mask of ST_ERR_ID_VC1 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC1_Msk = 0x2
	// Bit ST_ERR_ID_VC1.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC1 = 0x2
	// Position of ST_ERR_ID_VC2 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC2_Pos = 0x2
	// Bit mask of ST_ERR_ID_VC2 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC2_Msk = 0x4
	// Bit ST_ERR_ID_VC2.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC2 = 0x4
	// Position of ST_ERR_ID_VC3 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC3_Pos = 0x3
	// Bit mask of ST_ERR_ID_VC3 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC3_Msk = 0x8
	// Bit ST_ERR_ID_VC3.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC3 = 0x8
	// Position of ST_ERR_ID_VC4 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC4_Pos = 0x4
	// Bit mask of ST_ERR_ID_VC4 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC4_Msk = 0x10
	// Bit ST_ERR_ID_VC4.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC4 = 0x10
	// Position of ST_ERR_ID_VC5 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC5_Pos = 0x5
	// Bit mask of ST_ERR_ID_VC5 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC5_Msk = 0x20
	// Bit ST_ERR_ID_VC5.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC5 = 0x20
	// Position of ST_ERR_ID_VC6 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC6_Pos = 0x6
	// Bit mask of ST_ERR_ID_VC6 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC6_Msk = 0x40
	// Bit ST_ERR_ID_VC6.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC6 = 0x40
	// Position of ST_ERR_ID_VC7 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC7_Pos = 0x7
	// Bit mask of ST_ERR_ID_VC7 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC7_Msk = 0x80
	// Bit ST_ERR_ID_VC7.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC7 = 0x80
	// Position of ST_ERR_ID_VC8 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC8_Pos = 0x8
	// Bit mask of ST_ERR_ID_VC8 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC8_Msk = 0x100
	// Bit ST_ERR_ID_VC8.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC8 = 0x100
	// Position of ST_ERR_ID_VC9 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC9_Pos = 0x9
	// Bit mask of ST_ERR_ID_VC9 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC9_Msk = 0x200
	// Bit ST_ERR_ID_VC9.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC9 = 0x200
	// Position of ST_ERR_ID_VC10 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC10_Pos = 0xa
	// Bit mask of ST_ERR_ID_VC10 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC10_Msk = 0x400
	// Bit ST_ERR_ID_VC10.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC10 = 0x400
	// Position of ST_ERR_ID_VC11 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC11_Pos = 0xb
	// Bit mask of ST_ERR_ID_VC11 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC11_Msk = 0x800
	// Bit ST_ERR_ID_VC11.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC11 = 0x800
	// Position of ST_ERR_ID_VC12 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC12_Pos = 0xc
	// Bit mask of ST_ERR_ID_VC12 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC12_Msk = 0x1000
	// Bit ST_ERR_ID_VC12.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC12 = 0x1000
	// Position of ST_ERR_ID_VC13 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC13_Pos = 0xd
	// Bit mask of ST_ERR_ID_VC13 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC13_Msk = 0x2000
	// Bit ST_ERR_ID_VC13.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC13 = 0x2000
	// Position of ST_ERR_ID_VC14 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC14_Pos = 0xe
	// Bit mask of ST_ERR_ID_VC14 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC14_Msk = 0x4000
	// Bit ST_ERR_ID_VC14.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC14 = 0x4000
	// Position of ST_ERR_ID_VC15 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC15_Pos = 0xf
	// Bit mask of ST_ERR_ID_VC15 field.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC15_Msk = 0x8000
	// Bit ST_ERR_ID_VC15.
	CSI_HOST_INT_ST_DATA_ID_ST_ERR_ID_VC15 = 0x8000

	// INT_MSK_DATA_ID: NA
	// Position of MASK_ERR_ID_VC0 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC0_Pos = 0x0
	// Bit mask of MASK_ERR_ID_VC0 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC0_Msk = 0x1
	// Bit MASK_ERR_ID_VC0.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC0 = 0x1
	// Position of MASK_ERR_ID_VC1 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC1_Pos = 0x1
	// Bit mask of MASK_ERR_ID_VC1 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC1_Msk = 0x2
	// Bit MASK_ERR_ID_VC1.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC1 = 0x2
	// Position of MASK_ERR_ID_VC2 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC2_Pos = 0x2
	// Bit mask of MASK_ERR_ID_VC2 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC2_Msk = 0x4
	// Bit MASK_ERR_ID_VC2.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC2 = 0x4
	// Position of MASK_ERR_ID_VC3 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC3_Pos = 0x3
	// Bit mask of MASK_ERR_ID_VC3 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC3_Msk = 0x8
	// Bit MASK_ERR_ID_VC3.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC3 = 0x8
	// Position of MASK_ERR_ID_VC4 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC4_Pos = 0x4
	// Bit mask of MASK_ERR_ID_VC4 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC4_Msk = 0x10
	// Bit MASK_ERR_ID_VC4.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC4 = 0x10
	// Position of MASK_ERR_ID_VC5 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC5_Pos = 0x5
	// Bit mask of MASK_ERR_ID_VC5 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC5_Msk = 0x20
	// Bit MASK_ERR_ID_VC5.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC5 = 0x20
	// Position of MASK_ERR_ID_VC6 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC6_Pos = 0x6
	// Bit mask of MASK_ERR_ID_VC6 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC6_Msk = 0x40
	// Bit MASK_ERR_ID_VC6.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC6 = 0x40
	// Position of MASK_ERR_ID_VC7 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC7_Pos = 0x7
	// Bit mask of MASK_ERR_ID_VC7 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC7_Msk = 0x80
	// Bit MASK_ERR_ID_VC7.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC7 = 0x80
	// Position of MASK_ERR_ID_VC8 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC8_Pos = 0x8
	// Bit mask of MASK_ERR_ID_VC8 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC8_Msk = 0x100
	// Bit MASK_ERR_ID_VC8.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC8 = 0x100
	// Position of MASK_ERR_ID_VC9 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC9_Pos = 0x9
	// Bit mask of MASK_ERR_ID_VC9 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC9_Msk = 0x200
	// Bit MASK_ERR_ID_VC9.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC9 = 0x200
	// Position of MASK_ERR_ID_VC10 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC10_Pos = 0xa
	// Bit mask of MASK_ERR_ID_VC10 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC10_Msk = 0x400
	// Bit MASK_ERR_ID_VC10.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC10 = 0x400
	// Position of MASK_ERR_ID_VC11 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC11_Pos = 0xb
	// Bit mask of MASK_ERR_ID_VC11 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC11_Msk = 0x800
	// Bit MASK_ERR_ID_VC11.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC11 = 0x800
	// Position of MASK_ERR_ID_VC12 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC12_Pos = 0xc
	// Bit mask of MASK_ERR_ID_VC12 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC12_Msk = 0x1000
	// Bit MASK_ERR_ID_VC12.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC12 = 0x1000
	// Position of MASK_ERR_ID_VC13 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC13_Pos = 0xd
	// Bit mask of MASK_ERR_ID_VC13 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC13_Msk = 0x2000
	// Bit MASK_ERR_ID_VC13.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC13 = 0x2000
	// Position of MASK_ERR_ID_VC14 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC14_Pos = 0xe
	// Bit mask of MASK_ERR_ID_VC14 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC14_Msk = 0x4000
	// Bit MASK_ERR_ID_VC14.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC14 = 0x4000
	// Position of MASK_ERR_ID_VC15 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC15_Pos = 0xf
	// Bit mask of MASK_ERR_ID_VC15 field.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC15_Msk = 0x8000
	// Bit MASK_ERR_ID_VC15.
	CSI_HOST_INT_MSK_DATA_ID_MASK_ERR_ID_VC15 = 0x8000

	// INT_FORCE_DATA_ID: NA
	// Position of FORCE_ERR_ID_VC0 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC0_Pos = 0x0
	// Bit mask of FORCE_ERR_ID_VC0 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC0_Msk = 0x1
	// Bit FORCE_ERR_ID_VC0.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC0 = 0x1
	// Position of FORCE_ERR_ID_VC1 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC1_Pos = 0x1
	// Bit mask of FORCE_ERR_ID_VC1 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC1_Msk = 0x2
	// Bit FORCE_ERR_ID_VC1.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC1 = 0x2
	// Position of FORCE_ERR_ID_VC2 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC2_Pos = 0x2
	// Bit mask of FORCE_ERR_ID_VC2 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC2_Msk = 0x4
	// Bit FORCE_ERR_ID_VC2.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC2 = 0x4
	// Position of FORCE_ERR_ID_VC3 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC3_Pos = 0x3
	// Bit mask of FORCE_ERR_ID_VC3 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC3_Msk = 0x8
	// Bit FORCE_ERR_ID_VC3.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC3 = 0x8
	// Position of FORCE_ERR_ID_VC4 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC4_Pos = 0x4
	// Bit mask of FORCE_ERR_ID_VC4 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC4_Msk = 0x10
	// Bit FORCE_ERR_ID_VC4.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC4 = 0x10
	// Position of FORCE_ERR_ID_VC5 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC5_Pos = 0x5
	// Bit mask of FORCE_ERR_ID_VC5 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC5_Msk = 0x20
	// Bit FORCE_ERR_ID_VC5.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC5 = 0x20
	// Position of FORCE_ERR_ID_VC6 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC6_Pos = 0x6
	// Bit mask of FORCE_ERR_ID_VC6 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC6_Msk = 0x40
	// Bit FORCE_ERR_ID_VC6.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC6 = 0x40
	// Position of FORCE_ERR_ID_VC7 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC7_Pos = 0x7
	// Bit mask of FORCE_ERR_ID_VC7 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC7_Msk = 0x80
	// Bit FORCE_ERR_ID_VC7.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC7 = 0x80
	// Position of FORCE_ERR_ID_VC8 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC8_Pos = 0x8
	// Bit mask of FORCE_ERR_ID_VC8 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC8_Msk = 0x100
	// Bit FORCE_ERR_ID_VC8.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC8 = 0x100
	// Position of FORCE_ERR_ID_VC9 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC9_Pos = 0x9
	// Bit mask of FORCE_ERR_ID_VC9 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC9_Msk = 0x200
	// Bit FORCE_ERR_ID_VC9.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC9 = 0x200
	// Position of FORCE_ERR_ID_VC10 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC10_Pos = 0xa
	// Bit mask of FORCE_ERR_ID_VC10 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC10_Msk = 0x400
	// Bit FORCE_ERR_ID_VC10.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC10 = 0x400
	// Position of FORCE_ERR_ID_VC11 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC11_Pos = 0xb
	// Bit mask of FORCE_ERR_ID_VC11 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC11_Msk = 0x800
	// Bit FORCE_ERR_ID_VC11.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC11 = 0x800
	// Position of FORCE_ERR_ID_VC12 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC12_Pos = 0xc
	// Bit mask of FORCE_ERR_ID_VC12 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC12_Msk = 0x1000
	// Bit FORCE_ERR_ID_VC12.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC12 = 0x1000
	// Position of FORCE_ERR_ID_VC13 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC13_Pos = 0xd
	// Bit mask of FORCE_ERR_ID_VC13 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC13_Msk = 0x2000
	// Bit FORCE_ERR_ID_VC13.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC13 = 0x2000
	// Position of FORCE_ERR_ID_VC14 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC14_Pos = 0xe
	// Bit mask of FORCE_ERR_ID_VC14 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC14_Msk = 0x4000
	// Bit FORCE_ERR_ID_VC14.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC14 = 0x4000
	// Position of FORCE_ERR_ID_VC15 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC15_Pos = 0xf
	// Bit mask of FORCE_ERR_ID_VC15 field.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC15_Msk = 0x8000
	// Bit FORCE_ERR_ID_VC15.
	CSI_HOST_INT_FORCE_DATA_ID_FORCE_ERR_ID_VC15 = 0x8000

	// INT_ST_ECC_CORRECTED: NA
	// Position of ST_ERR_ECC_CORRECTED_VC0 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC0_Pos = 0x0
	// Bit mask of ST_ERR_ECC_CORRECTED_VC0 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC0_Msk = 0x1
	// Bit ST_ERR_ECC_CORRECTED_VC0.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC0 = 0x1
	// Position of ST_ERR_ECC_CORRECTED_VC1 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC1_Pos = 0x1
	// Bit mask of ST_ERR_ECC_CORRECTED_VC1 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC1_Msk = 0x2
	// Bit ST_ERR_ECC_CORRECTED_VC1.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC1 = 0x2
	// Position of ST_ERR_ECC_CORRECTED_VC2 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC2_Pos = 0x2
	// Bit mask of ST_ERR_ECC_CORRECTED_VC2 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC2_Msk = 0x4
	// Bit ST_ERR_ECC_CORRECTED_VC2.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC2 = 0x4
	// Position of ST_ERR_ECC_CORRECTED_VC3 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC3_Pos = 0x3
	// Bit mask of ST_ERR_ECC_CORRECTED_VC3 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC3_Msk = 0x8
	// Bit ST_ERR_ECC_CORRECTED_VC3.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC3 = 0x8
	// Position of ST_ERR_ECC_CORRECTED_VC4 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC4_Pos = 0x4
	// Bit mask of ST_ERR_ECC_CORRECTED_VC4 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC4_Msk = 0x10
	// Bit ST_ERR_ECC_CORRECTED_VC4.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC4 = 0x10
	// Position of ST_ERR_ECC_CORRECTED_VC5 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC5_Pos = 0x5
	// Bit mask of ST_ERR_ECC_CORRECTED_VC5 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC5_Msk = 0x20
	// Bit ST_ERR_ECC_CORRECTED_VC5.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC5 = 0x20
	// Position of ST_ERR_ECC_CORRECTED_VC6 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC6_Pos = 0x6
	// Bit mask of ST_ERR_ECC_CORRECTED_VC6 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC6_Msk = 0x40
	// Bit ST_ERR_ECC_CORRECTED_VC6.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC6 = 0x40
	// Position of ST_ERR_ECC_CORRECTED_VC7 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC7_Pos = 0x7
	// Bit mask of ST_ERR_ECC_CORRECTED_VC7 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC7_Msk = 0x80
	// Bit ST_ERR_ECC_CORRECTED_VC7.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC7 = 0x80
	// Position of ST_ERR_ECC_CORRECTED_VC8 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC8_Pos = 0x8
	// Bit mask of ST_ERR_ECC_CORRECTED_VC8 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC8_Msk = 0x100
	// Bit ST_ERR_ECC_CORRECTED_VC8.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC8 = 0x100
	// Position of ST_ERR_ECC_CORRECTED_VC9 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC9_Pos = 0x9
	// Bit mask of ST_ERR_ECC_CORRECTED_VC9 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC9_Msk = 0x200
	// Bit ST_ERR_ECC_CORRECTED_VC9.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC9 = 0x200
	// Position of ST_ERR_ECC_CORRECTED_VC10 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC10_Pos = 0xa
	// Bit mask of ST_ERR_ECC_CORRECTED_VC10 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC10_Msk = 0x400
	// Bit ST_ERR_ECC_CORRECTED_VC10.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC10 = 0x400
	// Position of ST_ERR_ECC_CORRECTED_VC11 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC11_Pos = 0xb
	// Bit mask of ST_ERR_ECC_CORRECTED_VC11 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC11_Msk = 0x800
	// Bit ST_ERR_ECC_CORRECTED_VC11.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC11 = 0x800
	// Position of ST_ERR_ECC_CORRECTED_VC12 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC12_Pos = 0xc
	// Bit mask of ST_ERR_ECC_CORRECTED_VC12 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC12_Msk = 0x1000
	// Bit ST_ERR_ECC_CORRECTED_VC12.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC12 = 0x1000
	// Position of ST_ERR_ECC_CORRECTED_VC13 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC13_Pos = 0xd
	// Bit mask of ST_ERR_ECC_CORRECTED_VC13 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC13_Msk = 0x2000
	// Bit ST_ERR_ECC_CORRECTED_VC13.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC13 = 0x2000
	// Position of ST_ERR_ECC_CORRECTED_VC14 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC14_Pos = 0xe
	// Bit mask of ST_ERR_ECC_CORRECTED_VC14 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC14_Msk = 0x4000
	// Bit ST_ERR_ECC_CORRECTED_VC14.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC14 = 0x4000
	// Position of ST_ERR_ECC_CORRECTED_VC15 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC15_Pos = 0xf
	// Bit mask of ST_ERR_ECC_CORRECTED_VC15 field.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC15_Msk = 0x8000
	// Bit ST_ERR_ECC_CORRECTED_VC15.
	CSI_HOST_INT_ST_ECC_CORRECTED_ST_ERR_ECC_CORRECTED_VC15 = 0x8000

	// INT_MSK_ECC_CORRECTED: NA
	// Position of MASK_ERR_ECC_CORRECTED_VC0 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC0_Pos = 0x0
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC0 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC0_Msk = 0x1
	// Bit MASK_ERR_ECC_CORRECTED_VC0.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC0 = 0x1
	// Position of MASK_ERR_ECC_CORRECTED_VC1 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC1_Pos = 0x1
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC1 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC1_Msk = 0x2
	// Bit MASK_ERR_ECC_CORRECTED_VC1.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC1 = 0x2
	// Position of MASK_ERR_ECC_CORRECTED_VC2 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC2_Pos = 0x2
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC2 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC2_Msk = 0x4
	// Bit MASK_ERR_ECC_CORRECTED_VC2.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC2 = 0x4
	// Position of MASK_ERR_ECC_CORRECTED_VC3 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC3_Pos = 0x3
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC3 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC3_Msk = 0x8
	// Bit MASK_ERR_ECC_CORRECTED_VC3.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC3 = 0x8
	// Position of MASK_ERR_ECC_CORRECTED_VC4 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC4_Pos = 0x4
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC4 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC4_Msk = 0x10
	// Bit MASK_ERR_ECC_CORRECTED_VC4.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC4 = 0x10
	// Position of MASK_ERR_ECC_CORRECTED_VC5 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC5_Pos = 0x5
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC5 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC5_Msk = 0x20
	// Bit MASK_ERR_ECC_CORRECTED_VC5.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC5 = 0x20
	// Position of MASK_ERR_ECC_CORRECTED_VC6 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC6_Pos = 0x6
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC6 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC6_Msk = 0x40
	// Bit MASK_ERR_ECC_CORRECTED_VC6.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC6 = 0x40
	// Position of MASK_ERR_ECC_CORRECTED_VC7 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC7_Pos = 0x7
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC7 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC7_Msk = 0x80
	// Bit MASK_ERR_ECC_CORRECTED_VC7.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC7 = 0x80
	// Position of MASK_ERR_ECC_CORRECTED_VC8 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC8_Pos = 0x8
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC8 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC8_Msk = 0x100
	// Bit MASK_ERR_ECC_CORRECTED_VC8.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC8 = 0x100
	// Position of MASK_ERR_ECC_CORRECTED_VC9 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC9_Pos = 0x9
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC9 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC9_Msk = 0x200
	// Bit MASK_ERR_ECC_CORRECTED_VC9.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC9 = 0x200
	// Position of MASK_ERR_ECC_CORRECTED_VC10 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC10_Pos = 0xa
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC10 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC10_Msk = 0x400
	// Bit MASK_ERR_ECC_CORRECTED_VC10.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC10 = 0x400
	// Position of MASK_ERR_ECC_CORRECTED_VC11 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC11_Pos = 0xb
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC11 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC11_Msk = 0x800
	// Bit MASK_ERR_ECC_CORRECTED_VC11.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC11 = 0x800
	// Position of MASK_ERR_ECC_CORRECTED_VC12 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC12_Pos = 0xc
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC12 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC12_Msk = 0x1000
	// Bit MASK_ERR_ECC_CORRECTED_VC12.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC12 = 0x1000
	// Position of MASK_ERR_ECC_CORRECTED_VC13 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC13_Pos = 0xd
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC13 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC13_Msk = 0x2000
	// Bit MASK_ERR_ECC_CORRECTED_VC13.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC13 = 0x2000
	// Position of MASK_ERR_ECC_CORRECTED_VC14 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC14_Pos = 0xe
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC14 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC14_Msk = 0x4000
	// Bit MASK_ERR_ECC_CORRECTED_VC14.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC14 = 0x4000
	// Position of MASK_ERR_ECC_CORRECTED_VC15 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC15_Pos = 0xf
	// Bit mask of MASK_ERR_ECC_CORRECTED_VC15 field.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC15_Msk = 0x8000
	// Bit MASK_ERR_ECC_CORRECTED_VC15.
	CSI_HOST_INT_MSK_ECC_CORRECTED_MASK_ERR_ECC_CORRECTED_VC15 = 0x8000

	// INT_FORCE_ECC_CORRECTED: NA
	// Position of FORCE_ERR_ECC_CORRECTED_VC0 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC0_Pos = 0x0
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC0 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC0_Msk = 0x1
	// Bit FORCE_ERR_ECC_CORRECTED_VC0.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC0 = 0x1
	// Position of FORCE_ERR_ECC_CORRECTED_VC1 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC1_Pos = 0x1
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC1 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC1_Msk = 0x2
	// Bit FORCE_ERR_ECC_CORRECTED_VC1.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC1 = 0x2
	// Position of FORCE_ERR_ECC_CORRECTED_VC2 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC2_Pos = 0x2
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC2 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC2_Msk = 0x4
	// Bit FORCE_ERR_ECC_CORRECTED_VC2.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC2 = 0x4
	// Position of FORCE_ERR_ECC_CORRECTED_VC3 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC3_Pos = 0x3
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC3 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC3_Msk = 0x8
	// Bit FORCE_ERR_ECC_CORRECTED_VC3.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC3 = 0x8
	// Position of FORCE_ERR_ECC_CORRECTED_VC4 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC4_Pos = 0x4
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC4 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC4_Msk = 0x10
	// Bit FORCE_ERR_ECC_CORRECTED_VC4.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC4 = 0x10
	// Position of FORCE_ERR_ECC_CORRECTED_VC5 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC5_Pos = 0x5
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC5 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC5_Msk = 0x20
	// Bit FORCE_ERR_ECC_CORRECTED_VC5.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC5 = 0x20
	// Position of FORCE_ERR_ECC_CORRECTED_VC6 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC6_Pos = 0x6
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC6 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC6_Msk = 0x40
	// Bit FORCE_ERR_ECC_CORRECTED_VC6.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC6 = 0x40
	// Position of FORCE_ERR_ECC_CORRECTED_VC7 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC7_Pos = 0x7
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC7 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC7_Msk = 0x80
	// Bit FORCE_ERR_ECC_CORRECTED_VC7.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC7 = 0x80
	// Position of FORCE_ERR_ECC_CORRECTED_VC8 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC8_Pos = 0x8
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC8 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC8_Msk = 0x100
	// Bit FORCE_ERR_ECC_CORRECTED_VC8.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC8 = 0x100
	// Position of FORCE_ERR_ECC_CORRECTED_VC9 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC9_Pos = 0x9
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC9 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC9_Msk = 0x200
	// Bit FORCE_ERR_ECC_CORRECTED_VC9.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC9 = 0x200
	// Position of FORCE_ERR_ECC_CORRECTED_VC10 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC10_Pos = 0xa
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC10 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC10_Msk = 0x400
	// Bit FORCE_ERR_ECC_CORRECTED_VC10.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC10 = 0x400
	// Position of FORCE_ERR_ECC_CORRECTED_VC11 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC11_Pos = 0xb
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC11 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC11_Msk = 0x800
	// Bit FORCE_ERR_ECC_CORRECTED_VC11.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC11 = 0x800
	// Position of FORCE_ERR_ECC_CORRECTED_VC12 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC12_Pos = 0xc
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC12 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC12_Msk = 0x1000
	// Bit FORCE_ERR_ECC_CORRECTED_VC12.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC12 = 0x1000
	// Position of FORCE_ERR_ECC_CORRECTED_VC13 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC13_Pos = 0xd
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC13 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC13_Msk = 0x2000
	// Bit FORCE_ERR_ECC_CORRECTED_VC13.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC13 = 0x2000
	// Position of FORCE_ERR_ECC_CORRECTED_VC14 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC14_Pos = 0xe
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC14 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC14_Msk = 0x4000
	// Bit FORCE_ERR_ECC_CORRECTED_VC14.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC14 = 0x4000
	// Position of FORCE_ERR_ECC_CORRECTED_VC15 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC15_Pos = 0xf
	// Bit mask of FORCE_ERR_ECC_CORRECTED_VC15 field.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC15_Msk = 0x8000
	// Bit FORCE_ERR_ECC_CORRECTED_VC15.
	CSI_HOST_INT_FORCE_ECC_CORRECTED_FORCE_ERR_ECC_CORRECTED_VC15 = 0x8000

	// SCRAMBLING: NA
	// Position of SCRAMBLE_ENABLE field.
	CSI_HOST_SCRAMBLING_SCRAMBLE_ENABLE_Pos = 0x0
	// Bit mask of SCRAMBLE_ENABLE field.
	CSI_HOST_SCRAMBLING_SCRAMBLE_ENABLE_Msk = 0x1
	// Bit SCRAMBLE_ENABLE.
	CSI_HOST_SCRAMBLING_SCRAMBLE_ENABLE = 0x1

	// SCRAMBLING_SEED1: NA
	// Position of SCRAMBLE_SEED_LANE1 field.
	CSI_HOST_SCRAMBLING_SEED1_SCRAMBLE_SEED_LANE1_Pos = 0x0
	// Bit mask of SCRAMBLE_SEED_LANE1 field.
	CSI_HOST_SCRAMBLING_SEED1_SCRAMBLE_SEED_LANE1_Msk = 0xffff

	// SCRAMBLING_SEED2: NA
	// Position of SCRAMBLE_SEED_LANE2 field.
	CSI_HOST_SCRAMBLING_SEED2_SCRAMBLE_SEED_LANE2_Pos = 0x0
	// Bit mask of SCRAMBLE_SEED_LANE2 field.
	CSI_HOST_SCRAMBLING_SEED2_SCRAMBLE_SEED_LANE2_Msk = 0xffff
)

// Constants for DMA: DMA (Direct Memory Access) Controller
const (
	// ID0: NA
	// Position of DMAC_ID field.
	DMAC_ID0_DMAC_ID_Pos = 0x0
	// Bit mask of DMAC_ID field.
	DMAC_ID0_DMAC_ID_Msk = 0xffffffff

	// COMPVER0: NA
	// Position of DMAC_COMPVER field.
	DMAC_COMPVER0_DMAC_COMPVER_Pos = 0x0
	// Bit mask of DMAC_COMPVER field.
	DMAC_COMPVER0_DMAC_COMPVER_Msk = 0xffffffff

	// CFG0: NA
	// Position of DMAC_EN field.
	DMAC_CFG0_DMAC_EN_Pos = 0x0
	// Bit mask of DMAC_EN field.
	DMAC_CFG0_DMAC_EN_Msk = 0x1
	// Bit DMAC_EN.
	DMAC_CFG0_DMAC_EN = 0x1
	// Position of INT_EN field.
	DMAC_CFG0_INT_EN_Pos = 0x1
	// Bit mask of INT_EN field.
	DMAC_CFG0_INT_EN_Msk = 0x2
	// Bit INT_EN.
	DMAC_CFG0_INT_EN = 0x2

	// CHEN0: NA
	// Position of CH1_EN field.
	DMAC_CHEN0_CH1_EN_Pos = 0x0
	// Bit mask of CH1_EN field.
	DMAC_CHEN0_CH1_EN_Msk = 0x1
	// Bit CH1_EN.
	DMAC_CHEN0_CH1_EN = 0x1
	// Position of CH2_EN field.
	DMAC_CHEN0_CH2_EN_Pos = 0x1
	// Bit mask of CH2_EN field.
	DMAC_CHEN0_CH2_EN_Msk = 0x2
	// Bit CH2_EN.
	DMAC_CHEN0_CH2_EN = 0x2
	// Position of CH3_EN field.
	DMAC_CHEN0_CH3_EN_Pos = 0x2
	// Bit mask of CH3_EN field.
	DMAC_CHEN0_CH3_EN_Msk = 0x4
	// Bit CH3_EN.
	DMAC_CHEN0_CH3_EN = 0x4
	// Position of CH4_EN field.
	DMAC_CHEN0_CH4_EN_Pos = 0x3
	// Bit mask of CH4_EN field.
	DMAC_CHEN0_CH4_EN_Msk = 0x8
	// Bit CH4_EN.
	DMAC_CHEN0_CH4_EN = 0x8
	// Position of CH1_EN_WE field.
	DMAC_CHEN0_CH1_EN_WE_Pos = 0x8
	// Bit mask of CH1_EN_WE field.
	DMAC_CHEN0_CH1_EN_WE_Msk = 0x100
	// Bit CH1_EN_WE.
	DMAC_CHEN0_CH1_EN_WE = 0x100
	// Position of CH2_EN_WE field.
	DMAC_CHEN0_CH2_EN_WE_Pos = 0x9
	// Bit mask of CH2_EN_WE field.
	DMAC_CHEN0_CH2_EN_WE_Msk = 0x200
	// Bit CH2_EN_WE.
	DMAC_CHEN0_CH2_EN_WE = 0x200
	// Position of CH3_EN_WE field.
	DMAC_CHEN0_CH3_EN_WE_Pos = 0xa
	// Bit mask of CH3_EN_WE field.
	DMAC_CHEN0_CH3_EN_WE_Msk = 0x400
	// Bit CH3_EN_WE.
	DMAC_CHEN0_CH3_EN_WE = 0x400
	// Position of CH4_EN_WE field.
	DMAC_CHEN0_CH4_EN_WE_Pos = 0xb
	// Bit mask of CH4_EN_WE field.
	DMAC_CHEN0_CH4_EN_WE_Msk = 0x800
	// Bit CH4_EN_WE.
	DMAC_CHEN0_CH4_EN_WE = 0x800
	// Position of CH1_SUSP field.
	DMAC_CHEN0_CH1_SUSP_Pos = 0x10
	// Bit mask of CH1_SUSP field.
	DMAC_CHEN0_CH1_SUSP_Msk = 0x10000
	// Bit CH1_SUSP.
	DMAC_CHEN0_CH1_SUSP = 0x10000
	// Position of CH2_SUSP field.
	DMAC_CHEN0_CH2_SUSP_Pos = 0x11
	// Bit mask of CH2_SUSP field.
	DMAC_CHEN0_CH2_SUSP_Msk = 0x20000
	// Bit CH2_SUSP.
	DMAC_CHEN0_CH2_SUSP = 0x20000
	// Position of CH3_SUSP field.
	DMAC_CHEN0_CH3_SUSP_Pos = 0x12
	// Bit mask of CH3_SUSP field.
	DMAC_CHEN0_CH3_SUSP_Msk = 0x40000
	// Bit CH3_SUSP.
	DMAC_CHEN0_CH3_SUSP = 0x40000
	// Position of CH4_SUSP field.
	DMAC_CHEN0_CH4_SUSP_Pos = 0x13
	// Bit mask of CH4_SUSP field.
	DMAC_CHEN0_CH4_SUSP_Msk = 0x80000
	// Bit CH4_SUSP.
	DMAC_CHEN0_CH4_SUSP = 0x80000
	// Position of CH1_SUSP_WE field.
	DMAC_CHEN0_CH1_SUSP_WE_Pos = 0x18
	// Bit mask of CH1_SUSP_WE field.
	DMAC_CHEN0_CH1_SUSP_WE_Msk = 0x1000000
	// Bit CH1_SUSP_WE.
	DMAC_CHEN0_CH1_SUSP_WE = 0x1000000
	// Position of CH2_SUSP_WE field.
	DMAC_CHEN0_CH2_SUSP_WE_Pos = 0x19
	// Bit mask of CH2_SUSP_WE field.
	DMAC_CHEN0_CH2_SUSP_WE_Msk = 0x2000000
	// Bit CH2_SUSP_WE.
	DMAC_CHEN0_CH2_SUSP_WE = 0x2000000
	// Position of CH3_SUSP_WE field.
	DMAC_CHEN0_CH3_SUSP_WE_Pos = 0x1a
	// Bit mask of CH3_SUSP_WE field.
	DMAC_CHEN0_CH3_SUSP_WE_Msk = 0x4000000
	// Bit CH3_SUSP_WE.
	DMAC_CHEN0_CH3_SUSP_WE = 0x4000000
	// Position of CH4_SUSP_WE field.
	DMAC_CHEN0_CH4_SUSP_WE_Pos = 0x1b
	// Bit mask of CH4_SUSP_WE field.
	DMAC_CHEN0_CH4_SUSP_WE_Msk = 0x8000000
	// Bit CH4_SUSP_WE.
	DMAC_CHEN0_CH4_SUSP_WE = 0x8000000

	// CHEN1: NA
	// Position of CH1_ABORT field.
	DMAC_CHEN1_CH1_ABORT_Pos = 0x0
	// Bit mask of CH1_ABORT field.
	DMAC_CHEN1_CH1_ABORT_Msk = 0x1
	// Bit CH1_ABORT.
	DMAC_CHEN1_CH1_ABORT = 0x1
	// Position of CH2_ABORT field.
	DMAC_CHEN1_CH2_ABORT_Pos = 0x1
	// Bit mask of CH2_ABORT field.
	DMAC_CHEN1_CH2_ABORT_Msk = 0x2
	// Bit CH2_ABORT.
	DMAC_CHEN1_CH2_ABORT = 0x2
	// Position of CH3_ABORT field.
	DMAC_CHEN1_CH3_ABORT_Pos = 0x2
	// Bit mask of CH3_ABORT field.
	DMAC_CHEN1_CH3_ABORT_Msk = 0x4
	// Bit CH3_ABORT.
	DMAC_CHEN1_CH3_ABORT = 0x4
	// Position of CH4_ABORT field.
	DMAC_CHEN1_CH4_ABORT_Pos = 0x3
	// Bit mask of CH4_ABORT field.
	DMAC_CHEN1_CH4_ABORT_Msk = 0x8
	// Bit CH4_ABORT.
	DMAC_CHEN1_CH4_ABORT = 0x8
	// Position of CH1_ABORT_WE field.
	DMAC_CHEN1_CH1_ABORT_WE_Pos = 0x8
	// Bit mask of CH1_ABORT_WE field.
	DMAC_CHEN1_CH1_ABORT_WE_Msk = 0x100
	// Bit CH1_ABORT_WE.
	DMAC_CHEN1_CH1_ABORT_WE = 0x100
	// Position of CH2_ABORT_WE field.
	DMAC_CHEN1_CH2_ABORT_WE_Pos = 0x9
	// Bit mask of CH2_ABORT_WE field.
	DMAC_CHEN1_CH2_ABORT_WE_Msk = 0x200
	// Bit CH2_ABORT_WE.
	DMAC_CHEN1_CH2_ABORT_WE = 0x200
	// Position of CH3_ABORT_WE field.
	DMAC_CHEN1_CH3_ABORT_WE_Pos = 0xa
	// Bit mask of CH3_ABORT_WE field.
	DMAC_CHEN1_CH3_ABORT_WE_Msk = 0x400
	// Bit CH3_ABORT_WE.
	DMAC_CHEN1_CH3_ABORT_WE = 0x400
	// Position of CH4_ABORT_WE field.
	DMAC_CHEN1_CH4_ABORT_WE_Pos = 0xb
	// Bit mask of CH4_ABORT_WE field.
	DMAC_CHEN1_CH4_ABORT_WE_Msk = 0x800
	// Bit CH4_ABORT_WE.
	DMAC_CHEN1_CH4_ABORT_WE = 0x800

	// INTSTATUS0: NA
	// Position of CH1_INTSTAT field.
	DMAC_INTSTATUS0_CH1_INTSTAT_Pos = 0x0
	// Bit mask of CH1_INTSTAT field.
	DMAC_INTSTATUS0_CH1_INTSTAT_Msk = 0x1
	// Bit CH1_INTSTAT.
	DMAC_INTSTATUS0_CH1_INTSTAT = 0x1
	// Position of CH2_INTSTAT field.
	DMAC_INTSTATUS0_CH2_INTSTAT_Pos = 0x1
	// Bit mask of CH2_INTSTAT field.
	DMAC_INTSTATUS0_CH2_INTSTAT_Msk = 0x2
	// Bit CH2_INTSTAT.
	DMAC_INTSTATUS0_CH2_INTSTAT = 0x2
	// Position of CH3_INTSTAT field.
	DMAC_INTSTATUS0_CH3_INTSTAT_Pos = 0x2
	// Bit mask of CH3_INTSTAT field.
	DMAC_INTSTATUS0_CH3_INTSTAT_Msk = 0x4
	// Bit CH3_INTSTAT.
	DMAC_INTSTATUS0_CH3_INTSTAT = 0x4
	// Position of CH4_INTSTAT field.
	DMAC_INTSTATUS0_CH4_INTSTAT_Pos = 0x3
	// Bit mask of CH4_INTSTAT field.
	DMAC_INTSTATUS0_CH4_INTSTAT_Msk = 0x8
	// Bit CH4_INTSTAT.
	DMAC_INTSTATUS0_CH4_INTSTAT = 0x8
	// Position of COMMONREG_INTSTAT field.
	DMAC_INTSTATUS0_COMMONREG_INTSTAT_Pos = 0x10
	// Bit mask of COMMONREG_INTSTAT field.
	DMAC_INTSTATUS0_COMMONREG_INTSTAT_Msk = 0x10000
	// Bit COMMONREG_INTSTAT.
	DMAC_INTSTATUS0_COMMONREG_INTSTAT = 0x10000

	// COMMONREG_INTCLEAR0: NA
	// Position of CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_Pos = 0x0
	// Bit mask of CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_Msk = 0x1
	// Bit CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT = 0x1
	// Position of CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_Pos = 0x1
	// Bit mask of CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_Msk = 0x2
	// Bit CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT = 0x2
	// Position of CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_Pos = 0x2
	// Bit mask of CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_Msk = 0x4
	// Bit CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT = 0x4
	// Position of CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_Pos = 0x3
	// Bit mask of CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_Msk = 0x8
	// Bit CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT = 0x8
	// Position of CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_Msk = 0x80
	// Bit CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT = 0x80
	// Position of CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_Msk = 0x100
	// Bit CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT = 0x100
	// Position of CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_Pos = 0x9
	// Bit mask of CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_Msk = 0x200
	// Bit CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT = 0x200
	// Position of CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xa
	// Bit mask of CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x400
	// Bit CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT = 0x400
	// Position of CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_Pos = 0xb
	// Bit mask of CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_Msk = 0x800
	// Bit CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT = 0x800
	// Position of CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xc
	// Bit mask of CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x1000
	// Bit CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT = 0x1000
	// Position of CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_Pos = 0xd
	// Bit mask of CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_Msk = 0x2000
	// Bit CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT = 0x2000
	// Position of CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xe
	// Bit mask of CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x4000
	// Bit CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT = 0x4000
	// Position of CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_Pos = 0xf
	// Bit mask of CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_Msk = 0x8000
	// Bit CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT = 0x8000
	// Position of CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x10
	// Bit mask of CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x10000
	// Bit CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT = 0x10000
	// Position of CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_Pos = 0x11
	// Bit mask of CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_Msk = 0x20000
	// Bit CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT = 0x20000
	// Position of CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x12
	// Bit mask of CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x40000
	// Bit CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT = 0x40000
	// Position of CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_Pos = 0x13
	// Bit mask of CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_Msk = 0x80000
	// Bit CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT = 0x80000
	// Position of CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x14
	// Bit mask of CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x100000
	// Bit CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTCLEAR0_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT = 0x100000

	// COMMONREG_INTSTATUS_ENABLE0: NA
	// Position of ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_Pos = 0x0
	// Bit mask of ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_Msk = 0x1
	// Bit ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT = 0x1
	// Position of ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_Pos = 0x1
	// Bit mask of ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_Msk = 0x2
	// Bit ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT = 0x2
	// Position of ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_Pos = 0x2
	// Bit mask of ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_Msk = 0x4
	// Bit ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT = 0x4
	// Position of ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_Pos = 0x3
	// Bit mask of ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_Msk = 0x8
	// Bit ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT = 0x8
	// Position of ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_Pos = 0x7
	// Bit mask of ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_Msk = 0x80
	// Bit ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT = 0x80
	// Position of ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_Pos = 0x8
	// Bit mask of ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_Msk = 0x100
	// Bit ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT = 0x100
	// Position of ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_Pos = 0x9
	// Bit mask of ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_Msk = 0x200
	// Bit ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT = 0x200
	// Position of ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xa
	// Bit mask of ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x400
	// Bit ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT = 0x400
	// Position of ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_Pos = 0xb
	// Bit mask of ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_Msk = 0x800
	// Bit ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT = 0x800
	// Position of ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xc
	// Bit mask of ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x1000
	// Bit ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT = 0x1000
	// Position of ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_Pos = 0xd
	// Bit mask of ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_Msk = 0x2000
	// Bit ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT = 0x2000
	// Position of ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xe
	// Bit mask of ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x4000
	// Bit ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT = 0x4000
	// Position of ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_Pos = 0xf
	// Bit mask of ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_Msk = 0x8000
	// Bit ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT = 0x8000
	// Position of ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x10
	// Bit mask of ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x10000
	// Bit ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT = 0x10000
	// Position of ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_Pos = 0x11
	// Bit mask of ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_Msk = 0x20000
	// Bit ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT = 0x20000
	// Position of ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x12
	// Bit mask of ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x40000
	// Bit ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT = 0x40000
	// Position of ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_Pos = 0x13
	// Bit mask of ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_Msk = 0x80000
	// Bit ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT = 0x80000
	// Position of ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x14
	// Bit mask of ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x100000
	// Bit ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT = 0x100000

	// COMMONREG_INTSIGNAL_ENABLE0: NA
	// Position of ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_Pos = 0x0
	// Bit mask of ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_Msk = 0x1
	// Bit ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL = 0x1
	// Position of ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_Pos = 0x1
	// Bit mask of ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_Msk = 0x2
	// Bit ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL = 0x2
	// Position of ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_Pos = 0x2
	// Bit mask of ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_Msk = 0x4
	// Bit ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL = 0x4
	// Position of ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_Pos = 0x3
	// Bit mask of ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_Msk = 0x8
	// Bit ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL = 0x8
	// Position of ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_Pos = 0x7
	// Bit mask of ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_Msk = 0x80
	// Bit ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL = 0x80
	// Position of ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_Pos = 0x8
	// Bit mask of ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_Msk = 0x100
	// Bit ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL = 0x100
	// Position of ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_Pos = 0x9
	// Bit mask of ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_Msk = 0x200
	// Bit ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL = 0x200
	// Position of ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_Pos = 0xa
	// Bit mask of ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_Msk = 0x400
	// Bit ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL = 0x400
	// Position of ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_Pos = 0xb
	// Bit mask of ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_Msk = 0x800
	// Bit ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL = 0x800
	// Position of ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_Pos = 0xc
	// Bit mask of ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_Msk = 0x1000
	// Bit ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL = 0x1000
	// Position of ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_Pos = 0xd
	// Bit mask of ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_Msk = 0x2000
	// Bit ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL = 0x2000
	// Position of ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_Pos = 0xe
	// Bit mask of ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_Msk = 0x4000
	// Bit ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL = 0x4000
	// Position of ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_Pos = 0xf
	// Bit mask of ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_Msk = 0x8000
	// Bit ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL = 0x8000
	// Position of ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_Pos = 0x10
	// Bit mask of ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_Msk = 0x10000
	// Bit ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL = 0x10000
	// Position of ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_Pos = 0x11
	// Bit mask of ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_Msk = 0x20000
	// Bit ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL = 0x20000
	// Position of ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_Pos = 0x12
	// Bit mask of ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_Msk = 0x40000
	// Bit ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL = 0x40000
	// Position of ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_Pos = 0x13
	// Bit mask of ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_Msk = 0x80000
	// Bit ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL = 0x80000
	// Position of ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_Pos = 0x14
	// Bit mask of ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL field.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_Msk = 0x100000
	// Bit ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL.
	DMAC_COMMONREG_INTSIGNAL_ENABLE0_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL = 0x100000

	// COMMONREG_INTSTATUS0: NA
	// Position of SLVIF_COMMONREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_DEC_ERR_INTSTAT_Pos = 0x0
	// Bit mask of SLVIF_COMMONREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_DEC_ERR_INTSTAT_Msk = 0x1
	// Bit SLVIF_COMMONREG_DEC_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_DEC_ERR_INTSTAT = 0x1
	// Position of SLVIF_COMMONREG_WR2RO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_Pos = 0x1
	// Bit mask of SLVIF_COMMONREG_WR2RO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_Msk = 0x2
	// Bit SLVIF_COMMONREG_WR2RO_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT = 0x2
	// Position of SLVIF_COMMONREG_RD2WO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_Pos = 0x2
	// Bit mask of SLVIF_COMMONREG_RD2WO_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_Msk = 0x4
	// Bit SLVIF_COMMONREG_RD2WO_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT = 0x4
	// Position of SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_Pos = 0x3
	// Bit mask of SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_Msk = 0x8
	// Bit SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT = 0x8
	// Position of SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_Pos = 0x7
	// Bit mask of SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_Msk = 0x80
	// Bit SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT = 0x80
	// Position of SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_Pos = 0x8
	// Bit mask of SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_Msk = 0x100
	// Bit SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT = 0x100
	// Position of MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_Pos = 0x9
	// Bit mask of MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_Msk = 0x200
	// Bit MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT = 0x200
	// Position of MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xa
	// Bit mask of MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x400
	// Bit MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT = 0x400
	// Position of MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_Pos = 0xb
	// Bit mask of MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_Msk = 0x800
	// Bit MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT = 0x800
	// Position of MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xc
	// Bit mask of MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x1000
	// Bit MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT = 0x1000
	// Position of MXIF1_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_Pos = 0xd
	// Bit mask of MXIF1_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_Msk = 0x2000
	// Bit MXIF1_BCH_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT = 0x2000
	// Position of MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_Pos = 0xe
	// Bit mask of MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x4000
	// Bit MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT = 0x4000
	// Position of MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_Pos = 0xf
	// Bit mask of MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_Msk = 0x8000
	// Bit MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT = 0x8000
	// Position of MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x10
	// Bit mask of MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x10000
	// Bit MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT = 0x10000
	// Position of MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_Pos = 0x11
	// Bit mask of MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_Msk = 0x20000
	// Bit MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT = 0x20000
	// Position of MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x12
	// Bit mask of MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x40000
	// Bit MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT = 0x40000
	// Position of MXIF2_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_Pos = 0x13
	// Bit mask of MXIF2_BCH_ECCPROT_CORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_Msk = 0x80000
	// Bit MXIF2_BCH_ECCPROT_CORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT = 0x80000
	// Position of MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_Pos = 0x14
	// Bit mask of MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT field.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_Msk = 0x100000
	// Bit MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT.
	DMAC_COMMONREG_INTSTATUS0_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT = 0x100000

	// RESET0: NA
	// Position of DMAC_RST field.
	DMAC_RESET0_DMAC_RST_Pos = 0x0
	// Bit mask of DMAC_RST field.
	DMAC_RESET0_DMAC_RST_Msk = 0x1
	// Bit DMAC_RST.
	DMAC_RESET0_DMAC_RST = 0x1

	// LOWPOWER_CFG0: NA
	// Position of GBL_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_GBL_CSLP_EN_Pos = 0x0
	// Bit mask of GBL_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_GBL_CSLP_EN_Msk = 0x1
	// Bit GBL_CSLP_EN.
	DMAC_LOWPOWER_CFG0_GBL_CSLP_EN = 0x1
	// Position of CHNL_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_CHNL_CSLP_EN_Pos = 0x1
	// Bit mask of CHNL_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_CHNL_CSLP_EN_Msk = 0x2
	// Bit CHNL_CSLP_EN.
	DMAC_LOWPOWER_CFG0_CHNL_CSLP_EN = 0x2
	// Position of SBIU_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_SBIU_CSLP_EN_Pos = 0x2
	// Bit mask of SBIU_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_SBIU_CSLP_EN_Msk = 0x4
	// Bit SBIU_CSLP_EN.
	DMAC_LOWPOWER_CFG0_SBIU_CSLP_EN = 0x4
	// Position of MXIF_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_MXIF_CSLP_EN_Pos = 0x3
	// Bit mask of MXIF_CSLP_EN field.
	DMAC_LOWPOWER_CFG0_MXIF_CSLP_EN_Msk = 0x8
	// Bit MXIF_CSLP_EN.
	DMAC_LOWPOWER_CFG0_MXIF_CSLP_EN = 0x8

	// LOWPOWER_CFG1: NA
	// Position of GLCH_LPDLY field.
	DMAC_LOWPOWER_CFG1_GLCH_LPDLY_Pos = 0x0
	// Bit mask of GLCH_LPDLY field.
	DMAC_LOWPOWER_CFG1_GLCH_LPDLY_Msk = 0xff
	// Position of SBIU_LPDLY field.
	DMAC_LOWPOWER_CFG1_SBIU_LPDLY_Pos = 0x8
	// Bit mask of SBIU_LPDLY field.
	DMAC_LOWPOWER_CFG1_SBIU_LPDLY_Msk = 0xff00
	// Position of MXIF_LPDLY field.
	DMAC_LOWPOWER_CFG1_MXIF_LPDLY_Pos = 0x10
	// Bit mask of MXIF_LPDLY field.
	DMAC_LOWPOWER_CFG1_MXIF_LPDLY_Msk = 0xff0000

	// CH1_SAR0: NA
	// Position of CH1_SAR0 field.
	DMAC_CH1_SAR0_CH1_SAR0_Pos = 0x0
	// Bit mask of CH1_SAR0 field.
	DMAC_CH1_SAR0_CH1_SAR0_Msk = 0xffffffff

	// CH1_SAR1: NA
	// Position of CH1_SAR1 field.
	DMAC_CH1_SAR1_CH1_SAR1_Pos = 0x0
	// Bit mask of CH1_SAR1 field.
	DMAC_CH1_SAR1_CH1_SAR1_Msk = 0xffffffff

	// CH1_DAR0: NA
	// Position of CH1_DAR0 field.
	DMAC_CH1_DAR0_CH1_DAR0_Pos = 0x0
	// Bit mask of CH1_DAR0 field.
	DMAC_CH1_DAR0_CH1_DAR0_Msk = 0xffffffff

	// CH1_DAR1: NA
	// Position of CH1_DAR1 field.
	DMAC_CH1_DAR1_CH1_DAR1_Pos = 0x0
	// Bit mask of CH1_DAR1 field.
	DMAC_CH1_DAR1_CH1_DAR1_Msk = 0xffffffff

	// CH1_BLOCK_TS0: NA
	// Position of CH1_BLOCK_TS field.
	DMAC_CH1_BLOCK_TS0_CH1_BLOCK_TS_Pos = 0x0
	// Bit mask of CH1_BLOCK_TS field.
	DMAC_CH1_BLOCK_TS0_CH1_BLOCK_TS_Msk = 0x3fffff

	// CH1_CTL0: NA
	// Position of CH1_SMS field.
	DMAC_CH1_CTL0_CH1_SMS_Pos = 0x0
	// Bit mask of CH1_SMS field.
	DMAC_CH1_CTL0_CH1_SMS_Msk = 0x1
	// Bit CH1_SMS.
	DMAC_CH1_CTL0_CH1_SMS = 0x1
	// Position of CH1_DMS field.
	DMAC_CH1_CTL0_CH1_DMS_Pos = 0x2
	// Bit mask of CH1_DMS field.
	DMAC_CH1_CTL0_CH1_DMS_Msk = 0x4
	// Bit CH1_DMS.
	DMAC_CH1_CTL0_CH1_DMS = 0x4
	// Position of CH1_SINC field.
	DMAC_CH1_CTL0_CH1_SINC_Pos = 0x4
	// Bit mask of CH1_SINC field.
	DMAC_CH1_CTL0_CH1_SINC_Msk = 0x10
	// Bit CH1_SINC.
	DMAC_CH1_CTL0_CH1_SINC = 0x10
	// Position of CH1_DINC field.
	DMAC_CH1_CTL0_CH1_DINC_Pos = 0x6
	// Bit mask of CH1_DINC field.
	DMAC_CH1_CTL0_CH1_DINC_Msk = 0x40
	// Bit CH1_DINC.
	DMAC_CH1_CTL0_CH1_DINC = 0x40
	// Position of CH1_SRC_TR_WIDTH field.
	DMAC_CH1_CTL0_CH1_SRC_TR_WIDTH_Pos = 0x8
	// Bit mask of CH1_SRC_TR_WIDTH field.
	DMAC_CH1_CTL0_CH1_SRC_TR_WIDTH_Msk = 0x700
	// Position of CH1_DST_TR_WIDTH field.
	DMAC_CH1_CTL0_CH1_DST_TR_WIDTH_Pos = 0xb
	// Bit mask of CH1_DST_TR_WIDTH field.
	DMAC_CH1_CTL0_CH1_DST_TR_WIDTH_Msk = 0x3800
	// Position of CH1_SRC_MSIZE field.
	DMAC_CH1_CTL0_CH1_SRC_MSIZE_Pos = 0xe
	// Bit mask of CH1_SRC_MSIZE field.
	DMAC_CH1_CTL0_CH1_SRC_MSIZE_Msk = 0x3c000
	// Position of CH1_DST_MSIZE field.
	DMAC_CH1_CTL0_CH1_DST_MSIZE_Pos = 0x12
	// Bit mask of CH1_DST_MSIZE field.
	DMAC_CH1_CTL0_CH1_DST_MSIZE_Msk = 0x3c0000
	// Position of CH1_AR_CACHE field.
	DMAC_CH1_CTL0_CH1_AR_CACHE_Pos = 0x16
	// Bit mask of CH1_AR_CACHE field.
	DMAC_CH1_CTL0_CH1_AR_CACHE_Msk = 0x3c00000
	// Position of CH1_AW_CACHE field.
	DMAC_CH1_CTL0_CH1_AW_CACHE_Pos = 0x1a
	// Bit mask of CH1_AW_CACHE field.
	DMAC_CH1_CTL0_CH1_AW_CACHE_Msk = 0x3c000000
	// Position of CH1_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH1_CTL0_CH1_NONPOSTED_LASTWRITE_EN_Pos = 0x1e
	// Bit mask of CH1_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH1_CTL0_CH1_NONPOSTED_LASTWRITE_EN_Msk = 0x40000000
	// Bit CH1_NONPOSTED_LASTWRITE_EN.
	DMAC_CH1_CTL0_CH1_NONPOSTED_LASTWRITE_EN = 0x40000000

	// CH1_CTL1: NA
	// Position of CH1_AR_PROT field.
	DMAC_CH1_CTL1_CH1_AR_PROT_Pos = 0x0
	// Bit mask of CH1_AR_PROT field.
	DMAC_CH1_CTL1_CH1_AR_PROT_Msk = 0x7
	// Position of CH1_AW_PROT field.
	DMAC_CH1_CTL1_CH1_AW_PROT_Pos = 0x3
	// Bit mask of CH1_AW_PROT field.
	DMAC_CH1_CTL1_CH1_AW_PROT_Msk = 0x38
	// Position of CH1_ARLEN_EN field.
	DMAC_CH1_CTL1_CH1_ARLEN_EN_Pos = 0x6
	// Bit mask of CH1_ARLEN_EN field.
	DMAC_CH1_CTL1_CH1_ARLEN_EN_Msk = 0x40
	// Bit CH1_ARLEN_EN.
	DMAC_CH1_CTL1_CH1_ARLEN_EN = 0x40
	// Position of CH1_ARLEN field.
	DMAC_CH1_CTL1_CH1_ARLEN_Pos = 0x7
	// Bit mask of CH1_ARLEN field.
	DMAC_CH1_CTL1_CH1_ARLEN_Msk = 0x7f80
	// Position of CH1_AWLEN_EN field.
	DMAC_CH1_CTL1_CH1_AWLEN_EN_Pos = 0xf
	// Bit mask of CH1_AWLEN_EN field.
	DMAC_CH1_CTL1_CH1_AWLEN_EN_Msk = 0x8000
	// Bit CH1_AWLEN_EN.
	DMAC_CH1_CTL1_CH1_AWLEN_EN = 0x8000
	// Position of CH1_AWLEN field.
	DMAC_CH1_CTL1_CH1_AWLEN_Pos = 0x10
	// Bit mask of CH1_AWLEN field.
	DMAC_CH1_CTL1_CH1_AWLEN_Msk = 0xff0000
	// Position of CH1_SRC_STAT_EN field.
	DMAC_CH1_CTL1_CH1_SRC_STAT_EN_Pos = 0x18
	// Bit mask of CH1_SRC_STAT_EN field.
	DMAC_CH1_CTL1_CH1_SRC_STAT_EN_Msk = 0x1000000
	// Bit CH1_SRC_STAT_EN.
	DMAC_CH1_CTL1_CH1_SRC_STAT_EN = 0x1000000
	// Position of CH1_DST_STAT_EN field.
	DMAC_CH1_CTL1_CH1_DST_STAT_EN_Pos = 0x19
	// Bit mask of CH1_DST_STAT_EN field.
	DMAC_CH1_CTL1_CH1_DST_STAT_EN_Msk = 0x2000000
	// Bit CH1_DST_STAT_EN.
	DMAC_CH1_CTL1_CH1_DST_STAT_EN = 0x2000000
	// Position of CH1_IOC_BLKTFR field.
	DMAC_CH1_CTL1_CH1_IOC_BLKTFR_Pos = 0x1a
	// Bit mask of CH1_IOC_BLKTFR field.
	DMAC_CH1_CTL1_CH1_IOC_BLKTFR_Msk = 0x4000000
	// Bit CH1_IOC_BLKTFR.
	DMAC_CH1_CTL1_CH1_IOC_BLKTFR = 0x4000000
	// Position of CH1_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH1_CTL1_CH1_SHADOWREG_OR_LLI_LAST_Pos = 0x1e
	// Bit mask of CH1_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH1_CTL1_CH1_SHADOWREG_OR_LLI_LAST_Msk = 0x40000000
	// Bit CH1_SHADOWREG_OR_LLI_LAST.
	DMAC_CH1_CTL1_CH1_SHADOWREG_OR_LLI_LAST = 0x40000000
	// Position of CH1_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH1_CTL1_CH1_SHADOWREG_OR_LLI_VALID_Pos = 0x1f
	// Bit mask of CH1_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH1_CTL1_CH1_SHADOWREG_OR_LLI_VALID_Msk = 0x80000000
	// Bit CH1_SHADOWREG_OR_LLI_VALID.
	DMAC_CH1_CTL1_CH1_SHADOWREG_OR_LLI_VALID = 0x80000000

	// CH1_CFG0: NA
	// Position of CH1_SRC_MULTBLK_TYPE field.
	DMAC_CH1_CFG0_CH1_SRC_MULTBLK_TYPE_Pos = 0x0
	// Bit mask of CH1_SRC_MULTBLK_TYPE field.
	DMAC_CH1_CFG0_CH1_SRC_MULTBLK_TYPE_Msk = 0x3
	// Position of CH1_DST_MULTBLK_TYPE field.
	DMAC_CH1_CFG0_CH1_DST_MULTBLK_TYPE_Pos = 0x2
	// Bit mask of CH1_DST_MULTBLK_TYPE field.
	DMAC_CH1_CFG0_CH1_DST_MULTBLK_TYPE_Msk = 0xc
	// Position of CH1_RD_UID field.
	DMAC_CH1_CFG0_CH1_RD_UID_Pos = 0x12
	// Bit mask of CH1_RD_UID field.
	DMAC_CH1_CFG0_CH1_RD_UID_Msk = 0x3c0000
	// Position of CH1_WR_UID field.
	DMAC_CH1_CFG0_CH1_WR_UID_Pos = 0x19
	// Bit mask of CH1_WR_UID field.
	DMAC_CH1_CFG0_CH1_WR_UID_Msk = 0x1e000000

	// CH1_CFG1: NA
	// Position of CH1_TT_FC field.
	DMAC_CH1_CFG1_CH1_TT_FC_Pos = 0x0
	// Bit mask of CH1_TT_FC field.
	DMAC_CH1_CFG1_CH1_TT_FC_Msk = 0x7
	// Position of CH1_HS_SEL_SRC field.
	DMAC_CH1_CFG1_CH1_HS_SEL_SRC_Pos = 0x3
	// Bit mask of CH1_HS_SEL_SRC field.
	DMAC_CH1_CFG1_CH1_HS_SEL_SRC_Msk = 0x8
	// Bit CH1_HS_SEL_SRC.
	DMAC_CH1_CFG1_CH1_HS_SEL_SRC = 0x8
	// Position of CH1_HS_SEL_DST field.
	DMAC_CH1_CFG1_CH1_HS_SEL_DST_Pos = 0x4
	// Bit mask of CH1_HS_SEL_DST field.
	DMAC_CH1_CFG1_CH1_HS_SEL_DST_Msk = 0x10
	// Bit CH1_HS_SEL_DST.
	DMAC_CH1_CFG1_CH1_HS_SEL_DST = 0x10
	// Position of CH1_SRC_HWHS_POL field.
	DMAC_CH1_CFG1_CH1_SRC_HWHS_POL_Pos = 0x5
	// Bit mask of CH1_SRC_HWHS_POL field.
	DMAC_CH1_CFG1_CH1_SRC_HWHS_POL_Msk = 0x20
	// Bit CH1_SRC_HWHS_POL.
	DMAC_CH1_CFG1_CH1_SRC_HWHS_POL = 0x20
	// Position of CH1_DST_HWHS_POL field.
	DMAC_CH1_CFG1_CH1_DST_HWHS_POL_Pos = 0x6
	// Bit mask of CH1_DST_HWHS_POL field.
	DMAC_CH1_CFG1_CH1_DST_HWHS_POL_Msk = 0x40
	// Bit CH1_DST_HWHS_POL.
	DMAC_CH1_CFG1_CH1_DST_HWHS_POL = 0x40
	// Position of CH1_SRC_PER field.
	DMAC_CH1_CFG1_CH1_SRC_PER_Pos = 0x7
	// Bit mask of CH1_SRC_PER field.
	DMAC_CH1_CFG1_CH1_SRC_PER_Msk = 0x180
	// Position of CH1_DST_PER field.
	DMAC_CH1_CFG1_CH1_DST_PER_Pos = 0xc
	// Bit mask of CH1_DST_PER field.
	DMAC_CH1_CFG1_CH1_DST_PER_Msk = 0x3000
	// Position of CH1_CH_PRIOR field.
	DMAC_CH1_CFG1_CH1_CH_PRIOR_Pos = 0x11
	// Bit mask of CH1_CH_PRIOR field.
	DMAC_CH1_CFG1_CH1_CH_PRIOR_Msk = 0xe0000
	// Position of CH1_LOCK_CH field.
	DMAC_CH1_CFG1_CH1_LOCK_CH_Pos = 0x14
	// Bit mask of CH1_LOCK_CH field.
	DMAC_CH1_CFG1_CH1_LOCK_CH_Msk = 0x100000
	// Bit CH1_LOCK_CH.
	DMAC_CH1_CFG1_CH1_LOCK_CH = 0x100000
	// Position of CH1_LOCK_CH_L field.
	DMAC_CH1_CFG1_CH1_LOCK_CH_L_Pos = 0x15
	// Bit mask of CH1_LOCK_CH_L field.
	DMAC_CH1_CFG1_CH1_LOCK_CH_L_Msk = 0x600000
	// Position of CH1_SRC_OSR_LMT field.
	DMAC_CH1_CFG1_CH1_SRC_OSR_LMT_Pos = 0x17
	// Bit mask of CH1_SRC_OSR_LMT field.
	DMAC_CH1_CFG1_CH1_SRC_OSR_LMT_Msk = 0x7800000
	// Position of CH1_DST_OSR_LMT field.
	DMAC_CH1_CFG1_CH1_DST_OSR_LMT_Pos = 0x1b
	// Bit mask of CH1_DST_OSR_LMT field.
	DMAC_CH1_CFG1_CH1_DST_OSR_LMT_Msk = 0x78000000

	// CH1_LLP0: NA
	// Position of CH1_LMS field.
	DMAC_CH1_LLP0_CH1_LMS_Pos = 0x0
	// Bit mask of CH1_LMS field.
	DMAC_CH1_LLP0_CH1_LMS_Msk = 0x1
	// Bit CH1_LMS.
	DMAC_CH1_LLP0_CH1_LMS = 0x1
	// Position of CH1_LOC0 field.
	DMAC_CH1_LLP0_CH1_LOC0_Pos = 0x6
	// Bit mask of CH1_LOC0 field.
	DMAC_CH1_LLP0_CH1_LOC0_Msk = 0xffffffc0

	// CH1_LLP1: NA
	// Position of CH1_LOC1 field.
	DMAC_CH1_LLP1_CH1_LOC1_Pos = 0x0
	// Bit mask of CH1_LOC1 field.
	DMAC_CH1_LLP1_CH1_LOC1_Msk = 0xffffffff

	// CH1_STATUS0: NA
	// Position of CH1_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH1_STATUS0_CH1_CMPLTD_BLK_TFR_SIZE_Pos = 0x0
	// Bit mask of CH1_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH1_STATUS0_CH1_CMPLTD_BLK_TFR_SIZE_Msk = 0x3fffff

	// CH1_STATUS1: NA
	// Position of CH1_DATA_LEFT_IN_FIFO field.
	DMAC_CH1_STATUS1_CH1_DATA_LEFT_IN_FIFO_Pos = 0x0
	// Bit mask of CH1_DATA_LEFT_IN_FIFO field.
	DMAC_CH1_STATUS1_CH1_DATA_LEFT_IN_FIFO_Msk = 0x7fff

	// CH1_SWHSSRC0: NA
	// Position of CH1_SWHS_REQ_SRC field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_REQ_SRC_Pos = 0x0
	// Bit mask of CH1_SWHS_REQ_SRC field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_REQ_SRC_Msk = 0x1
	// Bit CH1_SWHS_REQ_SRC.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_REQ_SRC = 0x1
	// Position of CH1_SWHS_REQ_SRC_WE field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_REQ_SRC_WE_Pos = 0x1
	// Bit mask of CH1_SWHS_REQ_SRC_WE field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_REQ_SRC_WE_Msk = 0x2
	// Bit CH1_SWHS_REQ_SRC_WE.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_REQ_SRC_WE = 0x2
	// Position of CH1_SWHS_SGLREQ_SRC field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_Pos = 0x2
	// Bit mask of CH1_SWHS_SGLREQ_SRC field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_Msk = 0x4
	// Bit CH1_SWHS_SGLREQ_SRC.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC = 0x4
	// Position of CH1_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_WE_Pos = 0x3
	// Bit mask of CH1_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_WE_Msk = 0x8
	// Bit CH1_SWHS_SGLREQ_SRC_WE.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_SGLREQ_SRC_WE = 0x8
	// Position of CH1_SWHS_LST_SRC field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_LST_SRC_Pos = 0x4
	// Bit mask of CH1_SWHS_LST_SRC field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_LST_SRC_Msk = 0x10
	// Bit CH1_SWHS_LST_SRC.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_LST_SRC = 0x10
	// Position of CH1_SWHS_LST_SRC_WE field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_LST_SRC_WE_Pos = 0x5
	// Bit mask of CH1_SWHS_LST_SRC_WE field.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_LST_SRC_WE_Msk = 0x20
	// Bit CH1_SWHS_LST_SRC_WE.
	DMAC_CH1_SWHSSRC0_CH1_SWHS_LST_SRC_WE = 0x20

	// CH1_SWHSDST0: NA
	// Position of CH1_SWHS_REQ_DST field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_REQ_DST_Pos = 0x0
	// Bit mask of CH1_SWHS_REQ_DST field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_REQ_DST_Msk = 0x1
	// Bit CH1_SWHS_REQ_DST.
	DMAC_CH1_SWHSDST0_CH1_SWHS_REQ_DST = 0x1
	// Position of CH1_SWHS_REQ_DST_WE field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_REQ_DST_WE_Pos = 0x1
	// Bit mask of CH1_SWHS_REQ_DST_WE field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_REQ_DST_WE_Msk = 0x2
	// Bit CH1_SWHS_REQ_DST_WE.
	DMAC_CH1_SWHSDST0_CH1_SWHS_REQ_DST_WE = 0x2
	// Position of CH1_SWHS_SGLREQ_DST field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_Pos = 0x2
	// Bit mask of CH1_SWHS_SGLREQ_DST field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_Msk = 0x4
	// Bit CH1_SWHS_SGLREQ_DST.
	DMAC_CH1_SWHSDST0_CH1_SWHS_SGLREQ_DST = 0x4
	// Position of CH1_SWHS_SGLREQ_DST_WE field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_WE_Pos = 0x3
	// Bit mask of CH1_SWHS_SGLREQ_DST_WE field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_WE_Msk = 0x8
	// Bit CH1_SWHS_SGLREQ_DST_WE.
	DMAC_CH1_SWHSDST0_CH1_SWHS_SGLREQ_DST_WE = 0x8
	// Position of CH1_SWHS_LST_DST field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_LST_DST_Pos = 0x4
	// Bit mask of CH1_SWHS_LST_DST field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_LST_DST_Msk = 0x10
	// Bit CH1_SWHS_LST_DST.
	DMAC_CH1_SWHSDST0_CH1_SWHS_LST_DST = 0x10
	// Position of CH1_SWHS_LST_DST_WE field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_LST_DST_WE_Pos = 0x5
	// Bit mask of CH1_SWHS_LST_DST_WE field.
	DMAC_CH1_SWHSDST0_CH1_SWHS_LST_DST_WE_Msk = 0x20
	// Bit CH1_SWHS_LST_DST_WE.
	DMAC_CH1_SWHSDST0_CH1_SWHS_LST_DST_WE = 0x20

	// CH1_BLK_TFR_RESUMEREQ0: NA
	// Position of CH1_BLK_TFR_RESUMEREQ field.
	DMAC_CH1_BLK_TFR_RESUMEREQ0_CH1_BLK_TFR_RESUMEREQ_Pos = 0x0
	// Bit mask of CH1_BLK_TFR_RESUMEREQ field.
	DMAC_CH1_BLK_TFR_RESUMEREQ0_CH1_BLK_TFR_RESUMEREQ_Msk = 0x1
	// Bit CH1_BLK_TFR_RESUMEREQ.
	DMAC_CH1_BLK_TFR_RESUMEREQ0_CH1_BLK_TFR_RESUMEREQ = 0x1

	// CH1_AXI_ID0: NA
	// Position of CH1_AXI_READ_ID_SUFFIX field.
	DMAC_CH1_AXI_ID0_CH1_AXI_READ_ID_SUFFIX_Pos = 0x0
	// Bit mask of CH1_AXI_READ_ID_SUFFIX field.
	DMAC_CH1_AXI_ID0_CH1_AXI_READ_ID_SUFFIX_Msk = 0x1
	// Bit CH1_AXI_READ_ID_SUFFIX.
	DMAC_CH1_AXI_ID0_CH1_AXI_READ_ID_SUFFIX = 0x1
	// Position of CH1_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH1_AXI_ID0_CH1_AXI_WRITE_ID_SUFFIX_Pos = 0x10
	// Bit mask of CH1_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH1_AXI_ID0_CH1_AXI_WRITE_ID_SUFFIX_Msk = 0x10000
	// Bit CH1_AXI_WRITE_ID_SUFFIX.
	DMAC_CH1_AXI_ID0_CH1_AXI_WRITE_ID_SUFFIX = 0x10000

	// CH1_AXI_QOS0: NA
	// Position of CH1_AXI_AWQOS field.
	DMAC_CH1_AXI_QOS0_CH1_AXI_AWQOS_Pos = 0x0
	// Bit mask of CH1_AXI_AWQOS field.
	DMAC_CH1_AXI_QOS0_CH1_AXI_AWQOS_Msk = 0xf
	// Position of CH1_AXI_ARQOS field.
	DMAC_CH1_AXI_QOS0_CH1_AXI_ARQOS_Pos = 0x4
	// Bit mask of CH1_AXI_ARQOS field.
	DMAC_CH1_AXI_QOS0_CH1_AXI_ARQOS_Msk = 0xf0

	// CH1_SSTAT0: NA
	// Position of CH1_SSTAT field.
	DMAC_CH1_SSTAT0_CH1_SSTAT_Pos = 0x0
	// Bit mask of CH1_SSTAT field.
	DMAC_CH1_SSTAT0_CH1_SSTAT_Msk = 0xffffffff

	// CH1_DSTAT0: NA
	// Position of CH1_DSTAT field.
	DMAC_CH1_DSTAT0_CH1_DSTAT_Pos = 0x0
	// Bit mask of CH1_DSTAT field.
	DMAC_CH1_DSTAT0_CH1_DSTAT_Msk = 0xffffffff

	// CH1_SSTATAR0: NA
	// Position of CH1_SSTATAR0 field.
	DMAC_CH1_SSTATAR0_CH1_SSTATAR0_Pos = 0x0
	// Bit mask of CH1_SSTATAR0 field.
	DMAC_CH1_SSTATAR0_CH1_SSTATAR0_Msk = 0xffffffff

	// CH1_SSTATAR1: NA
	// Position of CH1_SSTATAR1 field.
	DMAC_CH1_SSTATAR1_CH1_SSTATAR1_Pos = 0x0
	// Bit mask of CH1_SSTATAR1 field.
	DMAC_CH1_SSTATAR1_CH1_SSTATAR1_Msk = 0xffffffff

	// CH1_DSTATAR0: NA
	// Position of CH1_DSTATAR0 field.
	DMAC_CH1_DSTATAR0_CH1_DSTATAR0_Pos = 0x0
	// Bit mask of CH1_DSTATAR0 field.
	DMAC_CH1_DSTATAR0_CH1_DSTATAR0_Msk = 0xffffffff

	// CH1_DSTATAR1: NA
	// Position of CH1_DSTATAR1 field.
	DMAC_CH1_DSTATAR1_CH1_DSTATAR1_Pos = 0x0
	// Bit mask of CH1_DSTATAR1 field.
	DMAC_CH1_DSTATAR1_CH1_DSTATAR1_Msk = 0xffffffff

	// CH1_INTSTATUS_ENABLE0: NA
	// Position of CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH1_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH1_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH1_ENABLE_DMA_TFR_DONE_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH1_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH1_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH1_ENABLE_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH1_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH1_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH1_ENABLE_DST_TRANSCOMP_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH1_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH1_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH1_ENABLE_SRC_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH1_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH1_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH1_ENABLE_DST_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH1_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH1_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH1_ENABLE_SRC_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH1_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH1_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH1_ENABLE_DST_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH1_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH1_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH1_ENABLE_CH_SUSPENDED_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH1_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH1_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH1_ENABLE_CH_DISABLED_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH1_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH1_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH1_ENABLE_CH_ABORTED_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSTAT = 0x80000000

	// CH1_INTSTATUS_ENABLE1: NA
	// Position of CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH1_INTSTATUS0: NA
	// Position of CH1_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH1_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH1_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH1_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH1_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH1_DMA_TFR_DONE_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH1_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH1_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH1_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH1_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH1_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH1_DST_TRANSCOMP_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH1_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH1_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH1_SRC_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH1_DST_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH1_DST_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH1_DST_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH1_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH1_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH1_SRC_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH1_DST_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH1_DST_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH1_DST_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH1_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH1_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH1_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH1_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH1_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH1_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH1_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH1_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH1_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH1_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH1_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH1_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH1_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH1_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH1_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH1_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH1_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH1_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH1_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH1_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH1_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH1_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH1_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH1_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH1_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH1_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH1_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH1_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH1_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH1_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH1_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH1_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH1_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH1_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH1_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH1_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH1_CH_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH1_CH_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH1_CH_SUSPENDED_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH1_CH_DISABLED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH1_CH_DISABLED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH1_CH_DISABLED_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH1_CH_ABORTED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH1_CH_ABORTED_INTSTAT field.
	DMAC_CH1_INTSTATUS0_CH1_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH1_CH_ABORTED_INTSTAT.
	DMAC_CH1_INTSTATUS0_CH1_CH_ABORTED_INTSTAT = 0x80000000

	// CH1_INTSTATUS1: NA
	// Position of CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH1_INTSTATUS1_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH1_INTSIGNAL_ENABLE0: NA
	// Position of CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Pos = 0x0
	// Bit mask of CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Msk = 0x1
	// Bit CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL = 0x1
	// Position of CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_Pos = 0x1
	// Bit mask of CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_Msk = 0x2
	// Bit CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL = 0x2
	// Position of CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Pos = 0x3
	// Bit mask of CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Msk = 0x8
	// Bit CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL = 0x8
	// Position of CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_Pos = 0x4
	// Bit mask of CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_Msk = 0x10
	// Bit CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL = 0x10
	// Position of CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_Pos = 0x5
	// Bit mask of CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_Msk = 0x20
	// Bit CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL = 0x20
	// Position of CH1_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_Pos = 0x6
	// Bit mask of CH1_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_Msk = 0x40
	// Bit CH1_ENABLE_DST_DEC_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL = 0x40
	// Position of CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_Pos = 0x7
	// Bit mask of CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_Msk = 0x80
	// Bit CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL = 0x80
	// Position of CH1_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_Pos = 0x8
	// Bit mask of CH1_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_Msk = 0x100
	// Bit CH1_ENABLE_DST_SLV_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL = 0x100
	// Position of CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Pos = 0x9
	// Bit mask of CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Msk = 0x200
	// Bit CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL = 0x200
	// Position of CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Pos = 0xa
	// Bit mask of CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Msk = 0x400
	// Bit CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL = 0x400
	// Position of CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Pos = 0xb
	// Bit mask of CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Msk = 0x800
	// Bit CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL = 0x800
	// Position of CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Pos = 0xc
	// Bit mask of CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Msk = 0x1000
	// Bit CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL = 0x1000
	// Position of CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Pos = 0xd
	// Bit mask of CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Msk = 0x2000
	// Bit CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL = 0x2000
	// Position of CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Pos = 0xe
	// Bit mask of CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Msk = 0x4000
	// Bit CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL = 0x4000
	// Position of CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Pos = 0x10
	// Bit mask of CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Msk = 0x10000
	// Bit CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL = 0x10000
	// Position of CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Pos = 0x11
	// Bit mask of CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Msk = 0x20000
	// Bit CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL = 0x20000
	// Position of CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Pos = 0x12
	// Bit mask of CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Msk = 0x40000
	// Bit CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL = 0x40000
	// Position of CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Pos = 0x13
	// Bit mask of CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Msk = 0x80000
	// Bit CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL = 0x80000
	// Position of CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Pos = 0x14
	// Bit mask of CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Msk = 0x100000
	// Bit CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL = 0x100000
	// Position of CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Pos = 0x15
	// Bit mask of CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Msk = 0x200000
	// Bit CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL = 0x200000
	// Position of CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Pos = 0x19
	// Bit mask of CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Msk = 0x2000000
	// Bit CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL = 0x2000000
	// Position of CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Pos = 0x1b
	// Bit mask of CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Msk = 0x8000000
	// Bit CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL = 0x8000000
	// Position of CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Pos = 0x1c
	// Bit mask of CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Msk = 0x10000000
	// Bit CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL = 0x10000000
	// Position of CH1_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_Pos = 0x1d
	// Bit mask of CH1_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_Msk = 0x20000000
	// Bit CH1_ENABLE_CH_SUSPENDED_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL = 0x20000000
	// Position of CH1_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSIGNAL_Pos = 0x1e
	// Bit mask of CH1_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSIGNAL_Msk = 0x40000000
	// Bit CH1_ENABLE_CH_DISABLED_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_DISABLED_INTSIGNAL = 0x40000000
	// Position of CH1_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSIGNAL_Pos = 0x1f
	// Bit mask of CH1_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSIGNAL_Msk = 0x80000000
	// Bit CH1_ENABLE_CH_ABORTED_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE0_CH1_ENABLE_CH_ABORTED_INTSIGNAL = 0x80000000

	// CH1_INTSIGNAL_ENABLE1: NA
	// Position of CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Pos = 0x0
	// Bit mask of CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Msk = 0x1
	// Bit CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL = 0x1
	// Position of CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Pos = 0x1
	// Bit mask of CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Msk = 0x2
	// Bit CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL = 0x2
	// Position of CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Pos = 0x2
	// Bit mask of CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Msk = 0x4
	// Bit CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL = 0x4
	// Position of CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Pos = 0x3
	// Bit mask of CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Msk = 0x8
	// Bit CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH1_INTSIGNAL_ENABLE1_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL = 0x8

	// CH1_INTCLEAR0: NA
	// Position of CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH1_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH1_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH1_CLEAR_DMA_TFR_DONE_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH1_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH1_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH1_CLEAR_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH1_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH1_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH1_CLEAR_DST_TRANSCOMP_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH1_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH1_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH1_CLEAR_SRC_DEC_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH1_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH1_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH1_CLEAR_DST_DEC_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH1_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH1_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH1_CLEAR_SRC_SLV_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH1_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH1_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH1_CLEAR_DST_SLV_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH1_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH1_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH1_CLEAR_CH_SUSPENDED_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH1_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH1_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH1_CLEAR_CH_DISABLED_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH1_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH1_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH1_CLEAR_CH_ABORTED_INTSTAT.
	DMAC_CH1_INTCLEAR0_CH1_CLEAR_CH_ABORTED_INTSTAT = 0x80000000

	// CH1_INTCLEAR1: NA
	// Position of CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH1_INTCLEAR1_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH2_SAR0: NA
	// Position of CH2_SAR0 field.
	DMAC_CH2_SAR0_CH2_SAR0_Pos = 0x0
	// Bit mask of CH2_SAR0 field.
	DMAC_CH2_SAR0_CH2_SAR0_Msk = 0xffffffff

	// CH2_SAR1: NA
	// Position of CH2_SAR1 field.
	DMAC_CH2_SAR1_CH2_SAR1_Pos = 0x0
	// Bit mask of CH2_SAR1 field.
	DMAC_CH2_SAR1_CH2_SAR1_Msk = 0xffffffff

	// CH2_DAR0: NA
	// Position of CH2_DAR0 field.
	DMAC_CH2_DAR0_CH2_DAR0_Pos = 0x0
	// Bit mask of CH2_DAR0 field.
	DMAC_CH2_DAR0_CH2_DAR0_Msk = 0xffffffff

	// CH2_DAR1: NA
	// Position of CH2_DAR1 field.
	DMAC_CH2_DAR1_CH2_DAR1_Pos = 0x0
	// Bit mask of CH2_DAR1 field.
	DMAC_CH2_DAR1_CH2_DAR1_Msk = 0xffffffff

	// CH2_BLOCK_TS0: NA
	// Position of CH2_BLOCK_TS field.
	DMAC_CH2_BLOCK_TS0_CH2_BLOCK_TS_Pos = 0x0
	// Bit mask of CH2_BLOCK_TS field.
	DMAC_CH2_BLOCK_TS0_CH2_BLOCK_TS_Msk = 0x3fffff

	// CH2_CTL0: NA
	// Position of CH2_SMS field.
	DMAC_CH2_CTL0_CH2_SMS_Pos = 0x0
	// Bit mask of CH2_SMS field.
	DMAC_CH2_CTL0_CH2_SMS_Msk = 0x1
	// Bit CH2_SMS.
	DMAC_CH2_CTL0_CH2_SMS = 0x1
	// Position of CH2_DMS field.
	DMAC_CH2_CTL0_CH2_DMS_Pos = 0x2
	// Bit mask of CH2_DMS field.
	DMAC_CH2_CTL0_CH2_DMS_Msk = 0x4
	// Bit CH2_DMS.
	DMAC_CH2_CTL0_CH2_DMS = 0x4
	// Position of CH2_SINC field.
	DMAC_CH2_CTL0_CH2_SINC_Pos = 0x4
	// Bit mask of CH2_SINC field.
	DMAC_CH2_CTL0_CH2_SINC_Msk = 0x10
	// Bit CH2_SINC.
	DMAC_CH2_CTL0_CH2_SINC = 0x10
	// Position of CH2_DINC field.
	DMAC_CH2_CTL0_CH2_DINC_Pos = 0x6
	// Bit mask of CH2_DINC field.
	DMAC_CH2_CTL0_CH2_DINC_Msk = 0x40
	// Bit CH2_DINC.
	DMAC_CH2_CTL0_CH2_DINC = 0x40
	// Position of CH2_SRC_TR_WIDTH field.
	DMAC_CH2_CTL0_CH2_SRC_TR_WIDTH_Pos = 0x8
	// Bit mask of CH2_SRC_TR_WIDTH field.
	DMAC_CH2_CTL0_CH2_SRC_TR_WIDTH_Msk = 0x700
	// Position of CH2_DST_TR_WIDTH field.
	DMAC_CH2_CTL0_CH2_DST_TR_WIDTH_Pos = 0xb
	// Bit mask of CH2_DST_TR_WIDTH field.
	DMAC_CH2_CTL0_CH2_DST_TR_WIDTH_Msk = 0x3800
	// Position of CH2_SRC_MSIZE field.
	DMAC_CH2_CTL0_CH2_SRC_MSIZE_Pos = 0xe
	// Bit mask of CH2_SRC_MSIZE field.
	DMAC_CH2_CTL0_CH2_SRC_MSIZE_Msk = 0x3c000
	// Position of CH2_DST_MSIZE field.
	DMAC_CH2_CTL0_CH2_DST_MSIZE_Pos = 0x12
	// Bit mask of CH2_DST_MSIZE field.
	DMAC_CH2_CTL0_CH2_DST_MSIZE_Msk = 0x3c0000
	// Position of CH2_AR_CACHE field.
	DMAC_CH2_CTL0_CH2_AR_CACHE_Pos = 0x16
	// Bit mask of CH2_AR_CACHE field.
	DMAC_CH2_CTL0_CH2_AR_CACHE_Msk = 0x3c00000
	// Position of CH2_AW_CACHE field.
	DMAC_CH2_CTL0_CH2_AW_CACHE_Pos = 0x1a
	// Bit mask of CH2_AW_CACHE field.
	DMAC_CH2_CTL0_CH2_AW_CACHE_Msk = 0x3c000000
	// Position of CH2_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH2_CTL0_CH2_NONPOSTED_LASTWRITE_EN_Pos = 0x1e
	// Bit mask of CH2_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH2_CTL0_CH2_NONPOSTED_LASTWRITE_EN_Msk = 0x40000000
	// Bit CH2_NONPOSTED_LASTWRITE_EN.
	DMAC_CH2_CTL0_CH2_NONPOSTED_LASTWRITE_EN = 0x40000000

	// CH2_CTL1: NA
	// Position of CH2_AR_PROT field.
	DMAC_CH2_CTL1_CH2_AR_PROT_Pos = 0x0
	// Bit mask of CH2_AR_PROT field.
	DMAC_CH2_CTL1_CH2_AR_PROT_Msk = 0x7
	// Position of CH2_AW_PROT field.
	DMAC_CH2_CTL1_CH2_AW_PROT_Pos = 0x3
	// Bit mask of CH2_AW_PROT field.
	DMAC_CH2_CTL1_CH2_AW_PROT_Msk = 0x38
	// Position of CH2_ARLEN_EN field.
	DMAC_CH2_CTL1_CH2_ARLEN_EN_Pos = 0x6
	// Bit mask of CH2_ARLEN_EN field.
	DMAC_CH2_CTL1_CH2_ARLEN_EN_Msk = 0x40
	// Bit CH2_ARLEN_EN.
	DMAC_CH2_CTL1_CH2_ARLEN_EN = 0x40
	// Position of CH2_ARLEN field.
	DMAC_CH2_CTL1_CH2_ARLEN_Pos = 0x7
	// Bit mask of CH2_ARLEN field.
	DMAC_CH2_CTL1_CH2_ARLEN_Msk = 0x7f80
	// Position of CH2_AWLEN_EN field.
	DMAC_CH2_CTL1_CH2_AWLEN_EN_Pos = 0xf
	// Bit mask of CH2_AWLEN_EN field.
	DMAC_CH2_CTL1_CH2_AWLEN_EN_Msk = 0x8000
	// Bit CH2_AWLEN_EN.
	DMAC_CH2_CTL1_CH2_AWLEN_EN = 0x8000
	// Position of CH2_AWLEN field.
	DMAC_CH2_CTL1_CH2_AWLEN_Pos = 0x10
	// Bit mask of CH2_AWLEN field.
	DMAC_CH2_CTL1_CH2_AWLEN_Msk = 0xff0000
	// Position of CH2_SRC_STAT_EN field.
	DMAC_CH2_CTL1_CH2_SRC_STAT_EN_Pos = 0x18
	// Bit mask of CH2_SRC_STAT_EN field.
	DMAC_CH2_CTL1_CH2_SRC_STAT_EN_Msk = 0x1000000
	// Bit CH2_SRC_STAT_EN.
	DMAC_CH2_CTL1_CH2_SRC_STAT_EN = 0x1000000
	// Position of CH2_DST_STAT_EN field.
	DMAC_CH2_CTL1_CH2_DST_STAT_EN_Pos = 0x19
	// Bit mask of CH2_DST_STAT_EN field.
	DMAC_CH2_CTL1_CH2_DST_STAT_EN_Msk = 0x2000000
	// Bit CH2_DST_STAT_EN.
	DMAC_CH2_CTL1_CH2_DST_STAT_EN = 0x2000000
	// Position of CH2_IOC_BLKTFR field.
	DMAC_CH2_CTL1_CH2_IOC_BLKTFR_Pos = 0x1a
	// Bit mask of CH2_IOC_BLKTFR field.
	DMAC_CH2_CTL1_CH2_IOC_BLKTFR_Msk = 0x4000000
	// Bit CH2_IOC_BLKTFR.
	DMAC_CH2_CTL1_CH2_IOC_BLKTFR = 0x4000000
	// Position of CH2_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH2_CTL1_CH2_SHADOWREG_OR_LLI_LAST_Pos = 0x1e
	// Bit mask of CH2_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH2_CTL1_CH2_SHADOWREG_OR_LLI_LAST_Msk = 0x40000000
	// Bit CH2_SHADOWREG_OR_LLI_LAST.
	DMAC_CH2_CTL1_CH2_SHADOWREG_OR_LLI_LAST = 0x40000000
	// Position of CH2_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH2_CTL1_CH2_SHADOWREG_OR_LLI_VALID_Pos = 0x1f
	// Bit mask of CH2_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH2_CTL1_CH2_SHADOWREG_OR_LLI_VALID_Msk = 0x80000000
	// Bit CH2_SHADOWREG_OR_LLI_VALID.
	DMAC_CH2_CTL1_CH2_SHADOWREG_OR_LLI_VALID = 0x80000000

	// CH2_CFG0: NA
	// Position of CH2_SRC_MULTBLK_TYPE field.
	DMAC_CH2_CFG0_CH2_SRC_MULTBLK_TYPE_Pos = 0x0
	// Bit mask of CH2_SRC_MULTBLK_TYPE field.
	DMAC_CH2_CFG0_CH2_SRC_MULTBLK_TYPE_Msk = 0x3
	// Position of CH2_DST_MULTBLK_TYPE field.
	DMAC_CH2_CFG0_CH2_DST_MULTBLK_TYPE_Pos = 0x2
	// Bit mask of CH2_DST_MULTBLK_TYPE field.
	DMAC_CH2_CFG0_CH2_DST_MULTBLK_TYPE_Msk = 0xc
	// Position of CH2_RD_UID field.
	DMAC_CH2_CFG0_CH2_RD_UID_Pos = 0x12
	// Bit mask of CH2_RD_UID field.
	DMAC_CH2_CFG0_CH2_RD_UID_Msk = 0x3c0000
	// Position of CH2_WR_UID field.
	DMAC_CH2_CFG0_CH2_WR_UID_Pos = 0x19
	// Bit mask of CH2_WR_UID field.
	DMAC_CH2_CFG0_CH2_WR_UID_Msk = 0x1e000000

	// CH2_CFG1: NA
	// Position of CH2_TT_FC field.
	DMAC_CH2_CFG1_CH2_TT_FC_Pos = 0x0
	// Bit mask of CH2_TT_FC field.
	DMAC_CH2_CFG1_CH2_TT_FC_Msk = 0x7
	// Position of CH2_HS_SEL_SRC field.
	DMAC_CH2_CFG1_CH2_HS_SEL_SRC_Pos = 0x3
	// Bit mask of CH2_HS_SEL_SRC field.
	DMAC_CH2_CFG1_CH2_HS_SEL_SRC_Msk = 0x8
	// Bit CH2_HS_SEL_SRC.
	DMAC_CH2_CFG1_CH2_HS_SEL_SRC = 0x8
	// Position of CH2_HS_SEL_DST field.
	DMAC_CH2_CFG1_CH2_HS_SEL_DST_Pos = 0x4
	// Bit mask of CH2_HS_SEL_DST field.
	DMAC_CH2_CFG1_CH2_HS_SEL_DST_Msk = 0x10
	// Bit CH2_HS_SEL_DST.
	DMAC_CH2_CFG1_CH2_HS_SEL_DST = 0x10
	// Position of CH2_SRC_HWHS_POL field.
	DMAC_CH2_CFG1_CH2_SRC_HWHS_POL_Pos = 0x5
	// Bit mask of CH2_SRC_HWHS_POL field.
	DMAC_CH2_CFG1_CH2_SRC_HWHS_POL_Msk = 0x20
	// Bit CH2_SRC_HWHS_POL.
	DMAC_CH2_CFG1_CH2_SRC_HWHS_POL = 0x20
	// Position of CH2_DST_HWHS_POL field.
	DMAC_CH2_CFG1_CH2_DST_HWHS_POL_Pos = 0x6
	// Bit mask of CH2_DST_HWHS_POL field.
	DMAC_CH2_CFG1_CH2_DST_HWHS_POL_Msk = 0x40
	// Bit CH2_DST_HWHS_POL.
	DMAC_CH2_CFG1_CH2_DST_HWHS_POL = 0x40
	// Position of CH2_SRC_PER field.
	DMAC_CH2_CFG1_CH2_SRC_PER_Pos = 0x7
	// Bit mask of CH2_SRC_PER field.
	DMAC_CH2_CFG1_CH2_SRC_PER_Msk = 0x180
	// Position of CH2_DST_PER field.
	DMAC_CH2_CFG1_CH2_DST_PER_Pos = 0xc
	// Bit mask of CH2_DST_PER field.
	DMAC_CH2_CFG1_CH2_DST_PER_Msk = 0x3000
	// Position of CH2_CH_PRIOR field.
	DMAC_CH2_CFG1_CH2_CH_PRIOR_Pos = 0x11
	// Bit mask of CH2_CH_PRIOR field.
	DMAC_CH2_CFG1_CH2_CH_PRIOR_Msk = 0xe0000
	// Position of CH2_LOCK_CH field.
	DMAC_CH2_CFG1_CH2_LOCK_CH_Pos = 0x14
	// Bit mask of CH2_LOCK_CH field.
	DMAC_CH2_CFG1_CH2_LOCK_CH_Msk = 0x100000
	// Bit CH2_LOCK_CH.
	DMAC_CH2_CFG1_CH2_LOCK_CH = 0x100000
	// Position of CH2_LOCK_CH_L field.
	DMAC_CH2_CFG1_CH2_LOCK_CH_L_Pos = 0x15
	// Bit mask of CH2_LOCK_CH_L field.
	DMAC_CH2_CFG1_CH2_LOCK_CH_L_Msk = 0x600000
	// Position of CH2_SRC_OSR_LMT field.
	DMAC_CH2_CFG1_CH2_SRC_OSR_LMT_Pos = 0x17
	// Bit mask of CH2_SRC_OSR_LMT field.
	DMAC_CH2_CFG1_CH2_SRC_OSR_LMT_Msk = 0x7800000
	// Position of CH2_DST_OSR_LMT field.
	DMAC_CH2_CFG1_CH2_DST_OSR_LMT_Pos = 0x1b
	// Bit mask of CH2_DST_OSR_LMT field.
	DMAC_CH2_CFG1_CH2_DST_OSR_LMT_Msk = 0x78000000

	// CH2_LLP0: NA
	// Position of CH2_LMS field.
	DMAC_CH2_LLP0_CH2_LMS_Pos = 0x0
	// Bit mask of CH2_LMS field.
	DMAC_CH2_LLP0_CH2_LMS_Msk = 0x1
	// Bit CH2_LMS.
	DMAC_CH2_LLP0_CH2_LMS = 0x1
	// Position of CH2_LOC0 field.
	DMAC_CH2_LLP0_CH2_LOC0_Pos = 0x6
	// Bit mask of CH2_LOC0 field.
	DMAC_CH2_LLP0_CH2_LOC0_Msk = 0xffffffc0

	// CH2_LLP1: NA
	// Position of CH2_LOC1 field.
	DMAC_CH2_LLP1_CH2_LOC1_Pos = 0x0
	// Bit mask of CH2_LOC1 field.
	DMAC_CH2_LLP1_CH2_LOC1_Msk = 0xffffffff

	// CH2_STATUS0: NA
	// Position of CH2_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH2_STATUS0_CH2_CMPLTD_BLK_TFR_SIZE_Pos = 0x0
	// Bit mask of CH2_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH2_STATUS0_CH2_CMPLTD_BLK_TFR_SIZE_Msk = 0x3fffff

	// CH2_STATUS1: NA
	// Position of CH2_DATA_LEFT_IN_FIFO field.
	DMAC_CH2_STATUS1_CH2_DATA_LEFT_IN_FIFO_Pos = 0x0
	// Bit mask of CH2_DATA_LEFT_IN_FIFO field.
	DMAC_CH2_STATUS1_CH2_DATA_LEFT_IN_FIFO_Msk = 0x7fff

	// CH2_SWHSSRC0: NA
	// Position of CH2_SWHS_REQ_SRC field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_REQ_SRC_Pos = 0x0
	// Bit mask of CH2_SWHS_REQ_SRC field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_REQ_SRC_Msk = 0x1
	// Bit CH2_SWHS_REQ_SRC.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_REQ_SRC = 0x1
	// Position of CH2_SWHS_REQ_SRC_WE field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_REQ_SRC_WE_Pos = 0x1
	// Bit mask of CH2_SWHS_REQ_SRC_WE field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_REQ_SRC_WE_Msk = 0x2
	// Bit CH2_SWHS_REQ_SRC_WE.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_REQ_SRC_WE = 0x2
	// Position of CH2_SWHS_SGLREQ_SRC field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_Pos = 0x2
	// Bit mask of CH2_SWHS_SGLREQ_SRC field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_Msk = 0x4
	// Bit CH2_SWHS_SGLREQ_SRC.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC = 0x4
	// Position of CH2_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_WE_Pos = 0x3
	// Bit mask of CH2_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_WE_Msk = 0x8
	// Bit CH2_SWHS_SGLREQ_SRC_WE.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_SGLREQ_SRC_WE = 0x8
	// Position of CH2_SWHS_LST_SRC field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_LST_SRC_Pos = 0x4
	// Bit mask of CH2_SWHS_LST_SRC field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_LST_SRC_Msk = 0x10
	// Bit CH2_SWHS_LST_SRC.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_LST_SRC = 0x10
	// Position of CH2_SWHS_LST_SRC_WE field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_LST_SRC_WE_Pos = 0x5
	// Bit mask of CH2_SWHS_LST_SRC_WE field.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_LST_SRC_WE_Msk = 0x20
	// Bit CH2_SWHS_LST_SRC_WE.
	DMAC_CH2_SWHSSRC0_CH2_SWHS_LST_SRC_WE = 0x20

	// CH2_SWHSDST0: NA
	// Position of CH2_SWHS_REQ_DST field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_REQ_DST_Pos = 0x0
	// Bit mask of CH2_SWHS_REQ_DST field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_REQ_DST_Msk = 0x1
	// Bit CH2_SWHS_REQ_DST.
	DMAC_CH2_SWHSDST0_CH2_SWHS_REQ_DST = 0x1
	// Position of CH2_SWHS_REQ_DST_WE field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_REQ_DST_WE_Pos = 0x1
	// Bit mask of CH2_SWHS_REQ_DST_WE field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_REQ_DST_WE_Msk = 0x2
	// Bit CH2_SWHS_REQ_DST_WE.
	DMAC_CH2_SWHSDST0_CH2_SWHS_REQ_DST_WE = 0x2
	// Position of CH2_SWHS_SGLREQ_DST field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_Pos = 0x2
	// Bit mask of CH2_SWHS_SGLREQ_DST field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_Msk = 0x4
	// Bit CH2_SWHS_SGLREQ_DST.
	DMAC_CH2_SWHSDST0_CH2_SWHS_SGLREQ_DST = 0x4
	// Position of CH2_SWHS_SGLREQ_DST_WE field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_WE_Pos = 0x3
	// Bit mask of CH2_SWHS_SGLREQ_DST_WE field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_WE_Msk = 0x8
	// Bit CH2_SWHS_SGLREQ_DST_WE.
	DMAC_CH2_SWHSDST0_CH2_SWHS_SGLREQ_DST_WE = 0x8
	// Position of CH2_SWHS_LST_DST field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_LST_DST_Pos = 0x4
	// Bit mask of CH2_SWHS_LST_DST field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_LST_DST_Msk = 0x10
	// Bit CH2_SWHS_LST_DST.
	DMAC_CH2_SWHSDST0_CH2_SWHS_LST_DST = 0x10
	// Position of CH2_SWHS_LST_DST_WE field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_LST_DST_WE_Pos = 0x5
	// Bit mask of CH2_SWHS_LST_DST_WE field.
	DMAC_CH2_SWHSDST0_CH2_SWHS_LST_DST_WE_Msk = 0x20
	// Bit CH2_SWHS_LST_DST_WE.
	DMAC_CH2_SWHSDST0_CH2_SWHS_LST_DST_WE = 0x20

	// CH2_BLK_TFR_RESUMEREQ0: NA
	// Position of CH2_BLK_TFR_RESUMEREQ field.
	DMAC_CH2_BLK_TFR_RESUMEREQ0_CH2_BLK_TFR_RESUMEREQ_Pos = 0x0
	// Bit mask of CH2_BLK_TFR_RESUMEREQ field.
	DMAC_CH2_BLK_TFR_RESUMEREQ0_CH2_BLK_TFR_RESUMEREQ_Msk = 0x1
	// Bit CH2_BLK_TFR_RESUMEREQ.
	DMAC_CH2_BLK_TFR_RESUMEREQ0_CH2_BLK_TFR_RESUMEREQ = 0x1

	// CH2_AXI_ID0: NA
	// Position of CH2_AXI_READ_ID_SUFFIX field.
	DMAC_CH2_AXI_ID0_CH2_AXI_READ_ID_SUFFIX_Pos = 0x0
	// Bit mask of CH2_AXI_READ_ID_SUFFIX field.
	DMAC_CH2_AXI_ID0_CH2_AXI_READ_ID_SUFFIX_Msk = 0x1
	// Bit CH2_AXI_READ_ID_SUFFIX.
	DMAC_CH2_AXI_ID0_CH2_AXI_READ_ID_SUFFIX = 0x1
	// Position of CH2_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH2_AXI_ID0_CH2_AXI_WRITE_ID_SUFFIX_Pos = 0x10
	// Bit mask of CH2_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH2_AXI_ID0_CH2_AXI_WRITE_ID_SUFFIX_Msk = 0x10000
	// Bit CH2_AXI_WRITE_ID_SUFFIX.
	DMAC_CH2_AXI_ID0_CH2_AXI_WRITE_ID_SUFFIX = 0x10000

	// CH2_AXI_QOS0: NA
	// Position of CH2_AXI_AWQOS field.
	DMAC_CH2_AXI_QOS0_CH2_AXI_AWQOS_Pos = 0x0
	// Bit mask of CH2_AXI_AWQOS field.
	DMAC_CH2_AXI_QOS0_CH2_AXI_AWQOS_Msk = 0xf
	// Position of CH2_AXI_ARQOS field.
	DMAC_CH2_AXI_QOS0_CH2_AXI_ARQOS_Pos = 0x4
	// Bit mask of CH2_AXI_ARQOS field.
	DMAC_CH2_AXI_QOS0_CH2_AXI_ARQOS_Msk = 0xf0

	// CH2_SSTAT0: NA
	// Position of CH2_SSTAT field.
	DMAC_CH2_SSTAT0_CH2_SSTAT_Pos = 0x0
	// Bit mask of CH2_SSTAT field.
	DMAC_CH2_SSTAT0_CH2_SSTAT_Msk = 0xffffffff

	// CH2_DSTAT0: NA
	// Position of CH2_DSTAT field.
	DMAC_CH2_DSTAT0_CH2_DSTAT_Pos = 0x0
	// Bit mask of CH2_DSTAT field.
	DMAC_CH2_DSTAT0_CH2_DSTAT_Msk = 0xffffffff

	// CH2_SSTATAR0: NA
	// Position of CH2_SSTATAR0 field.
	DMAC_CH2_SSTATAR0_CH2_SSTATAR0_Pos = 0x0
	// Bit mask of CH2_SSTATAR0 field.
	DMAC_CH2_SSTATAR0_CH2_SSTATAR0_Msk = 0xffffffff

	// CH2_SSTATAR1: NA
	// Position of CH2_SSTATAR1 field.
	DMAC_CH2_SSTATAR1_CH2_SSTATAR1_Pos = 0x0
	// Bit mask of CH2_SSTATAR1 field.
	DMAC_CH2_SSTATAR1_CH2_SSTATAR1_Msk = 0xffffffff

	// CH2_DSTATAR0: NA
	// Position of CH2_DSTATAR0 field.
	DMAC_CH2_DSTATAR0_CH2_DSTATAR0_Pos = 0x0
	// Bit mask of CH2_DSTATAR0 field.
	DMAC_CH2_DSTATAR0_CH2_DSTATAR0_Msk = 0xffffffff

	// CH2_DSTATAR1: NA
	// Position of CH2_DSTATAR1 field.
	DMAC_CH2_DSTATAR1_CH2_DSTATAR1_Pos = 0x0
	// Bit mask of CH2_DSTATAR1 field.
	DMAC_CH2_DSTATAR1_CH2_DSTATAR1_Msk = 0xffffffff

	// CH2_INTSTATUS_ENABLE0: NA
	// Position of CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH2_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH2_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH2_ENABLE_DMA_TFR_DONE_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH2_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH2_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH2_ENABLE_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH2_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH2_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH2_ENABLE_DST_TRANSCOMP_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH2_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH2_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH2_ENABLE_SRC_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH2_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH2_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH2_ENABLE_DST_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH2_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH2_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH2_ENABLE_SRC_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH2_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH2_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH2_ENABLE_DST_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH2_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH2_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH2_ENABLE_CH_SUSPENDED_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH2_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH2_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH2_ENABLE_CH_DISABLED_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH2_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH2_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH2_ENABLE_CH_ABORTED_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSTAT = 0x80000000

	// CH2_INTSTATUS_ENABLE1: NA
	// Position of CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH2_INTSTATUS0: NA
	// Position of CH2_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH2_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH2_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH2_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH2_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH2_DMA_TFR_DONE_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH2_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH2_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH2_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH2_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH2_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH2_DST_TRANSCOMP_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH2_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH2_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH2_SRC_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH2_DST_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH2_DST_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH2_DST_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH2_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH2_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH2_SRC_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH2_DST_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH2_DST_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH2_DST_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH2_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH2_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH2_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH2_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH2_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH2_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH2_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH2_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH2_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH2_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH2_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH2_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH2_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH2_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH2_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH2_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH2_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH2_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH2_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH2_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH2_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH2_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH2_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH2_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH2_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH2_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH2_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH2_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH2_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH2_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH2_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH2_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH2_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH2_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH2_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH2_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH2_CH_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH2_CH_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH2_CH_SUSPENDED_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH2_CH_DISABLED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH2_CH_DISABLED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH2_CH_DISABLED_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH2_CH_ABORTED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH2_CH_ABORTED_INTSTAT field.
	DMAC_CH2_INTSTATUS0_CH2_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH2_CH_ABORTED_INTSTAT.
	DMAC_CH2_INTSTATUS0_CH2_CH_ABORTED_INTSTAT = 0x80000000

	// CH2_INTSTATUS1: NA
	// Position of CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH2_INTSTATUS1_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH2_INTSIGNAL_ENABLE0: NA
	// Position of CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Pos = 0x0
	// Bit mask of CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Msk = 0x1
	// Bit CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL = 0x1
	// Position of CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_Pos = 0x1
	// Bit mask of CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_Msk = 0x2
	// Bit CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL = 0x2
	// Position of CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Pos = 0x3
	// Bit mask of CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Msk = 0x8
	// Bit CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL = 0x8
	// Position of CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_Pos = 0x4
	// Bit mask of CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_Msk = 0x10
	// Bit CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL = 0x10
	// Position of CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_Pos = 0x5
	// Bit mask of CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_Msk = 0x20
	// Bit CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL = 0x20
	// Position of CH2_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_Pos = 0x6
	// Bit mask of CH2_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_Msk = 0x40
	// Bit CH2_ENABLE_DST_DEC_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL = 0x40
	// Position of CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_Pos = 0x7
	// Bit mask of CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_Msk = 0x80
	// Bit CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL = 0x80
	// Position of CH2_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_Pos = 0x8
	// Bit mask of CH2_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_Msk = 0x100
	// Bit CH2_ENABLE_DST_SLV_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL = 0x100
	// Position of CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Pos = 0x9
	// Bit mask of CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Msk = 0x200
	// Bit CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL = 0x200
	// Position of CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Pos = 0xa
	// Bit mask of CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Msk = 0x400
	// Bit CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL = 0x400
	// Position of CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Pos = 0xb
	// Bit mask of CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Msk = 0x800
	// Bit CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL = 0x800
	// Position of CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Pos = 0xc
	// Bit mask of CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Msk = 0x1000
	// Bit CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL = 0x1000
	// Position of CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Pos = 0xd
	// Bit mask of CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Msk = 0x2000
	// Bit CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL = 0x2000
	// Position of CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Pos = 0xe
	// Bit mask of CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Msk = 0x4000
	// Bit CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL = 0x4000
	// Position of CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Pos = 0x10
	// Bit mask of CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Msk = 0x10000
	// Bit CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL = 0x10000
	// Position of CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Pos = 0x11
	// Bit mask of CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Msk = 0x20000
	// Bit CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL = 0x20000
	// Position of CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Pos = 0x12
	// Bit mask of CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Msk = 0x40000
	// Bit CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL = 0x40000
	// Position of CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Pos = 0x13
	// Bit mask of CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Msk = 0x80000
	// Bit CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL = 0x80000
	// Position of CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Pos = 0x14
	// Bit mask of CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Msk = 0x100000
	// Bit CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL = 0x100000
	// Position of CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Pos = 0x15
	// Bit mask of CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Msk = 0x200000
	// Bit CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL = 0x200000
	// Position of CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Pos = 0x19
	// Bit mask of CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Msk = 0x2000000
	// Bit CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL = 0x2000000
	// Position of CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Pos = 0x1b
	// Bit mask of CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Msk = 0x8000000
	// Bit CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL = 0x8000000
	// Position of CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Pos = 0x1c
	// Bit mask of CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Msk = 0x10000000
	// Bit CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL = 0x10000000
	// Position of CH2_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_Pos = 0x1d
	// Bit mask of CH2_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_Msk = 0x20000000
	// Bit CH2_ENABLE_CH_SUSPENDED_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL = 0x20000000
	// Position of CH2_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSIGNAL_Pos = 0x1e
	// Bit mask of CH2_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSIGNAL_Msk = 0x40000000
	// Bit CH2_ENABLE_CH_DISABLED_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_DISABLED_INTSIGNAL = 0x40000000
	// Position of CH2_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSIGNAL_Pos = 0x1f
	// Bit mask of CH2_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSIGNAL_Msk = 0x80000000
	// Bit CH2_ENABLE_CH_ABORTED_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE0_CH2_ENABLE_CH_ABORTED_INTSIGNAL = 0x80000000

	// CH2_INTSIGNAL_ENABLE1: NA
	// Position of CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Pos = 0x0
	// Bit mask of CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Msk = 0x1
	// Bit CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL = 0x1
	// Position of CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Pos = 0x1
	// Bit mask of CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Msk = 0x2
	// Bit CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL = 0x2
	// Position of CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Pos = 0x2
	// Bit mask of CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Msk = 0x4
	// Bit CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL = 0x4
	// Position of CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Pos = 0x3
	// Bit mask of CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Msk = 0x8
	// Bit CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH2_INTSIGNAL_ENABLE1_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL = 0x8

	// CH2_INTCLEAR0: NA
	// Position of CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH2_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH2_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH2_CLEAR_DMA_TFR_DONE_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH2_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH2_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH2_CLEAR_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH2_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH2_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH2_CLEAR_DST_TRANSCOMP_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH2_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH2_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH2_CLEAR_SRC_DEC_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH2_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH2_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH2_CLEAR_DST_DEC_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH2_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH2_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH2_CLEAR_SRC_SLV_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH2_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH2_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH2_CLEAR_DST_SLV_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH2_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH2_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH2_CLEAR_CH_SUSPENDED_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH2_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH2_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH2_CLEAR_CH_DISABLED_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH2_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH2_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH2_CLEAR_CH_ABORTED_INTSTAT.
	DMAC_CH2_INTCLEAR0_CH2_CLEAR_CH_ABORTED_INTSTAT = 0x80000000

	// CH2_INTCLEAR1: NA
	// Position of CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH2_INTCLEAR1_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH3_SAR0: NA
	// Position of CH3_SAR0 field.
	DMAC_CH3_SAR0_CH3_SAR0_Pos = 0x0
	// Bit mask of CH3_SAR0 field.
	DMAC_CH3_SAR0_CH3_SAR0_Msk = 0xffffffff

	// CH3_SAR1: NA
	// Position of CH3_SAR1 field.
	DMAC_CH3_SAR1_CH3_SAR1_Pos = 0x0
	// Bit mask of CH3_SAR1 field.
	DMAC_CH3_SAR1_CH3_SAR1_Msk = 0xffffffff

	// CH3_DAR0: NA
	// Position of CH3_DAR0 field.
	DMAC_CH3_DAR0_CH3_DAR0_Pos = 0x0
	// Bit mask of CH3_DAR0 field.
	DMAC_CH3_DAR0_CH3_DAR0_Msk = 0xffffffff

	// CH3_DAR1: NA
	// Position of CH3_DAR1 field.
	DMAC_CH3_DAR1_CH3_DAR1_Pos = 0x0
	// Bit mask of CH3_DAR1 field.
	DMAC_CH3_DAR1_CH3_DAR1_Msk = 0xffffffff

	// CH3_BLOCK_TS0: NA
	// Position of CH3_BLOCK_TS field.
	DMAC_CH3_BLOCK_TS0_CH3_BLOCK_TS_Pos = 0x0
	// Bit mask of CH3_BLOCK_TS field.
	DMAC_CH3_BLOCK_TS0_CH3_BLOCK_TS_Msk = 0x3fffff

	// CH3_CTL0: NA
	// Position of CH3_SMS field.
	DMAC_CH3_CTL0_CH3_SMS_Pos = 0x0
	// Bit mask of CH3_SMS field.
	DMAC_CH3_CTL0_CH3_SMS_Msk = 0x1
	// Bit CH3_SMS.
	DMAC_CH3_CTL0_CH3_SMS = 0x1
	// Position of CH3_DMS field.
	DMAC_CH3_CTL0_CH3_DMS_Pos = 0x2
	// Bit mask of CH3_DMS field.
	DMAC_CH3_CTL0_CH3_DMS_Msk = 0x4
	// Bit CH3_DMS.
	DMAC_CH3_CTL0_CH3_DMS = 0x4
	// Position of CH3_SINC field.
	DMAC_CH3_CTL0_CH3_SINC_Pos = 0x4
	// Bit mask of CH3_SINC field.
	DMAC_CH3_CTL0_CH3_SINC_Msk = 0x10
	// Bit CH3_SINC.
	DMAC_CH3_CTL0_CH3_SINC = 0x10
	// Position of CH3_DINC field.
	DMAC_CH3_CTL0_CH3_DINC_Pos = 0x6
	// Bit mask of CH3_DINC field.
	DMAC_CH3_CTL0_CH3_DINC_Msk = 0x40
	// Bit CH3_DINC.
	DMAC_CH3_CTL0_CH3_DINC = 0x40
	// Position of CH3_SRC_TR_WIDTH field.
	DMAC_CH3_CTL0_CH3_SRC_TR_WIDTH_Pos = 0x8
	// Bit mask of CH3_SRC_TR_WIDTH field.
	DMAC_CH3_CTL0_CH3_SRC_TR_WIDTH_Msk = 0x700
	// Position of CH3_DST_TR_WIDTH field.
	DMAC_CH3_CTL0_CH3_DST_TR_WIDTH_Pos = 0xb
	// Bit mask of CH3_DST_TR_WIDTH field.
	DMAC_CH3_CTL0_CH3_DST_TR_WIDTH_Msk = 0x3800
	// Position of CH3_SRC_MSIZE field.
	DMAC_CH3_CTL0_CH3_SRC_MSIZE_Pos = 0xe
	// Bit mask of CH3_SRC_MSIZE field.
	DMAC_CH3_CTL0_CH3_SRC_MSIZE_Msk = 0x3c000
	// Position of CH3_DST_MSIZE field.
	DMAC_CH3_CTL0_CH3_DST_MSIZE_Pos = 0x12
	// Bit mask of CH3_DST_MSIZE field.
	DMAC_CH3_CTL0_CH3_DST_MSIZE_Msk = 0x3c0000
	// Position of CH3_AR_CACHE field.
	DMAC_CH3_CTL0_CH3_AR_CACHE_Pos = 0x16
	// Bit mask of CH3_AR_CACHE field.
	DMAC_CH3_CTL0_CH3_AR_CACHE_Msk = 0x3c00000
	// Position of CH3_AW_CACHE field.
	DMAC_CH3_CTL0_CH3_AW_CACHE_Pos = 0x1a
	// Bit mask of CH3_AW_CACHE field.
	DMAC_CH3_CTL0_CH3_AW_CACHE_Msk = 0x3c000000
	// Position of CH3_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH3_CTL0_CH3_NONPOSTED_LASTWRITE_EN_Pos = 0x1e
	// Bit mask of CH3_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH3_CTL0_CH3_NONPOSTED_LASTWRITE_EN_Msk = 0x40000000
	// Bit CH3_NONPOSTED_LASTWRITE_EN.
	DMAC_CH3_CTL0_CH3_NONPOSTED_LASTWRITE_EN = 0x40000000

	// CH3_CTL1: NA
	// Position of CH3_AR_PROT field.
	DMAC_CH3_CTL1_CH3_AR_PROT_Pos = 0x0
	// Bit mask of CH3_AR_PROT field.
	DMAC_CH3_CTL1_CH3_AR_PROT_Msk = 0x7
	// Position of CH3_AW_PROT field.
	DMAC_CH3_CTL1_CH3_AW_PROT_Pos = 0x3
	// Bit mask of CH3_AW_PROT field.
	DMAC_CH3_CTL1_CH3_AW_PROT_Msk = 0x38
	// Position of CH3_ARLEN_EN field.
	DMAC_CH3_CTL1_CH3_ARLEN_EN_Pos = 0x6
	// Bit mask of CH3_ARLEN_EN field.
	DMAC_CH3_CTL1_CH3_ARLEN_EN_Msk = 0x40
	// Bit CH3_ARLEN_EN.
	DMAC_CH3_CTL1_CH3_ARLEN_EN = 0x40
	// Position of CH3_ARLEN field.
	DMAC_CH3_CTL1_CH3_ARLEN_Pos = 0x7
	// Bit mask of CH3_ARLEN field.
	DMAC_CH3_CTL1_CH3_ARLEN_Msk = 0x7f80
	// Position of CH3_AWLEN_EN field.
	DMAC_CH3_CTL1_CH3_AWLEN_EN_Pos = 0xf
	// Bit mask of CH3_AWLEN_EN field.
	DMAC_CH3_CTL1_CH3_AWLEN_EN_Msk = 0x8000
	// Bit CH3_AWLEN_EN.
	DMAC_CH3_CTL1_CH3_AWLEN_EN = 0x8000
	// Position of CH3_AWLEN field.
	DMAC_CH3_CTL1_CH3_AWLEN_Pos = 0x10
	// Bit mask of CH3_AWLEN field.
	DMAC_CH3_CTL1_CH3_AWLEN_Msk = 0xff0000
	// Position of CH3_SRC_STAT_EN field.
	DMAC_CH3_CTL1_CH3_SRC_STAT_EN_Pos = 0x18
	// Bit mask of CH3_SRC_STAT_EN field.
	DMAC_CH3_CTL1_CH3_SRC_STAT_EN_Msk = 0x1000000
	// Bit CH3_SRC_STAT_EN.
	DMAC_CH3_CTL1_CH3_SRC_STAT_EN = 0x1000000
	// Position of CH3_DST_STAT_EN field.
	DMAC_CH3_CTL1_CH3_DST_STAT_EN_Pos = 0x19
	// Bit mask of CH3_DST_STAT_EN field.
	DMAC_CH3_CTL1_CH3_DST_STAT_EN_Msk = 0x2000000
	// Bit CH3_DST_STAT_EN.
	DMAC_CH3_CTL1_CH3_DST_STAT_EN = 0x2000000
	// Position of CH3_IOC_BLKTFR field.
	DMAC_CH3_CTL1_CH3_IOC_BLKTFR_Pos = 0x1a
	// Bit mask of CH3_IOC_BLKTFR field.
	DMAC_CH3_CTL1_CH3_IOC_BLKTFR_Msk = 0x4000000
	// Bit CH3_IOC_BLKTFR.
	DMAC_CH3_CTL1_CH3_IOC_BLKTFR = 0x4000000
	// Position of CH3_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH3_CTL1_CH3_SHADOWREG_OR_LLI_LAST_Pos = 0x1e
	// Bit mask of CH3_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH3_CTL1_CH3_SHADOWREG_OR_LLI_LAST_Msk = 0x40000000
	// Bit CH3_SHADOWREG_OR_LLI_LAST.
	DMAC_CH3_CTL1_CH3_SHADOWREG_OR_LLI_LAST = 0x40000000
	// Position of CH3_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH3_CTL1_CH3_SHADOWREG_OR_LLI_VALID_Pos = 0x1f
	// Bit mask of CH3_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH3_CTL1_CH3_SHADOWREG_OR_LLI_VALID_Msk = 0x80000000
	// Bit CH3_SHADOWREG_OR_LLI_VALID.
	DMAC_CH3_CTL1_CH3_SHADOWREG_OR_LLI_VALID = 0x80000000

	// CH3_CFG0: NA
	// Position of CH3_SRC_MULTBLK_TYPE field.
	DMAC_CH3_CFG0_CH3_SRC_MULTBLK_TYPE_Pos = 0x0
	// Bit mask of CH3_SRC_MULTBLK_TYPE field.
	DMAC_CH3_CFG0_CH3_SRC_MULTBLK_TYPE_Msk = 0x3
	// Position of CH3_DST_MULTBLK_TYPE field.
	DMAC_CH3_CFG0_CH3_DST_MULTBLK_TYPE_Pos = 0x2
	// Bit mask of CH3_DST_MULTBLK_TYPE field.
	DMAC_CH3_CFG0_CH3_DST_MULTBLK_TYPE_Msk = 0xc
	// Position of CH3_RD_UID field.
	DMAC_CH3_CFG0_CH3_RD_UID_Pos = 0x12
	// Bit mask of CH3_RD_UID field.
	DMAC_CH3_CFG0_CH3_RD_UID_Msk = 0x3c0000
	// Position of CH3_WR_UID field.
	DMAC_CH3_CFG0_CH3_WR_UID_Pos = 0x19
	// Bit mask of CH3_WR_UID field.
	DMAC_CH3_CFG0_CH3_WR_UID_Msk = 0x1e000000

	// CH3_CFG1: NA
	// Position of CH3_TT_FC field.
	DMAC_CH3_CFG1_CH3_TT_FC_Pos = 0x0
	// Bit mask of CH3_TT_FC field.
	DMAC_CH3_CFG1_CH3_TT_FC_Msk = 0x7
	// Position of CH3_HS_SEL_SRC field.
	DMAC_CH3_CFG1_CH3_HS_SEL_SRC_Pos = 0x3
	// Bit mask of CH3_HS_SEL_SRC field.
	DMAC_CH3_CFG1_CH3_HS_SEL_SRC_Msk = 0x8
	// Bit CH3_HS_SEL_SRC.
	DMAC_CH3_CFG1_CH3_HS_SEL_SRC = 0x8
	// Position of CH3_HS_SEL_DST field.
	DMAC_CH3_CFG1_CH3_HS_SEL_DST_Pos = 0x4
	// Bit mask of CH3_HS_SEL_DST field.
	DMAC_CH3_CFG1_CH3_HS_SEL_DST_Msk = 0x10
	// Bit CH3_HS_SEL_DST.
	DMAC_CH3_CFG1_CH3_HS_SEL_DST = 0x10
	// Position of CH3_SRC_HWHS_POL field.
	DMAC_CH3_CFG1_CH3_SRC_HWHS_POL_Pos = 0x5
	// Bit mask of CH3_SRC_HWHS_POL field.
	DMAC_CH3_CFG1_CH3_SRC_HWHS_POL_Msk = 0x20
	// Bit CH3_SRC_HWHS_POL.
	DMAC_CH3_CFG1_CH3_SRC_HWHS_POL = 0x20
	// Position of CH3_DST_HWHS_POL field.
	DMAC_CH3_CFG1_CH3_DST_HWHS_POL_Pos = 0x6
	// Bit mask of CH3_DST_HWHS_POL field.
	DMAC_CH3_CFG1_CH3_DST_HWHS_POL_Msk = 0x40
	// Bit CH3_DST_HWHS_POL.
	DMAC_CH3_CFG1_CH3_DST_HWHS_POL = 0x40
	// Position of CH3_SRC_PER field.
	DMAC_CH3_CFG1_CH3_SRC_PER_Pos = 0x7
	// Bit mask of CH3_SRC_PER field.
	DMAC_CH3_CFG1_CH3_SRC_PER_Msk = 0x180
	// Position of CH3_DST_PER field.
	DMAC_CH3_CFG1_CH3_DST_PER_Pos = 0xc
	// Bit mask of CH3_DST_PER field.
	DMAC_CH3_CFG1_CH3_DST_PER_Msk = 0x3000
	// Position of CH3_CH_PRIOR field.
	DMAC_CH3_CFG1_CH3_CH_PRIOR_Pos = 0x11
	// Bit mask of CH3_CH_PRIOR field.
	DMAC_CH3_CFG1_CH3_CH_PRIOR_Msk = 0xe0000
	// Position of CH3_LOCK_CH field.
	DMAC_CH3_CFG1_CH3_LOCK_CH_Pos = 0x14
	// Bit mask of CH3_LOCK_CH field.
	DMAC_CH3_CFG1_CH3_LOCK_CH_Msk = 0x100000
	// Bit CH3_LOCK_CH.
	DMAC_CH3_CFG1_CH3_LOCK_CH = 0x100000
	// Position of CH3_LOCK_CH_L field.
	DMAC_CH3_CFG1_CH3_LOCK_CH_L_Pos = 0x15
	// Bit mask of CH3_LOCK_CH_L field.
	DMAC_CH3_CFG1_CH3_LOCK_CH_L_Msk = 0x600000
	// Position of CH3_SRC_OSR_LMT field.
	DMAC_CH3_CFG1_CH3_SRC_OSR_LMT_Pos = 0x17
	// Bit mask of CH3_SRC_OSR_LMT field.
	DMAC_CH3_CFG1_CH3_SRC_OSR_LMT_Msk = 0x7800000
	// Position of CH3_DST_OSR_LMT field.
	DMAC_CH3_CFG1_CH3_DST_OSR_LMT_Pos = 0x1b
	// Bit mask of CH3_DST_OSR_LMT field.
	DMAC_CH3_CFG1_CH3_DST_OSR_LMT_Msk = 0x78000000

	// CH3_LLP0: NA
	// Position of CH3_LMS field.
	DMAC_CH3_LLP0_CH3_LMS_Pos = 0x0
	// Bit mask of CH3_LMS field.
	DMAC_CH3_LLP0_CH3_LMS_Msk = 0x1
	// Bit CH3_LMS.
	DMAC_CH3_LLP0_CH3_LMS = 0x1
	// Position of CH3_LOC0 field.
	DMAC_CH3_LLP0_CH3_LOC0_Pos = 0x6
	// Bit mask of CH3_LOC0 field.
	DMAC_CH3_LLP0_CH3_LOC0_Msk = 0xffffffc0

	// CH3_LLP1: NA
	// Position of CH3_LOC1 field.
	DMAC_CH3_LLP1_CH3_LOC1_Pos = 0x0
	// Bit mask of CH3_LOC1 field.
	DMAC_CH3_LLP1_CH3_LOC1_Msk = 0xffffffff

	// CH3_STATUS0: NA
	// Position of CH3_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH3_STATUS0_CH3_CMPLTD_BLK_TFR_SIZE_Pos = 0x0
	// Bit mask of CH3_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH3_STATUS0_CH3_CMPLTD_BLK_TFR_SIZE_Msk = 0x3fffff

	// CH3_STATUS1: NA
	// Position of CH3_DATA_LEFT_IN_FIFO field.
	DMAC_CH3_STATUS1_CH3_DATA_LEFT_IN_FIFO_Pos = 0x0
	// Bit mask of CH3_DATA_LEFT_IN_FIFO field.
	DMAC_CH3_STATUS1_CH3_DATA_LEFT_IN_FIFO_Msk = 0x7fff

	// CH3_SWHSSRC0: NA
	// Position of CH3_SWHS_REQ_SRC field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_REQ_SRC_Pos = 0x0
	// Bit mask of CH3_SWHS_REQ_SRC field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_REQ_SRC_Msk = 0x1
	// Bit CH3_SWHS_REQ_SRC.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_REQ_SRC = 0x1
	// Position of CH3_SWHS_REQ_SRC_WE field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_REQ_SRC_WE_Pos = 0x1
	// Bit mask of CH3_SWHS_REQ_SRC_WE field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_REQ_SRC_WE_Msk = 0x2
	// Bit CH3_SWHS_REQ_SRC_WE.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_REQ_SRC_WE = 0x2
	// Position of CH3_SWHS_SGLREQ_SRC field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_Pos = 0x2
	// Bit mask of CH3_SWHS_SGLREQ_SRC field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_Msk = 0x4
	// Bit CH3_SWHS_SGLREQ_SRC.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC = 0x4
	// Position of CH3_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_WE_Pos = 0x3
	// Bit mask of CH3_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_WE_Msk = 0x8
	// Bit CH3_SWHS_SGLREQ_SRC_WE.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_SGLREQ_SRC_WE = 0x8
	// Position of CH3_SWHS_LST_SRC field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_LST_SRC_Pos = 0x4
	// Bit mask of CH3_SWHS_LST_SRC field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_LST_SRC_Msk = 0x10
	// Bit CH3_SWHS_LST_SRC.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_LST_SRC = 0x10
	// Position of CH3_SWHS_LST_SRC_WE field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_LST_SRC_WE_Pos = 0x5
	// Bit mask of CH3_SWHS_LST_SRC_WE field.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_LST_SRC_WE_Msk = 0x20
	// Bit CH3_SWHS_LST_SRC_WE.
	DMAC_CH3_SWHSSRC0_CH3_SWHS_LST_SRC_WE = 0x20

	// CH3_SWHSDST0: NA
	// Position of CH3_SWHS_REQ_DST field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_REQ_DST_Pos = 0x0
	// Bit mask of CH3_SWHS_REQ_DST field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_REQ_DST_Msk = 0x1
	// Bit CH3_SWHS_REQ_DST.
	DMAC_CH3_SWHSDST0_CH3_SWHS_REQ_DST = 0x1
	// Position of CH3_SWHS_REQ_DST_WE field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_REQ_DST_WE_Pos = 0x1
	// Bit mask of CH3_SWHS_REQ_DST_WE field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_REQ_DST_WE_Msk = 0x2
	// Bit CH3_SWHS_REQ_DST_WE.
	DMAC_CH3_SWHSDST0_CH3_SWHS_REQ_DST_WE = 0x2
	// Position of CH3_SWHS_SGLREQ_DST field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_Pos = 0x2
	// Bit mask of CH3_SWHS_SGLREQ_DST field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_Msk = 0x4
	// Bit CH3_SWHS_SGLREQ_DST.
	DMAC_CH3_SWHSDST0_CH3_SWHS_SGLREQ_DST = 0x4
	// Position of CH3_SWHS_SGLREQ_DST_WE field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_WE_Pos = 0x3
	// Bit mask of CH3_SWHS_SGLREQ_DST_WE field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_WE_Msk = 0x8
	// Bit CH3_SWHS_SGLREQ_DST_WE.
	DMAC_CH3_SWHSDST0_CH3_SWHS_SGLREQ_DST_WE = 0x8
	// Position of CH3_SWHS_LST_DST field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_LST_DST_Pos = 0x4
	// Bit mask of CH3_SWHS_LST_DST field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_LST_DST_Msk = 0x10
	// Bit CH3_SWHS_LST_DST.
	DMAC_CH3_SWHSDST0_CH3_SWHS_LST_DST = 0x10
	// Position of CH3_SWHS_LST_DST_WE field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_LST_DST_WE_Pos = 0x5
	// Bit mask of CH3_SWHS_LST_DST_WE field.
	DMAC_CH3_SWHSDST0_CH3_SWHS_LST_DST_WE_Msk = 0x20
	// Bit CH3_SWHS_LST_DST_WE.
	DMAC_CH3_SWHSDST0_CH3_SWHS_LST_DST_WE = 0x20

	// CH3_BLK_TFR_RESUMEREQ0: NA
	// Position of CH3_BLK_TFR_RESUMEREQ field.
	DMAC_CH3_BLK_TFR_RESUMEREQ0_CH3_BLK_TFR_RESUMEREQ_Pos = 0x0
	// Bit mask of CH3_BLK_TFR_RESUMEREQ field.
	DMAC_CH3_BLK_TFR_RESUMEREQ0_CH3_BLK_TFR_RESUMEREQ_Msk = 0x1
	// Bit CH3_BLK_TFR_RESUMEREQ.
	DMAC_CH3_BLK_TFR_RESUMEREQ0_CH3_BLK_TFR_RESUMEREQ = 0x1

	// CH3_AXI_ID0: NA
	// Position of CH3_AXI_READ_ID_SUFFIX field.
	DMAC_CH3_AXI_ID0_CH3_AXI_READ_ID_SUFFIX_Pos = 0x0
	// Bit mask of CH3_AXI_READ_ID_SUFFIX field.
	DMAC_CH3_AXI_ID0_CH3_AXI_READ_ID_SUFFIX_Msk = 0x1
	// Bit CH3_AXI_READ_ID_SUFFIX.
	DMAC_CH3_AXI_ID0_CH3_AXI_READ_ID_SUFFIX = 0x1
	// Position of CH3_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH3_AXI_ID0_CH3_AXI_WRITE_ID_SUFFIX_Pos = 0x10
	// Bit mask of CH3_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH3_AXI_ID0_CH3_AXI_WRITE_ID_SUFFIX_Msk = 0x10000
	// Bit CH3_AXI_WRITE_ID_SUFFIX.
	DMAC_CH3_AXI_ID0_CH3_AXI_WRITE_ID_SUFFIX = 0x10000

	// CH3_AXI_QOS0: NA
	// Position of CH3_AXI_AWQOS field.
	DMAC_CH3_AXI_QOS0_CH3_AXI_AWQOS_Pos = 0x0
	// Bit mask of CH3_AXI_AWQOS field.
	DMAC_CH3_AXI_QOS0_CH3_AXI_AWQOS_Msk = 0xf
	// Position of CH3_AXI_ARQOS field.
	DMAC_CH3_AXI_QOS0_CH3_AXI_ARQOS_Pos = 0x4
	// Bit mask of CH3_AXI_ARQOS field.
	DMAC_CH3_AXI_QOS0_CH3_AXI_ARQOS_Msk = 0xf0

	// CH3_SSTAT0: NA
	// Position of CH3_SSTAT field.
	DMAC_CH3_SSTAT0_CH3_SSTAT_Pos = 0x0
	// Bit mask of CH3_SSTAT field.
	DMAC_CH3_SSTAT0_CH3_SSTAT_Msk = 0xffffffff

	// CH3_DSTAT0: NA
	// Position of CH3_DSTAT field.
	DMAC_CH3_DSTAT0_CH3_DSTAT_Pos = 0x0
	// Bit mask of CH3_DSTAT field.
	DMAC_CH3_DSTAT0_CH3_DSTAT_Msk = 0xffffffff

	// CH3_SSTATAR0: NA
	// Position of CH3_SSTATAR0 field.
	DMAC_CH3_SSTATAR0_CH3_SSTATAR0_Pos = 0x0
	// Bit mask of CH3_SSTATAR0 field.
	DMAC_CH3_SSTATAR0_CH3_SSTATAR0_Msk = 0xffffffff

	// CH3_SSTATAR1: NA
	// Position of CH3_SSTATAR1 field.
	DMAC_CH3_SSTATAR1_CH3_SSTATAR1_Pos = 0x0
	// Bit mask of CH3_SSTATAR1 field.
	DMAC_CH3_SSTATAR1_CH3_SSTATAR1_Msk = 0xffffffff

	// CH3_DSTATAR0: NA
	// Position of CH3_DSTATAR0 field.
	DMAC_CH3_DSTATAR0_CH3_DSTATAR0_Pos = 0x0
	// Bit mask of CH3_DSTATAR0 field.
	DMAC_CH3_DSTATAR0_CH3_DSTATAR0_Msk = 0xffffffff

	// CH3_DSTATAR1: NA
	// Position of CH3_DSTATAR1 field.
	DMAC_CH3_DSTATAR1_CH3_DSTATAR1_Pos = 0x0
	// Bit mask of CH3_DSTATAR1 field.
	DMAC_CH3_DSTATAR1_CH3_DSTATAR1_Msk = 0xffffffff

	// CH3_INTSTATUS_ENABLE0: NA
	// Position of CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH3_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH3_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH3_ENABLE_DMA_TFR_DONE_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH3_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH3_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH3_ENABLE_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH3_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH3_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH3_ENABLE_DST_TRANSCOMP_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH3_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH3_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH3_ENABLE_SRC_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH3_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH3_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH3_ENABLE_DST_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH3_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH3_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH3_ENABLE_SRC_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH3_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH3_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH3_ENABLE_DST_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH3_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH3_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH3_ENABLE_CH_SUSPENDED_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH3_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH3_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH3_ENABLE_CH_DISABLED_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH3_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH3_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH3_ENABLE_CH_ABORTED_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSTAT = 0x80000000

	// CH3_INTSTATUS_ENABLE1: NA
	// Position of CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH3_INTSTATUS0: NA
	// Position of CH3_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH3_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH3_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH3_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH3_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH3_DMA_TFR_DONE_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH3_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH3_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH3_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH3_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH3_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH3_DST_TRANSCOMP_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH3_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH3_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH3_SRC_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH3_DST_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH3_DST_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH3_DST_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH3_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH3_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH3_SRC_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH3_DST_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH3_DST_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH3_DST_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH3_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH3_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH3_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH3_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH3_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH3_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH3_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH3_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH3_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH3_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH3_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH3_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH3_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH3_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH3_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH3_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH3_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH3_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH3_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH3_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH3_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH3_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH3_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH3_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH3_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH3_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH3_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH3_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH3_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH3_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH3_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH3_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH3_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH3_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH3_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH3_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH3_CH_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH3_CH_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH3_CH_SUSPENDED_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH3_CH_DISABLED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH3_CH_DISABLED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH3_CH_DISABLED_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH3_CH_ABORTED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH3_CH_ABORTED_INTSTAT field.
	DMAC_CH3_INTSTATUS0_CH3_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH3_CH_ABORTED_INTSTAT.
	DMAC_CH3_INTSTATUS0_CH3_CH_ABORTED_INTSTAT = 0x80000000

	// CH3_INTSTATUS1: NA
	// Position of CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH3_INTSTATUS1_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH3_INTSIGNAL_ENABLE0: NA
	// Position of CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Pos = 0x0
	// Bit mask of CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Msk = 0x1
	// Bit CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL = 0x1
	// Position of CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_Pos = 0x1
	// Bit mask of CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_Msk = 0x2
	// Bit CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL = 0x2
	// Position of CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Pos = 0x3
	// Bit mask of CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Msk = 0x8
	// Bit CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL = 0x8
	// Position of CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_Pos = 0x4
	// Bit mask of CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_Msk = 0x10
	// Bit CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL = 0x10
	// Position of CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_Pos = 0x5
	// Bit mask of CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_Msk = 0x20
	// Bit CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL = 0x20
	// Position of CH3_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_Pos = 0x6
	// Bit mask of CH3_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_Msk = 0x40
	// Bit CH3_ENABLE_DST_DEC_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL = 0x40
	// Position of CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_Pos = 0x7
	// Bit mask of CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_Msk = 0x80
	// Bit CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL = 0x80
	// Position of CH3_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_Pos = 0x8
	// Bit mask of CH3_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_Msk = 0x100
	// Bit CH3_ENABLE_DST_SLV_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL = 0x100
	// Position of CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Pos = 0x9
	// Bit mask of CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Msk = 0x200
	// Bit CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL = 0x200
	// Position of CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Pos = 0xa
	// Bit mask of CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Msk = 0x400
	// Bit CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL = 0x400
	// Position of CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Pos = 0xb
	// Bit mask of CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Msk = 0x800
	// Bit CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL = 0x800
	// Position of CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Pos = 0xc
	// Bit mask of CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Msk = 0x1000
	// Bit CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL = 0x1000
	// Position of CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Pos = 0xd
	// Bit mask of CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Msk = 0x2000
	// Bit CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL = 0x2000
	// Position of CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Pos = 0xe
	// Bit mask of CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Msk = 0x4000
	// Bit CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL = 0x4000
	// Position of CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Pos = 0x10
	// Bit mask of CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Msk = 0x10000
	// Bit CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL = 0x10000
	// Position of CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Pos = 0x11
	// Bit mask of CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Msk = 0x20000
	// Bit CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL = 0x20000
	// Position of CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Pos = 0x12
	// Bit mask of CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Msk = 0x40000
	// Bit CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL = 0x40000
	// Position of CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Pos = 0x13
	// Bit mask of CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Msk = 0x80000
	// Bit CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL = 0x80000
	// Position of CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Pos = 0x14
	// Bit mask of CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Msk = 0x100000
	// Bit CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL = 0x100000
	// Position of CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Pos = 0x15
	// Bit mask of CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Msk = 0x200000
	// Bit CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL = 0x200000
	// Position of CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Pos = 0x19
	// Bit mask of CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Msk = 0x2000000
	// Bit CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL = 0x2000000
	// Position of CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Pos = 0x1b
	// Bit mask of CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Msk = 0x8000000
	// Bit CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL = 0x8000000
	// Position of CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Pos = 0x1c
	// Bit mask of CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Msk = 0x10000000
	// Bit CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL = 0x10000000
	// Position of CH3_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_Pos = 0x1d
	// Bit mask of CH3_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_Msk = 0x20000000
	// Bit CH3_ENABLE_CH_SUSPENDED_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL = 0x20000000
	// Position of CH3_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSIGNAL_Pos = 0x1e
	// Bit mask of CH3_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSIGNAL_Msk = 0x40000000
	// Bit CH3_ENABLE_CH_DISABLED_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_DISABLED_INTSIGNAL = 0x40000000
	// Position of CH3_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSIGNAL_Pos = 0x1f
	// Bit mask of CH3_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSIGNAL_Msk = 0x80000000
	// Bit CH3_ENABLE_CH_ABORTED_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE0_CH3_ENABLE_CH_ABORTED_INTSIGNAL = 0x80000000

	// CH3_INTSIGNAL_ENABLE1: NA
	// Position of CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Pos = 0x0
	// Bit mask of CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Msk = 0x1
	// Bit CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL = 0x1
	// Position of CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Pos = 0x1
	// Bit mask of CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Msk = 0x2
	// Bit CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL = 0x2
	// Position of CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Pos = 0x2
	// Bit mask of CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Msk = 0x4
	// Bit CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL = 0x4
	// Position of CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Pos = 0x3
	// Bit mask of CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Msk = 0x8
	// Bit CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH3_INTSIGNAL_ENABLE1_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL = 0x8

	// CH3_INTCLEAR0: NA
	// Position of CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH3_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH3_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH3_CLEAR_DMA_TFR_DONE_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH3_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH3_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH3_CLEAR_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH3_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH3_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH3_CLEAR_DST_TRANSCOMP_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH3_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH3_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH3_CLEAR_SRC_DEC_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH3_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH3_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH3_CLEAR_DST_DEC_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH3_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH3_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH3_CLEAR_SRC_SLV_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH3_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH3_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH3_CLEAR_DST_SLV_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH3_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH3_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH3_CLEAR_CH_SUSPENDED_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH3_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH3_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH3_CLEAR_CH_DISABLED_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH3_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH3_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH3_CLEAR_CH_ABORTED_INTSTAT.
	DMAC_CH3_INTCLEAR0_CH3_CLEAR_CH_ABORTED_INTSTAT = 0x80000000

	// CH3_INTCLEAR1: NA
	// Position of CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH3_INTCLEAR1_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH4_SAR0: NA
	// Position of CH4_SAR0 field.
	DMAC_CH4_SAR0_CH4_SAR0_Pos = 0x0
	// Bit mask of CH4_SAR0 field.
	DMAC_CH4_SAR0_CH4_SAR0_Msk = 0xffffffff

	// CH4_SAR1: NA
	// Position of CH4_SAR1 field.
	DMAC_CH4_SAR1_CH4_SAR1_Pos = 0x0
	// Bit mask of CH4_SAR1 field.
	DMAC_CH4_SAR1_CH4_SAR1_Msk = 0xffffffff

	// CH4_DAR0: NA
	// Position of CH4_DAR0 field.
	DMAC_CH4_DAR0_CH4_DAR0_Pos = 0x0
	// Bit mask of CH4_DAR0 field.
	DMAC_CH4_DAR0_CH4_DAR0_Msk = 0xffffffff

	// CH4_DAR1: NA
	// Position of CH4_DAR1 field.
	DMAC_CH4_DAR1_CH4_DAR1_Pos = 0x0
	// Bit mask of CH4_DAR1 field.
	DMAC_CH4_DAR1_CH4_DAR1_Msk = 0xffffffff

	// CH4_BLOCK_TS0: NA
	// Position of CH4_BLOCK_TS field.
	DMAC_CH4_BLOCK_TS0_CH4_BLOCK_TS_Pos = 0x0
	// Bit mask of CH4_BLOCK_TS field.
	DMAC_CH4_BLOCK_TS0_CH4_BLOCK_TS_Msk = 0x3fffff

	// CH4_CTL0: NA
	// Position of CH4_SMS field.
	DMAC_CH4_CTL0_CH4_SMS_Pos = 0x0
	// Bit mask of CH4_SMS field.
	DMAC_CH4_CTL0_CH4_SMS_Msk = 0x1
	// Bit CH4_SMS.
	DMAC_CH4_CTL0_CH4_SMS = 0x1
	// Position of CH4_DMS field.
	DMAC_CH4_CTL0_CH4_DMS_Pos = 0x2
	// Bit mask of CH4_DMS field.
	DMAC_CH4_CTL0_CH4_DMS_Msk = 0x4
	// Bit CH4_DMS.
	DMAC_CH4_CTL0_CH4_DMS = 0x4
	// Position of CH4_SINC field.
	DMAC_CH4_CTL0_CH4_SINC_Pos = 0x4
	// Bit mask of CH4_SINC field.
	DMAC_CH4_CTL0_CH4_SINC_Msk = 0x10
	// Bit CH4_SINC.
	DMAC_CH4_CTL0_CH4_SINC = 0x10
	// Position of CH4_DINC field.
	DMAC_CH4_CTL0_CH4_DINC_Pos = 0x6
	// Bit mask of CH4_DINC field.
	DMAC_CH4_CTL0_CH4_DINC_Msk = 0x40
	// Bit CH4_DINC.
	DMAC_CH4_CTL0_CH4_DINC = 0x40
	// Position of CH4_SRC_TR_WIDTH field.
	DMAC_CH4_CTL0_CH4_SRC_TR_WIDTH_Pos = 0x8
	// Bit mask of CH4_SRC_TR_WIDTH field.
	DMAC_CH4_CTL0_CH4_SRC_TR_WIDTH_Msk = 0x700
	// Position of CH4_DST_TR_WIDTH field.
	DMAC_CH4_CTL0_CH4_DST_TR_WIDTH_Pos = 0xb
	// Bit mask of CH4_DST_TR_WIDTH field.
	DMAC_CH4_CTL0_CH4_DST_TR_WIDTH_Msk = 0x3800
	// Position of CH4_SRC_MSIZE field.
	DMAC_CH4_CTL0_CH4_SRC_MSIZE_Pos = 0xe
	// Bit mask of CH4_SRC_MSIZE field.
	DMAC_CH4_CTL0_CH4_SRC_MSIZE_Msk = 0x3c000
	// Position of CH4_DST_MSIZE field.
	DMAC_CH4_CTL0_CH4_DST_MSIZE_Pos = 0x12
	// Bit mask of CH4_DST_MSIZE field.
	DMAC_CH4_CTL0_CH4_DST_MSIZE_Msk = 0x3c0000
	// Position of CH4_AR_CACHE field.
	DMAC_CH4_CTL0_CH4_AR_CACHE_Pos = 0x16
	// Bit mask of CH4_AR_CACHE field.
	DMAC_CH4_CTL0_CH4_AR_CACHE_Msk = 0x3c00000
	// Position of CH4_AW_CACHE field.
	DMAC_CH4_CTL0_CH4_AW_CACHE_Pos = 0x1a
	// Bit mask of CH4_AW_CACHE field.
	DMAC_CH4_CTL0_CH4_AW_CACHE_Msk = 0x3c000000
	// Position of CH4_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH4_CTL0_CH4_NONPOSTED_LASTWRITE_EN_Pos = 0x1e
	// Bit mask of CH4_NONPOSTED_LASTWRITE_EN field.
	DMAC_CH4_CTL0_CH4_NONPOSTED_LASTWRITE_EN_Msk = 0x40000000
	// Bit CH4_NONPOSTED_LASTWRITE_EN.
	DMAC_CH4_CTL0_CH4_NONPOSTED_LASTWRITE_EN = 0x40000000

	// CH4_CTL1: NA
	// Position of CH4_AR_PROT field.
	DMAC_CH4_CTL1_CH4_AR_PROT_Pos = 0x0
	// Bit mask of CH4_AR_PROT field.
	DMAC_CH4_CTL1_CH4_AR_PROT_Msk = 0x7
	// Position of CH4_AW_PROT field.
	DMAC_CH4_CTL1_CH4_AW_PROT_Pos = 0x3
	// Bit mask of CH4_AW_PROT field.
	DMAC_CH4_CTL1_CH4_AW_PROT_Msk = 0x38
	// Position of CH4_ARLEN_EN field.
	DMAC_CH4_CTL1_CH4_ARLEN_EN_Pos = 0x6
	// Bit mask of CH4_ARLEN_EN field.
	DMAC_CH4_CTL1_CH4_ARLEN_EN_Msk = 0x40
	// Bit CH4_ARLEN_EN.
	DMAC_CH4_CTL1_CH4_ARLEN_EN = 0x40
	// Position of CH4_ARLEN field.
	DMAC_CH4_CTL1_CH4_ARLEN_Pos = 0x7
	// Bit mask of CH4_ARLEN field.
	DMAC_CH4_CTL1_CH4_ARLEN_Msk = 0x7f80
	// Position of CH4_AWLEN_EN field.
	DMAC_CH4_CTL1_CH4_AWLEN_EN_Pos = 0xf
	// Bit mask of CH4_AWLEN_EN field.
	DMAC_CH4_CTL1_CH4_AWLEN_EN_Msk = 0x8000
	// Bit CH4_AWLEN_EN.
	DMAC_CH4_CTL1_CH4_AWLEN_EN = 0x8000
	// Position of CH4_AWLEN field.
	DMAC_CH4_CTL1_CH4_AWLEN_Pos = 0x10
	// Bit mask of CH4_AWLEN field.
	DMAC_CH4_CTL1_CH4_AWLEN_Msk = 0xff0000
	// Position of CH4_SRC_STAT_EN field.
	DMAC_CH4_CTL1_CH4_SRC_STAT_EN_Pos = 0x18
	// Bit mask of CH4_SRC_STAT_EN field.
	DMAC_CH4_CTL1_CH4_SRC_STAT_EN_Msk = 0x1000000
	// Bit CH4_SRC_STAT_EN.
	DMAC_CH4_CTL1_CH4_SRC_STAT_EN = 0x1000000
	// Position of CH4_DST_STAT_EN field.
	DMAC_CH4_CTL1_CH4_DST_STAT_EN_Pos = 0x19
	// Bit mask of CH4_DST_STAT_EN field.
	DMAC_CH4_CTL1_CH4_DST_STAT_EN_Msk = 0x2000000
	// Bit CH4_DST_STAT_EN.
	DMAC_CH4_CTL1_CH4_DST_STAT_EN = 0x2000000
	// Position of CH4_IOC_BLKTFR field.
	DMAC_CH4_CTL1_CH4_IOC_BLKTFR_Pos = 0x1a
	// Bit mask of CH4_IOC_BLKTFR field.
	DMAC_CH4_CTL1_CH4_IOC_BLKTFR_Msk = 0x4000000
	// Bit CH4_IOC_BLKTFR.
	DMAC_CH4_CTL1_CH4_IOC_BLKTFR = 0x4000000
	// Position of CH4_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH4_CTL1_CH4_SHADOWREG_OR_LLI_LAST_Pos = 0x1e
	// Bit mask of CH4_SHADOWREG_OR_LLI_LAST field.
	DMAC_CH4_CTL1_CH4_SHADOWREG_OR_LLI_LAST_Msk = 0x40000000
	// Bit CH4_SHADOWREG_OR_LLI_LAST.
	DMAC_CH4_CTL1_CH4_SHADOWREG_OR_LLI_LAST = 0x40000000
	// Position of CH4_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH4_CTL1_CH4_SHADOWREG_OR_LLI_VALID_Pos = 0x1f
	// Bit mask of CH4_SHADOWREG_OR_LLI_VALID field.
	DMAC_CH4_CTL1_CH4_SHADOWREG_OR_LLI_VALID_Msk = 0x80000000
	// Bit CH4_SHADOWREG_OR_LLI_VALID.
	DMAC_CH4_CTL1_CH4_SHADOWREG_OR_LLI_VALID = 0x80000000

	// CH4_CFG0: NA
	// Position of CH4_SRC_MULTBLK_TYPE field.
	DMAC_CH4_CFG0_CH4_SRC_MULTBLK_TYPE_Pos = 0x0
	// Bit mask of CH4_SRC_MULTBLK_TYPE field.
	DMAC_CH4_CFG0_CH4_SRC_MULTBLK_TYPE_Msk = 0x3
	// Position of CH4_DST_MULTBLK_TYPE field.
	DMAC_CH4_CFG0_CH4_DST_MULTBLK_TYPE_Pos = 0x2
	// Bit mask of CH4_DST_MULTBLK_TYPE field.
	DMAC_CH4_CFG0_CH4_DST_MULTBLK_TYPE_Msk = 0xc
	// Position of CH4_RD_UID field.
	DMAC_CH4_CFG0_CH4_RD_UID_Pos = 0x12
	// Bit mask of CH4_RD_UID field.
	DMAC_CH4_CFG0_CH4_RD_UID_Msk = 0x3c0000
	// Position of CH4_WR_UID field.
	DMAC_CH4_CFG0_CH4_WR_UID_Pos = 0x19
	// Bit mask of CH4_WR_UID field.
	DMAC_CH4_CFG0_CH4_WR_UID_Msk = 0x1e000000

	// CH4_CFG1: NA
	// Position of CH4_TT_FC field.
	DMAC_CH4_CFG1_CH4_TT_FC_Pos = 0x0
	// Bit mask of CH4_TT_FC field.
	DMAC_CH4_CFG1_CH4_TT_FC_Msk = 0x7
	// Position of CH4_HS_SEL_SRC field.
	DMAC_CH4_CFG1_CH4_HS_SEL_SRC_Pos = 0x3
	// Bit mask of CH4_HS_SEL_SRC field.
	DMAC_CH4_CFG1_CH4_HS_SEL_SRC_Msk = 0x8
	// Bit CH4_HS_SEL_SRC.
	DMAC_CH4_CFG1_CH4_HS_SEL_SRC = 0x8
	// Position of CH4_HS_SEL_DST field.
	DMAC_CH4_CFG1_CH4_HS_SEL_DST_Pos = 0x4
	// Bit mask of CH4_HS_SEL_DST field.
	DMAC_CH4_CFG1_CH4_HS_SEL_DST_Msk = 0x10
	// Bit CH4_HS_SEL_DST.
	DMAC_CH4_CFG1_CH4_HS_SEL_DST = 0x10
	// Position of CH4_SRC_HWHS_POL field.
	DMAC_CH4_CFG1_CH4_SRC_HWHS_POL_Pos = 0x5
	// Bit mask of CH4_SRC_HWHS_POL field.
	DMAC_CH4_CFG1_CH4_SRC_HWHS_POL_Msk = 0x20
	// Bit CH4_SRC_HWHS_POL.
	DMAC_CH4_CFG1_CH4_SRC_HWHS_POL = 0x20
	// Position of CH4_DST_HWHS_POL field.
	DMAC_CH4_CFG1_CH4_DST_HWHS_POL_Pos = 0x6
	// Bit mask of CH4_DST_HWHS_POL field.
	DMAC_CH4_CFG1_CH4_DST_HWHS_POL_Msk = 0x40
	// Bit CH4_DST_HWHS_POL.
	DMAC_CH4_CFG1_CH4_DST_HWHS_POL = 0x40
	// Position of CH4_SRC_PER field.
	DMAC_CH4_CFG1_CH4_SRC_PER_Pos = 0x7
	// Bit mask of CH4_SRC_PER field.
	DMAC_CH4_CFG1_CH4_SRC_PER_Msk = 0x180
	// Position of CH4_DST_PER field.
	DMAC_CH4_CFG1_CH4_DST_PER_Pos = 0xc
	// Bit mask of CH4_DST_PER field.
	DMAC_CH4_CFG1_CH4_DST_PER_Msk = 0x3000
	// Position of CH4_CH_PRIOR field.
	DMAC_CH4_CFG1_CH4_CH_PRIOR_Pos = 0x11
	// Bit mask of CH4_CH_PRIOR field.
	DMAC_CH4_CFG1_CH4_CH_PRIOR_Msk = 0xe0000
	// Position of CH4_LOCK_CH field.
	DMAC_CH4_CFG1_CH4_LOCK_CH_Pos = 0x14
	// Bit mask of CH4_LOCK_CH field.
	DMAC_CH4_CFG1_CH4_LOCK_CH_Msk = 0x100000
	// Bit CH4_LOCK_CH.
	DMAC_CH4_CFG1_CH4_LOCK_CH = 0x100000
	// Position of CH4_LOCK_CH_L field.
	DMAC_CH4_CFG1_CH4_LOCK_CH_L_Pos = 0x15
	// Bit mask of CH4_LOCK_CH_L field.
	DMAC_CH4_CFG1_CH4_LOCK_CH_L_Msk = 0x600000
	// Position of CH4_SRC_OSR_LMT field.
	DMAC_CH4_CFG1_CH4_SRC_OSR_LMT_Pos = 0x17
	// Bit mask of CH4_SRC_OSR_LMT field.
	DMAC_CH4_CFG1_CH4_SRC_OSR_LMT_Msk = 0x7800000
	// Position of CH4_DST_OSR_LMT field.
	DMAC_CH4_CFG1_CH4_DST_OSR_LMT_Pos = 0x1b
	// Bit mask of CH4_DST_OSR_LMT field.
	DMAC_CH4_CFG1_CH4_DST_OSR_LMT_Msk = 0x78000000

	// CH4_LLP0: NA
	// Position of CH4_LMS field.
	DMAC_CH4_LLP0_CH4_LMS_Pos = 0x0
	// Bit mask of CH4_LMS field.
	DMAC_CH4_LLP0_CH4_LMS_Msk = 0x1
	// Bit CH4_LMS.
	DMAC_CH4_LLP0_CH4_LMS = 0x1
	// Position of CH4_LOC0 field.
	DMAC_CH4_LLP0_CH4_LOC0_Pos = 0x6
	// Bit mask of CH4_LOC0 field.
	DMAC_CH4_LLP0_CH4_LOC0_Msk = 0xffffffc0

	// CH4_LLP1: NA
	// Position of CH4_LOC1 field.
	DMAC_CH4_LLP1_CH4_LOC1_Pos = 0x0
	// Bit mask of CH4_LOC1 field.
	DMAC_CH4_LLP1_CH4_LOC1_Msk = 0xffffffff

	// CH4_STATUS0: NA
	// Position of CH4_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH4_STATUS0_CH4_CMPLTD_BLK_TFR_SIZE_Pos = 0x0
	// Bit mask of CH4_CMPLTD_BLK_TFR_SIZE field.
	DMAC_CH4_STATUS0_CH4_CMPLTD_BLK_TFR_SIZE_Msk = 0x3fffff

	// CH4_STATUS1: NA
	// Position of CH4_DATA_LEFT_IN_FIFO field.
	DMAC_CH4_STATUS1_CH4_DATA_LEFT_IN_FIFO_Pos = 0x0
	// Bit mask of CH4_DATA_LEFT_IN_FIFO field.
	DMAC_CH4_STATUS1_CH4_DATA_LEFT_IN_FIFO_Msk = 0x7fff

	// CH4_SWHSSRC0: NA
	// Position of CH4_SWHS_REQ_SRC field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_REQ_SRC_Pos = 0x0
	// Bit mask of CH4_SWHS_REQ_SRC field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_REQ_SRC_Msk = 0x1
	// Bit CH4_SWHS_REQ_SRC.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_REQ_SRC = 0x1
	// Position of CH4_SWHS_REQ_SRC_WE field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_REQ_SRC_WE_Pos = 0x1
	// Bit mask of CH4_SWHS_REQ_SRC_WE field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_REQ_SRC_WE_Msk = 0x2
	// Bit CH4_SWHS_REQ_SRC_WE.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_REQ_SRC_WE = 0x2
	// Position of CH4_SWHS_SGLREQ_SRC field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_Pos = 0x2
	// Bit mask of CH4_SWHS_SGLREQ_SRC field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_Msk = 0x4
	// Bit CH4_SWHS_SGLREQ_SRC.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC = 0x4
	// Position of CH4_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_WE_Pos = 0x3
	// Bit mask of CH4_SWHS_SGLREQ_SRC_WE field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_WE_Msk = 0x8
	// Bit CH4_SWHS_SGLREQ_SRC_WE.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_SGLREQ_SRC_WE = 0x8
	// Position of CH4_SWHS_LST_SRC field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_LST_SRC_Pos = 0x4
	// Bit mask of CH4_SWHS_LST_SRC field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_LST_SRC_Msk = 0x10
	// Bit CH4_SWHS_LST_SRC.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_LST_SRC = 0x10
	// Position of CH4_SWHS_LST_SRC_WE field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_LST_SRC_WE_Pos = 0x5
	// Bit mask of CH4_SWHS_LST_SRC_WE field.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_LST_SRC_WE_Msk = 0x20
	// Bit CH4_SWHS_LST_SRC_WE.
	DMAC_CH4_SWHSSRC0_CH4_SWHS_LST_SRC_WE = 0x20

	// CH4_SWHSDST0: NA
	// Position of CH4_SWHS_REQ_DST field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_REQ_DST_Pos = 0x0
	// Bit mask of CH4_SWHS_REQ_DST field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_REQ_DST_Msk = 0x1
	// Bit CH4_SWHS_REQ_DST.
	DMAC_CH4_SWHSDST0_CH4_SWHS_REQ_DST = 0x1
	// Position of CH4_SWHS_REQ_DST_WE field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_REQ_DST_WE_Pos = 0x1
	// Bit mask of CH4_SWHS_REQ_DST_WE field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_REQ_DST_WE_Msk = 0x2
	// Bit CH4_SWHS_REQ_DST_WE.
	DMAC_CH4_SWHSDST0_CH4_SWHS_REQ_DST_WE = 0x2
	// Position of CH4_SWHS_SGLREQ_DST field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_Pos = 0x2
	// Bit mask of CH4_SWHS_SGLREQ_DST field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_Msk = 0x4
	// Bit CH4_SWHS_SGLREQ_DST.
	DMAC_CH4_SWHSDST0_CH4_SWHS_SGLREQ_DST = 0x4
	// Position of CH4_SWHS_SGLREQ_DST_WE field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_WE_Pos = 0x3
	// Bit mask of CH4_SWHS_SGLREQ_DST_WE field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_WE_Msk = 0x8
	// Bit CH4_SWHS_SGLREQ_DST_WE.
	DMAC_CH4_SWHSDST0_CH4_SWHS_SGLREQ_DST_WE = 0x8
	// Position of CH4_SWHS_LST_DST field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_LST_DST_Pos = 0x4
	// Bit mask of CH4_SWHS_LST_DST field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_LST_DST_Msk = 0x10
	// Bit CH4_SWHS_LST_DST.
	DMAC_CH4_SWHSDST0_CH4_SWHS_LST_DST = 0x10
	// Position of CH4_SWHS_LST_DST_WE field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_LST_DST_WE_Pos = 0x5
	// Bit mask of CH4_SWHS_LST_DST_WE field.
	DMAC_CH4_SWHSDST0_CH4_SWHS_LST_DST_WE_Msk = 0x20
	// Bit CH4_SWHS_LST_DST_WE.
	DMAC_CH4_SWHSDST0_CH4_SWHS_LST_DST_WE = 0x20

	// CH4_BLK_TFR_RESUMEREQ0: NA
	// Position of CH4_BLK_TFR_RESUMEREQ field.
	DMAC_CH4_BLK_TFR_RESUMEREQ0_CH4_BLK_TFR_RESUMEREQ_Pos = 0x0
	// Bit mask of CH4_BLK_TFR_RESUMEREQ field.
	DMAC_CH4_BLK_TFR_RESUMEREQ0_CH4_BLK_TFR_RESUMEREQ_Msk = 0x1
	// Bit CH4_BLK_TFR_RESUMEREQ.
	DMAC_CH4_BLK_TFR_RESUMEREQ0_CH4_BLK_TFR_RESUMEREQ = 0x1

	// CH4_AXI_ID0: NA
	// Position of CH4_AXI_READ_ID_SUFFIX field.
	DMAC_CH4_AXI_ID0_CH4_AXI_READ_ID_SUFFIX_Pos = 0x0
	// Bit mask of CH4_AXI_READ_ID_SUFFIX field.
	DMAC_CH4_AXI_ID0_CH4_AXI_READ_ID_SUFFIX_Msk = 0x1
	// Bit CH4_AXI_READ_ID_SUFFIX.
	DMAC_CH4_AXI_ID0_CH4_AXI_READ_ID_SUFFIX = 0x1
	// Position of CH4_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH4_AXI_ID0_CH4_AXI_WRITE_ID_SUFFIX_Pos = 0x10
	// Bit mask of CH4_AXI_WRITE_ID_SUFFIX field.
	DMAC_CH4_AXI_ID0_CH4_AXI_WRITE_ID_SUFFIX_Msk = 0x10000
	// Bit CH4_AXI_WRITE_ID_SUFFIX.
	DMAC_CH4_AXI_ID0_CH4_AXI_WRITE_ID_SUFFIX = 0x10000

	// CH4_AXI_QOS0: NA
	// Position of CH4_AXI_AWQOS field.
	DMAC_CH4_AXI_QOS0_CH4_AXI_AWQOS_Pos = 0x0
	// Bit mask of CH4_AXI_AWQOS field.
	DMAC_CH4_AXI_QOS0_CH4_AXI_AWQOS_Msk = 0xf
	// Position of CH4_AXI_ARQOS field.
	DMAC_CH4_AXI_QOS0_CH4_AXI_ARQOS_Pos = 0x4
	// Bit mask of CH4_AXI_ARQOS field.
	DMAC_CH4_AXI_QOS0_CH4_AXI_ARQOS_Msk = 0xf0

	// CH4_SSTAT0: NA
	// Position of CH4_SSTAT field.
	DMAC_CH4_SSTAT0_CH4_SSTAT_Pos = 0x0
	// Bit mask of CH4_SSTAT field.
	DMAC_CH4_SSTAT0_CH4_SSTAT_Msk = 0xffffffff

	// CH4_DSTAT0: NA
	// Position of CH4_DSTAT field.
	DMAC_CH4_DSTAT0_CH4_DSTAT_Pos = 0x0
	// Bit mask of CH4_DSTAT field.
	DMAC_CH4_DSTAT0_CH4_DSTAT_Msk = 0xffffffff

	// CH4_SSTATAR0: NA
	// Position of CH4_SSTATAR0 field.
	DMAC_CH4_SSTATAR0_CH4_SSTATAR0_Pos = 0x0
	// Bit mask of CH4_SSTATAR0 field.
	DMAC_CH4_SSTATAR0_CH4_SSTATAR0_Msk = 0xffffffff

	// CH4_SSTATAR1: NA
	// Position of CH4_SSTATAR1 field.
	DMAC_CH4_SSTATAR1_CH4_SSTATAR1_Pos = 0x0
	// Bit mask of CH4_SSTATAR1 field.
	DMAC_CH4_SSTATAR1_CH4_SSTATAR1_Msk = 0xffffffff

	// CH4_DSTATAR0: NA
	// Position of CH4_DSTATAR0 field.
	DMAC_CH4_DSTATAR0_CH4_DSTATAR0_Pos = 0x0
	// Bit mask of CH4_DSTATAR0 field.
	DMAC_CH4_DSTATAR0_CH4_DSTATAR0_Msk = 0xffffffff

	// CH4_DSTATAR1: NA
	// Position of CH4_DSTATAR1 field.
	DMAC_CH4_DSTATAR1_CH4_DSTATAR1_Pos = 0x0
	// Bit mask of CH4_DSTATAR1 field.
	DMAC_CH4_DSTATAR1_CH4_DSTATAR1_Msk = 0xffffffff

	// CH4_INTSTATUS_ENABLE0: NA
	// Position of CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH4_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH4_ENABLE_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH4_ENABLE_DMA_TFR_DONE_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH4_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH4_ENABLE_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH4_ENABLE_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH4_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH4_ENABLE_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH4_ENABLE_DST_TRANSCOMP_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH4_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH4_ENABLE_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH4_ENABLE_SRC_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH4_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH4_ENABLE_DST_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH4_ENABLE_DST_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH4_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH4_ENABLE_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH4_ENABLE_SRC_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH4_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH4_ENABLE_DST_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH4_ENABLE_DST_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH4_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH4_ENABLE_CH_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH4_ENABLE_CH_SUSPENDED_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH4_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH4_ENABLE_CH_DISABLED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH4_ENABLE_CH_DISABLED_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH4_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH4_ENABLE_CH_ABORTED_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH4_ENABLE_CH_ABORTED_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSTAT = 0x80000000

	// CH4_INTSTATUS_ENABLE1: NA
	// Position of CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH4_INTSTATUS0: NA
	// Position of CH4_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH4_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH4_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH4_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH4_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH4_DMA_TFR_DONE_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH4_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH4_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH4_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH4_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH4_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH4_DST_TRANSCOMP_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH4_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH4_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH4_SRC_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH4_DST_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH4_DST_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH4_DST_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH4_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH4_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH4_SRC_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH4_DST_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH4_DST_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH4_DST_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH4_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH4_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH4_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH4_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH4_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH4_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH4_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH4_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH4_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH4_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH4_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH4_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH4_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH4_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH4_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH4_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH4_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH4_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH4_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH4_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH4_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH4_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH4_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH4_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH4_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH4_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH4_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH4_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH4_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH4_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH4_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH4_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH4_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH4_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH4_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH4_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH4_CH_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH4_CH_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH4_CH_SUSPENDED_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH4_CH_DISABLED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH4_CH_DISABLED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH4_CH_DISABLED_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH4_CH_ABORTED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH4_CH_ABORTED_INTSTAT field.
	DMAC_CH4_INTSTATUS0_CH4_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH4_CH_ABORTED_INTSTAT.
	DMAC_CH4_INTSTATUS0_CH4_CH_ABORTED_INTSTAT = 0x80000000

	// CH4_INTSTATUS1: NA
	// Position of CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH4_INTSTATUS1_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8

	// CH4_INTSIGNAL_ENABLE0: NA
	// Position of CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Pos = 0x0
	// Bit mask of CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_Msk = 0x1
	// Bit CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL = 0x1
	// Position of CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_Pos = 0x1
	// Bit mask of CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_Msk = 0x2
	// Bit CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL = 0x2
	// Position of CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Pos = 0x3
	// Bit mask of CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_Msk = 0x8
	// Bit CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL = 0x8
	// Position of CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_Pos = 0x4
	// Bit mask of CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_Msk = 0x10
	// Bit CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL = 0x10
	// Position of CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_Pos = 0x5
	// Bit mask of CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_Msk = 0x20
	// Bit CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL = 0x20
	// Position of CH4_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_Pos = 0x6
	// Bit mask of CH4_ENABLE_DST_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_Msk = 0x40
	// Bit CH4_ENABLE_DST_DEC_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL = 0x40
	// Position of CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_Pos = 0x7
	// Bit mask of CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_Msk = 0x80
	// Bit CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL = 0x80
	// Position of CH4_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_Pos = 0x8
	// Bit mask of CH4_ENABLE_DST_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_Msk = 0x100
	// Bit CH4_ENABLE_DST_SLV_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL = 0x100
	// Position of CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Pos = 0x9
	// Bit mask of CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_Msk = 0x200
	// Bit CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL = 0x200
	// Position of CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Pos = 0xa
	// Bit mask of CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_Msk = 0x400
	// Bit CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL = 0x400
	// Position of CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Pos = 0xb
	// Bit mask of CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_Msk = 0x800
	// Bit CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL = 0x800
	// Position of CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Pos = 0xc
	// Bit mask of CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_Msk = 0x1000
	// Bit CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL = 0x1000
	// Position of CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Pos = 0xd
	// Bit mask of CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_Msk = 0x2000
	// Bit CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL = 0x2000
	// Position of CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Pos = 0xe
	// Bit mask of CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_Msk = 0x4000
	// Bit CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL = 0x4000
	// Position of CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Pos = 0x10
	// Bit mask of CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_Msk = 0x10000
	// Bit CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL = 0x10000
	// Position of CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Pos = 0x11
	// Bit mask of CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_Msk = 0x20000
	// Bit CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL = 0x20000
	// Position of CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Pos = 0x12
	// Bit mask of CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_Msk = 0x40000
	// Bit CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL = 0x40000
	// Position of CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Pos = 0x13
	// Bit mask of CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_Msk = 0x80000
	// Bit CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL = 0x80000
	// Position of CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Pos = 0x14
	// Bit mask of CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_Msk = 0x100000
	// Bit CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL = 0x100000
	// Position of CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Pos = 0x15
	// Bit mask of CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_Msk = 0x200000
	// Bit CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL = 0x200000
	// Position of CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Pos = 0x19
	// Bit mask of CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_Msk = 0x2000000
	// Bit CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL = 0x2000000
	// Position of CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Pos = 0x1b
	// Bit mask of CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_Msk = 0x8000000
	// Bit CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL = 0x8000000
	// Position of CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Pos = 0x1c
	// Bit mask of CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_Msk = 0x10000000
	// Bit CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL = 0x10000000
	// Position of CH4_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_Pos = 0x1d
	// Bit mask of CH4_ENABLE_CH_SUSPENDED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_Msk = 0x20000000
	// Bit CH4_ENABLE_CH_SUSPENDED_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL = 0x20000000
	// Position of CH4_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSIGNAL_Pos = 0x1e
	// Bit mask of CH4_ENABLE_CH_DISABLED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSIGNAL_Msk = 0x40000000
	// Bit CH4_ENABLE_CH_DISABLED_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_DISABLED_INTSIGNAL = 0x40000000
	// Position of CH4_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSIGNAL_Pos = 0x1f
	// Bit mask of CH4_ENABLE_CH_ABORTED_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSIGNAL_Msk = 0x80000000
	// Bit CH4_ENABLE_CH_ABORTED_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE0_CH4_ENABLE_CH_ABORTED_INTSIGNAL = 0x80000000

	// CH4_INTSIGNAL_ENABLE1: NA
	// Position of CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Pos = 0x0
	// Bit mask of CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_Msk = 0x1
	// Bit CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL = 0x1
	// Position of CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Pos = 0x1
	// Bit mask of CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_Msk = 0x2
	// Bit CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL = 0x2
	// Position of CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Pos = 0x2
	// Bit mask of CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_Msk = 0x4
	// Bit CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL = 0x4
	// Position of CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Pos = 0x3
	// Bit mask of CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL field.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_Msk = 0x8
	// Bit CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL.
	DMAC_CH4_INTSIGNAL_ENABLE1_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL = 0x8

	// CH4_INTCLEAR0: NA
	// Position of CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_Pos = 0x0
	// Bit mask of CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_Msk = 0x1
	// Bit CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT = 0x1
	// Position of CH4_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_Pos = 0x1
	// Bit mask of CH4_CLEAR_DMA_TFR_DONE_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_Msk = 0x2
	// Bit CH4_CLEAR_DMA_TFR_DONE_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DMA_TFR_DONE_INTSTAT = 0x2
	// Position of CH4_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_Pos = 0x3
	// Bit mask of CH4_CLEAR_SRC_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_Msk = 0x8
	// Bit CH4_CLEAR_SRC_TRANSCOMP_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT = 0x8
	// Position of CH4_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_Pos = 0x4
	// Bit mask of CH4_CLEAR_DST_TRANSCOMP_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_Msk = 0x10
	// Bit CH4_CLEAR_DST_TRANSCOMP_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_TRANSCOMP_INTSTAT = 0x10
	// Position of CH4_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_Pos = 0x5
	// Bit mask of CH4_CLEAR_SRC_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_Msk = 0x20
	// Bit CH4_CLEAR_SRC_DEC_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_DEC_ERR_INTSTAT = 0x20
	// Position of CH4_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_DEC_ERR_INTSTAT_Pos = 0x6
	// Bit mask of CH4_CLEAR_DST_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_DEC_ERR_INTSTAT_Msk = 0x40
	// Bit CH4_CLEAR_DST_DEC_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_DEC_ERR_INTSTAT = 0x40
	// Position of CH4_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_Pos = 0x7
	// Bit mask of CH4_CLEAR_SRC_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_Msk = 0x80
	// Bit CH4_CLEAR_SRC_SLV_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SRC_SLV_ERR_INTSTAT = 0x80
	// Position of CH4_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_SLV_ERR_INTSTAT_Pos = 0x8
	// Bit mask of CH4_CLEAR_DST_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_SLV_ERR_INTSTAT_Msk = 0x100
	// Bit CH4_CLEAR_DST_SLV_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_DST_SLV_ERR_INTSTAT = 0x100
	// Position of CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Pos = 0x9
	// Bit mask of CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_Msk = 0x200
	// Bit CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT = 0x200
	// Position of CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Pos = 0xa
	// Bit mask of CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_Msk = 0x400
	// Bit CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT = 0x400
	// Position of CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Pos = 0xb
	// Bit mask of CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_Msk = 0x800
	// Bit CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT = 0x800
	// Position of CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Pos = 0xc
	// Bit mask of CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_Msk = 0x1000
	// Bit CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT = 0x1000
	// Position of CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Pos = 0xd
	// Bit mask of CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_Msk = 0x2000
	// Bit CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT = 0x2000
	// Position of CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Pos = 0xe
	// Bit mask of CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_Msk = 0x4000
	// Bit CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT = 0x4000
	// Position of CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_Pos = 0x10
	// Bit mask of CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_Msk = 0x10000
	// Bit CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT = 0x10000
	// Position of CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Pos = 0x11
	// Bit mask of CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_Msk = 0x20000
	// Bit CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT = 0x20000
	// Position of CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Pos = 0x12
	// Bit mask of CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_Msk = 0x40000
	// Bit CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT = 0x40000
	// Position of CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Pos = 0x13
	// Bit mask of CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_Msk = 0x80000
	// Bit CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT = 0x80000
	// Position of CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Pos = 0x14
	// Bit mask of CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_Msk = 0x100000
	// Bit CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT = 0x100000
	// Position of CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Pos = 0x15
	// Bit mask of CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_Msk = 0x200000
	// Bit CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT = 0x200000
	// Position of CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Pos = 0x19
	// Bit mask of CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_Msk = 0x2000000
	// Bit CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT = 0x2000000
	// Position of CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_Pos = 0x1b
	// Bit mask of CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_Msk = 0x8000000
	// Bit CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT = 0x8000000
	// Position of CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Pos = 0x1c
	// Bit mask of CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_Msk = 0x10000000
	// Bit CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT = 0x10000000
	// Position of CH4_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_SUSPENDED_INTSTAT_Pos = 0x1d
	// Bit mask of CH4_CLEAR_CH_SUSPENDED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_SUSPENDED_INTSTAT_Msk = 0x20000000
	// Bit CH4_CLEAR_CH_SUSPENDED_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_SUSPENDED_INTSTAT = 0x20000000
	// Position of CH4_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_DISABLED_INTSTAT_Pos = 0x1e
	// Bit mask of CH4_CLEAR_CH_DISABLED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_DISABLED_INTSTAT_Msk = 0x40000000
	// Bit CH4_CLEAR_CH_DISABLED_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_DISABLED_INTSTAT = 0x40000000
	// Position of CH4_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_ABORTED_INTSTAT_Pos = 0x1f
	// Bit mask of CH4_CLEAR_CH_ABORTED_INTSTAT field.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_ABORTED_INTSTAT_Msk = 0x80000000
	// Bit CH4_CLEAR_CH_ABORTED_INTSTAT.
	DMAC_CH4_INTCLEAR0_CH4_CLEAR_CH_ABORTED_INTSTAT = 0x80000000

	// CH4_INTCLEAR1: NA
	// Position of CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Pos = 0x0
	// Bit mask of CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_Msk = 0x1
	// Bit CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT = 0x1
	// Position of CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Pos = 0x1
	// Bit mask of CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_Msk = 0x2
	// Bit CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT = 0x2
	// Position of CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Pos = 0x2
	// Bit mask of CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_Msk = 0x4
	// Bit CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT = 0x4
	// Position of CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Pos = 0x3
	// Bit mask of CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT field.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_Msk = 0x8
	// Bit CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT.
	DMAC_CH4_INTCLEAR1_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT = 0x8
)

// Constants for DS: Digital Signature
const (
	// SET_START: DS start control register
	// Position of SET_START field.
	DS_SET_START_SET_START_Pos = 0x0
	// Bit mask of SET_START field.
	DS_SET_START_SET_START_Msk = 0x1
	// Bit SET_START.
	DS_SET_START_SET_START = 0x1

	// SET_CONTINUE: DS continue control register
	// Position of SET_CONTINUE field.
	DS_SET_CONTINUE_SET_CONTINUE_Pos = 0x0
	// Bit mask of SET_CONTINUE field.
	DS_SET_CONTINUE_SET_CONTINUE_Msk = 0x1
	// Bit SET_CONTINUE.
	DS_SET_CONTINUE_SET_CONTINUE = 0x1

	// SET_FINISH: DS finish control register
	// Position of SET_FINISH field.
	DS_SET_FINISH_SET_FINISH_Pos = 0x0
	// Bit mask of SET_FINISH field.
	DS_SET_FINISH_SET_FINISH_Msk = 0x1
	// Bit SET_FINISH.
	DS_SET_FINISH_SET_FINISH = 0x1

	// QUERY_BUSY: DS query busy register
	// Position of QUERY_BUSY field.
	DS_QUERY_BUSY_QUERY_BUSY_Pos = 0x0
	// Bit mask of QUERY_BUSY field.
	DS_QUERY_BUSY_QUERY_BUSY_Msk = 0x1
	// Bit QUERY_BUSY.
	DS_QUERY_BUSY_QUERY_BUSY = 0x1

	// QUERY_KEY_WRONG: DS query key-wrong counter register
	// Position of QUERY_KEY_WRONG field.
	DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Pos = 0x0
	// Bit mask of QUERY_KEY_WRONG field.
	DS_QUERY_KEY_WRONG_QUERY_KEY_WRONG_Msk = 0xf

	// QUERY_CHECK: DS query check result register
	// Position of MD_ERROR field.
	DS_QUERY_CHECK_MD_ERROR_Pos = 0x0
	// Bit mask of MD_ERROR field.
	DS_QUERY_CHECK_MD_ERROR_Msk = 0x1
	// Bit MD_ERROR.
	DS_QUERY_CHECK_MD_ERROR = 0x1
	// Position of PADDING_BAD field.
	DS_QUERY_CHECK_PADDING_BAD_Pos = 0x1
	// Bit mask of PADDING_BAD field.
	DS_QUERY_CHECK_PADDING_BAD_Msk = 0x2
	// Bit PADDING_BAD.
	DS_QUERY_CHECK_PADDING_BAD = 0x2

	// DATE: DS version control register
	// Position of DATE field.
	DS_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	DS_DATE_DATE_Msk = 0x3fffffff
)

// Constants for MIPI_DSI_BRIDGE: MIPI Camera Interface Bridge
const (
	// CLK_EN: dsi bridge clk control register
	// Position of CLK_EN field.
	DSI_BRG_CLK_EN_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	DSI_BRG_CLK_EN_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	DSI_BRG_CLK_EN_CLK_EN = 0x1

	// EN: dsi bridge en register
	// Position of DSI_EN field.
	DSI_BRG_EN_DSI_EN_Pos = 0x0
	// Bit mask of DSI_EN field.
	DSI_BRG_EN_DSI_EN_Msk = 0x1
	// Bit DSI_EN.
	DSI_BRG_EN_DSI_EN = 0x1

	// DMA_REQ_CFG: dsi bridge dma burst len register
	// Position of DMA_BURST_LEN field.
	DSI_BRG_DMA_REQ_CFG_DMA_BURST_LEN_Pos = 0x0
	// Bit mask of DMA_BURST_LEN field.
	DSI_BRG_DMA_REQ_CFG_DMA_BURST_LEN_Msk = 0xfff

	// RAW_NUM_CFG: dsi bridge raw number control register
	// Position of RAW_NUM_TOTAL field.
	DSI_BRG_RAW_NUM_CFG_RAW_NUM_TOTAL_Pos = 0x0
	// Bit mask of RAW_NUM_TOTAL field.
	DSI_BRG_RAW_NUM_CFG_RAW_NUM_TOTAL_Msk = 0x3fffff
	// Position of UNALIGN_64BIT_EN field.
	DSI_BRG_RAW_NUM_CFG_UNALIGN_64BIT_EN_Pos = 0x16
	// Bit mask of UNALIGN_64BIT_EN field.
	DSI_BRG_RAW_NUM_CFG_UNALIGN_64BIT_EN_Msk = 0x400000
	// Bit UNALIGN_64BIT_EN.
	DSI_BRG_RAW_NUM_CFG_UNALIGN_64BIT_EN = 0x400000
	// Position of RAW_NUM_TOTAL_SET field.
	DSI_BRG_RAW_NUM_CFG_RAW_NUM_TOTAL_SET_Pos = 0x1f
	// Bit mask of RAW_NUM_TOTAL_SET field.
	DSI_BRG_RAW_NUM_CFG_RAW_NUM_TOTAL_SET_Msk = 0x80000000
	// Bit RAW_NUM_TOTAL_SET.
	DSI_BRG_RAW_NUM_CFG_RAW_NUM_TOTAL_SET = 0x80000000

	// RAW_BUF_CREDIT_CTL: dsi bridge credit register
	// Position of CREDIT_THRD field.
	DSI_BRG_RAW_BUF_CREDIT_CTL_CREDIT_THRD_Pos = 0x0
	// Bit mask of CREDIT_THRD field.
	DSI_BRG_RAW_BUF_CREDIT_CTL_CREDIT_THRD_Msk = 0x7fff
	// Position of CREDIT_BURST_THRD field.
	DSI_BRG_RAW_BUF_CREDIT_CTL_CREDIT_BURST_THRD_Pos = 0x10
	// Bit mask of CREDIT_BURST_THRD field.
	DSI_BRG_RAW_BUF_CREDIT_CTL_CREDIT_BURST_THRD_Msk = 0x7fff0000
	// Position of CREDIT_RESET field.
	DSI_BRG_RAW_BUF_CREDIT_CTL_CREDIT_RESET_Pos = 0x1f
	// Bit mask of CREDIT_RESET field.
	DSI_BRG_RAW_BUF_CREDIT_CTL_CREDIT_RESET_Msk = 0x80000000
	// Bit CREDIT_RESET.
	DSI_BRG_RAW_BUF_CREDIT_CTL_CREDIT_RESET = 0x80000000

	// FIFO_FLOW_STATUS: dsi bridge raw buffer depth register
	// Position of RAW_BUF_DEPTH field.
	DSI_BRG_FIFO_FLOW_STATUS_RAW_BUF_DEPTH_Pos = 0x0
	// Bit mask of RAW_BUF_DEPTH field.
	DSI_BRG_FIFO_FLOW_STATUS_RAW_BUF_DEPTH_Msk = 0x3fff

	// PIXEL_TYPE: dsi bridge dpi type control register
	// Position of RAW_TYPE field.
	DSI_BRG_PIXEL_TYPE_RAW_TYPE_Pos = 0x0
	// Bit mask of RAW_TYPE field.
	DSI_BRG_PIXEL_TYPE_RAW_TYPE_Msk = 0xf
	// Position of DPI_CONFIG field.
	DSI_BRG_PIXEL_TYPE_DPI_CONFIG_Pos = 0x4
	// Bit mask of DPI_CONFIG field.
	DSI_BRG_PIXEL_TYPE_DPI_CONFIG_Msk = 0x30
	// Position of DATA_IN_TYPE field.
	DSI_BRG_PIXEL_TYPE_DATA_IN_TYPE_Pos = 0x6
	// Bit mask of DATA_IN_TYPE field.
	DSI_BRG_PIXEL_TYPE_DATA_IN_TYPE_Msk = 0x40
	// Bit DATA_IN_TYPE.
	DSI_BRG_PIXEL_TYPE_DATA_IN_TYPE = 0x40

	// DMA_BLOCK_INTERVAL: dsi bridge dma block interval control register
	// Position of DMA_BLOCK_SLOT field.
	DSI_BRG_DMA_BLOCK_INTERVAL_DMA_BLOCK_SLOT_Pos = 0x0
	// Bit mask of DMA_BLOCK_SLOT field.
	DSI_BRG_DMA_BLOCK_INTERVAL_DMA_BLOCK_SLOT_Msk = 0x3ff
	// Position of DMA_BLOCK_INTERVAL field.
	DSI_BRG_DMA_BLOCK_INTERVAL_DMA_BLOCK_INTERVAL_Pos = 0xa
	// Bit mask of DMA_BLOCK_INTERVAL field.
	DSI_BRG_DMA_BLOCK_INTERVAL_DMA_BLOCK_INTERVAL_Msk = 0xffffc00
	// Position of RAW_NUM_TOTAL_AUTO_RELOAD field.
	DSI_BRG_DMA_BLOCK_INTERVAL_RAW_NUM_TOTAL_AUTO_RELOAD_Pos = 0x1c
	// Bit mask of RAW_NUM_TOTAL_AUTO_RELOAD field.
	DSI_BRG_DMA_BLOCK_INTERVAL_RAW_NUM_TOTAL_AUTO_RELOAD_Msk = 0x10000000
	// Bit RAW_NUM_TOTAL_AUTO_RELOAD.
	DSI_BRG_DMA_BLOCK_INTERVAL_RAW_NUM_TOTAL_AUTO_RELOAD = 0x10000000
	// Position of EN field.
	DSI_BRG_DMA_BLOCK_INTERVAL_EN_Pos = 0x1d
	// Bit mask of EN field.
	DSI_BRG_DMA_BLOCK_INTERVAL_EN_Msk = 0x20000000
	// Bit EN.
	DSI_BRG_DMA_BLOCK_INTERVAL_EN = 0x20000000

	// DMA_REQ_INTERVAL: dsi bridge dma req interval control register
	// Position of DMA_REQ_INTERVAL field.
	DSI_BRG_DMA_REQ_INTERVAL_DMA_REQ_INTERVAL_Pos = 0x0
	// Bit mask of DMA_REQ_INTERVAL field.
	DSI_BRG_DMA_REQ_INTERVAL_DMA_REQ_INTERVAL_Msk = 0xffff

	// DPI_LCD_CTL: dsi bridge dpi signal control register
	// Position of DPISHUTDN field.
	DSI_BRG_DPI_LCD_CTL_DPISHUTDN_Pos = 0x0
	// Bit mask of DPISHUTDN field.
	DSI_BRG_DPI_LCD_CTL_DPISHUTDN_Msk = 0x1
	// Bit DPISHUTDN.
	DSI_BRG_DPI_LCD_CTL_DPISHUTDN = 0x1
	// Position of DPICOLORM field.
	DSI_BRG_DPI_LCD_CTL_DPICOLORM_Pos = 0x1
	// Bit mask of DPICOLORM field.
	DSI_BRG_DPI_LCD_CTL_DPICOLORM_Msk = 0x2
	// Bit DPICOLORM.
	DSI_BRG_DPI_LCD_CTL_DPICOLORM = 0x2
	// Position of DPIUPDATECFG field.
	DSI_BRG_DPI_LCD_CTL_DPIUPDATECFG_Pos = 0x2
	// Bit mask of DPIUPDATECFG field.
	DSI_BRG_DPI_LCD_CTL_DPIUPDATECFG_Msk = 0x4
	// Bit DPIUPDATECFG.
	DSI_BRG_DPI_LCD_CTL_DPIUPDATECFG = 0x4

	// DPI_RSV_DPI_DATA: dsi bridge dpi reserved data register
	// Position of DPI_RSV_DATA field.
	DSI_BRG_DPI_RSV_DPI_DATA_DPI_RSV_DATA_Pos = 0x0
	// Bit mask of DPI_RSV_DATA field.
	DSI_BRG_DPI_RSV_DPI_DATA_DPI_RSV_DATA_Msk = 0x3fffffff

	// DPI_V_CFG0: dsi bridge dpi v config register 0
	// Position of VTOTAL field.
	DSI_BRG_DPI_V_CFG0_VTOTAL_Pos = 0x0
	// Bit mask of VTOTAL field.
	DSI_BRG_DPI_V_CFG0_VTOTAL_Msk = 0xfff
	// Position of VDISP field.
	DSI_BRG_DPI_V_CFG0_VDISP_Pos = 0x10
	// Bit mask of VDISP field.
	DSI_BRG_DPI_V_CFG0_VDISP_Msk = 0xfff0000

	// DPI_V_CFG1: dsi bridge dpi v config register 1
	// Position of VBANK field.
	DSI_BRG_DPI_V_CFG1_VBANK_Pos = 0x0
	// Bit mask of VBANK field.
	DSI_BRG_DPI_V_CFG1_VBANK_Msk = 0xfff
	// Position of VSYNC field.
	DSI_BRG_DPI_V_CFG1_VSYNC_Pos = 0x10
	// Bit mask of VSYNC field.
	DSI_BRG_DPI_V_CFG1_VSYNC_Msk = 0xfff0000

	// DPI_H_CFG0: dsi bridge dpi h config register 0
	// Position of HTOTAL field.
	DSI_BRG_DPI_H_CFG0_HTOTAL_Pos = 0x0
	// Bit mask of HTOTAL field.
	DSI_BRG_DPI_H_CFG0_HTOTAL_Msk = 0xfff
	// Position of HDISP field.
	DSI_BRG_DPI_H_CFG0_HDISP_Pos = 0x10
	// Bit mask of HDISP field.
	DSI_BRG_DPI_H_CFG0_HDISP_Msk = 0xfff0000

	// DPI_H_CFG1: dsi bridge dpi h config register 1
	// Position of HBANK field.
	DSI_BRG_DPI_H_CFG1_HBANK_Pos = 0x0
	// Bit mask of HBANK field.
	DSI_BRG_DPI_H_CFG1_HBANK_Msk = 0xfff
	// Position of HSYNC field.
	DSI_BRG_DPI_H_CFG1_HSYNC_Pos = 0x10
	// Bit mask of HSYNC field.
	DSI_BRG_DPI_H_CFG1_HSYNC_Msk = 0xfff0000

	// DPI_MISC_CONFIG: dsi_bridge dpi misc config register
	// Position of DPI_EN field.
	DSI_BRG_DPI_MISC_CONFIG_DPI_EN_Pos = 0x0
	// Bit mask of DPI_EN field.
	DSI_BRG_DPI_MISC_CONFIG_DPI_EN_Msk = 0x1
	// Bit DPI_EN.
	DSI_BRG_DPI_MISC_CONFIG_DPI_EN = 0x1
	// Position of FIFO_UNDERRUN_DISCARD_VCNT field.
	DSI_BRG_DPI_MISC_CONFIG_FIFO_UNDERRUN_DISCARD_VCNT_Pos = 0x4
	// Bit mask of FIFO_UNDERRUN_DISCARD_VCNT field.
	DSI_BRG_DPI_MISC_CONFIG_FIFO_UNDERRUN_DISCARD_VCNT_Msk = 0xfff0

	// DPI_CONFIG_UPDATE: dsi_bridge dpi config update register
	// Position of DPI_CONFIG_UPDATE field.
	DSI_BRG_DPI_CONFIG_UPDATE_DPI_CONFIG_UPDATE_Pos = 0x0
	// Bit mask of DPI_CONFIG_UPDATE field.
	DSI_BRG_DPI_CONFIG_UPDATE_DPI_CONFIG_UPDATE_Msk = 0x1
	// Bit DPI_CONFIG_UPDATE.
	DSI_BRG_DPI_CONFIG_UPDATE_DPI_CONFIG_UPDATE = 0x1

	// INT_ENA: dsi_bridge interrupt enable register
	// Position of UNDERRUN_INT_ENA field.
	DSI_BRG_INT_ENA_UNDERRUN_INT_ENA_Pos = 0x0
	// Bit mask of UNDERRUN_INT_ENA field.
	DSI_BRG_INT_ENA_UNDERRUN_INT_ENA_Msk = 0x1
	// Bit UNDERRUN_INT_ENA.
	DSI_BRG_INT_ENA_UNDERRUN_INT_ENA = 0x1

	// INT_CLR: dsi_bridge interrupt clear register
	// Position of UNDERRUN_INT_CLR field.
	DSI_BRG_INT_CLR_UNDERRUN_INT_CLR_Pos = 0x0
	// Bit mask of UNDERRUN_INT_CLR field.
	DSI_BRG_INT_CLR_UNDERRUN_INT_CLR_Msk = 0x1
	// Bit UNDERRUN_INT_CLR.
	DSI_BRG_INT_CLR_UNDERRUN_INT_CLR = 0x1

	// INT_RAW: dsi_bridge raw interrupt register
	// Position of UNDERRUN_INT_RAW field.
	DSI_BRG_INT_RAW_UNDERRUN_INT_RAW_Pos = 0x0
	// Bit mask of UNDERRUN_INT_RAW field.
	DSI_BRG_INT_RAW_UNDERRUN_INT_RAW_Msk = 0x1
	// Bit UNDERRUN_INT_RAW.
	DSI_BRG_INT_RAW_UNDERRUN_INT_RAW = 0x1

	// INT_ST: dsi_bridge masked interrupt register
	// Position of UNDERRUN_INT_ST field.
	DSI_BRG_INT_ST_UNDERRUN_INT_ST_Pos = 0x0
	// Bit mask of UNDERRUN_INT_ST field.
	DSI_BRG_INT_ST_UNDERRUN_INT_ST_Msk = 0x1
	// Bit UNDERRUN_INT_ST.
	DSI_BRG_INT_ST_UNDERRUN_INT_ST = 0x1

	// HOST_BIST_CTL: dsi_bridge host bist control register
	// Position of BISTOK field.
	DSI_BRG_HOST_BIST_CTL_BISTOK_Pos = 0x0
	// Bit mask of BISTOK field.
	DSI_BRG_HOST_BIST_CTL_BISTOK_Msk = 0x1
	// Bit BISTOK.
	DSI_BRG_HOST_BIST_CTL_BISTOK = 0x1
	// Position of BISTON field.
	DSI_BRG_HOST_BIST_CTL_BISTON_Pos = 0x1
	// Bit mask of BISTON field.
	DSI_BRG_HOST_BIST_CTL_BISTON_Msk = 0x2
	// Bit BISTON.
	DSI_BRG_HOST_BIST_CTL_BISTON = 0x2

	// HOST_TRIGGER_REV: dsi_bridge host trigger reverse control register
	// Position of TX_TRIGGER_REV_EN field.
	DSI_BRG_HOST_TRIGGER_REV_TX_TRIGGER_REV_EN_Pos = 0x0
	// Bit mask of TX_TRIGGER_REV_EN field.
	DSI_BRG_HOST_TRIGGER_REV_TX_TRIGGER_REV_EN_Msk = 0x1
	// Bit TX_TRIGGER_REV_EN.
	DSI_BRG_HOST_TRIGGER_REV_TX_TRIGGER_REV_EN = 0x1
	// Position of RX_TRIGGER_REV_EN field.
	DSI_BRG_HOST_TRIGGER_REV_RX_TRIGGER_REV_EN_Pos = 0x1
	// Bit mask of RX_TRIGGER_REV_EN field.
	DSI_BRG_HOST_TRIGGER_REV_RX_TRIGGER_REV_EN_Msk = 0x2
	// Bit RX_TRIGGER_REV_EN.
	DSI_BRG_HOST_TRIGGER_REV_RX_TRIGGER_REV_EN = 0x2

	// BLK_RAW_NUM_CFG: dsi_bridge block raw number control register
	// Position of BLK_RAW_NUM_TOTAL field.
	DSI_BRG_BLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_Pos = 0x0
	// Bit mask of BLK_RAW_NUM_TOTAL field.
	DSI_BRG_BLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_Msk = 0x3fffff
	// Position of BLK_RAW_NUM_TOTAL_SET field.
	DSI_BRG_BLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_SET_Pos = 0x1f
	// Bit mask of BLK_RAW_NUM_TOTAL_SET field.
	DSI_BRG_BLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_SET_Msk = 0x80000000
	// Bit BLK_RAW_NUM_TOTAL_SET.
	DSI_BRG_BLK_RAW_NUM_CFG_BLK_RAW_NUM_TOTAL_SET = 0x80000000

	// DMA_FRAME_INTERVAL: dsi_bridge dam frame interval control register
	// Position of DMA_FRAME_SLOT field.
	DSI_BRG_DMA_FRAME_INTERVAL_DMA_FRAME_SLOT_Pos = 0x0
	// Bit mask of DMA_FRAME_SLOT field.
	DSI_BRG_DMA_FRAME_INTERVAL_DMA_FRAME_SLOT_Msk = 0x3ff
	// Position of DMA_FRAME_INTERVAL field.
	DSI_BRG_DMA_FRAME_INTERVAL_DMA_FRAME_INTERVAL_Pos = 0xa
	// Bit mask of DMA_FRAME_INTERVAL field.
	DSI_BRG_DMA_FRAME_INTERVAL_DMA_FRAME_INTERVAL_Msk = 0xffffc00
	// Position of DMA_MULTIBLK_EN field.
	DSI_BRG_DMA_FRAME_INTERVAL_DMA_MULTIBLK_EN_Pos = 0x1c
	// Bit mask of DMA_MULTIBLK_EN field.
	DSI_BRG_DMA_FRAME_INTERVAL_DMA_MULTIBLK_EN_Msk = 0x10000000
	// Bit DMA_MULTIBLK_EN.
	DSI_BRG_DMA_FRAME_INTERVAL_DMA_MULTIBLK_EN = 0x10000000
	// Position of EN field.
	DSI_BRG_DMA_FRAME_INTERVAL_EN_Pos = 0x1d
	// Bit mask of EN field.
	DSI_BRG_DMA_FRAME_INTERVAL_EN_Msk = 0x20000000
	// Bit EN.
	DSI_BRG_DMA_FRAME_INTERVAL_EN = 0x20000000

	// MEM_AUX_CTRL: dsi_bridge mem aux control register
	// Position of DSI_MEM_AUX_CTRL field.
	DSI_BRG_MEM_AUX_CTRL_DSI_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of DSI_MEM_AUX_CTRL field.
	DSI_BRG_MEM_AUX_CTRL_DSI_MEM_AUX_CTRL_Msk = 0x3fff

	// RDN_ECO_CS: dsi_bridge rdn eco cs register
	// Position of RDN_ECO_EN field.
	DSI_BRG_RDN_ECO_CS_RDN_ECO_EN_Pos = 0x0
	// Bit mask of RDN_ECO_EN field.
	DSI_BRG_RDN_ECO_CS_RDN_ECO_EN_Msk = 0x1
	// Bit RDN_ECO_EN.
	DSI_BRG_RDN_ECO_CS_RDN_ECO_EN = 0x1
	// Position of RDN_ECO_RESULT field.
	DSI_BRG_RDN_ECO_CS_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of RDN_ECO_RESULT field.
	DSI_BRG_RDN_ECO_CS_RDN_ECO_RESULT_Msk = 0x2
	// Bit RDN_ECO_RESULT.
	DSI_BRG_RDN_ECO_CS_RDN_ECO_RESULT = 0x2

	// RDN_ECO_LOW: dsi_bridge rdn eco all low register
	// Position of RDN_ECO_LOW field.
	DSI_BRG_RDN_ECO_LOW_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of RDN_ECO_LOW field.
	DSI_BRG_RDN_ECO_LOW_RDN_ECO_LOW_Msk = 0xffffffff

	// RDN_ECO_HIGH: dsi_bridge rdn eco all high register
	// Position of RDN_ECO_HIGH field.
	DSI_BRG_RDN_ECO_HIGH_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of RDN_ECO_HIGH field.
	DSI_BRG_RDN_ECO_HIGH_RDN_ECO_HIGH_Msk = 0xffffffff

	// HOST_CTRL: dsi_bridge host control register
	// Position of DSI_CFG_REF_CLK_EN field.
	DSI_BRG_HOST_CTRL_DSI_CFG_REF_CLK_EN_Pos = 0x0
	// Bit mask of DSI_CFG_REF_CLK_EN field.
	DSI_BRG_HOST_CTRL_DSI_CFG_REF_CLK_EN_Msk = 0x1
	// Bit DSI_CFG_REF_CLK_EN.
	DSI_BRG_HOST_CTRL_DSI_CFG_REF_CLK_EN = 0x1

	// MEM_CLK_CTRL: dsi_bridge mem force on control register
	// Position of DSI_BRIDGE_MEM_CLK_FORCE_ON field.
	DSI_BRG_MEM_CLK_CTRL_DSI_BRIDGE_MEM_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of DSI_BRIDGE_MEM_CLK_FORCE_ON field.
	DSI_BRG_MEM_CLK_CTRL_DSI_BRIDGE_MEM_CLK_FORCE_ON_Msk = 0x1
	// Bit DSI_BRIDGE_MEM_CLK_FORCE_ON.
	DSI_BRG_MEM_CLK_CTRL_DSI_BRIDGE_MEM_CLK_FORCE_ON = 0x1
	// Position of DSI_MEM_CLK_FORCE_ON field.
	DSI_BRG_MEM_CLK_CTRL_DSI_MEM_CLK_FORCE_ON_Pos = 0x1
	// Bit mask of DSI_MEM_CLK_FORCE_ON field.
	DSI_BRG_MEM_CLK_CTRL_DSI_MEM_CLK_FORCE_ON_Msk = 0x2
	// Bit DSI_MEM_CLK_FORCE_ON.
	DSI_BRG_MEM_CLK_CTRL_DSI_MEM_CLK_FORCE_ON = 0x2

	// DMA_FLOW_CTRL: dsi_bridge dma flow controller register
	// Position of DSI_DMA_FLOW_CONTROLLER field.
	DSI_BRG_DMA_FLOW_CTRL_DSI_DMA_FLOW_CONTROLLER_Pos = 0x0
	// Bit mask of DSI_DMA_FLOW_CONTROLLER field.
	DSI_BRG_DMA_FLOW_CTRL_DSI_DMA_FLOW_CONTROLLER_Msk = 0x1
	// Bit DSI_DMA_FLOW_CONTROLLER.
	DSI_BRG_DMA_FLOW_CTRL_DSI_DMA_FLOW_CONTROLLER = 0x1
	// Position of DMA_FLOW_MULTIBLK_NUM field.
	DSI_BRG_DMA_FLOW_CTRL_DMA_FLOW_MULTIBLK_NUM_Pos = 0x4
	// Bit mask of DMA_FLOW_MULTIBLK_NUM field.
	DSI_BRG_DMA_FLOW_CTRL_DMA_FLOW_MULTIBLK_NUM_Msk = 0xf0

	// RAW_BUF_ALMOST_EMPTY_THRD: dsi_bridge buffer empty threshold register
	// Position of DSI_RAW_BUF_ALMOST_EMPTY_THRD field.
	DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_DSI_RAW_BUF_ALMOST_EMPTY_THRD_Pos = 0x0
	// Bit mask of DSI_RAW_BUF_ALMOST_EMPTY_THRD field.
	DSI_BRG_RAW_BUF_ALMOST_EMPTY_THRD_DSI_RAW_BUF_ALMOST_EMPTY_THRD_Msk = 0x7ff

	// YUV_CFG: dsi_bridge yuv format config register
	// Position of PROTOCAL field.
	DSI_BRG_YUV_CFG_PROTOCAL_Pos = 0x0
	// Bit mask of PROTOCAL field.
	DSI_BRG_YUV_CFG_PROTOCAL_Msk = 0x1
	// Bit PROTOCAL.
	DSI_BRG_YUV_CFG_PROTOCAL = 0x1
	// Position of YUV_PIX_ENDIAN field.
	DSI_BRG_YUV_CFG_YUV_PIX_ENDIAN_Pos = 0x1
	// Bit mask of YUV_PIX_ENDIAN field.
	DSI_BRG_YUV_CFG_YUV_PIX_ENDIAN_Msk = 0x2
	// Bit YUV_PIX_ENDIAN.
	DSI_BRG_YUV_CFG_YUV_PIX_ENDIAN = 0x2
	// Position of YUV422_FORMAT field.
	DSI_BRG_YUV_CFG_YUV422_FORMAT_Pos = 0x2
	// Bit mask of YUV422_FORMAT field.
	DSI_BRG_YUV_CFG_YUV422_FORMAT_Msk = 0xc

	// PHY_LP_LOOPBACK_CTRL: dsi phy lp_loopback test ctrl
	// Position of PHY_LP_TXDATAESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_1_Pos = 0x0
	// Bit mask of PHY_LP_TXDATAESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_1_Msk = 0xff
	// Position of PHY_LP_TXREQUESTESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_1_Pos = 0x8
	// Bit mask of PHY_LP_TXREQUESTESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_1_Msk = 0x100
	// Bit PHY_LP_TXREQUESTESC_1.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_1 = 0x100
	// Position of PHY_LP_TXVALIDESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_1_Pos = 0x9
	// Bit mask of PHY_LP_TXVALIDESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_1_Msk = 0x200
	// Bit PHY_LP_TXVALIDESC_1.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_1 = 0x200
	// Position of PHY_LP_TXLPDTESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_1_Pos = 0xa
	// Bit mask of PHY_LP_TXLPDTESC_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_1_Msk = 0x400
	// Bit PHY_LP_TXLPDTESC_1.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_1 = 0x400
	// Position of PHY_LP_BASEDIR_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_1_Pos = 0xb
	// Bit mask of PHY_LP_BASEDIR_1 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_1_Msk = 0x800
	// Bit PHY_LP_BASEDIR_1.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_1 = 0x800
	// Position of PHY_LP_TXDATAESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_0_Pos = 0x10
	// Bit mask of PHY_LP_TXDATAESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXDATAESC_0_Msk = 0xff0000
	// Position of PHY_LP_TXREQUESTESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_0_Pos = 0x18
	// Bit mask of PHY_LP_TXREQUESTESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_0_Msk = 0x1000000
	// Bit PHY_LP_TXREQUESTESC_0.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXREQUESTESC_0 = 0x1000000
	// Position of PHY_LP_TXVALIDESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_0_Pos = 0x19
	// Bit mask of PHY_LP_TXVALIDESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_0_Msk = 0x2000000
	// Bit PHY_LP_TXVALIDESC_0.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXVALIDESC_0 = 0x2000000
	// Position of PHY_LP_TXLPDTESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_0_Pos = 0x1a
	// Bit mask of PHY_LP_TXLPDTESC_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_0_Msk = 0x4000000
	// Bit PHY_LP_TXLPDTESC_0.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_TXLPDTESC_0 = 0x4000000
	// Position of PHY_LP_BASEDIR_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_0_Pos = 0x1b
	// Bit mask of PHY_LP_BASEDIR_0 field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_0_Msk = 0x8000000
	// Bit PHY_LP_BASEDIR_0.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_BASEDIR_0 = 0x8000000
	// Position of PHY_LP_LOOPBACK_CHECK field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_Pos = 0x1c
	// Bit mask of PHY_LP_LOOPBACK_CHECK field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_Msk = 0x10000000
	// Bit PHY_LP_LOOPBACK_CHECK.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK = 0x10000000
	// Position of PHY_LP_LOOPBACK_CHECK_DONE field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_DONE_Pos = 0x1d
	// Bit mask of PHY_LP_LOOPBACK_CHECK_DONE field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_DONE_Msk = 0x20000000
	// Bit PHY_LP_LOOPBACK_CHECK_DONE.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_CHECK_DONE = 0x20000000
	// Position of PHY_LP_LOOPBACK_EN field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_EN_Pos = 0x1e
	// Bit mask of PHY_LP_LOOPBACK_EN field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_EN_Msk = 0x40000000
	// Bit PHY_LP_LOOPBACK_EN.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_EN = 0x40000000
	// Position of PHY_LP_LOOPBACK_OK field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_OK_Pos = 0x1f
	// Bit mask of PHY_LP_LOOPBACK_OK field.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_OK_Msk = 0x80000000
	// Bit PHY_LP_LOOPBACK_OK.
	DSI_BRG_PHY_LP_LOOPBACK_CTRL_PHY_LP_LOOPBACK_OK = 0x80000000

	// PHY_HS_LOOPBACK_CTRL: dsi phy hp_loopback test ctrl
	// Position of PHY_HS_TXDATAHS_1 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_1_Pos = 0x0
	// Bit mask of PHY_HS_TXDATAHS_1 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_1_Msk = 0xff
	// Position of PHY_HS_TXREQUESTDATAHS_1 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_1_Pos = 0x8
	// Bit mask of PHY_HS_TXREQUESTDATAHS_1 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_1_Msk = 0x100
	// Bit PHY_HS_TXREQUESTDATAHS_1.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_1 = 0x100
	// Position of PHY_HS_BASEDIR_1 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_1_Pos = 0x9
	// Bit mask of PHY_HS_BASEDIR_1 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_1_Msk = 0x200
	// Bit PHY_HS_BASEDIR_1.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_1 = 0x200
	// Position of PHY_HS_TXDATAHS_0 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_0_Pos = 0x10
	// Bit mask of PHY_HS_TXDATAHS_0 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXDATAHS_0_Msk = 0xff0000
	// Position of PHY_HS_TXREQUESTDATAHS_0 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_0_Pos = 0x18
	// Bit mask of PHY_HS_TXREQUESTDATAHS_0 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_0_Msk = 0x1000000
	// Bit PHY_HS_TXREQUESTDATAHS_0.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTDATAHS_0 = 0x1000000
	// Position of PHY_HS_BASEDIR_0 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_0_Pos = 0x19
	// Bit mask of PHY_HS_BASEDIR_0 field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_0_Msk = 0x2000000
	// Bit PHY_HS_BASEDIR_0.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_BASEDIR_0 = 0x2000000
	// Position of PHY_HS_TXREQUESTHSCLK field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTHSCLK_Pos = 0x1b
	// Bit mask of PHY_HS_TXREQUESTHSCLK field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTHSCLK_Msk = 0x8000000
	// Bit PHY_HS_TXREQUESTHSCLK.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_TXREQUESTHSCLK = 0x8000000
	// Position of PHY_HS_LOOPBACK_CHECK field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_Pos = 0x1c
	// Bit mask of PHY_HS_LOOPBACK_CHECK field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_Msk = 0x10000000
	// Bit PHY_HS_LOOPBACK_CHECK.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK = 0x10000000
	// Position of PHY_HS_LOOPBACK_CHECK_DONE field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_DONE_Pos = 0x1d
	// Bit mask of PHY_HS_LOOPBACK_CHECK_DONE field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_DONE_Msk = 0x20000000
	// Bit PHY_HS_LOOPBACK_CHECK_DONE.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_CHECK_DONE = 0x20000000
	// Position of PHY_HS_LOOPBACK_EN field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_EN_Pos = 0x1e
	// Bit mask of PHY_HS_LOOPBACK_EN field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_EN_Msk = 0x40000000
	// Bit PHY_HS_LOOPBACK_EN.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_EN = 0x40000000
	// Position of PHY_HS_LOOPBACK_OK field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_OK_Pos = 0x1f
	// Bit mask of PHY_HS_LOOPBACK_OK field.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_OK_Msk = 0x80000000
	// Bit PHY_HS_LOOPBACK_OK.
	DSI_BRG_PHY_HS_LOOPBACK_CTRL_PHY_HS_LOOPBACK_OK = 0x80000000

	// PHY_LOOPBACK_CNT: loopback test cnt
	// Position of PHY_HS_CHECK_CNT_TH field.
	DSI_BRG_PHY_LOOPBACK_CNT_PHY_HS_CHECK_CNT_TH_Pos = 0x0
	// Bit mask of PHY_HS_CHECK_CNT_TH field.
	DSI_BRG_PHY_LOOPBACK_CNT_PHY_HS_CHECK_CNT_TH_Msk = 0xff
	// Position of PHY_LP_CHECK_CNT_TH field.
	DSI_BRG_PHY_LOOPBACK_CNT_PHY_LP_CHECK_CNT_TH_Pos = 0x10
	// Bit mask of PHY_LP_CHECK_CNT_TH field.
	DSI_BRG_PHY_LOOPBACK_CNT_PHY_LP_CHECK_CNT_TH_Msk = 0xff0000
)

// Constants for MIPI_DSI_HOST: MIPI Display Interface Host
const (
	// VERSION: NA
	// Position of VERSION field.
	DSI_HOST_VERSION_VERSION_Pos = 0x0
	// Bit mask of VERSION field.
	DSI_HOST_VERSION_VERSION_Msk = 0xffffffff

	// PWR_UP: NA
	// Position of SHUTDOWNZ field.
	DSI_HOST_PWR_UP_SHUTDOWNZ_Pos = 0x0
	// Bit mask of SHUTDOWNZ field.
	DSI_HOST_PWR_UP_SHUTDOWNZ_Msk = 0x1
	// Bit SHUTDOWNZ.
	DSI_HOST_PWR_UP_SHUTDOWNZ = 0x1

	// CLKMGR_CFG: NA
	// Position of TX_ESC_CLK_DIVISION field.
	DSI_HOST_CLKMGR_CFG_TX_ESC_CLK_DIVISION_Pos = 0x0
	// Bit mask of TX_ESC_CLK_DIVISION field.
	DSI_HOST_CLKMGR_CFG_TX_ESC_CLK_DIVISION_Msk = 0xff
	// Position of TO_CLK_DIVISION field.
	DSI_HOST_CLKMGR_CFG_TO_CLK_DIVISION_Pos = 0x8
	// Bit mask of TO_CLK_DIVISION field.
	DSI_HOST_CLKMGR_CFG_TO_CLK_DIVISION_Msk = 0xff00

	// DPI_VCID: NA
	// Position of DPI_VCID field.
	DSI_HOST_DPI_VCID_DPI_VCID_Pos = 0x0
	// Bit mask of DPI_VCID field.
	DSI_HOST_DPI_VCID_DPI_VCID_Msk = 0x3

	// DPI_COLOR_CODING: NA
	// Position of DPI_COLOR_CODING field.
	DSI_HOST_DPI_COLOR_CODING_DPI_COLOR_CODING_Pos = 0x0
	// Bit mask of DPI_COLOR_CODING field.
	DSI_HOST_DPI_COLOR_CODING_DPI_COLOR_CODING_Msk = 0xf
	// Position of LOOSELY18_EN field.
	DSI_HOST_DPI_COLOR_CODING_LOOSELY18_EN_Pos = 0x8
	// Bit mask of LOOSELY18_EN field.
	DSI_HOST_DPI_COLOR_CODING_LOOSELY18_EN_Msk = 0x100
	// Bit LOOSELY18_EN.
	DSI_HOST_DPI_COLOR_CODING_LOOSELY18_EN = 0x100

	// DPI_CFG_POL: NA
	// Position of DATAEN_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_DATAEN_ACTIVE_LOW_Pos = 0x0
	// Bit mask of DATAEN_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_DATAEN_ACTIVE_LOW_Msk = 0x1
	// Bit DATAEN_ACTIVE_LOW.
	DSI_HOST_DPI_CFG_POL_DATAEN_ACTIVE_LOW = 0x1
	// Position of VSYNC_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_VSYNC_ACTIVE_LOW_Pos = 0x1
	// Bit mask of VSYNC_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_VSYNC_ACTIVE_LOW_Msk = 0x2
	// Bit VSYNC_ACTIVE_LOW.
	DSI_HOST_DPI_CFG_POL_VSYNC_ACTIVE_LOW = 0x2
	// Position of HSYNC_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_HSYNC_ACTIVE_LOW_Pos = 0x2
	// Bit mask of HSYNC_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_HSYNC_ACTIVE_LOW_Msk = 0x4
	// Bit HSYNC_ACTIVE_LOW.
	DSI_HOST_DPI_CFG_POL_HSYNC_ACTIVE_LOW = 0x4
	// Position of SHUTD_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_SHUTD_ACTIVE_LOW_Pos = 0x3
	// Bit mask of SHUTD_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_SHUTD_ACTIVE_LOW_Msk = 0x8
	// Bit SHUTD_ACTIVE_LOW.
	DSI_HOST_DPI_CFG_POL_SHUTD_ACTIVE_LOW = 0x8
	// Position of COLORM_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_COLORM_ACTIVE_LOW_Pos = 0x4
	// Bit mask of COLORM_ACTIVE_LOW field.
	DSI_HOST_DPI_CFG_POL_COLORM_ACTIVE_LOW_Msk = 0x10
	// Bit COLORM_ACTIVE_LOW.
	DSI_HOST_DPI_CFG_POL_COLORM_ACTIVE_LOW = 0x10

	// DPI_LP_CMD_TIM: NA
	// Position of INVACT_LPCMD_TIME field.
	DSI_HOST_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Pos = 0x0
	// Bit mask of INVACT_LPCMD_TIME field.
	DSI_HOST_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_Msk = 0xff
	// Position of OUTVACT_LPCMD_TIME field.
	DSI_HOST_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_Pos = 0x10
	// Bit mask of OUTVACT_LPCMD_TIME field.
	DSI_HOST_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_Msk = 0xff0000

	// DBI_VCID: NA
	// Position of DBI_VCID field.
	DSI_HOST_DBI_VCID_DBI_VCID_Pos = 0x0
	// Bit mask of DBI_VCID field.
	DSI_HOST_DBI_VCID_DBI_VCID_Msk = 0x3

	// DBI_CFG: NA
	// Position of IN_DBI_CONF field.
	DSI_HOST_DBI_CFG_IN_DBI_CONF_Pos = 0x0
	// Bit mask of IN_DBI_CONF field.
	DSI_HOST_DBI_CFG_IN_DBI_CONF_Msk = 0xf
	// Position of OUT_DBI_CONF field.
	DSI_HOST_DBI_CFG_OUT_DBI_CONF_Pos = 0x8
	// Bit mask of OUT_DBI_CONF field.
	DSI_HOST_DBI_CFG_OUT_DBI_CONF_Msk = 0xf00
	// Position of LUT_SIZE_CONF field.
	DSI_HOST_DBI_CFG_LUT_SIZE_CONF_Pos = 0x10
	// Bit mask of LUT_SIZE_CONF field.
	DSI_HOST_DBI_CFG_LUT_SIZE_CONF_Msk = 0x30000

	// DBI_PARTITIONING_EN: NA
	// Position of PARTITIONING_EN field.
	DSI_HOST_DBI_PARTITIONING_EN_PARTITIONING_EN_Pos = 0x0
	// Bit mask of PARTITIONING_EN field.
	DSI_HOST_DBI_PARTITIONING_EN_PARTITIONING_EN_Msk = 0x1
	// Bit PARTITIONING_EN.
	DSI_HOST_DBI_PARTITIONING_EN_PARTITIONING_EN = 0x1

	// DBI_CMDSIZE: NA
	// Position of WR_CMD_SIZE field.
	DSI_HOST_DBI_CMDSIZE_WR_CMD_SIZE_Pos = 0x0
	// Bit mask of WR_CMD_SIZE field.
	DSI_HOST_DBI_CMDSIZE_WR_CMD_SIZE_Msk = 0xffff
	// Position of ALLOWED_CMD_SIZE field.
	DSI_HOST_DBI_CMDSIZE_ALLOWED_CMD_SIZE_Pos = 0x10
	// Bit mask of ALLOWED_CMD_SIZE field.
	DSI_HOST_DBI_CMDSIZE_ALLOWED_CMD_SIZE_Msk = 0xffff0000

	// PCKHDL_CFG: NA
	// Position of EOTP_TX_EN field.
	DSI_HOST_PCKHDL_CFG_EOTP_TX_EN_Pos = 0x0
	// Bit mask of EOTP_TX_EN field.
	DSI_HOST_PCKHDL_CFG_EOTP_TX_EN_Msk = 0x1
	// Bit EOTP_TX_EN.
	DSI_HOST_PCKHDL_CFG_EOTP_TX_EN = 0x1
	// Position of EOTP_RX_EN field.
	DSI_HOST_PCKHDL_CFG_EOTP_RX_EN_Pos = 0x1
	// Bit mask of EOTP_RX_EN field.
	DSI_HOST_PCKHDL_CFG_EOTP_RX_EN_Msk = 0x2
	// Bit EOTP_RX_EN.
	DSI_HOST_PCKHDL_CFG_EOTP_RX_EN = 0x2
	// Position of BTA_EN field.
	DSI_HOST_PCKHDL_CFG_BTA_EN_Pos = 0x2
	// Bit mask of BTA_EN field.
	DSI_HOST_PCKHDL_CFG_BTA_EN_Msk = 0x4
	// Bit BTA_EN.
	DSI_HOST_PCKHDL_CFG_BTA_EN = 0x4
	// Position of ECC_RX_EN field.
	DSI_HOST_PCKHDL_CFG_ECC_RX_EN_Pos = 0x3
	// Bit mask of ECC_RX_EN field.
	DSI_HOST_PCKHDL_CFG_ECC_RX_EN_Msk = 0x8
	// Bit ECC_RX_EN.
	DSI_HOST_PCKHDL_CFG_ECC_RX_EN = 0x8
	// Position of CRC_RX_EN field.
	DSI_HOST_PCKHDL_CFG_CRC_RX_EN_Pos = 0x4
	// Bit mask of CRC_RX_EN field.
	DSI_HOST_PCKHDL_CFG_CRC_RX_EN_Msk = 0x10
	// Bit CRC_RX_EN.
	DSI_HOST_PCKHDL_CFG_CRC_RX_EN = 0x10
	// Position of EOTP_TX_LP_EN field.
	DSI_HOST_PCKHDL_CFG_EOTP_TX_LP_EN_Pos = 0x5
	// Bit mask of EOTP_TX_LP_EN field.
	DSI_HOST_PCKHDL_CFG_EOTP_TX_LP_EN_Msk = 0x20
	// Bit EOTP_TX_LP_EN.
	DSI_HOST_PCKHDL_CFG_EOTP_TX_LP_EN = 0x20

	// GEN_VCID: NA
	// Position of RX field.
	DSI_HOST_GEN_VCID_RX_Pos = 0x0
	// Bit mask of RX field.
	DSI_HOST_GEN_VCID_RX_Msk = 0x3
	// Position of TEAR_AUTO field.
	DSI_HOST_GEN_VCID_TEAR_AUTO_Pos = 0x8
	// Bit mask of TEAR_AUTO field.
	DSI_HOST_GEN_VCID_TEAR_AUTO_Msk = 0x300
	// Position of TX_AUTO field.
	DSI_HOST_GEN_VCID_TX_AUTO_Pos = 0x10
	// Bit mask of TX_AUTO field.
	DSI_HOST_GEN_VCID_TX_AUTO_Msk = 0x30000

	// MODE_CFG: NA
	// Position of CMD_VIDEO_MODE field.
	DSI_HOST_MODE_CFG_CMD_VIDEO_MODE_Pos = 0x0
	// Bit mask of CMD_VIDEO_MODE field.
	DSI_HOST_MODE_CFG_CMD_VIDEO_MODE_Msk = 0x1
	// Bit CMD_VIDEO_MODE.
	DSI_HOST_MODE_CFG_CMD_VIDEO_MODE = 0x1

	// VID_MODE_CFG: NA
	// Position of VID_MODE_TYPE field.
	DSI_HOST_VID_MODE_CFG_VID_MODE_TYPE_Pos = 0x0
	// Bit mask of VID_MODE_TYPE field.
	DSI_HOST_VID_MODE_CFG_VID_MODE_TYPE_Msk = 0x3
	// Position of LP_VSA_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VSA_EN_Pos = 0x8
	// Bit mask of LP_VSA_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VSA_EN_Msk = 0x100
	// Bit LP_VSA_EN.
	DSI_HOST_VID_MODE_CFG_LP_VSA_EN = 0x100
	// Position of LP_VBP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VBP_EN_Pos = 0x9
	// Bit mask of LP_VBP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VBP_EN_Msk = 0x200
	// Bit LP_VBP_EN.
	DSI_HOST_VID_MODE_CFG_LP_VBP_EN = 0x200
	// Position of LP_VFP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VFP_EN_Pos = 0xa
	// Bit mask of LP_VFP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VFP_EN_Msk = 0x400
	// Bit LP_VFP_EN.
	DSI_HOST_VID_MODE_CFG_LP_VFP_EN = 0x400
	// Position of LP_VACT_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VACT_EN_Pos = 0xb
	// Bit mask of LP_VACT_EN field.
	DSI_HOST_VID_MODE_CFG_LP_VACT_EN_Msk = 0x800
	// Bit LP_VACT_EN.
	DSI_HOST_VID_MODE_CFG_LP_VACT_EN = 0x800
	// Position of LP_HBP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_HBP_EN_Pos = 0xc
	// Bit mask of LP_HBP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_HBP_EN_Msk = 0x1000
	// Bit LP_HBP_EN.
	DSI_HOST_VID_MODE_CFG_LP_HBP_EN = 0x1000
	// Position of LP_HFP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_HFP_EN_Pos = 0xd
	// Bit mask of LP_HFP_EN field.
	DSI_HOST_VID_MODE_CFG_LP_HFP_EN_Msk = 0x2000
	// Bit LP_HFP_EN.
	DSI_HOST_VID_MODE_CFG_LP_HFP_EN = 0x2000
	// Position of FRAME_BTA_ACK_EN field.
	DSI_HOST_VID_MODE_CFG_FRAME_BTA_ACK_EN_Pos = 0xe
	// Bit mask of FRAME_BTA_ACK_EN field.
	DSI_HOST_VID_MODE_CFG_FRAME_BTA_ACK_EN_Msk = 0x4000
	// Bit FRAME_BTA_ACK_EN.
	DSI_HOST_VID_MODE_CFG_FRAME_BTA_ACK_EN = 0x4000
	// Position of LP_CMD_EN field.
	DSI_HOST_VID_MODE_CFG_LP_CMD_EN_Pos = 0xf
	// Bit mask of LP_CMD_EN field.
	DSI_HOST_VID_MODE_CFG_LP_CMD_EN_Msk = 0x8000
	// Bit LP_CMD_EN.
	DSI_HOST_VID_MODE_CFG_LP_CMD_EN = 0x8000
	// Position of VPG_EN field.
	DSI_HOST_VID_MODE_CFG_VPG_EN_Pos = 0x10
	// Bit mask of VPG_EN field.
	DSI_HOST_VID_MODE_CFG_VPG_EN_Msk = 0x10000
	// Bit VPG_EN.
	DSI_HOST_VID_MODE_CFG_VPG_EN = 0x10000
	// Position of VPG_MODE field.
	DSI_HOST_VID_MODE_CFG_VPG_MODE_Pos = 0x14
	// Bit mask of VPG_MODE field.
	DSI_HOST_VID_MODE_CFG_VPG_MODE_Msk = 0x100000
	// Bit VPG_MODE.
	DSI_HOST_VID_MODE_CFG_VPG_MODE = 0x100000
	// Position of VPG_ORIENTATION field.
	DSI_HOST_VID_MODE_CFG_VPG_ORIENTATION_Pos = 0x18
	// Bit mask of VPG_ORIENTATION field.
	DSI_HOST_VID_MODE_CFG_VPG_ORIENTATION_Msk = 0x1000000
	// Bit VPG_ORIENTATION.
	DSI_HOST_VID_MODE_CFG_VPG_ORIENTATION = 0x1000000

	// VID_PKT_SIZE: NA
	// Position of VID_PKT_SIZE field.
	DSI_HOST_VID_PKT_SIZE_VID_PKT_SIZE_Pos = 0x0
	// Bit mask of VID_PKT_SIZE field.
	DSI_HOST_VID_PKT_SIZE_VID_PKT_SIZE_Msk = 0x3fff

	// VID_NUM_CHUNKS: NA
	// Position of VID_NUM_CHUNKS field.
	DSI_HOST_VID_NUM_CHUNKS_VID_NUM_CHUNKS_Pos = 0x0
	// Bit mask of VID_NUM_CHUNKS field.
	DSI_HOST_VID_NUM_CHUNKS_VID_NUM_CHUNKS_Msk = 0x1fff

	// VID_NULL_SIZE: NA
	// Position of VID_NULL_SIZE field.
	DSI_HOST_VID_NULL_SIZE_VID_NULL_SIZE_Pos = 0x0
	// Bit mask of VID_NULL_SIZE field.
	DSI_HOST_VID_NULL_SIZE_VID_NULL_SIZE_Msk = 0x1fff

	// VID_HSA_TIME: NA
	// Position of VID_HSA_TIME field.
	DSI_HOST_VID_HSA_TIME_VID_HSA_TIME_Pos = 0x0
	// Bit mask of VID_HSA_TIME field.
	DSI_HOST_VID_HSA_TIME_VID_HSA_TIME_Msk = 0xfff

	// VID_HBP_TIME: NA
	// Position of VID_HBP_TIME field.
	DSI_HOST_VID_HBP_TIME_VID_HBP_TIME_Pos = 0x0
	// Bit mask of VID_HBP_TIME field.
	DSI_HOST_VID_HBP_TIME_VID_HBP_TIME_Msk = 0xfff

	// VID_HLINE_TIME: NA
	// Position of VID_HLINE_TIME field.
	DSI_HOST_VID_HLINE_TIME_VID_HLINE_TIME_Pos = 0x0
	// Bit mask of VID_HLINE_TIME field.
	DSI_HOST_VID_HLINE_TIME_VID_HLINE_TIME_Msk = 0x7fff

	// VID_VSA_LINES: NA
	// Position of VSA_LINES field.
	DSI_HOST_VID_VSA_LINES_VSA_LINES_Pos = 0x0
	// Bit mask of VSA_LINES field.
	DSI_HOST_VID_VSA_LINES_VSA_LINES_Msk = 0x3ff

	// VID_VBP_LINES: NA
	// Position of VBP_LINES field.
	DSI_HOST_VID_VBP_LINES_VBP_LINES_Pos = 0x0
	// Bit mask of VBP_LINES field.
	DSI_HOST_VID_VBP_LINES_VBP_LINES_Msk = 0x3ff

	// VID_VFP_LINES: NA
	// Position of VFP_LINES field.
	DSI_HOST_VID_VFP_LINES_VFP_LINES_Pos = 0x0
	// Bit mask of VFP_LINES field.
	DSI_HOST_VID_VFP_LINES_VFP_LINES_Msk = 0x3ff

	// VID_VACTIVE_LINES: NA
	// Position of V_ACTIVE_LINES field.
	DSI_HOST_VID_VACTIVE_LINES_V_ACTIVE_LINES_Pos = 0x0
	// Bit mask of V_ACTIVE_LINES field.
	DSI_HOST_VID_VACTIVE_LINES_V_ACTIVE_LINES_Msk = 0x3fff

	// EDPI_CMD_SIZE: NA
	// Position of EDPI_ALLOWED_CMD_SIZE field.
	DSI_HOST_EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Pos = 0x0
	// Bit mask of EDPI_ALLOWED_CMD_SIZE field.
	DSI_HOST_EDPI_CMD_SIZE_EDPI_ALLOWED_CMD_SIZE_Msk = 0xffff

	// CMD_MODE_CFG: NA
	// Position of TEAR_FX_EN field.
	DSI_HOST_CMD_MODE_CFG_TEAR_FX_EN_Pos = 0x0
	// Bit mask of TEAR_FX_EN field.
	DSI_HOST_CMD_MODE_CFG_TEAR_FX_EN_Msk = 0x1
	// Bit TEAR_FX_EN.
	DSI_HOST_CMD_MODE_CFG_TEAR_FX_EN = 0x1
	// Position of ACK_RQST_EN field.
	DSI_HOST_CMD_MODE_CFG_ACK_RQST_EN_Pos = 0x1
	// Bit mask of ACK_RQST_EN field.
	DSI_HOST_CMD_MODE_CFG_ACK_RQST_EN_Msk = 0x2
	// Bit ACK_RQST_EN.
	DSI_HOST_CMD_MODE_CFG_ACK_RQST_EN = 0x2
	// Position of GEN_SW_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_0P_TX_Pos = 0x8
	// Bit mask of GEN_SW_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_0P_TX_Msk = 0x100
	// Bit GEN_SW_0P_TX.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_0P_TX = 0x100
	// Position of GEN_SW_1P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_1P_TX_Pos = 0x9
	// Bit mask of GEN_SW_1P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_1P_TX_Msk = 0x200
	// Bit GEN_SW_1P_TX.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_1P_TX = 0x200
	// Position of GEN_SW_2P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_2P_TX_Pos = 0xa
	// Bit mask of GEN_SW_2P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_2P_TX_Msk = 0x400
	// Bit GEN_SW_2P_TX.
	DSI_HOST_CMD_MODE_CFG_GEN_SW_2P_TX = 0x400
	// Position of GEN_SR_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_0P_TX_Pos = 0xb
	// Bit mask of GEN_SR_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_0P_TX_Msk = 0x800
	// Bit GEN_SR_0P_TX.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_0P_TX = 0x800
	// Position of GEN_SR_1P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_1P_TX_Pos = 0xc
	// Bit mask of GEN_SR_1P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_1P_TX_Msk = 0x1000
	// Bit GEN_SR_1P_TX.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_1P_TX = 0x1000
	// Position of GEN_SR_2P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_2P_TX_Pos = 0xd
	// Bit mask of GEN_SR_2P_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_2P_TX_Msk = 0x2000
	// Bit GEN_SR_2P_TX.
	DSI_HOST_CMD_MODE_CFG_GEN_SR_2P_TX = 0x2000
	// Position of GEN_LW_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_LW_TX_Pos = 0xe
	// Bit mask of GEN_LW_TX field.
	DSI_HOST_CMD_MODE_CFG_GEN_LW_TX_Msk = 0x4000
	// Bit GEN_LW_TX.
	DSI_HOST_CMD_MODE_CFG_GEN_LW_TX = 0x4000
	// Position of DCS_SW_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_SW_0P_TX_Pos = 0x10
	// Bit mask of DCS_SW_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_SW_0P_TX_Msk = 0x10000
	// Bit DCS_SW_0P_TX.
	DSI_HOST_CMD_MODE_CFG_DCS_SW_0P_TX = 0x10000
	// Position of DCS_SW_1P_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_SW_1P_TX_Pos = 0x11
	// Bit mask of DCS_SW_1P_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_SW_1P_TX_Msk = 0x20000
	// Bit DCS_SW_1P_TX.
	DSI_HOST_CMD_MODE_CFG_DCS_SW_1P_TX = 0x20000
	// Position of DCS_SR_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_SR_0P_TX_Pos = 0x12
	// Bit mask of DCS_SR_0P_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_SR_0P_TX_Msk = 0x40000
	// Bit DCS_SR_0P_TX.
	DSI_HOST_CMD_MODE_CFG_DCS_SR_0P_TX = 0x40000
	// Position of DCS_LW_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_LW_TX_Pos = 0x13
	// Bit mask of DCS_LW_TX field.
	DSI_HOST_CMD_MODE_CFG_DCS_LW_TX_Msk = 0x80000
	// Bit DCS_LW_TX.
	DSI_HOST_CMD_MODE_CFG_DCS_LW_TX = 0x80000
	// Position of MAX_RD_PKT_SIZE field.
	DSI_HOST_CMD_MODE_CFG_MAX_RD_PKT_SIZE_Pos = 0x18
	// Bit mask of MAX_RD_PKT_SIZE field.
	DSI_HOST_CMD_MODE_CFG_MAX_RD_PKT_SIZE_Msk = 0x1000000
	// Bit MAX_RD_PKT_SIZE.
	DSI_HOST_CMD_MODE_CFG_MAX_RD_PKT_SIZE = 0x1000000

	// GEN_HDR: NA
	// Position of GEN_DT field.
	DSI_HOST_GEN_HDR_GEN_DT_Pos = 0x0
	// Bit mask of GEN_DT field.
	DSI_HOST_GEN_HDR_GEN_DT_Msk = 0x3f
	// Position of GEN_VC field.
	DSI_HOST_GEN_HDR_GEN_VC_Pos = 0x6
	// Bit mask of GEN_VC field.
	DSI_HOST_GEN_HDR_GEN_VC_Msk = 0xc0
	// Position of GEN_WC_LSBYTE field.
	DSI_HOST_GEN_HDR_GEN_WC_LSBYTE_Pos = 0x8
	// Bit mask of GEN_WC_LSBYTE field.
	DSI_HOST_GEN_HDR_GEN_WC_LSBYTE_Msk = 0xff00
	// Position of GEN_WC_MSBYTE field.
	DSI_HOST_GEN_HDR_GEN_WC_MSBYTE_Pos = 0x10
	// Bit mask of GEN_WC_MSBYTE field.
	DSI_HOST_GEN_HDR_GEN_WC_MSBYTE_Msk = 0xff0000

	// GEN_PLD_DATA: NA
	// Position of GEN_PLD_B1 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B1_Pos = 0x0
	// Bit mask of GEN_PLD_B1 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B1_Msk = 0xff
	// Position of GEN_PLD_B2 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B2_Pos = 0x8
	// Bit mask of GEN_PLD_B2 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B2_Msk = 0xff00
	// Position of GEN_PLD_B3 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B3_Pos = 0x10
	// Bit mask of GEN_PLD_B3 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B3_Msk = 0xff0000
	// Position of GEN_PLD_B4 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B4_Pos = 0x18
	// Bit mask of GEN_PLD_B4 field.
	DSI_HOST_GEN_PLD_DATA_GEN_PLD_B4_Msk = 0xff000000

	// CMD_PKT_STATUS: NA
	// Position of GEN_CMD_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_CMD_EMPTY_Pos = 0x0
	// Bit mask of GEN_CMD_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_CMD_EMPTY_Msk = 0x1
	// Bit GEN_CMD_EMPTY.
	DSI_HOST_CMD_PKT_STATUS_GEN_CMD_EMPTY = 0x1
	// Position of GEN_CMD_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_CMD_FULL_Pos = 0x1
	// Bit mask of GEN_CMD_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_CMD_FULL_Msk = 0x2
	// Bit GEN_CMD_FULL.
	DSI_HOST_CMD_PKT_STATUS_GEN_CMD_FULL = 0x2
	// Position of GEN_PLD_W_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_Pos = 0x2
	// Bit mask of GEN_PLD_W_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_Msk = 0x4
	// Bit GEN_PLD_W_EMPTY.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_W_EMPTY = 0x4
	// Position of GEN_PLD_W_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_W_FULL_Pos = 0x3
	// Bit mask of GEN_PLD_W_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_W_FULL_Msk = 0x8
	// Bit GEN_PLD_W_FULL.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_W_FULL = 0x8
	// Position of GEN_PLD_R_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_Pos = 0x4
	// Bit mask of GEN_PLD_R_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_Msk = 0x10
	// Bit GEN_PLD_R_EMPTY.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_R_EMPTY = 0x10
	// Position of GEN_PLD_R_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_R_FULL_Pos = 0x5
	// Bit mask of GEN_PLD_R_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_R_FULL_Msk = 0x20
	// Bit GEN_PLD_R_FULL.
	DSI_HOST_CMD_PKT_STATUS_GEN_PLD_R_FULL = 0x20
	// Position of GEN_RD_CMD_BUSY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_Pos = 0x6
	// Bit mask of GEN_RD_CMD_BUSY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_Msk = 0x40
	// Bit GEN_RD_CMD_BUSY.
	DSI_HOST_CMD_PKT_STATUS_GEN_RD_CMD_BUSY = 0x40
	// Position of GEN_BUFF_CMD_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_Pos = 0x10
	// Bit mask of GEN_BUFF_CMD_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_Msk = 0x10000
	// Bit GEN_BUFF_CMD_EMPTY.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY = 0x10000
	// Position of GEN_BUFF_CMD_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_Pos = 0x11
	// Bit mask of GEN_BUFF_CMD_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_Msk = 0x20000
	// Bit GEN_BUFF_CMD_FULL.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL = 0x20000
	// Position of GEN_BUFF_PLD_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_Pos = 0x12
	// Bit mask of GEN_BUFF_PLD_EMPTY field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_Msk = 0x40000
	// Bit GEN_BUFF_PLD_EMPTY.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY = 0x40000
	// Position of GEN_BUFF_PLD_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_Pos = 0x13
	// Bit mask of GEN_BUFF_PLD_FULL field.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_Msk = 0x80000
	// Bit GEN_BUFF_PLD_FULL.
	DSI_HOST_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL = 0x80000

	// TO_CNT_CFG: NA
	// Position of LPRX_TO_CNT field.
	DSI_HOST_TO_CNT_CFG_LPRX_TO_CNT_Pos = 0x0
	// Bit mask of LPRX_TO_CNT field.
	DSI_HOST_TO_CNT_CFG_LPRX_TO_CNT_Msk = 0xffff
	// Position of HSTX_TO_CNT field.
	DSI_HOST_TO_CNT_CFG_HSTX_TO_CNT_Pos = 0x10
	// Bit mask of HSTX_TO_CNT field.
	DSI_HOST_TO_CNT_CFG_HSTX_TO_CNT_Msk = 0xffff0000

	// HS_RD_TO_CNT: NA
	// Position of HS_RD_TO_CNT field.
	DSI_HOST_HS_RD_TO_CNT_HS_RD_TO_CNT_Pos = 0x0
	// Bit mask of HS_RD_TO_CNT field.
	DSI_HOST_HS_RD_TO_CNT_HS_RD_TO_CNT_Msk = 0xffff

	// LP_RD_TO_CNT: NA
	// Position of LP_RD_TO_CNT field.
	DSI_HOST_LP_RD_TO_CNT_LP_RD_TO_CNT_Pos = 0x0
	// Bit mask of LP_RD_TO_CNT field.
	DSI_HOST_LP_RD_TO_CNT_LP_RD_TO_CNT_Msk = 0xffff

	// HS_WR_TO_CNT: NA
	// Position of HS_WR_TO_CNT field.
	DSI_HOST_HS_WR_TO_CNT_HS_WR_TO_CNT_Pos = 0x0
	// Bit mask of HS_WR_TO_CNT field.
	DSI_HOST_HS_WR_TO_CNT_HS_WR_TO_CNT_Msk = 0xffff

	// LP_WR_TO_CNT: NA
	// Position of LP_WR_TO_CNT field.
	DSI_HOST_LP_WR_TO_CNT_LP_WR_TO_CNT_Pos = 0x0
	// Bit mask of LP_WR_TO_CNT field.
	DSI_HOST_LP_WR_TO_CNT_LP_WR_TO_CNT_Msk = 0xffff

	// BTA_TO_CNT: NA
	// Position of BTA_TO_CNT field.
	DSI_HOST_BTA_TO_CNT_BTA_TO_CNT_Pos = 0x0
	// Bit mask of BTA_TO_CNT field.
	DSI_HOST_BTA_TO_CNT_BTA_TO_CNT_Msk = 0xffff

	// SDF_3D: NA
	// Position of MODE_3D field.
	DSI_HOST_SDF_3D_MODE_3D_Pos = 0x0
	// Bit mask of MODE_3D field.
	DSI_HOST_SDF_3D_MODE_3D_Msk = 0x3
	// Position of FORMAT_3D field.
	DSI_HOST_SDF_3D_FORMAT_3D_Pos = 0x2
	// Bit mask of FORMAT_3D field.
	DSI_HOST_SDF_3D_FORMAT_3D_Msk = 0xc
	// Position of SECOND_VSYNC field.
	DSI_HOST_SDF_3D_SECOND_VSYNC_Pos = 0x4
	// Bit mask of SECOND_VSYNC field.
	DSI_HOST_SDF_3D_SECOND_VSYNC_Msk = 0x10
	// Bit SECOND_VSYNC.
	DSI_HOST_SDF_3D_SECOND_VSYNC = 0x10
	// Position of RIGHT_FIRST field.
	DSI_HOST_SDF_3D_RIGHT_FIRST_Pos = 0x5
	// Bit mask of RIGHT_FIRST field.
	DSI_HOST_SDF_3D_RIGHT_FIRST_Msk = 0x20
	// Bit RIGHT_FIRST.
	DSI_HOST_SDF_3D_RIGHT_FIRST = 0x20
	// Position of SEND_3D_CFG field.
	DSI_HOST_SDF_3D_SEND_3D_CFG_Pos = 0x10
	// Bit mask of SEND_3D_CFG field.
	DSI_HOST_SDF_3D_SEND_3D_CFG_Msk = 0x10000
	// Bit SEND_3D_CFG.
	DSI_HOST_SDF_3D_SEND_3D_CFG = 0x10000

	// LPCLK_CTRL: NA
	// Position of PHY_TXREQUESTCLKHS field.
	DSI_HOST_LPCLK_CTRL_PHY_TXREQUESTCLKHS_Pos = 0x0
	// Bit mask of PHY_TXREQUESTCLKHS field.
	DSI_HOST_LPCLK_CTRL_PHY_TXREQUESTCLKHS_Msk = 0x1
	// Bit PHY_TXREQUESTCLKHS.
	DSI_HOST_LPCLK_CTRL_PHY_TXREQUESTCLKHS = 0x1
	// Position of AUTO_CLKLANE_CTRL field.
	DSI_HOST_LPCLK_CTRL_AUTO_CLKLANE_CTRL_Pos = 0x1
	// Bit mask of AUTO_CLKLANE_CTRL field.
	DSI_HOST_LPCLK_CTRL_AUTO_CLKLANE_CTRL_Msk = 0x2
	// Bit AUTO_CLKLANE_CTRL.
	DSI_HOST_LPCLK_CTRL_AUTO_CLKLANE_CTRL = 0x2

	// PHY_TMR_LPCLK_CFG: NA
	// Position of PHY_CLKLP2HS_TIME field.
	DSI_HOST_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Pos = 0x0
	// Bit mask of PHY_CLKLP2HS_TIME field.
	DSI_HOST_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_Msk = 0x3ff
	// Position of PHY_CLKHS2LP_TIME field.
	DSI_HOST_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Pos = 0x10
	// Bit mask of PHY_CLKHS2LP_TIME field.
	DSI_HOST_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_Msk = 0x3ff0000

	// PHY_TMR_CFG: NA
	// Position of PHY_LP2HS_TIME field.
	DSI_HOST_PHY_TMR_CFG_PHY_LP2HS_TIME_Pos = 0x0
	// Bit mask of PHY_LP2HS_TIME field.
	DSI_HOST_PHY_TMR_CFG_PHY_LP2HS_TIME_Msk = 0x3ff
	// Position of PHY_HS2LP_TIME field.
	DSI_HOST_PHY_TMR_CFG_PHY_HS2LP_TIME_Pos = 0x10
	// Bit mask of PHY_HS2LP_TIME field.
	DSI_HOST_PHY_TMR_CFG_PHY_HS2LP_TIME_Msk = 0x3ff0000

	// PHY_RSTZ: NA
	// Position of PHY_SHUTDOWNZ field.
	DSI_HOST_PHY_RSTZ_PHY_SHUTDOWNZ_Pos = 0x0
	// Bit mask of PHY_SHUTDOWNZ field.
	DSI_HOST_PHY_RSTZ_PHY_SHUTDOWNZ_Msk = 0x1
	// Bit PHY_SHUTDOWNZ.
	DSI_HOST_PHY_RSTZ_PHY_SHUTDOWNZ = 0x1
	// Position of PHY_RSTZ field.
	DSI_HOST_PHY_RSTZ_PHY_RSTZ_Pos = 0x1
	// Bit mask of PHY_RSTZ field.
	DSI_HOST_PHY_RSTZ_PHY_RSTZ_Msk = 0x2
	// Bit PHY_RSTZ.
	DSI_HOST_PHY_RSTZ_PHY_RSTZ = 0x2
	// Position of PHY_ENABLECLK field.
	DSI_HOST_PHY_RSTZ_PHY_ENABLECLK_Pos = 0x2
	// Bit mask of PHY_ENABLECLK field.
	DSI_HOST_PHY_RSTZ_PHY_ENABLECLK_Msk = 0x4
	// Bit PHY_ENABLECLK.
	DSI_HOST_PHY_RSTZ_PHY_ENABLECLK = 0x4
	// Position of PHY_FORCEPLL field.
	DSI_HOST_PHY_RSTZ_PHY_FORCEPLL_Pos = 0x3
	// Bit mask of PHY_FORCEPLL field.
	DSI_HOST_PHY_RSTZ_PHY_FORCEPLL_Msk = 0x8
	// Bit PHY_FORCEPLL.
	DSI_HOST_PHY_RSTZ_PHY_FORCEPLL = 0x8

	// PHY_IF_CFG: NA
	// Position of N_LANES field.
	DSI_HOST_PHY_IF_CFG_N_LANES_Pos = 0x0
	// Bit mask of N_LANES field.
	DSI_HOST_PHY_IF_CFG_N_LANES_Msk = 0x3
	// Position of PHY_STOP_WAIT_TIME field.
	DSI_HOST_PHY_IF_CFG_PHY_STOP_WAIT_TIME_Pos = 0x8
	// Bit mask of PHY_STOP_WAIT_TIME field.
	DSI_HOST_PHY_IF_CFG_PHY_STOP_WAIT_TIME_Msk = 0xff00

	// PHY_ULPS_CTRL: NA
	// Position of PHY_TXREQULPSCLK field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_Pos = 0x0
	// Bit mask of PHY_TXREQULPSCLK field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_Msk = 0x1
	// Bit PHY_TXREQULPSCLK.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXREQULPSCLK = 0x1
	// Position of PHY_TXEXITULPSCLK field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_Pos = 0x1
	// Bit mask of PHY_TXEXITULPSCLK field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_Msk = 0x2
	// Bit PHY_TXEXITULPSCLK.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK = 0x2
	// Position of PHY_TXREQULPSLAN field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_Pos = 0x2
	// Bit mask of PHY_TXREQULPSLAN field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_Msk = 0x4
	// Bit PHY_TXREQULPSLAN.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXREQULPSLAN = 0x4
	// Position of PHY_TXEXITULPSLAN field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_Pos = 0x3
	// Bit mask of PHY_TXEXITULPSLAN field.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_Msk = 0x8
	// Bit PHY_TXEXITULPSLAN.
	DSI_HOST_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN = 0x8

	// PHY_TX_TRIGGERS: NA
	// Position of PHY_TX_TRIGGERS field.
	DSI_HOST_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Pos = 0x0
	// Bit mask of PHY_TX_TRIGGERS field.
	DSI_HOST_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_Msk = 0xf

	// PHY_STATUS: NA
	// Position of PHY_LOCK field.
	DSI_HOST_PHY_STATUS_PHY_LOCK_Pos = 0x0
	// Bit mask of PHY_LOCK field.
	DSI_HOST_PHY_STATUS_PHY_LOCK_Msk = 0x1
	// Bit PHY_LOCK.
	DSI_HOST_PHY_STATUS_PHY_LOCK = 0x1
	// Position of PHY_DIRECTION field.
	DSI_HOST_PHY_STATUS_PHY_DIRECTION_Pos = 0x1
	// Bit mask of PHY_DIRECTION field.
	DSI_HOST_PHY_STATUS_PHY_DIRECTION_Msk = 0x2
	// Bit PHY_DIRECTION.
	DSI_HOST_PHY_STATUS_PHY_DIRECTION = 0x2
	// Position of PHY_STOPSTATECLKLANE field.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATECLKLANE_Pos = 0x2
	// Bit mask of PHY_STOPSTATECLKLANE field.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATECLKLANE_Msk = 0x4
	// Bit PHY_STOPSTATECLKLANE.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATECLKLANE = 0x4
	// Position of PHY_ULPSACTIVENOTCLK field.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOTCLK_Pos = 0x3
	// Bit mask of PHY_ULPSACTIVENOTCLK field.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOTCLK_Msk = 0x8
	// Bit PHY_ULPSACTIVENOTCLK.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOTCLK = 0x8
	// Position of PHY_STOPSTATE0LANE field.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATE0LANE_Pos = 0x4
	// Bit mask of PHY_STOPSTATE0LANE field.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATE0LANE_Msk = 0x10
	// Bit PHY_STOPSTATE0LANE.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATE0LANE = 0x10
	// Position of PHY_ULPSACTIVENOT0LANE field.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_Pos = 0x5
	// Bit mask of PHY_ULPSACTIVENOT0LANE field.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_Msk = 0x20
	// Bit PHY_ULPSACTIVENOT0LANE.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOT0LANE = 0x20
	// Position of PHY_RXULPSESC0LANE field.
	DSI_HOST_PHY_STATUS_PHY_RXULPSESC0LANE_Pos = 0x6
	// Bit mask of PHY_RXULPSESC0LANE field.
	DSI_HOST_PHY_STATUS_PHY_RXULPSESC0LANE_Msk = 0x40
	// Bit PHY_RXULPSESC0LANE.
	DSI_HOST_PHY_STATUS_PHY_RXULPSESC0LANE = 0x40
	// Position of PHY_STOPSTATE1LANE field.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATE1LANE_Pos = 0x7
	// Bit mask of PHY_STOPSTATE1LANE field.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATE1LANE_Msk = 0x80
	// Bit PHY_STOPSTATE1LANE.
	DSI_HOST_PHY_STATUS_PHY_STOPSTATE1LANE = 0x80
	// Position of PHY_ULPSACTIVENOT1LANE field.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_Pos = 0x8
	// Bit mask of PHY_ULPSACTIVENOT1LANE field.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_Msk = 0x100
	// Bit PHY_ULPSACTIVENOT1LANE.
	DSI_HOST_PHY_STATUS_PHY_ULPSACTIVENOT1LANE = 0x100

	// PHY_TST_CTRL0: NA
	// Position of PHY_TESTCLR field.
	DSI_HOST_PHY_TST_CTRL0_PHY_TESTCLR_Pos = 0x0
	// Bit mask of PHY_TESTCLR field.
	DSI_HOST_PHY_TST_CTRL0_PHY_TESTCLR_Msk = 0x1
	// Bit PHY_TESTCLR.
	DSI_HOST_PHY_TST_CTRL0_PHY_TESTCLR = 0x1
	// Position of PHY_TESTCLK field.
	DSI_HOST_PHY_TST_CTRL0_PHY_TESTCLK_Pos = 0x1
	// Bit mask of PHY_TESTCLK field.
	DSI_HOST_PHY_TST_CTRL0_PHY_TESTCLK_Msk = 0x2
	// Bit PHY_TESTCLK.
	DSI_HOST_PHY_TST_CTRL0_PHY_TESTCLK = 0x2

	// PHY_TST_CTRL1: NA
	// Position of PHY_TESTDIN field.
	DSI_HOST_PHY_TST_CTRL1_PHY_TESTDIN_Pos = 0x0
	// Bit mask of PHY_TESTDIN field.
	DSI_HOST_PHY_TST_CTRL1_PHY_TESTDIN_Msk = 0xff
	// Position of PHT_TESTDOUT field.
	DSI_HOST_PHY_TST_CTRL1_PHT_TESTDOUT_Pos = 0x8
	// Bit mask of PHT_TESTDOUT field.
	DSI_HOST_PHY_TST_CTRL1_PHT_TESTDOUT_Msk = 0xff00
	// Position of PHY_TESTEN field.
	DSI_HOST_PHY_TST_CTRL1_PHY_TESTEN_Pos = 0x10
	// Bit mask of PHY_TESTEN field.
	DSI_HOST_PHY_TST_CTRL1_PHY_TESTEN_Msk = 0x10000
	// Bit PHY_TESTEN.
	DSI_HOST_PHY_TST_CTRL1_PHY_TESTEN = 0x10000

	// INT_ST0: NA
	// Position of ACK_WITH_ERR_0 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_0_Pos = 0x0
	// Bit mask of ACK_WITH_ERR_0 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_0_Msk = 0x1
	// Bit ACK_WITH_ERR_0.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_0 = 0x1
	// Position of ACK_WITH_ERR_1 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_1_Pos = 0x1
	// Bit mask of ACK_WITH_ERR_1 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_1_Msk = 0x2
	// Bit ACK_WITH_ERR_1.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_1 = 0x2
	// Position of ACK_WITH_ERR_2 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_2_Pos = 0x2
	// Bit mask of ACK_WITH_ERR_2 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_2_Msk = 0x4
	// Bit ACK_WITH_ERR_2.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_2 = 0x4
	// Position of ACK_WITH_ERR_3 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_3_Pos = 0x3
	// Bit mask of ACK_WITH_ERR_3 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_3_Msk = 0x8
	// Bit ACK_WITH_ERR_3.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_3 = 0x8
	// Position of ACK_WITH_ERR_4 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_4_Pos = 0x4
	// Bit mask of ACK_WITH_ERR_4 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_4_Msk = 0x10
	// Bit ACK_WITH_ERR_4.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_4 = 0x10
	// Position of ACK_WITH_ERR_5 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_5_Pos = 0x5
	// Bit mask of ACK_WITH_ERR_5 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_5_Msk = 0x20
	// Bit ACK_WITH_ERR_5.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_5 = 0x20
	// Position of ACK_WITH_ERR_6 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_6_Pos = 0x6
	// Bit mask of ACK_WITH_ERR_6 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_6_Msk = 0x40
	// Bit ACK_WITH_ERR_6.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_6 = 0x40
	// Position of ACK_WITH_ERR_7 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_7_Pos = 0x7
	// Bit mask of ACK_WITH_ERR_7 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_7_Msk = 0x80
	// Bit ACK_WITH_ERR_7.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_7 = 0x80
	// Position of ACK_WITH_ERR_8 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_8_Pos = 0x8
	// Bit mask of ACK_WITH_ERR_8 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_8_Msk = 0x100
	// Bit ACK_WITH_ERR_8.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_8 = 0x100
	// Position of ACK_WITH_ERR_9 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_9_Pos = 0x9
	// Bit mask of ACK_WITH_ERR_9 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_9_Msk = 0x200
	// Bit ACK_WITH_ERR_9.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_9 = 0x200
	// Position of ACK_WITH_ERR_10 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_10_Pos = 0xa
	// Bit mask of ACK_WITH_ERR_10 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_10_Msk = 0x400
	// Bit ACK_WITH_ERR_10.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_10 = 0x400
	// Position of ACK_WITH_ERR_11 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_11_Pos = 0xb
	// Bit mask of ACK_WITH_ERR_11 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_11_Msk = 0x800
	// Bit ACK_WITH_ERR_11.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_11 = 0x800
	// Position of ACK_WITH_ERR_12 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_12_Pos = 0xc
	// Bit mask of ACK_WITH_ERR_12 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_12_Msk = 0x1000
	// Bit ACK_WITH_ERR_12.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_12 = 0x1000
	// Position of ACK_WITH_ERR_13 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_13_Pos = 0xd
	// Bit mask of ACK_WITH_ERR_13 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_13_Msk = 0x2000
	// Bit ACK_WITH_ERR_13.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_13 = 0x2000
	// Position of ACK_WITH_ERR_14 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_14_Pos = 0xe
	// Bit mask of ACK_WITH_ERR_14 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_14_Msk = 0x4000
	// Bit ACK_WITH_ERR_14.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_14 = 0x4000
	// Position of ACK_WITH_ERR_15 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_15_Pos = 0xf
	// Bit mask of ACK_WITH_ERR_15 field.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_15_Msk = 0x8000
	// Bit ACK_WITH_ERR_15.
	DSI_HOST_INT_ST0_ACK_WITH_ERR_15 = 0x8000
	// Position of DPHY_ERRORS_0 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_0_Pos = 0x10
	// Bit mask of DPHY_ERRORS_0 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_0_Msk = 0x10000
	// Bit DPHY_ERRORS_0.
	DSI_HOST_INT_ST0_DPHY_ERRORS_0 = 0x10000
	// Position of DPHY_ERRORS_1 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_1_Pos = 0x11
	// Bit mask of DPHY_ERRORS_1 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_1_Msk = 0x20000
	// Bit DPHY_ERRORS_1.
	DSI_HOST_INT_ST0_DPHY_ERRORS_1 = 0x20000
	// Position of DPHY_ERRORS_2 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_2_Pos = 0x12
	// Bit mask of DPHY_ERRORS_2 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_2_Msk = 0x40000
	// Bit DPHY_ERRORS_2.
	DSI_HOST_INT_ST0_DPHY_ERRORS_2 = 0x40000
	// Position of DPHY_ERRORS_3 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_3_Pos = 0x13
	// Bit mask of DPHY_ERRORS_3 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_3_Msk = 0x80000
	// Bit DPHY_ERRORS_3.
	DSI_HOST_INT_ST0_DPHY_ERRORS_3 = 0x80000
	// Position of DPHY_ERRORS_4 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_4_Pos = 0x14
	// Bit mask of DPHY_ERRORS_4 field.
	DSI_HOST_INT_ST0_DPHY_ERRORS_4_Msk = 0x100000
	// Bit DPHY_ERRORS_4.
	DSI_HOST_INT_ST0_DPHY_ERRORS_4 = 0x100000

	// INT_ST1: NA
	// Position of TO_HS_TX field.
	DSI_HOST_INT_ST1_TO_HS_TX_Pos = 0x0
	// Bit mask of TO_HS_TX field.
	DSI_HOST_INT_ST1_TO_HS_TX_Msk = 0x1
	// Bit TO_HS_TX.
	DSI_HOST_INT_ST1_TO_HS_TX = 0x1
	// Position of TO_LP_RX field.
	DSI_HOST_INT_ST1_TO_LP_RX_Pos = 0x1
	// Bit mask of TO_LP_RX field.
	DSI_HOST_INT_ST1_TO_LP_RX_Msk = 0x2
	// Bit TO_LP_RX.
	DSI_HOST_INT_ST1_TO_LP_RX = 0x2
	// Position of ECC_SINGLE_ERR field.
	DSI_HOST_INT_ST1_ECC_SINGLE_ERR_Pos = 0x2
	// Bit mask of ECC_SINGLE_ERR field.
	DSI_HOST_INT_ST1_ECC_SINGLE_ERR_Msk = 0x4
	// Bit ECC_SINGLE_ERR.
	DSI_HOST_INT_ST1_ECC_SINGLE_ERR = 0x4
	// Position of ECC_MILTI_ERR field.
	DSI_HOST_INT_ST1_ECC_MILTI_ERR_Pos = 0x3
	// Bit mask of ECC_MILTI_ERR field.
	DSI_HOST_INT_ST1_ECC_MILTI_ERR_Msk = 0x8
	// Bit ECC_MILTI_ERR.
	DSI_HOST_INT_ST1_ECC_MILTI_ERR = 0x8
	// Position of CRC_ERR field.
	DSI_HOST_INT_ST1_CRC_ERR_Pos = 0x4
	// Bit mask of CRC_ERR field.
	DSI_HOST_INT_ST1_CRC_ERR_Msk = 0x10
	// Bit CRC_ERR.
	DSI_HOST_INT_ST1_CRC_ERR = 0x10
	// Position of PKT_SIZE_ERR field.
	DSI_HOST_INT_ST1_PKT_SIZE_ERR_Pos = 0x5
	// Bit mask of PKT_SIZE_ERR field.
	DSI_HOST_INT_ST1_PKT_SIZE_ERR_Msk = 0x20
	// Bit PKT_SIZE_ERR.
	DSI_HOST_INT_ST1_PKT_SIZE_ERR = 0x20
	// Position of EOPT_ERR field.
	DSI_HOST_INT_ST1_EOPT_ERR_Pos = 0x6
	// Bit mask of EOPT_ERR field.
	DSI_HOST_INT_ST1_EOPT_ERR_Msk = 0x40
	// Bit EOPT_ERR.
	DSI_HOST_INT_ST1_EOPT_ERR = 0x40
	// Position of DPI_PLD_WR_ERR field.
	DSI_HOST_INT_ST1_DPI_PLD_WR_ERR_Pos = 0x7
	// Bit mask of DPI_PLD_WR_ERR field.
	DSI_HOST_INT_ST1_DPI_PLD_WR_ERR_Msk = 0x80
	// Bit DPI_PLD_WR_ERR.
	DSI_HOST_INT_ST1_DPI_PLD_WR_ERR = 0x80
	// Position of GEN_CMD_WR_ERR field.
	DSI_HOST_INT_ST1_GEN_CMD_WR_ERR_Pos = 0x8
	// Bit mask of GEN_CMD_WR_ERR field.
	DSI_HOST_INT_ST1_GEN_CMD_WR_ERR_Msk = 0x100
	// Bit GEN_CMD_WR_ERR.
	DSI_HOST_INT_ST1_GEN_CMD_WR_ERR = 0x100
	// Position of GEN_PLD_WR_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_WR_ERR_Pos = 0x9
	// Bit mask of GEN_PLD_WR_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_WR_ERR_Msk = 0x200
	// Bit GEN_PLD_WR_ERR.
	DSI_HOST_INT_ST1_GEN_PLD_WR_ERR = 0x200
	// Position of GEN_PLD_SEND_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_SEND_ERR_Pos = 0xa
	// Bit mask of GEN_PLD_SEND_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_SEND_ERR_Msk = 0x400
	// Bit GEN_PLD_SEND_ERR.
	DSI_HOST_INT_ST1_GEN_PLD_SEND_ERR = 0x400
	// Position of GEN_PLD_RD_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_RD_ERR_Pos = 0xb
	// Bit mask of GEN_PLD_RD_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_RD_ERR_Msk = 0x800
	// Bit GEN_PLD_RD_ERR.
	DSI_HOST_INT_ST1_GEN_PLD_RD_ERR = 0x800
	// Position of GEN_PLD_RECEV_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_RECEV_ERR_Pos = 0xc
	// Bit mask of GEN_PLD_RECEV_ERR field.
	DSI_HOST_INT_ST1_GEN_PLD_RECEV_ERR_Msk = 0x1000
	// Bit GEN_PLD_RECEV_ERR.
	DSI_HOST_INT_ST1_GEN_PLD_RECEV_ERR = 0x1000
	// Position of DPI_BUFF_PLD_UNDER field.
	DSI_HOST_INT_ST1_DPI_BUFF_PLD_UNDER_Pos = 0x13
	// Bit mask of DPI_BUFF_PLD_UNDER field.
	DSI_HOST_INT_ST1_DPI_BUFF_PLD_UNDER_Msk = 0x80000
	// Bit DPI_BUFF_PLD_UNDER.
	DSI_HOST_INT_ST1_DPI_BUFF_PLD_UNDER = 0x80000

	// INT_MSK0: NA
	// Position of MASK_ACK_WITH_ERR_0 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_0_Pos = 0x0
	// Bit mask of MASK_ACK_WITH_ERR_0 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_0_Msk = 0x1
	// Bit MASK_ACK_WITH_ERR_0.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_0 = 0x1
	// Position of MASK_ACK_WITH_ERR_1 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_1_Pos = 0x1
	// Bit mask of MASK_ACK_WITH_ERR_1 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_1_Msk = 0x2
	// Bit MASK_ACK_WITH_ERR_1.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_1 = 0x2
	// Position of MASK_ACK_WITH_ERR_2 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_2_Pos = 0x2
	// Bit mask of MASK_ACK_WITH_ERR_2 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_2_Msk = 0x4
	// Bit MASK_ACK_WITH_ERR_2.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_2 = 0x4
	// Position of MASK_ACK_WITH_ERR_3 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_3_Pos = 0x3
	// Bit mask of MASK_ACK_WITH_ERR_3 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_3_Msk = 0x8
	// Bit MASK_ACK_WITH_ERR_3.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_3 = 0x8
	// Position of MASK_ACK_WITH_ERR_4 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_4_Pos = 0x4
	// Bit mask of MASK_ACK_WITH_ERR_4 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_4_Msk = 0x10
	// Bit MASK_ACK_WITH_ERR_4.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_4 = 0x10
	// Position of MASK_ACK_WITH_ERR_5 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_5_Pos = 0x5
	// Bit mask of MASK_ACK_WITH_ERR_5 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_5_Msk = 0x20
	// Bit MASK_ACK_WITH_ERR_5.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_5 = 0x20
	// Position of MASK_ACK_WITH_ERR_6 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_6_Pos = 0x6
	// Bit mask of MASK_ACK_WITH_ERR_6 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_6_Msk = 0x40
	// Bit MASK_ACK_WITH_ERR_6.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_6 = 0x40
	// Position of MASK_ACK_WITH_ERR_7 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_7_Pos = 0x7
	// Bit mask of MASK_ACK_WITH_ERR_7 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_7_Msk = 0x80
	// Bit MASK_ACK_WITH_ERR_7.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_7 = 0x80
	// Position of MASK_ACK_WITH_ERR_8 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_8_Pos = 0x8
	// Bit mask of MASK_ACK_WITH_ERR_8 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_8_Msk = 0x100
	// Bit MASK_ACK_WITH_ERR_8.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_8 = 0x100
	// Position of MASK_ACK_WITH_ERR_9 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_9_Pos = 0x9
	// Bit mask of MASK_ACK_WITH_ERR_9 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_9_Msk = 0x200
	// Bit MASK_ACK_WITH_ERR_9.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_9 = 0x200
	// Position of MASK_ACK_WITH_ERR_10 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_10_Pos = 0xa
	// Bit mask of MASK_ACK_WITH_ERR_10 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_10_Msk = 0x400
	// Bit MASK_ACK_WITH_ERR_10.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_10 = 0x400
	// Position of MASK_ACK_WITH_ERR_11 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_11_Pos = 0xb
	// Bit mask of MASK_ACK_WITH_ERR_11 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_11_Msk = 0x800
	// Bit MASK_ACK_WITH_ERR_11.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_11 = 0x800
	// Position of MASK_ACK_WITH_ERR_12 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_12_Pos = 0xc
	// Bit mask of MASK_ACK_WITH_ERR_12 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_12_Msk = 0x1000
	// Bit MASK_ACK_WITH_ERR_12.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_12 = 0x1000
	// Position of MASK_ACK_WITH_ERR_13 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_13_Pos = 0xd
	// Bit mask of MASK_ACK_WITH_ERR_13 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_13_Msk = 0x2000
	// Bit MASK_ACK_WITH_ERR_13.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_13 = 0x2000
	// Position of MASK_ACK_WITH_ERR_14 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_14_Pos = 0xe
	// Bit mask of MASK_ACK_WITH_ERR_14 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_14_Msk = 0x4000
	// Bit MASK_ACK_WITH_ERR_14.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_14 = 0x4000
	// Position of MASK_ACK_WITH_ERR_15 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_15_Pos = 0xf
	// Bit mask of MASK_ACK_WITH_ERR_15 field.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_15_Msk = 0x8000
	// Bit MASK_ACK_WITH_ERR_15.
	DSI_HOST_INT_MSK0_MASK_ACK_WITH_ERR_15 = 0x8000
	// Position of MASK_DPHY_ERRORS_0 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_0_Pos = 0x10
	// Bit mask of MASK_DPHY_ERRORS_0 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_0_Msk = 0x10000
	// Bit MASK_DPHY_ERRORS_0.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_0 = 0x10000
	// Position of MASK_DPHY_ERRORS_1 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_1_Pos = 0x11
	// Bit mask of MASK_DPHY_ERRORS_1 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_1_Msk = 0x20000
	// Bit MASK_DPHY_ERRORS_1.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_1 = 0x20000
	// Position of MASK_DPHY_ERRORS_2 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_2_Pos = 0x12
	// Bit mask of MASK_DPHY_ERRORS_2 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_2_Msk = 0x40000
	// Bit MASK_DPHY_ERRORS_2.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_2 = 0x40000
	// Position of MASK_DPHY_ERRORS_3 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_3_Pos = 0x13
	// Bit mask of MASK_DPHY_ERRORS_3 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_3_Msk = 0x80000
	// Bit MASK_DPHY_ERRORS_3.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_3 = 0x80000
	// Position of MASK_DPHY_ERRORS_4 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_4_Pos = 0x14
	// Bit mask of MASK_DPHY_ERRORS_4 field.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_4_Msk = 0x100000
	// Bit MASK_DPHY_ERRORS_4.
	DSI_HOST_INT_MSK0_MASK_DPHY_ERRORS_4 = 0x100000

	// INT_MSK1: NA
	// Position of MASK_TO_HS_TX field.
	DSI_HOST_INT_MSK1_MASK_TO_HS_TX_Pos = 0x0
	// Bit mask of MASK_TO_HS_TX field.
	DSI_HOST_INT_MSK1_MASK_TO_HS_TX_Msk = 0x1
	// Bit MASK_TO_HS_TX.
	DSI_HOST_INT_MSK1_MASK_TO_HS_TX = 0x1
	// Position of MASK_TO_LP_RX field.
	DSI_HOST_INT_MSK1_MASK_TO_LP_RX_Pos = 0x1
	// Bit mask of MASK_TO_LP_RX field.
	DSI_HOST_INT_MSK1_MASK_TO_LP_RX_Msk = 0x2
	// Bit MASK_TO_LP_RX.
	DSI_HOST_INT_MSK1_MASK_TO_LP_RX = 0x2
	// Position of MASK_ECC_SINGLE_ERR field.
	DSI_HOST_INT_MSK1_MASK_ECC_SINGLE_ERR_Pos = 0x2
	// Bit mask of MASK_ECC_SINGLE_ERR field.
	DSI_HOST_INT_MSK1_MASK_ECC_SINGLE_ERR_Msk = 0x4
	// Bit MASK_ECC_SINGLE_ERR.
	DSI_HOST_INT_MSK1_MASK_ECC_SINGLE_ERR = 0x4
	// Position of MASK_ECC_MILTI_ERR field.
	DSI_HOST_INT_MSK1_MASK_ECC_MILTI_ERR_Pos = 0x3
	// Bit mask of MASK_ECC_MILTI_ERR field.
	DSI_HOST_INT_MSK1_MASK_ECC_MILTI_ERR_Msk = 0x8
	// Bit MASK_ECC_MILTI_ERR.
	DSI_HOST_INT_MSK1_MASK_ECC_MILTI_ERR = 0x8
	// Position of MASK_CRC_ERR field.
	DSI_HOST_INT_MSK1_MASK_CRC_ERR_Pos = 0x4
	// Bit mask of MASK_CRC_ERR field.
	DSI_HOST_INT_MSK1_MASK_CRC_ERR_Msk = 0x10
	// Bit MASK_CRC_ERR.
	DSI_HOST_INT_MSK1_MASK_CRC_ERR = 0x10
	// Position of MASK_PKT_SIZE_ERR field.
	DSI_HOST_INT_MSK1_MASK_PKT_SIZE_ERR_Pos = 0x5
	// Bit mask of MASK_PKT_SIZE_ERR field.
	DSI_HOST_INT_MSK1_MASK_PKT_SIZE_ERR_Msk = 0x20
	// Bit MASK_PKT_SIZE_ERR.
	DSI_HOST_INT_MSK1_MASK_PKT_SIZE_ERR = 0x20
	// Position of MASK_EOPT_ERR field.
	DSI_HOST_INT_MSK1_MASK_EOPT_ERR_Pos = 0x6
	// Bit mask of MASK_EOPT_ERR field.
	DSI_HOST_INT_MSK1_MASK_EOPT_ERR_Msk = 0x40
	// Bit MASK_EOPT_ERR.
	DSI_HOST_INT_MSK1_MASK_EOPT_ERR = 0x40
	// Position of MASK_DPI_PLD_WR_ERR field.
	DSI_HOST_INT_MSK1_MASK_DPI_PLD_WR_ERR_Pos = 0x7
	// Bit mask of MASK_DPI_PLD_WR_ERR field.
	DSI_HOST_INT_MSK1_MASK_DPI_PLD_WR_ERR_Msk = 0x80
	// Bit MASK_DPI_PLD_WR_ERR.
	DSI_HOST_INT_MSK1_MASK_DPI_PLD_WR_ERR = 0x80
	// Position of MASK_GEN_CMD_WR_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_CMD_WR_ERR_Pos = 0x8
	// Bit mask of MASK_GEN_CMD_WR_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_CMD_WR_ERR_Msk = 0x100
	// Bit MASK_GEN_CMD_WR_ERR.
	DSI_HOST_INT_MSK1_MASK_GEN_CMD_WR_ERR = 0x100
	// Position of MASK_GEN_PLD_WR_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_WR_ERR_Pos = 0x9
	// Bit mask of MASK_GEN_PLD_WR_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_WR_ERR_Msk = 0x200
	// Bit MASK_GEN_PLD_WR_ERR.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_WR_ERR = 0x200
	// Position of MASK_GEN_PLD_SEND_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_SEND_ERR_Pos = 0xa
	// Bit mask of MASK_GEN_PLD_SEND_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_SEND_ERR_Msk = 0x400
	// Bit MASK_GEN_PLD_SEND_ERR.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_SEND_ERR = 0x400
	// Position of MASK_GEN_PLD_RD_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_RD_ERR_Pos = 0xb
	// Bit mask of MASK_GEN_PLD_RD_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_RD_ERR_Msk = 0x800
	// Bit MASK_GEN_PLD_RD_ERR.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_RD_ERR = 0x800
	// Position of MASK_GEN_PLD_RECEV_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_Pos = 0xc
	// Bit mask of MASK_GEN_PLD_RECEV_ERR field.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_Msk = 0x1000
	// Bit MASK_GEN_PLD_RECEV_ERR.
	DSI_HOST_INT_MSK1_MASK_GEN_PLD_RECEV_ERR = 0x1000
	// Position of MASK_DPI_BUFF_PLD_UNDER field.
	DSI_HOST_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_Pos = 0x13
	// Bit mask of MASK_DPI_BUFF_PLD_UNDER field.
	DSI_HOST_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_Msk = 0x80000
	// Bit MASK_DPI_BUFF_PLD_UNDER.
	DSI_HOST_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER = 0x80000

	// PHY_CAL: NA
	// Position of TXSKEWCALHS field.
	DSI_HOST_PHY_CAL_TXSKEWCALHS_Pos = 0x0
	// Bit mask of TXSKEWCALHS field.
	DSI_HOST_PHY_CAL_TXSKEWCALHS_Msk = 0x1
	// Bit TXSKEWCALHS.
	DSI_HOST_PHY_CAL_TXSKEWCALHS = 0x1

	// INT_FORCE0: NA
	// Position of FORCE_ACK_WITH_ERR_0 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_0_Pos = 0x0
	// Bit mask of FORCE_ACK_WITH_ERR_0 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_0_Msk = 0x1
	// Bit FORCE_ACK_WITH_ERR_0.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_0 = 0x1
	// Position of FORCE_ACK_WITH_ERR_1 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_1_Pos = 0x1
	// Bit mask of FORCE_ACK_WITH_ERR_1 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_1_Msk = 0x2
	// Bit FORCE_ACK_WITH_ERR_1.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_1 = 0x2
	// Position of FORCE_ACK_WITH_ERR_2 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_2_Pos = 0x2
	// Bit mask of FORCE_ACK_WITH_ERR_2 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_2_Msk = 0x4
	// Bit FORCE_ACK_WITH_ERR_2.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_2 = 0x4
	// Position of FORCE_ACK_WITH_ERR_3 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_3_Pos = 0x3
	// Bit mask of FORCE_ACK_WITH_ERR_3 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_3_Msk = 0x8
	// Bit FORCE_ACK_WITH_ERR_3.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_3 = 0x8
	// Position of FORCE_ACK_WITH_ERR_4 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_4_Pos = 0x4
	// Bit mask of FORCE_ACK_WITH_ERR_4 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_4_Msk = 0x10
	// Bit FORCE_ACK_WITH_ERR_4.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_4 = 0x10
	// Position of FORCE_ACK_WITH_ERR_5 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_5_Pos = 0x5
	// Bit mask of FORCE_ACK_WITH_ERR_5 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_5_Msk = 0x20
	// Bit FORCE_ACK_WITH_ERR_5.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_5 = 0x20
	// Position of FORCE_ACK_WITH_ERR_6 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_6_Pos = 0x6
	// Bit mask of FORCE_ACK_WITH_ERR_6 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_6_Msk = 0x40
	// Bit FORCE_ACK_WITH_ERR_6.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_6 = 0x40
	// Position of FORCE_ACK_WITH_ERR_7 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_7_Pos = 0x7
	// Bit mask of FORCE_ACK_WITH_ERR_7 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_7_Msk = 0x80
	// Bit FORCE_ACK_WITH_ERR_7.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_7 = 0x80
	// Position of FORCE_ACK_WITH_ERR_8 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_8_Pos = 0x8
	// Bit mask of FORCE_ACK_WITH_ERR_8 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_8_Msk = 0x100
	// Bit FORCE_ACK_WITH_ERR_8.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_8 = 0x100
	// Position of FORCE_ACK_WITH_ERR_9 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_9_Pos = 0x9
	// Bit mask of FORCE_ACK_WITH_ERR_9 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_9_Msk = 0x200
	// Bit FORCE_ACK_WITH_ERR_9.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_9 = 0x200
	// Position of FORCE_ACK_WITH_ERR_10 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_10_Pos = 0xa
	// Bit mask of FORCE_ACK_WITH_ERR_10 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_10_Msk = 0x400
	// Bit FORCE_ACK_WITH_ERR_10.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_10 = 0x400
	// Position of FORCE_ACK_WITH_ERR_11 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_11_Pos = 0xb
	// Bit mask of FORCE_ACK_WITH_ERR_11 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_11_Msk = 0x800
	// Bit FORCE_ACK_WITH_ERR_11.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_11 = 0x800
	// Position of FORCE_ACK_WITH_ERR_12 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_12_Pos = 0xc
	// Bit mask of FORCE_ACK_WITH_ERR_12 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_12_Msk = 0x1000
	// Bit FORCE_ACK_WITH_ERR_12.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_12 = 0x1000
	// Position of FORCE_ACK_WITH_ERR_13 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_13_Pos = 0xd
	// Bit mask of FORCE_ACK_WITH_ERR_13 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_13_Msk = 0x2000
	// Bit FORCE_ACK_WITH_ERR_13.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_13 = 0x2000
	// Position of FORCE_ACK_WITH_ERR_14 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_14_Pos = 0xe
	// Bit mask of FORCE_ACK_WITH_ERR_14 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_14_Msk = 0x4000
	// Bit FORCE_ACK_WITH_ERR_14.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_14 = 0x4000
	// Position of FORCE_ACK_WITH_ERR_15 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_15_Pos = 0xf
	// Bit mask of FORCE_ACK_WITH_ERR_15 field.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_15_Msk = 0x8000
	// Bit FORCE_ACK_WITH_ERR_15.
	DSI_HOST_INT_FORCE0_FORCE_ACK_WITH_ERR_15 = 0x8000
	// Position of FORCE_DPHY_ERRORS_0 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_0_Pos = 0x10
	// Bit mask of FORCE_DPHY_ERRORS_0 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_0_Msk = 0x10000
	// Bit FORCE_DPHY_ERRORS_0.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_0 = 0x10000
	// Position of FORCE_DPHY_ERRORS_1 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_1_Pos = 0x11
	// Bit mask of FORCE_DPHY_ERRORS_1 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_1_Msk = 0x20000
	// Bit FORCE_DPHY_ERRORS_1.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_1 = 0x20000
	// Position of FORCE_DPHY_ERRORS_2 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_2_Pos = 0x12
	// Bit mask of FORCE_DPHY_ERRORS_2 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_2_Msk = 0x40000
	// Bit FORCE_DPHY_ERRORS_2.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_2 = 0x40000
	// Position of FORCE_DPHY_ERRORS_3 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_3_Pos = 0x13
	// Bit mask of FORCE_DPHY_ERRORS_3 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_3_Msk = 0x80000
	// Bit FORCE_DPHY_ERRORS_3.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_3 = 0x80000
	// Position of FORCE_DPHY_ERRORS_4 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_4_Pos = 0x14
	// Bit mask of FORCE_DPHY_ERRORS_4 field.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_4_Msk = 0x100000
	// Bit FORCE_DPHY_ERRORS_4.
	DSI_HOST_INT_FORCE0_FORCE_DPHY_ERRORS_4 = 0x100000

	// INT_FORCE1: NA
	// Position of FORCE_TO_HS_TX field.
	DSI_HOST_INT_FORCE1_FORCE_TO_HS_TX_Pos = 0x0
	// Bit mask of FORCE_TO_HS_TX field.
	DSI_HOST_INT_FORCE1_FORCE_TO_HS_TX_Msk = 0x1
	// Bit FORCE_TO_HS_TX.
	DSI_HOST_INT_FORCE1_FORCE_TO_HS_TX = 0x1
	// Position of FORCE_TO_LP_RX field.
	DSI_HOST_INT_FORCE1_FORCE_TO_LP_RX_Pos = 0x1
	// Bit mask of FORCE_TO_LP_RX field.
	DSI_HOST_INT_FORCE1_FORCE_TO_LP_RX_Msk = 0x2
	// Bit FORCE_TO_LP_RX.
	DSI_HOST_INT_FORCE1_FORCE_TO_LP_RX = 0x2
	// Position of FORCE_ECC_SINGLE_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_ECC_SINGLE_ERR_Pos = 0x2
	// Bit mask of FORCE_ECC_SINGLE_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_ECC_SINGLE_ERR_Msk = 0x4
	// Bit FORCE_ECC_SINGLE_ERR.
	DSI_HOST_INT_FORCE1_FORCE_ECC_SINGLE_ERR = 0x4
	// Position of FORCE_ECC_MILTI_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_ECC_MILTI_ERR_Pos = 0x3
	// Bit mask of FORCE_ECC_MILTI_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_ECC_MILTI_ERR_Msk = 0x8
	// Bit FORCE_ECC_MILTI_ERR.
	DSI_HOST_INT_FORCE1_FORCE_ECC_MILTI_ERR = 0x8
	// Position of FORCE_CRC_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_CRC_ERR_Pos = 0x4
	// Bit mask of FORCE_CRC_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_CRC_ERR_Msk = 0x10
	// Bit FORCE_CRC_ERR.
	DSI_HOST_INT_FORCE1_FORCE_CRC_ERR = 0x10
	// Position of FORCE_PKT_SIZE_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_PKT_SIZE_ERR_Pos = 0x5
	// Bit mask of FORCE_PKT_SIZE_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_PKT_SIZE_ERR_Msk = 0x20
	// Bit FORCE_PKT_SIZE_ERR.
	DSI_HOST_INT_FORCE1_FORCE_PKT_SIZE_ERR = 0x20
	// Position of FORCE_EOPT_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_EOPT_ERR_Pos = 0x6
	// Bit mask of FORCE_EOPT_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_EOPT_ERR_Msk = 0x40
	// Bit FORCE_EOPT_ERR.
	DSI_HOST_INT_FORCE1_FORCE_EOPT_ERR = 0x40
	// Position of FORCE_DPI_PLD_WR_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_DPI_PLD_WR_ERR_Pos = 0x7
	// Bit mask of FORCE_DPI_PLD_WR_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_DPI_PLD_WR_ERR_Msk = 0x80
	// Bit FORCE_DPI_PLD_WR_ERR.
	DSI_HOST_INT_FORCE1_FORCE_DPI_PLD_WR_ERR = 0x80
	// Position of FORCE_GEN_CMD_WR_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_Pos = 0x8
	// Bit mask of FORCE_GEN_CMD_WR_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_Msk = 0x100
	// Bit FORCE_GEN_CMD_WR_ERR.
	DSI_HOST_INT_FORCE1_FORCE_GEN_CMD_WR_ERR = 0x100
	// Position of FORCE_GEN_PLD_WR_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_Pos = 0x9
	// Bit mask of FORCE_GEN_PLD_WR_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_Msk = 0x200
	// Bit FORCE_GEN_PLD_WR_ERR.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_WR_ERR = 0x200
	// Position of FORCE_GEN_PLD_SEND_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_Pos = 0xa
	// Bit mask of FORCE_GEN_PLD_SEND_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_Msk = 0x400
	// Bit FORCE_GEN_PLD_SEND_ERR.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR = 0x400
	// Position of FORCE_GEN_PLD_RD_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_Pos = 0xb
	// Bit mask of FORCE_GEN_PLD_RD_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_Msk = 0x800
	// Bit FORCE_GEN_PLD_RD_ERR.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_RD_ERR = 0x800
	// Position of FORCE_GEN_PLD_RECEV_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_Pos = 0xc
	// Bit mask of FORCE_GEN_PLD_RECEV_ERR field.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_Msk = 0x1000
	// Bit FORCE_GEN_PLD_RECEV_ERR.
	DSI_HOST_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR = 0x1000
	// Position of FORCE_DPI_BUFF_PLD_UNDER field.
	DSI_HOST_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_Pos = 0x13
	// Bit mask of FORCE_DPI_BUFF_PLD_UNDER field.
	DSI_HOST_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_Msk = 0x80000
	// Bit FORCE_DPI_BUFF_PLD_UNDER.
	DSI_HOST_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER = 0x80000

	// DSC_PARAMETER: NA
	// Position of COMPRESSION_MODE field.
	DSI_HOST_DSC_PARAMETER_COMPRESSION_MODE_Pos = 0x0
	// Bit mask of COMPRESSION_MODE field.
	DSI_HOST_DSC_PARAMETER_COMPRESSION_MODE_Msk = 0x1
	// Bit COMPRESSION_MODE.
	DSI_HOST_DSC_PARAMETER_COMPRESSION_MODE = 0x1
	// Position of COMPRESS_ALGO field.
	DSI_HOST_DSC_PARAMETER_COMPRESS_ALGO_Pos = 0x8
	// Bit mask of COMPRESS_ALGO field.
	DSI_HOST_DSC_PARAMETER_COMPRESS_ALGO_Msk = 0x300
	// Position of PPS_SEL field.
	DSI_HOST_DSC_PARAMETER_PPS_SEL_Pos = 0x10
	// Bit mask of PPS_SEL field.
	DSI_HOST_DSC_PARAMETER_PPS_SEL_Msk = 0x30000

	// PHY_TMR_RD_CFG: NA
	// Position of MAX_RD_TIME field.
	DSI_HOST_PHY_TMR_RD_CFG_MAX_RD_TIME_Pos = 0x0
	// Bit mask of MAX_RD_TIME field.
	DSI_HOST_PHY_TMR_RD_CFG_MAX_RD_TIME_Msk = 0x7fff

	// VID_SHADOW_CTRL: NA
	// Position of VID_SHADOW_EN field.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_EN_Pos = 0x0
	// Bit mask of VID_SHADOW_EN field.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_EN_Msk = 0x1
	// Bit VID_SHADOW_EN.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_EN = 0x1
	// Position of VID_SHADOW_REQ field.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_REQ_Pos = 0x8
	// Bit mask of VID_SHADOW_REQ field.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_REQ_Msk = 0x100
	// Bit VID_SHADOW_REQ.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_REQ = 0x100
	// Position of VID_SHADOW_PIN_REQ field.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_Pos = 0x10
	// Bit mask of VID_SHADOW_PIN_REQ field.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_Msk = 0x10000
	// Bit VID_SHADOW_PIN_REQ.
	DSI_HOST_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ = 0x10000

	// DPI_VCID_ACT: NA
	// Position of DPI_VCID_ACT field.
	DSI_HOST_DPI_VCID_ACT_DPI_VCID_ACT_Pos = 0x0
	// Bit mask of DPI_VCID_ACT field.
	DSI_HOST_DPI_VCID_ACT_DPI_VCID_ACT_Msk = 0x3

	// DPI_COLOR_CODING_ACT: NA
	// Position of DPI_COLOR_CODING_ACT field.
	DSI_HOST_DPI_COLOR_CODING_ACT_DPI_COLOR_CODING_ACT_Pos = 0x0
	// Bit mask of DPI_COLOR_CODING_ACT field.
	DSI_HOST_DPI_COLOR_CODING_ACT_DPI_COLOR_CODING_ACT_Msk = 0xf
	// Position of LOOSELY18_EN_ACT field.
	DSI_HOST_DPI_COLOR_CODING_ACT_LOOSELY18_EN_ACT_Pos = 0x8
	// Bit mask of LOOSELY18_EN_ACT field.
	DSI_HOST_DPI_COLOR_CODING_ACT_LOOSELY18_EN_ACT_Msk = 0x100
	// Bit LOOSELY18_EN_ACT.
	DSI_HOST_DPI_COLOR_CODING_ACT_LOOSELY18_EN_ACT = 0x100

	// DPI_LP_CMD_TIM_ACT: NA
	// Position of INVACT_LPCMD_TIME_ACT field.
	DSI_HOST_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_ACT_Pos = 0x0
	// Bit mask of INVACT_LPCMD_TIME_ACT field.
	DSI_HOST_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_ACT_Msk = 0xff
	// Position of OUTVACT_LPCMD_TIME_ACT field.
	DSI_HOST_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_ACT_Pos = 0x10
	// Bit mask of OUTVACT_LPCMD_TIME_ACT field.
	DSI_HOST_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_ACT_Msk = 0xff0000

	// EDPI_TE_HW_CFG: NA
	// Position of HW_TEAR_EFFECT_ON field.
	DSI_HOST_EDPI_TE_HW_CFG_HW_TEAR_EFFECT_ON_Pos = 0x0
	// Bit mask of HW_TEAR_EFFECT_ON field.
	DSI_HOST_EDPI_TE_HW_CFG_HW_TEAR_EFFECT_ON_Msk = 0x1
	// Bit HW_TEAR_EFFECT_ON.
	DSI_HOST_EDPI_TE_HW_CFG_HW_TEAR_EFFECT_ON = 0x1
	// Position of HW_TEAR_EFFECT_GEN field.
	DSI_HOST_EDPI_TE_HW_CFG_HW_TEAR_EFFECT_GEN_Pos = 0x1
	// Bit mask of HW_TEAR_EFFECT_GEN field.
	DSI_HOST_EDPI_TE_HW_CFG_HW_TEAR_EFFECT_GEN_Msk = 0x2
	// Bit HW_TEAR_EFFECT_GEN.
	DSI_HOST_EDPI_TE_HW_CFG_HW_TEAR_EFFECT_GEN = 0x2
	// Position of HW_SET_SCAN_LINE field.
	DSI_HOST_EDPI_TE_HW_CFG_HW_SET_SCAN_LINE_Pos = 0x4
	// Bit mask of HW_SET_SCAN_LINE field.
	DSI_HOST_EDPI_TE_HW_CFG_HW_SET_SCAN_LINE_Msk = 0x10
	// Bit HW_SET_SCAN_LINE.
	DSI_HOST_EDPI_TE_HW_CFG_HW_SET_SCAN_LINE = 0x10
	// Position of SCAN_LINE_PARAMETER field.
	DSI_HOST_EDPI_TE_HW_CFG_SCAN_LINE_PARAMETER_Pos = 0x10
	// Bit mask of SCAN_LINE_PARAMETER field.
	DSI_HOST_EDPI_TE_HW_CFG_SCAN_LINE_PARAMETER_Msk = 0xffff0000

	// VID_MODE_CFG_ACT: NA
	// Position of VID_MODE_TYPE_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_VID_MODE_TYPE_ACT_Pos = 0x0
	// Bit mask of VID_MODE_TYPE_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_VID_MODE_TYPE_ACT_Msk = 0x3
	// Position of LP_VSA_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VSA_EN_ACT_Pos = 0x2
	// Bit mask of LP_VSA_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VSA_EN_ACT_Msk = 0x4
	// Bit LP_VSA_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VSA_EN_ACT = 0x4
	// Position of LP_VBP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VBP_EN_ACT_Pos = 0x3
	// Bit mask of LP_VBP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VBP_EN_ACT_Msk = 0x8
	// Bit LP_VBP_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VBP_EN_ACT = 0x8
	// Position of LP_VFP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VFP_EN_ACT_Pos = 0x4
	// Bit mask of LP_VFP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VFP_EN_ACT_Msk = 0x10
	// Bit LP_VFP_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VFP_EN_ACT = 0x10
	// Position of LP_VACT_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VACT_EN_ACT_Pos = 0x5
	// Bit mask of LP_VACT_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VACT_EN_ACT_Msk = 0x20
	// Bit LP_VACT_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_LP_VACT_EN_ACT = 0x20
	// Position of LP_HBP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_HBP_EN_ACT_Pos = 0x6
	// Bit mask of LP_HBP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_HBP_EN_ACT_Msk = 0x40
	// Bit LP_HBP_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_LP_HBP_EN_ACT = 0x40
	// Position of LP_HFP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_HFP_EN_ACT_Pos = 0x7
	// Bit mask of LP_HFP_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_HFP_EN_ACT_Msk = 0x80
	// Bit LP_HFP_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_LP_HFP_EN_ACT = 0x80
	// Position of FRAME_BTA_ACK_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_ACT_Pos = 0x8
	// Bit mask of FRAME_BTA_ACK_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_ACT_Msk = 0x100
	// Bit FRAME_BTA_ACK_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_ACT = 0x100
	// Position of LP_CMD_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_CMD_EN_ACT_Pos = 0x9
	// Bit mask of LP_CMD_EN_ACT field.
	DSI_HOST_VID_MODE_CFG_ACT_LP_CMD_EN_ACT_Msk = 0x200
	// Bit LP_CMD_EN_ACT.
	DSI_HOST_VID_MODE_CFG_ACT_LP_CMD_EN_ACT = 0x200

	// VID_PKT_SIZE_ACT: NA
	// Position of VID_PKT_SIZE_ACT field.
	DSI_HOST_VID_PKT_SIZE_ACT_VID_PKT_SIZE_ACT_Pos = 0x0
	// Bit mask of VID_PKT_SIZE_ACT field.
	DSI_HOST_VID_PKT_SIZE_ACT_VID_PKT_SIZE_ACT_Msk = 0x3fff

	// VID_NUM_CHUNKS_ACT: NA
	// Position of VID_NUM_CHUNKS_ACT field.
	DSI_HOST_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_ACT_Pos = 0x0
	// Bit mask of VID_NUM_CHUNKS_ACT field.
	DSI_HOST_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_ACT_Msk = 0x1fff

	// VID_NULL_SIZE_ACT: NA
	// Position of VID_NULL_SIZE_ACT field.
	DSI_HOST_VID_NULL_SIZE_ACT_VID_NULL_SIZE_ACT_Pos = 0x0
	// Bit mask of VID_NULL_SIZE_ACT field.
	DSI_HOST_VID_NULL_SIZE_ACT_VID_NULL_SIZE_ACT_Msk = 0x1fff

	// VID_HSA_TIME_ACT: NA
	// Position of VID_HSA_TIME_ACT field.
	DSI_HOST_VID_HSA_TIME_ACT_VID_HSA_TIME_ACT_Pos = 0x0
	// Bit mask of VID_HSA_TIME_ACT field.
	DSI_HOST_VID_HSA_TIME_ACT_VID_HSA_TIME_ACT_Msk = 0xfff

	// VID_HBP_TIME_ACT: NA
	// Position of VID_HBP_TIME_ACT field.
	DSI_HOST_VID_HBP_TIME_ACT_VID_HBP_TIME_ACT_Pos = 0x0
	// Bit mask of VID_HBP_TIME_ACT field.
	DSI_HOST_VID_HBP_TIME_ACT_VID_HBP_TIME_ACT_Msk = 0xfff

	// VID_HLINE_TIME_ACT: NA
	// Position of VID_HLINE_TIME_ACT field.
	DSI_HOST_VID_HLINE_TIME_ACT_VID_HLINE_TIME_ACT_Pos = 0x0
	// Bit mask of VID_HLINE_TIME_ACT field.
	DSI_HOST_VID_HLINE_TIME_ACT_VID_HLINE_TIME_ACT_Msk = 0x7fff

	// VID_VSA_LINES_ACT: NA
	// Position of VSA_LINES_ACT field.
	DSI_HOST_VID_VSA_LINES_ACT_VSA_LINES_ACT_Pos = 0x0
	// Bit mask of VSA_LINES_ACT field.
	DSI_HOST_VID_VSA_LINES_ACT_VSA_LINES_ACT_Msk = 0x3ff

	// VID_VBP_LINES_ACT: NA
	// Position of VBP_LINES_ACT field.
	DSI_HOST_VID_VBP_LINES_ACT_VBP_LINES_ACT_Pos = 0x0
	// Bit mask of VBP_LINES_ACT field.
	DSI_HOST_VID_VBP_LINES_ACT_VBP_LINES_ACT_Msk = 0x3ff

	// VID_VFP_LINES_ACT: NA
	// Position of VFP_LINES_ACT field.
	DSI_HOST_VID_VFP_LINES_ACT_VFP_LINES_ACT_Pos = 0x0
	// Bit mask of VFP_LINES_ACT field.
	DSI_HOST_VID_VFP_LINES_ACT_VFP_LINES_ACT_Msk = 0x3ff

	// VID_VACTIVE_LINES_ACT: NA
	// Position of V_ACTIVE_LINES_ACT field.
	DSI_HOST_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_ACT_Pos = 0x0
	// Bit mask of V_ACTIVE_LINES_ACT field.
	DSI_HOST_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_ACT_Msk = 0x3fff

	// VID_PKT_STATUS: NA
	// Position of DPI_CMD_W_EMPTY field.
	DSI_HOST_VID_PKT_STATUS_DPI_CMD_W_EMPTY_Pos = 0x0
	// Bit mask of DPI_CMD_W_EMPTY field.
	DSI_HOST_VID_PKT_STATUS_DPI_CMD_W_EMPTY_Msk = 0x1
	// Bit DPI_CMD_W_EMPTY.
	DSI_HOST_VID_PKT_STATUS_DPI_CMD_W_EMPTY = 0x1
	// Position of DPI_CMD_W_FULL field.
	DSI_HOST_VID_PKT_STATUS_DPI_CMD_W_FULL_Pos = 0x1
	// Bit mask of DPI_CMD_W_FULL field.
	DSI_HOST_VID_PKT_STATUS_DPI_CMD_W_FULL_Msk = 0x2
	// Bit DPI_CMD_W_FULL.
	DSI_HOST_VID_PKT_STATUS_DPI_CMD_W_FULL = 0x2
	// Position of DPI_PLD_W_EMPTY field.
	DSI_HOST_VID_PKT_STATUS_DPI_PLD_W_EMPTY_Pos = 0x2
	// Bit mask of DPI_PLD_W_EMPTY field.
	DSI_HOST_VID_PKT_STATUS_DPI_PLD_W_EMPTY_Msk = 0x4
	// Bit DPI_PLD_W_EMPTY.
	DSI_HOST_VID_PKT_STATUS_DPI_PLD_W_EMPTY = 0x4
	// Position of DPI_PLD_W_FULL field.
	DSI_HOST_VID_PKT_STATUS_DPI_PLD_W_FULL_Pos = 0x3
	// Bit mask of DPI_PLD_W_FULL field.
	DSI_HOST_VID_PKT_STATUS_DPI_PLD_W_FULL_Msk = 0x8
	// Bit DPI_PLD_W_FULL.
	DSI_HOST_VID_PKT_STATUS_DPI_PLD_W_FULL = 0x8
	// Position of DPI_BUFF_PLD_EMPTY field.
	DSI_HOST_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_Pos = 0x10
	// Bit mask of DPI_BUFF_PLD_EMPTY field.
	DSI_HOST_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_Msk = 0x10000
	// Bit DPI_BUFF_PLD_EMPTY.
	DSI_HOST_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY = 0x10000
	// Position of DPI_BUFF_PLD_FULL field.
	DSI_HOST_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_Pos = 0x11
	// Bit mask of DPI_BUFF_PLD_FULL field.
	DSI_HOST_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_Msk = 0x20000
	// Bit DPI_BUFF_PLD_FULL.
	DSI_HOST_VID_PKT_STATUS_DPI_BUFF_PLD_FULL = 0x20000

	// SDF_3D_ACT: NA
	// Position of MODE_3D_ACT field.
	DSI_HOST_SDF_3D_ACT_MODE_3D_ACT_Pos = 0x0
	// Bit mask of MODE_3D_ACT field.
	DSI_HOST_SDF_3D_ACT_MODE_3D_ACT_Msk = 0x3
	// Position of FORMAT_3D_ACT field.
	DSI_HOST_SDF_3D_ACT_FORMAT_3D_ACT_Pos = 0x2
	// Bit mask of FORMAT_3D_ACT field.
	DSI_HOST_SDF_3D_ACT_FORMAT_3D_ACT_Msk = 0xc
	// Position of SECOND_VSYNC_ACT field.
	DSI_HOST_SDF_3D_ACT_SECOND_VSYNC_ACT_Pos = 0x4
	// Bit mask of SECOND_VSYNC_ACT field.
	DSI_HOST_SDF_3D_ACT_SECOND_VSYNC_ACT_Msk = 0x10
	// Bit SECOND_VSYNC_ACT.
	DSI_HOST_SDF_3D_ACT_SECOND_VSYNC_ACT = 0x10
	// Position of RIGHT_FIRST_ACT field.
	DSI_HOST_SDF_3D_ACT_RIGHT_FIRST_ACT_Pos = 0x5
	// Bit mask of RIGHT_FIRST_ACT field.
	DSI_HOST_SDF_3D_ACT_RIGHT_FIRST_ACT_Msk = 0x20
	// Bit RIGHT_FIRST_ACT.
	DSI_HOST_SDF_3D_ACT_RIGHT_FIRST_ACT = 0x20
	// Position of SEND_3D_CFG_ACT field.
	DSI_HOST_SDF_3D_ACT_SEND_3D_CFG_ACT_Pos = 0x10
	// Bit mask of SEND_3D_CFG_ACT field.
	DSI_HOST_SDF_3D_ACT_SEND_3D_CFG_ACT_Msk = 0x10000
	// Bit SEND_3D_CFG_ACT.
	DSI_HOST_SDF_3D_ACT_SEND_3D_CFG_ACT = 0x10000
)

// Constants for ECC: ECC (ECC Hardware Accelerator)
const (
	// MULT_INT_RAW: ECC interrupt raw register, valid in level.
	// Position of CALC_DONE_INT_RAW field.
	ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Pos = 0x0
	// Bit mask of CALC_DONE_INT_RAW field.
	ECC_MULT_INT_RAW_CALC_DONE_INT_RAW_Msk = 0x1
	// Bit CALC_DONE_INT_RAW.
	ECC_MULT_INT_RAW_CALC_DONE_INT_RAW = 0x1

	// MULT_INT_ST: ECC interrupt status register.
	// Position of CALC_DONE_INT_ST field.
	ECC_MULT_INT_ST_CALC_DONE_INT_ST_Pos = 0x0
	// Bit mask of CALC_DONE_INT_ST field.
	ECC_MULT_INT_ST_CALC_DONE_INT_ST_Msk = 0x1
	// Bit CALC_DONE_INT_ST.
	ECC_MULT_INT_ST_CALC_DONE_INT_ST = 0x1

	// MULT_INT_ENA: ECC interrupt enable register.
	// Position of CALC_DONE_INT_ENA field.
	ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Pos = 0x0
	// Bit mask of CALC_DONE_INT_ENA field.
	ECC_MULT_INT_ENA_CALC_DONE_INT_ENA_Msk = 0x1
	// Bit CALC_DONE_INT_ENA.
	ECC_MULT_INT_ENA_CALC_DONE_INT_ENA = 0x1

	// MULT_INT_CLR: ECC interrupt clear register.
	// Position of CALC_DONE_INT_CLR field.
	ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Pos = 0x0
	// Bit mask of CALC_DONE_INT_CLR field.
	ECC_MULT_INT_CLR_CALC_DONE_INT_CLR_Msk = 0x1
	// Bit CALC_DONE_INT_CLR.
	ECC_MULT_INT_CLR_CALC_DONE_INT_CLR = 0x1

	// MULT_CONF: ECC configure register
	// Position of START field.
	ECC_MULT_CONF_START_Pos = 0x0
	// Bit mask of START field.
	ECC_MULT_CONF_START_Msk = 0x1
	// Bit START.
	ECC_MULT_CONF_START = 0x1
	// Position of RESET field.
	ECC_MULT_CONF_RESET_Pos = 0x1
	// Bit mask of RESET field.
	ECC_MULT_CONF_RESET_Msk = 0x2
	// Bit RESET.
	ECC_MULT_CONF_RESET = 0x2
	// Position of KEY_LENGTH field.
	ECC_MULT_CONF_KEY_LENGTH_Pos = 0x2
	// Bit mask of KEY_LENGTH field.
	ECC_MULT_CONF_KEY_LENGTH_Msk = 0x4
	// Bit KEY_LENGTH.
	ECC_MULT_CONF_KEY_LENGTH = 0x4
	// Position of MOD_BASE field.
	ECC_MULT_CONF_MOD_BASE_Pos = 0x3
	// Bit mask of MOD_BASE field.
	ECC_MULT_CONF_MOD_BASE_Msk = 0x8
	// Bit MOD_BASE.
	ECC_MULT_CONF_MOD_BASE = 0x8
	// Position of WORK_MODE field.
	ECC_MULT_CONF_WORK_MODE_Pos = 0x4
	// Bit mask of WORK_MODE field.
	ECC_MULT_CONF_WORK_MODE_Msk = 0xf0
	// Position of SECURITY_MODE field.
	ECC_MULT_CONF_SECURITY_MODE_Pos = 0x8
	// Bit mask of SECURITY_MODE field.
	ECC_MULT_CONF_SECURITY_MODE_Msk = 0x100
	// Bit SECURITY_MODE.
	ECC_MULT_CONF_SECURITY_MODE = 0x100
	// Position of VERIFICATION_RESULT field.
	ECC_MULT_CONF_VERIFICATION_RESULT_Pos = 0x1d
	// Bit mask of VERIFICATION_RESULT field.
	ECC_MULT_CONF_VERIFICATION_RESULT_Msk = 0x20000000
	// Bit VERIFICATION_RESULT.
	ECC_MULT_CONF_VERIFICATION_RESULT = 0x20000000
	// Position of CLK_EN field.
	ECC_MULT_CONF_CLK_EN_Pos = 0x1e
	// Bit mask of CLK_EN field.
	ECC_MULT_CONF_CLK_EN_Msk = 0x40000000
	// Bit CLK_EN.
	ECC_MULT_CONF_CLK_EN = 0x40000000
	// Position of MEM_CLOCK_GATE_FORCE_ON field.
	ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON_Pos = 0x1f
	// Bit mask of MEM_CLOCK_GATE_FORCE_ON field.
	ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON_Msk = 0x80000000
	// Bit MEM_CLOCK_GATE_FORCE_ON.
	ECC_MULT_CONF_MEM_CLOCK_GATE_FORCE_ON = 0x80000000

	// MULT_DATE: Version control register
	// Position of DATE field.
	ECC_MULT_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	ECC_MULT_DATE_DATE_Msk = 0xfffffff
)

// Constants for ECDSA: ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator
const (
	// CONF: ECDSA configure register
	// Position of WORK_MODE field.
	ECDSA_CONF_WORK_MODE_Pos = 0x0
	// Bit mask of WORK_MODE field.
	ECDSA_CONF_WORK_MODE_Msk = 0x3
	// Position of ECC_CURVE field.
	ECDSA_CONF_ECC_CURVE_Pos = 0x2
	// Bit mask of ECC_CURVE field.
	ECDSA_CONF_ECC_CURVE_Msk = 0x4
	// Bit ECC_CURVE.
	ECDSA_CONF_ECC_CURVE = 0x4
	// Position of SOFTWARE_SET_K field.
	ECDSA_CONF_SOFTWARE_SET_K_Pos = 0x3
	// Bit mask of SOFTWARE_SET_K field.
	ECDSA_CONF_SOFTWARE_SET_K_Msk = 0x8
	// Bit SOFTWARE_SET_K.
	ECDSA_CONF_SOFTWARE_SET_K = 0x8
	// Position of SOFTWARE_SET_Z field.
	ECDSA_CONF_SOFTWARE_SET_Z_Pos = 0x4
	// Bit mask of SOFTWARE_SET_Z field.
	ECDSA_CONF_SOFTWARE_SET_Z_Msk = 0x10
	// Bit SOFTWARE_SET_Z.
	ECDSA_CONF_SOFTWARE_SET_Z = 0x10
	// Position of DETERMINISTIC_K field.
	ECDSA_CONF_DETERMINISTIC_K_Pos = 0x5
	// Bit mask of DETERMINISTIC_K field.
	ECDSA_CONF_DETERMINISTIC_K_Msk = 0x20
	// Bit DETERMINISTIC_K.
	ECDSA_CONF_DETERMINISTIC_K = 0x20
	// Position of DETERMINISTIC_LOOP field.
	ECDSA_CONF_DETERMINISTIC_LOOP_Pos = 0x6
	// Bit mask of DETERMINISTIC_LOOP field.
	ECDSA_CONF_DETERMINISTIC_LOOP_Msk = 0x3fffc0

	// CLK: ECDSA clock gate register
	// Position of GATE_FORCE_ON field.
	ECDSA_CLK_GATE_FORCE_ON_Pos = 0x0
	// Bit mask of GATE_FORCE_ON field.
	ECDSA_CLK_GATE_FORCE_ON_Msk = 0x1
	// Bit GATE_FORCE_ON.
	ECDSA_CLK_GATE_FORCE_ON = 0x1

	// INT_RAW: ECDSA interrupt raw register, valid in level.
	// Position of CALC_DONE_INT_RAW field.
	ECDSA_INT_RAW_CALC_DONE_INT_RAW_Pos = 0x0
	// Bit mask of CALC_DONE_INT_RAW field.
	ECDSA_INT_RAW_CALC_DONE_INT_RAW_Msk = 0x1
	// Bit CALC_DONE_INT_RAW.
	ECDSA_INT_RAW_CALC_DONE_INT_RAW = 0x1
	// Position of SHA_RELEASE_INT_RAW field.
	ECDSA_INT_RAW_SHA_RELEASE_INT_RAW_Pos = 0x1
	// Bit mask of SHA_RELEASE_INT_RAW field.
	ECDSA_INT_RAW_SHA_RELEASE_INT_RAW_Msk = 0x2
	// Bit SHA_RELEASE_INT_RAW.
	ECDSA_INT_RAW_SHA_RELEASE_INT_RAW = 0x2

	// INT_ST: ECDSA interrupt status register.
	// Position of CALC_DONE_INT_ST field.
	ECDSA_INT_ST_CALC_DONE_INT_ST_Pos = 0x0
	// Bit mask of CALC_DONE_INT_ST field.
	ECDSA_INT_ST_CALC_DONE_INT_ST_Msk = 0x1
	// Bit CALC_DONE_INT_ST.
	ECDSA_INT_ST_CALC_DONE_INT_ST = 0x1
	// Position of SHA_RELEASE_INT_ST field.
	ECDSA_INT_ST_SHA_RELEASE_INT_ST_Pos = 0x1
	// Bit mask of SHA_RELEASE_INT_ST field.
	ECDSA_INT_ST_SHA_RELEASE_INT_ST_Msk = 0x2
	// Bit SHA_RELEASE_INT_ST.
	ECDSA_INT_ST_SHA_RELEASE_INT_ST = 0x2

	// INT_ENA: ECDSA interrupt enable register.
	// Position of CALC_DONE_INT_ENA field.
	ECDSA_INT_ENA_CALC_DONE_INT_ENA_Pos = 0x0
	// Bit mask of CALC_DONE_INT_ENA field.
	ECDSA_INT_ENA_CALC_DONE_INT_ENA_Msk = 0x1
	// Bit CALC_DONE_INT_ENA.
	ECDSA_INT_ENA_CALC_DONE_INT_ENA = 0x1
	// Position of SHA_RELEASE_INT_ENA field.
	ECDSA_INT_ENA_SHA_RELEASE_INT_ENA_Pos = 0x1
	// Bit mask of SHA_RELEASE_INT_ENA field.
	ECDSA_INT_ENA_SHA_RELEASE_INT_ENA_Msk = 0x2
	// Bit SHA_RELEASE_INT_ENA.
	ECDSA_INT_ENA_SHA_RELEASE_INT_ENA = 0x2

	// INT_CLR: ECDSA interrupt clear register.
	// Position of CALC_DONE_INT_CLR field.
	ECDSA_INT_CLR_CALC_DONE_INT_CLR_Pos = 0x0
	// Bit mask of CALC_DONE_INT_CLR field.
	ECDSA_INT_CLR_CALC_DONE_INT_CLR_Msk = 0x1
	// Bit CALC_DONE_INT_CLR.
	ECDSA_INT_CLR_CALC_DONE_INT_CLR = 0x1
	// Position of SHA_RELEASE_INT_CLR field.
	ECDSA_INT_CLR_SHA_RELEASE_INT_CLR_Pos = 0x1
	// Bit mask of SHA_RELEASE_INT_CLR field.
	ECDSA_INT_CLR_SHA_RELEASE_INT_CLR_Msk = 0x2
	// Bit SHA_RELEASE_INT_CLR.
	ECDSA_INT_CLR_SHA_RELEASE_INT_CLR = 0x2

	// START: ECDSA start register
	// Position of START field.
	ECDSA_START_START_Pos = 0x0
	// Bit mask of START field.
	ECDSA_START_START_Msk = 0x1
	// Bit START.
	ECDSA_START_START = 0x1
	// Position of LOAD_DONE field.
	ECDSA_START_LOAD_DONE_Pos = 0x1
	// Bit mask of LOAD_DONE field.
	ECDSA_START_LOAD_DONE_Msk = 0x2
	// Bit LOAD_DONE.
	ECDSA_START_LOAD_DONE = 0x2
	// Position of GET_DONE field.
	ECDSA_START_GET_DONE_Pos = 0x2
	// Bit mask of GET_DONE field.
	ECDSA_START_GET_DONE_Msk = 0x4
	// Bit GET_DONE.
	ECDSA_START_GET_DONE = 0x4

	// STATE: ECDSA status register
	// Position of BUSY field.
	ECDSA_STATE_BUSY_Pos = 0x0
	// Bit mask of BUSY field.
	ECDSA_STATE_BUSY_Msk = 0x3

	// RESULT: ECDSA result register
	// Position of OPERATION_RESULT field.
	ECDSA_RESULT_OPERATION_RESULT_Pos = 0x0
	// Bit mask of OPERATION_RESULT field.
	ECDSA_RESULT_OPERATION_RESULT_Msk = 0x1
	// Bit OPERATION_RESULT.
	ECDSA_RESULT_OPERATION_RESULT = 0x1
	// Position of K_VALUE_WARNING field.
	ECDSA_RESULT_K_VALUE_WARNING_Pos = 0x1
	// Bit mask of K_VALUE_WARNING field.
	ECDSA_RESULT_K_VALUE_WARNING_Msk = 0x2
	// Bit K_VALUE_WARNING.
	ECDSA_RESULT_K_VALUE_WARNING = 0x2

	// DATE: Version control register
	// Position of DATE field.
	ECDSA_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	ECDSA_DATE_DATE_Msk = 0xfffffff

	// SHA_MODE: ECDSA control SHA register
	// Position of SHA_MODE field.
	ECDSA_SHA_MODE_SHA_MODE_Pos = 0x0
	// Bit mask of SHA_MODE field.
	ECDSA_SHA_MODE_SHA_MODE_Msk = 0x7

	// SHA_START: ECDSA control SHA register
	// Position of SHA_START field.
	ECDSA_SHA_START_SHA_START_Pos = 0x0
	// Bit mask of SHA_START field.
	ECDSA_SHA_START_SHA_START_Msk = 0x1
	// Bit SHA_START.
	ECDSA_SHA_START_SHA_START = 0x1

	// SHA_CONTINUE: ECDSA control SHA register
	// Position of SHA_CONTINUE field.
	ECDSA_SHA_CONTINUE_SHA_CONTINUE_Pos = 0x0
	// Bit mask of SHA_CONTINUE field.
	ECDSA_SHA_CONTINUE_SHA_CONTINUE_Msk = 0x1
	// Bit SHA_CONTINUE.
	ECDSA_SHA_CONTINUE_SHA_CONTINUE = 0x1

	// SHA_BUSY: ECDSA status register
	// Position of SHA_BUSY field.
	ECDSA_SHA_BUSY_SHA_BUSY_Pos = 0x0
	// Bit mask of SHA_BUSY field.
	ECDSA_SHA_BUSY_SHA_BUSY_Msk = 0x1
	// Bit SHA_BUSY.
	ECDSA_SHA_BUSY_SHA_BUSY = 0x1
)

// Constants for EFUSE: eFuse Controller
const (
	// PGM_DATA0: Register 0 that stores data to be programmed.
	// Position of PGM_DATA_0 field.
	EFUSE_PGM_DATA0_PGM_DATA_0_Pos = 0x0
	// Bit mask of PGM_DATA_0 field.
	EFUSE_PGM_DATA0_PGM_DATA_0_Msk = 0xffffffff

	// PGM_DATA1: Register 1 that stores data to be programmed.
	// Position of PGM_DATA_1 field.
	EFUSE_PGM_DATA1_PGM_DATA_1_Pos = 0x0
	// Bit mask of PGM_DATA_1 field.
	EFUSE_PGM_DATA1_PGM_DATA_1_Msk = 0xffffffff

	// PGM_DATA2: Register 2 that stores data to be programmed.
	// Position of PGM_DATA_2 field.
	EFUSE_PGM_DATA2_PGM_DATA_2_Pos = 0x0
	// Bit mask of PGM_DATA_2 field.
	EFUSE_PGM_DATA2_PGM_DATA_2_Msk = 0xffffffff

	// PGM_DATA3: Register 3 that stores data to be programmed.
	// Position of PGM_DATA_3 field.
	EFUSE_PGM_DATA3_PGM_DATA_3_Pos = 0x0
	// Bit mask of PGM_DATA_3 field.
	EFUSE_PGM_DATA3_PGM_DATA_3_Msk = 0xffffffff

	// PGM_DATA4: Register 4 that stores data to be programmed.
	// Position of PGM_DATA_4 field.
	EFUSE_PGM_DATA4_PGM_DATA_4_Pos = 0x0
	// Bit mask of PGM_DATA_4 field.
	EFUSE_PGM_DATA4_PGM_DATA_4_Msk = 0xffffffff

	// PGM_DATA5: Register 5 that stores data to be programmed.
	// Position of PGM_DATA_5 field.
	EFUSE_PGM_DATA5_PGM_DATA_5_Pos = 0x0
	// Bit mask of PGM_DATA_5 field.
	EFUSE_PGM_DATA5_PGM_DATA_5_Msk = 0xffffffff

	// PGM_DATA6: Register 6 that stores data to be programmed.
	// Position of PGM_DATA_6 field.
	EFUSE_PGM_DATA6_PGM_DATA_6_Pos = 0x0
	// Bit mask of PGM_DATA_6 field.
	EFUSE_PGM_DATA6_PGM_DATA_6_Msk = 0xffffffff

	// PGM_DATA7: Register 7 that stores data to be programmed.
	// Position of PGM_DATA_7 field.
	EFUSE_PGM_DATA7_PGM_DATA_7_Pos = 0x0
	// Bit mask of PGM_DATA_7 field.
	EFUSE_PGM_DATA7_PGM_DATA_7_Msk = 0xffffffff

	// PGM_CHECK_VALUE0: Register 0 that stores the RS code to be programmed.
	// Position of PGM_RS_DATA_0 field.
	EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Pos = 0x0
	// Bit mask of PGM_RS_DATA_0 field.
	EFUSE_PGM_CHECK_VALUE0_PGM_RS_DATA_0_Msk = 0xffffffff

	// PGM_CHECK_VALUE1: Register 1 that stores the RS code to be programmed.
	// Position of PGM_RS_DATA_1 field.
	EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Pos = 0x0
	// Bit mask of PGM_RS_DATA_1 field.
	EFUSE_PGM_CHECK_VALUE1_PGM_RS_DATA_1_Msk = 0xffffffff

	// PGM_CHECK_VALUE2: Register 2 that stores the RS code to be programmed.
	// Position of PGM_RS_DATA_2 field.
	EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Pos = 0x0
	// Bit mask of PGM_RS_DATA_2 field.
	EFUSE_PGM_CHECK_VALUE2_PGM_RS_DATA_2_Msk = 0xffffffff

	// RD_WR_DIS: BLOCK0 data register 0.
	// Position of WR_DIS field.
	EFUSE_RD_WR_DIS_WR_DIS_Pos = 0x0
	// Bit mask of WR_DIS field.
	EFUSE_RD_WR_DIS_WR_DIS_Msk = 0xffffffff

	// RD_REPEAT_DATA0: BLOCK0 data register 1.
	// Position of RD_DIS field.
	EFUSE_RD_REPEAT_DATA0_RD_DIS_Pos = 0x0
	// Bit mask of RD_DIS field.
	EFUSE_RD_REPEAT_DATA0_RD_DIS_Msk = 0x7f
	// Position of USB_DEVICE_EXCHG_PINS field.
	EFUSE_RD_REPEAT_DATA0_USB_DEVICE_EXCHG_PINS_Pos = 0x7
	// Bit mask of USB_DEVICE_EXCHG_PINS field.
	EFUSE_RD_REPEAT_DATA0_USB_DEVICE_EXCHG_PINS_Msk = 0x80
	// Bit USB_DEVICE_EXCHG_PINS.
	EFUSE_RD_REPEAT_DATA0_USB_DEVICE_EXCHG_PINS = 0x80
	// Position of USB_OTG11_EXCHG_PINS field.
	EFUSE_RD_REPEAT_DATA0_USB_OTG11_EXCHG_PINS_Pos = 0x8
	// Bit mask of USB_OTG11_EXCHG_PINS field.
	EFUSE_RD_REPEAT_DATA0_USB_OTG11_EXCHG_PINS_Msk = 0x100
	// Bit USB_OTG11_EXCHG_PINS.
	EFUSE_RD_REPEAT_DATA0_USB_OTG11_EXCHG_PINS = 0x100
	// Position of DIS_USB_JTAG field.
	EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Pos = 0x9
	// Bit mask of DIS_USB_JTAG field.
	EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG_Msk = 0x200
	// Bit DIS_USB_JTAG.
	EFUSE_RD_REPEAT_DATA0_DIS_USB_JTAG = 0x200
	// Position of POWERGLITCH_EN field.
	EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN_Pos = 0xa
	// Bit mask of POWERGLITCH_EN field.
	EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN_Msk = 0x400
	// Bit POWERGLITCH_EN.
	EFUSE_RD_REPEAT_DATA0_POWERGLITCH_EN = 0x400
	// Position of DIS_USB_SERIAL_JTAG field.
	EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG_Pos = 0xb
	// Bit mask of DIS_USB_SERIAL_JTAG field.
	EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG_Msk = 0x800
	// Bit DIS_USB_SERIAL_JTAG.
	EFUSE_RD_REPEAT_DATA0_DIS_USB_SERIAL_JTAG = 0x800
	// Position of DIS_FORCE_DOWNLOAD field.
	EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Pos = 0xc
	// Bit mask of DIS_FORCE_DOWNLOAD field.
	EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD_Msk = 0x1000
	// Bit DIS_FORCE_DOWNLOAD.
	EFUSE_RD_REPEAT_DATA0_DIS_FORCE_DOWNLOAD = 0x1000
	// Position of SPI_DOWNLOAD_MSPI_DIS field.
	EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS_Pos = 0xd
	// Bit mask of SPI_DOWNLOAD_MSPI_DIS field.
	EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS_Msk = 0x2000
	// Bit SPI_DOWNLOAD_MSPI_DIS.
	EFUSE_RD_REPEAT_DATA0_SPI_DOWNLOAD_MSPI_DIS = 0x2000
	// Position of DIS_TWAI field.
	EFUSE_RD_REPEAT_DATA0_DIS_TWAI_Pos = 0xe
	// Bit mask of DIS_TWAI field.
	EFUSE_RD_REPEAT_DATA0_DIS_TWAI_Msk = 0x4000
	// Bit DIS_TWAI.
	EFUSE_RD_REPEAT_DATA0_DIS_TWAI = 0x4000
	// Position of JTAG_SEL_ENABLE field.
	EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Pos = 0xf
	// Bit mask of JTAG_SEL_ENABLE field.
	EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE_Msk = 0x8000
	// Bit JTAG_SEL_ENABLE.
	EFUSE_RD_REPEAT_DATA0_JTAG_SEL_ENABLE = 0x8000
	// Position of SOFT_DIS_JTAG field.
	EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Pos = 0x10
	// Bit mask of SOFT_DIS_JTAG field.
	EFUSE_RD_REPEAT_DATA0_SOFT_DIS_JTAG_Msk = 0x70000
	// Position of DIS_PAD_JTAG field.
	EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Pos = 0x13
	// Bit mask of DIS_PAD_JTAG field.
	EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG_Msk = 0x80000
	// Bit DIS_PAD_JTAG.
	EFUSE_RD_REPEAT_DATA0_DIS_PAD_JTAG = 0x80000
	// Position of DIS_DOWNLOAD_MANUAL_ENCRYPT field.
	EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x14
	// Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT field.
	EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x100000
	// Bit DIS_DOWNLOAD_MANUAL_ENCRYPT.
	EFUSE_RD_REPEAT_DATA0_DIS_DOWNLOAD_MANUAL_ENCRYPT = 0x100000
	// Position of USB_DEVICE_DREFH field.
	EFUSE_RD_REPEAT_DATA0_USB_DEVICE_DREFH_Pos = 0x15
	// Bit mask of USB_DEVICE_DREFH field.
	EFUSE_RD_REPEAT_DATA0_USB_DEVICE_DREFH_Msk = 0x600000
	// Position of USB_OTG11_DREFH field.
	EFUSE_RD_REPEAT_DATA0_USB_OTG11_DREFH_Pos = 0x17
	// Bit mask of USB_OTG11_DREFH field.
	EFUSE_RD_REPEAT_DATA0_USB_OTG11_DREFH_Msk = 0x1800000
	// Position of USB_PHY_SEL field.
	EFUSE_RD_REPEAT_DATA0_USB_PHY_SEL_Pos = 0x19
	// Bit mask of USB_PHY_SEL field.
	EFUSE_RD_REPEAT_DATA0_USB_PHY_SEL_Msk = 0x2000000
	// Bit USB_PHY_SEL.
	EFUSE_RD_REPEAT_DATA0_USB_PHY_SEL = 0x2000000
	// Position of KM_HUK_GEN_STATE_LOW field.
	EFUSE_RD_REPEAT_DATA0_KM_HUK_GEN_STATE_LOW_Pos = 0x1a
	// Bit mask of KM_HUK_GEN_STATE_LOW field.
	EFUSE_RD_REPEAT_DATA0_KM_HUK_GEN_STATE_LOW_Msk = 0xfc000000

	// RD_REPEAT_DATA1: BLOCK0 data register 2.
	// Position of KM_HUK_GEN_STATE_HIGH field.
	EFUSE_RD_REPEAT_DATA1_KM_HUK_GEN_STATE_HIGH_Pos = 0x0
	// Bit mask of KM_HUK_GEN_STATE_HIGH field.
	EFUSE_RD_REPEAT_DATA1_KM_HUK_GEN_STATE_HIGH_Msk = 0x7
	// Position of KM_RND_SWITCH_CYCLE field.
	EFUSE_RD_REPEAT_DATA1_KM_RND_SWITCH_CYCLE_Pos = 0x3
	// Bit mask of KM_RND_SWITCH_CYCLE field.
	EFUSE_RD_REPEAT_DATA1_KM_RND_SWITCH_CYCLE_Msk = 0x18
	// Position of KM_DEPLOY_ONLY_ONCE field.
	EFUSE_RD_REPEAT_DATA1_KM_DEPLOY_ONLY_ONCE_Pos = 0x5
	// Bit mask of KM_DEPLOY_ONLY_ONCE field.
	EFUSE_RD_REPEAT_DATA1_KM_DEPLOY_ONLY_ONCE_Msk = 0x1e0
	// Position of FORCE_USE_KEY_MANAGER_KEY field.
	EFUSE_RD_REPEAT_DATA1_FORCE_USE_KEY_MANAGER_KEY_Pos = 0x9
	// Bit mask of FORCE_USE_KEY_MANAGER_KEY field.
	EFUSE_RD_REPEAT_DATA1_FORCE_USE_KEY_MANAGER_KEY_Msk = 0x1e00
	// Position of FORCE_DISABLE_SW_INIT_KEY field.
	EFUSE_RD_REPEAT_DATA1_FORCE_DISABLE_SW_INIT_KEY_Pos = 0xd
	// Bit mask of FORCE_DISABLE_SW_INIT_KEY field.
	EFUSE_RD_REPEAT_DATA1_FORCE_DISABLE_SW_INIT_KEY_Msk = 0x2000
	// Bit FORCE_DISABLE_SW_INIT_KEY.
	EFUSE_RD_REPEAT_DATA1_FORCE_DISABLE_SW_INIT_KEY = 0x2000
	// Position of XTS_KEY_LENGTH_256 field.
	EFUSE_RD_REPEAT_DATA1_XTS_KEY_LENGTH_256_Pos = 0xe
	// Bit mask of XTS_KEY_LENGTH_256 field.
	EFUSE_RD_REPEAT_DATA1_XTS_KEY_LENGTH_256_Msk = 0x4000
	// Bit XTS_KEY_LENGTH_256.
	EFUSE_RD_REPEAT_DATA1_XTS_KEY_LENGTH_256 = 0x4000
	// Position of WDT_DELAY_SEL field.
	EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Pos = 0x10
	// Bit mask of WDT_DELAY_SEL field.
	EFUSE_RD_REPEAT_DATA1_WDT_DELAY_SEL_Msk = 0x30000
	// Position of SPI_BOOT_CRYPT_CNT field.
	EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Pos = 0x12
	// Bit mask of SPI_BOOT_CRYPT_CNT field.
	EFUSE_RD_REPEAT_DATA1_SPI_BOOT_CRYPT_CNT_Msk = 0x1c0000
	// Position of SECURE_BOOT_KEY_REVOKE0 field.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Pos = 0x15
	// Bit mask of SECURE_BOOT_KEY_REVOKE0 field.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0_Msk = 0x200000
	// Bit SECURE_BOOT_KEY_REVOKE0.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE0 = 0x200000
	// Position of SECURE_BOOT_KEY_REVOKE1 field.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Pos = 0x16
	// Bit mask of SECURE_BOOT_KEY_REVOKE1 field.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1_Msk = 0x400000
	// Bit SECURE_BOOT_KEY_REVOKE1.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE1 = 0x400000
	// Position of SECURE_BOOT_KEY_REVOKE2 field.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Pos = 0x17
	// Bit mask of SECURE_BOOT_KEY_REVOKE2 field.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2_Msk = 0x800000
	// Bit SECURE_BOOT_KEY_REVOKE2.
	EFUSE_RD_REPEAT_DATA1_SECURE_BOOT_KEY_REVOKE2 = 0x800000
	// Position of KEY_PURPOSE_0 field.
	EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Pos = 0x18
	// Bit mask of KEY_PURPOSE_0 field.
	EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_0_Msk = 0xf000000
	// Position of KEY_PURPOSE_1 field.
	EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Pos = 0x1c
	// Bit mask of KEY_PURPOSE_1 field.
	EFUSE_RD_REPEAT_DATA1_KEY_PURPOSE_1_Msk = 0xf0000000

	// RD_REPEAT_DATA2: BLOCK0 data register 3.
	// Position of KEY_PURPOSE_2 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Pos = 0x0
	// Bit mask of KEY_PURPOSE_2 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_2_Msk = 0xf
	// Position of KEY_PURPOSE_3 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Pos = 0x4
	// Bit mask of KEY_PURPOSE_3 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_3_Msk = 0xf0
	// Position of KEY_PURPOSE_4 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Pos = 0x8
	// Bit mask of KEY_PURPOSE_4 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_4_Msk = 0xf00
	// Position of KEY_PURPOSE_5 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Pos = 0xc
	// Bit mask of KEY_PURPOSE_5 field.
	EFUSE_RD_REPEAT_DATA2_KEY_PURPOSE_5_Msk = 0xf000
	// Position of SEC_DPA_LEVEL field.
	EFUSE_RD_REPEAT_DATA2_SEC_DPA_LEVEL_Pos = 0x10
	// Bit mask of SEC_DPA_LEVEL field.
	EFUSE_RD_REPEAT_DATA2_SEC_DPA_LEVEL_Msk = 0x30000
	// Position of ECDSA_ENABLE_SOFT_K field.
	EFUSE_RD_REPEAT_DATA2_ECDSA_ENABLE_SOFT_K_Pos = 0x12
	// Bit mask of ECDSA_ENABLE_SOFT_K field.
	EFUSE_RD_REPEAT_DATA2_ECDSA_ENABLE_SOFT_K_Msk = 0x40000
	// Bit ECDSA_ENABLE_SOFT_K.
	EFUSE_RD_REPEAT_DATA2_ECDSA_ENABLE_SOFT_K = 0x40000
	// Position of CRYPT_DPA_ENABLE field.
	EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE_Pos = 0x13
	// Bit mask of CRYPT_DPA_ENABLE field.
	EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE_Msk = 0x80000
	// Bit CRYPT_DPA_ENABLE.
	EFUSE_RD_REPEAT_DATA2_CRYPT_DPA_ENABLE = 0x80000
	// Position of SECURE_BOOT_EN field.
	EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Pos = 0x14
	// Bit mask of SECURE_BOOT_EN field.
	EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN_Msk = 0x100000
	// Bit SECURE_BOOT_EN.
	EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_EN = 0x100000
	// Position of SECURE_BOOT_AGGRESSIVE_REVOKE field.
	EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Pos = 0x15
	// Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE field.
	EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE_Msk = 0x200000
	// Bit SECURE_BOOT_AGGRESSIVE_REVOKE.
	EFUSE_RD_REPEAT_DATA2_SECURE_BOOT_AGGRESSIVE_REVOKE = 0x200000
	// Position of FLASH_TYPE field.
	EFUSE_RD_REPEAT_DATA2_FLASH_TYPE_Pos = 0x17
	// Bit mask of FLASH_TYPE field.
	EFUSE_RD_REPEAT_DATA2_FLASH_TYPE_Msk = 0x800000
	// Bit FLASH_TYPE.
	EFUSE_RD_REPEAT_DATA2_FLASH_TYPE = 0x800000
	// Position of FLASH_PAGE_SIZE field.
	EFUSE_RD_REPEAT_DATA2_FLASH_PAGE_SIZE_Pos = 0x18
	// Bit mask of FLASH_PAGE_SIZE field.
	EFUSE_RD_REPEAT_DATA2_FLASH_PAGE_SIZE_Msk = 0x3000000
	// Position of FLASH_ECC_EN field.
	EFUSE_RD_REPEAT_DATA2_FLASH_ECC_EN_Pos = 0x1a
	// Bit mask of FLASH_ECC_EN field.
	EFUSE_RD_REPEAT_DATA2_FLASH_ECC_EN_Msk = 0x4000000
	// Bit FLASH_ECC_EN.
	EFUSE_RD_REPEAT_DATA2_FLASH_ECC_EN = 0x4000000
	// Position of DIS_USB_OTG_DOWNLOAD_MODE field.
	EFUSE_RD_REPEAT_DATA2_DIS_USB_OTG_DOWNLOAD_MODE_Pos = 0x1b
	// Bit mask of DIS_USB_OTG_DOWNLOAD_MODE field.
	EFUSE_RD_REPEAT_DATA2_DIS_USB_OTG_DOWNLOAD_MODE_Msk = 0x8000000
	// Bit DIS_USB_OTG_DOWNLOAD_MODE.
	EFUSE_RD_REPEAT_DATA2_DIS_USB_OTG_DOWNLOAD_MODE = 0x8000000
	// Position of FLASH_TPUW field.
	EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Pos = 0x1c
	// Bit mask of FLASH_TPUW field.
	EFUSE_RD_REPEAT_DATA2_FLASH_TPUW_Msk = 0xf0000000

	// RD_REPEAT_DATA3: BLOCK0 data register 4.
	// Position of DIS_DOWNLOAD_MODE field.
	EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Pos = 0x0
	// Bit mask of DIS_DOWNLOAD_MODE field.
	EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE_Msk = 0x1
	// Bit DIS_DOWNLOAD_MODE.
	EFUSE_RD_REPEAT_DATA3_DIS_DOWNLOAD_MODE = 0x1
	// Position of DIS_DIRECT_BOOT field.
	EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT_Pos = 0x1
	// Bit mask of DIS_DIRECT_BOOT field.
	EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT_Msk = 0x2
	// Bit DIS_DIRECT_BOOT.
	EFUSE_RD_REPEAT_DATA3_DIS_DIRECT_BOOT = 0x2
	// Position of DIS_USB_SERIAL_JTAG_ROM_PRINT field.
	EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_ROM_PRINT_Pos = 0x2
	// Bit mask of DIS_USB_SERIAL_JTAG_ROM_PRINT field.
	EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_ROM_PRINT_Msk = 0x4
	// Bit DIS_USB_SERIAL_JTAG_ROM_PRINT.
	EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_ROM_PRINT = 0x4
	// Position of LOCK_KM_KEY field.
	EFUSE_RD_REPEAT_DATA3_LOCK_KM_KEY_Pos = 0x3
	// Bit mask of LOCK_KM_KEY field.
	EFUSE_RD_REPEAT_DATA3_LOCK_KM_KEY_Msk = 0x8
	// Bit LOCK_KM_KEY.
	EFUSE_RD_REPEAT_DATA3_LOCK_KM_KEY = 0x8
	// Position of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE field.
	EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_Pos = 0x4
	// Bit mask of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE field.
	EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_Msk = 0x10
	// Bit DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
	EFUSE_RD_REPEAT_DATA3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE = 0x10
	// Position of ENABLE_SECURITY_DOWNLOAD field.
	EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Pos = 0x5
	// Bit mask of ENABLE_SECURITY_DOWNLOAD field.
	EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD_Msk = 0x20
	// Bit ENABLE_SECURITY_DOWNLOAD.
	EFUSE_RD_REPEAT_DATA3_ENABLE_SECURITY_DOWNLOAD = 0x20
	// Position of UART_PRINT_CONTROL field.
	EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Pos = 0x6
	// Bit mask of UART_PRINT_CONTROL field.
	EFUSE_RD_REPEAT_DATA3_UART_PRINT_CONTROL_Msk = 0xc0
	// Position of FORCE_SEND_RESUME field.
	EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Pos = 0x8
	// Bit mask of FORCE_SEND_RESUME field.
	EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME_Msk = 0x100
	// Bit FORCE_SEND_RESUME.
	EFUSE_RD_REPEAT_DATA3_FORCE_SEND_RESUME = 0x100
	// Position of SECURE_VERSION field.
	EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Pos = 0x9
	// Bit mask of SECURE_VERSION field.
	EFUSE_RD_REPEAT_DATA3_SECURE_VERSION_Msk = 0x1fffe00
	// Position of SECURE_BOOT_DISABLE_FAST_WAKE field.
	EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE_Pos = 0x19
	// Bit mask of SECURE_BOOT_DISABLE_FAST_WAKE field.
	EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE_Msk = 0x2000000
	// Bit SECURE_BOOT_DISABLE_FAST_WAKE.
	EFUSE_RD_REPEAT_DATA3_SECURE_BOOT_DISABLE_FAST_WAKE = 0x2000000
	// Position of HYS_EN_PAD field.
	EFUSE_RD_REPEAT_DATA3_HYS_EN_PAD_Pos = 0x1a
	// Bit mask of HYS_EN_PAD field.
	EFUSE_RD_REPEAT_DATA3_HYS_EN_PAD_Msk = 0x4000000
	// Bit HYS_EN_PAD.
	EFUSE_RD_REPEAT_DATA3_HYS_EN_PAD = 0x4000000
	// Position of DCDC_VSET field.
	EFUSE_RD_REPEAT_DATA3_DCDC_VSET_Pos = 0x1b
	// Bit mask of DCDC_VSET field.
	EFUSE_RD_REPEAT_DATA3_DCDC_VSET_Msk = 0xf8000000

	// RD_REPEAT_DATA4: BLOCK0 data register 5.
	// Position of _0PXA_TIEH_SEL_0 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_0_Pos = 0x0
	// Bit mask of _0PXA_TIEH_SEL_0 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_0_Msk = 0x3
	// Position of _0PXA_TIEH_SEL_1 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_1_Pos = 0x2
	// Bit mask of _0PXA_TIEH_SEL_1 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_1_Msk = 0xc
	// Position of _0PXA_TIEH_SEL_2 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_2_Pos = 0x4
	// Bit mask of _0PXA_TIEH_SEL_2 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_2_Msk = 0x30
	// Position of _0PXA_TIEH_SEL_3 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_3_Pos = 0x6
	// Bit mask of _0PXA_TIEH_SEL_3 field.
	EFUSE_RD_REPEAT_DATA4__0PXA_TIEH_SEL_3_Msk = 0xc0
	// Position of KM_DISABLE_DEPLOY_MODE field.
	EFUSE_RD_REPEAT_DATA4_KM_DISABLE_DEPLOY_MODE_Pos = 0x8
	// Bit mask of KM_DISABLE_DEPLOY_MODE field.
	EFUSE_RD_REPEAT_DATA4_KM_DISABLE_DEPLOY_MODE_Msk = 0xf00
	// Position of USB_DEVICE_DREFL field.
	EFUSE_RD_REPEAT_DATA4_USB_DEVICE_DREFL_Pos = 0xc
	// Bit mask of USB_DEVICE_DREFL field.
	EFUSE_RD_REPEAT_DATA4_USB_DEVICE_DREFL_Msk = 0x3000
	// Position of USB_OTG11_DREFL field.
	EFUSE_RD_REPEAT_DATA4_USB_OTG11_DREFL_Pos = 0xe
	// Bit mask of USB_OTG11_DREFL field.
	EFUSE_RD_REPEAT_DATA4_USB_OTG11_DREFL_Msk = 0xc000
	// Position of HP_PWR_SRC_SEL field.
	EFUSE_RD_REPEAT_DATA4_HP_PWR_SRC_SEL_Pos = 0x12
	// Bit mask of HP_PWR_SRC_SEL field.
	EFUSE_RD_REPEAT_DATA4_HP_PWR_SRC_SEL_Msk = 0x40000
	// Bit HP_PWR_SRC_SEL.
	EFUSE_RD_REPEAT_DATA4_HP_PWR_SRC_SEL = 0x40000
	// Position of DCDC_VSET_EN field.
	EFUSE_RD_REPEAT_DATA4_DCDC_VSET_EN_Pos = 0x13
	// Bit mask of DCDC_VSET_EN field.
	EFUSE_RD_REPEAT_DATA4_DCDC_VSET_EN_Msk = 0x80000
	// Bit DCDC_VSET_EN.
	EFUSE_RD_REPEAT_DATA4_DCDC_VSET_EN = 0x80000
	// Position of DIS_WDT field.
	EFUSE_RD_REPEAT_DATA4_DIS_WDT_Pos = 0x14
	// Bit mask of DIS_WDT field.
	EFUSE_RD_REPEAT_DATA4_DIS_WDT_Msk = 0x100000
	// Bit DIS_WDT.
	EFUSE_RD_REPEAT_DATA4_DIS_WDT = 0x100000
	// Position of DIS_SWD field.
	EFUSE_RD_REPEAT_DATA4_DIS_SWD_Pos = 0x15
	// Bit mask of DIS_SWD field.
	EFUSE_RD_REPEAT_DATA4_DIS_SWD_Msk = 0x200000
	// Bit DIS_SWD.
	EFUSE_RD_REPEAT_DATA4_DIS_SWD = 0x200000

	// RD_MAC_SYS_0: BLOCK1 data register $n.
	// Position of MAC_0 field.
	EFUSE_RD_MAC_SYS_0_MAC_0_Pos = 0x0
	// Bit mask of MAC_0 field.
	EFUSE_RD_MAC_SYS_0_MAC_0_Msk = 0xffffffff

	// RD_MAC_SYS_1: BLOCK1 data register $n.
	// Position of MAC_1 field.
	EFUSE_RD_MAC_SYS_1_MAC_1_Pos = 0x0
	// Bit mask of MAC_1 field.
	EFUSE_RD_MAC_SYS_1_MAC_1_Msk = 0xffff
	// Position of MAC_EXT field.
	EFUSE_RD_MAC_SYS_1_MAC_EXT_Pos = 0x10
	// Bit mask of MAC_EXT field.
	EFUSE_RD_MAC_SYS_1_MAC_EXT_Msk = 0xffff0000

	// RD_MAC_SYS_2: BLOCK1 data register $n.
	// Position of MAC_RESERVED_1 field.
	EFUSE_RD_MAC_SYS_2_MAC_RESERVED_1_Pos = 0x0
	// Bit mask of MAC_RESERVED_1 field.
	EFUSE_RD_MAC_SYS_2_MAC_RESERVED_1_Msk = 0x3fff
	// Position of MAC_RESERVED_0 field.
	EFUSE_RD_MAC_SYS_2_MAC_RESERVED_0_Pos = 0xe
	// Bit mask of MAC_RESERVED_0 field.
	EFUSE_RD_MAC_SYS_2_MAC_RESERVED_0_Msk = 0xffffc000

	// RD_MAC_SYS_3: BLOCK1 data register $n.
	// Position of MAC_RESERVED_2 field.
	EFUSE_RD_MAC_SYS_3_MAC_RESERVED_2_Pos = 0x0
	// Bit mask of MAC_RESERVED_2 field.
	EFUSE_RD_MAC_SYS_3_MAC_RESERVED_2_Msk = 0x3ffff
	// Position of SYS_DATA_PART0_0 field.
	EFUSE_RD_MAC_SYS_3_SYS_DATA_PART0_0_Pos = 0x12
	// Bit mask of SYS_DATA_PART0_0 field.
	EFUSE_RD_MAC_SYS_3_SYS_DATA_PART0_0_Msk = 0xfffc0000

	// RD_MAC_SYS_4: BLOCK1 data register $n.
	// Position of SYS_DATA_PART0_1 field.
	EFUSE_RD_MAC_SYS_4_SYS_DATA_PART0_1_Pos = 0x0
	// Bit mask of SYS_DATA_PART0_1 field.
	EFUSE_RD_MAC_SYS_4_SYS_DATA_PART0_1_Msk = 0xffffffff

	// RD_MAC_SYS_5: BLOCK1 data register $n.
	// Position of SYS_DATA_PART0_2 field.
	EFUSE_RD_MAC_SYS_5_SYS_DATA_PART0_2_Pos = 0x0
	// Bit mask of SYS_DATA_PART0_2 field.
	EFUSE_RD_MAC_SYS_5_SYS_DATA_PART0_2_Msk = 0xffffffff

	// RD_SYS_PART1_DATA0: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_0 field.
	EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_0 field.
	EFUSE_RD_SYS_PART1_DATA0_SYS_DATA_PART1_0_Msk = 0xffffffff

	// RD_SYS_PART1_DATA1: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_1 field.
	EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_1 field.
	EFUSE_RD_SYS_PART1_DATA1_SYS_DATA_PART1_1_Msk = 0xffffffff

	// RD_SYS_PART1_DATA2: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_2 field.
	EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_2 field.
	EFUSE_RD_SYS_PART1_DATA2_SYS_DATA_PART1_2_Msk = 0xffffffff

	// RD_SYS_PART1_DATA3: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_3 field.
	EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_3 field.
	EFUSE_RD_SYS_PART1_DATA3_SYS_DATA_PART1_3_Msk = 0xffffffff

	// RD_SYS_PART1_DATA4: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_4 field.
	EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_4 field.
	EFUSE_RD_SYS_PART1_DATA4_SYS_DATA_PART1_4_Msk = 0xffffffff

	// RD_SYS_PART1_DATA5: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_5 field.
	EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_5 field.
	EFUSE_RD_SYS_PART1_DATA5_SYS_DATA_PART1_5_Msk = 0xffffffff

	// RD_SYS_PART1_DATA6: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_6 field.
	EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_6 field.
	EFUSE_RD_SYS_PART1_DATA6_SYS_DATA_PART1_6_Msk = 0xffffffff

	// RD_SYS_PART1_DATA7: Register $n of BLOCK2 (system).
	// Position of SYS_DATA_PART1_7 field.
	EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Pos = 0x0
	// Bit mask of SYS_DATA_PART1_7 field.
	EFUSE_RD_SYS_PART1_DATA7_SYS_DATA_PART1_7_Msk = 0xffffffff

	// RD_USR_DATA0: Register $n of BLOCK3 (user).
	// Position of USR_DATA0 field.
	EFUSE_RD_USR_DATA0_USR_DATA0_Pos = 0x0
	// Bit mask of USR_DATA0 field.
	EFUSE_RD_USR_DATA0_USR_DATA0_Msk = 0xffffffff

	// RD_USR_DATA1: Register $n of BLOCK3 (user).
	// Position of USR_DATA1 field.
	EFUSE_RD_USR_DATA1_USR_DATA1_Pos = 0x0
	// Bit mask of USR_DATA1 field.
	EFUSE_RD_USR_DATA1_USR_DATA1_Msk = 0xffffffff

	// RD_USR_DATA2: Register $n of BLOCK3 (user).
	// Position of USR_DATA2 field.
	EFUSE_RD_USR_DATA2_USR_DATA2_Pos = 0x0
	// Bit mask of USR_DATA2 field.
	EFUSE_RD_USR_DATA2_USR_DATA2_Msk = 0xffffffff

	// RD_USR_DATA3: Register $n of BLOCK3 (user).
	// Position of USR_DATA3 field.
	EFUSE_RD_USR_DATA3_USR_DATA3_Pos = 0x0
	// Bit mask of USR_DATA3 field.
	EFUSE_RD_USR_DATA3_USR_DATA3_Msk = 0xffffffff

	// RD_USR_DATA4: Register $n of BLOCK3 (user).
	// Position of USR_DATA4 field.
	EFUSE_RD_USR_DATA4_USR_DATA4_Pos = 0x0
	// Bit mask of USR_DATA4 field.
	EFUSE_RD_USR_DATA4_USR_DATA4_Msk = 0xffffffff

	// RD_USR_DATA5: Register $n of BLOCK3 (user).
	// Position of USR_DATA5 field.
	EFUSE_RD_USR_DATA5_USR_DATA5_Pos = 0x0
	// Bit mask of USR_DATA5 field.
	EFUSE_RD_USR_DATA5_USR_DATA5_Msk = 0xffffffff

	// RD_USR_DATA6: Register $n of BLOCK3 (user).
	// Position of USR_DATA6 field.
	EFUSE_RD_USR_DATA6_USR_DATA6_Pos = 0x0
	// Bit mask of USR_DATA6 field.
	EFUSE_RD_USR_DATA6_USR_DATA6_Msk = 0xffffffff

	// RD_USR_DATA7: Register $n of BLOCK3 (user).
	// Position of USR_DATA7 field.
	EFUSE_RD_USR_DATA7_USR_DATA7_Pos = 0x0
	// Bit mask of USR_DATA7 field.
	EFUSE_RD_USR_DATA7_USR_DATA7_Msk = 0xffffffff

	// RD_KEY0_DATA0: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA0 field.
	EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Pos = 0x0
	// Bit mask of KEY0_DATA0 field.
	EFUSE_RD_KEY0_DATA0_KEY0_DATA0_Msk = 0xffffffff

	// RD_KEY0_DATA1: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA1 field.
	EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Pos = 0x0
	// Bit mask of KEY0_DATA1 field.
	EFUSE_RD_KEY0_DATA1_KEY0_DATA1_Msk = 0xffffffff

	// RD_KEY0_DATA2: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA2 field.
	EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Pos = 0x0
	// Bit mask of KEY0_DATA2 field.
	EFUSE_RD_KEY0_DATA2_KEY0_DATA2_Msk = 0xffffffff

	// RD_KEY0_DATA3: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA3 field.
	EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Pos = 0x0
	// Bit mask of KEY0_DATA3 field.
	EFUSE_RD_KEY0_DATA3_KEY0_DATA3_Msk = 0xffffffff

	// RD_KEY0_DATA4: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA4 field.
	EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Pos = 0x0
	// Bit mask of KEY0_DATA4 field.
	EFUSE_RD_KEY0_DATA4_KEY0_DATA4_Msk = 0xffffffff

	// RD_KEY0_DATA5: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA5 field.
	EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Pos = 0x0
	// Bit mask of KEY0_DATA5 field.
	EFUSE_RD_KEY0_DATA5_KEY0_DATA5_Msk = 0xffffffff

	// RD_KEY0_DATA6: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA6 field.
	EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Pos = 0x0
	// Bit mask of KEY0_DATA6 field.
	EFUSE_RD_KEY0_DATA6_KEY0_DATA6_Msk = 0xffffffff

	// RD_KEY0_DATA7: Register $n of BLOCK4 (KEY0).
	// Position of KEY0_DATA7 field.
	EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Pos = 0x0
	// Bit mask of KEY0_DATA7 field.
	EFUSE_RD_KEY0_DATA7_KEY0_DATA7_Msk = 0xffffffff

	// RD_KEY1_DATA0: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA0 field.
	EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Pos = 0x0
	// Bit mask of KEY1_DATA0 field.
	EFUSE_RD_KEY1_DATA0_KEY1_DATA0_Msk = 0xffffffff

	// RD_KEY1_DATA1: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA1 field.
	EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Pos = 0x0
	// Bit mask of KEY1_DATA1 field.
	EFUSE_RD_KEY1_DATA1_KEY1_DATA1_Msk = 0xffffffff

	// RD_KEY1_DATA2: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA2 field.
	EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Pos = 0x0
	// Bit mask of KEY1_DATA2 field.
	EFUSE_RD_KEY1_DATA2_KEY1_DATA2_Msk = 0xffffffff

	// RD_KEY1_DATA3: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA3 field.
	EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Pos = 0x0
	// Bit mask of KEY1_DATA3 field.
	EFUSE_RD_KEY1_DATA3_KEY1_DATA3_Msk = 0xffffffff

	// RD_KEY1_DATA4: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA4 field.
	EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Pos = 0x0
	// Bit mask of KEY1_DATA4 field.
	EFUSE_RD_KEY1_DATA4_KEY1_DATA4_Msk = 0xffffffff

	// RD_KEY1_DATA5: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA5 field.
	EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Pos = 0x0
	// Bit mask of KEY1_DATA5 field.
	EFUSE_RD_KEY1_DATA5_KEY1_DATA5_Msk = 0xffffffff

	// RD_KEY1_DATA6: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA6 field.
	EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Pos = 0x0
	// Bit mask of KEY1_DATA6 field.
	EFUSE_RD_KEY1_DATA6_KEY1_DATA6_Msk = 0xffffffff

	// RD_KEY1_DATA7: Register $n of BLOCK5 (KEY1).
	// Position of KEY1_DATA7 field.
	EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Pos = 0x0
	// Bit mask of KEY1_DATA7 field.
	EFUSE_RD_KEY1_DATA7_KEY1_DATA7_Msk = 0xffffffff

	// RD_KEY2_DATA0: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA0 field.
	EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Pos = 0x0
	// Bit mask of KEY2_DATA0 field.
	EFUSE_RD_KEY2_DATA0_KEY2_DATA0_Msk = 0xffffffff

	// RD_KEY2_DATA1: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA1 field.
	EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Pos = 0x0
	// Bit mask of KEY2_DATA1 field.
	EFUSE_RD_KEY2_DATA1_KEY2_DATA1_Msk = 0xffffffff

	// RD_KEY2_DATA2: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA2 field.
	EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Pos = 0x0
	// Bit mask of KEY2_DATA2 field.
	EFUSE_RD_KEY2_DATA2_KEY2_DATA2_Msk = 0xffffffff

	// RD_KEY2_DATA3: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA3 field.
	EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Pos = 0x0
	// Bit mask of KEY2_DATA3 field.
	EFUSE_RD_KEY2_DATA3_KEY2_DATA3_Msk = 0xffffffff

	// RD_KEY2_DATA4: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA4 field.
	EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Pos = 0x0
	// Bit mask of KEY2_DATA4 field.
	EFUSE_RD_KEY2_DATA4_KEY2_DATA4_Msk = 0xffffffff

	// RD_KEY2_DATA5: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA5 field.
	EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Pos = 0x0
	// Bit mask of KEY2_DATA5 field.
	EFUSE_RD_KEY2_DATA5_KEY2_DATA5_Msk = 0xffffffff

	// RD_KEY2_DATA6: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA6 field.
	EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Pos = 0x0
	// Bit mask of KEY2_DATA6 field.
	EFUSE_RD_KEY2_DATA6_KEY2_DATA6_Msk = 0xffffffff

	// RD_KEY2_DATA7: Register $n of BLOCK6 (KEY2).
	// Position of KEY2_DATA7 field.
	EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Pos = 0x0
	// Bit mask of KEY2_DATA7 field.
	EFUSE_RD_KEY2_DATA7_KEY2_DATA7_Msk = 0xffffffff

	// RD_KEY3_DATA0: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA0 field.
	EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Pos = 0x0
	// Bit mask of KEY3_DATA0 field.
	EFUSE_RD_KEY3_DATA0_KEY3_DATA0_Msk = 0xffffffff

	// RD_KEY3_DATA1: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA1 field.
	EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Pos = 0x0
	// Bit mask of KEY3_DATA1 field.
	EFUSE_RD_KEY3_DATA1_KEY3_DATA1_Msk = 0xffffffff

	// RD_KEY3_DATA2: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA2 field.
	EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Pos = 0x0
	// Bit mask of KEY3_DATA2 field.
	EFUSE_RD_KEY3_DATA2_KEY3_DATA2_Msk = 0xffffffff

	// RD_KEY3_DATA3: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA3 field.
	EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Pos = 0x0
	// Bit mask of KEY3_DATA3 field.
	EFUSE_RD_KEY3_DATA3_KEY3_DATA3_Msk = 0xffffffff

	// RD_KEY3_DATA4: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA4 field.
	EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Pos = 0x0
	// Bit mask of KEY3_DATA4 field.
	EFUSE_RD_KEY3_DATA4_KEY3_DATA4_Msk = 0xffffffff

	// RD_KEY3_DATA5: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA5 field.
	EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Pos = 0x0
	// Bit mask of KEY3_DATA5 field.
	EFUSE_RD_KEY3_DATA5_KEY3_DATA5_Msk = 0xffffffff

	// RD_KEY3_DATA6: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA6 field.
	EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Pos = 0x0
	// Bit mask of KEY3_DATA6 field.
	EFUSE_RD_KEY3_DATA6_KEY3_DATA6_Msk = 0xffffffff

	// RD_KEY3_DATA7: Register $n of BLOCK7 (KEY3).
	// Position of KEY3_DATA7 field.
	EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Pos = 0x0
	// Bit mask of KEY3_DATA7 field.
	EFUSE_RD_KEY3_DATA7_KEY3_DATA7_Msk = 0xffffffff

	// RD_KEY4_DATA0: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA0 field.
	EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Pos = 0x0
	// Bit mask of KEY4_DATA0 field.
	EFUSE_RD_KEY4_DATA0_KEY4_DATA0_Msk = 0xffffffff

	// RD_KEY4_DATA1: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA1 field.
	EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Pos = 0x0
	// Bit mask of KEY4_DATA1 field.
	EFUSE_RD_KEY4_DATA1_KEY4_DATA1_Msk = 0xffffffff

	// RD_KEY4_DATA2: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA2 field.
	EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Pos = 0x0
	// Bit mask of KEY4_DATA2 field.
	EFUSE_RD_KEY4_DATA2_KEY4_DATA2_Msk = 0xffffffff

	// RD_KEY4_DATA3: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA3 field.
	EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Pos = 0x0
	// Bit mask of KEY4_DATA3 field.
	EFUSE_RD_KEY4_DATA3_KEY4_DATA3_Msk = 0xffffffff

	// RD_KEY4_DATA4: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA4 field.
	EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Pos = 0x0
	// Bit mask of KEY4_DATA4 field.
	EFUSE_RD_KEY4_DATA4_KEY4_DATA4_Msk = 0xffffffff

	// RD_KEY4_DATA5: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA5 field.
	EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Pos = 0x0
	// Bit mask of KEY4_DATA5 field.
	EFUSE_RD_KEY4_DATA5_KEY4_DATA5_Msk = 0xffffffff

	// RD_KEY4_DATA6: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA6 field.
	EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Pos = 0x0
	// Bit mask of KEY4_DATA6 field.
	EFUSE_RD_KEY4_DATA6_KEY4_DATA6_Msk = 0xffffffff

	// RD_KEY4_DATA7: Register $n of BLOCK8 (KEY4).
	// Position of KEY4_DATA7 field.
	EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Pos = 0x0
	// Bit mask of KEY4_DATA7 field.
	EFUSE_RD_KEY4_DATA7_KEY4_DATA7_Msk = 0xffffffff

	// RD_KEY5_DATA0: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA0 field.
	EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Pos = 0x0
	// Bit mask of KEY5_DATA0 field.
	EFUSE_RD_KEY5_DATA0_KEY5_DATA0_Msk = 0xffffffff

	// RD_KEY5_DATA1: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA1 field.
	EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Pos = 0x0
	// Bit mask of KEY5_DATA1 field.
	EFUSE_RD_KEY5_DATA1_KEY5_DATA1_Msk = 0xffffffff

	// RD_KEY5_DATA2: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA2 field.
	EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Pos = 0x0
	// Bit mask of KEY5_DATA2 field.
	EFUSE_RD_KEY5_DATA2_KEY5_DATA2_Msk = 0xffffffff

	// RD_KEY5_DATA3: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA3 field.
	EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Pos = 0x0
	// Bit mask of KEY5_DATA3 field.
	EFUSE_RD_KEY5_DATA3_KEY5_DATA3_Msk = 0xffffffff

	// RD_KEY5_DATA4: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA4 field.
	EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Pos = 0x0
	// Bit mask of KEY5_DATA4 field.
	EFUSE_RD_KEY5_DATA4_KEY5_DATA4_Msk = 0xffffffff

	// RD_KEY5_DATA5: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA5 field.
	EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Pos = 0x0
	// Bit mask of KEY5_DATA5 field.
	EFUSE_RD_KEY5_DATA5_KEY5_DATA5_Msk = 0xffffffff

	// RD_KEY5_DATA6: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA6 field.
	EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Pos = 0x0
	// Bit mask of KEY5_DATA6 field.
	EFUSE_RD_KEY5_DATA6_KEY5_DATA6_Msk = 0xffffffff

	// RD_KEY5_DATA7: Register $n of BLOCK9 (KEY5).
	// Position of KEY5_DATA7 field.
	EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Pos = 0x0
	// Bit mask of KEY5_DATA7 field.
	EFUSE_RD_KEY5_DATA7_KEY5_DATA7_Msk = 0xffffffff

	// RD_SYS_PART2_DATA0: Register $n of BLOCK10 (system).
	// Position of SYS_DATA_PART2_0 field.
	EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_0 field.
	EFUSE_RD_SYS_PART2_DATA0_SYS_DATA_PART2_0_Msk = 0xffffffff

	// RD_SYS_PART2_DATA1: Register $n of BLOCK9 (KEY5).
	// Position of SYS_DATA_PART2_1 field.
	EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_1 field.
	EFUSE_RD_SYS_PART2_DATA1_SYS_DATA_PART2_1_Msk = 0xffffffff

	// RD_SYS_PART2_DATA2: Register $n of BLOCK10 (system).
	// Position of SYS_DATA_PART2_2 field.
	EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_2 field.
	EFUSE_RD_SYS_PART2_DATA2_SYS_DATA_PART2_2_Msk = 0xffffffff

	// RD_SYS_PART2_DATA3: Register $n of BLOCK10 (system).
	// Position of SYS_DATA_PART2_3 field.
	EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_3 field.
	EFUSE_RD_SYS_PART2_DATA3_SYS_DATA_PART2_3_Msk = 0xffffffff

	// RD_SYS_PART2_DATA4: Register $n of BLOCK10 (system).
	// Position of SYS_DATA_PART2_4 field.
	EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_4 field.
	EFUSE_RD_SYS_PART2_DATA4_SYS_DATA_PART2_4_Msk = 0xffffffff

	// RD_SYS_PART2_DATA5: Register $n of BLOCK10 (system).
	// Position of SYS_DATA_PART2_5 field.
	EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_5 field.
	EFUSE_RD_SYS_PART2_DATA5_SYS_DATA_PART2_5_Msk = 0xffffffff

	// RD_SYS_PART2_DATA6: Register $n of BLOCK10 (system).
	// Position of SYS_DATA_PART2_6 field.
	EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_6 field.
	EFUSE_RD_SYS_PART2_DATA6_SYS_DATA_PART2_6_Msk = 0xffffffff

	// RD_SYS_PART2_DATA7: Register $n of BLOCK10 (system).
	// Position of SYS_DATA_PART2_7 field.
	EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Pos = 0x0
	// Bit mask of SYS_DATA_PART2_7 field.
	EFUSE_RD_SYS_PART2_DATA7_SYS_DATA_PART2_7_Msk = 0xffffffff

	// RD_REPEAT_ERR0: Programming error record register 0 of BLOCK0.
	// Position of RD_DIS_ERR field.
	EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Pos = 0x0
	// Bit mask of RD_DIS_ERR field.
	EFUSE_RD_REPEAT_ERR0_RD_DIS_ERR_Msk = 0x7f
	// Position of DIS_USB_DEVICE_EXCHG_PINS_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_DEVICE_EXCHG_PINS_ERR_Pos = 0x7
	// Bit mask of DIS_USB_DEVICE_EXCHG_PINS_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_DEVICE_EXCHG_PINS_ERR_Msk = 0x80
	// Bit DIS_USB_DEVICE_EXCHG_PINS_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_DEVICE_EXCHG_PINS_ERR = 0x80
	// Position of DIS_USB_OTG11_EXCHG_PINS_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_OTG11_EXCHG_PINS_ERR_Pos = 0x8
	// Bit mask of DIS_USB_OTG11_EXCHG_PINS_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_OTG11_EXCHG_PINS_ERR_Msk = 0x100
	// Bit DIS_USB_OTG11_EXCHG_PINS_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_OTG11_EXCHG_PINS_ERR = 0x100
	// Position of DIS_USB_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Pos = 0x9
	// Bit mask of DIS_USB_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR_Msk = 0x200
	// Bit DIS_USB_JTAG_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_JTAG_ERR = 0x200
	// Position of POWERGLITCH_EN_ERR field.
	EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR_Pos = 0xa
	// Bit mask of POWERGLITCH_EN_ERR field.
	EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR_Msk = 0x400
	// Bit POWERGLITCH_EN_ERR.
	EFUSE_RD_REPEAT_ERR0_POWERGLITCH_EN_ERR = 0x400
	// Position of DIS_USB_SERIAL_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR_Pos = 0xb
	// Bit mask of DIS_USB_SERIAL_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR_Msk = 0x800
	// Bit DIS_USB_SERIAL_JTAG_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_USB_SERIAL_JTAG_ERR = 0x800
	// Position of DIS_FORCE_DOWNLOAD_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Pos = 0xc
	// Bit mask of DIS_FORCE_DOWNLOAD_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR_Msk = 0x1000
	// Bit DIS_FORCE_DOWNLOAD_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_FORCE_DOWNLOAD_ERR = 0x1000
	// Position of SPI_DOWNLOAD_MSPI_DIS_ERR field.
	EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR_Pos = 0xd
	// Bit mask of SPI_DOWNLOAD_MSPI_DIS_ERR field.
	EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR_Msk = 0x2000
	// Bit SPI_DOWNLOAD_MSPI_DIS_ERR.
	EFUSE_RD_REPEAT_ERR0_SPI_DOWNLOAD_MSPI_DIS_ERR = 0x2000
	// Position of DIS_TWAI_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR_Pos = 0xe
	// Bit mask of DIS_TWAI_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR_Msk = 0x4000
	// Bit DIS_TWAI_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_TWAI_ERR = 0x4000
	// Position of JTAG_SEL_ENABLE_ERR field.
	EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Pos = 0xf
	// Bit mask of JTAG_SEL_ENABLE_ERR field.
	EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR_Msk = 0x8000
	// Bit JTAG_SEL_ENABLE_ERR.
	EFUSE_RD_REPEAT_ERR0_JTAG_SEL_ENABLE_ERR = 0x8000
	// Position of SOFT_DIS_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Pos = 0x10
	// Bit mask of SOFT_DIS_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_SOFT_DIS_JTAG_ERR_Msk = 0x70000
	// Position of DIS_PAD_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Pos = 0x13
	// Bit mask of DIS_PAD_JTAG_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR_Msk = 0x80000
	// Bit DIS_PAD_JTAG_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_PAD_JTAG_ERR = 0x80000
	// Position of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Pos = 0x14
	// Bit mask of DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR field.
	EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_Msk = 0x100000
	// Bit DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR.
	EFUSE_RD_REPEAT_ERR0_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR = 0x100000
	// Position of USB_DEVICE_DREFH_ERR field.
	EFUSE_RD_REPEAT_ERR0_USB_DEVICE_DREFH_ERR_Pos = 0x15
	// Bit mask of USB_DEVICE_DREFH_ERR field.
	EFUSE_RD_REPEAT_ERR0_USB_DEVICE_DREFH_ERR_Msk = 0x600000
	// Position of USB_OTG11_DREFH_ERR field.
	EFUSE_RD_REPEAT_ERR0_USB_OTG11_DREFH_ERR_Pos = 0x17
	// Bit mask of USB_OTG11_DREFH_ERR field.
	EFUSE_RD_REPEAT_ERR0_USB_OTG11_DREFH_ERR_Msk = 0x1800000
	// Position of USB_PHY_SEL_ERR field.
	EFUSE_RD_REPEAT_ERR0_USB_PHY_SEL_ERR_Pos = 0x19
	// Bit mask of USB_PHY_SEL_ERR field.
	EFUSE_RD_REPEAT_ERR0_USB_PHY_SEL_ERR_Msk = 0x2000000
	// Bit USB_PHY_SEL_ERR.
	EFUSE_RD_REPEAT_ERR0_USB_PHY_SEL_ERR = 0x2000000
	// Position of HUK_GEN_STATE_LOW_ERR field.
	EFUSE_RD_REPEAT_ERR0_HUK_GEN_STATE_LOW_ERR_Pos = 0x1a
	// Bit mask of HUK_GEN_STATE_LOW_ERR field.
	EFUSE_RD_REPEAT_ERR0_HUK_GEN_STATE_LOW_ERR_Msk = 0xfc000000

	// RD_REPEAT_ERR1: Programming error record register 1 of BLOCK0.
	// Position of KM_HUK_GEN_STATE_HIGH_ERR field.
	EFUSE_RD_REPEAT_ERR1_KM_HUK_GEN_STATE_HIGH_ERR_Pos = 0x0
	// Bit mask of KM_HUK_GEN_STATE_HIGH_ERR field.
	EFUSE_RD_REPEAT_ERR1_KM_HUK_GEN_STATE_HIGH_ERR_Msk = 0x7
	// Position of KM_RND_SWITCH_CYCLE_ERR field.
	EFUSE_RD_REPEAT_ERR1_KM_RND_SWITCH_CYCLE_ERR_Pos = 0x3
	// Bit mask of KM_RND_SWITCH_CYCLE_ERR field.
	EFUSE_RD_REPEAT_ERR1_KM_RND_SWITCH_CYCLE_ERR_Msk = 0x18
	// Position of KM_DEPLOY_ONLY_ONCE_ERR field.
	EFUSE_RD_REPEAT_ERR1_KM_DEPLOY_ONLY_ONCE_ERR_Pos = 0x5
	// Bit mask of KM_DEPLOY_ONLY_ONCE_ERR field.
	EFUSE_RD_REPEAT_ERR1_KM_DEPLOY_ONLY_ONCE_ERR_Msk = 0x1e0
	// Position of FORCE_USE_KEY_MANAGER_KEY_ERR field.
	EFUSE_RD_REPEAT_ERR1_FORCE_USE_KEY_MANAGER_KEY_ERR_Pos = 0x9
	// Bit mask of FORCE_USE_KEY_MANAGER_KEY_ERR field.
	EFUSE_RD_REPEAT_ERR1_FORCE_USE_KEY_MANAGER_KEY_ERR_Msk = 0x1e00
	// Position of FORCE_DISABLE_SW_INIT_KEY_ERR field.
	EFUSE_RD_REPEAT_ERR1_FORCE_DISABLE_SW_INIT_KEY_ERR_Pos = 0xd
	// Bit mask of FORCE_DISABLE_SW_INIT_KEY_ERR field.
	EFUSE_RD_REPEAT_ERR1_FORCE_DISABLE_SW_INIT_KEY_ERR_Msk = 0x2000
	// Bit FORCE_DISABLE_SW_INIT_KEY_ERR.
	EFUSE_RD_REPEAT_ERR1_FORCE_DISABLE_SW_INIT_KEY_ERR = 0x2000
	// Position of XTS_KEY_LENGTH_256_ERR field.
	EFUSE_RD_REPEAT_ERR1_XTS_KEY_LENGTH_256_ERR_Pos = 0xe
	// Bit mask of XTS_KEY_LENGTH_256_ERR field.
	EFUSE_RD_REPEAT_ERR1_XTS_KEY_LENGTH_256_ERR_Msk = 0x4000
	// Bit XTS_KEY_LENGTH_256_ERR.
	EFUSE_RD_REPEAT_ERR1_XTS_KEY_LENGTH_256_ERR = 0x4000
	// Position of WDT_DELAY_SEL_ERR field.
	EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Pos = 0x10
	// Bit mask of WDT_DELAY_SEL_ERR field.
	EFUSE_RD_REPEAT_ERR1_WDT_DELAY_SEL_ERR_Msk = 0x30000
	// Position of SPI_BOOT_CRYPT_CNT_ERR field.
	EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Pos = 0x12
	// Bit mask of SPI_BOOT_CRYPT_CNT_ERR field.
	EFUSE_RD_REPEAT_ERR1_SPI_BOOT_CRYPT_CNT_ERR_Msk = 0x1c0000
	// Position of SECURE_BOOT_KEY_REVOKE0_ERR field.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Pos = 0x15
	// Bit mask of SECURE_BOOT_KEY_REVOKE0_ERR field.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR_Msk = 0x200000
	// Bit SECURE_BOOT_KEY_REVOKE0_ERR.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE0_ERR = 0x200000
	// Position of SECURE_BOOT_KEY_REVOKE1_ERR field.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Pos = 0x16
	// Bit mask of SECURE_BOOT_KEY_REVOKE1_ERR field.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR_Msk = 0x400000
	// Bit SECURE_BOOT_KEY_REVOKE1_ERR.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE1_ERR = 0x400000
	// Position of SECURE_BOOT_KEY_REVOKE2_ERR field.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Pos = 0x17
	// Bit mask of SECURE_BOOT_KEY_REVOKE2_ERR field.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR_Msk = 0x800000
	// Bit SECURE_BOOT_KEY_REVOKE2_ERR.
	EFUSE_RD_REPEAT_ERR1_SECURE_BOOT_KEY_REVOKE2_ERR = 0x800000
	// Position of KEY_PURPOSE_0_ERR field.
	EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Pos = 0x18
	// Bit mask of KEY_PURPOSE_0_ERR field.
	EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_0_ERR_Msk = 0xf000000
	// Position of KEY_PURPOSE_1_ERR field.
	EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Pos = 0x1c
	// Bit mask of KEY_PURPOSE_1_ERR field.
	EFUSE_RD_REPEAT_ERR1_KEY_PURPOSE_1_ERR_Msk = 0xf0000000

	// RD_REPEAT_ERR2: Programming error record register 2 of BLOCK0.
	// Position of KEY_PURPOSE_2_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Pos = 0x0
	// Bit mask of KEY_PURPOSE_2_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_2_ERR_Msk = 0xf
	// Position of KEY_PURPOSE_3_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Pos = 0x4
	// Bit mask of KEY_PURPOSE_3_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_3_ERR_Msk = 0xf0
	// Position of KEY_PURPOSE_4_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Pos = 0x8
	// Bit mask of KEY_PURPOSE_4_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_4_ERR_Msk = 0xf00
	// Position of KEY_PURPOSE_5_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Pos = 0xc
	// Bit mask of KEY_PURPOSE_5_ERR field.
	EFUSE_RD_REPEAT_ERR2_KEY_PURPOSE_5_ERR_Msk = 0xf000
	// Position of SEC_DPA_LEVEL_ERR field.
	EFUSE_RD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR_Pos = 0x10
	// Bit mask of SEC_DPA_LEVEL_ERR field.
	EFUSE_RD_REPEAT_ERR2_SEC_DPA_LEVEL_ERR_Msk = 0x30000
	// Position of ECDSA_ENABLE_SOFT_K_ERR field.
	EFUSE_RD_REPEAT_ERR2_ECDSA_ENABLE_SOFT_K_ERR_Pos = 0x12
	// Bit mask of ECDSA_ENABLE_SOFT_K_ERR field.
	EFUSE_RD_REPEAT_ERR2_ECDSA_ENABLE_SOFT_K_ERR_Msk = 0x40000
	// Bit ECDSA_ENABLE_SOFT_K_ERR.
	EFUSE_RD_REPEAT_ERR2_ECDSA_ENABLE_SOFT_K_ERR = 0x40000
	// Position of CRYPT_DPA_ENABLE_ERR field.
	EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR_Pos = 0x13
	// Bit mask of CRYPT_DPA_ENABLE_ERR field.
	EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR_Msk = 0x80000
	// Bit CRYPT_DPA_ENABLE_ERR.
	EFUSE_RD_REPEAT_ERR2_CRYPT_DPA_ENABLE_ERR = 0x80000
	// Position of SECURE_BOOT_EN_ERR field.
	EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Pos = 0x14
	// Bit mask of SECURE_BOOT_EN_ERR field.
	EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR_Msk = 0x100000
	// Bit SECURE_BOOT_EN_ERR.
	EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_EN_ERR = 0x100000
	// Position of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field.
	EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Pos = 0x15
	// Bit mask of SECURE_BOOT_AGGRESSIVE_REVOKE_ERR field.
	EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_Msk = 0x200000
	// Bit SECURE_BOOT_AGGRESSIVE_REVOKE_ERR.
	EFUSE_RD_REPEAT_ERR2_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR = 0x200000
	// Position of FLASH_TYPE_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_TYPE_ERR_Pos = 0x17
	// Bit mask of FLASH_TYPE_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_TYPE_ERR_Msk = 0x800000
	// Bit FLASH_TYPE_ERR.
	EFUSE_RD_REPEAT_ERR2_FLASH_TYPE_ERR = 0x800000
	// Position of FLASH_PAGE_SIZE_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_PAGE_SIZE_ERR_Pos = 0x18
	// Bit mask of FLASH_PAGE_SIZE_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_PAGE_SIZE_ERR_Msk = 0x3000000
	// Position of FLASH_ECC_EN_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_ECC_EN_ERR_Pos = 0x1a
	// Bit mask of FLASH_ECC_EN_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_ECC_EN_ERR_Msk = 0x4000000
	// Bit FLASH_ECC_EN_ERR.
	EFUSE_RD_REPEAT_ERR2_FLASH_ECC_EN_ERR = 0x4000000
	// Position of DIS_USB_OTG_DOWNLOAD_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR2_DIS_USB_OTG_DOWNLOAD_MODE_ERR_Pos = 0x1b
	// Bit mask of DIS_USB_OTG_DOWNLOAD_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR2_DIS_USB_OTG_DOWNLOAD_MODE_ERR_Msk = 0x8000000
	// Bit DIS_USB_OTG_DOWNLOAD_MODE_ERR.
	EFUSE_RD_REPEAT_ERR2_DIS_USB_OTG_DOWNLOAD_MODE_ERR = 0x8000000
	// Position of FLASH_TPUW_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Pos = 0x1c
	// Bit mask of FLASH_TPUW_ERR field.
	EFUSE_RD_REPEAT_ERR2_FLASH_TPUW_ERR_Msk = 0xf0000000

	// RD_REPEAT_ERR3: Programming error record register 3 of BLOCK0.
	// Position of DIS_DOWNLOAD_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Pos = 0x0
	// Bit mask of DIS_DOWNLOAD_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR_Msk = 0x1
	// Bit DIS_DOWNLOAD_MODE_ERR.
	EFUSE_RD_REPEAT_ERR3_DIS_DOWNLOAD_MODE_ERR = 0x1
	// Position of DIS_DIRECT_BOOT_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR_Pos = 0x1
	// Bit mask of DIS_DIRECT_BOOT_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR_Msk = 0x2
	// Bit DIS_DIRECT_BOOT_ERR.
	EFUSE_RD_REPEAT_ERR3_DIS_DIRECT_BOOT_ERR = 0x2
	// Position of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_Pos = 0x2
	// Bit mask of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_Msk = 0x4
	// Bit DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
	EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR = 0x4
	// Position of LOCK_KM_KEY_ERR field.
	EFUSE_RD_REPEAT_ERR3_LOCK_KM_KEY_ERR_Pos = 0x3
	// Bit mask of LOCK_KM_KEY_ERR field.
	EFUSE_RD_REPEAT_ERR3_LOCK_KM_KEY_ERR_Msk = 0x8
	// Bit LOCK_KM_KEY_ERR.
	EFUSE_RD_REPEAT_ERR3_LOCK_KM_KEY_ERR = 0x8
	// Position of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_Pos = 0x4
	// Bit mask of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_Msk = 0x10
	// Bit DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR.
	EFUSE_RD_REPEAT_ERR3_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR = 0x10
	// Position of ENABLE_SECURITY_DOWNLOAD_ERR field.
	EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Pos = 0x5
	// Bit mask of ENABLE_SECURITY_DOWNLOAD_ERR field.
	EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR_Msk = 0x20
	// Bit ENABLE_SECURITY_DOWNLOAD_ERR.
	EFUSE_RD_REPEAT_ERR3_ENABLE_SECURITY_DOWNLOAD_ERR = 0x20
	// Position of UART_PRINT_CONTROL_ERR field.
	EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Pos = 0x6
	// Bit mask of UART_PRINT_CONTROL_ERR field.
	EFUSE_RD_REPEAT_ERR3_UART_PRINT_CONTROL_ERR_Msk = 0xc0
	// Position of FORCE_SEND_RESUME_ERR field.
	EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Pos = 0x8
	// Bit mask of FORCE_SEND_RESUME_ERR field.
	EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR_Msk = 0x100
	// Bit FORCE_SEND_RESUME_ERR.
	EFUSE_RD_REPEAT_ERR3_FORCE_SEND_RESUME_ERR = 0x100
	// Position of SECURE_VERSION_ERR field.
	EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Pos = 0x9
	// Bit mask of SECURE_VERSION_ERR field.
	EFUSE_RD_REPEAT_ERR3_SECURE_VERSION_ERR_Msk = 0x1fffe00
	// Position of SECURE_BOOT_DISABLE_FAST_WAKE_ERR field.
	EFUSE_RD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_Pos = 0x19
	// Bit mask of SECURE_BOOT_DISABLE_FAST_WAKE_ERR field.
	EFUSE_RD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_Msk = 0x2000000
	// Bit SECURE_BOOT_DISABLE_FAST_WAKE_ERR.
	EFUSE_RD_REPEAT_ERR3_SECURE_BOOT_DISABLE_FAST_WAKE_ERR = 0x2000000
	// Position of HYS_EN_PAD_ERR field.
	EFUSE_RD_REPEAT_ERR3_HYS_EN_PAD_ERR_Pos = 0x1a
	// Bit mask of HYS_EN_PAD_ERR field.
	EFUSE_RD_REPEAT_ERR3_HYS_EN_PAD_ERR_Msk = 0x4000000
	// Bit HYS_EN_PAD_ERR.
	EFUSE_RD_REPEAT_ERR3_HYS_EN_PAD_ERR = 0x4000000
	// Position of DCDC_VSET_ERR field.
	EFUSE_RD_REPEAT_ERR3_DCDC_VSET_ERR_Pos = 0x1b
	// Bit mask of DCDC_VSET_ERR field.
	EFUSE_RD_REPEAT_ERR3_DCDC_VSET_ERR_Msk = 0xf8000000

	// RD_REPEAT_ERR4: Programming error record register 4 of BLOCK0.
	// Position of _0PXA_TIEH_SEL_0_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_0_ERR_Pos = 0x0
	// Bit mask of _0PXA_TIEH_SEL_0_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_0_ERR_Msk = 0x3
	// Position of _0PXA_TIEH_SEL_1_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_1_ERR_Pos = 0x2
	// Bit mask of _0PXA_TIEH_SEL_1_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_1_ERR_Msk = 0xc
	// Position of _0PXA_TIEH_SEL_2_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_2_ERR_Pos = 0x4
	// Bit mask of _0PXA_TIEH_SEL_2_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_2_ERR_Msk = 0x30
	// Position of _0PXA_TIEH_SEL_3_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_3_ERR_Pos = 0x6
	// Bit mask of _0PXA_TIEH_SEL_3_ERR field.
	EFUSE_RD_REPEAT_ERR4__0PXA_TIEH_SEL_3_ERR_Msk = 0xc0
	// Position of KM_DISABLE_DEPLOY_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR4_KM_DISABLE_DEPLOY_MODE_ERR_Pos = 0x8
	// Bit mask of KM_DISABLE_DEPLOY_MODE_ERR field.
	EFUSE_RD_REPEAT_ERR4_KM_DISABLE_DEPLOY_MODE_ERR_Msk = 0xf00
	// Position of USB_DEVICE_DREFL_ERR field.
	EFUSE_RD_REPEAT_ERR4_USB_DEVICE_DREFL_ERR_Pos = 0xc
	// Bit mask of USB_DEVICE_DREFL_ERR field.
	EFUSE_RD_REPEAT_ERR4_USB_DEVICE_DREFL_ERR_Msk = 0x3000
	// Position of USB_OTG11_DREFL_ERR field.
	EFUSE_RD_REPEAT_ERR4_USB_OTG11_DREFL_ERR_Pos = 0xe
	// Bit mask of USB_OTG11_DREFL_ERR field.
	EFUSE_RD_REPEAT_ERR4_USB_OTG11_DREFL_ERR_Msk = 0xc000
	// Position of HP_PWR_SRC_SEL_ERR field.
	EFUSE_RD_REPEAT_ERR4_HP_PWR_SRC_SEL_ERR_Pos = 0x12
	// Bit mask of HP_PWR_SRC_SEL_ERR field.
	EFUSE_RD_REPEAT_ERR4_HP_PWR_SRC_SEL_ERR_Msk = 0x40000
	// Bit HP_PWR_SRC_SEL_ERR.
	EFUSE_RD_REPEAT_ERR4_HP_PWR_SRC_SEL_ERR = 0x40000
	// Position of DCDC_VSET_EN_ERR field.
	EFUSE_RD_REPEAT_ERR4_DCDC_VSET_EN_ERR_Pos = 0x13
	// Bit mask of DCDC_VSET_EN_ERR field.
	EFUSE_RD_REPEAT_ERR4_DCDC_VSET_EN_ERR_Msk = 0x80000
	// Bit DCDC_VSET_EN_ERR.
	EFUSE_RD_REPEAT_ERR4_DCDC_VSET_EN_ERR = 0x80000
	// Position of DIS_WDT_ERR field.
	EFUSE_RD_REPEAT_ERR4_DIS_WDT_ERR_Pos = 0x14
	// Bit mask of DIS_WDT_ERR field.
	EFUSE_RD_REPEAT_ERR4_DIS_WDT_ERR_Msk = 0x100000
	// Bit DIS_WDT_ERR.
	EFUSE_RD_REPEAT_ERR4_DIS_WDT_ERR = 0x100000
	// Position of DIS_SWD_ERR field.
	EFUSE_RD_REPEAT_ERR4_DIS_SWD_ERR_Pos = 0x15
	// Bit mask of DIS_SWD_ERR field.
	EFUSE_RD_REPEAT_ERR4_DIS_SWD_ERR_Msk = 0x200000
	// Bit DIS_SWD_ERR.
	EFUSE_RD_REPEAT_ERR4_DIS_SWD_ERR = 0x200000

	// RD_RS_ERR0: Programming error record register 0 of BLOCK1-10.
	// Position of MAC_SYS_ERR_NUM field.
	EFUSE_RD_RS_ERR0_MAC_SYS_ERR_NUM_Pos = 0x0
	// Bit mask of MAC_SYS_ERR_NUM field.
	EFUSE_RD_RS_ERR0_MAC_SYS_ERR_NUM_Msk = 0x7
	// Position of MAC_SYS_FAIL field.
	EFUSE_RD_RS_ERR0_MAC_SYS_FAIL_Pos = 0x3
	// Bit mask of MAC_SYS_FAIL field.
	EFUSE_RD_RS_ERR0_MAC_SYS_FAIL_Msk = 0x8
	// Bit MAC_SYS_FAIL.
	EFUSE_RD_RS_ERR0_MAC_SYS_FAIL = 0x8
	// Position of SYS_PART1_ERR_NUM field.
	EFUSE_RD_RS_ERR0_SYS_PART1_ERR_NUM_Pos = 0x4
	// Bit mask of SYS_PART1_ERR_NUM field.
	EFUSE_RD_RS_ERR0_SYS_PART1_ERR_NUM_Msk = 0x70
	// Position of SYS_PART1_FAIL field.
	EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Pos = 0x7
	// Bit mask of SYS_PART1_FAIL field.
	EFUSE_RD_RS_ERR0_SYS_PART1_FAIL_Msk = 0x80
	// Bit SYS_PART1_FAIL.
	EFUSE_RD_RS_ERR0_SYS_PART1_FAIL = 0x80
	// Position of USR_DATA_ERR_NUM field.
	EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Pos = 0x8
	// Bit mask of USR_DATA_ERR_NUM field.
	EFUSE_RD_RS_ERR0_USR_DATA_ERR_NUM_Msk = 0x700
	// Position of USR_DATA_FAIL field.
	EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Pos = 0xb
	// Bit mask of USR_DATA_FAIL field.
	EFUSE_RD_RS_ERR0_USR_DATA_FAIL_Msk = 0x800
	// Bit USR_DATA_FAIL.
	EFUSE_RD_RS_ERR0_USR_DATA_FAIL = 0x800
	// Position of KEY0_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Pos = 0xc
	// Bit mask of KEY0_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY0_ERR_NUM_Msk = 0x7000
	// Position of KEY0_FAIL field.
	EFUSE_RD_RS_ERR0_KEY0_FAIL_Pos = 0xf
	// Bit mask of KEY0_FAIL field.
	EFUSE_RD_RS_ERR0_KEY0_FAIL_Msk = 0x8000
	// Bit KEY0_FAIL.
	EFUSE_RD_RS_ERR0_KEY0_FAIL = 0x8000
	// Position of KEY1_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Pos = 0x10
	// Bit mask of KEY1_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY1_ERR_NUM_Msk = 0x70000
	// Position of KEY1_FAIL field.
	EFUSE_RD_RS_ERR0_KEY1_FAIL_Pos = 0x13
	// Bit mask of KEY1_FAIL field.
	EFUSE_RD_RS_ERR0_KEY1_FAIL_Msk = 0x80000
	// Bit KEY1_FAIL.
	EFUSE_RD_RS_ERR0_KEY1_FAIL = 0x80000
	// Position of KEY2_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Pos = 0x14
	// Bit mask of KEY2_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY2_ERR_NUM_Msk = 0x700000
	// Position of KEY2_FAIL field.
	EFUSE_RD_RS_ERR0_KEY2_FAIL_Pos = 0x17
	// Bit mask of KEY2_FAIL field.
	EFUSE_RD_RS_ERR0_KEY2_FAIL_Msk = 0x800000
	// Bit KEY2_FAIL.
	EFUSE_RD_RS_ERR0_KEY2_FAIL = 0x800000
	// Position of KEY3_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Pos = 0x18
	// Bit mask of KEY3_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY3_ERR_NUM_Msk = 0x7000000
	// Position of KEY3_FAIL field.
	EFUSE_RD_RS_ERR0_KEY3_FAIL_Pos = 0x1b
	// Bit mask of KEY3_FAIL field.
	EFUSE_RD_RS_ERR0_KEY3_FAIL_Msk = 0x8000000
	// Bit KEY3_FAIL.
	EFUSE_RD_RS_ERR0_KEY3_FAIL = 0x8000000
	// Position of KEY4_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Pos = 0x1c
	// Bit mask of KEY4_ERR_NUM field.
	EFUSE_RD_RS_ERR0_KEY4_ERR_NUM_Msk = 0x70000000
	// Position of KEY4_FAIL field.
	EFUSE_RD_RS_ERR0_KEY4_FAIL_Pos = 0x1f
	// Bit mask of KEY4_FAIL field.
	EFUSE_RD_RS_ERR0_KEY4_FAIL_Msk = 0x80000000
	// Bit KEY4_FAIL.
	EFUSE_RD_RS_ERR0_KEY4_FAIL = 0x80000000

	// RD_RS_ERR1: Programming error record register 1 of BLOCK1-10.
	// Position of KEY5_ERR_NUM field.
	EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Pos = 0x0
	// Bit mask of KEY5_ERR_NUM field.
	EFUSE_RD_RS_ERR1_KEY5_ERR_NUM_Msk = 0x7
	// Position of KEY5_FAIL field.
	EFUSE_RD_RS_ERR1_KEY5_FAIL_Pos = 0x3
	// Bit mask of KEY5_FAIL field.
	EFUSE_RD_RS_ERR1_KEY5_FAIL_Msk = 0x8
	// Bit KEY5_FAIL.
	EFUSE_RD_RS_ERR1_KEY5_FAIL = 0x8
	// Position of SYS_PART2_ERR_NUM field.
	EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Pos = 0x4
	// Bit mask of SYS_PART2_ERR_NUM field.
	EFUSE_RD_RS_ERR1_SYS_PART2_ERR_NUM_Msk = 0x70
	// Position of SYS_PART2_FAIL field.
	EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Pos = 0x7
	// Bit mask of SYS_PART2_FAIL field.
	EFUSE_RD_RS_ERR1_SYS_PART2_FAIL_Msk = 0x80
	// Bit SYS_PART2_FAIL.
	EFUSE_RD_RS_ERR1_SYS_PART2_FAIL = 0x80

	// CLK: eFuse clcok configuration register.
	// Position of MEM_FORCE_PD field.
	EFUSE_CLK_MEM_FORCE_PD_Pos = 0x0
	// Bit mask of MEM_FORCE_PD field.
	EFUSE_CLK_MEM_FORCE_PD_Msk = 0x1
	// Bit MEM_FORCE_PD.
	EFUSE_CLK_MEM_FORCE_PD = 0x1
	// Position of MEM_CLK_FORCE_ON field.
	EFUSE_CLK_MEM_CLK_FORCE_ON_Pos = 0x1
	// Bit mask of MEM_CLK_FORCE_ON field.
	EFUSE_CLK_MEM_CLK_FORCE_ON_Msk = 0x2
	// Bit MEM_CLK_FORCE_ON.
	EFUSE_CLK_MEM_CLK_FORCE_ON = 0x2
	// Position of MEM_FORCE_PU field.
	EFUSE_CLK_MEM_FORCE_PU_Pos = 0x2
	// Bit mask of MEM_FORCE_PU field.
	EFUSE_CLK_MEM_FORCE_PU_Msk = 0x4
	// Bit MEM_FORCE_PU.
	EFUSE_CLK_MEM_FORCE_PU = 0x4
	// Position of EN field.
	EFUSE_CLK_EN_Pos = 0x10
	// Bit mask of EN field.
	EFUSE_CLK_EN_Msk = 0x10000
	// Bit EN.
	EFUSE_CLK_EN = 0x10000

	// CONF: eFuse operation mode configuraiton register
	// Position of OP_CODE field.
	EFUSE_CONF_OP_CODE_Pos = 0x0
	// Bit mask of OP_CODE field.
	EFUSE_CONF_OP_CODE_Msk = 0xffff
	// Position of CFG_ECDSA_BLK field.
	EFUSE_CONF_CFG_ECDSA_BLK_Pos = 0x10
	// Bit mask of CFG_ECDSA_BLK field.
	EFUSE_CONF_CFG_ECDSA_BLK_Msk = 0xf0000

	// STATUS: eFuse status register.
	// Position of STATE field.
	EFUSE_STATUS_STATE_Pos = 0x0
	// Bit mask of STATE field.
	EFUSE_STATUS_STATE_Msk = 0xf
	// Position of OTP_LOAD_SW field.
	EFUSE_STATUS_OTP_LOAD_SW_Pos = 0x4
	// Bit mask of OTP_LOAD_SW field.
	EFUSE_STATUS_OTP_LOAD_SW_Msk = 0x10
	// Bit OTP_LOAD_SW.
	EFUSE_STATUS_OTP_LOAD_SW = 0x10
	// Position of OTP_VDDQ_C_SYNC2 field.
	EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Pos = 0x5
	// Bit mask of OTP_VDDQ_C_SYNC2 field.
	EFUSE_STATUS_OTP_VDDQ_C_SYNC2_Msk = 0x20
	// Bit OTP_VDDQ_C_SYNC2.
	EFUSE_STATUS_OTP_VDDQ_C_SYNC2 = 0x20
	// Position of OTP_STROBE_SW field.
	EFUSE_STATUS_OTP_STROBE_SW_Pos = 0x6
	// Bit mask of OTP_STROBE_SW field.
	EFUSE_STATUS_OTP_STROBE_SW_Msk = 0x40
	// Bit OTP_STROBE_SW.
	EFUSE_STATUS_OTP_STROBE_SW = 0x40
	// Position of OTP_CSB_SW field.
	EFUSE_STATUS_OTP_CSB_SW_Pos = 0x7
	// Bit mask of OTP_CSB_SW field.
	EFUSE_STATUS_OTP_CSB_SW_Msk = 0x80
	// Bit OTP_CSB_SW.
	EFUSE_STATUS_OTP_CSB_SW = 0x80
	// Position of OTP_PGENB_SW field.
	EFUSE_STATUS_OTP_PGENB_SW_Pos = 0x8
	// Bit mask of OTP_PGENB_SW field.
	EFUSE_STATUS_OTP_PGENB_SW_Msk = 0x100
	// Bit OTP_PGENB_SW.
	EFUSE_STATUS_OTP_PGENB_SW = 0x100
	// Position of OTP_VDDQ_IS_SW field.
	EFUSE_STATUS_OTP_VDDQ_IS_SW_Pos = 0x9
	// Bit mask of OTP_VDDQ_IS_SW field.
	EFUSE_STATUS_OTP_VDDQ_IS_SW_Msk = 0x200
	// Bit OTP_VDDQ_IS_SW.
	EFUSE_STATUS_OTP_VDDQ_IS_SW = 0x200
	// Position of BLK0_VALID_BIT_CNT field.
	EFUSE_STATUS_BLK0_VALID_BIT_CNT_Pos = 0xa
	// Bit mask of BLK0_VALID_BIT_CNT field.
	EFUSE_STATUS_BLK0_VALID_BIT_CNT_Msk = 0xffc00
	// Position of CUR_ECDSA_BLK field.
	EFUSE_STATUS_CUR_ECDSA_BLK_Pos = 0x14
	// Bit mask of CUR_ECDSA_BLK field.
	EFUSE_STATUS_CUR_ECDSA_BLK_Msk = 0xf00000

	// CMD: eFuse command register.
	// Position of READ_CMD field.
	EFUSE_CMD_READ_CMD_Pos = 0x0
	// Bit mask of READ_CMD field.
	EFUSE_CMD_READ_CMD_Msk = 0x1
	// Bit READ_CMD.
	EFUSE_CMD_READ_CMD = 0x1
	// Position of PGM_CMD field.
	EFUSE_CMD_PGM_CMD_Pos = 0x1
	// Bit mask of PGM_CMD field.
	EFUSE_CMD_PGM_CMD_Msk = 0x2
	// Bit PGM_CMD.
	EFUSE_CMD_PGM_CMD = 0x2
	// Position of BLK_NUM field.
	EFUSE_CMD_BLK_NUM_Pos = 0x2
	// Bit mask of BLK_NUM field.
	EFUSE_CMD_BLK_NUM_Msk = 0x3c

	// INT_RAW: eFuse raw interrupt register.
	// Position of READ_DONE_INT_RAW field.
	EFUSE_INT_RAW_READ_DONE_INT_RAW_Pos = 0x0
	// Bit mask of READ_DONE_INT_RAW field.
	EFUSE_INT_RAW_READ_DONE_INT_RAW_Msk = 0x1
	// Bit READ_DONE_INT_RAW.
	EFUSE_INT_RAW_READ_DONE_INT_RAW = 0x1
	// Position of PGM_DONE_INT_RAW field.
	EFUSE_INT_RAW_PGM_DONE_INT_RAW_Pos = 0x1
	// Bit mask of PGM_DONE_INT_RAW field.
	EFUSE_INT_RAW_PGM_DONE_INT_RAW_Msk = 0x2
	// Bit PGM_DONE_INT_RAW.
	EFUSE_INT_RAW_PGM_DONE_INT_RAW = 0x2

	// INT_ST: eFuse interrupt status register.
	// Position of READ_DONE_INT_ST field.
	EFUSE_INT_ST_READ_DONE_INT_ST_Pos = 0x0
	// Bit mask of READ_DONE_INT_ST field.
	EFUSE_INT_ST_READ_DONE_INT_ST_Msk = 0x1
	// Bit READ_DONE_INT_ST.
	EFUSE_INT_ST_READ_DONE_INT_ST = 0x1
	// Position of PGM_DONE_INT_ST field.
	EFUSE_INT_ST_PGM_DONE_INT_ST_Pos = 0x1
	// Bit mask of PGM_DONE_INT_ST field.
	EFUSE_INT_ST_PGM_DONE_INT_ST_Msk = 0x2
	// Bit PGM_DONE_INT_ST.
	EFUSE_INT_ST_PGM_DONE_INT_ST = 0x2

	// INT_ENA: eFuse interrupt enable register.
	// Position of READ_DONE_INT_ENA field.
	EFUSE_INT_ENA_READ_DONE_INT_ENA_Pos = 0x0
	// Bit mask of READ_DONE_INT_ENA field.
	EFUSE_INT_ENA_READ_DONE_INT_ENA_Msk = 0x1
	// Bit READ_DONE_INT_ENA.
	EFUSE_INT_ENA_READ_DONE_INT_ENA = 0x1
	// Position of PGM_DONE_INT_ENA field.
	EFUSE_INT_ENA_PGM_DONE_INT_ENA_Pos = 0x1
	// Bit mask of PGM_DONE_INT_ENA field.
	EFUSE_INT_ENA_PGM_DONE_INT_ENA_Msk = 0x2
	// Bit PGM_DONE_INT_ENA.
	EFUSE_INT_ENA_PGM_DONE_INT_ENA = 0x2

	// INT_CLR: eFuse interrupt clear register.
	// Position of READ_DONE_INT_CLR field.
	EFUSE_INT_CLR_READ_DONE_INT_CLR_Pos = 0x0
	// Bit mask of READ_DONE_INT_CLR field.
	EFUSE_INT_CLR_READ_DONE_INT_CLR_Msk = 0x1
	// Bit READ_DONE_INT_CLR.
	EFUSE_INT_CLR_READ_DONE_INT_CLR = 0x1
	// Position of PGM_DONE_INT_CLR field.
	EFUSE_INT_CLR_PGM_DONE_INT_CLR_Pos = 0x1
	// Bit mask of PGM_DONE_INT_CLR field.
	EFUSE_INT_CLR_PGM_DONE_INT_CLR_Msk = 0x2
	// Bit PGM_DONE_INT_CLR.
	EFUSE_INT_CLR_PGM_DONE_INT_CLR = 0x2

	// DAC_CONF: Controls the eFuse programming voltage.
	// Position of DAC_CLK_DIV field.
	EFUSE_DAC_CONF_DAC_CLK_DIV_Pos = 0x0
	// Bit mask of DAC_CLK_DIV field.
	EFUSE_DAC_CONF_DAC_CLK_DIV_Msk = 0xff
	// Position of DAC_CLK_PAD_SEL field.
	EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Pos = 0x8
	// Bit mask of DAC_CLK_PAD_SEL field.
	EFUSE_DAC_CONF_DAC_CLK_PAD_SEL_Msk = 0x100
	// Bit DAC_CLK_PAD_SEL.
	EFUSE_DAC_CONF_DAC_CLK_PAD_SEL = 0x100
	// Position of DAC_NUM field.
	EFUSE_DAC_CONF_DAC_NUM_Pos = 0x9
	// Bit mask of DAC_NUM field.
	EFUSE_DAC_CONF_DAC_NUM_Msk = 0x1fe00
	// Position of OE_CLR field.
	EFUSE_DAC_CONF_OE_CLR_Pos = 0x11
	// Bit mask of OE_CLR field.
	EFUSE_DAC_CONF_OE_CLR_Msk = 0x20000
	// Bit OE_CLR.
	EFUSE_DAC_CONF_OE_CLR = 0x20000

	// RD_TIM_CONF: Configures read timing parameters.
	// Position of THR_A field.
	EFUSE_RD_TIM_CONF_THR_A_Pos = 0x0
	// Bit mask of THR_A field.
	EFUSE_RD_TIM_CONF_THR_A_Msk = 0xff
	// Position of TRD field.
	EFUSE_RD_TIM_CONF_TRD_Pos = 0x8
	// Bit mask of TRD field.
	EFUSE_RD_TIM_CONF_TRD_Msk = 0xff00
	// Position of TSUR_A field.
	EFUSE_RD_TIM_CONF_TSUR_A_Pos = 0x10
	// Bit mask of TSUR_A field.
	EFUSE_RD_TIM_CONF_TSUR_A_Msk = 0xff0000
	// Position of READ_INIT_NUM field.
	EFUSE_RD_TIM_CONF_READ_INIT_NUM_Pos = 0x18
	// Bit mask of READ_INIT_NUM field.
	EFUSE_RD_TIM_CONF_READ_INIT_NUM_Msk = 0xff000000

	// WR_TIM_CONF1: Configurarion register 1 of eFuse programming timing parameters.
	// Position of TSUP_A field.
	EFUSE_WR_TIM_CONF1_TSUP_A_Pos = 0x0
	// Bit mask of TSUP_A field.
	EFUSE_WR_TIM_CONF1_TSUP_A_Msk = 0xff
	// Position of PWR_ON_NUM field.
	EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Pos = 0x8
	// Bit mask of PWR_ON_NUM field.
	EFUSE_WR_TIM_CONF1_PWR_ON_NUM_Msk = 0xffff00
	// Position of THP_A field.
	EFUSE_WR_TIM_CONF1_THP_A_Pos = 0x18
	// Bit mask of THP_A field.
	EFUSE_WR_TIM_CONF1_THP_A_Msk = 0xff000000

	// WR_TIM_CONF2: Configurarion register 2 of eFuse programming timing parameters.
	// Position of PWR_OFF_NUM field.
	EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Pos = 0x0
	// Bit mask of PWR_OFF_NUM field.
	EFUSE_WR_TIM_CONF2_PWR_OFF_NUM_Msk = 0xffff
	// Position of TPGM field.
	EFUSE_WR_TIM_CONF2_TPGM_Pos = 0x10
	// Bit mask of TPGM field.
	EFUSE_WR_TIM_CONF2_TPGM_Msk = 0xffff0000

	// WR_TIM_CONF0_RS_BYPASS: Configurarion register0 of eFuse programming time parameters and rs bypass operation.
	// Position of BYPASS_RS_CORRECTION field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION_Pos = 0x0
	// Bit mask of BYPASS_RS_CORRECTION field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION_Msk = 0x1
	// Bit BYPASS_RS_CORRECTION.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_CORRECTION = 0x1
	// Position of BYPASS_RS_BLK_NUM field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM_Pos = 0x1
	// Bit mask of BYPASS_RS_BLK_NUM field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_BYPASS_RS_BLK_NUM_Msk = 0xffe
	// Position of UPDATE field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE_Pos = 0xc
	// Bit mask of UPDATE field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE_Msk = 0x1000
	// Bit UPDATE.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_UPDATE = 0x1000
	// Position of TPGM_INACTIVE field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE_Pos = 0xd
	// Bit mask of TPGM_INACTIVE field.
	EFUSE_WR_TIM_CONF0_RS_BYPASS_TPGM_INACTIVE_Msk = 0x1fe000

	// DATE: eFuse version register.
	// Position of DATE field.
	EFUSE_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	EFUSE_DATE_DATE_Msk = 0xfffffff

	// APB2OTP_WR_DIS: eFuse apb2otp block0 data register1.
	// Position of APB2OTP_BLOCK0_WR_DIS field.
	EFUSE_APB2OTP_WR_DIS_APB2OTP_BLOCK0_WR_DIS_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_WR_DIS field.
	EFUSE_APB2OTP_WR_DIS_APB2OTP_BLOCK0_WR_DIS_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP1_W1: eFuse apb2otp block0 data register2.
	// Position of APB2OTP_BLOCK0_BACKUP1_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W1_APB2OTP_BLOCK0_BACKUP1_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP1_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W1_APB2OTP_BLOCK0_BACKUP1_W1_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP1_W2: eFuse apb2otp block0 data register3.
	// Position of APB2OTP_BLOCK0_BACKUP1_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W2_APB2OTP_BLOCK0_BACKUP1_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP1_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W2_APB2OTP_BLOCK0_BACKUP1_W2_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP1_W3: eFuse apb2otp block0 data register4.
	// Position of APB2OTP_BLOCK0_BACKUP1_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W3_APB2OTP_BLOCK0_BACKUP1_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP1_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W3_APB2OTP_BLOCK0_BACKUP1_W3_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP1_W4: eFuse apb2otp block0 data register5.
	// Position of APB2OTP_BLOCK0_BACKUP1_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W4_APB2OTP_BLOCK0_BACKUP1_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP1_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W4_APB2OTP_BLOCK0_BACKUP1_W4_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP1_W5: eFuse apb2otp block0 data register6.
	// Position of APB2OTP_BLOCK0_BACKUP1_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W5_APB2OTP_BLOCK0_BACKUP1_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP1_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP1_W5_APB2OTP_BLOCK0_BACKUP1_W5_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP2_W1: eFuse apb2otp block0 data register7.
	// Position of APB2OTP_BLOCK0_BACKUP2_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W1_APB2OTP_BLOCK0_BACKUP2_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP2_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W1_APB2OTP_BLOCK0_BACKUP2_W1_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP2_W2: eFuse apb2otp block0 data register8.
	// Position of APB2OTP_BLOCK0_BACKUP2_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W2_APB2OTP_BLOCK0_BACKUP2_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP2_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W2_APB2OTP_BLOCK0_BACKUP2_W2_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP2_W3: eFuse apb2otp block0 data register9.
	// Position of APB2OTP_BLOCK0_BACKUP2_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W3_APB2OTP_BLOCK0_BACKUP2_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP2_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W3_APB2OTP_BLOCK0_BACKUP2_W3_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP2_W4: eFuse apb2otp block0 data register10.
	// Position of APB2OTP_BLOCK0_BACKUP2_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W4_APB2OTP_BLOCK0_BACKUP2_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP2_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W4_APB2OTP_BLOCK0_BACKUP2_W4_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP2_W5: eFuse apb2otp block0 data register11.
	// Position of APB2OTP_BLOCK0_BACKUP2_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W5_APB2OTP_BLOCK0_BACKUP2_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP2_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP2_W5_APB2OTP_BLOCK0_BACKUP2_W5_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP3_W1: eFuse apb2otp block0 data register12.
	// Position of APB2OTP_BLOCK0_BACKUP3_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W1_APB2OTP_BLOCK0_BACKUP3_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP3_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W1_APB2OTP_BLOCK0_BACKUP3_W1_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP3_W2: eFuse apb2otp block0 data register13.
	// Position of APB2OTP_BLOCK0_BACKUP3_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W2_APB2OTP_BLOCK0_BACKUP3_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP3_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W2_APB2OTP_BLOCK0_BACKUP3_W2_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP3_W3: eFuse apb2otp block0 data register14.
	// Position of APB2OTP_BLOCK0_BACKUP3_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W3_APB2OTP_BLOCK0_BACKUP3_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP3_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W3_APB2OTP_BLOCK0_BACKUP3_W3_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP3_W4: eFuse apb2otp block0 data register15.
	// Position of APB2OTP_BLOCK0_BACKUP3_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W4_APB2OTP_BLOCK0_BACKUP3_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP3_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W4_APB2OTP_BLOCK0_BACKUP3_W4_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP3_W5: eFuse apb2otp block0 data register16.
	// Position of APB2OTP_BLOCK0_BACKUP3_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W5_APB2OTP_BLOCK0_BACKUP3_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP3_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP3_W5_APB2OTP_BLOCK0_BACKUP3_W5_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP4_W1: eFuse apb2otp block0 data register17.
	// Position of APB2OTP_BLOCK0_BACKUP4_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W1_APB2OTP_BLOCK0_BACKUP4_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP4_W1 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W1_APB2OTP_BLOCK0_BACKUP4_W1_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP4_W2: eFuse apb2otp block0 data register18.
	// Position of APB2OTP_BLOCK0_BACKUP4_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W2_APB2OTP_BLOCK0_BACKUP4_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP4_W2 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W2_APB2OTP_BLOCK0_BACKUP4_W2_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP4_W3: eFuse apb2otp block0 data register19.
	// Position of APB2OTP_BLOCK0_BACKUP4_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W3_APB2OTP_BLOCK0_BACKUP4_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP4_W3 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W3_APB2OTP_BLOCK0_BACKUP4_W3_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP4_W4: eFuse apb2otp block0 data register20.
	// Position of APB2OTP_BLOCK0_BACKUP4_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W4_APB2OTP_BLOCK0_BACKUP4_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP4_W4 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W4_APB2OTP_BLOCK0_BACKUP4_W4_Msk = 0xffffffff

	// APB2OTP_BLK0_BACKUP4_W5: eFuse apb2otp block0 data register21.
	// Position of APB2OTP_BLOCK0_BACKUP4_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W5_APB2OTP_BLOCK0_BACKUP4_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK0_BACKUP4_W5 field.
	EFUSE_APB2OTP_BLK0_BACKUP4_W5_APB2OTP_BLOCK0_BACKUP4_W5_Msk = 0xffffffff

	// APB2OTP_BLK1_W1: eFuse apb2otp block1 data register1.
	// Position of APB2OTP_BLOCK1_W1 field.
	EFUSE_APB2OTP_BLK1_W1_APB2OTP_BLOCK1_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W1 field.
	EFUSE_APB2OTP_BLK1_W1_APB2OTP_BLOCK1_W1_Msk = 0xffffffff

	// APB2OTP_BLK1_W2: eFuse apb2otp block1 data register2.
	// Position of APB2OTP_BLOCK1_W2 field.
	EFUSE_APB2OTP_BLK1_W2_APB2OTP_BLOCK1_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W2 field.
	EFUSE_APB2OTP_BLK1_W2_APB2OTP_BLOCK1_W2_Msk = 0xffffffff

	// APB2OTP_BLK1_W3: eFuse apb2otp block1 data register3.
	// Position of APB2OTP_BLOCK1_W3 field.
	EFUSE_APB2OTP_BLK1_W3_APB2OTP_BLOCK1_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W3 field.
	EFUSE_APB2OTP_BLK1_W3_APB2OTP_BLOCK1_W3_Msk = 0xffffffff

	// APB2OTP_BLK1_W4: eFuse apb2otp block1 data register4.
	// Position of APB2OTP_BLOCK1_W4 field.
	EFUSE_APB2OTP_BLK1_W4_APB2OTP_BLOCK1_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W4 field.
	EFUSE_APB2OTP_BLK1_W4_APB2OTP_BLOCK1_W4_Msk = 0xffffffff

	// APB2OTP_BLK1_W5: eFuse apb2otp block1 data register5.
	// Position of APB2OTP_BLOCK1_W5 field.
	EFUSE_APB2OTP_BLK1_W5_APB2OTP_BLOCK1_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W5 field.
	EFUSE_APB2OTP_BLK1_W5_APB2OTP_BLOCK1_W5_Msk = 0xffffffff

	// APB2OTP_BLK1_W6: eFuse apb2otp block1 data register6.
	// Position of APB2OTP_BLOCK1_W6 field.
	EFUSE_APB2OTP_BLK1_W6_APB2OTP_BLOCK1_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W6 field.
	EFUSE_APB2OTP_BLK1_W6_APB2OTP_BLOCK1_W6_Msk = 0xffffffff

	// APB2OTP_BLK1_W7: eFuse apb2otp block1 data register7.
	// Position of APB2OTP_BLOCK1_W7 field.
	EFUSE_APB2OTP_BLK1_W7_APB2OTP_BLOCK1_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W7 field.
	EFUSE_APB2OTP_BLK1_W7_APB2OTP_BLOCK1_W7_Msk = 0xffffffff

	// APB2OTP_BLK1_W8: eFuse apb2otp block1 data register8.
	// Position of APB2OTP_BLOCK1_W8 field.
	EFUSE_APB2OTP_BLK1_W8_APB2OTP_BLOCK1_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W8 field.
	EFUSE_APB2OTP_BLK1_W8_APB2OTP_BLOCK1_W8_Msk = 0xffffffff

	// APB2OTP_BLK1_W9: eFuse apb2otp block1 data register9.
	// Position of APB2OTP_BLOCK1_W9 field.
	EFUSE_APB2OTP_BLK1_W9_APB2OTP_BLOCK1_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK1_W9 field.
	EFUSE_APB2OTP_BLK1_W9_APB2OTP_BLOCK1_W9_Msk = 0xffffffff

	// APB2OTP_BLK2_W1: eFuse apb2otp block2 data register1.
	// Position of APB2OTP_BLOCK2_W1 field.
	EFUSE_APB2OTP_BLK2_W1_APB2OTP_BLOCK2_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W1 field.
	EFUSE_APB2OTP_BLK2_W1_APB2OTP_BLOCK2_W1_Msk = 0xffffffff

	// APB2OTP_BLK2_W2: eFuse apb2otp block2 data register2.
	// Position of APB2OTP_BLOCK2_W2 field.
	EFUSE_APB2OTP_BLK2_W2_APB2OTP_BLOCK2_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W2 field.
	EFUSE_APB2OTP_BLK2_W2_APB2OTP_BLOCK2_W2_Msk = 0xffffffff

	// APB2OTP_BLK2_W3: eFuse apb2otp block2 data register3.
	// Position of APB2OTP_BLOCK2_W3 field.
	EFUSE_APB2OTP_BLK2_W3_APB2OTP_BLOCK2_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W3 field.
	EFUSE_APB2OTP_BLK2_W3_APB2OTP_BLOCK2_W3_Msk = 0xffffffff

	// APB2OTP_BLK2_W4: eFuse apb2otp block2 data register4.
	// Position of APB2OTP_BLOCK2_W4 field.
	EFUSE_APB2OTP_BLK2_W4_APB2OTP_BLOCK2_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W4 field.
	EFUSE_APB2OTP_BLK2_W4_APB2OTP_BLOCK2_W4_Msk = 0xffffffff

	// APB2OTP_BLK2_W5: eFuse apb2otp block2 data register5.
	// Position of APB2OTP_BLOCK2_W5 field.
	EFUSE_APB2OTP_BLK2_W5_APB2OTP_BLOCK2_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W5 field.
	EFUSE_APB2OTP_BLK2_W5_APB2OTP_BLOCK2_W5_Msk = 0xffffffff

	// APB2OTP_BLK2_W6: eFuse apb2otp block2 data register6.
	// Position of APB2OTP_BLOCK2_W6 field.
	EFUSE_APB2OTP_BLK2_W6_APB2OTP_BLOCK2_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W6 field.
	EFUSE_APB2OTP_BLK2_W6_APB2OTP_BLOCK2_W6_Msk = 0xffffffff

	// APB2OTP_BLK2_W7: eFuse apb2otp block2 data register7.
	// Position of APB2OTP_BLOCK2_W7 field.
	EFUSE_APB2OTP_BLK2_W7_APB2OTP_BLOCK2_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W7 field.
	EFUSE_APB2OTP_BLK2_W7_APB2OTP_BLOCK2_W7_Msk = 0xffffffff

	// APB2OTP_BLK2_W8: eFuse apb2otp block2 data register8.
	// Position of APB2OTP_BLOCK2_W8 field.
	EFUSE_APB2OTP_BLK2_W8_APB2OTP_BLOCK2_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W8 field.
	EFUSE_APB2OTP_BLK2_W8_APB2OTP_BLOCK2_W8_Msk = 0xffffffff

	// APB2OTP_BLK2_W9: eFuse apb2otp block2 data register9.
	// Position of APB2OTP_BLOCK2_W9 field.
	EFUSE_APB2OTP_BLK2_W9_APB2OTP_BLOCK2_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W9 field.
	EFUSE_APB2OTP_BLK2_W9_APB2OTP_BLOCK2_W9_Msk = 0xffffffff

	// APB2OTP_BLK2_W10: eFuse apb2otp block2 data register10.
	// Position of APB2OTP_BLOCK2_W10 field.
	EFUSE_APB2OTP_BLK2_W10_APB2OTP_BLOCK2_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W10 field.
	EFUSE_APB2OTP_BLK2_W10_APB2OTP_BLOCK2_W10_Msk = 0xffffffff

	// APB2OTP_BLK2_W11: eFuse apb2otp block2 data register11.
	// Position of APB2OTP_BLOCK2_W11 field.
	EFUSE_APB2OTP_BLK2_W11_APB2OTP_BLOCK2_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK2_W11 field.
	EFUSE_APB2OTP_BLK2_W11_APB2OTP_BLOCK2_W11_Msk = 0xffffffff

	// APB2OTP_BLK3_W1: eFuse apb2otp block3 data register1.
	// Position of APB2OTP_BLOCK3_W1 field.
	EFUSE_APB2OTP_BLK3_W1_APB2OTP_BLOCK3_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W1 field.
	EFUSE_APB2OTP_BLK3_W1_APB2OTP_BLOCK3_W1_Msk = 0xffffffff

	// APB2OTP_BLK3_W2: eFuse apb2otp block3 data register2.
	// Position of APB2OTP_BLOCK3_W2 field.
	EFUSE_APB2OTP_BLK3_W2_APB2OTP_BLOCK3_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W2 field.
	EFUSE_APB2OTP_BLK3_W2_APB2OTP_BLOCK3_W2_Msk = 0xffffffff

	// APB2OTP_BLK3_W3: eFuse apb2otp block3 data register3.
	// Position of APB2OTP_BLOCK3_W3 field.
	EFUSE_APB2OTP_BLK3_W3_APB2OTP_BLOCK3_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W3 field.
	EFUSE_APB2OTP_BLK3_W3_APB2OTP_BLOCK3_W3_Msk = 0xffffffff

	// APB2OTP_BLK3_W4: eFuse apb2otp block3 data register4.
	// Position of APB2OTP_BLOCK3_W4 field.
	EFUSE_APB2OTP_BLK3_W4_APB2OTP_BLOCK3_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W4 field.
	EFUSE_APB2OTP_BLK3_W4_APB2OTP_BLOCK3_W4_Msk = 0xffffffff

	// APB2OTP_BLK3_W5: eFuse apb2otp block3 data register5.
	// Position of APB2OTP_BLOCK3_W5 field.
	EFUSE_APB2OTP_BLK3_W5_APB2OTP_BLOCK3_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W5 field.
	EFUSE_APB2OTP_BLK3_W5_APB2OTP_BLOCK3_W5_Msk = 0xffffffff

	// APB2OTP_BLK3_W6: eFuse apb2otp block3 data register6.
	// Position of APB2OTP_BLOCK3_W6 field.
	EFUSE_APB2OTP_BLK3_W6_APB2OTP_BLOCK3_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W6 field.
	EFUSE_APB2OTP_BLK3_W6_APB2OTP_BLOCK3_W6_Msk = 0xffffffff

	// APB2OTP_BLK3_W7: eFuse apb2otp block3 data register7.
	// Position of APB2OTP_BLOCK3_W7 field.
	EFUSE_APB2OTP_BLK3_W7_APB2OTP_BLOCK3_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W7 field.
	EFUSE_APB2OTP_BLK3_W7_APB2OTP_BLOCK3_W7_Msk = 0xffffffff

	// APB2OTP_BLK3_W8: eFuse apb2otp block3 data register8.
	// Position of APB2OTP_BLOCK3_W8 field.
	EFUSE_APB2OTP_BLK3_W8_APB2OTP_BLOCK3_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W8 field.
	EFUSE_APB2OTP_BLK3_W8_APB2OTP_BLOCK3_W8_Msk = 0xffffffff

	// APB2OTP_BLK3_W9: eFuse apb2otp block3 data register9.
	// Position of APB2OTP_BLOCK3_W9 field.
	EFUSE_APB2OTP_BLK3_W9_APB2OTP_BLOCK3_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W9 field.
	EFUSE_APB2OTP_BLK3_W9_APB2OTP_BLOCK3_W9_Msk = 0xffffffff

	// APB2OTP_BLK3_W10: eFuse apb2otp block3 data register10.
	// Position of APB2OTP_BLOCK3_W10 field.
	EFUSE_APB2OTP_BLK3_W10_APB2OTP_BLOCK3_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W10 field.
	EFUSE_APB2OTP_BLK3_W10_APB2OTP_BLOCK3_W10_Msk = 0xffffffff

	// APB2OTP_BLK3_W11: eFuse apb2otp block3 data register11.
	// Position of APB2OTP_BLOCK3_W11 field.
	EFUSE_APB2OTP_BLK3_W11_APB2OTP_BLOCK3_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK3_W11 field.
	EFUSE_APB2OTP_BLK3_W11_APB2OTP_BLOCK3_W11_Msk = 0xffffffff

	// APB2OTP_BLK4_W1: eFuse apb2otp block4 data register1.
	// Position of APB2OTP_BLOCK4_W1 field.
	EFUSE_APB2OTP_BLK4_W1_APB2OTP_BLOCK4_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W1 field.
	EFUSE_APB2OTP_BLK4_W1_APB2OTP_BLOCK4_W1_Msk = 0xffffffff

	// APB2OTP_BLK4_W2: eFuse apb2otp block4 data register2.
	// Position of APB2OTP_BLOCK4_W2 field.
	EFUSE_APB2OTP_BLK4_W2_APB2OTP_BLOCK4_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W2 field.
	EFUSE_APB2OTP_BLK4_W2_APB2OTP_BLOCK4_W2_Msk = 0xffffffff

	// APB2OTP_BLK4_W3: eFuse apb2otp block4 data register3.
	// Position of APB2OTP_BLOCK4_W3 field.
	EFUSE_APB2OTP_BLK4_W3_APB2OTP_BLOCK4_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W3 field.
	EFUSE_APB2OTP_BLK4_W3_APB2OTP_BLOCK4_W3_Msk = 0xffffffff

	// APB2OTP_BLK4_W4: eFuse apb2otp block4 data register4.
	// Position of APB2OTP_BLOCK4_W4 field.
	EFUSE_APB2OTP_BLK4_W4_APB2OTP_BLOCK4_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W4 field.
	EFUSE_APB2OTP_BLK4_W4_APB2OTP_BLOCK4_W4_Msk = 0xffffffff

	// APB2OTP_BLK4_W5: eFuse apb2otp block4 data register5.
	// Position of APB2OTP_BLOCK4_W5 field.
	EFUSE_APB2OTP_BLK4_W5_APB2OTP_BLOCK4_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W5 field.
	EFUSE_APB2OTP_BLK4_W5_APB2OTP_BLOCK4_W5_Msk = 0xffffffff

	// APB2OTP_BLK4_W6: eFuse apb2otp block4 data register6.
	// Position of APB2OTP_BLOCK4_W6 field.
	EFUSE_APB2OTP_BLK4_W6_APB2OTP_BLOCK4_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W6 field.
	EFUSE_APB2OTP_BLK4_W6_APB2OTP_BLOCK4_W6_Msk = 0xffffffff

	// APB2OTP_BLK4_W7: eFuse apb2otp block4 data register7.
	// Position of APB2OTP_BLOCK4_W7 field.
	EFUSE_APB2OTP_BLK4_W7_APB2OTP_BLOCK4_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W7 field.
	EFUSE_APB2OTP_BLK4_W7_APB2OTP_BLOCK4_W7_Msk = 0xffffffff

	// APB2OTP_BLK4_W8: eFuse apb2otp block4 data register8.
	// Position of APB2OTP_BLOCK4_W8 field.
	EFUSE_APB2OTP_BLK4_W8_APB2OTP_BLOCK4_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W8 field.
	EFUSE_APB2OTP_BLK4_W8_APB2OTP_BLOCK4_W8_Msk = 0xffffffff

	// APB2OTP_BLK4_W9: eFuse apb2otp block4 data register9.
	// Position of APB2OTP_BLOCK4_W9 field.
	EFUSE_APB2OTP_BLK4_W9_APB2OTP_BLOCK4_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W9 field.
	EFUSE_APB2OTP_BLK4_W9_APB2OTP_BLOCK4_W9_Msk = 0xffffffff

	// APB2OTP_BLK4_W10: eFuse apb2otp block4 data registe10.
	// Position of APB2OTP_BLOCK4_W10 field.
	EFUSE_APB2OTP_BLK4_W10_APB2OTP_BLOCK4_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W10 field.
	EFUSE_APB2OTP_BLK4_W10_APB2OTP_BLOCK4_W10_Msk = 0xffffffff

	// APB2OTP_BLK4_W11: eFuse apb2otp block4 data register11.
	// Position of APB2OTP_BLOCK4_W11 field.
	EFUSE_APB2OTP_BLK4_W11_APB2OTP_BLOCK4_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK4_W11 field.
	EFUSE_APB2OTP_BLK4_W11_APB2OTP_BLOCK4_W11_Msk = 0xffffffff

	// APB2OTP_BLK5_W1: eFuse apb2otp block5 data register1.
	// Position of APB2OTP_BLOCK5_W1 field.
	EFUSE_APB2OTP_BLK5_W1_APB2OTP_BLOCK5_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W1 field.
	EFUSE_APB2OTP_BLK5_W1_APB2OTP_BLOCK5_W1_Msk = 0xffffffff

	// APB2OTP_BLK5_W2: eFuse apb2otp block5 data register2.
	// Position of APB2OTP_BLOCK5_W2 field.
	EFUSE_APB2OTP_BLK5_W2_APB2OTP_BLOCK5_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W2 field.
	EFUSE_APB2OTP_BLK5_W2_APB2OTP_BLOCK5_W2_Msk = 0xffffffff

	// APB2OTP_BLK5_W3: eFuse apb2otp block5 data register3.
	// Position of APB2OTP_BLOCK5_W3 field.
	EFUSE_APB2OTP_BLK5_W3_APB2OTP_BLOCK5_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W3 field.
	EFUSE_APB2OTP_BLK5_W3_APB2OTP_BLOCK5_W3_Msk = 0xffffffff

	// APB2OTP_BLK5_W4: eFuse apb2otp block5 data register4.
	// Position of APB2OTP_BLOCK5_W4 field.
	EFUSE_APB2OTP_BLK5_W4_APB2OTP_BLOCK5_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W4 field.
	EFUSE_APB2OTP_BLK5_W4_APB2OTP_BLOCK5_W4_Msk = 0xffffffff

	// APB2OTP_BLK5_W5: eFuse apb2otp block5 data register5.
	// Position of APB2OTP_BLOCK5_W5 field.
	EFUSE_APB2OTP_BLK5_W5_APB2OTP_BLOCK5_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W5 field.
	EFUSE_APB2OTP_BLK5_W5_APB2OTP_BLOCK5_W5_Msk = 0xffffffff

	// APB2OTP_BLK5_W6: eFuse apb2otp block5 data register6.
	// Position of APB2OTP_BLOCK5_W6 field.
	EFUSE_APB2OTP_BLK5_W6_APB2OTP_BLOCK5_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W6 field.
	EFUSE_APB2OTP_BLK5_W6_APB2OTP_BLOCK5_W6_Msk = 0xffffffff

	// APB2OTP_BLK5_W7: eFuse apb2otp block5 data register7.
	// Position of APB2OTP_BLOCK5_W7 field.
	EFUSE_APB2OTP_BLK5_W7_APB2OTP_BLOCK5_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W7 field.
	EFUSE_APB2OTP_BLK5_W7_APB2OTP_BLOCK5_W7_Msk = 0xffffffff

	// APB2OTP_BLK5_W8: eFuse apb2otp block5 data register8.
	// Position of APB2OTP_BLOCK5_W8 field.
	EFUSE_APB2OTP_BLK5_W8_APB2OTP_BLOCK5_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W8 field.
	EFUSE_APB2OTP_BLK5_W8_APB2OTP_BLOCK5_W8_Msk = 0xffffffff

	// APB2OTP_BLK5_W9: eFuse apb2otp block5 data register9.
	// Position of APB2OTP_BLOCK5_W9 field.
	EFUSE_APB2OTP_BLK5_W9_APB2OTP_BLOCK5_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W9 field.
	EFUSE_APB2OTP_BLK5_W9_APB2OTP_BLOCK5_W9_Msk = 0xffffffff

	// APB2OTP_BLK5_W10: eFuse apb2otp block5 data register10.
	// Position of APB2OTP_BLOCK5_W10 field.
	EFUSE_APB2OTP_BLK5_W10_APB2OTP_BLOCK5_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W10 field.
	EFUSE_APB2OTP_BLK5_W10_APB2OTP_BLOCK5_W10_Msk = 0xffffffff

	// APB2OTP_BLK5_W11: eFuse apb2otp block5 data register11.
	// Position of APB2OTP_BLOCK5_W11 field.
	EFUSE_APB2OTP_BLK5_W11_APB2OTP_BLOCK5_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK5_W11 field.
	EFUSE_APB2OTP_BLK5_W11_APB2OTP_BLOCK5_W11_Msk = 0xffffffff

	// APB2OTP_BLK6_W1: eFuse apb2otp block6 data register1.
	// Position of APB2OTP_BLOCK6_W1 field.
	EFUSE_APB2OTP_BLK6_W1_APB2OTP_BLOCK6_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W1 field.
	EFUSE_APB2OTP_BLK6_W1_APB2OTP_BLOCK6_W1_Msk = 0xffffffff

	// APB2OTP_BLK6_W2: eFuse apb2otp block6 data register2.
	// Position of APB2OTP_BLOCK6_W2 field.
	EFUSE_APB2OTP_BLK6_W2_APB2OTP_BLOCK6_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W2 field.
	EFUSE_APB2OTP_BLK6_W2_APB2OTP_BLOCK6_W2_Msk = 0xffffffff

	// APB2OTP_BLK6_W3: eFuse apb2otp block6 data register3.
	// Position of APB2OTP_BLOCK6_W3 field.
	EFUSE_APB2OTP_BLK6_W3_APB2OTP_BLOCK6_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W3 field.
	EFUSE_APB2OTP_BLK6_W3_APB2OTP_BLOCK6_W3_Msk = 0xffffffff

	// APB2OTP_BLK6_W4: eFuse apb2otp block6 data register4.
	// Position of APB2OTP_BLOCK6_W4 field.
	EFUSE_APB2OTP_BLK6_W4_APB2OTP_BLOCK6_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W4 field.
	EFUSE_APB2OTP_BLK6_W4_APB2OTP_BLOCK6_W4_Msk = 0xffffffff

	// APB2OTP_BLK6_W5: eFuse apb2otp block6 data register5.
	// Position of APB2OTP_BLOCK6_W5 field.
	EFUSE_APB2OTP_BLK6_W5_APB2OTP_BLOCK6_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W5 field.
	EFUSE_APB2OTP_BLK6_W5_APB2OTP_BLOCK6_W5_Msk = 0xffffffff

	// APB2OTP_BLK6_W6: eFuse apb2otp block6 data register6.
	// Position of APB2OTP_BLOCK6_W6 field.
	EFUSE_APB2OTP_BLK6_W6_APB2OTP_BLOCK6_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W6 field.
	EFUSE_APB2OTP_BLK6_W6_APB2OTP_BLOCK6_W6_Msk = 0xffffffff

	// APB2OTP_BLK6_W7: eFuse apb2otp block6 data register7.
	// Position of APB2OTP_BLOCK6_W7 field.
	EFUSE_APB2OTP_BLK6_W7_APB2OTP_BLOCK6_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W7 field.
	EFUSE_APB2OTP_BLK6_W7_APB2OTP_BLOCK6_W7_Msk = 0xffffffff

	// APB2OTP_BLK6_W8: eFuse apb2otp block6 data register8.
	// Position of APB2OTP_BLOCK6_W8 field.
	EFUSE_APB2OTP_BLK6_W8_APB2OTP_BLOCK6_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W8 field.
	EFUSE_APB2OTP_BLK6_W8_APB2OTP_BLOCK6_W8_Msk = 0xffffffff

	// APB2OTP_BLK6_W9: eFuse apb2otp block6 data register9.
	// Position of APB2OTP_BLOCK6_W9 field.
	EFUSE_APB2OTP_BLK6_W9_APB2OTP_BLOCK6_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W9 field.
	EFUSE_APB2OTP_BLK6_W9_APB2OTP_BLOCK6_W9_Msk = 0xffffffff

	// APB2OTP_BLK6_W10: eFuse apb2otp block6 data register10.
	// Position of APB2OTP_BLOCK6_W10 field.
	EFUSE_APB2OTP_BLK6_W10_APB2OTP_BLOCK6_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W10 field.
	EFUSE_APB2OTP_BLK6_W10_APB2OTP_BLOCK6_W10_Msk = 0xffffffff

	// APB2OTP_BLK6_W11: eFuse apb2otp block6 data register11.
	// Position of APB2OTP_BLOCK6_W11 field.
	EFUSE_APB2OTP_BLK6_W11_APB2OTP_BLOCK6_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK6_W11 field.
	EFUSE_APB2OTP_BLK6_W11_APB2OTP_BLOCK6_W11_Msk = 0xffffffff

	// APB2OTP_BLK7_W1: eFuse apb2otp block7 data register1.
	// Position of APB2OTP_BLOCK7_W1 field.
	EFUSE_APB2OTP_BLK7_W1_APB2OTP_BLOCK7_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W1 field.
	EFUSE_APB2OTP_BLK7_W1_APB2OTP_BLOCK7_W1_Msk = 0xffffffff

	// APB2OTP_BLK7_W2: eFuse apb2otp block7 data register2.
	// Position of APB2OTP_BLOCK7_W2 field.
	EFUSE_APB2OTP_BLK7_W2_APB2OTP_BLOCK7_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W2 field.
	EFUSE_APB2OTP_BLK7_W2_APB2OTP_BLOCK7_W2_Msk = 0xffffffff

	// APB2OTP_BLK7_W3: eFuse apb2otp block7 data register3.
	// Position of APB2OTP_BLOCK7_W3 field.
	EFUSE_APB2OTP_BLK7_W3_APB2OTP_BLOCK7_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W3 field.
	EFUSE_APB2OTP_BLK7_W3_APB2OTP_BLOCK7_W3_Msk = 0xffffffff

	// APB2OTP_BLK7_W4: eFuse apb2otp block7 data register4.
	// Position of APB2OTP_BLOCK7_W4 field.
	EFUSE_APB2OTP_BLK7_W4_APB2OTP_BLOCK7_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W4 field.
	EFUSE_APB2OTP_BLK7_W4_APB2OTP_BLOCK7_W4_Msk = 0xffffffff

	// APB2OTP_BLK7_W5: eFuse apb2otp block7 data register5.
	// Position of APB2OTP_BLOCK7_W5 field.
	EFUSE_APB2OTP_BLK7_W5_APB2OTP_BLOCK7_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W5 field.
	EFUSE_APB2OTP_BLK7_W5_APB2OTP_BLOCK7_W5_Msk = 0xffffffff

	// APB2OTP_BLK7_W6: eFuse apb2otp block7 data register6.
	// Position of APB2OTP_BLOCK7_W6 field.
	EFUSE_APB2OTP_BLK7_W6_APB2OTP_BLOCK7_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W6 field.
	EFUSE_APB2OTP_BLK7_W6_APB2OTP_BLOCK7_W6_Msk = 0xffffffff

	// APB2OTP_BLK7_W7: eFuse apb2otp block7 data register7.
	// Position of APB2OTP_BLOCK7_W7 field.
	EFUSE_APB2OTP_BLK7_W7_APB2OTP_BLOCK7_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W7 field.
	EFUSE_APB2OTP_BLK7_W7_APB2OTP_BLOCK7_W7_Msk = 0xffffffff

	// APB2OTP_BLK7_W8: eFuse apb2otp block7 data register8.
	// Position of APB2OTP_BLOCK7_W8 field.
	EFUSE_APB2OTP_BLK7_W8_APB2OTP_BLOCK7_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W8 field.
	EFUSE_APB2OTP_BLK7_W8_APB2OTP_BLOCK7_W8_Msk = 0xffffffff

	// APB2OTP_BLK7_W9: eFuse apb2otp block7 data register9.
	// Position of APB2OTP_BLOCK7_W9 field.
	EFUSE_APB2OTP_BLK7_W9_APB2OTP_BLOCK7_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W9 field.
	EFUSE_APB2OTP_BLK7_W9_APB2OTP_BLOCK7_W9_Msk = 0xffffffff

	// APB2OTP_BLK7_W10: eFuse apb2otp block7 data register10.
	// Position of APB2OTP_BLOCK7_W10 field.
	EFUSE_APB2OTP_BLK7_W10_APB2OTP_BLOCK7_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W10 field.
	EFUSE_APB2OTP_BLK7_W10_APB2OTP_BLOCK7_W10_Msk = 0xffffffff

	// APB2OTP_BLK7_W11: eFuse apb2otp block7 data register11.
	// Position of APB2OTP_BLOCK7_W11 field.
	EFUSE_APB2OTP_BLK7_W11_APB2OTP_BLOCK7_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK7_W11 field.
	EFUSE_APB2OTP_BLK7_W11_APB2OTP_BLOCK7_W11_Msk = 0xffffffff

	// APB2OTP_BLK8_W1: eFuse apb2otp block8 data register1.
	// Position of APB2OTP_BLOCK8_W1 field.
	EFUSE_APB2OTP_BLK8_W1_APB2OTP_BLOCK8_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W1 field.
	EFUSE_APB2OTP_BLK8_W1_APB2OTP_BLOCK8_W1_Msk = 0xffffffff

	// APB2OTP_BLK8_W2: eFuse apb2otp block8 data register2.
	// Position of APB2OTP_BLOCK8_W2 field.
	EFUSE_APB2OTP_BLK8_W2_APB2OTP_BLOCK8_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W2 field.
	EFUSE_APB2OTP_BLK8_W2_APB2OTP_BLOCK8_W2_Msk = 0xffffffff

	// APB2OTP_BLK8_W3: eFuse apb2otp block8 data register3.
	// Position of APB2OTP_BLOCK8_W3 field.
	EFUSE_APB2OTP_BLK8_W3_APB2OTP_BLOCK8_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W3 field.
	EFUSE_APB2OTP_BLK8_W3_APB2OTP_BLOCK8_W3_Msk = 0xffffffff

	// APB2OTP_BLK8_W4: eFuse apb2otp block8 data register4.
	// Position of APB2OTP_BLOCK8_W4 field.
	EFUSE_APB2OTP_BLK8_W4_APB2OTP_BLOCK8_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W4 field.
	EFUSE_APB2OTP_BLK8_W4_APB2OTP_BLOCK8_W4_Msk = 0xffffffff

	// APB2OTP_BLK8_W5: eFuse apb2otp block8 data register5.
	// Position of APB2OTP_BLOCK8_W5 field.
	EFUSE_APB2OTP_BLK8_W5_APB2OTP_BLOCK8_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W5 field.
	EFUSE_APB2OTP_BLK8_W5_APB2OTP_BLOCK8_W5_Msk = 0xffffffff

	// APB2OTP_BLK8_W6: eFuse apb2otp block8 data register6.
	// Position of APB2OTP_BLOCK8_W6 field.
	EFUSE_APB2OTP_BLK8_W6_APB2OTP_BLOCK8_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W6 field.
	EFUSE_APB2OTP_BLK8_W6_APB2OTP_BLOCK8_W6_Msk = 0xffffffff

	// APB2OTP_BLK8_W7: eFuse apb2otp block8 data register7.
	// Position of APB2OTP_BLOCK8_W7 field.
	EFUSE_APB2OTP_BLK8_W7_APB2OTP_BLOCK8_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W7 field.
	EFUSE_APB2OTP_BLK8_W7_APB2OTP_BLOCK8_W7_Msk = 0xffffffff

	// APB2OTP_BLK8_W8: eFuse apb2otp block8 data register8.
	// Position of APB2OTP_BLOCK8_W8 field.
	EFUSE_APB2OTP_BLK8_W8_APB2OTP_BLOCK8_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W8 field.
	EFUSE_APB2OTP_BLK8_W8_APB2OTP_BLOCK8_W8_Msk = 0xffffffff

	// APB2OTP_BLK8_W9: eFuse apb2otp block8 data register9.
	// Position of APB2OTP_BLOCK8_W9 field.
	EFUSE_APB2OTP_BLK8_W9_APB2OTP_BLOCK8_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W9 field.
	EFUSE_APB2OTP_BLK8_W9_APB2OTP_BLOCK8_W9_Msk = 0xffffffff

	// APB2OTP_BLK8_W10: eFuse apb2otp block8 data register10.
	// Position of APB2OTP_BLOCK8_W10 field.
	EFUSE_APB2OTP_BLK8_W10_APB2OTP_BLOCK8_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W10 field.
	EFUSE_APB2OTP_BLK8_W10_APB2OTP_BLOCK8_W10_Msk = 0xffffffff

	// APB2OTP_BLK8_W11: eFuse apb2otp block8 data register11.
	// Position of APB2OTP_BLOCK8_W11 field.
	EFUSE_APB2OTP_BLK8_W11_APB2OTP_BLOCK8_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK8_W11 field.
	EFUSE_APB2OTP_BLK8_W11_APB2OTP_BLOCK8_W11_Msk = 0xffffffff

	// APB2OTP_BLK9_W1: eFuse apb2otp block9 data register1.
	// Position of APB2OTP_BLOCK9_W1 field.
	EFUSE_APB2OTP_BLK9_W1_APB2OTP_BLOCK9_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W1 field.
	EFUSE_APB2OTP_BLK9_W1_APB2OTP_BLOCK9_W1_Msk = 0xffffffff

	// APB2OTP_BLK9_W2: eFuse apb2otp block9 data register2.
	// Position of APB2OTP_BLOCK9_W2 field.
	EFUSE_APB2OTP_BLK9_W2_APB2OTP_BLOCK9_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W2 field.
	EFUSE_APB2OTP_BLK9_W2_APB2OTP_BLOCK9_W2_Msk = 0xffffffff

	// APB2OTP_BLK9_W3: eFuse apb2otp block9 data register3.
	// Position of APB2OTP_BLOCK9_W3 field.
	EFUSE_APB2OTP_BLK9_W3_APB2OTP_BLOCK9_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W3 field.
	EFUSE_APB2OTP_BLK9_W3_APB2OTP_BLOCK9_W3_Msk = 0xffffffff

	// APB2OTP_BLK9_W4: eFuse apb2otp block9 data register4.
	// Position of APB2OTP_BLOCK9_W4 field.
	EFUSE_APB2OTP_BLK9_W4_APB2OTP_BLOCK9_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W4 field.
	EFUSE_APB2OTP_BLK9_W4_APB2OTP_BLOCK9_W4_Msk = 0xffffffff

	// APB2OTP_BLK9_W5: eFuse apb2otp block9 data register5.
	// Position of APB2OTP_BLOCK9_W5 field.
	EFUSE_APB2OTP_BLK9_W5_APB2OTP_BLOCK9_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W5 field.
	EFUSE_APB2OTP_BLK9_W5_APB2OTP_BLOCK9_W5_Msk = 0xffffffff

	// APB2OTP_BLK9_W6: eFuse apb2otp block9 data register6.
	// Position of APB2OTP_BLOCK9_W6 field.
	EFUSE_APB2OTP_BLK9_W6_APB2OTP_BLOCK9_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W6 field.
	EFUSE_APB2OTP_BLK9_W6_APB2OTP_BLOCK9_W6_Msk = 0xffffffff

	// APB2OTP_BLK9_W7: eFuse apb2otp block9 data register7.
	// Position of APB2OTP_BLOCK9_W7 field.
	EFUSE_APB2OTP_BLK9_W7_APB2OTP_BLOCK9_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W7 field.
	EFUSE_APB2OTP_BLK9_W7_APB2OTP_BLOCK9_W7_Msk = 0xffffffff

	// APB2OTP_BLK9_W8: eFuse apb2otp block9 data register8.
	// Position of APB2OTP_BLOCK9_W8 field.
	EFUSE_APB2OTP_BLK9_W8_APB2OTP_BLOCK9_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W8 field.
	EFUSE_APB2OTP_BLK9_W8_APB2OTP_BLOCK9_W8_Msk = 0xffffffff

	// APB2OTP_BLK9_W9: eFuse apb2otp block9 data register9.
	// Position of APB2OTP_BLOCK9_W9 field.
	EFUSE_APB2OTP_BLK9_W9_APB2OTP_BLOCK9_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W9 field.
	EFUSE_APB2OTP_BLK9_W9_APB2OTP_BLOCK9_W9_Msk = 0xffffffff

	// APB2OTP_BLK9_W10: eFuse apb2otp block9 data register10.
	// Position of APB2OTP_BLOCK9_W10 field.
	EFUSE_APB2OTP_BLK9_W10_APB2OTP_BLOCK9_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W10 field.
	EFUSE_APB2OTP_BLK9_W10_APB2OTP_BLOCK9_W10_Msk = 0xffffffff

	// APB2OTP_BLK9_W11: eFuse apb2otp block9 data register11.
	// Position of APB2OTP_BLOCK9_W11 field.
	EFUSE_APB2OTP_BLK9_W11_APB2OTP_BLOCK9_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK9_W11 field.
	EFUSE_APB2OTP_BLK9_W11_APB2OTP_BLOCK9_W11_Msk = 0xffffffff

	// APB2OTP_BLK10_W1: eFuse apb2otp block10 data register1.
	// Position of APB2OTP_BLOCK10_W1 field.
	EFUSE_APB2OTP_BLK10_W1_APB2OTP_BLOCK10_W1_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W1 field.
	EFUSE_APB2OTP_BLK10_W1_APB2OTP_BLOCK10_W1_Msk = 0xffffffff

	// APB2OTP_BLK10_W2: eFuse apb2otp block10 data register2.
	// Position of APB2OTP_BLOCK10_W2 field.
	EFUSE_APB2OTP_BLK10_W2_APB2OTP_BLOCK10_W2_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W2 field.
	EFUSE_APB2OTP_BLK10_W2_APB2OTP_BLOCK10_W2_Msk = 0xffffffff

	// APB2OTP_BLK10_W3: eFuse apb2otp block10 data register3.
	// Position of APB2OTP_BLOCK10_W3 field.
	EFUSE_APB2OTP_BLK10_W3_APB2OTP_BLOCK10_W3_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W3 field.
	EFUSE_APB2OTP_BLK10_W3_APB2OTP_BLOCK10_W3_Msk = 0xffffffff

	// APB2OTP_BLK10_W4: eFuse apb2otp block10 data register4.
	// Position of APB2OTP_BLOCK10_W4 field.
	EFUSE_APB2OTP_BLK10_W4_APB2OTP_BLOCK10_W4_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W4 field.
	EFUSE_APB2OTP_BLK10_W4_APB2OTP_BLOCK10_W4_Msk = 0xffffffff

	// APB2OTP_BLK10_W5: eFuse apb2otp block10 data register5.
	// Position of APB2OTP_BLOCK10_W5 field.
	EFUSE_APB2OTP_BLK10_W5_APB2OTP_BLOCK10_W5_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W5 field.
	EFUSE_APB2OTP_BLK10_W5_APB2OTP_BLOCK10_W5_Msk = 0xffffffff

	// APB2OTP_BLK10_W6: eFuse apb2otp block10 data register6.
	// Position of APB2OTP_BLOCK10_W6 field.
	EFUSE_APB2OTP_BLK10_W6_APB2OTP_BLOCK10_W6_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W6 field.
	EFUSE_APB2OTP_BLK10_W6_APB2OTP_BLOCK10_W6_Msk = 0xffffffff

	// APB2OTP_BLK10_W7: eFuse apb2otp block10 data register7.
	// Position of APB2OTP_BLOCK10_W7 field.
	EFUSE_APB2OTP_BLK10_W7_APB2OTP_BLOCK10_W7_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W7 field.
	EFUSE_APB2OTP_BLK10_W7_APB2OTP_BLOCK10_W7_Msk = 0xffffffff

	// APB2OTP_BLK10_W8: eFuse apb2otp block10 data register8.
	// Position of APB2OTP_BLOCK10_W8 field.
	EFUSE_APB2OTP_BLK10_W8_APB2OTP_BLOCK10_W8_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W8 field.
	EFUSE_APB2OTP_BLK10_W8_APB2OTP_BLOCK10_W8_Msk = 0xffffffff

	// APB2OTP_BLK10_W9: eFuse apb2otp block10 data register9.
	// Position of APB2OTP_BLOCK10_W9 field.
	EFUSE_APB2OTP_BLK10_W9_APB2OTP_BLOCK10_W9_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W9 field.
	EFUSE_APB2OTP_BLK10_W9_APB2OTP_BLOCK10_W9_Msk = 0xffffffff

	// APB2OTP_BLK10_W10: eFuse apb2otp block10 data register10.
	// Position of APB2OTP_BLOCK19_W10 field.
	EFUSE_APB2OTP_BLK10_W10_APB2OTP_BLOCK19_W10_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK19_W10 field.
	EFUSE_APB2OTP_BLK10_W10_APB2OTP_BLOCK19_W10_Msk = 0xffffffff

	// APB2OTP_BLK10_W11: eFuse apb2otp block10 data register11.
	// Position of APB2OTP_BLOCK10_W11 field.
	EFUSE_APB2OTP_BLK10_W11_APB2OTP_BLOCK10_W11_Pos = 0x0
	// Bit mask of APB2OTP_BLOCK10_W11 field.
	EFUSE_APB2OTP_BLK10_W11_APB2OTP_BLOCK10_W11_Msk = 0xffffffff

	// APB2OTP_EN: eFuse apb2otp enable configuration register.
	// Position of APB2OTP_APB2OTP_EN field.
	EFUSE_APB2OTP_EN_APB2OTP_APB2OTP_EN_Pos = 0x0
	// Bit mask of APB2OTP_APB2OTP_EN field.
	EFUSE_APB2OTP_EN_APB2OTP_APB2OTP_EN_Msk = 0x1
	// Bit APB2OTP_APB2OTP_EN.
	EFUSE_APB2OTP_EN_APB2OTP_APB2OTP_EN = 0x1
)

// Constants for GPIO: General Purpose Input/Output
const (
	// BT_SELECT: GPIO bit select register
	// Position of BT_SEL field.
	GPIO_BT_SELECT_BT_SEL_Pos = 0x0
	// Bit mask of BT_SEL field.
	GPIO_BT_SELECT_BT_SEL_Msk = 0xffffffff

	// OUT: GPIO output register for GPIO0-31
	// Position of DATA_ORIG field.
	GPIO_OUT_DATA_ORIG_Pos = 0x0
	// Bit mask of DATA_ORIG field.
	GPIO_OUT_DATA_ORIG_Msk = 0xffffffff

	// OUT_W1TS: GPIO output set register for GPIO0-31
	// Position of OUT_W1TS field.
	GPIO_OUT_W1TS_OUT_W1TS_Pos = 0x0
	// Bit mask of OUT_W1TS field.
	GPIO_OUT_W1TS_OUT_W1TS_Msk = 0xffffffff

	// OUT_W1TC: GPIO output clear register for GPIO0-31
	// Position of OUT_W1TC field.
	GPIO_OUT_W1TC_OUT_W1TC_Pos = 0x0
	// Bit mask of OUT_W1TC field.
	GPIO_OUT_W1TC_OUT_W1TC_Msk = 0xffffffff

	// OUT1: GPIO output register for GPIO32-56
	// Position of DATA_ORIG field.
	GPIO_OUT1_DATA_ORIG_Pos = 0x0
	// Bit mask of DATA_ORIG field.
	GPIO_OUT1_DATA_ORIG_Msk = 0x1ffffff

	// OUT1_W1TS: GPIO output set register for GPIO32-56
	// Position of OUT1_W1TS field.
	GPIO_OUT1_W1TS_OUT1_W1TS_Pos = 0x0
	// Bit mask of OUT1_W1TS field.
	GPIO_OUT1_W1TS_OUT1_W1TS_Msk = 0x1ffffff

	// OUT1_W1TC: GPIO output clear register for GPIO32-56
	// Position of OUT1_W1TC field.
	GPIO_OUT1_W1TC_OUT1_W1TC_Pos = 0x0
	// Bit mask of OUT1_W1TC field.
	GPIO_OUT1_W1TC_OUT1_W1TC_Msk = 0x1ffffff

	// ENABLE: GPIO output enable register for GPIO0-31
	// Position of DATA field.
	GPIO_ENABLE_DATA_Pos = 0x0
	// Bit mask of DATA field.
	GPIO_ENABLE_DATA_Msk = 0xffffffff

	// ENABLE_W1TS: GPIO output enable set register for GPIO0-31
	// Position of ENABLE_W1TS field.
	GPIO_ENABLE_W1TS_ENABLE_W1TS_Pos = 0x0
	// Bit mask of ENABLE_W1TS field.
	GPIO_ENABLE_W1TS_ENABLE_W1TS_Msk = 0xffffffff

	// ENABLE_W1TC: GPIO output enable clear register for GPIO0-31
	// Position of ENABLE_W1TC field.
	GPIO_ENABLE_W1TC_ENABLE_W1TC_Pos = 0x0
	// Bit mask of ENABLE_W1TC field.
	GPIO_ENABLE_W1TC_ENABLE_W1TC_Msk = 0xffffffff

	// ENABLE1: GPIO output enable register for GPIO32-56
	// Position of DATA field.
	GPIO_ENABLE1_DATA_Pos = 0x0
	// Bit mask of DATA field.
	GPIO_ENABLE1_DATA_Msk = 0x1ffffff

	// ENABLE1_W1TS: GPIO output enable set register for GPIO32-56
	// Position of ENABLE1_W1TS field.
	GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Pos = 0x0
	// Bit mask of ENABLE1_W1TS field.
	GPIO_ENABLE1_W1TS_ENABLE1_W1TS_Msk = 0x1ffffff

	// ENABLE1_W1TC: GPIO output enable clear register for GPIO32-56
	// Position of ENABLE1_W1TC field.
	GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Pos = 0x0
	// Bit mask of ENABLE1_W1TC field.
	GPIO_ENABLE1_W1TC_ENABLE1_W1TC_Msk = 0x1ffffff

	// STRAP: pad strapping register
	// Position of STRAPPING field.
	GPIO_STRAP_STRAPPING_Pos = 0x0
	// Bit mask of STRAPPING field.
	GPIO_STRAP_STRAPPING_Msk = 0xffff

	// IN: GPIO input register for GPIO0-31
	// Position of DATA_NEXT field.
	GPIO_IN_DATA_NEXT_Pos = 0x0
	// Bit mask of DATA_NEXT field.
	GPIO_IN_DATA_NEXT_Msk = 0xffffffff

	// IN1: GPIO input register for GPIO32-56
	// Position of DATA_NEXT field.
	GPIO_IN1_DATA_NEXT_Pos = 0x0
	// Bit mask of DATA_NEXT field.
	GPIO_IN1_DATA_NEXT_Msk = 0x1ffffff

	// STATUS: GPIO interrupt status register for GPIO0-31
	// Position of INTERRUPT field.
	GPIO_STATUS_INTERRUPT_Pos = 0x0
	// Bit mask of INTERRUPT field.
	GPIO_STATUS_INTERRUPT_Msk = 0xffffffff

	// STATUS_W1TS: GPIO interrupt status set register for GPIO0-31
	// Position of STATUS_W1TS field.
	GPIO_STATUS_W1TS_STATUS_W1TS_Pos = 0x0
	// Bit mask of STATUS_W1TS field.
	GPIO_STATUS_W1TS_STATUS_W1TS_Msk = 0xffffffff

	// STATUS_W1TC: GPIO interrupt status clear register for GPIO0-31
	// Position of STATUS_W1TC field.
	GPIO_STATUS_W1TC_STATUS_W1TC_Pos = 0x0
	// Bit mask of STATUS_W1TC field.
	GPIO_STATUS_W1TC_STATUS_W1TC_Msk = 0xffffffff

	// STATUS1: GPIO interrupt status register for GPIO32-56
	// Position of INTERRUPT field.
	GPIO_STATUS1_INTERRUPT_Pos = 0x0
	// Bit mask of INTERRUPT field.
	GPIO_STATUS1_INTERRUPT_Msk = 0x1ffffff

	// STATUS1_W1TS: GPIO interrupt status set register for GPIO32-56
	// Position of STATUS1_W1TS field.
	GPIO_STATUS1_W1TS_STATUS1_W1TS_Pos = 0x0
	// Bit mask of STATUS1_W1TS field.
	GPIO_STATUS1_W1TS_STATUS1_W1TS_Msk = 0x1ffffff

	// STATUS1_W1TC: GPIO interrupt status clear register for GPIO32-56
	// Position of STATUS1_W1TC field.
	GPIO_STATUS1_W1TC_STATUS1_W1TC_Pos = 0x0
	// Bit mask of STATUS1_W1TC field.
	GPIO_STATUS1_W1TC_STATUS1_W1TC_Msk = 0x1ffffff

	// INTR_0: GPIO interrupt 0 status register for GPIO0-31
	// Position of INT_0 field.
	GPIO_INTR_0_INT_0_Pos = 0x0
	// Bit mask of INT_0 field.
	GPIO_INTR_0_INT_0_Msk = 0xffffffff

	// INTR1_0: GPIO interrupt 0 status register for GPIO32-56
	// Position of INT1_0 field.
	GPIO_INTR1_0_INT1_0_Pos = 0x0
	// Bit mask of INT1_0 field.
	GPIO_INTR1_0_INT1_0_Msk = 0x1ffffff

	// INTR_1: GPIO interrupt 1 status register for GPIO0-31
	// Position of INT_1 field.
	GPIO_INTR_1_INT_1_Pos = 0x0
	// Bit mask of INT_1 field.
	GPIO_INTR_1_INT_1_Msk = 0xffffffff

	// INTR1_1: GPIO interrupt 1 status register for GPIO32-56
	// Position of INT1_1 field.
	GPIO_INTR1_1_INT1_1_Pos = 0x0
	// Bit mask of INT1_1 field.
	GPIO_INTR1_1_INT1_1_Msk = 0x1ffffff

	// STATUS_NEXT: GPIO interrupt source register for GPIO0-31
	// Position of STATUS_INTERRUPT_NEXT field.
	GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Pos = 0x0
	// Bit mask of STATUS_INTERRUPT_NEXT field.
	GPIO_STATUS_NEXT_STATUS_INTERRUPT_NEXT_Msk = 0xffffffff

	// STATUS_NEXT1: GPIO interrupt source register for GPIO32-56
	// Position of STATUS_INTERRUPT_NEXT1 field.
	GPIO_STATUS_NEXT1_STATUS_INTERRUPT_NEXT1_Pos = 0x0
	// Bit mask of STATUS_INTERRUPT_NEXT1 field.
	GPIO_STATUS_NEXT1_STATUS_INTERRUPT_NEXT1_Msk = 0x1ffffff

	// PIN0: GPIO pin configuration register
	// Position of SYNC2_BYPASS field.
	GPIO_PIN_SYNC2_BYPASS_Pos = 0x0
	// Bit mask of SYNC2_BYPASS field.
	GPIO_PIN_SYNC2_BYPASS_Msk = 0x3
	// Position of PAD_DRIVER field.
	GPIO_PIN_PAD_DRIVER_Pos = 0x2
	// Bit mask of PAD_DRIVER field.
	GPIO_PIN_PAD_DRIVER_Msk = 0x4
	// Bit PAD_DRIVER.
	GPIO_PIN_PAD_DRIVER = 0x4
	// Position of SYNC1_BYPASS field.
	GPIO_PIN_SYNC1_BYPASS_Pos = 0x3
	// Bit mask of SYNC1_BYPASS field.
	GPIO_PIN_SYNC1_BYPASS_Msk = 0x18
	// Position of INT_TYPE field.
	GPIO_PIN_INT_TYPE_Pos = 0x7
	// Bit mask of INT_TYPE field.
	GPIO_PIN_INT_TYPE_Msk = 0x380
	// Position of WAKEUP_ENABLE field.
	GPIO_PIN_WAKEUP_ENABLE_Pos = 0xa
	// Bit mask of WAKEUP_ENABLE field.
	GPIO_PIN_WAKEUP_ENABLE_Msk = 0x400
	// Bit WAKEUP_ENABLE.
	GPIO_PIN_WAKEUP_ENABLE = 0x400
	// Position of CONFIG field.
	GPIO_PIN_CONFIG_Pos = 0xb
	// Bit mask of CONFIG field.
	GPIO_PIN_CONFIG_Msk = 0x1800
	// Position of INT_ENA field.
	GPIO_PIN_INT_ENA_Pos = 0xd
	// Bit mask of INT_ENA field.
	GPIO_PIN_INT_ENA_Msk = 0x3e000

	// FUNC1_IN_SEL_CFG: GPIO input function configuration register
	// Position of IN_SEL field.
	GPIO_FUNC_IN_SEL_CFG_IN_SEL_Pos = 0x0
	// Bit mask of IN_SEL field.
	GPIO_FUNC_IN_SEL_CFG_IN_SEL_Msk = 0x3f
	// Position of IN_INV_SEL field.
	GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Pos = 0x6
	// Bit mask of IN_INV_SEL field.
	GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL_Msk = 0x40
	// Bit IN_INV_SEL.
	GPIO_FUNC_IN_SEL_CFG_IN_INV_SEL = 0x40
	// Position of SEL field.
	GPIO_FUNC_IN_SEL_CFG_SEL_Pos = 0x7
	// Bit mask of SEL field.
	GPIO_FUNC_IN_SEL_CFG_SEL_Msk = 0x80
	// Bit SEL.
	GPIO_FUNC_IN_SEL_CFG_SEL = 0x80

	// FUNC0_OUT_SEL_CFG: GPIO output function select register
	// Position of OUT_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Pos = 0x0
	// Bit mask of OUT_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_OUT_SEL_Msk = 0x1ff
	// Position of INV_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Pos = 0x9
	// Bit mask of INV_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_INV_SEL_Msk = 0x200
	// Bit INV_SEL.
	GPIO_FUNC_OUT_SEL_CFG_INV_SEL = 0x200
	// Position of OEN_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Pos = 0xa
	// Bit mask of OEN_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_OEN_SEL_Msk = 0x400
	// Bit OEN_SEL.
	GPIO_FUNC_OUT_SEL_CFG_OEN_SEL = 0x400
	// Position of OEN_INV_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Pos = 0xb
	// Bit mask of OEN_INV_SEL field.
	GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL_Msk = 0x800
	// Bit OEN_INV_SEL.
	GPIO_FUNC_OUT_SEL_CFG_OEN_INV_SEL = 0x800

	// INTR_2: GPIO interrupt 2 status register for GPIO0-31
	// Position of INT_2 field.
	GPIO_INTR_2_INT_2_Pos = 0x0
	// Bit mask of INT_2 field.
	GPIO_INTR_2_INT_2_Msk = 0xffffffff

	// INTR1_2: GPIO interrupt 2 status register for GPIO32-56
	// Position of INT1_2 field.
	GPIO_INTR1_2_INT1_2_Pos = 0x0
	// Bit mask of INT1_2 field.
	GPIO_INTR1_2_INT1_2_Msk = 0x1ffffff

	// INTR_3: GPIO interrupt 3 status register for GPIO0-31
	// Position of INT_3 field.
	GPIO_INTR_3_INT_3_Pos = 0x0
	// Bit mask of INT_3 field.
	GPIO_INTR_3_INT_3_Msk = 0xffffffff

	// INTR1_3: GPIO interrupt 3 status register for GPIO32-56
	// Position of INT1_3 field.
	GPIO_INTR1_3_INT1_3_Pos = 0x0
	// Bit mask of INT1_3 field.
	GPIO_INTR1_3_INT1_3_Msk = 0x1ffffff

	// CLOCK_GATE: GPIO clock gate register
	// Position of CLK_EN field.
	GPIO_CLOCK_GATE_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	GPIO_CLOCK_GATE_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	GPIO_CLOCK_GATE_CLK_EN = 0x1

	// INT_RAW: analog comparator interrupt raw
	// Position of COMP0_NEG_INT_RAW field.
	GPIO_INT_RAW_COMP0_NEG_INT_RAW_Pos = 0x0
	// Bit mask of COMP0_NEG_INT_RAW field.
	GPIO_INT_RAW_COMP0_NEG_INT_RAW_Msk = 0x1
	// Bit COMP0_NEG_INT_RAW.
	GPIO_INT_RAW_COMP0_NEG_INT_RAW = 0x1
	// Position of COMP0_POS_INT_RAW field.
	GPIO_INT_RAW_COMP0_POS_INT_RAW_Pos = 0x1
	// Bit mask of COMP0_POS_INT_RAW field.
	GPIO_INT_RAW_COMP0_POS_INT_RAW_Msk = 0x2
	// Bit COMP0_POS_INT_RAW.
	GPIO_INT_RAW_COMP0_POS_INT_RAW = 0x2
	// Position of COMP0_ALL_INT_RAW field.
	GPIO_INT_RAW_COMP0_ALL_INT_RAW_Pos = 0x2
	// Bit mask of COMP0_ALL_INT_RAW field.
	GPIO_INT_RAW_COMP0_ALL_INT_RAW_Msk = 0x4
	// Bit COMP0_ALL_INT_RAW.
	GPIO_INT_RAW_COMP0_ALL_INT_RAW = 0x4
	// Position of COMP1_NEG_INT_RAW field.
	GPIO_INT_RAW_COMP1_NEG_INT_RAW_Pos = 0x3
	// Bit mask of COMP1_NEG_INT_RAW field.
	GPIO_INT_RAW_COMP1_NEG_INT_RAW_Msk = 0x8
	// Bit COMP1_NEG_INT_RAW.
	GPIO_INT_RAW_COMP1_NEG_INT_RAW = 0x8
	// Position of COMP1_POS_INT_RAW field.
	GPIO_INT_RAW_COMP1_POS_INT_RAW_Pos = 0x4
	// Bit mask of COMP1_POS_INT_RAW field.
	GPIO_INT_RAW_COMP1_POS_INT_RAW_Msk = 0x10
	// Bit COMP1_POS_INT_RAW.
	GPIO_INT_RAW_COMP1_POS_INT_RAW = 0x10
	// Position of COMP1_ALL_INT_RAW field.
	GPIO_INT_RAW_COMP1_ALL_INT_RAW_Pos = 0x5
	// Bit mask of COMP1_ALL_INT_RAW field.
	GPIO_INT_RAW_COMP1_ALL_INT_RAW_Msk = 0x20
	// Bit COMP1_ALL_INT_RAW.
	GPIO_INT_RAW_COMP1_ALL_INT_RAW = 0x20
	// Position of BISTOK_INT_RAW field.
	GPIO_INT_RAW_BISTOK_INT_RAW_Pos = 0x6
	// Bit mask of BISTOK_INT_RAW field.
	GPIO_INT_RAW_BISTOK_INT_RAW_Msk = 0x40
	// Bit BISTOK_INT_RAW.
	GPIO_INT_RAW_BISTOK_INT_RAW = 0x40
	// Position of BISTFAIL_INT_RAW field.
	GPIO_INT_RAW_BISTFAIL_INT_RAW_Pos = 0x7
	// Bit mask of BISTFAIL_INT_RAW field.
	GPIO_INT_RAW_BISTFAIL_INT_RAW_Msk = 0x80
	// Bit BISTFAIL_INT_RAW.
	GPIO_INT_RAW_BISTFAIL_INT_RAW = 0x80

	// INT_ST: analog comparator interrupt status
	// Position of COMP0_NEG_INT_ST field.
	GPIO_INT_ST_COMP0_NEG_INT_ST_Pos = 0x0
	// Bit mask of COMP0_NEG_INT_ST field.
	GPIO_INT_ST_COMP0_NEG_INT_ST_Msk = 0x1
	// Bit COMP0_NEG_INT_ST.
	GPIO_INT_ST_COMP0_NEG_INT_ST = 0x1
	// Position of COMP0_POS_INT_ST field.
	GPIO_INT_ST_COMP0_POS_INT_ST_Pos = 0x1
	// Bit mask of COMP0_POS_INT_ST field.
	GPIO_INT_ST_COMP0_POS_INT_ST_Msk = 0x2
	// Bit COMP0_POS_INT_ST.
	GPIO_INT_ST_COMP0_POS_INT_ST = 0x2
	// Position of COMP0_ALL_INT_ST field.
	GPIO_INT_ST_COMP0_ALL_INT_ST_Pos = 0x2
	// Bit mask of COMP0_ALL_INT_ST field.
	GPIO_INT_ST_COMP0_ALL_INT_ST_Msk = 0x4
	// Bit COMP0_ALL_INT_ST.
	GPIO_INT_ST_COMP0_ALL_INT_ST = 0x4
	// Position of COMP1_NEG_INT_ST field.
	GPIO_INT_ST_COMP1_NEG_INT_ST_Pos = 0x3
	// Bit mask of COMP1_NEG_INT_ST field.
	GPIO_INT_ST_COMP1_NEG_INT_ST_Msk = 0x8
	// Bit COMP1_NEG_INT_ST.
	GPIO_INT_ST_COMP1_NEG_INT_ST = 0x8
	// Position of COMP1_POS_INT_ST field.
	GPIO_INT_ST_COMP1_POS_INT_ST_Pos = 0x4
	// Bit mask of COMP1_POS_INT_ST field.
	GPIO_INT_ST_COMP1_POS_INT_ST_Msk = 0x10
	// Bit COMP1_POS_INT_ST.
	GPIO_INT_ST_COMP1_POS_INT_ST = 0x10
	// Position of COMP1_ALL_INT_ST field.
	GPIO_INT_ST_COMP1_ALL_INT_ST_Pos = 0x5
	// Bit mask of COMP1_ALL_INT_ST field.
	GPIO_INT_ST_COMP1_ALL_INT_ST_Msk = 0x20
	// Bit COMP1_ALL_INT_ST.
	GPIO_INT_ST_COMP1_ALL_INT_ST = 0x20
	// Position of BISTOK_INT_ST field.
	GPIO_INT_ST_BISTOK_INT_ST_Pos = 0x6
	// Bit mask of BISTOK_INT_ST field.
	GPIO_INT_ST_BISTOK_INT_ST_Msk = 0x40
	// Bit BISTOK_INT_ST.
	GPIO_INT_ST_BISTOK_INT_ST = 0x40
	// Position of BISTFAIL_INT_ST field.
	GPIO_INT_ST_BISTFAIL_INT_ST_Pos = 0x7
	// Bit mask of BISTFAIL_INT_ST field.
	GPIO_INT_ST_BISTFAIL_INT_ST_Msk = 0x80
	// Bit BISTFAIL_INT_ST.
	GPIO_INT_ST_BISTFAIL_INT_ST = 0x80

	// INT_ENA: analog comparator interrupt enable
	// Position of COMP0_NEG_INT_ENA field.
	GPIO_INT_ENA_COMP0_NEG_INT_ENA_Pos = 0x0
	// Bit mask of COMP0_NEG_INT_ENA field.
	GPIO_INT_ENA_COMP0_NEG_INT_ENA_Msk = 0x1
	// Bit COMP0_NEG_INT_ENA.
	GPIO_INT_ENA_COMP0_NEG_INT_ENA = 0x1
	// Position of COMP0_POS_INT_ENA field.
	GPIO_INT_ENA_COMP0_POS_INT_ENA_Pos = 0x1
	// Bit mask of COMP0_POS_INT_ENA field.
	GPIO_INT_ENA_COMP0_POS_INT_ENA_Msk = 0x2
	// Bit COMP0_POS_INT_ENA.
	GPIO_INT_ENA_COMP0_POS_INT_ENA = 0x2
	// Position of COMP0_ALL_INT_ENA field.
	GPIO_INT_ENA_COMP0_ALL_INT_ENA_Pos = 0x2
	// Bit mask of COMP0_ALL_INT_ENA field.
	GPIO_INT_ENA_COMP0_ALL_INT_ENA_Msk = 0x4
	// Bit COMP0_ALL_INT_ENA.
	GPIO_INT_ENA_COMP0_ALL_INT_ENA = 0x4
	// Position of COMP1_NEG_INT_ENA field.
	GPIO_INT_ENA_COMP1_NEG_INT_ENA_Pos = 0x3
	// Bit mask of COMP1_NEG_INT_ENA field.
	GPIO_INT_ENA_COMP1_NEG_INT_ENA_Msk = 0x8
	// Bit COMP1_NEG_INT_ENA.
	GPIO_INT_ENA_COMP1_NEG_INT_ENA = 0x8
	// Position of COMP1_POS_INT_ENA field.
	GPIO_INT_ENA_COMP1_POS_INT_ENA_Pos = 0x4
	// Bit mask of COMP1_POS_INT_ENA field.
	GPIO_INT_ENA_COMP1_POS_INT_ENA_Msk = 0x10
	// Bit COMP1_POS_INT_ENA.
	GPIO_INT_ENA_COMP1_POS_INT_ENA = 0x10
	// Position of COMP1_ALL_INT_ENA field.
	GPIO_INT_ENA_COMP1_ALL_INT_ENA_Pos = 0x5
	// Bit mask of COMP1_ALL_INT_ENA field.
	GPIO_INT_ENA_COMP1_ALL_INT_ENA_Msk = 0x20
	// Bit COMP1_ALL_INT_ENA.
	GPIO_INT_ENA_COMP1_ALL_INT_ENA = 0x20
	// Position of BISTOK_INT_ENA field.
	GPIO_INT_ENA_BISTOK_INT_ENA_Pos = 0x6
	// Bit mask of BISTOK_INT_ENA field.
	GPIO_INT_ENA_BISTOK_INT_ENA_Msk = 0x40
	// Bit BISTOK_INT_ENA.
	GPIO_INT_ENA_BISTOK_INT_ENA = 0x40
	// Position of BISTFAIL_INT_ENA field.
	GPIO_INT_ENA_BISTFAIL_INT_ENA_Pos = 0x7
	// Bit mask of BISTFAIL_INT_ENA field.
	GPIO_INT_ENA_BISTFAIL_INT_ENA_Msk = 0x80
	// Bit BISTFAIL_INT_ENA.
	GPIO_INT_ENA_BISTFAIL_INT_ENA = 0x80

	// INT_CLR: analog comparator interrupt clear
	// Position of COMP0_NEG_INT_CLR field.
	GPIO_INT_CLR_COMP0_NEG_INT_CLR_Pos = 0x0
	// Bit mask of COMP0_NEG_INT_CLR field.
	GPIO_INT_CLR_COMP0_NEG_INT_CLR_Msk = 0x1
	// Bit COMP0_NEG_INT_CLR.
	GPIO_INT_CLR_COMP0_NEG_INT_CLR = 0x1
	// Position of COMP0_POS_INT_CLR field.
	GPIO_INT_CLR_COMP0_POS_INT_CLR_Pos = 0x1
	// Bit mask of COMP0_POS_INT_CLR field.
	GPIO_INT_CLR_COMP0_POS_INT_CLR_Msk = 0x2
	// Bit COMP0_POS_INT_CLR.
	GPIO_INT_CLR_COMP0_POS_INT_CLR = 0x2
	// Position of COMP0_ALL_INT_CLR field.
	GPIO_INT_CLR_COMP0_ALL_INT_CLR_Pos = 0x2
	// Bit mask of COMP0_ALL_INT_CLR field.
	GPIO_INT_CLR_COMP0_ALL_INT_CLR_Msk = 0x4
	// Bit COMP0_ALL_INT_CLR.
	GPIO_INT_CLR_COMP0_ALL_INT_CLR = 0x4
	// Position of COMP1_NEG_INT_CLR field.
	GPIO_INT_CLR_COMP1_NEG_INT_CLR_Pos = 0x3
	// Bit mask of COMP1_NEG_INT_CLR field.
	GPIO_INT_CLR_COMP1_NEG_INT_CLR_Msk = 0x8
	// Bit COMP1_NEG_INT_CLR.
	GPIO_INT_CLR_COMP1_NEG_INT_CLR = 0x8
	// Position of COMP1_POS_INT_CLR field.
	GPIO_INT_CLR_COMP1_POS_INT_CLR_Pos = 0x4
	// Bit mask of COMP1_POS_INT_CLR field.
	GPIO_INT_CLR_COMP1_POS_INT_CLR_Msk = 0x10
	// Bit COMP1_POS_INT_CLR.
	GPIO_INT_CLR_COMP1_POS_INT_CLR = 0x10
	// Position of COMP1_ALL_INT_CLR field.
	GPIO_INT_CLR_COMP1_ALL_INT_CLR_Pos = 0x5
	// Bit mask of COMP1_ALL_INT_CLR field.
	GPIO_INT_CLR_COMP1_ALL_INT_CLR_Msk = 0x20
	// Bit COMP1_ALL_INT_CLR.
	GPIO_INT_CLR_COMP1_ALL_INT_CLR = 0x20
	// Position of BISTOK_INT_CLR field.
	GPIO_INT_CLR_BISTOK_INT_CLR_Pos = 0x6
	// Bit mask of BISTOK_INT_CLR field.
	GPIO_INT_CLR_BISTOK_INT_CLR_Msk = 0x40
	// Bit BISTOK_INT_CLR.
	GPIO_INT_CLR_BISTOK_INT_CLR = 0x40
	// Position of BISTFAIL_INT_CLR field.
	GPIO_INT_CLR_BISTFAIL_INT_CLR_Pos = 0x7
	// Bit mask of BISTFAIL_INT_CLR field.
	GPIO_INT_CLR_BISTFAIL_INT_CLR_Msk = 0x80
	// Bit BISTFAIL_INT_CLR.
	GPIO_INT_CLR_BISTFAIL_INT_CLR = 0x80

	// ZERO_DET0_FILTER_CNT: GPIO analog comparator zero detect filter count
	// Position of ZERO_DET0_FILTER_CNT field.
	GPIO_ZERO_DET0_FILTER_CNT_ZERO_DET0_FILTER_CNT_Pos = 0x0
	// Bit mask of ZERO_DET0_FILTER_CNT field.
	GPIO_ZERO_DET0_FILTER_CNT_ZERO_DET0_FILTER_CNT_Msk = 0xffffffff

	// ZERO_DET1_FILTER_CNT: GPIO analog comparator zero detect filter count
	// Position of ZERO_DET1_FILTER_CNT field.
	GPIO_ZERO_DET1_FILTER_CNT_ZERO_DET1_FILTER_CNT_Pos = 0x0
	// Bit mask of ZERO_DET1_FILTER_CNT field.
	GPIO_ZERO_DET1_FILTER_CNT_ZERO_DET1_FILTER_CNT_Msk = 0xffffffff

	// SEND_SEQ: High speed sdio pad bist send sequence
	// Position of SEND_SEQ field.
	GPIO_SEND_SEQ_SEND_SEQ_Pos = 0x0
	// Bit mask of SEND_SEQ field.
	GPIO_SEND_SEQ_SEND_SEQ_Msk = 0xffffffff

	// RECIVE_SEQ: High speed sdio pad bist recive sequence
	// Position of RECIVE_SEQ field.
	GPIO_RECIVE_SEQ_RECIVE_SEQ_Pos = 0x0
	// Bit mask of RECIVE_SEQ field.
	GPIO_RECIVE_SEQ_RECIVE_SEQ_Msk = 0xffffffff

	// BISTIN_SEL: High speed sdio pad bist in pad sel
	// Position of BISTIN_SEL field.
	GPIO_BISTIN_SEL_BISTIN_SEL_Pos = 0x0
	// Bit mask of BISTIN_SEL field.
	GPIO_BISTIN_SEL_BISTIN_SEL_Msk = 0xf

	// BIST_CTRL: High speed sdio pad bist control
	// Position of BIST_PAD_OE field.
	GPIO_BIST_CTRL_BIST_PAD_OE_Pos = 0x0
	// Bit mask of BIST_PAD_OE field.
	GPIO_BIST_CTRL_BIST_PAD_OE_Msk = 0x1
	// Bit BIST_PAD_OE.
	GPIO_BIST_CTRL_BIST_PAD_OE = 0x1
	// Position of BIST_START field.
	GPIO_BIST_CTRL_BIST_START_Pos = 0x1
	// Bit mask of BIST_START field.
	GPIO_BIST_CTRL_BIST_START_Msk = 0x2
	// Bit BIST_START.
	GPIO_BIST_CTRL_BIST_START = 0x2

	// DATE: GPIO version register
	// Position of DATE field.
	GPIO_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	GPIO_DATE_DATE_Msk = 0xfffffff
)

// Constants for GPIO_SD: Sigma-Delta Modulation
const (
	// SIGMADELTA0: Duty Cycle Configure Register of SDM%s
	// Position of SD_IN field.
	GPIOSD_SIGMADELTA_SD_IN_Pos = 0x0
	// Bit mask of SD_IN field.
	GPIOSD_SIGMADELTA_SD_IN_Msk = 0xff
	// Position of SD_PRESCALE field.
	GPIOSD_SIGMADELTA_SD_PRESCALE_Pos = 0x8
	// Bit mask of SD_PRESCALE field.
	GPIOSD_SIGMADELTA_SD_PRESCALE_Msk = 0xff00

	// CLOCK_GATE: Clock Gating Configure Register
	// Position of CLK_EN field.
	GPIOSD_CLOCK_GATE_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	GPIOSD_CLOCK_GATE_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	GPIOSD_CLOCK_GATE_CLK_EN = 0x1

	// SIGMADELTA_MISC: MISC Register
	// Position of FUNCTION_CLK_EN field.
	GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Pos = 0x1e
	// Bit mask of FUNCTION_CLK_EN field.
	GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN_Msk = 0x40000000
	// Bit FUNCTION_CLK_EN.
	GPIOSD_SIGMADELTA_MISC_FUNCTION_CLK_EN = 0x40000000
	// Position of SPI_SWAP field.
	GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Pos = 0x1f
	// Bit mask of SPI_SWAP field.
	GPIOSD_SIGMADELTA_MISC_SPI_SWAP_Msk = 0x80000000
	// Bit SPI_SWAP.
	GPIOSD_SIGMADELTA_MISC_SPI_SWAP = 0x80000000

	// GLITCH_FILTER_CH0: Glitch Filter Configure Register of Channel%s
	// Position of FILTER_CH0_EN field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN_Pos = 0x0
	// Bit mask of FILTER_CH0_EN field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN_Msk = 0x1
	// Bit FILTER_CH0_EN.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_EN = 0x1
	// Position of FILTER_CH0_INPUT_IO_NUM field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_INPUT_IO_NUM_Pos = 0x1
	// Bit mask of FILTER_CH0_INPUT_IO_NUM field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_INPUT_IO_NUM_Msk = 0x7e
	// Position of FILTER_CH0_WINDOW_THRES field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_THRES_Pos = 0x7
	// Bit mask of FILTER_CH0_WINDOW_THRES field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_THRES_Msk = 0x1f80
	// Position of FILTER_CH0_WINDOW_WIDTH field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_WIDTH_Pos = 0xd
	// Bit mask of FILTER_CH0_WINDOW_WIDTH field.
	GPIOSD_GLITCH_FILTER_CH_FILTER_CH0_WINDOW_WIDTH_Msk = 0x7e000

	// ETM_EVENT_CH0_CFG: Etm Config register of Channel%s
	// Position of ETM_CH0_EVENT_SEL field.
	GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_SEL_Pos = 0x0
	// Bit mask of ETM_CH0_EVENT_SEL field.
	GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_SEL_Msk = 0x3f
	// Position of ETM_CH0_EVENT_EN field.
	GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN_Pos = 0x7
	// Bit mask of ETM_CH0_EVENT_EN field.
	GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN_Msk = 0x80
	// Bit ETM_CH0_EVENT_EN.
	GPIOSD_ETM_EVENT_CH_CFG_ETM_CH0_EVENT_EN = 0x80

	// ETM_TASK_P0_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO0_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO0_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO0_EN.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_EN = 0x1
	// Position of ETM_TASK_GPIO0_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO0_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO0_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO1_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO1_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO1_EN.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_EN = 0x100
	// Position of ETM_TASK_GPIO1_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO1_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO1_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO2_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO2_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO2_EN.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_EN = 0x10000
	// Position of ETM_TASK_GPIO2_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO2_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO2_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO3_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO3_EN field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO3_EN.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_EN = 0x1000000
	// Position of ETM_TASK_GPIO3_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO3_SEL field.
	GPIOSD_ETM_TASK_P0_CFG_ETM_TASK_GPIO3_SEL_Msk = 0xe000000

	// ETM_TASK_P1_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO4_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO4_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO4_EN.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_EN = 0x1
	// Position of ETM_TASK_GPIO4_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO4_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO4_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO5_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO5_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO5_EN.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_EN = 0x100
	// Position of ETM_TASK_GPIO5_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO5_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO5_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO6_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO6_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO6_EN.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_EN = 0x10000
	// Position of ETM_TASK_GPIO6_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO6_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO6_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO7_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO7_EN field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO7_EN.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_EN = 0x1000000
	// Position of ETM_TASK_GPIO7_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO7_SEL field.
	GPIOSD_ETM_TASK_P1_CFG_ETM_TASK_GPIO7_SEL_Msk = 0xe000000

	// ETM_TASK_P2_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO8_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO8_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO8_EN.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_EN = 0x1
	// Position of ETM_TASK_GPIO8_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO8_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO8_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO9_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO9_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO9_EN.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_EN = 0x100
	// Position of ETM_TASK_GPIO9_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO9_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO9_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO10_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO10_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO10_EN.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_EN = 0x10000
	// Position of ETM_TASK_GPIO10_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO10_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO10_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO11_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO11_EN field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO11_EN.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_EN = 0x1000000
	// Position of ETM_TASK_GPIO11_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO11_SEL field.
	GPIOSD_ETM_TASK_P2_CFG_ETM_TASK_GPIO11_SEL_Msk = 0xe000000

	// ETM_TASK_P3_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO12_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO12_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO12_EN.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_EN = 0x1
	// Position of ETM_TASK_GPIO12_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO12_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO12_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO13_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO13_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO13_EN.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_EN = 0x100
	// Position of ETM_TASK_GPIO13_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO13_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO13_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO14_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO14_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO14_EN.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_EN = 0x10000
	// Position of ETM_TASK_GPIO14_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO14_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO14_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO15_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO15_EN field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO15_EN.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_EN = 0x1000000
	// Position of ETM_TASK_GPIO15_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO15_SEL field.
	GPIOSD_ETM_TASK_P3_CFG_ETM_TASK_GPIO15_SEL_Msk = 0xe000000

	// ETM_TASK_P4_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO16_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO16_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO16_EN.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_EN = 0x1
	// Position of ETM_TASK_GPIO16_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO16_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO16_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO17_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO17_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO17_EN.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_EN = 0x100
	// Position of ETM_TASK_GPIO17_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO17_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO17_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO18_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO18_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO18_EN.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_EN = 0x10000
	// Position of ETM_TASK_GPIO18_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO18_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO18_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO19_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO19_EN field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO19_EN.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_EN = 0x1000000
	// Position of ETM_TASK_GPIO19_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO19_SEL field.
	GPIOSD_ETM_TASK_P4_CFG_ETM_TASK_GPIO19_SEL_Msk = 0xe000000

	// ETM_TASK_P5_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO20_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO20_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO20_EN.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_EN = 0x1
	// Position of ETM_TASK_GPIO20_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO20_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO20_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO21_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO21_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO21_EN.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_EN = 0x100
	// Position of ETM_TASK_GPIO21_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO21_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO21_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO22_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO22_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO22_EN.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_EN = 0x10000
	// Position of ETM_TASK_GPIO22_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO22_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO22_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO23_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO23_EN field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO23_EN.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_EN = 0x1000000
	// Position of ETM_TASK_GPIO23_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO23_SEL field.
	GPIOSD_ETM_TASK_P5_CFG_ETM_TASK_GPIO23_SEL_Msk = 0xe000000

	// ETM_TASK_P6_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO24_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO24_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO24_EN.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_EN = 0x1
	// Position of ETM_TASK_GPIO24_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO24_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO24_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO25_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO25_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO25_EN.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_EN = 0x100
	// Position of ETM_TASK_GPIO25_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO25_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO25_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO26_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO26_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO26_EN.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_EN = 0x10000
	// Position of ETM_TASK_GPIO26_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO26_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO26_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO27_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO27_EN field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO27_EN.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_EN = 0x1000000
	// Position of ETM_TASK_GPIO27_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO27_SEL field.
	GPIOSD_ETM_TASK_P6_CFG_ETM_TASK_GPIO27_SEL_Msk = 0xe000000

	// ETM_TASK_P7_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO28_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO28_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO28_EN.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_EN = 0x1
	// Position of ETM_TASK_GPIO28_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO28_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO28_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO29_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO29_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO29_EN.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_EN = 0x100
	// Position of ETM_TASK_GPIO29_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO29_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO29_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO30_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO30_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO30_EN.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_EN = 0x10000
	// Position of ETM_TASK_GPIO30_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO30_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO30_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO31_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO31_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO31_EN field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO31_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO31_EN.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO31_EN = 0x1000000
	// Position of ETM_TASK_GPIO31_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO31_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO31_SEL field.
	GPIOSD_ETM_TASK_P7_CFG_ETM_TASK_GPIO31_SEL_Msk = 0xe000000

	// ETM_TASK_P8_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO32_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO32_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO32_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO32_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO32_EN.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO32_EN = 0x1
	// Position of ETM_TASK_GPIO32_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO32_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO32_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO32_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO33_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO33_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO33_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO33_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO33_EN.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO33_EN = 0x100
	// Position of ETM_TASK_GPIO33_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO33_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO33_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO33_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO34_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO34_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO34_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO34_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO34_EN.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO34_EN = 0x10000
	// Position of ETM_TASK_GPIO34_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO34_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO34_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO34_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO35_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO35_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO35_EN field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO35_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO35_EN.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO35_EN = 0x1000000
	// Position of ETM_TASK_GPIO35_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO35_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO35_SEL field.
	GPIOSD_ETM_TASK_P8_CFG_ETM_TASK_GPIO35_SEL_Msk = 0xe000000

	// ETM_TASK_P9_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO36_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO36_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO36_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO36_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO36_EN.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO36_EN = 0x1
	// Position of ETM_TASK_GPIO36_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO36_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO36_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO36_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO37_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO37_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO37_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO37_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO37_EN.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO37_EN = 0x100
	// Position of ETM_TASK_GPIO37_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO37_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO37_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO37_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO38_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO38_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO38_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO38_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO38_EN.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO38_EN = 0x10000
	// Position of ETM_TASK_GPIO38_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO38_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO38_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO38_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO39_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO39_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO39_EN field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO39_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO39_EN.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO39_EN = 0x1000000
	// Position of ETM_TASK_GPIO39_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO39_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO39_SEL field.
	GPIOSD_ETM_TASK_P9_CFG_ETM_TASK_GPIO39_SEL_Msk = 0xe000000

	// ETM_TASK_P10_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO40_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO40_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO40_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO40_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO40_EN.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO40_EN = 0x1
	// Position of ETM_TASK_GPIO40_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO40_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO40_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO40_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO41_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO41_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO41_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO41_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO41_EN.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO41_EN = 0x100
	// Position of ETM_TASK_GPIO41_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO41_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO41_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO41_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO42_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO42_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO42_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO42_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO42_EN.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO42_EN = 0x10000
	// Position of ETM_TASK_GPIO42_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO42_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO42_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO42_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO43_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO43_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO43_EN field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO43_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO43_EN.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO43_EN = 0x1000000
	// Position of ETM_TASK_GPIO43_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO43_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO43_SEL field.
	GPIOSD_ETM_TASK_P10_CFG_ETM_TASK_GPIO43_SEL_Msk = 0xe000000

	// ETM_TASK_P11_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO44_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO44_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO44_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO44_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO44_EN.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO44_EN = 0x1
	// Position of ETM_TASK_GPIO44_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO44_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO44_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO44_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO45_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO45_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO45_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO45_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO45_EN.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO45_EN = 0x100
	// Position of ETM_TASK_GPIO45_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO45_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO45_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO45_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO46_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO46_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO46_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO46_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO46_EN.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO46_EN = 0x10000
	// Position of ETM_TASK_GPIO46_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO46_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO46_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO46_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO47_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO47_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO47_EN field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO47_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO47_EN.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO47_EN = 0x1000000
	// Position of ETM_TASK_GPIO47_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO47_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO47_SEL field.
	GPIOSD_ETM_TASK_P11_CFG_ETM_TASK_GPIO47_SEL_Msk = 0xe000000

	// ETM_TASK_P12_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO48_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO48_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO48_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO48_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO48_EN.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO48_EN = 0x1
	// Position of ETM_TASK_GPIO48_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO48_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO48_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO48_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO49_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO49_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO49_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO49_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO49_EN.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO49_EN = 0x100
	// Position of ETM_TASK_GPIO49_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO49_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO49_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO49_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO50_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO50_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO50_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO50_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO50_EN.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO50_EN = 0x10000
	// Position of ETM_TASK_GPIO50_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO50_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO50_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO50_SEL_Msk = 0xe0000
	// Position of ETM_TASK_GPIO51_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO51_EN_Pos = 0x18
	// Bit mask of ETM_TASK_GPIO51_EN field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO51_EN_Msk = 0x1000000
	// Bit ETM_TASK_GPIO51_EN.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO51_EN = 0x1000000
	// Position of ETM_TASK_GPIO51_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO51_SEL_Pos = 0x19
	// Bit mask of ETM_TASK_GPIO51_SEL field.
	GPIOSD_ETM_TASK_P12_CFG_ETM_TASK_GPIO51_SEL_Msk = 0xe000000

	// ETM_TASK_P13_CFG: Etm Configure Register to decide which GPIO been chosen
	// Position of ETM_TASK_GPIO52_EN field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO52_EN_Pos = 0x0
	// Bit mask of ETM_TASK_GPIO52_EN field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO52_EN_Msk = 0x1
	// Bit ETM_TASK_GPIO52_EN.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO52_EN = 0x1
	// Position of ETM_TASK_GPIO52_SEL field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO52_SEL_Pos = 0x1
	// Bit mask of ETM_TASK_GPIO52_SEL field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO52_SEL_Msk = 0xe
	// Position of ETM_TASK_GPIO53_EN field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO53_EN_Pos = 0x8
	// Bit mask of ETM_TASK_GPIO53_EN field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO53_EN_Msk = 0x100
	// Bit ETM_TASK_GPIO53_EN.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO53_EN = 0x100
	// Position of ETM_TASK_GPIO53_SEL field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO53_SEL_Pos = 0x9
	// Bit mask of ETM_TASK_GPIO53_SEL field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO53_SEL_Msk = 0xe00
	// Position of ETM_TASK_GPIO54_EN field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO54_EN_Pos = 0x10
	// Bit mask of ETM_TASK_GPIO54_EN field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO54_EN_Msk = 0x10000
	// Bit ETM_TASK_GPIO54_EN.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO54_EN = 0x10000
	// Position of ETM_TASK_GPIO54_SEL field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO54_SEL_Pos = 0x11
	// Bit mask of ETM_TASK_GPIO54_SEL field.
	GPIOSD_ETM_TASK_P13_CFG_ETM_TASK_GPIO54_SEL_Msk = 0xe0000

	// VERSION: Version Control Register
	// Position of GPIO_SD_DATE field.
	GPIOSD_VERSION_GPIO_SD_DATE_Pos = 0x0
	// Bit mask of GPIO_SD_DATE field.
	GPIOSD_VERSION_GPIO_SD_DATE_Msk = 0xfffffff
)

// Constants for H264: H264 Encoder (Core)
const (
	// SYS_CTRL: H264 system level control register.
	// Position of FRAME_START field.
	H264_SYS_CTRL_FRAME_START_Pos = 0x0
	// Bit mask of FRAME_START field.
	H264_SYS_CTRL_FRAME_START_Msk = 0x1
	// Bit FRAME_START.
	H264_SYS_CTRL_FRAME_START = 0x1
	// Position of DMA_MOVE_START field.
	H264_SYS_CTRL_DMA_MOVE_START_Pos = 0x1
	// Bit mask of DMA_MOVE_START field.
	H264_SYS_CTRL_DMA_MOVE_START_Msk = 0x2
	// Bit DMA_MOVE_START.
	H264_SYS_CTRL_DMA_MOVE_START = 0x2
	// Position of FRAME_MODE field.
	H264_SYS_CTRL_FRAME_MODE_Pos = 0x2
	// Bit mask of FRAME_MODE field.
	H264_SYS_CTRL_FRAME_MODE_Msk = 0x4
	// Bit FRAME_MODE.
	H264_SYS_CTRL_FRAME_MODE = 0x4
	// Position of SYS_RST_PULSE field.
	H264_SYS_CTRL_SYS_RST_PULSE_Pos = 0x3
	// Bit mask of SYS_RST_PULSE field.
	H264_SYS_CTRL_SYS_RST_PULSE_Msk = 0x8
	// Bit SYS_RST_PULSE.
	H264_SYS_CTRL_SYS_RST_PULSE = 0x8

	// GOP_CONF: GOP related configuration register.
	// Position of DUAL_STREAM_MODE field.
	H264_GOP_CONF_DUAL_STREAM_MODE_Pos = 0x0
	// Bit mask of DUAL_STREAM_MODE field.
	H264_GOP_CONF_DUAL_STREAM_MODE_Msk = 0x1
	// Bit DUAL_STREAM_MODE.
	H264_GOP_CONF_DUAL_STREAM_MODE = 0x1
	// Position of GOP_NUM field.
	H264_GOP_CONF_GOP_NUM_Pos = 0x1
	// Bit mask of GOP_NUM field.
	H264_GOP_CONF_GOP_NUM_Msk = 0x1fe

	// A_SYS_MB_RES: Video A horizontal and vertical MB resolution register.
	// Position of A_SYS_TOTAL_MB_Y field.
	H264_A_SYS_MB_RES_A_SYS_TOTAL_MB_Y_Pos = 0x0
	// Bit mask of A_SYS_TOTAL_MB_Y field.
	H264_A_SYS_MB_RES_A_SYS_TOTAL_MB_Y_Msk = 0x7f
	// Position of A_SYS_TOTAL_MB_X field.
	H264_A_SYS_MB_RES_A_SYS_TOTAL_MB_X_Pos = 0x7
	// Bit mask of A_SYS_TOTAL_MB_X field.
	H264_A_SYS_MB_RES_A_SYS_TOTAL_MB_X_Msk = 0x3f80

	// A_SYS_CONF: Video A system level configuration register.
	// Position of A_DB_TMP_READY_TRIGGER_MB_NUM field.
	H264_A_SYS_CONF_A_DB_TMP_READY_TRIGGER_MB_NUM_Pos = 0x0
	// Bit mask of A_DB_TMP_READY_TRIGGER_MB_NUM field.
	H264_A_SYS_CONF_A_DB_TMP_READY_TRIGGER_MB_NUM_Msk = 0x7f
	// Position of A_REC_READY_TRIGGER_MB_LINES field.
	H264_A_SYS_CONF_A_REC_READY_TRIGGER_MB_LINES_Pos = 0x7
	// Bit mask of A_REC_READY_TRIGGER_MB_LINES field.
	H264_A_SYS_CONF_A_REC_READY_TRIGGER_MB_LINES_Msk = 0x3f80
	// Position of A_INTRA_COST_CMP_OFFSET field.
	H264_A_SYS_CONF_A_INTRA_COST_CMP_OFFSET_Pos = 0xe
	// Bit mask of A_INTRA_COST_CMP_OFFSET field.
	H264_A_SYS_CONF_A_INTRA_COST_CMP_OFFSET_Msk = 0x3fffc000

	// A_DECI_SCORE: Video A luma and chroma MB decimate score Register.
	// Position of A_C_DECI_SCORE field.
	H264_A_DECI_SCORE_A_C_DECI_SCORE_Pos = 0x0
	// Bit mask of A_C_DECI_SCORE field.
	H264_A_DECI_SCORE_A_C_DECI_SCORE_Msk = 0x3ff
	// Position of A_L_DECI_SCORE field.
	H264_A_DECI_SCORE_A_L_DECI_SCORE_Pos = 0xa
	// Bit mask of A_L_DECI_SCORE field.
	H264_A_DECI_SCORE_A_L_DECI_SCORE_Msk = 0xffc00

	// A_DECI_SCORE_OFFSET: Video A luma and chroma MB decimate score offset Register.
	// Position of A_I16X16_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_I16X16_DECI_SCORE_OFFSET_Pos = 0x0
	// Bit mask of A_I16X16_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_I16X16_DECI_SCORE_OFFSET_Msk = 0x3f
	// Position of A_I_CHROMA_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_I_CHROMA_DECI_SCORE_OFFSET_Pos = 0x6
	// Bit mask of A_I_CHROMA_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_I_CHROMA_DECI_SCORE_OFFSET_Msk = 0xfc0
	// Position of A_P16X16_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_P16X16_DECI_SCORE_OFFSET_Pos = 0xc
	// Bit mask of A_P16X16_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_P16X16_DECI_SCORE_OFFSET_Msk = 0x3f000
	// Position of A_P_CHROMA_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_P_CHROMA_DECI_SCORE_OFFSET_Pos = 0x12
	// Bit mask of A_P_CHROMA_DECI_SCORE_OFFSET field.
	H264_A_DECI_SCORE_OFFSET_A_P_CHROMA_DECI_SCORE_OFFSET_Msk = 0xfc0000

	// A_RC_CONF0: Video A rate control configuration register0.
	// Position of A_QP field.
	H264_A_RC_CONF0_A_QP_Pos = 0x0
	// Bit mask of A_QP field.
	H264_A_RC_CONF0_A_QP_Msk = 0x3f
	// Position of A_RATE_CTRL_U field.
	H264_A_RC_CONF0_A_RATE_CTRL_U_Pos = 0x6
	// Bit mask of A_RATE_CTRL_U field.
	H264_A_RC_CONF0_A_RATE_CTRL_U_Msk = 0x3fffc0
	// Position of A_MB_RATE_CTRL_EN field.
	H264_A_RC_CONF0_A_MB_RATE_CTRL_EN_Pos = 0x16
	// Bit mask of A_MB_RATE_CTRL_EN field.
	H264_A_RC_CONF0_A_MB_RATE_CTRL_EN_Msk = 0x400000
	// Bit A_MB_RATE_CTRL_EN.
	H264_A_RC_CONF0_A_MB_RATE_CTRL_EN = 0x400000

	// A_RC_CONF1: Video A rate control configuration register1.
	// Position of A_CHROMA_DC_QP_DELTA field.
	H264_A_RC_CONF1_A_CHROMA_DC_QP_DELTA_Pos = 0x0
	// Bit mask of A_CHROMA_DC_QP_DELTA field.
	H264_A_RC_CONF1_A_CHROMA_DC_QP_DELTA_Msk = 0x7
	// Position of A_CHROMA_QP_DELTA field.
	H264_A_RC_CONF1_A_CHROMA_QP_DELTA_Pos = 0x3
	// Bit mask of A_CHROMA_QP_DELTA field.
	H264_A_RC_CONF1_A_CHROMA_QP_DELTA_Msk = 0x78
	// Position of A_QP_MIN field.
	H264_A_RC_CONF1_A_QP_MIN_Pos = 0x7
	// Bit mask of A_QP_MIN field.
	H264_A_RC_CONF1_A_QP_MIN_Msk = 0x1f80
	// Position of A_QP_MAX field.
	H264_A_RC_CONF1_A_QP_MAX_Pos = 0xd
	// Bit mask of A_QP_MAX field.
	H264_A_RC_CONF1_A_QP_MAX_Msk = 0x7e000
	// Position of A_MAD_FRAME_PRED field.
	H264_A_RC_CONF1_A_MAD_FRAME_PRED_Pos = 0x13
	// Bit mask of A_MAD_FRAME_PRED field.
	H264_A_RC_CONF1_A_MAD_FRAME_PRED_Msk = 0x7ff80000

	// A_DB_BYPASS: Video A Deblocking bypass register
	// Position of A_BYPASS_DB_FILTER field.
	H264_A_DB_BYPASS_A_BYPASS_DB_FILTER_Pos = 0x0
	// Bit mask of A_BYPASS_DB_FILTER field.
	H264_A_DB_BYPASS_A_BYPASS_DB_FILTER_Msk = 0x1
	// Bit A_BYPASS_DB_FILTER.
	H264_A_DB_BYPASS_A_BYPASS_DB_FILTER = 0x1

	// A_ROI_REGION0: Video A H264 ROI region0 range configure register.
	// Position of X field.
	H264_A_ROI_REGION0_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION0_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION0_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION0_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION0_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION0_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION0_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION0_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION0_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION0_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION0_EN = 0x10000000

	// A_ROI_REGION1: Video A H264 ROI region1 range configure register.
	// Position of X field.
	H264_A_ROI_REGION1_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION1_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION1_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION1_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION1_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION1_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION1_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION1_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION1_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION1_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION1_EN = 0x10000000

	// A_ROI_REGION2: Video A H264 ROI region2 range configure register.
	// Position of X field.
	H264_A_ROI_REGION2_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION2_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION2_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION2_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION2_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION2_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION2_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION2_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION2_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION2_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION2_EN = 0x10000000

	// A_ROI_REGION3: Video A H264 ROI region3 range configure register.
	// Position of X field.
	H264_A_ROI_REGION3_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION3_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION3_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION3_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION3_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION3_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION3_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION3_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION3_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION3_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION3_EN = 0x10000000

	// A_ROI_REGION4: Video A H264 ROI region4 range configure register.
	// Position of X field.
	H264_A_ROI_REGION4_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION4_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION4_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION4_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION4_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION4_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION4_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION4_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION4_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION4_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION4_EN = 0x10000000

	// A_ROI_REGION5: Video A H264 ROI region5 range configure register.
	// Position of X field.
	H264_A_ROI_REGION5_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION5_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION5_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION5_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION5_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION5_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION5_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION5_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION5_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION5_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION5_EN = 0x10000000

	// A_ROI_REGION6: Video A H264 ROI region6 range configure register.
	// Position of X field.
	H264_A_ROI_REGION6_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION6_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION6_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION6_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION6_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION6_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION6_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION6_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION6_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION6_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION6_EN = 0x10000000

	// A_ROI_REGION7: Video A H264 ROI region7 range configure register.
	// Position of X field.
	H264_A_ROI_REGION7_X_Pos = 0x0
	// Bit mask of X field.
	H264_A_ROI_REGION7_X_Msk = 0x7f
	// Position of Y field.
	H264_A_ROI_REGION7_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_A_ROI_REGION7_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_A_ROI_REGION7_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_A_ROI_REGION7_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_A_ROI_REGION7_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_A_ROI_REGION7_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_A_ROI_REGION7_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_A_ROI_REGION7_EN_Msk = 0x10000000
	// Bit EN.
	H264_A_ROI_REGION7_EN = 0x10000000

	// A_ROI_REGION0_3_QP: Video A H264 ROI region0, region1,region2,region3 QP register.
	// Position of A_ROI_REGION0_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION0_QP_Pos = 0x0
	// Bit mask of A_ROI_REGION0_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION0_QP_Msk = 0x7f
	// Position of A_ROI_REGION1_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION1_QP_Pos = 0x7
	// Bit mask of A_ROI_REGION1_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION1_QP_Msk = 0x3f80
	// Position of A_ROI_REGION2_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION2_QP_Pos = 0xe
	// Bit mask of A_ROI_REGION2_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION2_QP_Msk = 0x1fc000
	// Position of A_ROI_REGION3_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION3_QP_Pos = 0x15
	// Bit mask of A_ROI_REGION3_QP field.
	H264_A_ROI_REGION0_3_QP_A_ROI_REGION3_QP_Msk = 0xfe00000

	// A_ROI_REGION4_7_QP: Video A H264 ROI region4, region5,region6,region7 QP register.
	// Position of A_ROI_REGION4_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION4_QP_Pos = 0x0
	// Bit mask of A_ROI_REGION4_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION4_QP_Msk = 0x7f
	// Position of A_ROI_REGION5_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION5_QP_Pos = 0x7
	// Bit mask of A_ROI_REGION5_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION5_QP_Msk = 0x3f80
	// Position of A_ROI_REGION6_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION6_QP_Pos = 0xe
	// Bit mask of A_ROI_REGION6_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION6_QP_Msk = 0x1fc000
	// Position of A_ROI_REGION7_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION7_QP_Pos = 0x15
	// Bit mask of A_ROI_REGION7_QP field.
	H264_A_ROI_REGION4_7_QP_A_ROI_REGION7_QP_Msk = 0xfe00000

	// A_NO_ROI_REGION_QP_OFFSET: Video A H264 no roi region QP register.
	// Position of A_NO_ROI_REGION_QP field.
	H264_A_NO_ROI_REGION_QP_OFFSET_A_NO_ROI_REGION_QP_Pos = 0x0
	// Bit mask of A_NO_ROI_REGION_QP field.
	H264_A_NO_ROI_REGION_QP_OFFSET_A_NO_ROI_REGION_QP_Msk = 0x7f

	// A_ROI_CONFIG: Video A H264 ROI configure register.
	// Position of A_ROI_EN field.
	H264_A_ROI_CONFIG_A_ROI_EN_Pos = 0x0
	// Bit mask of A_ROI_EN field.
	H264_A_ROI_CONFIG_A_ROI_EN_Msk = 0x1
	// Bit A_ROI_EN.
	H264_A_ROI_CONFIG_A_ROI_EN = 0x1
	// Position of A_ROI_MODE field.
	H264_A_ROI_CONFIG_A_ROI_MODE_Pos = 0x1
	// Bit mask of A_ROI_MODE field.
	H264_A_ROI_CONFIG_A_ROI_MODE_Msk = 0x2
	// Bit A_ROI_MODE.
	H264_A_ROI_CONFIG_A_ROI_MODE = 0x2

	// B_SYS_MB_RES: Video B horizontal and vertical MB resolution register.
	// Position of B_SYS_TOTAL_MB_Y field.
	H264_B_SYS_MB_RES_B_SYS_TOTAL_MB_Y_Pos = 0x0
	// Bit mask of B_SYS_TOTAL_MB_Y field.
	H264_B_SYS_MB_RES_B_SYS_TOTAL_MB_Y_Msk = 0x7f
	// Position of B_SYS_TOTAL_MB_X field.
	H264_B_SYS_MB_RES_B_SYS_TOTAL_MB_X_Pos = 0x7
	// Bit mask of B_SYS_TOTAL_MB_X field.
	H264_B_SYS_MB_RES_B_SYS_TOTAL_MB_X_Msk = 0x3f80

	// B_SYS_CONF: Video B system level configuration register.
	// Position of B_DB_TMP_READY_TRIGGER_MB_NUM field.
	H264_B_SYS_CONF_B_DB_TMP_READY_TRIGGER_MB_NUM_Pos = 0x0
	// Bit mask of B_DB_TMP_READY_TRIGGER_MB_NUM field.
	H264_B_SYS_CONF_B_DB_TMP_READY_TRIGGER_MB_NUM_Msk = 0x7f
	// Position of B_REC_READY_TRIGGER_MB_LINES field.
	H264_B_SYS_CONF_B_REC_READY_TRIGGER_MB_LINES_Pos = 0x7
	// Bit mask of B_REC_READY_TRIGGER_MB_LINES field.
	H264_B_SYS_CONF_B_REC_READY_TRIGGER_MB_LINES_Msk = 0x3f80
	// Position of B_INTRA_COST_CMP_OFFSET field.
	H264_B_SYS_CONF_B_INTRA_COST_CMP_OFFSET_Pos = 0xe
	// Bit mask of B_INTRA_COST_CMP_OFFSET field.
	H264_B_SYS_CONF_B_INTRA_COST_CMP_OFFSET_Msk = 0x3fffc000

	// B_DECI_SCORE: Video B luma and chroma MB decimate score Register.
	// Position of B_C_DECI_SCORE field.
	H264_B_DECI_SCORE_B_C_DECI_SCORE_Pos = 0x0
	// Bit mask of B_C_DECI_SCORE field.
	H264_B_DECI_SCORE_B_C_DECI_SCORE_Msk = 0x3ff
	// Position of B_L_DECI_SCORE field.
	H264_B_DECI_SCORE_B_L_DECI_SCORE_Pos = 0xa
	// Bit mask of B_L_DECI_SCORE field.
	H264_B_DECI_SCORE_B_L_DECI_SCORE_Msk = 0xffc00

	// B_DECI_SCORE_OFFSET: Video B luma and chroma MB decimate score offset Register.
	// Position of B_I16X16_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_I16X16_DECI_SCORE_OFFSET_Pos = 0x0
	// Bit mask of B_I16X16_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_I16X16_DECI_SCORE_OFFSET_Msk = 0x3f
	// Position of B_I_CHROMA_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_I_CHROMA_DECI_SCORE_OFFSET_Pos = 0x6
	// Bit mask of B_I_CHROMA_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_I_CHROMA_DECI_SCORE_OFFSET_Msk = 0xfc0
	// Position of B_P16X16_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_P16X16_DECI_SCORE_OFFSET_Pos = 0xc
	// Bit mask of B_P16X16_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_P16X16_DECI_SCORE_OFFSET_Msk = 0x3f000
	// Position of B_P_CHROMA_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_P_CHROMA_DECI_SCORE_OFFSET_Pos = 0x12
	// Bit mask of B_P_CHROMA_DECI_SCORE_OFFSET field.
	H264_B_DECI_SCORE_OFFSET_B_P_CHROMA_DECI_SCORE_OFFSET_Msk = 0xfc0000

	// B_RC_CONF0: Video B rate control configuration register0.
	// Position of B_QP field.
	H264_B_RC_CONF0_B_QP_Pos = 0x0
	// Bit mask of B_QP field.
	H264_B_RC_CONF0_B_QP_Msk = 0x3f
	// Position of B_RATE_CTRL_U field.
	H264_B_RC_CONF0_B_RATE_CTRL_U_Pos = 0x6
	// Bit mask of B_RATE_CTRL_U field.
	H264_B_RC_CONF0_B_RATE_CTRL_U_Msk = 0x3fffc0
	// Position of B_MB_RATE_CTRL_EN field.
	H264_B_RC_CONF0_B_MB_RATE_CTRL_EN_Pos = 0x16
	// Bit mask of B_MB_RATE_CTRL_EN field.
	H264_B_RC_CONF0_B_MB_RATE_CTRL_EN_Msk = 0x400000
	// Bit B_MB_RATE_CTRL_EN.
	H264_B_RC_CONF0_B_MB_RATE_CTRL_EN = 0x400000

	// B_RC_CONF1: Video B rate control configuration register1.
	// Position of B_CHROMA_DC_QP_DELTA field.
	H264_B_RC_CONF1_B_CHROMA_DC_QP_DELTA_Pos = 0x0
	// Bit mask of B_CHROMA_DC_QP_DELTA field.
	H264_B_RC_CONF1_B_CHROMA_DC_QP_DELTA_Msk = 0x7
	// Position of B_CHROMA_QP_DELTA field.
	H264_B_RC_CONF1_B_CHROMA_QP_DELTA_Pos = 0x3
	// Bit mask of B_CHROMA_QP_DELTA field.
	H264_B_RC_CONF1_B_CHROMA_QP_DELTA_Msk = 0x78
	// Position of B_QP_MIN field.
	H264_B_RC_CONF1_B_QP_MIN_Pos = 0x7
	// Bit mask of B_QP_MIN field.
	H264_B_RC_CONF1_B_QP_MIN_Msk = 0x1f80
	// Position of B_QP_MAX field.
	H264_B_RC_CONF1_B_QP_MAX_Pos = 0xd
	// Bit mask of B_QP_MAX field.
	H264_B_RC_CONF1_B_QP_MAX_Msk = 0x7e000
	// Position of B_MAD_FRAME_PRED field.
	H264_B_RC_CONF1_B_MAD_FRAME_PRED_Pos = 0x13
	// Bit mask of B_MAD_FRAME_PRED field.
	H264_B_RC_CONF1_B_MAD_FRAME_PRED_Msk = 0x7ff80000

	// B_DB_BYPASS: Video B Deblocking bypass register
	// Position of B_BYPASS_DB_FILTER field.
	H264_B_DB_BYPASS_B_BYPASS_DB_FILTER_Pos = 0x0
	// Bit mask of B_BYPASS_DB_FILTER field.
	H264_B_DB_BYPASS_B_BYPASS_DB_FILTER_Msk = 0x1
	// Bit B_BYPASS_DB_FILTER.
	H264_B_DB_BYPASS_B_BYPASS_DB_FILTER = 0x1

	// B_ROI_REGION0: Video B H264 ROI region0 range configure register.
	// Position of X field.
	H264_B_ROI_REGION0_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION0_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION0_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION0_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION0_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION0_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION0_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION0_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION0_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION0_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION0_EN = 0x10000000

	// B_ROI_REGION1: Video B H264 ROI region1 range configure register.
	// Position of X field.
	H264_B_ROI_REGION1_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION1_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION1_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION1_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION1_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION1_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION1_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION1_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION1_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION1_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION1_EN = 0x10000000

	// B_ROI_REGION2: Video B H264 ROI region2 range configure register.
	// Position of X field.
	H264_B_ROI_REGION2_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION2_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION2_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION2_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION2_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION2_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION2_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION2_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION2_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION2_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION2_EN = 0x10000000

	// B_ROI_REGION3: Video B H264 ROI region3 range configure register.
	// Position of X field.
	H264_B_ROI_REGION3_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION3_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION3_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION3_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION3_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION3_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION3_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION3_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION3_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION3_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION3_EN = 0x10000000

	// B_ROI_REGION4: Video B H264 ROI region4 range configure register.
	// Position of X field.
	H264_B_ROI_REGION4_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION4_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION4_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION4_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION4_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION4_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION4_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION4_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION4_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION4_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION4_EN = 0x10000000

	// B_ROI_REGION5: Video B H264 ROI region5 range configure register.
	// Position of X field.
	H264_B_ROI_REGION5_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION5_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION5_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION5_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION5_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION5_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION5_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION5_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION5_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION5_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION5_EN = 0x10000000

	// B_ROI_REGION6: Video B H264 ROI region6 range configure register.
	// Position of X field.
	H264_B_ROI_REGION6_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION6_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION6_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION6_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION6_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION6_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION6_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION6_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION6_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION6_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION6_EN = 0x10000000

	// B_ROI_REGION7: Video B H264 ROI region7 range configure register.
	// Position of X field.
	H264_B_ROI_REGION7_X_Pos = 0x0
	// Bit mask of X field.
	H264_B_ROI_REGION7_X_Msk = 0x7f
	// Position of Y field.
	H264_B_ROI_REGION7_Y_Pos = 0x7
	// Bit mask of Y field.
	H264_B_ROI_REGION7_Y_Msk = 0x3f80
	// Position of X_LEN field.
	H264_B_ROI_REGION7_X_LEN_Pos = 0xe
	// Bit mask of X_LEN field.
	H264_B_ROI_REGION7_X_LEN_Msk = 0x1fc000
	// Position of Y_LEN field.
	H264_B_ROI_REGION7_Y_LEN_Pos = 0x15
	// Bit mask of Y_LEN field.
	H264_B_ROI_REGION7_Y_LEN_Msk = 0xfe00000
	// Position of EN field.
	H264_B_ROI_REGION7_EN_Pos = 0x1c
	// Bit mask of EN field.
	H264_B_ROI_REGION7_EN_Msk = 0x10000000
	// Bit EN.
	H264_B_ROI_REGION7_EN = 0x10000000

	// B_ROI_REGION0_3_QP: Video B H264 ROI region0, region1,region2,region3 QP register.
	// Position of B_ROI_REGION0_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION0_QP_Pos = 0x0
	// Bit mask of B_ROI_REGION0_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION0_QP_Msk = 0x7f
	// Position of B_ROI_REGION1_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION1_QP_Pos = 0x7
	// Bit mask of B_ROI_REGION1_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION1_QP_Msk = 0x3f80
	// Position of B_ROI_REGION2_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION2_QP_Pos = 0xe
	// Bit mask of B_ROI_REGION2_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION2_QP_Msk = 0x1fc000
	// Position of B_ROI_REGION3_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION3_QP_Pos = 0x15
	// Bit mask of B_ROI_REGION3_QP field.
	H264_B_ROI_REGION0_3_QP_B_ROI_REGION3_QP_Msk = 0xfe00000

	// B_ROI_REGION4_7_QP: Video B H264 ROI region4, region5,region6,region7 QP register.
	// Position of B_ROI_REGION4_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION4_QP_Pos = 0x0
	// Bit mask of B_ROI_REGION4_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION4_QP_Msk = 0x7f
	// Position of B_ROI_REGION5_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION5_QP_Pos = 0x7
	// Bit mask of B_ROI_REGION5_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION5_QP_Msk = 0x3f80
	// Position of B_ROI_REGION6_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION6_QP_Pos = 0xe
	// Bit mask of B_ROI_REGION6_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION6_QP_Msk = 0x1fc000
	// Position of B_ROI_REGION7_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION7_QP_Pos = 0x15
	// Bit mask of B_ROI_REGION7_QP field.
	H264_B_ROI_REGION4_7_QP_B_ROI_REGION7_QP_Msk = 0xfe00000

	// B_NO_ROI_REGION_QP_OFFSET: Video B H264 no roi region QP register.
	// Position of B_NO_ROI_REGION_QP field.
	H264_B_NO_ROI_REGION_QP_OFFSET_B_NO_ROI_REGION_QP_Pos = 0x0
	// Bit mask of B_NO_ROI_REGION_QP field.
	H264_B_NO_ROI_REGION_QP_OFFSET_B_NO_ROI_REGION_QP_Msk = 0x7f

	// B_ROI_CONFIG: Video B H264 ROI configure register.
	// Position of B_ROI_EN field.
	H264_B_ROI_CONFIG_B_ROI_EN_Pos = 0x0
	// Bit mask of B_ROI_EN field.
	H264_B_ROI_CONFIG_B_ROI_EN_Msk = 0x1
	// Bit B_ROI_EN.
	H264_B_ROI_CONFIG_B_ROI_EN = 0x1
	// Position of B_ROI_MODE field.
	H264_B_ROI_CONFIG_B_ROI_MODE_Pos = 0x1
	// Bit mask of B_ROI_MODE field.
	H264_B_ROI_CONFIG_B_ROI_MODE_Msk = 0x2
	// Bit B_ROI_MODE.
	H264_B_ROI_CONFIG_B_ROI_MODE = 0x2

	// RC_STATUS0: Rate control status register0.
	// Position of FRAME_MAD_SUM field.
	H264_RC_STATUS0_FRAME_MAD_SUM_Pos = 0x0
	// Bit mask of FRAME_MAD_SUM field.
	H264_RC_STATUS0_FRAME_MAD_SUM_Msk = 0x1fffff

	// RC_STATUS1: Rate control status register1.
	// Position of FRAME_ENC_BITS field.
	H264_RC_STATUS1_FRAME_ENC_BITS_Pos = 0x0
	// Bit mask of FRAME_ENC_BITS field.
	H264_RC_STATUS1_FRAME_ENC_BITS_Msk = 0x7ffffff

	// RC_STATUS2: Rate control status register2.
	// Position of FRAME_QP_SUM field.
	H264_RC_STATUS2_FRAME_QP_SUM_Pos = 0x0
	// Bit mask of FRAME_QP_SUM field.
	H264_RC_STATUS2_FRAME_QP_SUM_Msk = 0x7ffff

	// SLICE_HEADER_REMAIN: Frame Slice Header remain bit register.
	// Position of SLICE_REMAIN_BITLENGTH field.
	H264_SLICE_HEADER_REMAIN_SLICE_REMAIN_BITLENGTH_Pos = 0x0
	// Bit mask of SLICE_REMAIN_BITLENGTH field.
	H264_SLICE_HEADER_REMAIN_SLICE_REMAIN_BITLENGTH_Msk = 0x7
	// Position of SLICE_REMAIN_BIT field.
	H264_SLICE_HEADER_REMAIN_SLICE_REMAIN_BIT_Pos = 0x3
	// Bit mask of SLICE_REMAIN_BIT field.
	H264_SLICE_HEADER_REMAIN_SLICE_REMAIN_BIT_Msk = 0x7f8

	// SLICE_HEADER_BYTE_LENGTH: Frame Slice Header byte length register.
	// Position of SLICE_BYTE_LENGTH field.
	H264_SLICE_HEADER_BYTE_LENGTH_SLICE_BYTE_LENGTH_Pos = 0x0
	// Bit mask of SLICE_BYTE_LENGTH field.
	H264_SLICE_HEADER_BYTE_LENGTH_SLICE_BYTE_LENGTH_Msk = 0xf

	// BS_THRESHOLD: Bitstream buffer overflow threshold register
	// Position of BS_BUFFER_THRESHOLD field.
	H264_BS_THRESHOLD_BS_BUFFER_THRESHOLD_Pos = 0x0
	// Bit mask of BS_BUFFER_THRESHOLD field.
	H264_BS_THRESHOLD_BS_BUFFER_THRESHOLD_Msk = 0x7f

	// SLICE_HEADER_BYTE0: Frame Slice Header byte low 32 bit register.
	// Position of SLICE_BYTE_LSB field.
	H264_SLICE_HEADER_BYTE0_SLICE_BYTE_LSB_Pos = 0x0
	// Bit mask of SLICE_BYTE_LSB field.
	H264_SLICE_HEADER_BYTE0_SLICE_BYTE_LSB_Msk = 0xffffffff

	// SLICE_HEADER_BYTE1: Frame Slice Header byte high 32 bit register.
	// Position of SLICE_BYTE_MSB field.
	H264_SLICE_HEADER_BYTE1_SLICE_BYTE_MSB_Pos = 0x0
	// Bit mask of SLICE_BYTE_MSB field.
	H264_SLICE_HEADER_BYTE1_SLICE_BYTE_MSB_Msk = 0xffffffff

	// INT_RAW: Interrupt raw status register
	// Position of DB_TMP_READY_INT_RAW field.
	H264_INT_RAW_DB_TMP_READY_INT_RAW_Pos = 0x0
	// Bit mask of DB_TMP_READY_INT_RAW field.
	H264_INT_RAW_DB_TMP_READY_INT_RAW_Msk = 0x1
	// Bit DB_TMP_READY_INT_RAW.
	H264_INT_RAW_DB_TMP_READY_INT_RAW = 0x1
	// Position of REC_READY_INT_RAW field.
	H264_INT_RAW_REC_READY_INT_RAW_Pos = 0x1
	// Bit mask of REC_READY_INT_RAW field.
	H264_INT_RAW_REC_READY_INT_RAW_Msk = 0x2
	// Bit REC_READY_INT_RAW.
	H264_INT_RAW_REC_READY_INT_RAW = 0x2
	// Position of FRAME_DONE_INT_RAW field.
	H264_INT_RAW_FRAME_DONE_INT_RAW_Pos = 0x2
	// Bit mask of FRAME_DONE_INT_RAW field.
	H264_INT_RAW_FRAME_DONE_INT_RAW_Msk = 0x4
	// Bit FRAME_DONE_INT_RAW.
	H264_INT_RAW_FRAME_DONE_INT_RAW = 0x4
	// Position of DMA_MOVE_2MB_LINE_DONE_INT_RAW field.
	H264_INT_RAW_DMA_MOVE_2MB_LINE_DONE_INT_RAW_Pos = 0x3
	// Bit mask of DMA_MOVE_2MB_LINE_DONE_INT_RAW field.
	H264_INT_RAW_DMA_MOVE_2MB_LINE_DONE_INT_RAW_Msk = 0x8
	// Bit DMA_MOVE_2MB_LINE_DONE_INT_RAW.
	H264_INT_RAW_DMA_MOVE_2MB_LINE_DONE_INT_RAW = 0x8

	// INT_ST: Interrupt masked status register
	// Position of DB_TMP_READY_INT_ST field.
	H264_INT_ST_DB_TMP_READY_INT_ST_Pos = 0x0
	// Bit mask of DB_TMP_READY_INT_ST field.
	H264_INT_ST_DB_TMP_READY_INT_ST_Msk = 0x1
	// Bit DB_TMP_READY_INT_ST.
	H264_INT_ST_DB_TMP_READY_INT_ST = 0x1
	// Position of REC_READY_INT_ST field.
	H264_INT_ST_REC_READY_INT_ST_Pos = 0x1
	// Bit mask of REC_READY_INT_ST field.
	H264_INT_ST_REC_READY_INT_ST_Msk = 0x2
	// Bit REC_READY_INT_ST.
	H264_INT_ST_REC_READY_INT_ST = 0x2
	// Position of FRAME_DONE_INT_ST field.
	H264_INT_ST_FRAME_DONE_INT_ST_Pos = 0x2
	// Bit mask of FRAME_DONE_INT_ST field.
	H264_INT_ST_FRAME_DONE_INT_ST_Msk = 0x4
	// Bit FRAME_DONE_INT_ST.
	H264_INT_ST_FRAME_DONE_INT_ST = 0x4
	// Position of DMA_MOVE_2MB_LINE_DONE_INT_ST field.
	H264_INT_ST_DMA_MOVE_2MB_LINE_DONE_INT_ST_Pos = 0x3
	// Bit mask of DMA_MOVE_2MB_LINE_DONE_INT_ST field.
	H264_INT_ST_DMA_MOVE_2MB_LINE_DONE_INT_ST_Msk = 0x8
	// Bit DMA_MOVE_2MB_LINE_DONE_INT_ST.
	H264_INT_ST_DMA_MOVE_2MB_LINE_DONE_INT_ST = 0x8

	// INT_ENA: Interrupt enable register
	// Position of DB_TMP_READY_INT_ENA field.
	H264_INT_ENA_DB_TMP_READY_INT_ENA_Pos = 0x0
	// Bit mask of DB_TMP_READY_INT_ENA field.
	H264_INT_ENA_DB_TMP_READY_INT_ENA_Msk = 0x1
	// Bit DB_TMP_READY_INT_ENA.
	H264_INT_ENA_DB_TMP_READY_INT_ENA = 0x1
	// Position of REC_READY_INT_ENA field.
	H264_INT_ENA_REC_READY_INT_ENA_Pos = 0x1
	// Bit mask of REC_READY_INT_ENA field.
	H264_INT_ENA_REC_READY_INT_ENA_Msk = 0x2
	// Bit REC_READY_INT_ENA.
	H264_INT_ENA_REC_READY_INT_ENA = 0x2
	// Position of FRAME_DONE_INT_ENA field.
	H264_INT_ENA_FRAME_DONE_INT_ENA_Pos = 0x2
	// Bit mask of FRAME_DONE_INT_ENA field.
	H264_INT_ENA_FRAME_DONE_INT_ENA_Msk = 0x4
	// Bit FRAME_DONE_INT_ENA.
	H264_INT_ENA_FRAME_DONE_INT_ENA = 0x4
	// Position of DMA_MOVE_2MB_LINE_DONE_INT_ENA field.
	H264_INT_ENA_DMA_MOVE_2MB_LINE_DONE_INT_ENA_Pos = 0x3
	// Bit mask of DMA_MOVE_2MB_LINE_DONE_INT_ENA field.
	H264_INT_ENA_DMA_MOVE_2MB_LINE_DONE_INT_ENA_Msk = 0x8
	// Bit DMA_MOVE_2MB_LINE_DONE_INT_ENA.
	H264_INT_ENA_DMA_MOVE_2MB_LINE_DONE_INT_ENA = 0x8

	// INT_CLR: Interrupt clear register
	// Position of DB_TMP_READY_INT_CLR field.
	H264_INT_CLR_DB_TMP_READY_INT_CLR_Pos = 0x0
	// Bit mask of DB_TMP_READY_INT_CLR field.
	H264_INT_CLR_DB_TMP_READY_INT_CLR_Msk = 0x1
	// Bit DB_TMP_READY_INT_CLR.
	H264_INT_CLR_DB_TMP_READY_INT_CLR = 0x1
	// Position of REC_READY_INT_CLR field.
	H264_INT_CLR_REC_READY_INT_CLR_Pos = 0x1
	// Bit mask of REC_READY_INT_CLR field.
	H264_INT_CLR_REC_READY_INT_CLR_Msk = 0x2
	// Bit REC_READY_INT_CLR.
	H264_INT_CLR_REC_READY_INT_CLR = 0x2
	// Position of FRAME_DONE_INT_CLR field.
	H264_INT_CLR_FRAME_DONE_INT_CLR_Pos = 0x2
	// Bit mask of FRAME_DONE_INT_CLR field.
	H264_INT_CLR_FRAME_DONE_INT_CLR_Msk = 0x4
	// Bit FRAME_DONE_INT_CLR.
	H264_INT_CLR_FRAME_DONE_INT_CLR = 0x4
	// Position of DMA_MOVE_2MB_LINE_DONE_INT_CLR field.
	H264_INT_CLR_DMA_MOVE_2MB_LINE_DONE_INT_CLR_Pos = 0x3
	// Bit mask of DMA_MOVE_2MB_LINE_DONE_INT_CLR field.
	H264_INT_CLR_DMA_MOVE_2MB_LINE_DONE_INT_CLR_Msk = 0x8
	// Bit DMA_MOVE_2MB_LINE_DONE_INT_CLR.
	H264_INT_CLR_DMA_MOVE_2MB_LINE_DONE_INT_CLR = 0x8

	// CONF: General configuration register.
	// Position of CLK_EN field.
	H264_CONF_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	H264_CONF_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	H264_CONF_CLK_EN = 0x1
	// Position of REC_RAM_CLK_EN2 field.
	H264_CONF_REC_RAM_CLK_EN2_Pos = 0x1
	// Bit mask of REC_RAM_CLK_EN2 field.
	H264_CONF_REC_RAM_CLK_EN2_Msk = 0x2
	// Bit REC_RAM_CLK_EN2.
	H264_CONF_REC_RAM_CLK_EN2 = 0x2
	// Position of REC_RAM_CLK_EN1 field.
	H264_CONF_REC_RAM_CLK_EN1_Pos = 0x2
	// Bit mask of REC_RAM_CLK_EN1 field.
	H264_CONF_REC_RAM_CLK_EN1_Msk = 0x4
	// Bit REC_RAM_CLK_EN1.
	H264_CONF_REC_RAM_CLK_EN1 = 0x4
	// Position of QUANT_RAM_CLK_EN2 field.
	H264_CONF_QUANT_RAM_CLK_EN2_Pos = 0x3
	// Bit mask of QUANT_RAM_CLK_EN2 field.
	H264_CONF_QUANT_RAM_CLK_EN2_Msk = 0x8
	// Bit QUANT_RAM_CLK_EN2.
	H264_CONF_QUANT_RAM_CLK_EN2 = 0x8
	// Position of QUANT_RAM_CLK_EN1 field.
	H264_CONF_QUANT_RAM_CLK_EN1_Pos = 0x4
	// Bit mask of QUANT_RAM_CLK_EN1 field.
	H264_CONF_QUANT_RAM_CLK_EN1_Msk = 0x10
	// Bit QUANT_RAM_CLK_EN1.
	H264_CONF_QUANT_RAM_CLK_EN1 = 0x10
	// Position of PRE_RAM_CLK_EN field.
	H264_CONF_PRE_RAM_CLK_EN_Pos = 0x5
	// Bit mask of PRE_RAM_CLK_EN field.
	H264_CONF_PRE_RAM_CLK_EN_Msk = 0x20
	// Bit PRE_RAM_CLK_EN.
	H264_CONF_PRE_RAM_CLK_EN = 0x20
	// Position of MVD_RAM_CLK_EN field.
	H264_CONF_MVD_RAM_CLK_EN_Pos = 0x6
	// Bit mask of MVD_RAM_CLK_EN field.
	H264_CONF_MVD_RAM_CLK_EN_Msk = 0x40
	// Bit MVD_RAM_CLK_EN.
	H264_CONF_MVD_RAM_CLK_EN = 0x40
	// Position of MC_RAM_CLK_EN field.
	H264_CONF_MC_RAM_CLK_EN_Pos = 0x7
	// Bit mask of MC_RAM_CLK_EN field.
	H264_CONF_MC_RAM_CLK_EN_Msk = 0x80
	// Bit MC_RAM_CLK_EN.
	H264_CONF_MC_RAM_CLK_EN = 0x80
	// Position of REF_RAM_CLK_EN field.
	H264_CONF_REF_RAM_CLK_EN_Pos = 0x8
	// Bit mask of REF_RAM_CLK_EN field.
	H264_CONF_REF_RAM_CLK_EN_Msk = 0x100
	// Bit REF_RAM_CLK_EN.
	H264_CONF_REF_RAM_CLK_EN = 0x100
	// Position of I4X4_REF_RAM_CLK_EN field.
	H264_CONF_I4X4_REF_RAM_CLK_EN_Pos = 0x9
	// Bit mask of I4X4_REF_RAM_CLK_EN field.
	H264_CONF_I4X4_REF_RAM_CLK_EN_Msk = 0x200
	// Bit I4X4_REF_RAM_CLK_EN.
	H264_CONF_I4X4_REF_RAM_CLK_EN = 0x200
	// Position of IME_RAM_CLK_EN field.
	H264_CONF_IME_RAM_CLK_EN_Pos = 0xa
	// Bit mask of IME_RAM_CLK_EN field.
	H264_CONF_IME_RAM_CLK_EN_Msk = 0x400
	// Bit IME_RAM_CLK_EN.
	H264_CONF_IME_RAM_CLK_EN = 0x400
	// Position of FME_RAM_CLK_EN field.
	H264_CONF_FME_RAM_CLK_EN_Pos = 0xb
	// Bit mask of FME_RAM_CLK_EN field.
	H264_CONF_FME_RAM_CLK_EN_Msk = 0x800
	// Bit FME_RAM_CLK_EN.
	H264_CONF_FME_RAM_CLK_EN = 0x800
	// Position of FETCH_RAM_CLK_EN field.
	H264_CONF_FETCH_RAM_CLK_EN_Pos = 0xc
	// Bit mask of FETCH_RAM_CLK_EN field.
	H264_CONF_FETCH_RAM_CLK_EN_Msk = 0x1000
	// Bit FETCH_RAM_CLK_EN.
	H264_CONF_FETCH_RAM_CLK_EN = 0x1000
	// Position of DB_RAM_CLK_EN field.
	H264_CONF_DB_RAM_CLK_EN_Pos = 0xd
	// Bit mask of DB_RAM_CLK_EN field.
	H264_CONF_DB_RAM_CLK_EN_Msk = 0x2000
	// Bit DB_RAM_CLK_EN.
	H264_CONF_DB_RAM_CLK_EN = 0x2000
	// Position of CUR_MB_RAM_CLK_EN field.
	H264_CONF_CUR_MB_RAM_CLK_EN_Pos = 0xe
	// Bit mask of CUR_MB_RAM_CLK_EN field.
	H264_CONF_CUR_MB_RAM_CLK_EN_Msk = 0x4000
	// Bit CUR_MB_RAM_CLK_EN.
	H264_CONF_CUR_MB_RAM_CLK_EN = 0x4000
	// Position of CAVLC_RAM_CLK_EN field.
	H264_CONF_CAVLC_RAM_CLK_EN_Pos = 0xf
	// Bit mask of CAVLC_RAM_CLK_EN field.
	H264_CONF_CAVLC_RAM_CLK_EN_Msk = 0x8000
	// Bit CAVLC_RAM_CLK_EN.
	H264_CONF_CAVLC_RAM_CLK_EN = 0x8000
	// Position of IME_CLK_EN field.
	H264_CONF_IME_CLK_EN_Pos = 0x10
	// Bit mask of IME_CLK_EN field.
	H264_CONF_IME_CLK_EN_Msk = 0x10000
	// Bit IME_CLK_EN.
	H264_CONF_IME_CLK_EN = 0x10000
	// Position of FME_CLK_EN field.
	H264_CONF_FME_CLK_EN_Pos = 0x11
	// Bit mask of FME_CLK_EN field.
	H264_CONF_FME_CLK_EN_Msk = 0x20000
	// Bit FME_CLK_EN.
	H264_CONF_FME_CLK_EN = 0x20000
	// Position of MC_CLK_EN field.
	H264_CONF_MC_CLK_EN_Pos = 0x12
	// Bit mask of MC_CLK_EN field.
	H264_CONF_MC_CLK_EN_Msk = 0x40000
	// Bit MC_CLK_EN.
	H264_CONF_MC_CLK_EN = 0x40000
	// Position of INTERPOLATOR_CLK_EN field.
	H264_CONF_INTERPOLATOR_CLK_EN_Pos = 0x13
	// Bit mask of INTERPOLATOR_CLK_EN field.
	H264_CONF_INTERPOLATOR_CLK_EN_Msk = 0x80000
	// Bit INTERPOLATOR_CLK_EN.
	H264_CONF_INTERPOLATOR_CLK_EN = 0x80000
	// Position of DB_CLK_EN field.
	H264_CONF_DB_CLK_EN_Pos = 0x14
	// Bit mask of DB_CLK_EN field.
	H264_CONF_DB_CLK_EN_Msk = 0x100000
	// Bit DB_CLK_EN.
	H264_CONF_DB_CLK_EN = 0x100000
	// Position of CLAVLC_CLK_EN field.
	H264_CONF_CLAVLC_CLK_EN_Pos = 0x15
	// Bit mask of CLAVLC_CLK_EN field.
	H264_CONF_CLAVLC_CLK_EN_Msk = 0x200000
	// Bit CLAVLC_CLK_EN.
	H264_CONF_CLAVLC_CLK_EN = 0x200000
	// Position of INTRA_CLK_EN field.
	H264_CONF_INTRA_CLK_EN_Pos = 0x16
	// Bit mask of INTRA_CLK_EN field.
	H264_CONF_INTRA_CLK_EN_Msk = 0x400000
	// Bit INTRA_CLK_EN.
	H264_CONF_INTRA_CLK_EN = 0x400000
	// Position of DECI_CLK_EN field.
	H264_CONF_DECI_CLK_EN_Pos = 0x17
	// Bit mask of DECI_CLK_EN field.
	H264_CONF_DECI_CLK_EN_Msk = 0x800000
	// Bit DECI_CLK_EN.
	H264_CONF_DECI_CLK_EN = 0x800000
	// Position of BS_CLK_EN field.
	H264_CONF_BS_CLK_EN_Pos = 0x18
	// Bit mask of BS_CLK_EN field.
	H264_CONF_BS_CLK_EN_Msk = 0x1000000
	// Bit BS_CLK_EN.
	H264_CONF_BS_CLK_EN = 0x1000000
	// Position of MV_MERGE_CLK_EN field.
	H264_CONF_MV_MERGE_CLK_EN_Pos = 0x19
	// Bit mask of MV_MERGE_CLK_EN field.
	H264_CONF_MV_MERGE_CLK_EN_Msk = 0x2000000
	// Bit MV_MERGE_CLK_EN.
	H264_CONF_MV_MERGE_CLK_EN = 0x2000000

	// MV_MERGE_CONFIG: Mv merge configuration register.
	// Position of MV_MERGE_TYPE field.
	H264_MV_MERGE_CONFIG_MV_MERGE_TYPE_Pos = 0x0
	// Bit mask of MV_MERGE_TYPE field.
	H264_MV_MERGE_CONFIG_MV_MERGE_TYPE_Msk = 0x3
	// Position of INT_MV_OUT_EN field.
	H264_MV_MERGE_CONFIG_INT_MV_OUT_EN_Pos = 0x2
	// Bit mask of INT_MV_OUT_EN field.
	H264_MV_MERGE_CONFIG_INT_MV_OUT_EN_Msk = 0x4
	// Bit INT_MV_OUT_EN.
	H264_MV_MERGE_CONFIG_INT_MV_OUT_EN = 0x4
	// Position of A_MV_MERGE_EN field.
	H264_MV_MERGE_CONFIG_A_MV_MERGE_EN_Pos = 0x3
	// Bit mask of A_MV_MERGE_EN field.
	H264_MV_MERGE_CONFIG_A_MV_MERGE_EN_Msk = 0x8
	// Bit A_MV_MERGE_EN.
	H264_MV_MERGE_CONFIG_A_MV_MERGE_EN = 0x8
	// Position of B_MV_MERGE_EN field.
	H264_MV_MERGE_CONFIG_B_MV_MERGE_EN_Pos = 0x4
	// Bit mask of B_MV_MERGE_EN field.
	H264_MV_MERGE_CONFIG_B_MV_MERGE_EN_Msk = 0x10
	// Bit B_MV_MERGE_EN.
	H264_MV_MERGE_CONFIG_B_MV_MERGE_EN = 0x10
	// Position of MB_VALID_NUM field.
	H264_MV_MERGE_CONFIG_MB_VALID_NUM_Pos = 0x5
	// Bit mask of MB_VALID_NUM field.
	H264_MV_MERGE_CONFIG_MB_VALID_NUM_Msk = 0x3ffe0

	// DEBUG_DMA_SEL: Debug H264 DMA select register
	// Position of DBG_DMA_SEL field.
	H264_DEBUG_DMA_SEL_DBG_DMA_SEL_Pos = 0x0
	// Bit mask of DBG_DMA_SEL field.
	H264_DEBUG_DMA_SEL_DBG_DMA_SEL_Msk = 0xff

	// SYS_STATUS: System status register.
	// Position of FRAME_NUM field.
	H264_SYS_STATUS_FRAME_NUM_Pos = 0x0
	// Bit mask of FRAME_NUM field.
	H264_SYS_STATUS_FRAME_NUM_Msk = 0x1ff
	// Position of DUAL_STREAM_SEL field.
	H264_SYS_STATUS_DUAL_STREAM_SEL_Pos = 0x9
	// Bit mask of DUAL_STREAM_SEL field.
	H264_SYS_STATUS_DUAL_STREAM_SEL_Msk = 0x200
	// Bit DUAL_STREAM_SEL.
	H264_SYS_STATUS_DUAL_STREAM_SEL = 0x200
	// Position of INTRA_FLAG field.
	H264_SYS_STATUS_INTRA_FLAG_Pos = 0xa
	// Bit mask of INTRA_FLAG field.
	H264_SYS_STATUS_INTRA_FLAG_Msk = 0x400
	// Bit INTRA_FLAG.
	H264_SYS_STATUS_INTRA_FLAG = 0x400

	// FRAME_CODE_LENGTH: Frame code byte length register.
	// Position of FRAME_CODE_LENGTH field.
	H264_FRAME_CODE_LENGTH_FRAME_CODE_LENGTH_Pos = 0x0
	// Bit mask of FRAME_CODE_LENGTH field.
	H264_FRAME_CODE_LENGTH_FRAME_CODE_LENGTH_Msk = 0xffffff

	// DEBUG_INFO0: Debug information register0.
	// Position of TOP_CTRL_INTER_DEBUG_STATE field.
	H264_DEBUG_INFO0_TOP_CTRL_INTER_DEBUG_STATE_Pos = 0x0
	// Bit mask of TOP_CTRL_INTER_DEBUG_STATE field.
	H264_DEBUG_INFO0_TOP_CTRL_INTER_DEBUG_STATE_Msk = 0xf
	// Position of TOP_CTRL_INTRA_DEBUG_STATE field.
	H264_DEBUG_INFO0_TOP_CTRL_INTRA_DEBUG_STATE_Pos = 0x4
	// Bit mask of TOP_CTRL_INTRA_DEBUG_STATE field.
	H264_DEBUG_INFO0_TOP_CTRL_INTRA_DEBUG_STATE_Msk = 0x70
	// Position of P_I_CMP_DEBUG_STATE field.
	H264_DEBUG_INFO0_P_I_CMP_DEBUG_STATE_Pos = 0x7
	// Bit mask of P_I_CMP_DEBUG_STATE field.
	H264_DEBUG_INFO0_P_I_CMP_DEBUG_STATE_Msk = 0x380
	// Position of MVD_DEBUG_STATE field.
	H264_DEBUG_INFO0_MVD_DEBUG_STATE_Pos = 0xa
	// Bit mask of MVD_DEBUG_STATE field.
	H264_DEBUG_INFO0_MVD_DEBUG_STATE_Msk = 0x1c00
	// Position of MC_CHROMA_IP_DEBUG_STATE field.
	H264_DEBUG_INFO0_MC_CHROMA_IP_DEBUG_STATE_Pos = 0xd
	// Bit mask of MC_CHROMA_IP_DEBUG_STATE field.
	H264_DEBUG_INFO0_MC_CHROMA_IP_DEBUG_STATE_Msk = 0x2000
	// Bit MC_CHROMA_IP_DEBUG_STATE.
	H264_DEBUG_INFO0_MC_CHROMA_IP_DEBUG_STATE = 0x2000
	// Position of INTRA_16X16_CHROMA_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_Pos = 0xe
	// Bit mask of INTRA_16X16_CHROMA_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_Msk = 0x3c000
	// Position of INTRA_4X4_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_INTRA_4X4_CTRL_DEBUG_STATE_Pos = 0x12
	// Bit mask of INTRA_4X4_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_INTRA_4X4_CTRL_DEBUG_STATE_Msk = 0x3c0000
	// Position of INTRA_TOP_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_INTRA_TOP_CTRL_DEBUG_STATE_Pos = 0x16
	// Bit mask of INTRA_TOP_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_INTRA_TOP_CTRL_DEBUG_STATE_Msk = 0x1c00000
	// Position of IME_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_IME_CTRL_DEBUG_STATE_Pos = 0x19
	// Bit mask of IME_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO0_IME_CTRL_DEBUG_STATE_Msk = 0xe000000

	// DEBUG_INFO1: Debug information register1.
	// Position of FME_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO1_FME_CTRL_DEBUG_STATE_Pos = 0x0
	// Bit mask of FME_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO1_FME_CTRL_DEBUG_STATE_Msk = 0x7
	// Position of DECI_CALC_DEBUG_STATE field.
	H264_DEBUG_INFO1_DECI_CALC_DEBUG_STATE_Pos = 0x3
	// Bit mask of DECI_CALC_DEBUG_STATE field.
	H264_DEBUG_INFO1_DECI_CALC_DEBUG_STATE_Msk = 0x18
	// Position of DB_DEBUG_STATE field.
	H264_DEBUG_INFO1_DB_DEBUG_STATE_Pos = 0x5
	// Bit mask of DB_DEBUG_STATE field.
	H264_DEBUG_INFO1_DB_DEBUG_STATE_Msk = 0xe0
	// Position of CAVLC_ENC_DEBUG_STATE field.
	H264_DEBUG_INFO1_CAVLC_ENC_DEBUG_STATE_Pos = 0x8
	// Bit mask of CAVLC_ENC_DEBUG_STATE field.
	H264_DEBUG_INFO1_CAVLC_ENC_DEBUG_STATE_Msk = 0xf00
	// Position of CAVLC_SCAN_DEBUG_STATE field.
	H264_DEBUG_INFO1_CAVLC_SCAN_DEBUG_STATE_Pos = 0xc
	// Bit mask of CAVLC_SCAN_DEBUG_STATE field.
	H264_DEBUG_INFO1_CAVLC_SCAN_DEBUG_STATE_Msk = 0xf000
	// Position of CAVLC_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO1_CAVLC_CTRL_DEBUG_STATE_Pos = 0x10
	// Bit mask of CAVLC_CTRL_DEBUG_STATE field.
	H264_DEBUG_INFO1_CAVLC_CTRL_DEBUG_STATE_Msk = 0x30000
	// Position of BS_BUFFER_DEBUG_STATE field.
	H264_DEBUG_INFO1_BS_BUFFER_DEBUG_STATE_Pos = 0x12
	// Bit mask of BS_BUFFER_DEBUG_STATE field.
	H264_DEBUG_INFO1_BS_BUFFER_DEBUG_STATE_Msk = 0x40000
	// Bit BS_BUFFER_DEBUG_STATE.
	H264_DEBUG_INFO1_BS_BUFFER_DEBUG_STATE = 0x40000

	// DEBUG_INFO2: Debug information register2.
	// Position of P_RC_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_RC_DONE_DEBUG_FLAG_Pos = 0x0
	// Bit mask of P_RC_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_RC_DONE_DEBUG_FLAG_Msk = 0x1
	// Bit P_RC_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_RC_DONE_DEBUG_FLAG = 0x1
	// Position of P_P_I_CMP_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_P_I_CMP_DONE_DEBUG_FLAG_Pos = 0x1
	// Bit mask of P_P_I_CMP_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_P_I_CMP_DONE_DEBUG_FLAG_Msk = 0x2
	// Bit P_P_I_CMP_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_P_I_CMP_DONE_DEBUG_FLAG = 0x2
	// Position of P_MV_MERGE_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_MV_MERGE_DONE_DEBUG_FLAG_Pos = 0x2
	// Bit mask of P_MV_MERGE_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_MV_MERGE_DONE_DEBUG_FLAG_Msk = 0x4
	// Bit P_MV_MERGE_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_MV_MERGE_DONE_DEBUG_FLAG = 0x4
	// Position of P_MOVE_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_MOVE_ORI_DONE_DEBUG_FLAG_Pos = 0x3
	// Bit mask of P_MOVE_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_MOVE_ORI_DONE_DEBUG_FLAG_Msk = 0x8
	// Bit P_MOVE_ORI_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_MOVE_ORI_DONE_DEBUG_FLAG = 0x8
	// Position of P_MC_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_MC_DONE_DEBUG_FLAG_Pos = 0x4
	// Bit mask of P_MC_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_MC_DONE_DEBUG_FLAG_Msk = 0x10
	// Bit P_MC_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_MC_DONE_DEBUG_FLAG = 0x10
	// Position of P_IME_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_IME_DONE_DEBUG_FLAG_Pos = 0x5
	// Bit mask of P_IME_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_IME_DONE_DEBUG_FLAG_Msk = 0x20
	// Bit P_IME_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_IME_DONE_DEBUG_FLAG = 0x20
	// Position of P_GET_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_GET_ORI_DONE_DEBUG_FLAG_Pos = 0x6
	// Bit mask of P_GET_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_GET_ORI_DONE_DEBUG_FLAG_Msk = 0x40
	// Bit P_GET_ORI_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_GET_ORI_DONE_DEBUG_FLAG = 0x40
	// Position of P_FME_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_FME_DONE_DEBUG_FLAG_Pos = 0x7
	// Bit mask of P_FME_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_FME_DONE_DEBUG_FLAG_Msk = 0x80
	// Bit P_FME_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_FME_DONE_DEBUG_FLAG = 0x80
	// Position of P_FETCH_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_FETCH_DONE_DEBUG_FLAG_Pos = 0x8
	// Bit mask of P_FETCH_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_FETCH_DONE_DEBUG_FLAG_Msk = 0x100
	// Bit P_FETCH_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_FETCH_DONE_DEBUG_FLAG = 0x100
	// Position of P_DB_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_DB_DONE_DEBUG_FLAG_Pos = 0x9
	// Bit mask of P_DB_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_DB_DONE_DEBUG_FLAG_Msk = 0x200
	// Bit P_DB_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_DB_DONE_DEBUG_FLAG = 0x200
	// Position of P_BS_BUF_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_BS_BUF_DONE_DEBUG_FLAG_Pos = 0xa
	// Bit mask of P_BS_BUF_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_P_BS_BUF_DONE_DEBUG_FLAG_Msk = 0x400
	// Bit P_BS_BUF_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_P_BS_BUF_DONE_DEBUG_FLAG = 0x400
	// Position of REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_Pos = 0xb
	// Bit mask of REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_Msk = 0x800
	// Bit REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG = 0x800
	// Position of I_P_I_CMP_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_P_I_CMP_DONE_DEBUG_FLAG_Pos = 0xc
	// Bit mask of I_P_I_CMP_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_P_I_CMP_DONE_DEBUG_FLAG_Msk = 0x1000
	// Bit I_P_I_CMP_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_I_P_I_CMP_DONE_DEBUG_FLAG = 0x1000
	// Position of I_MOVE_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_MOVE_ORI_DONE_DEBUG_FLAG_Pos = 0xd
	// Bit mask of I_MOVE_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_MOVE_ORI_DONE_DEBUG_FLAG_Msk = 0x2000
	// Bit I_MOVE_ORI_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_I_MOVE_ORI_DONE_DEBUG_FLAG = 0x2000
	// Position of I_GET_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_GET_ORI_DONE_DEBUG_FLAG_Pos = 0xe
	// Bit mask of I_GET_ORI_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_GET_ORI_DONE_DEBUG_FLAG_Msk = 0x4000
	// Bit I_GET_ORI_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_I_GET_ORI_DONE_DEBUG_FLAG = 0x4000
	// Position of I_EC_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_EC_DONE_DEBUG_FLAG_Pos = 0xf
	// Bit mask of I_EC_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_EC_DONE_DEBUG_FLAG_Msk = 0x8000
	// Bit I_EC_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_I_EC_DONE_DEBUG_FLAG = 0x8000
	// Position of I_DB_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_DB_DONE_DEBUG_FLAG_Pos = 0x10
	// Bit mask of I_DB_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_DB_DONE_DEBUG_FLAG_Msk = 0x10000
	// Bit I_DB_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_I_DB_DONE_DEBUG_FLAG = 0x10000
	// Position of I_BS_BUF_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_BS_BUF_DONE_DEBUG_FLAG_Pos = 0x11
	// Bit mask of I_BS_BUF_DONE_DEBUG_FLAG field.
	H264_DEBUG_INFO2_I_BS_BUF_DONE_DEBUG_FLAG_Msk = 0x20000
	// Bit I_BS_BUF_DONE_DEBUG_FLAG.
	H264_DEBUG_INFO2_I_BS_BUF_DONE_DEBUG_FLAG = 0x20000

	// DATE: Version control register
	// Position of LEDC_DATE field.
	H264_DATE_LEDC_DATE_Pos = 0x0
	// Bit mask of LEDC_DATE field.
	H264_DATE_LEDC_DATE_Msk = 0xfffffff
)

// Constants for H264_DMA: H264 Encoder (DMA)
const (
	// OUT_CONF0_CH0: TX CH0 config0 register
	// Position of OUT_AUTO_WRBACK_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Pos = 0x0
	// Bit mask of OUT_AUTO_WRBACK_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0_Msk = 0x1
	// Bit OUT_AUTO_WRBACK_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_AUTO_WRBACK_CH0 = 0x1
	// Position of OUT_EOF_MODE_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Pos = 0x1
	// Bit mask of OUT_EOF_MODE_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0_Msk = 0x2
	// Bit OUT_EOF_MODE_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_EOF_MODE_CH0 = 0x2
	// Position of OUTDSCR_BURST_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Pos = 0x2
	// Bit mask of OUTDSCR_BURST_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0_Msk = 0x4
	// Bit OUTDSCR_BURST_EN_CH0.
	H264_DMA_OUT_CONF0_CH0_OUTDSCR_BURST_EN_CH0 = 0x4
	// Position of OUT_ECC_AES_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_ECC_AES_EN_CH0_Pos = 0x3
	// Bit mask of OUT_ECC_AES_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_ECC_AES_EN_CH0_Msk = 0x8
	// Bit OUT_ECC_AES_EN_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_ECC_AES_EN_CH0 = 0x8
	// Position of OUT_CHECK_OWNER_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_CHECK_OWNER_CH0_Pos = 0x4
	// Bit mask of OUT_CHECK_OWNER_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_CHECK_OWNER_CH0_Msk = 0x10
	// Bit OUT_CHECK_OWNER_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_CHECK_OWNER_CH0 = 0x10
	// Position of OUT_MEM_BURST_LENGTH_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_MEM_BURST_LENGTH_CH0_Pos = 0x6
	// Bit mask of OUT_MEM_BURST_LENGTH_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_MEM_BURST_LENGTH_CH0_Msk = 0x1c0
	// Position of OUT_PAGE_BOUND_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_PAGE_BOUND_EN_CH0_Pos = 0xc
	// Bit mask of OUT_PAGE_BOUND_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_PAGE_BOUND_EN_CH0_Msk = 0x1000
	// Bit OUT_PAGE_BOUND_EN_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_PAGE_BOUND_EN_CH0 = 0x1000
	// Position of OUT_REORDER_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_REORDER_EN_CH0_Pos = 0x10
	// Bit mask of OUT_REORDER_EN_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_REORDER_EN_CH0_Msk = 0x10000
	// Bit OUT_REORDER_EN_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_REORDER_EN_CH0 = 0x10000
	// Position of OUT_RST_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Pos = 0x18
	// Bit mask of OUT_RST_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_RST_CH0_Msk = 0x1000000
	// Bit OUT_RST_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_RST_CH0 = 0x1000000
	// Position of OUT_CMD_DISABLE_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_CMD_DISABLE_CH0_Pos = 0x19
	// Bit mask of OUT_CMD_DISABLE_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_CMD_DISABLE_CH0_Msk = 0x2000000
	// Bit OUT_CMD_DISABLE_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_CMD_DISABLE_CH0 = 0x2000000
	// Position of OUT_ARB_WEIGHT_OPT_DIS_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_ARB_WEIGHT_OPT_DIS_CH0_Pos = 0x1a
	// Bit mask of OUT_ARB_WEIGHT_OPT_DIS_CH0 field.
	H264_DMA_OUT_CONF0_CH0_OUT_ARB_WEIGHT_OPT_DIS_CH0_Msk = 0x4000000
	// Bit OUT_ARB_WEIGHT_OPT_DIS_CH0.
	H264_DMA_OUT_CONF0_CH0_OUT_ARB_WEIGHT_OPT_DIS_CH0 = 0x4000000

	// OUT_INT_RAW_CH0: TX CH0 interrupt raw register
	// Position of OUT_DONE_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DONE_CH0_INT_RAW_Pos = 0x0
	// Bit mask of OUT_DONE_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DONE_CH0_INT_RAW_Msk = 0x1
	// Bit OUT_DONE_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DONE_CH0_INT_RAW = 0x1
	// Position of OUT_EOF_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_EOF_CH0_INT_RAW_Pos = 0x1
	// Bit mask of OUT_EOF_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_EOF_CH0_INT_RAW_Msk = 0x2
	// Bit OUT_EOF_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUT_EOF_CH0_INT_RAW = 0x2
	// Position of OUT_DSCR_ERR_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DSCR_ERR_CH0_INT_RAW_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DSCR_ERR_CH0_INT_RAW_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DSCR_ERR_CH0_INT_RAW = 0x4
	// Position of OUT_TOTAL_EOF_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH0_INT_RAW_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH0_INT_RAW_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUT_TOTAL_EOF_CH0_INT_RAW = 0x8
	// Position of OUTFIFO_OVF_L1_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_OVF_L1_CH0_INT_RAW_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_OVF_L1_CH0_INT_RAW_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_OVF_L1_CH0_INT_RAW = 0x10
	// Position of OUTFIFO_UDF_L1_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_UDF_L1_CH0_INT_RAW_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_UDF_L1_CH0_INT_RAW_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_UDF_L1_CH0_INT_RAW = 0x20
	// Position of OUTFIFO_OVF_L2_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_OVF_L2_CH0_INT_RAW_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_OVF_L2_CH0_INT_RAW_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_OVF_L2_CH0_INT_RAW = 0x40
	// Position of OUTFIFO_UDF_L2_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_UDF_L2_CH0_INT_RAW_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_UDF_L2_CH0_INT_RAW_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUTFIFO_UDF_L2_CH0_INT_RAW = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DSCR_TASK_OVF_CH0_INT_RAW_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH0_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DSCR_TASK_OVF_CH0_INT_RAW_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH0_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH0_OUT_DSCR_TASK_OVF_CH0_INT_RAW = 0x100

	// OUT_INT_ENA_CH0: TX CH0 interrupt ena register
	// Position of OUT_DONE_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DONE_CH0_INT_ENA_Pos = 0x0
	// Bit mask of OUT_DONE_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DONE_CH0_INT_ENA_Msk = 0x1
	// Bit OUT_DONE_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DONE_CH0_INT_ENA = 0x1
	// Position of OUT_EOF_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_EOF_CH0_INT_ENA_Pos = 0x1
	// Bit mask of OUT_EOF_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_EOF_CH0_INT_ENA_Msk = 0x2
	// Bit OUT_EOF_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUT_EOF_CH0_INT_ENA = 0x2
	// Position of OUT_DSCR_ERR_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DSCR_ERR_CH0_INT_ENA_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DSCR_ERR_CH0_INT_ENA_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DSCR_ERR_CH0_INT_ENA = 0x4
	// Position of OUT_TOTAL_EOF_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH0_INT_ENA_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH0_INT_ENA_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUT_TOTAL_EOF_CH0_INT_ENA = 0x8
	// Position of OUTFIFO_OVF_L1_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_OVF_L1_CH0_INT_ENA_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_OVF_L1_CH0_INT_ENA_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_OVF_L1_CH0_INT_ENA = 0x10
	// Position of OUTFIFO_UDF_L1_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_UDF_L1_CH0_INT_ENA_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_UDF_L1_CH0_INT_ENA_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_UDF_L1_CH0_INT_ENA = 0x20
	// Position of OUTFIFO_OVF_L2_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_OVF_L2_CH0_INT_ENA_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_OVF_L2_CH0_INT_ENA_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_OVF_L2_CH0_INT_ENA = 0x40
	// Position of OUTFIFO_UDF_L2_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_UDF_L2_CH0_INT_ENA_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_UDF_L2_CH0_INT_ENA_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUTFIFO_UDF_L2_CH0_INT_ENA = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ENA_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH0_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ENA_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH0_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ENA = 0x100

	// OUT_INT_ST_CH0: TX CH0 interrupt st register
	// Position of OUT_DONE_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_DONE_CH0_INT_ST_Pos = 0x0
	// Bit mask of OUT_DONE_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_DONE_CH0_INT_ST_Msk = 0x1
	// Bit OUT_DONE_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUT_DONE_CH0_INT_ST = 0x1
	// Position of OUT_EOF_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_EOF_CH0_INT_ST_Pos = 0x1
	// Bit mask of OUT_EOF_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_EOF_CH0_INT_ST_Msk = 0x2
	// Bit OUT_EOF_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUT_EOF_CH0_INT_ST = 0x2
	// Position of OUT_DSCR_ERR_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_DSCR_ERR_CH0_INT_ST_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_DSCR_ERR_CH0_INT_ST_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUT_DSCR_ERR_CH0_INT_ST = 0x4
	// Position of OUT_TOTAL_EOF_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_TOTAL_EOF_CH0_INT_ST_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_TOTAL_EOF_CH0_INT_ST_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUT_TOTAL_EOF_CH0_INT_ST = 0x8
	// Position of OUTFIFO_OVF_L1_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_OVF_L1_CH0_INT_ST_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_OVF_L1_CH0_INT_ST_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_OVF_L1_CH0_INT_ST = 0x10
	// Position of OUTFIFO_UDF_L1_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_UDF_L1_CH0_INT_ST_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_UDF_L1_CH0_INT_ST_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_UDF_L1_CH0_INT_ST = 0x20
	// Position of OUTFIFO_OVF_L2_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_OVF_L2_CH0_INT_ST_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_OVF_L2_CH0_INT_ST_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_OVF_L2_CH0_INT_ST = 0x40
	// Position of OUTFIFO_UDF_L2_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_UDF_L2_CH0_INT_ST_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_UDF_L2_CH0_INT_ST_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUTFIFO_UDF_L2_CH0_INT_ST = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ST_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH0_INT_ST field.
	H264_DMA_OUT_INT_ST_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ST_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH0_INT_ST.
	H264_DMA_OUT_INT_ST_CH0_OUT_DSCR_TASK_OVF_CH0_INT_ST = 0x100

	// OUT_INT_CLR_CH0: TX CH0 interrupt clr register
	// Position of OUT_DONE_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DONE_CH0_INT_CLR_Pos = 0x0
	// Bit mask of OUT_DONE_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DONE_CH0_INT_CLR_Msk = 0x1
	// Bit OUT_DONE_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DONE_CH0_INT_CLR = 0x1
	// Position of OUT_EOF_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_EOF_CH0_INT_CLR_Pos = 0x1
	// Bit mask of OUT_EOF_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_EOF_CH0_INT_CLR_Msk = 0x2
	// Bit OUT_EOF_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUT_EOF_CH0_INT_CLR = 0x2
	// Position of OUT_DSCR_ERR_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DSCR_ERR_CH0_INT_CLR_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DSCR_ERR_CH0_INT_CLR_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DSCR_ERR_CH0_INT_CLR = 0x4
	// Position of OUT_TOTAL_EOF_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH0_INT_CLR_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH0_INT_CLR_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUT_TOTAL_EOF_CH0_INT_CLR = 0x8
	// Position of OUTFIFO_OVF_L1_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_OVF_L1_CH0_INT_CLR_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_OVF_L1_CH0_INT_CLR_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_OVF_L1_CH0_INT_CLR = 0x10
	// Position of OUTFIFO_UDF_L1_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_UDF_L1_CH0_INT_CLR_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_UDF_L1_CH0_INT_CLR_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_UDF_L1_CH0_INT_CLR = 0x20
	// Position of OUTFIFO_OVF_L2_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_OVF_L2_CH0_INT_CLR_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_OVF_L2_CH0_INT_CLR_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_OVF_L2_CH0_INT_CLR = 0x40
	// Position of OUTFIFO_UDF_L2_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_UDF_L2_CH0_INT_CLR_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_UDF_L2_CH0_INT_CLR_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUTFIFO_UDF_L2_CH0_INT_CLR = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DSCR_TASK_OVF_CH0_INT_CLR_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH0_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DSCR_TASK_OVF_CH0_INT_CLR_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH0_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH0_OUT_DSCR_TASK_OVF_CH0_INT_CLR = 0x100

	// OUTFIFO_STATUS_CH0: TX CH0 outfifo status register
	// Position of OUTFIFO_FULL_L2_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2_CH0_Pos = 0x0
	// Bit mask of OUTFIFO_FULL_L2_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2_CH0_Msk = 0x1
	// Bit OUTFIFO_FULL_L2_CH0.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L2_CH0 = 0x1
	// Position of OUTFIFO_EMPTY_L2_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2_CH0_Pos = 0x1
	// Bit mask of OUTFIFO_EMPTY_L2_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2_CH0_Msk = 0x2
	// Bit OUTFIFO_EMPTY_L2_CH0.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L2_CH0 = 0x2
	// Position of OUTFIFO_CNT_L2_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2_CH0_Pos = 0x2
	// Bit mask of OUTFIFO_CNT_L2_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_L2_CH0_Msk = 0x3c
	// Position of OUTFIFO_FULL_L1_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1_CH0_Pos = 0x6
	// Bit mask of OUTFIFO_FULL_L1_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1_CH0_Msk = 0x40
	// Bit OUTFIFO_FULL_L1_CH0.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L1_CH0 = 0x40
	// Position of OUTFIFO_EMPTY_L1_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1_CH0_Pos = 0x7
	// Bit mask of OUTFIFO_EMPTY_L1_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1_CH0_Msk = 0x80
	// Bit OUTFIFO_EMPTY_L1_CH0.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L1_CH0 = 0x80
	// Position of OUTFIFO_CNT_L1_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1_CH0_Pos = 0x8
	// Bit mask of OUTFIFO_CNT_L1_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_L1_CH0_Msk = 0x1f00
	// Position of OUTFIFO_FULL_L3_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3_CH0_Pos = 0x10
	// Bit mask of OUTFIFO_FULL_L3_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3_CH0_Msk = 0x10000
	// Bit OUTFIFO_FULL_L3_CH0.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_FULL_L3_CH0 = 0x10000
	// Position of OUTFIFO_EMPTY_L3_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3_CH0_Pos = 0x11
	// Bit mask of OUTFIFO_EMPTY_L3_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3_CH0_Msk = 0x20000
	// Bit OUTFIFO_EMPTY_L3_CH0.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_EMPTY_L3_CH0 = 0x20000
	// Position of OUTFIFO_CNT_L3_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3_CH0_Pos = 0x12
	// Bit mask of OUTFIFO_CNT_L3_CH0 field.
	H264_DMA_OUTFIFO_STATUS_CH0_OUTFIFO_CNT_L3_CH0_Msk = 0xc0000

	// OUT_PUSH_CH0: TX CH0 outfifo push register
	// Position of OUTFIFO_WDATA_CH0 field.
	H264_DMA_OUT_PUSH_CH0_OUTFIFO_WDATA_CH0_Pos = 0x0
	// Bit mask of OUTFIFO_WDATA_CH0 field.
	H264_DMA_OUT_PUSH_CH0_OUTFIFO_WDATA_CH0_Msk = 0x3ff
	// Position of OUTFIFO_PUSH_CH0 field.
	H264_DMA_OUT_PUSH_CH0_OUTFIFO_PUSH_CH0_Pos = 0xa
	// Bit mask of OUTFIFO_PUSH_CH0 field.
	H264_DMA_OUT_PUSH_CH0_OUTFIFO_PUSH_CH0_Msk = 0x400
	// Bit OUTFIFO_PUSH_CH0.
	H264_DMA_OUT_PUSH_CH0_OUTFIFO_PUSH_CH0 = 0x400

	// OUT_LINK_CONF_CH0: TX CH0 out_link dscr ctrl register
	// Position of OUTLINK_STOP_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_STOP_CH0_Pos = 0x14
	// Bit mask of OUTLINK_STOP_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_STOP_CH0_Msk = 0x100000
	// Bit OUTLINK_STOP_CH0.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_STOP_CH0 = 0x100000
	// Position of OUTLINK_START_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_START_CH0_Pos = 0x15
	// Bit mask of OUTLINK_START_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_START_CH0_Msk = 0x200000
	// Bit OUTLINK_START_CH0.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_START_CH0 = 0x200000
	// Position of OUTLINK_RESTART_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_RESTART_CH0_Pos = 0x16
	// Bit mask of OUTLINK_RESTART_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_RESTART_CH0_Msk = 0x400000
	// Bit OUTLINK_RESTART_CH0.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_RESTART_CH0 = 0x400000
	// Position of OUTLINK_PARK_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_PARK_CH0_Pos = 0x17
	// Bit mask of OUTLINK_PARK_CH0 field.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_PARK_CH0_Msk = 0x800000
	// Bit OUTLINK_PARK_CH0.
	H264_DMA_OUT_LINK_CONF_CH0_OUTLINK_PARK_CH0 = 0x800000

	// OUT_LINK_ADDR_CH0: TX CH0 out_link dscr addr register
	// Position of OUTLINK_ADDR_CH0 field.
	H264_DMA_OUT_LINK_ADDR_CH0_OUTLINK_ADDR_CH0_Pos = 0x0
	// Bit mask of OUTLINK_ADDR_CH0 field.
	H264_DMA_OUT_LINK_ADDR_CH0_OUTLINK_ADDR_CH0_Msk = 0xffffffff

	// OUT_STATE_CH0: TX CH0 state register
	// Position of OUTLINK_DSCR_ADDR_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH0_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_ADDR_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUTLINK_DSCR_ADDR_CH0_Msk = 0x3ffff
	// Position of OUT_DSCR_STATE_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUT_DSCR_STATE_CH0_Pos = 0x12
	// Bit mask of OUT_DSCR_STATE_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUT_DSCR_STATE_CH0_Msk = 0xc0000
	// Position of OUT_STATE_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUT_STATE_CH0_Pos = 0x14
	// Bit mask of OUT_STATE_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUT_STATE_CH0_Msk = 0xf00000
	// Position of OUT_RESET_AVAIL_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUT_RESET_AVAIL_CH0_Pos = 0x18
	// Bit mask of OUT_RESET_AVAIL_CH0 field.
	H264_DMA_OUT_STATE_CH0_OUT_RESET_AVAIL_CH0_Msk = 0x1000000
	// Bit OUT_RESET_AVAIL_CH0.
	H264_DMA_OUT_STATE_CH0_OUT_RESET_AVAIL_CH0 = 0x1000000

	// OUT_EOF_DES_ADDR_CH0: TX CH0 eof des addr register
	// Position of OUT_EOF_DES_ADDR_CH0 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH0_OUT_EOF_DES_ADDR_CH0_Pos = 0x0
	// Bit mask of OUT_EOF_DES_ADDR_CH0 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH0_OUT_EOF_DES_ADDR_CH0_Msk = 0xffffffff

	// OUT_DSCR_CH0: TX CH0 next dscr addr register
	// Position of OUTLINK_DSCR_CH0 field.
	H264_DMA_OUT_DSCR_CH0_OUTLINK_DSCR_CH0_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_CH0 field.
	H264_DMA_OUT_DSCR_CH0_OUTLINK_DSCR_CH0_Msk = 0xffffffff

	// OUT_DSCR_BF0_CH0: TX CH0 last dscr addr register
	// Position of OUTLINK_DSCR_BF0_CH0 field.
	H264_DMA_OUT_DSCR_BF0_CH0_OUTLINK_DSCR_BF0_CH0_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF0_CH0 field.
	H264_DMA_OUT_DSCR_BF0_CH0_OUTLINK_DSCR_BF0_CH0_Msk = 0xffffffff

	// OUT_DSCR_BF1_CH0: TX CH0 second-to-last dscr addr register
	// Position of OUTLINK_DSCR_BF1_CH0 field.
	H264_DMA_OUT_DSCR_BF1_CH0_OUTLINK_DSCR_BF1_CH0_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF1_CH0 field.
	H264_DMA_OUT_DSCR_BF1_CH0_OUTLINK_DSCR_BF1_CH0_Msk = 0xffffffff

	// OUT_ARB_CH0: TX CH0 arb register
	// Position of OUT_ARB_TOKEN_NUM_CH0 field.
	H264_DMA_OUT_ARB_CH0_OUT_ARB_TOKEN_NUM_CH0_Pos = 0x0
	// Bit mask of OUT_ARB_TOKEN_NUM_CH0 field.
	H264_DMA_OUT_ARB_CH0_OUT_ARB_TOKEN_NUM_CH0_Msk = 0xf
	// Position of EXTER_OUT_ARB_PRIORITY_CH0 field.
	H264_DMA_OUT_ARB_CH0_EXTER_OUT_ARB_PRIORITY_CH0_Pos = 0x4
	// Bit mask of EXTER_OUT_ARB_PRIORITY_CH0 field.
	H264_DMA_OUT_ARB_CH0_EXTER_OUT_ARB_PRIORITY_CH0_Msk = 0x30

	// OUT_RO_STATUS_CH0: TX CH0 reorder status register
	// Position of OUTFIFO_RO_CNT_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUTFIFO_RO_CNT_CH0_Pos = 0x0
	// Bit mask of OUTFIFO_RO_CNT_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUTFIFO_RO_CNT_CH0_Msk = 0x3
	// Position of OUT_RO_WR_STATE_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_RO_WR_STATE_CH0_Pos = 0x6
	// Bit mask of OUT_RO_WR_STATE_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_RO_WR_STATE_CH0_Msk = 0xc0
	// Position of OUT_RO_RD_STATE_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_RO_RD_STATE_CH0_Pos = 0x8
	// Bit mask of OUT_RO_RD_STATE_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_RO_RD_STATE_CH0_Msk = 0x300
	// Position of OUT_PIXEL_BYTE_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_PIXEL_BYTE_CH0_Pos = 0xa
	// Bit mask of OUT_PIXEL_BYTE_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_PIXEL_BYTE_CH0_Msk = 0x3c00
	// Position of OUT_BURST_BLOCK_NUM_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_BURST_BLOCK_NUM_CH0_Pos = 0xe
	// Bit mask of OUT_BURST_BLOCK_NUM_CH0 field.
	H264_DMA_OUT_RO_STATUS_CH0_OUT_BURST_BLOCK_NUM_CH0_Msk = 0x3c000

	// OUT_RO_PD_CONF_CH0: TX CH0 reorder power config register
	// Position of OUT_RO_RAM_FORCE_PD_CH0 field.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PD_CH0_Pos = 0x4
	// Bit mask of OUT_RO_RAM_FORCE_PD_CH0 field.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PD_CH0_Msk = 0x10
	// Bit OUT_RO_RAM_FORCE_PD_CH0.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PD_CH0 = 0x10
	// Position of OUT_RO_RAM_FORCE_PU_CH0 field.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PU_CH0_Pos = 0x5
	// Bit mask of OUT_RO_RAM_FORCE_PU_CH0 field.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PU_CH0_Msk = 0x20
	// Bit OUT_RO_RAM_FORCE_PU_CH0.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_FORCE_PU_CH0 = 0x20
	// Position of OUT_RO_RAM_CLK_FO_CH0 field.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_CLK_FO_CH0_Pos = 0x6
	// Bit mask of OUT_RO_RAM_CLK_FO_CH0 field.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_CLK_FO_CH0_Msk = 0x40
	// Bit OUT_RO_RAM_CLK_FO_CH0.
	H264_DMA_OUT_RO_PD_CONF_CH0_OUT_RO_RAM_CLK_FO_CH0 = 0x40

	// OUT_MODE_ENABLE_CH0: tx CH0 mode enable register
	// Position of OUT_TEST_MODE_ENABLE_CH0 field.
	H264_DMA_OUT_MODE_ENABLE_CH0_OUT_TEST_MODE_ENABLE_CH0_Pos = 0x0
	// Bit mask of OUT_TEST_MODE_ENABLE_CH0 field.
	H264_DMA_OUT_MODE_ENABLE_CH0_OUT_TEST_MODE_ENABLE_CH0_Msk = 0x1
	// Bit OUT_TEST_MODE_ENABLE_CH0.
	H264_DMA_OUT_MODE_ENABLE_CH0_OUT_TEST_MODE_ENABLE_CH0 = 0x1

	// OUT_MODE_YUV_CH0: tx CH0 test mode yuv value register
	// Position of OUT_TEST_Y_VALUE_CH0 field.
	H264_DMA_OUT_MODE_YUV_CH0_OUT_TEST_Y_VALUE_CH0_Pos = 0x0
	// Bit mask of OUT_TEST_Y_VALUE_CH0 field.
	H264_DMA_OUT_MODE_YUV_CH0_OUT_TEST_Y_VALUE_CH0_Msk = 0xff
	// Position of OUT_TEST_U_VALUE_CH0 field.
	H264_DMA_OUT_MODE_YUV_CH0_OUT_TEST_U_VALUE_CH0_Pos = 0x8
	// Bit mask of OUT_TEST_U_VALUE_CH0 field.
	H264_DMA_OUT_MODE_YUV_CH0_OUT_TEST_U_VALUE_CH0_Msk = 0xff00
	// Position of OUT_TEST_V_VALUE_CH0 field.
	H264_DMA_OUT_MODE_YUV_CH0_OUT_TEST_V_VALUE_CH0_Pos = 0x10
	// Bit mask of OUT_TEST_V_VALUE_CH0 field.
	H264_DMA_OUT_MODE_YUV_CH0_OUT_TEST_V_VALUE_CH0_Msk = 0xff0000

	// OUT_ETM_CONF_CH0: TX CH0 ETM config register
	// Position of OUT_ETM_EN_CH0 field.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_ETM_EN_CH0_Pos = 0x0
	// Bit mask of OUT_ETM_EN_CH0 field.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_ETM_EN_CH0_Msk = 0x1
	// Bit OUT_ETM_EN_CH0.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_ETM_EN_CH0 = 0x1
	// Position of OUT_ETM_LOOP_EN_CH0 field.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_ETM_LOOP_EN_CH0_Pos = 0x1
	// Bit mask of OUT_ETM_LOOP_EN_CH0 field.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_ETM_LOOP_EN_CH0_Msk = 0x2
	// Bit OUT_ETM_LOOP_EN_CH0.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_ETM_LOOP_EN_CH0 = 0x2
	// Position of OUT_DSCR_TASK_MAK_CH0 field.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_DSCR_TASK_MAK_CH0_Pos = 0x2
	// Bit mask of OUT_DSCR_TASK_MAK_CH0 field.
	H264_DMA_OUT_ETM_CONF_CH0_OUT_DSCR_TASK_MAK_CH0_Msk = 0xc

	// OUT_BUF_LEN_CH0: tx CH0 buf len register
	// Position of OUT_CMDFIFO_BUF_LEN_HB_CH0 field.
	H264_DMA_OUT_BUF_LEN_CH0_OUT_CMDFIFO_BUF_LEN_HB_CH0_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_BUF_LEN_HB_CH0 field.
	H264_DMA_OUT_BUF_LEN_CH0_OUT_CMDFIFO_BUF_LEN_HB_CH0_Msk = 0x1fff

	// OUT_FIFO_BCNT_CH0: tx CH0 fifo byte cnt register
	// Position of OUT_CMDFIFO_OUTFIFO_BCNT_CH0 field.
	H264_DMA_OUT_FIFO_BCNT_CH0_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_OUTFIFO_BCNT_CH0 field.
	H264_DMA_OUT_FIFO_BCNT_CH0_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_Msk = 0x3ff

	// OUT_PUSH_BYTECNT_CH0: tx CH0 push byte cnt register
	// Position of OUT_CMDFIFO_PUSH_BYTECNT_CH0 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH0_OUT_CMDFIFO_PUSH_BYTECNT_CH0_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_PUSH_BYTECNT_CH0 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH0_OUT_CMDFIFO_PUSH_BYTECNT_CH0_Msk = 0xff

	// OUT_XADDR_CH0: tx CH0 xaddr register
	// Position of OUT_CMDFIFO_XADDR_CH0 field.
	H264_DMA_OUT_XADDR_CH0_OUT_CMDFIFO_XADDR_CH0_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_XADDR_CH0 field.
	H264_DMA_OUT_XADDR_CH0_OUT_CMDFIFO_XADDR_CH0_Msk = 0xffffffff

	// OUT_CONF0_CH1: TX CH1 config0 register
	// Position of OUT_AUTO_WRBACK_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1_Pos = 0x0
	// Bit mask of OUT_AUTO_WRBACK_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1_Msk = 0x1
	// Bit OUT_AUTO_WRBACK_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_AUTO_WRBACK_CH1 = 0x1
	// Position of OUT_EOF_MODE_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_EOF_MODE_CH1_Pos = 0x1
	// Bit mask of OUT_EOF_MODE_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_EOF_MODE_CH1_Msk = 0x2
	// Bit OUT_EOF_MODE_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_EOF_MODE_CH1 = 0x2
	// Position of OUTDSCR_BURST_EN_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1_Pos = 0x2
	// Bit mask of OUTDSCR_BURST_EN_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1_Msk = 0x4
	// Bit OUTDSCR_BURST_EN_CH1.
	H264_DMA_OUT_CONF0_CH1_OUTDSCR_BURST_EN_CH1 = 0x4
	// Position of OUT_ECC_AES_EN_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_ECC_AES_EN_CH1_Pos = 0x3
	// Bit mask of OUT_ECC_AES_EN_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_ECC_AES_EN_CH1_Msk = 0x8
	// Bit OUT_ECC_AES_EN_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_ECC_AES_EN_CH1 = 0x8
	// Position of OUT_CHECK_OWNER_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_CHECK_OWNER_CH1_Pos = 0x4
	// Bit mask of OUT_CHECK_OWNER_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_CHECK_OWNER_CH1_Msk = 0x10
	// Bit OUT_CHECK_OWNER_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_CHECK_OWNER_CH1 = 0x10
	// Position of OUT_MEM_BURST_LENGTH_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_MEM_BURST_LENGTH_CH1_Pos = 0x6
	// Bit mask of OUT_MEM_BURST_LENGTH_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_MEM_BURST_LENGTH_CH1_Msk = 0x1c0
	// Position of OUT_PAGE_BOUND_EN_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_PAGE_BOUND_EN_CH1_Pos = 0xc
	// Bit mask of OUT_PAGE_BOUND_EN_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_PAGE_BOUND_EN_CH1_Msk = 0x1000
	// Bit OUT_PAGE_BOUND_EN_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_PAGE_BOUND_EN_CH1 = 0x1000
	// Position of OUT_RST_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_RST_CH1_Pos = 0x18
	// Bit mask of OUT_RST_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_RST_CH1_Msk = 0x1000000
	// Bit OUT_RST_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_RST_CH1 = 0x1000000
	// Position of OUT_CMD_DISABLE_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_CMD_DISABLE_CH1_Pos = 0x19
	// Bit mask of OUT_CMD_DISABLE_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_CMD_DISABLE_CH1_Msk = 0x2000000
	// Bit OUT_CMD_DISABLE_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_CMD_DISABLE_CH1 = 0x2000000
	// Position of OUT_ARB_WEIGHT_OPT_DIS_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_ARB_WEIGHT_OPT_DIS_CH1_Pos = 0x1a
	// Bit mask of OUT_ARB_WEIGHT_OPT_DIS_CH1 field.
	H264_DMA_OUT_CONF0_CH1_OUT_ARB_WEIGHT_OPT_DIS_CH1_Msk = 0x4000000
	// Bit OUT_ARB_WEIGHT_OPT_DIS_CH1.
	H264_DMA_OUT_CONF0_CH1_OUT_ARB_WEIGHT_OPT_DIS_CH1 = 0x4000000

	// OUT_INT_RAW_CH1: TX CH1 interrupt raw register
	// Position of OUT_DONE_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DONE_CH1_INT_RAW_Pos = 0x0
	// Bit mask of OUT_DONE_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DONE_CH1_INT_RAW_Msk = 0x1
	// Bit OUT_DONE_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DONE_CH1_INT_RAW = 0x1
	// Position of OUT_EOF_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_EOF_CH1_INT_RAW_Pos = 0x1
	// Bit mask of OUT_EOF_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_EOF_CH1_INT_RAW_Msk = 0x2
	// Bit OUT_EOF_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUT_EOF_CH1_INT_RAW = 0x2
	// Position of OUT_DSCR_ERR_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DSCR_ERR_CH1_INT_RAW_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DSCR_ERR_CH1_INT_RAW_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DSCR_ERR_CH1_INT_RAW = 0x4
	// Position of OUT_TOTAL_EOF_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH1_INT_RAW_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH1_INT_RAW_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUT_TOTAL_EOF_CH1_INT_RAW = 0x8
	// Position of OUTFIFO_OVF_L1_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_OVF_L1_CH1_INT_RAW_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_OVF_L1_CH1_INT_RAW_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_OVF_L1_CH1_INT_RAW = 0x10
	// Position of OUTFIFO_UDF_L1_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_UDF_L1_CH1_INT_RAW_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_UDF_L1_CH1_INT_RAW_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_UDF_L1_CH1_INT_RAW = 0x20
	// Position of OUTFIFO_OVF_L2_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_OVF_L2_CH1_INT_RAW_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_OVF_L2_CH1_INT_RAW_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_OVF_L2_CH1_INT_RAW = 0x40
	// Position of OUTFIFO_UDF_L2_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_UDF_L2_CH1_INT_RAW_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_UDF_L2_CH1_INT_RAW_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUTFIFO_UDF_L2_CH1_INT_RAW = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DSCR_TASK_OVF_CH1_INT_RAW_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH1_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DSCR_TASK_OVF_CH1_INT_RAW_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH1_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH1_OUT_DSCR_TASK_OVF_CH1_INT_RAW = 0x100

	// OUT_INT_ENA_CH1: TX CH1 interrupt ena register
	// Position of OUT_DONE_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DONE_CH1_INT_ENA_Pos = 0x0
	// Bit mask of OUT_DONE_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DONE_CH1_INT_ENA_Msk = 0x1
	// Bit OUT_DONE_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DONE_CH1_INT_ENA = 0x1
	// Position of OUT_EOF_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_EOF_CH1_INT_ENA_Pos = 0x1
	// Bit mask of OUT_EOF_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_EOF_CH1_INT_ENA_Msk = 0x2
	// Bit OUT_EOF_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUT_EOF_CH1_INT_ENA = 0x2
	// Position of OUT_DSCR_ERR_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DSCR_ERR_CH1_INT_ENA_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DSCR_ERR_CH1_INT_ENA_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DSCR_ERR_CH1_INT_ENA = 0x4
	// Position of OUT_TOTAL_EOF_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH1_INT_ENA_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH1_INT_ENA_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUT_TOTAL_EOF_CH1_INT_ENA = 0x8
	// Position of OUTFIFO_OVF_L1_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_OVF_L1_CH1_INT_ENA_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_OVF_L1_CH1_INT_ENA_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_OVF_L1_CH1_INT_ENA = 0x10
	// Position of OUTFIFO_UDF_L1_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_UDF_L1_CH1_INT_ENA_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_UDF_L1_CH1_INT_ENA_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_UDF_L1_CH1_INT_ENA = 0x20
	// Position of OUTFIFO_OVF_L2_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_OVF_L2_CH1_INT_ENA_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_OVF_L2_CH1_INT_ENA_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_OVF_L2_CH1_INT_ENA = 0x40
	// Position of OUTFIFO_UDF_L2_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_UDF_L2_CH1_INT_ENA_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_UDF_L2_CH1_INT_ENA_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUTFIFO_UDF_L2_CH1_INT_ENA = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ENA_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH1_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ENA_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH1_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ENA = 0x100

	// OUT_INT_ST_CH1: TX CH1 interrupt st register
	// Position of OUT_DONE_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_DONE_CH1_INT_ST_Pos = 0x0
	// Bit mask of OUT_DONE_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_DONE_CH1_INT_ST_Msk = 0x1
	// Bit OUT_DONE_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUT_DONE_CH1_INT_ST = 0x1
	// Position of OUT_EOF_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_EOF_CH1_INT_ST_Pos = 0x1
	// Bit mask of OUT_EOF_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_EOF_CH1_INT_ST_Msk = 0x2
	// Bit OUT_EOF_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUT_EOF_CH1_INT_ST = 0x2
	// Position of OUT_DSCR_ERR_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_DSCR_ERR_CH1_INT_ST_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_DSCR_ERR_CH1_INT_ST_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUT_DSCR_ERR_CH1_INT_ST = 0x4
	// Position of OUT_TOTAL_EOF_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_TOTAL_EOF_CH1_INT_ST_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_TOTAL_EOF_CH1_INT_ST_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUT_TOTAL_EOF_CH1_INT_ST = 0x8
	// Position of OUTFIFO_OVF_L1_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_OVF_L1_CH1_INT_ST_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_OVF_L1_CH1_INT_ST_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_OVF_L1_CH1_INT_ST = 0x10
	// Position of OUTFIFO_UDF_L1_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_UDF_L1_CH1_INT_ST_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_UDF_L1_CH1_INT_ST_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_UDF_L1_CH1_INT_ST = 0x20
	// Position of OUTFIFO_OVF_L2_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_OVF_L2_CH1_INT_ST_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_OVF_L2_CH1_INT_ST_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_OVF_L2_CH1_INT_ST = 0x40
	// Position of OUTFIFO_UDF_L2_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_UDF_L2_CH1_INT_ST_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_UDF_L2_CH1_INT_ST_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUTFIFO_UDF_L2_CH1_INT_ST = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ST_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH1_INT_ST field.
	H264_DMA_OUT_INT_ST_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ST_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH1_INT_ST.
	H264_DMA_OUT_INT_ST_CH1_OUT_DSCR_TASK_OVF_CH1_INT_ST = 0x100

	// OUT_INT_CLR_CH1: TX CH1 interrupt clr register
	// Position of OUT_DONE_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DONE_CH1_INT_CLR_Pos = 0x0
	// Bit mask of OUT_DONE_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DONE_CH1_INT_CLR_Msk = 0x1
	// Bit OUT_DONE_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DONE_CH1_INT_CLR = 0x1
	// Position of OUT_EOF_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_EOF_CH1_INT_CLR_Pos = 0x1
	// Bit mask of OUT_EOF_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_EOF_CH1_INT_CLR_Msk = 0x2
	// Bit OUT_EOF_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUT_EOF_CH1_INT_CLR = 0x2
	// Position of OUT_DSCR_ERR_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DSCR_ERR_CH1_INT_CLR_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DSCR_ERR_CH1_INT_CLR_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DSCR_ERR_CH1_INT_CLR = 0x4
	// Position of OUT_TOTAL_EOF_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH1_INT_CLR_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH1_INT_CLR_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUT_TOTAL_EOF_CH1_INT_CLR = 0x8
	// Position of OUTFIFO_OVF_L1_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_OVF_L1_CH1_INT_CLR_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_OVF_L1_CH1_INT_CLR_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_OVF_L1_CH1_INT_CLR = 0x10
	// Position of OUTFIFO_UDF_L1_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_UDF_L1_CH1_INT_CLR_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_UDF_L1_CH1_INT_CLR_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_UDF_L1_CH1_INT_CLR = 0x20
	// Position of OUTFIFO_OVF_L2_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_OVF_L2_CH1_INT_CLR_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_OVF_L2_CH1_INT_CLR_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_OVF_L2_CH1_INT_CLR = 0x40
	// Position of OUTFIFO_UDF_L2_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_UDF_L2_CH1_INT_CLR_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_UDF_L2_CH1_INT_CLR_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUTFIFO_UDF_L2_CH1_INT_CLR = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DSCR_TASK_OVF_CH1_INT_CLR_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH1_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DSCR_TASK_OVF_CH1_INT_CLR_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH1_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH1_OUT_DSCR_TASK_OVF_CH1_INT_CLR = 0x100

	// OUTFIFO_STATUS_CH1: TX CH1 outfifo status register
	// Position of OUTFIFO_FULL_L2_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2_CH1_Pos = 0x0
	// Bit mask of OUTFIFO_FULL_L2_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2_CH1_Msk = 0x1
	// Bit OUTFIFO_FULL_L2_CH1.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L2_CH1 = 0x1
	// Position of OUTFIFO_EMPTY_L2_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2_CH1_Pos = 0x1
	// Bit mask of OUTFIFO_EMPTY_L2_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2_CH1_Msk = 0x2
	// Bit OUTFIFO_EMPTY_L2_CH1.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L2_CH1 = 0x2
	// Position of OUTFIFO_CNT_L2_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2_CH1_Pos = 0x2
	// Bit mask of OUTFIFO_CNT_L2_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_L2_CH1_Msk = 0x3c
	// Position of OUTFIFO_FULL_L1_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1_CH1_Pos = 0x6
	// Bit mask of OUTFIFO_FULL_L1_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1_CH1_Msk = 0x40
	// Bit OUTFIFO_FULL_L1_CH1.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L1_CH1 = 0x40
	// Position of OUTFIFO_EMPTY_L1_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1_CH1_Pos = 0x7
	// Bit mask of OUTFIFO_EMPTY_L1_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1_CH1_Msk = 0x80
	// Bit OUTFIFO_EMPTY_L1_CH1.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L1_CH1 = 0x80
	// Position of OUTFIFO_CNT_L1_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1_CH1_Pos = 0x8
	// Bit mask of OUTFIFO_CNT_L1_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_L1_CH1_Msk = 0x1f00
	// Position of OUTFIFO_FULL_L3_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3_CH1_Pos = 0x10
	// Bit mask of OUTFIFO_FULL_L3_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3_CH1_Msk = 0x10000
	// Bit OUTFIFO_FULL_L3_CH1.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_FULL_L3_CH1 = 0x10000
	// Position of OUTFIFO_EMPTY_L3_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3_CH1_Pos = 0x11
	// Bit mask of OUTFIFO_EMPTY_L3_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3_CH1_Msk = 0x20000
	// Bit OUTFIFO_EMPTY_L3_CH1.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_EMPTY_L3_CH1 = 0x20000
	// Position of OUTFIFO_CNT_L3_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3_CH1_Pos = 0x12
	// Bit mask of OUTFIFO_CNT_L3_CH1 field.
	H264_DMA_OUTFIFO_STATUS_CH1_OUTFIFO_CNT_L3_CH1_Msk = 0xc0000

	// OUT_PUSH_CH1: TX CH1 outfifo push register
	// Position of OUTFIFO_WDATA_CH1 field.
	H264_DMA_OUT_PUSH_CH1_OUTFIFO_WDATA_CH1_Pos = 0x0
	// Bit mask of OUTFIFO_WDATA_CH1 field.
	H264_DMA_OUT_PUSH_CH1_OUTFIFO_WDATA_CH1_Msk = 0x3ff
	// Position of OUTFIFO_PUSH_CH1 field.
	H264_DMA_OUT_PUSH_CH1_OUTFIFO_PUSH_CH1_Pos = 0xa
	// Bit mask of OUTFIFO_PUSH_CH1 field.
	H264_DMA_OUT_PUSH_CH1_OUTFIFO_PUSH_CH1_Msk = 0x400
	// Bit OUTFIFO_PUSH_CH1.
	H264_DMA_OUT_PUSH_CH1_OUTFIFO_PUSH_CH1 = 0x400

	// OUT_LINK_CONF_CH1: TX CH1 out_link dscr ctrl register
	// Position of OUTLINK_STOP_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_STOP_CH1_Pos = 0x14
	// Bit mask of OUTLINK_STOP_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_STOP_CH1_Msk = 0x100000
	// Bit OUTLINK_STOP_CH1.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_STOP_CH1 = 0x100000
	// Position of OUTLINK_START_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_START_CH1_Pos = 0x15
	// Bit mask of OUTLINK_START_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_START_CH1_Msk = 0x200000
	// Bit OUTLINK_START_CH1.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_START_CH1 = 0x200000
	// Position of OUTLINK_RESTART_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_RESTART_CH1_Pos = 0x16
	// Bit mask of OUTLINK_RESTART_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_RESTART_CH1_Msk = 0x400000
	// Bit OUTLINK_RESTART_CH1.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_RESTART_CH1 = 0x400000
	// Position of OUTLINK_PARK_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_PARK_CH1_Pos = 0x17
	// Bit mask of OUTLINK_PARK_CH1 field.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_PARK_CH1_Msk = 0x800000
	// Bit OUTLINK_PARK_CH1.
	H264_DMA_OUT_LINK_CONF_CH1_OUTLINK_PARK_CH1 = 0x800000

	// OUT_LINK_ADDR_CH1: TX CH1 out_link dscr addr register
	// Position of OUTLINK_ADDR_CH1 field.
	H264_DMA_OUT_LINK_ADDR_CH1_OUTLINK_ADDR_CH1_Pos = 0x0
	// Bit mask of OUTLINK_ADDR_CH1 field.
	H264_DMA_OUT_LINK_ADDR_CH1_OUTLINK_ADDR_CH1_Msk = 0xffffffff

	// OUT_STATE_CH1: TX CH1 state register
	// Position of OUTLINK_DSCR_ADDR_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH1_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_ADDR_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUTLINK_DSCR_ADDR_CH1_Msk = 0x3ffff
	// Position of OUT_DSCR_STATE_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUT_DSCR_STATE_CH1_Pos = 0x12
	// Bit mask of OUT_DSCR_STATE_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUT_DSCR_STATE_CH1_Msk = 0xc0000
	// Position of OUT_STATE_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUT_STATE_CH1_Pos = 0x14
	// Bit mask of OUT_STATE_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUT_STATE_CH1_Msk = 0xf00000
	// Position of OUT_RESET_AVAIL_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUT_RESET_AVAIL_CH1_Pos = 0x18
	// Bit mask of OUT_RESET_AVAIL_CH1 field.
	H264_DMA_OUT_STATE_CH1_OUT_RESET_AVAIL_CH1_Msk = 0x1000000
	// Bit OUT_RESET_AVAIL_CH1.
	H264_DMA_OUT_STATE_CH1_OUT_RESET_AVAIL_CH1 = 0x1000000

	// OUT_EOF_DES_ADDR_CH1: TX CH1 eof des addr register
	// Position of OUT_EOF_DES_ADDR_CH1 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH1_OUT_EOF_DES_ADDR_CH1_Pos = 0x0
	// Bit mask of OUT_EOF_DES_ADDR_CH1 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH1_OUT_EOF_DES_ADDR_CH1_Msk = 0xffffffff

	// OUT_DSCR_CH1: TX CH1 next dscr addr register
	// Position of OUTLINK_DSCR_CH1 field.
	H264_DMA_OUT_DSCR_CH1_OUTLINK_DSCR_CH1_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_CH1 field.
	H264_DMA_OUT_DSCR_CH1_OUTLINK_DSCR_CH1_Msk = 0xffffffff

	// OUT_DSCR_BF0_CH1: TX CH1 last dscr addr register
	// Position of OUTLINK_DSCR_BF0_CH1 field.
	H264_DMA_OUT_DSCR_BF0_CH1_OUTLINK_DSCR_BF0_CH1_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF0_CH1 field.
	H264_DMA_OUT_DSCR_BF0_CH1_OUTLINK_DSCR_BF0_CH1_Msk = 0xffffffff

	// OUT_DSCR_BF1_CH1: TX CH1 second-to-last dscr addr register
	// Position of OUTLINK_DSCR_BF1_CH1 field.
	H264_DMA_OUT_DSCR_BF1_CH1_OUTLINK_DSCR_BF1_CH1_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF1_CH1 field.
	H264_DMA_OUT_DSCR_BF1_CH1_OUTLINK_DSCR_BF1_CH1_Msk = 0xffffffff

	// OUT_ARB_CH1: TX CH1 arb register
	// Position of OUT_ARB_TOKEN_NUM_CH1 field.
	H264_DMA_OUT_ARB_CH1_OUT_ARB_TOKEN_NUM_CH1_Pos = 0x0
	// Bit mask of OUT_ARB_TOKEN_NUM_CH1 field.
	H264_DMA_OUT_ARB_CH1_OUT_ARB_TOKEN_NUM_CH1_Msk = 0xf
	// Position of INTER_OUT_ARB_PRIORITY_CH1 field.
	H264_DMA_OUT_ARB_CH1_INTER_OUT_ARB_PRIORITY_CH1_Pos = 0x6
	// Bit mask of INTER_OUT_ARB_PRIORITY_CH1 field.
	H264_DMA_OUT_ARB_CH1_INTER_OUT_ARB_PRIORITY_CH1_Msk = 0x40
	// Bit INTER_OUT_ARB_PRIORITY_CH1.
	H264_DMA_OUT_ARB_CH1_INTER_OUT_ARB_PRIORITY_CH1 = 0x40

	// OUT_ETM_CONF_CH1: TX CH1 ETM config register
	// Position of OUT_ETM_EN_CH1 field.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_ETM_EN_CH1_Pos = 0x0
	// Bit mask of OUT_ETM_EN_CH1 field.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_ETM_EN_CH1_Msk = 0x1
	// Bit OUT_ETM_EN_CH1.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_ETM_EN_CH1 = 0x1
	// Position of OUT_ETM_LOOP_EN_CH1 field.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_ETM_LOOP_EN_CH1_Pos = 0x1
	// Bit mask of OUT_ETM_LOOP_EN_CH1 field.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_ETM_LOOP_EN_CH1_Msk = 0x2
	// Bit OUT_ETM_LOOP_EN_CH1.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_ETM_LOOP_EN_CH1 = 0x2
	// Position of OUT_DSCR_TASK_MAK_CH1 field.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_DSCR_TASK_MAK_CH1_Pos = 0x2
	// Bit mask of OUT_DSCR_TASK_MAK_CH1 field.
	H264_DMA_OUT_ETM_CONF_CH1_OUT_DSCR_TASK_MAK_CH1_Msk = 0xc

	// OUT_BUF_LEN_CH1: tx CH1 buf len register
	// Position of OUT_CMDFIFO_BUF_LEN_HB_CH1 field.
	H264_DMA_OUT_BUF_LEN_CH1_OUT_CMDFIFO_BUF_LEN_HB_CH1_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_BUF_LEN_HB_CH1 field.
	H264_DMA_OUT_BUF_LEN_CH1_OUT_CMDFIFO_BUF_LEN_HB_CH1_Msk = 0x1fff

	// OUT_FIFO_BCNT_CH1: tx CH1 fifo byte cnt register
	// Position of OUT_CMDFIFO_OUTFIFO_BCNT_CH1 field.
	H264_DMA_OUT_FIFO_BCNT_CH1_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_OUTFIFO_BCNT_CH1 field.
	H264_DMA_OUT_FIFO_BCNT_CH1_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_Msk = 0x3ff

	// OUT_PUSH_BYTECNT_CH1: tx CH1 push byte cnt register
	// Position of OUT_CMDFIFO_PUSH_BYTECNT_CH1 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH1_OUT_CMDFIFO_PUSH_BYTECNT_CH1_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_PUSH_BYTECNT_CH1 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH1_OUT_CMDFIFO_PUSH_BYTECNT_CH1_Msk = 0xff

	// OUT_XADDR_CH1: tx CH1 xaddr register
	// Position of OUT_CMDFIFO_XADDR_CH1 field.
	H264_DMA_OUT_XADDR_CH1_OUT_CMDFIFO_XADDR_CH1_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_XADDR_CH1 field.
	H264_DMA_OUT_XADDR_CH1_OUT_CMDFIFO_XADDR_CH1_Msk = 0xffffffff

	// OUT_CONF0_CH2: TX CH2 config0 register
	// Position of OUT_AUTO_WRBACK_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2_Pos = 0x0
	// Bit mask of OUT_AUTO_WRBACK_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2_Msk = 0x1
	// Bit OUT_AUTO_WRBACK_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_AUTO_WRBACK_CH2 = 0x1
	// Position of OUT_EOF_MODE_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_EOF_MODE_CH2_Pos = 0x1
	// Bit mask of OUT_EOF_MODE_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_EOF_MODE_CH2_Msk = 0x2
	// Bit OUT_EOF_MODE_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_EOF_MODE_CH2 = 0x2
	// Position of OUTDSCR_BURST_EN_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2_Pos = 0x2
	// Bit mask of OUTDSCR_BURST_EN_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2_Msk = 0x4
	// Bit OUTDSCR_BURST_EN_CH2.
	H264_DMA_OUT_CONF0_CH2_OUTDSCR_BURST_EN_CH2 = 0x4
	// Position of OUT_ECC_AES_EN_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_ECC_AES_EN_CH2_Pos = 0x3
	// Bit mask of OUT_ECC_AES_EN_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_ECC_AES_EN_CH2_Msk = 0x8
	// Bit OUT_ECC_AES_EN_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_ECC_AES_EN_CH2 = 0x8
	// Position of OUT_CHECK_OWNER_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_CHECK_OWNER_CH2_Pos = 0x4
	// Bit mask of OUT_CHECK_OWNER_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_CHECK_OWNER_CH2_Msk = 0x10
	// Bit OUT_CHECK_OWNER_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_CHECK_OWNER_CH2 = 0x10
	// Position of OUT_MEM_BURST_LENGTH_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_MEM_BURST_LENGTH_CH2_Pos = 0x6
	// Bit mask of OUT_MEM_BURST_LENGTH_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_MEM_BURST_LENGTH_CH2_Msk = 0x1c0
	// Position of OUT_PAGE_BOUND_EN_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_PAGE_BOUND_EN_CH2_Pos = 0xc
	// Bit mask of OUT_PAGE_BOUND_EN_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_PAGE_BOUND_EN_CH2_Msk = 0x1000
	// Bit OUT_PAGE_BOUND_EN_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_PAGE_BOUND_EN_CH2 = 0x1000
	// Position of OUT_RST_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_RST_CH2_Pos = 0x18
	// Bit mask of OUT_RST_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_RST_CH2_Msk = 0x1000000
	// Bit OUT_RST_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_RST_CH2 = 0x1000000
	// Position of OUT_CMD_DISABLE_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_CMD_DISABLE_CH2_Pos = 0x19
	// Bit mask of OUT_CMD_DISABLE_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_CMD_DISABLE_CH2_Msk = 0x2000000
	// Bit OUT_CMD_DISABLE_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_CMD_DISABLE_CH2 = 0x2000000
	// Position of OUT_ARB_WEIGHT_OPT_DIS_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_ARB_WEIGHT_OPT_DIS_CH2_Pos = 0x1a
	// Bit mask of OUT_ARB_WEIGHT_OPT_DIS_CH2 field.
	H264_DMA_OUT_CONF0_CH2_OUT_ARB_WEIGHT_OPT_DIS_CH2_Msk = 0x4000000
	// Bit OUT_ARB_WEIGHT_OPT_DIS_CH2.
	H264_DMA_OUT_CONF0_CH2_OUT_ARB_WEIGHT_OPT_DIS_CH2 = 0x4000000

	// OUT_INT_RAW_CH2: TX CH2 interrupt raw register
	// Position of OUT_DONE_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DONE_CH2_INT_RAW_Pos = 0x0
	// Bit mask of OUT_DONE_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DONE_CH2_INT_RAW_Msk = 0x1
	// Bit OUT_DONE_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DONE_CH2_INT_RAW = 0x1
	// Position of OUT_EOF_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_EOF_CH2_INT_RAW_Pos = 0x1
	// Bit mask of OUT_EOF_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_EOF_CH2_INT_RAW_Msk = 0x2
	// Bit OUT_EOF_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUT_EOF_CH2_INT_RAW = 0x2
	// Position of OUT_DSCR_ERR_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DSCR_ERR_CH2_INT_RAW_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DSCR_ERR_CH2_INT_RAW_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DSCR_ERR_CH2_INT_RAW = 0x4
	// Position of OUT_TOTAL_EOF_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH2_INT_RAW_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH2_INT_RAW_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUT_TOTAL_EOF_CH2_INT_RAW = 0x8
	// Position of OUTFIFO_OVF_L1_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_OVF_L1_CH2_INT_RAW_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_OVF_L1_CH2_INT_RAW_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_OVF_L1_CH2_INT_RAW = 0x10
	// Position of OUTFIFO_UDF_L1_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_UDF_L1_CH2_INT_RAW_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_UDF_L1_CH2_INT_RAW_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_UDF_L1_CH2_INT_RAW = 0x20
	// Position of OUTFIFO_OVF_L2_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_OVF_L2_CH2_INT_RAW_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_OVF_L2_CH2_INT_RAW_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_OVF_L2_CH2_INT_RAW = 0x40
	// Position of OUTFIFO_UDF_L2_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_UDF_L2_CH2_INT_RAW_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_UDF_L2_CH2_INT_RAW_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUTFIFO_UDF_L2_CH2_INT_RAW = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DSCR_TASK_OVF_CH2_INT_RAW_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH2_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DSCR_TASK_OVF_CH2_INT_RAW_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH2_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH2_OUT_DSCR_TASK_OVF_CH2_INT_RAW = 0x100

	// OUT_INT_ENA_CH2: TX CH2 interrupt ena register
	// Position of OUT_DONE_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DONE_CH2_INT_ENA_Pos = 0x0
	// Bit mask of OUT_DONE_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DONE_CH2_INT_ENA_Msk = 0x1
	// Bit OUT_DONE_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DONE_CH2_INT_ENA = 0x1
	// Position of OUT_EOF_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_EOF_CH2_INT_ENA_Pos = 0x1
	// Bit mask of OUT_EOF_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_EOF_CH2_INT_ENA_Msk = 0x2
	// Bit OUT_EOF_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUT_EOF_CH2_INT_ENA = 0x2
	// Position of OUT_DSCR_ERR_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DSCR_ERR_CH2_INT_ENA_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DSCR_ERR_CH2_INT_ENA_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DSCR_ERR_CH2_INT_ENA = 0x4
	// Position of OUT_TOTAL_EOF_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH2_INT_ENA_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH2_INT_ENA_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUT_TOTAL_EOF_CH2_INT_ENA = 0x8
	// Position of OUTFIFO_OVF_L1_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_OVF_L1_CH2_INT_ENA_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_OVF_L1_CH2_INT_ENA_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_OVF_L1_CH2_INT_ENA = 0x10
	// Position of OUTFIFO_UDF_L1_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_UDF_L1_CH2_INT_ENA_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_UDF_L1_CH2_INT_ENA_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_UDF_L1_CH2_INT_ENA = 0x20
	// Position of OUTFIFO_OVF_L2_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_OVF_L2_CH2_INT_ENA_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_OVF_L2_CH2_INT_ENA_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_OVF_L2_CH2_INT_ENA = 0x40
	// Position of OUTFIFO_UDF_L2_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_UDF_L2_CH2_INT_ENA_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_UDF_L2_CH2_INT_ENA_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUTFIFO_UDF_L2_CH2_INT_ENA = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ENA_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH2_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ENA_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH2_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ENA = 0x100

	// OUT_INT_ST_CH2: TX CH2 interrupt st register
	// Position of OUT_DONE_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_DONE_CH2_INT_ST_Pos = 0x0
	// Bit mask of OUT_DONE_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_DONE_CH2_INT_ST_Msk = 0x1
	// Bit OUT_DONE_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUT_DONE_CH2_INT_ST = 0x1
	// Position of OUT_EOF_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_EOF_CH2_INT_ST_Pos = 0x1
	// Bit mask of OUT_EOF_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_EOF_CH2_INT_ST_Msk = 0x2
	// Bit OUT_EOF_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUT_EOF_CH2_INT_ST = 0x2
	// Position of OUT_DSCR_ERR_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_DSCR_ERR_CH2_INT_ST_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_DSCR_ERR_CH2_INT_ST_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUT_DSCR_ERR_CH2_INT_ST = 0x4
	// Position of OUT_TOTAL_EOF_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_TOTAL_EOF_CH2_INT_ST_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_TOTAL_EOF_CH2_INT_ST_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUT_TOTAL_EOF_CH2_INT_ST = 0x8
	// Position of OUTFIFO_OVF_L1_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_OVF_L1_CH2_INT_ST_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_OVF_L1_CH2_INT_ST_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_OVF_L1_CH2_INT_ST = 0x10
	// Position of OUTFIFO_UDF_L1_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_UDF_L1_CH2_INT_ST_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_UDF_L1_CH2_INT_ST_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_UDF_L1_CH2_INT_ST = 0x20
	// Position of OUTFIFO_OVF_L2_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_OVF_L2_CH2_INT_ST_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_OVF_L2_CH2_INT_ST_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_OVF_L2_CH2_INT_ST = 0x40
	// Position of OUTFIFO_UDF_L2_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_UDF_L2_CH2_INT_ST_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_UDF_L2_CH2_INT_ST_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUTFIFO_UDF_L2_CH2_INT_ST = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ST_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH2_INT_ST field.
	H264_DMA_OUT_INT_ST_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ST_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH2_INT_ST.
	H264_DMA_OUT_INT_ST_CH2_OUT_DSCR_TASK_OVF_CH2_INT_ST = 0x100

	// OUT_INT_CLR_CH2: TX CH2 interrupt clr register
	// Position of OUT_DONE_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DONE_CH2_INT_CLR_Pos = 0x0
	// Bit mask of OUT_DONE_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DONE_CH2_INT_CLR_Msk = 0x1
	// Bit OUT_DONE_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DONE_CH2_INT_CLR = 0x1
	// Position of OUT_EOF_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_EOF_CH2_INT_CLR_Pos = 0x1
	// Bit mask of OUT_EOF_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_EOF_CH2_INT_CLR_Msk = 0x2
	// Bit OUT_EOF_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUT_EOF_CH2_INT_CLR = 0x2
	// Position of OUT_DSCR_ERR_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DSCR_ERR_CH2_INT_CLR_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DSCR_ERR_CH2_INT_CLR_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DSCR_ERR_CH2_INT_CLR = 0x4
	// Position of OUT_TOTAL_EOF_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH2_INT_CLR_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH2_INT_CLR_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUT_TOTAL_EOF_CH2_INT_CLR = 0x8
	// Position of OUTFIFO_OVF_L1_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_OVF_L1_CH2_INT_CLR_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_OVF_L1_CH2_INT_CLR_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_OVF_L1_CH2_INT_CLR = 0x10
	// Position of OUTFIFO_UDF_L1_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_UDF_L1_CH2_INT_CLR_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_UDF_L1_CH2_INT_CLR_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_UDF_L1_CH2_INT_CLR = 0x20
	// Position of OUTFIFO_OVF_L2_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_OVF_L2_CH2_INT_CLR_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_OVF_L2_CH2_INT_CLR_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_OVF_L2_CH2_INT_CLR = 0x40
	// Position of OUTFIFO_UDF_L2_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_UDF_L2_CH2_INT_CLR_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_UDF_L2_CH2_INT_CLR_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUTFIFO_UDF_L2_CH2_INT_CLR = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DSCR_TASK_OVF_CH2_INT_CLR_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH2_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DSCR_TASK_OVF_CH2_INT_CLR_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH2_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH2_OUT_DSCR_TASK_OVF_CH2_INT_CLR = 0x100

	// OUTFIFO_STATUS_CH2: TX CH2 outfifo status register
	// Position of OUTFIFO_FULL_L2_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2_CH2_Pos = 0x0
	// Bit mask of OUTFIFO_FULL_L2_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2_CH2_Msk = 0x1
	// Bit OUTFIFO_FULL_L2_CH2.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L2_CH2 = 0x1
	// Position of OUTFIFO_EMPTY_L2_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2_CH2_Pos = 0x1
	// Bit mask of OUTFIFO_EMPTY_L2_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2_CH2_Msk = 0x2
	// Bit OUTFIFO_EMPTY_L2_CH2.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L2_CH2 = 0x2
	// Position of OUTFIFO_CNT_L2_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2_CH2_Pos = 0x2
	// Bit mask of OUTFIFO_CNT_L2_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_L2_CH2_Msk = 0x3c
	// Position of OUTFIFO_FULL_L1_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1_CH2_Pos = 0x6
	// Bit mask of OUTFIFO_FULL_L1_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1_CH2_Msk = 0x40
	// Bit OUTFIFO_FULL_L1_CH2.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L1_CH2 = 0x40
	// Position of OUTFIFO_EMPTY_L1_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1_CH2_Pos = 0x7
	// Bit mask of OUTFIFO_EMPTY_L1_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1_CH2_Msk = 0x80
	// Bit OUTFIFO_EMPTY_L1_CH2.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L1_CH2 = 0x80
	// Position of OUTFIFO_CNT_L1_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1_CH2_Pos = 0x8
	// Bit mask of OUTFIFO_CNT_L1_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_L1_CH2_Msk = 0x1f00
	// Position of OUTFIFO_FULL_L3_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3_CH2_Pos = 0x10
	// Bit mask of OUTFIFO_FULL_L3_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3_CH2_Msk = 0x10000
	// Bit OUTFIFO_FULL_L3_CH2.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_FULL_L3_CH2 = 0x10000
	// Position of OUTFIFO_EMPTY_L3_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3_CH2_Pos = 0x11
	// Bit mask of OUTFIFO_EMPTY_L3_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3_CH2_Msk = 0x20000
	// Bit OUTFIFO_EMPTY_L3_CH2.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_EMPTY_L3_CH2 = 0x20000
	// Position of OUTFIFO_CNT_L3_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3_CH2_Pos = 0x12
	// Bit mask of OUTFIFO_CNT_L3_CH2 field.
	H264_DMA_OUTFIFO_STATUS_CH2_OUTFIFO_CNT_L3_CH2_Msk = 0xc0000

	// OUT_PUSH_CH2: TX CH2 outfifo push register
	// Position of OUTFIFO_WDATA_CH2 field.
	H264_DMA_OUT_PUSH_CH2_OUTFIFO_WDATA_CH2_Pos = 0x0
	// Bit mask of OUTFIFO_WDATA_CH2 field.
	H264_DMA_OUT_PUSH_CH2_OUTFIFO_WDATA_CH2_Msk = 0x3ff
	// Position of OUTFIFO_PUSH_CH2 field.
	H264_DMA_OUT_PUSH_CH2_OUTFIFO_PUSH_CH2_Pos = 0xa
	// Bit mask of OUTFIFO_PUSH_CH2 field.
	H264_DMA_OUT_PUSH_CH2_OUTFIFO_PUSH_CH2_Msk = 0x400
	// Bit OUTFIFO_PUSH_CH2.
	H264_DMA_OUT_PUSH_CH2_OUTFIFO_PUSH_CH2 = 0x400

	// OUT_LINK_CONF_CH2: TX CH2 out_link dscr ctrl register
	// Position of OUTLINK_STOP_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_STOP_CH2_Pos = 0x14
	// Bit mask of OUTLINK_STOP_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_STOP_CH2_Msk = 0x100000
	// Bit OUTLINK_STOP_CH2.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_STOP_CH2 = 0x100000
	// Position of OUTLINK_START_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_START_CH2_Pos = 0x15
	// Bit mask of OUTLINK_START_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_START_CH2_Msk = 0x200000
	// Bit OUTLINK_START_CH2.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_START_CH2 = 0x200000
	// Position of OUTLINK_RESTART_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_RESTART_CH2_Pos = 0x16
	// Bit mask of OUTLINK_RESTART_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_RESTART_CH2_Msk = 0x400000
	// Bit OUTLINK_RESTART_CH2.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_RESTART_CH2 = 0x400000
	// Position of OUTLINK_PARK_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_PARK_CH2_Pos = 0x17
	// Bit mask of OUTLINK_PARK_CH2 field.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_PARK_CH2_Msk = 0x800000
	// Bit OUTLINK_PARK_CH2.
	H264_DMA_OUT_LINK_CONF_CH2_OUTLINK_PARK_CH2 = 0x800000

	// OUT_LINK_ADDR_CH2: TX CH2 out_link dscr addr register
	// Position of OUTLINK_ADDR_CH2 field.
	H264_DMA_OUT_LINK_ADDR_CH2_OUTLINK_ADDR_CH2_Pos = 0x0
	// Bit mask of OUTLINK_ADDR_CH2 field.
	H264_DMA_OUT_LINK_ADDR_CH2_OUTLINK_ADDR_CH2_Msk = 0xffffffff

	// OUT_STATE_CH2: TX CH2 state register
	// Position of OUTLINK_DSCR_ADDR_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH2_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_ADDR_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUTLINK_DSCR_ADDR_CH2_Msk = 0x3ffff
	// Position of OUT_DSCR_STATE_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUT_DSCR_STATE_CH2_Pos = 0x12
	// Bit mask of OUT_DSCR_STATE_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUT_DSCR_STATE_CH2_Msk = 0xc0000
	// Position of OUT_STATE_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUT_STATE_CH2_Pos = 0x14
	// Bit mask of OUT_STATE_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUT_STATE_CH2_Msk = 0xf00000
	// Position of OUT_RESET_AVAIL_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUT_RESET_AVAIL_CH2_Pos = 0x18
	// Bit mask of OUT_RESET_AVAIL_CH2 field.
	H264_DMA_OUT_STATE_CH2_OUT_RESET_AVAIL_CH2_Msk = 0x1000000
	// Bit OUT_RESET_AVAIL_CH2.
	H264_DMA_OUT_STATE_CH2_OUT_RESET_AVAIL_CH2 = 0x1000000

	// OUT_EOF_DES_ADDR_CH2: TX CH2 eof des addr register
	// Position of OUT_EOF_DES_ADDR_CH2 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH2_OUT_EOF_DES_ADDR_CH2_Pos = 0x0
	// Bit mask of OUT_EOF_DES_ADDR_CH2 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH2_OUT_EOF_DES_ADDR_CH2_Msk = 0xffffffff

	// OUT_DSCR_CH2: TX CH2 next dscr addr register
	// Position of OUTLINK_DSCR_CH2 field.
	H264_DMA_OUT_DSCR_CH2_OUTLINK_DSCR_CH2_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_CH2 field.
	H264_DMA_OUT_DSCR_CH2_OUTLINK_DSCR_CH2_Msk = 0xffffffff

	// OUT_DSCR_BF0_CH2: TX CH2 last dscr addr register
	// Position of OUTLINK_DSCR_BF0_CH2 field.
	H264_DMA_OUT_DSCR_BF0_CH2_OUTLINK_DSCR_BF0_CH2_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF0_CH2 field.
	H264_DMA_OUT_DSCR_BF0_CH2_OUTLINK_DSCR_BF0_CH2_Msk = 0xffffffff

	// OUT_DSCR_BF1_CH2: TX CH2 second-to-last dscr addr register
	// Position of OUTLINK_DSCR_BF1_CH2 field.
	H264_DMA_OUT_DSCR_BF1_CH2_OUTLINK_DSCR_BF1_CH2_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF1_CH2 field.
	H264_DMA_OUT_DSCR_BF1_CH2_OUTLINK_DSCR_BF1_CH2_Msk = 0xffffffff

	// OUT_ARB_CH2: TX CH2 arb register
	// Position of OUT_ARB_TOKEN_NUM_CH2 field.
	H264_DMA_OUT_ARB_CH2_OUT_ARB_TOKEN_NUM_CH2_Pos = 0x0
	// Bit mask of OUT_ARB_TOKEN_NUM_CH2 field.
	H264_DMA_OUT_ARB_CH2_OUT_ARB_TOKEN_NUM_CH2_Msk = 0xf
	// Position of INTER_OUT_ARB_PRIORITY_CH2 field.
	H264_DMA_OUT_ARB_CH2_INTER_OUT_ARB_PRIORITY_CH2_Pos = 0x6
	// Bit mask of INTER_OUT_ARB_PRIORITY_CH2 field.
	H264_DMA_OUT_ARB_CH2_INTER_OUT_ARB_PRIORITY_CH2_Msk = 0x40
	// Bit INTER_OUT_ARB_PRIORITY_CH2.
	H264_DMA_OUT_ARB_CH2_INTER_OUT_ARB_PRIORITY_CH2 = 0x40

	// OUT_ETM_CONF_CH2: TX CH2 ETM config register
	// Position of OUT_ETM_EN_CH2 field.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_ETM_EN_CH2_Pos = 0x0
	// Bit mask of OUT_ETM_EN_CH2 field.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_ETM_EN_CH2_Msk = 0x1
	// Bit OUT_ETM_EN_CH2.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_ETM_EN_CH2 = 0x1
	// Position of OUT_ETM_LOOP_EN_CH2 field.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_ETM_LOOP_EN_CH2_Pos = 0x1
	// Bit mask of OUT_ETM_LOOP_EN_CH2 field.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_ETM_LOOP_EN_CH2_Msk = 0x2
	// Bit OUT_ETM_LOOP_EN_CH2.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_ETM_LOOP_EN_CH2 = 0x2
	// Position of OUT_DSCR_TASK_MAK_CH2 field.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_DSCR_TASK_MAK_CH2_Pos = 0x2
	// Bit mask of OUT_DSCR_TASK_MAK_CH2 field.
	H264_DMA_OUT_ETM_CONF_CH2_OUT_DSCR_TASK_MAK_CH2_Msk = 0xc

	// OUT_BUF_LEN_CH2: tx CH2 buf len register
	// Position of OUT_CMDFIFO_BUF_LEN_HB_CH2 field.
	H264_DMA_OUT_BUF_LEN_CH2_OUT_CMDFIFO_BUF_LEN_HB_CH2_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_BUF_LEN_HB_CH2 field.
	H264_DMA_OUT_BUF_LEN_CH2_OUT_CMDFIFO_BUF_LEN_HB_CH2_Msk = 0x1fff

	// OUT_FIFO_BCNT_CH2: tx CH2 fifo byte cnt register
	// Position of OUT_CMDFIFO_OUTFIFO_BCNT_CH2 field.
	H264_DMA_OUT_FIFO_BCNT_CH2_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_OUTFIFO_BCNT_CH2 field.
	H264_DMA_OUT_FIFO_BCNT_CH2_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_Msk = 0x3ff

	// OUT_PUSH_BYTECNT_CH2: tx CH2 push byte cnt register
	// Position of OUT_CMDFIFO_PUSH_BYTECNT_CH2 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH2_OUT_CMDFIFO_PUSH_BYTECNT_CH2_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_PUSH_BYTECNT_CH2 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH2_OUT_CMDFIFO_PUSH_BYTECNT_CH2_Msk = 0xff

	// OUT_XADDR_CH2: tx CH2 xaddr register
	// Position of OUT_CMDFIFO_XADDR_CH2 field.
	H264_DMA_OUT_XADDR_CH2_OUT_CMDFIFO_XADDR_CH2_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_XADDR_CH2 field.
	H264_DMA_OUT_XADDR_CH2_OUT_CMDFIFO_XADDR_CH2_Msk = 0xffffffff

	// OUT_CONF0_CH3: TX CH3 config0 register
	// Position of OUT_AUTO_WRBACK_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_AUTO_WRBACK_CH3_Pos = 0x0
	// Bit mask of OUT_AUTO_WRBACK_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_AUTO_WRBACK_CH3_Msk = 0x1
	// Bit OUT_AUTO_WRBACK_CH3.
	H264_DMA_OUT_CONF0_CH3_OUT_AUTO_WRBACK_CH3 = 0x1
	// Position of OUT_EOF_MODE_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_EOF_MODE_CH3_Pos = 0x1
	// Bit mask of OUT_EOF_MODE_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_EOF_MODE_CH3_Msk = 0x2
	// Bit OUT_EOF_MODE_CH3.
	H264_DMA_OUT_CONF0_CH3_OUT_EOF_MODE_CH3 = 0x2
	// Position of OUTDSCR_BURST_EN_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUTDSCR_BURST_EN_CH3_Pos = 0x2
	// Bit mask of OUTDSCR_BURST_EN_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUTDSCR_BURST_EN_CH3_Msk = 0x4
	// Bit OUTDSCR_BURST_EN_CH3.
	H264_DMA_OUT_CONF0_CH3_OUTDSCR_BURST_EN_CH3 = 0x4
	// Position of OUT_ECC_AES_EN_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_ECC_AES_EN_CH3_Pos = 0x3
	// Bit mask of OUT_ECC_AES_EN_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_ECC_AES_EN_CH3_Msk = 0x8
	// Bit OUT_ECC_AES_EN_CH3.
	H264_DMA_OUT_CONF0_CH3_OUT_ECC_AES_EN_CH3 = 0x8
	// Position of OUT_CHECK_OWNER_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_CHECK_OWNER_CH3_Pos = 0x4
	// Bit mask of OUT_CHECK_OWNER_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_CHECK_OWNER_CH3_Msk = 0x10
	// Bit OUT_CHECK_OWNER_CH3.
	H264_DMA_OUT_CONF0_CH3_OUT_CHECK_OWNER_CH3 = 0x10
	// Position of OUT_MEM_BURST_LENGTH_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_MEM_BURST_LENGTH_CH3_Pos = 0x6
	// Bit mask of OUT_MEM_BURST_LENGTH_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_MEM_BURST_LENGTH_CH3_Msk = 0x1c0
	// Position of OUT_PAGE_BOUND_EN_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_PAGE_BOUND_EN_CH3_Pos = 0xc
	// Bit mask of OUT_PAGE_BOUND_EN_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_PAGE_BOUND_EN_CH3_Msk = 0x1000
	// Bit OUT_PAGE_BOUND_EN_CH3.
	H264_DMA_OUT_CONF0_CH3_OUT_PAGE_BOUND_EN_CH3 = 0x1000
	// Position of OUT_ARB_WEIGHT_OPT_DIS_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_ARB_WEIGHT_OPT_DIS_CH3_Pos = 0x1a
	// Bit mask of OUT_ARB_WEIGHT_OPT_DIS_CH3 field.
	H264_DMA_OUT_CONF0_CH3_OUT_ARB_WEIGHT_OPT_DIS_CH3_Msk = 0x4000000
	// Bit OUT_ARB_WEIGHT_OPT_DIS_CH3.
	H264_DMA_OUT_CONF0_CH3_OUT_ARB_WEIGHT_OPT_DIS_CH3 = 0x4000000

	// OUT_INT_RAW_CH3: TX CH3 interrupt raw register
	// Position of OUT_DONE_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DONE_CH3_INT_RAW_Pos = 0x0
	// Bit mask of OUT_DONE_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DONE_CH3_INT_RAW_Msk = 0x1
	// Bit OUT_DONE_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DONE_CH3_INT_RAW = 0x1
	// Position of OUT_EOF_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_EOF_CH3_INT_RAW_Pos = 0x1
	// Bit mask of OUT_EOF_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_EOF_CH3_INT_RAW_Msk = 0x2
	// Bit OUT_EOF_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUT_EOF_CH3_INT_RAW = 0x2
	// Position of OUT_DSCR_ERR_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DSCR_ERR_CH3_INT_RAW_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DSCR_ERR_CH3_INT_RAW_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DSCR_ERR_CH3_INT_RAW = 0x4
	// Position of OUT_TOTAL_EOF_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_TOTAL_EOF_CH3_INT_RAW_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_TOTAL_EOF_CH3_INT_RAW_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUT_TOTAL_EOF_CH3_INT_RAW = 0x8
	// Position of OUTFIFO_OVF_L1_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_OVF_L1_CH3_INT_RAW_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_OVF_L1_CH3_INT_RAW_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_OVF_L1_CH3_INT_RAW = 0x10
	// Position of OUTFIFO_UDF_L1_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_UDF_L1_CH3_INT_RAW_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_UDF_L1_CH3_INT_RAW_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_UDF_L1_CH3_INT_RAW = 0x20
	// Position of OUTFIFO_OVF_L2_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_OVF_L2_CH3_INT_RAW_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_OVF_L2_CH3_INT_RAW_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_OVF_L2_CH3_INT_RAW = 0x40
	// Position of OUTFIFO_UDF_L2_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_UDF_L2_CH3_INT_RAW_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_UDF_L2_CH3_INT_RAW_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUTFIFO_UDF_L2_CH3_INT_RAW = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DSCR_TASK_OVF_CH3_INT_RAW_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH3_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DSCR_TASK_OVF_CH3_INT_RAW_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH3_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH3_OUT_DSCR_TASK_OVF_CH3_INT_RAW = 0x100

	// OUT_INT_ENA_CH3: TX CH3 interrupt ena register
	// Position of OUT_DONE_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DONE_CH3_INT_ENA_Pos = 0x0
	// Bit mask of OUT_DONE_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DONE_CH3_INT_ENA_Msk = 0x1
	// Bit OUT_DONE_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DONE_CH3_INT_ENA = 0x1
	// Position of OUT_EOF_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_EOF_CH3_INT_ENA_Pos = 0x1
	// Bit mask of OUT_EOF_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_EOF_CH3_INT_ENA_Msk = 0x2
	// Bit OUT_EOF_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUT_EOF_CH3_INT_ENA = 0x2
	// Position of OUT_DSCR_ERR_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DSCR_ERR_CH3_INT_ENA_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DSCR_ERR_CH3_INT_ENA_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DSCR_ERR_CH3_INT_ENA = 0x4
	// Position of OUT_TOTAL_EOF_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_TOTAL_EOF_CH3_INT_ENA_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_TOTAL_EOF_CH3_INT_ENA_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUT_TOTAL_EOF_CH3_INT_ENA = 0x8
	// Position of OUTFIFO_OVF_L1_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_OVF_L1_CH3_INT_ENA_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_OVF_L1_CH3_INT_ENA_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_OVF_L1_CH3_INT_ENA = 0x10
	// Position of OUTFIFO_UDF_L1_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_UDF_L1_CH3_INT_ENA_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_UDF_L1_CH3_INT_ENA_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_UDF_L1_CH3_INT_ENA = 0x20
	// Position of OUTFIFO_OVF_L2_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_OVF_L2_CH3_INT_ENA_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_OVF_L2_CH3_INT_ENA_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_OVF_L2_CH3_INT_ENA = 0x40
	// Position of OUTFIFO_UDF_L2_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_UDF_L2_CH3_INT_ENA_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_UDF_L2_CH3_INT_ENA_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUTFIFO_UDF_L2_CH3_INT_ENA = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ENA_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH3_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ENA_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH3_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ENA = 0x100

	// OUT_INT_ST_CH3: TX CH3 interrupt st register
	// Position of OUT_DONE_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_DONE_CH3_INT_ST_Pos = 0x0
	// Bit mask of OUT_DONE_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_DONE_CH3_INT_ST_Msk = 0x1
	// Bit OUT_DONE_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUT_DONE_CH3_INT_ST = 0x1
	// Position of OUT_EOF_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_EOF_CH3_INT_ST_Pos = 0x1
	// Bit mask of OUT_EOF_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_EOF_CH3_INT_ST_Msk = 0x2
	// Bit OUT_EOF_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUT_EOF_CH3_INT_ST = 0x2
	// Position of OUT_DSCR_ERR_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_DSCR_ERR_CH3_INT_ST_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_DSCR_ERR_CH3_INT_ST_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUT_DSCR_ERR_CH3_INT_ST = 0x4
	// Position of OUT_TOTAL_EOF_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_TOTAL_EOF_CH3_INT_ST_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_TOTAL_EOF_CH3_INT_ST_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUT_TOTAL_EOF_CH3_INT_ST = 0x8
	// Position of OUTFIFO_OVF_L1_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_OVF_L1_CH3_INT_ST_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_OVF_L1_CH3_INT_ST_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_OVF_L1_CH3_INT_ST = 0x10
	// Position of OUTFIFO_UDF_L1_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_UDF_L1_CH3_INT_ST_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_UDF_L1_CH3_INT_ST_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_UDF_L1_CH3_INT_ST = 0x20
	// Position of OUTFIFO_OVF_L2_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_OVF_L2_CH3_INT_ST_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_OVF_L2_CH3_INT_ST_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_OVF_L2_CH3_INT_ST = 0x40
	// Position of OUTFIFO_UDF_L2_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_UDF_L2_CH3_INT_ST_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_UDF_L2_CH3_INT_ST_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUTFIFO_UDF_L2_CH3_INT_ST = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ST_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH3_INT_ST field.
	H264_DMA_OUT_INT_ST_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ST_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH3_INT_ST.
	H264_DMA_OUT_INT_ST_CH3_OUT_DSCR_TASK_OVF_CH3_INT_ST = 0x100

	// OUT_INT_CLR_CH3: TX CH3 interrupt clr register
	// Position of OUT_DONE_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DONE_CH3_INT_CLR_Pos = 0x0
	// Bit mask of OUT_DONE_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DONE_CH3_INT_CLR_Msk = 0x1
	// Bit OUT_DONE_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DONE_CH3_INT_CLR = 0x1
	// Position of OUT_EOF_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_EOF_CH3_INT_CLR_Pos = 0x1
	// Bit mask of OUT_EOF_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_EOF_CH3_INT_CLR_Msk = 0x2
	// Bit OUT_EOF_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUT_EOF_CH3_INT_CLR = 0x2
	// Position of OUT_DSCR_ERR_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DSCR_ERR_CH3_INT_CLR_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DSCR_ERR_CH3_INT_CLR_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DSCR_ERR_CH3_INT_CLR = 0x4
	// Position of OUT_TOTAL_EOF_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_TOTAL_EOF_CH3_INT_CLR_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_TOTAL_EOF_CH3_INT_CLR_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUT_TOTAL_EOF_CH3_INT_CLR = 0x8
	// Position of OUTFIFO_OVF_L1_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_OVF_L1_CH3_INT_CLR_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_OVF_L1_CH3_INT_CLR_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_OVF_L1_CH3_INT_CLR = 0x10
	// Position of OUTFIFO_UDF_L1_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_UDF_L1_CH3_INT_CLR_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_UDF_L1_CH3_INT_CLR_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_UDF_L1_CH3_INT_CLR = 0x20
	// Position of OUTFIFO_OVF_L2_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_OVF_L2_CH3_INT_CLR_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_OVF_L2_CH3_INT_CLR_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_OVF_L2_CH3_INT_CLR = 0x40
	// Position of OUTFIFO_UDF_L2_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_UDF_L2_CH3_INT_CLR_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_UDF_L2_CH3_INT_CLR_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUTFIFO_UDF_L2_CH3_INT_CLR = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DSCR_TASK_OVF_CH3_INT_CLR_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH3_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DSCR_TASK_OVF_CH3_INT_CLR_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH3_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH3_OUT_DSCR_TASK_OVF_CH3_INT_CLR = 0x100

	// OUTFIFO_STATUS_CH3: TX CH3 outfifo status register
	// Position of OUTFIFO_FULL_L2_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2_CH3_Pos = 0x0
	// Bit mask of OUTFIFO_FULL_L2_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2_CH3_Msk = 0x1
	// Bit OUTFIFO_FULL_L2_CH3.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L2_CH3 = 0x1
	// Position of OUTFIFO_EMPTY_L2_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2_CH3_Pos = 0x1
	// Bit mask of OUTFIFO_EMPTY_L2_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2_CH3_Msk = 0x2
	// Bit OUTFIFO_EMPTY_L2_CH3.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L2_CH3 = 0x2
	// Position of OUTFIFO_CNT_L2_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2_CH3_Pos = 0x2
	// Bit mask of OUTFIFO_CNT_L2_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_CNT_L2_CH3_Msk = 0x3c
	// Position of OUTFIFO_FULL_L1_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1_CH3_Pos = 0x6
	// Bit mask of OUTFIFO_FULL_L1_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1_CH3_Msk = 0x40
	// Bit OUTFIFO_FULL_L1_CH3.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L1_CH3 = 0x40
	// Position of OUTFIFO_EMPTY_L1_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1_CH3_Pos = 0x7
	// Bit mask of OUTFIFO_EMPTY_L1_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1_CH3_Msk = 0x80
	// Bit OUTFIFO_EMPTY_L1_CH3.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L1_CH3 = 0x80
	// Position of OUTFIFO_CNT_L1_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1_CH3_Pos = 0x8
	// Bit mask of OUTFIFO_CNT_L1_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_CNT_L1_CH3_Msk = 0x1f00
	// Position of OUTFIFO_FULL_L3_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3_CH3_Pos = 0x10
	// Bit mask of OUTFIFO_FULL_L3_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3_CH3_Msk = 0x10000
	// Bit OUTFIFO_FULL_L3_CH3.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_FULL_L3_CH3 = 0x10000
	// Position of OUTFIFO_EMPTY_L3_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3_CH3_Pos = 0x11
	// Bit mask of OUTFIFO_EMPTY_L3_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3_CH3_Msk = 0x20000
	// Bit OUTFIFO_EMPTY_L3_CH3.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_EMPTY_L3_CH3 = 0x20000
	// Position of OUTFIFO_CNT_L3_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3_CH3_Pos = 0x12
	// Bit mask of OUTFIFO_CNT_L3_CH3 field.
	H264_DMA_OUTFIFO_STATUS_CH3_OUTFIFO_CNT_L3_CH3_Msk = 0xc0000

	// OUT_PUSH_CH3: TX CH3 outfifo push register
	// Position of OUTFIFO_WDATA_CH3 field.
	H264_DMA_OUT_PUSH_CH3_OUTFIFO_WDATA_CH3_Pos = 0x0
	// Bit mask of OUTFIFO_WDATA_CH3 field.
	H264_DMA_OUT_PUSH_CH3_OUTFIFO_WDATA_CH3_Msk = 0x3ff
	// Position of OUTFIFO_PUSH_CH3 field.
	H264_DMA_OUT_PUSH_CH3_OUTFIFO_PUSH_CH3_Pos = 0xa
	// Bit mask of OUTFIFO_PUSH_CH3 field.
	H264_DMA_OUT_PUSH_CH3_OUTFIFO_PUSH_CH3_Msk = 0x400
	// Bit OUTFIFO_PUSH_CH3.
	H264_DMA_OUT_PUSH_CH3_OUTFIFO_PUSH_CH3 = 0x400

	// OUT_LINK_CONF_CH3: TX CH3 out_link dscr ctrl register
	// Position of OUTLINK_STOP_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_STOP_CH3_Pos = 0x14
	// Bit mask of OUTLINK_STOP_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_STOP_CH3_Msk = 0x100000
	// Bit OUTLINK_STOP_CH3.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_STOP_CH3 = 0x100000
	// Position of OUTLINK_START_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_START_CH3_Pos = 0x15
	// Bit mask of OUTLINK_START_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_START_CH3_Msk = 0x200000
	// Bit OUTLINK_START_CH3.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_START_CH3 = 0x200000
	// Position of OUTLINK_RESTART_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_RESTART_CH3_Pos = 0x16
	// Bit mask of OUTLINK_RESTART_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_RESTART_CH3_Msk = 0x400000
	// Bit OUTLINK_RESTART_CH3.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_RESTART_CH3 = 0x400000
	// Position of OUTLINK_PARK_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_PARK_CH3_Pos = 0x17
	// Bit mask of OUTLINK_PARK_CH3 field.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_PARK_CH3_Msk = 0x800000
	// Bit OUTLINK_PARK_CH3.
	H264_DMA_OUT_LINK_CONF_CH3_OUTLINK_PARK_CH3 = 0x800000

	// OUT_LINK_ADDR_CH3: TX CH3 out_link dscr addr register
	// Position of OUTLINK_ADDR_CH3 field.
	H264_DMA_OUT_LINK_ADDR_CH3_OUTLINK_ADDR_CH3_Pos = 0x0
	// Bit mask of OUTLINK_ADDR_CH3 field.
	H264_DMA_OUT_LINK_ADDR_CH3_OUTLINK_ADDR_CH3_Msk = 0xffffffff

	// OUT_STATE_CH3: TX CH3 state register
	// Position of OUTLINK_DSCR_ADDR_CH3 field.
	H264_DMA_OUT_STATE_CH3_OUTLINK_DSCR_ADDR_CH3_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_ADDR_CH3 field.
	H264_DMA_OUT_STATE_CH3_OUTLINK_DSCR_ADDR_CH3_Msk = 0x3ffff
	// Position of OUT_DSCR_STATE_CH3 field.
	H264_DMA_OUT_STATE_CH3_OUT_DSCR_STATE_CH3_Pos = 0x12
	// Bit mask of OUT_DSCR_STATE_CH3 field.
	H264_DMA_OUT_STATE_CH3_OUT_DSCR_STATE_CH3_Msk = 0xc0000
	// Position of OUT_STATE_CH3 field.
	H264_DMA_OUT_STATE_CH3_OUT_STATE_CH3_Pos = 0x14
	// Bit mask of OUT_STATE_CH3 field.
	H264_DMA_OUT_STATE_CH3_OUT_STATE_CH3_Msk = 0xf00000

	// OUT_EOF_DES_ADDR_CH3: TX CH3 eof des addr register
	// Position of OUT_EOF_DES_ADDR_CH3 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH3_OUT_EOF_DES_ADDR_CH3_Pos = 0x0
	// Bit mask of OUT_EOF_DES_ADDR_CH3 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH3_OUT_EOF_DES_ADDR_CH3_Msk = 0xffffffff

	// OUT_DSCR_CH3: TX CH3 next dscr addr register
	// Position of OUTLINK_DSCR_CH3 field.
	H264_DMA_OUT_DSCR_CH3_OUTLINK_DSCR_CH3_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_CH3 field.
	H264_DMA_OUT_DSCR_CH3_OUTLINK_DSCR_CH3_Msk = 0xffffffff

	// OUT_DSCR_BF0_CH3: TX CH3 last dscr addr register
	// Position of OUTLINK_DSCR_BF0_CH3 field.
	H264_DMA_OUT_DSCR_BF0_CH3_OUTLINK_DSCR_BF0_CH3_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF0_CH3 field.
	H264_DMA_OUT_DSCR_BF0_CH3_OUTLINK_DSCR_BF0_CH3_Msk = 0xffffffff

	// OUT_DSCR_BF1_CH3: TX CH3 second-to-last dscr addr register
	// Position of OUTLINK_DSCR_BF1_CH3 field.
	H264_DMA_OUT_DSCR_BF1_CH3_OUTLINK_DSCR_BF1_CH3_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF1_CH3 field.
	H264_DMA_OUT_DSCR_BF1_CH3_OUTLINK_DSCR_BF1_CH3_Msk = 0xffffffff

	// OUT_ARB_CH3: TX CH3 arb register
	// Position of OUT_ARB_TOKEN_NUM_CH3 field.
	H264_DMA_OUT_ARB_CH3_OUT_ARB_TOKEN_NUM_CH3_Pos = 0x0
	// Bit mask of OUT_ARB_TOKEN_NUM_CH3 field.
	H264_DMA_OUT_ARB_CH3_OUT_ARB_TOKEN_NUM_CH3_Msk = 0xf
	// Position of EXTER_OUT_ARB_PRIORITY_CH3 field.
	H264_DMA_OUT_ARB_CH3_EXTER_OUT_ARB_PRIORITY_CH3_Pos = 0x4
	// Bit mask of EXTER_OUT_ARB_PRIORITY_CH3 field.
	H264_DMA_OUT_ARB_CH3_EXTER_OUT_ARB_PRIORITY_CH3_Msk = 0x30

	// OUT_ETM_CONF_CH3: TX CH3 ETM config register
	// Position of OUT_ETM_EN_CH3 field.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_ETM_EN_CH3_Pos = 0x0
	// Bit mask of OUT_ETM_EN_CH3 field.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_ETM_EN_CH3_Msk = 0x1
	// Bit OUT_ETM_EN_CH3.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_ETM_EN_CH3 = 0x1
	// Position of OUT_ETM_LOOP_EN_CH3 field.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_ETM_LOOP_EN_CH3_Pos = 0x1
	// Bit mask of OUT_ETM_LOOP_EN_CH3 field.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_ETM_LOOP_EN_CH3_Msk = 0x2
	// Bit OUT_ETM_LOOP_EN_CH3.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_ETM_LOOP_EN_CH3 = 0x2
	// Position of OUT_DSCR_TASK_MAK_CH3 field.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_DSCR_TASK_MAK_CH3_Pos = 0x2
	// Bit mask of OUT_DSCR_TASK_MAK_CH3 field.
	H264_DMA_OUT_ETM_CONF_CH3_OUT_DSCR_TASK_MAK_CH3_Msk = 0xc

	// OUT_BUF_LEN_CH3: tx CH3 buf len register
	// Position of OUT_CMDFIFO_BUF_LEN_HB_CH3 field.
	H264_DMA_OUT_BUF_LEN_CH3_OUT_CMDFIFO_BUF_LEN_HB_CH3_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_BUF_LEN_HB_CH3 field.
	H264_DMA_OUT_BUF_LEN_CH3_OUT_CMDFIFO_BUF_LEN_HB_CH3_Msk = 0x1fff

	// OUT_FIFO_BCNT_CH3: tx CH3 fifo byte cnt register
	// Position of OUT_CMDFIFO_OUTFIFO_BCNT_CH3 field.
	H264_DMA_OUT_FIFO_BCNT_CH3_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_OUTFIFO_BCNT_CH3 field.
	H264_DMA_OUT_FIFO_BCNT_CH3_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_Msk = 0x3ff

	// OUT_PUSH_BYTECNT_CH3: tx CH3 push byte cnt register
	// Position of OUT_CMDFIFO_PUSH_BYTECNT_CH3 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH3_OUT_CMDFIFO_PUSH_BYTECNT_CH3_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_PUSH_BYTECNT_CH3 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH3_OUT_CMDFIFO_PUSH_BYTECNT_CH3_Msk = 0xff

	// OUT_XADDR_CH3: tx CH3 xaddr register
	// Position of OUT_CMDFIFO_XADDR_CH3 field.
	H264_DMA_OUT_XADDR_CH3_OUT_CMDFIFO_XADDR_CH3_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_XADDR_CH3 field.
	H264_DMA_OUT_XADDR_CH3_OUT_CMDFIFO_XADDR_CH3_Msk = 0xffffffff

	// OUT_BLOCK_BUF_LEN_CH3: tx CH3 block buf len register
	// Position of OUT_BLOCK_BUF_LEN_CH3 field.
	H264_DMA_OUT_BLOCK_BUF_LEN_CH3_OUT_BLOCK_BUF_LEN_CH3_Pos = 0x0
	// Bit mask of OUT_BLOCK_BUF_LEN_CH3 field.
	H264_DMA_OUT_BLOCK_BUF_LEN_CH3_OUT_BLOCK_BUF_LEN_CH3_Msk = 0xfffffff

	// OUT_CONF0_CH4: TX CH4 config0 register
	// Position of OUT_AUTO_WRBACK_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_AUTO_WRBACK_CH4_Pos = 0x0
	// Bit mask of OUT_AUTO_WRBACK_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_AUTO_WRBACK_CH4_Msk = 0x1
	// Bit OUT_AUTO_WRBACK_CH4.
	H264_DMA_OUT_CONF0_CH4_OUT_AUTO_WRBACK_CH4 = 0x1
	// Position of OUT_EOF_MODE_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_EOF_MODE_CH4_Pos = 0x1
	// Bit mask of OUT_EOF_MODE_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_EOF_MODE_CH4_Msk = 0x2
	// Bit OUT_EOF_MODE_CH4.
	H264_DMA_OUT_CONF0_CH4_OUT_EOF_MODE_CH4 = 0x2
	// Position of OUTDSCR_BURST_EN_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUTDSCR_BURST_EN_CH4_Pos = 0x2
	// Bit mask of OUTDSCR_BURST_EN_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUTDSCR_BURST_EN_CH4_Msk = 0x4
	// Bit OUTDSCR_BURST_EN_CH4.
	H264_DMA_OUT_CONF0_CH4_OUTDSCR_BURST_EN_CH4 = 0x4
	// Position of OUT_ECC_AES_EN_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_ECC_AES_EN_CH4_Pos = 0x3
	// Bit mask of OUT_ECC_AES_EN_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_ECC_AES_EN_CH4_Msk = 0x8
	// Bit OUT_ECC_AES_EN_CH4.
	H264_DMA_OUT_CONF0_CH4_OUT_ECC_AES_EN_CH4 = 0x8
	// Position of OUT_CHECK_OWNER_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_CHECK_OWNER_CH4_Pos = 0x4
	// Bit mask of OUT_CHECK_OWNER_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_CHECK_OWNER_CH4_Msk = 0x10
	// Bit OUT_CHECK_OWNER_CH4.
	H264_DMA_OUT_CONF0_CH4_OUT_CHECK_OWNER_CH4 = 0x10
	// Position of OUT_MEM_BURST_LENGTH_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_MEM_BURST_LENGTH_CH4_Pos = 0x6
	// Bit mask of OUT_MEM_BURST_LENGTH_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_MEM_BURST_LENGTH_CH4_Msk = 0x1c0
	// Position of OUT_PAGE_BOUND_EN_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_PAGE_BOUND_EN_CH4_Pos = 0xc
	// Bit mask of OUT_PAGE_BOUND_EN_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_PAGE_BOUND_EN_CH4_Msk = 0x1000
	// Bit OUT_PAGE_BOUND_EN_CH4.
	H264_DMA_OUT_CONF0_CH4_OUT_PAGE_BOUND_EN_CH4 = 0x1000
	// Position of OUT_ARB_WEIGHT_OPT_DIS_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_ARB_WEIGHT_OPT_DIS_CH4_Pos = 0x1a
	// Bit mask of OUT_ARB_WEIGHT_OPT_DIS_CH4 field.
	H264_DMA_OUT_CONF0_CH4_OUT_ARB_WEIGHT_OPT_DIS_CH4_Msk = 0x4000000
	// Bit OUT_ARB_WEIGHT_OPT_DIS_CH4.
	H264_DMA_OUT_CONF0_CH4_OUT_ARB_WEIGHT_OPT_DIS_CH4 = 0x4000000

	// OUT_INT_RAW_CH4: TX CH4 interrupt raw register
	// Position of OUT_DONE_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DONE_CH4_INT_RAW_Pos = 0x0
	// Bit mask of OUT_DONE_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DONE_CH4_INT_RAW_Msk = 0x1
	// Bit OUT_DONE_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DONE_CH4_INT_RAW = 0x1
	// Position of OUT_EOF_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_EOF_CH4_INT_RAW_Pos = 0x1
	// Bit mask of OUT_EOF_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_EOF_CH4_INT_RAW_Msk = 0x2
	// Bit OUT_EOF_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUT_EOF_CH4_INT_RAW = 0x2
	// Position of OUT_DSCR_ERR_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DSCR_ERR_CH4_INT_RAW_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DSCR_ERR_CH4_INT_RAW_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DSCR_ERR_CH4_INT_RAW = 0x4
	// Position of OUT_TOTAL_EOF_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_TOTAL_EOF_CH4_INT_RAW_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_TOTAL_EOF_CH4_INT_RAW_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUT_TOTAL_EOF_CH4_INT_RAW = 0x8
	// Position of OUTFIFO_OVF_L1_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_OVF_L1_CH4_INT_RAW_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_OVF_L1_CH4_INT_RAW_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_OVF_L1_CH4_INT_RAW = 0x10
	// Position of OUTFIFO_UDF_L1_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_UDF_L1_CH4_INT_RAW_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_UDF_L1_CH4_INT_RAW_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_UDF_L1_CH4_INT_RAW = 0x20
	// Position of OUTFIFO_OVF_L2_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_OVF_L2_CH4_INT_RAW_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_OVF_L2_CH4_INT_RAW_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_OVF_L2_CH4_INT_RAW = 0x40
	// Position of OUTFIFO_UDF_L2_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_UDF_L2_CH4_INT_RAW_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_UDF_L2_CH4_INT_RAW_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUTFIFO_UDF_L2_CH4_INT_RAW = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DSCR_TASK_OVF_CH4_INT_RAW_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH4_INT_RAW field.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DSCR_TASK_OVF_CH4_INT_RAW_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH4_INT_RAW.
	H264_DMA_OUT_INT_RAW_CH4_OUT_DSCR_TASK_OVF_CH4_INT_RAW = 0x100

	// OUT_INT_ENA_CH4: TX CH4 interrupt ena register
	// Position of OUT_DONE_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DONE_CH4_INT_ENA_Pos = 0x0
	// Bit mask of OUT_DONE_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DONE_CH4_INT_ENA_Msk = 0x1
	// Bit OUT_DONE_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DONE_CH4_INT_ENA = 0x1
	// Position of OUT_EOF_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_EOF_CH4_INT_ENA_Pos = 0x1
	// Bit mask of OUT_EOF_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_EOF_CH4_INT_ENA_Msk = 0x2
	// Bit OUT_EOF_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUT_EOF_CH4_INT_ENA = 0x2
	// Position of OUT_DSCR_ERR_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DSCR_ERR_CH4_INT_ENA_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DSCR_ERR_CH4_INT_ENA_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DSCR_ERR_CH4_INT_ENA = 0x4
	// Position of OUT_TOTAL_EOF_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_TOTAL_EOF_CH4_INT_ENA_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_TOTAL_EOF_CH4_INT_ENA_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUT_TOTAL_EOF_CH4_INT_ENA = 0x8
	// Position of OUTFIFO_OVF_L1_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_OVF_L1_CH4_INT_ENA_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_OVF_L1_CH4_INT_ENA_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_OVF_L1_CH4_INT_ENA = 0x10
	// Position of OUTFIFO_UDF_L1_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_UDF_L1_CH4_INT_ENA_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_UDF_L1_CH4_INT_ENA_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_UDF_L1_CH4_INT_ENA = 0x20
	// Position of OUTFIFO_OVF_L2_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_OVF_L2_CH4_INT_ENA_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_OVF_L2_CH4_INT_ENA_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_OVF_L2_CH4_INT_ENA = 0x40
	// Position of OUTFIFO_UDF_L2_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_UDF_L2_CH4_INT_ENA_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_UDF_L2_CH4_INT_ENA_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUTFIFO_UDF_L2_CH4_INT_ENA = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ENA_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH4_INT_ENA field.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ENA_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH4_INT_ENA.
	H264_DMA_OUT_INT_ENA_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ENA = 0x100

	// OUT_INT_ST_CH4: TX CH4 interrupt st register
	// Position of OUT_DONE_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_DONE_CH4_INT_ST_Pos = 0x0
	// Bit mask of OUT_DONE_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_DONE_CH4_INT_ST_Msk = 0x1
	// Bit OUT_DONE_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUT_DONE_CH4_INT_ST = 0x1
	// Position of OUT_EOF_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_EOF_CH4_INT_ST_Pos = 0x1
	// Bit mask of OUT_EOF_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_EOF_CH4_INT_ST_Msk = 0x2
	// Bit OUT_EOF_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUT_EOF_CH4_INT_ST = 0x2
	// Position of OUT_DSCR_ERR_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_DSCR_ERR_CH4_INT_ST_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_DSCR_ERR_CH4_INT_ST_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUT_DSCR_ERR_CH4_INT_ST = 0x4
	// Position of OUT_TOTAL_EOF_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_TOTAL_EOF_CH4_INT_ST_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_TOTAL_EOF_CH4_INT_ST_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUT_TOTAL_EOF_CH4_INT_ST = 0x8
	// Position of OUTFIFO_OVF_L1_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_OVF_L1_CH4_INT_ST_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_OVF_L1_CH4_INT_ST_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_OVF_L1_CH4_INT_ST = 0x10
	// Position of OUTFIFO_UDF_L1_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_UDF_L1_CH4_INT_ST_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_UDF_L1_CH4_INT_ST_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_UDF_L1_CH4_INT_ST = 0x20
	// Position of OUTFIFO_OVF_L2_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_OVF_L2_CH4_INT_ST_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_OVF_L2_CH4_INT_ST_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_OVF_L2_CH4_INT_ST = 0x40
	// Position of OUTFIFO_UDF_L2_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_UDF_L2_CH4_INT_ST_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_UDF_L2_CH4_INT_ST_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUTFIFO_UDF_L2_CH4_INT_ST = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ST_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH4_INT_ST field.
	H264_DMA_OUT_INT_ST_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ST_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH4_INT_ST.
	H264_DMA_OUT_INT_ST_CH4_OUT_DSCR_TASK_OVF_CH4_INT_ST = 0x100

	// OUT_INT_CLR_CH4: TX CH4 interrupt clr register
	// Position of OUT_DONE_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DONE_CH4_INT_CLR_Pos = 0x0
	// Bit mask of OUT_DONE_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DONE_CH4_INT_CLR_Msk = 0x1
	// Bit OUT_DONE_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DONE_CH4_INT_CLR = 0x1
	// Position of OUT_EOF_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_EOF_CH4_INT_CLR_Pos = 0x1
	// Bit mask of OUT_EOF_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_EOF_CH4_INT_CLR_Msk = 0x2
	// Bit OUT_EOF_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUT_EOF_CH4_INT_CLR = 0x2
	// Position of OUT_DSCR_ERR_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DSCR_ERR_CH4_INT_CLR_Pos = 0x2
	// Bit mask of OUT_DSCR_ERR_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DSCR_ERR_CH4_INT_CLR_Msk = 0x4
	// Bit OUT_DSCR_ERR_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DSCR_ERR_CH4_INT_CLR = 0x4
	// Position of OUT_TOTAL_EOF_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_TOTAL_EOF_CH4_INT_CLR_Pos = 0x3
	// Bit mask of OUT_TOTAL_EOF_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_TOTAL_EOF_CH4_INT_CLR_Msk = 0x8
	// Bit OUT_TOTAL_EOF_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUT_TOTAL_EOF_CH4_INT_CLR = 0x8
	// Position of OUTFIFO_OVF_L1_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_OVF_L1_CH4_INT_CLR_Pos = 0x4
	// Bit mask of OUTFIFO_OVF_L1_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_OVF_L1_CH4_INT_CLR_Msk = 0x10
	// Bit OUTFIFO_OVF_L1_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_OVF_L1_CH4_INT_CLR = 0x10
	// Position of OUTFIFO_UDF_L1_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_UDF_L1_CH4_INT_CLR_Pos = 0x5
	// Bit mask of OUTFIFO_UDF_L1_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_UDF_L1_CH4_INT_CLR_Msk = 0x20
	// Bit OUTFIFO_UDF_L1_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_UDF_L1_CH4_INT_CLR = 0x20
	// Position of OUTFIFO_OVF_L2_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_OVF_L2_CH4_INT_CLR_Pos = 0x6
	// Bit mask of OUTFIFO_OVF_L2_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_OVF_L2_CH4_INT_CLR_Msk = 0x40
	// Bit OUTFIFO_OVF_L2_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_OVF_L2_CH4_INT_CLR = 0x40
	// Position of OUTFIFO_UDF_L2_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_UDF_L2_CH4_INT_CLR_Pos = 0x7
	// Bit mask of OUTFIFO_UDF_L2_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_UDF_L2_CH4_INT_CLR_Msk = 0x80
	// Bit OUTFIFO_UDF_L2_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUTFIFO_UDF_L2_CH4_INT_CLR = 0x80
	// Position of OUT_DSCR_TASK_OVF_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DSCR_TASK_OVF_CH4_INT_CLR_Pos = 0x8
	// Bit mask of OUT_DSCR_TASK_OVF_CH4_INT_CLR field.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DSCR_TASK_OVF_CH4_INT_CLR_Msk = 0x100
	// Bit OUT_DSCR_TASK_OVF_CH4_INT_CLR.
	H264_DMA_OUT_INT_CLR_CH4_OUT_DSCR_TASK_OVF_CH4_INT_CLR = 0x100

	// OUTFIFO_STATUS_CH4: TX CH4 outfifo status register
	// Position of OUTFIFO_FULL_L2_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2_CH4_Pos = 0x0
	// Bit mask of OUTFIFO_FULL_L2_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2_CH4_Msk = 0x1
	// Bit OUTFIFO_FULL_L2_CH4.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L2_CH4 = 0x1
	// Position of OUTFIFO_EMPTY_L2_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2_CH4_Pos = 0x1
	// Bit mask of OUTFIFO_EMPTY_L2_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2_CH4_Msk = 0x2
	// Bit OUTFIFO_EMPTY_L2_CH4.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L2_CH4 = 0x2
	// Position of OUTFIFO_CNT_L2_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2_CH4_Pos = 0x2
	// Bit mask of OUTFIFO_CNT_L2_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_CNT_L2_CH4_Msk = 0x3c
	// Position of OUTFIFO_FULL_L1_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1_CH4_Pos = 0x6
	// Bit mask of OUTFIFO_FULL_L1_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1_CH4_Msk = 0x40
	// Bit OUTFIFO_FULL_L1_CH4.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L1_CH4 = 0x40
	// Position of OUTFIFO_EMPTY_L1_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1_CH4_Pos = 0x7
	// Bit mask of OUTFIFO_EMPTY_L1_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1_CH4_Msk = 0x80
	// Bit OUTFIFO_EMPTY_L1_CH4.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L1_CH4 = 0x80
	// Position of OUTFIFO_CNT_L1_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1_CH4_Pos = 0x8
	// Bit mask of OUTFIFO_CNT_L1_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_CNT_L1_CH4_Msk = 0x1f00
	// Position of OUTFIFO_FULL_L3_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3_CH4_Pos = 0x10
	// Bit mask of OUTFIFO_FULL_L3_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3_CH4_Msk = 0x10000
	// Bit OUTFIFO_FULL_L3_CH4.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_FULL_L3_CH4 = 0x10000
	// Position of OUTFIFO_EMPTY_L3_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3_CH4_Pos = 0x11
	// Bit mask of OUTFIFO_EMPTY_L3_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3_CH4_Msk = 0x20000
	// Bit OUTFIFO_EMPTY_L3_CH4.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_EMPTY_L3_CH4 = 0x20000
	// Position of OUTFIFO_CNT_L3_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3_CH4_Pos = 0x12
	// Bit mask of OUTFIFO_CNT_L3_CH4 field.
	H264_DMA_OUTFIFO_STATUS_CH4_OUTFIFO_CNT_L3_CH4_Msk = 0xc0000

	// OUT_PUSH_CH4: TX CH4 outfifo push register
	// Position of OUTFIFO_WDATA_CH4 field.
	H264_DMA_OUT_PUSH_CH4_OUTFIFO_WDATA_CH4_Pos = 0x0
	// Bit mask of OUTFIFO_WDATA_CH4 field.
	H264_DMA_OUT_PUSH_CH4_OUTFIFO_WDATA_CH4_Msk = 0x3ff
	// Position of OUTFIFO_PUSH_CH4 field.
	H264_DMA_OUT_PUSH_CH4_OUTFIFO_PUSH_CH4_Pos = 0xa
	// Bit mask of OUTFIFO_PUSH_CH4 field.
	H264_DMA_OUT_PUSH_CH4_OUTFIFO_PUSH_CH4_Msk = 0x400
	// Bit OUTFIFO_PUSH_CH4.
	H264_DMA_OUT_PUSH_CH4_OUTFIFO_PUSH_CH4 = 0x400

	// OUT_LINK_CONF_CH4: TX CH4 out_link dscr ctrl register
	// Position of OUTLINK_STOP_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_STOP_CH4_Pos = 0x14
	// Bit mask of OUTLINK_STOP_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_STOP_CH4_Msk = 0x100000
	// Bit OUTLINK_STOP_CH4.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_STOP_CH4 = 0x100000
	// Position of OUTLINK_START_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_START_CH4_Pos = 0x15
	// Bit mask of OUTLINK_START_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_START_CH4_Msk = 0x200000
	// Bit OUTLINK_START_CH4.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_START_CH4 = 0x200000
	// Position of OUTLINK_RESTART_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_RESTART_CH4_Pos = 0x16
	// Bit mask of OUTLINK_RESTART_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_RESTART_CH4_Msk = 0x400000
	// Bit OUTLINK_RESTART_CH4.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_RESTART_CH4 = 0x400000
	// Position of OUTLINK_PARK_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_PARK_CH4_Pos = 0x17
	// Bit mask of OUTLINK_PARK_CH4 field.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_PARK_CH4_Msk = 0x800000
	// Bit OUTLINK_PARK_CH4.
	H264_DMA_OUT_LINK_CONF_CH4_OUTLINK_PARK_CH4 = 0x800000

	// OUT_LINK_ADDR_CH4: TX CH4 out_link dscr addr register
	// Position of OUTLINK_ADDR_CH4 field.
	H264_DMA_OUT_LINK_ADDR_CH4_OUTLINK_ADDR_CH4_Pos = 0x0
	// Bit mask of OUTLINK_ADDR_CH4 field.
	H264_DMA_OUT_LINK_ADDR_CH4_OUTLINK_ADDR_CH4_Msk = 0xffffffff

	// OUT_STATE_CH4: TX CH4 state register
	// Position of OUTLINK_DSCR_ADDR_CH4 field.
	H264_DMA_OUT_STATE_CH4_OUTLINK_DSCR_ADDR_CH4_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_ADDR_CH4 field.
	H264_DMA_OUT_STATE_CH4_OUTLINK_DSCR_ADDR_CH4_Msk = 0x3ffff
	// Position of OUT_DSCR_STATE_CH4 field.
	H264_DMA_OUT_STATE_CH4_OUT_DSCR_STATE_CH4_Pos = 0x12
	// Bit mask of OUT_DSCR_STATE_CH4 field.
	H264_DMA_OUT_STATE_CH4_OUT_DSCR_STATE_CH4_Msk = 0xc0000
	// Position of OUT_STATE_CH4 field.
	H264_DMA_OUT_STATE_CH4_OUT_STATE_CH4_Pos = 0x14
	// Bit mask of OUT_STATE_CH4 field.
	H264_DMA_OUT_STATE_CH4_OUT_STATE_CH4_Msk = 0xf00000

	// OUT_EOF_DES_ADDR_CH4: TX CH4 eof des addr register
	// Position of OUT_EOF_DES_ADDR_CH4 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH4_OUT_EOF_DES_ADDR_CH4_Pos = 0x0
	// Bit mask of OUT_EOF_DES_ADDR_CH4 field.
	H264_DMA_OUT_EOF_DES_ADDR_CH4_OUT_EOF_DES_ADDR_CH4_Msk = 0xffffffff

	// OUT_DSCR_CH4: TX CH4 next dscr addr register
	// Position of OUTLINK_DSCR_CH4 field.
	H264_DMA_OUT_DSCR_CH4_OUTLINK_DSCR_CH4_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_CH4 field.
	H264_DMA_OUT_DSCR_CH4_OUTLINK_DSCR_CH4_Msk = 0xffffffff

	// OUT_DSCR_BF0_CH4: TX CH4 last dscr addr register
	// Position of OUTLINK_DSCR_BF0_CH4 field.
	H264_DMA_OUT_DSCR_BF0_CH4_OUTLINK_DSCR_BF0_CH4_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF0_CH4 field.
	H264_DMA_OUT_DSCR_BF0_CH4_OUTLINK_DSCR_BF0_CH4_Msk = 0xffffffff

	// OUT_DSCR_BF1_CH4: TX CH4 second-to-last dscr addr register
	// Position of OUTLINK_DSCR_BF1_CH4 field.
	H264_DMA_OUT_DSCR_BF1_CH4_OUTLINK_DSCR_BF1_CH4_Pos = 0x0
	// Bit mask of OUTLINK_DSCR_BF1_CH4 field.
	H264_DMA_OUT_DSCR_BF1_CH4_OUTLINK_DSCR_BF1_CH4_Msk = 0xffffffff

	// OUT_ARB_CH4: TX CH4 arb register
	// Position of OUT_ARB_TOKEN_NUM_CH4 field.
	H264_DMA_OUT_ARB_CH4_OUT_ARB_TOKEN_NUM_CH4_Pos = 0x0
	// Bit mask of OUT_ARB_TOKEN_NUM_CH4 field.
	H264_DMA_OUT_ARB_CH4_OUT_ARB_TOKEN_NUM_CH4_Msk = 0xf
	// Position of EXTER_OUT_ARB_PRIORITY_CH4 field.
	H264_DMA_OUT_ARB_CH4_EXTER_OUT_ARB_PRIORITY_CH4_Pos = 0x4
	// Bit mask of EXTER_OUT_ARB_PRIORITY_CH4 field.
	H264_DMA_OUT_ARB_CH4_EXTER_OUT_ARB_PRIORITY_CH4_Msk = 0x30

	// OUT_ETM_CONF_CH4: TX CH4 ETM config register
	// Position of OUT_ETM_EN_CH4 field.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_ETM_EN_CH4_Pos = 0x0
	// Bit mask of OUT_ETM_EN_CH4 field.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_ETM_EN_CH4_Msk = 0x1
	// Bit OUT_ETM_EN_CH4.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_ETM_EN_CH4 = 0x1
	// Position of OUT_ETM_LOOP_EN_CH4 field.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_ETM_LOOP_EN_CH4_Pos = 0x1
	// Bit mask of OUT_ETM_LOOP_EN_CH4 field.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_ETM_LOOP_EN_CH4_Msk = 0x2
	// Bit OUT_ETM_LOOP_EN_CH4.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_ETM_LOOP_EN_CH4 = 0x2
	// Position of OUT_DSCR_TASK_MAK_CH4 field.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_DSCR_TASK_MAK_CH4_Pos = 0x2
	// Bit mask of OUT_DSCR_TASK_MAK_CH4 field.
	H264_DMA_OUT_ETM_CONF_CH4_OUT_DSCR_TASK_MAK_CH4_Msk = 0xc

	// OUT_BUF_LEN_CH4: tx CH4 buf len register
	// Position of OUT_CMDFIFO_BUF_LEN_HB_CH4 field.
	H264_DMA_OUT_BUF_LEN_CH4_OUT_CMDFIFO_BUF_LEN_HB_CH4_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_BUF_LEN_HB_CH4 field.
	H264_DMA_OUT_BUF_LEN_CH4_OUT_CMDFIFO_BUF_LEN_HB_CH4_Msk = 0x1fff

	// OUT_FIFO_BCNT_CH4: tx CH4 fifo byte cnt register
	// Position of OUT_CMDFIFO_OUTFIFO_BCNT_CH4 field.
	H264_DMA_OUT_FIFO_BCNT_CH4_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_OUTFIFO_BCNT_CH4 field.
	H264_DMA_OUT_FIFO_BCNT_CH4_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_Msk = 0x3ff

	// OUT_PUSH_BYTECNT_CH4: tx CH4 push byte cnt register
	// Position of OUT_CMDFIFO_PUSH_BYTECNT_CH4 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH4_OUT_CMDFIFO_PUSH_BYTECNT_CH4_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_PUSH_BYTECNT_CH4 field.
	H264_DMA_OUT_PUSH_BYTECNT_CH4_OUT_CMDFIFO_PUSH_BYTECNT_CH4_Msk = 0xff

	// OUT_XADDR_CH4: tx CH4 xaddr register
	// Position of OUT_CMDFIFO_XADDR_CH4 field.
	H264_DMA_OUT_XADDR_CH4_OUT_CMDFIFO_XADDR_CH4_Pos = 0x0
	// Bit mask of OUT_CMDFIFO_XADDR_CH4 field.
	H264_DMA_OUT_XADDR_CH4_OUT_CMDFIFO_XADDR_CH4_Msk = 0xffffffff

	// OUT_BLOCK_BUF_LEN_CH4: tx CH4 block buf len register
	// Position of OUT_BLOCK_BUF_LEN_CH4 field.
	H264_DMA_OUT_BLOCK_BUF_LEN_CH4_OUT_BLOCK_BUF_LEN_CH4_Pos = 0x0
	// Bit mask of OUT_BLOCK_BUF_LEN_CH4 field.
	H264_DMA_OUT_BLOCK_BUF_LEN_CH4_OUT_BLOCK_BUF_LEN_CH4_Msk = 0xfffffff

	// IN_CONF0_CH0: RX CH0 config0 register
	// Position of INDSCR_BURST_EN_CH0 field.
	H264_DMA_IN_CONF0_CH0_INDSCR_BURST_EN_CH0_Pos = 0x2
	// Bit mask of INDSCR_BURST_EN_CH0 field.
	H264_DMA_IN_CONF0_CH0_INDSCR_BURST_EN_CH0_Msk = 0x4
	// Bit INDSCR_BURST_EN_CH0.
	H264_DMA_IN_CONF0_CH0_INDSCR_BURST_EN_CH0 = 0x4
	// Position of IN_ECC_AES_EN_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_ECC_AES_EN_CH0_Pos = 0x3
	// Bit mask of IN_ECC_AES_EN_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_ECC_AES_EN_CH0_Msk = 0x8
	// Bit IN_ECC_AES_EN_CH0.
	H264_DMA_IN_CONF0_CH0_IN_ECC_AES_EN_CH0 = 0x8
	// Position of IN_CHECK_OWNER_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_CHECK_OWNER_CH0_Pos = 0x4
	// Bit mask of IN_CHECK_OWNER_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_CHECK_OWNER_CH0_Msk = 0x10
	// Bit IN_CHECK_OWNER_CH0.
	H264_DMA_IN_CONF0_CH0_IN_CHECK_OWNER_CH0 = 0x10
	// Position of IN_MEM_BURST_LENGTH_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_MEM_BURST_LENGTH_CH0_Pos = 0x6
	// Bit mask of IN_MEM_BURST_LENGTH_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_MEM_BURST_LENGTH_CH0_Msk = 0x1c0
	// Position of IN_PAGE_BOUND_EN_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_PAGE_BOUND_EN_CH0_Pos = 0xc
	// Bit mask of IN_PAGE_BOUND_EN_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_PAGE_BOUND_EN_CH0_Msk = 0x1000
	// Bit IN_PAGE_BOUND_EN_CH0.
	H264_DMA_IN_CONF0_CH0_IN_PAGE_BOUND_EN_CH0 = 0x1000
	// Position of IN_RST_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_RST_CH0_Pos = 0x18
	// Bit mask of IN_RST_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_RST_CH0_Msk = 0x1000000
	// Bit IN_RST_CH0.
	H264_DMA_IN_CONF0_CH0_IN_RST_CH0 = 0x1000000
	// Position of IN_CMD_DISABLE_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_CMD_DISABLE_CH0_Pos = 0x19
	// Bit mask of IN_CMD_DISABLE_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_CMD_DISABLE_CH0_Msk = 0x2000000
	// Bit IN_CMD_DISABLE_CH0.
	H264_DMA_IN_CONF0_CH0_IN_CMD_DISABLE_CH0 = 0x2000000
	// Position of IN_ARB_WEIGHT_OPT_DIS_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_ARB_WEIGHT_OPT_DIS_CH0_Pos = 0x1a
	// Bit mask of IN_ARB_WEIGHT_OPT_DIS_CH0 field.
	H264_DMA_IN_CONF0_CH0_IN_ARB_WEIGHT_OPT_DIS_CH0_Msk = 0x4000000
	// Bit IN_ARB_WEIGHT_OPT_DIS_CH0.
	H264_DMA_IN_CONF0_CH0_IN_ARB_WEIGHT_OPT_DIS_CH0 = 0x4000000

	// IN_INT_RAW_CH0: RX CH0 interrupt raw register
	// Position of IN_DONE_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DONE_CH0_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DONE_CH0_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_IN_DONE_CH0_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_SUC_EOF_CH0_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_SUC_EOF_CH0_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_IN_SUC_EOF_CH0_INT_RAW = 0x2
	// Position of IN_ERR_EOF_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_ERR_EOF_CH0_INT_RAW_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_ERR_EOF_CH0_INT_RAW_Msk = 0x4
	// Bit IN_ERR_EOF_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_IN_ERR_EOF_CH0_INT_RAW = 0x4
	// Position of IN_DSCR_ERR_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_ERR_CH0_INT_RAW_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_ERR_CH0_INT_RAW_Msk = 0x8
	// Bit IN_DSCR_ERR_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_ERR_CH0_INT_RAW = 0x8
	// Position of INFIFO_OVF_L1_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_OVF_L1_CH0_INT_RAW_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_OVF_L1_CH0_INT_RAW_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_OVF_L1_CH0_INT_RAW = 0x10
	// Position of INFIFO_UDF_L1_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_UDF_L1_CH0_INT_RAW_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_UDF_L1_CH0_INT_RAW_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_UDF_L1_CH0_INT_RAW = 0x20
	// Position of INFIFO_OVF_L2_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_OVF_L2_CH0_INT_RAW_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_OVF_L2_CH0_INT_RAW_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_OVF_L2_CH0_INT_RAW = 0x40
	// Position of INFIFO_UDF_L2_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_UDF_L2_CH0_INT_RAW_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_UDF_L2_CH0_INT_RAW_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_INFIFO_UDF_L2_CH0_INT_RAW = 0x80
	// Position of IN_DSCR_EMPTY_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_EMPTY_CH0_INT_RAW_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_EMPTY_CH0_INT_RAW_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_EMPTY_CH0_INT_RAW = 0x100
	// Position of IN_DSCR_TASK_OVF_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_TASK_OVF_CH0_INT_RAW_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH0_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_TASK_OVF_CH0_INT_RAW_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH0_INT_RAW.
	H264_DMA_IN_INT_RAW_CH0_IN_DSCR_TASK_OVF_CH0_INT_RAW = 0x200

	// IN_INT_ENA_CH0: RX CH0 interrupt ena register
	// Position of IN_DONE_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DONE_CH0_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DONE_CH0_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_IN_DONE_CH0_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_SUC_EOF_CH0_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_SUC_EOF_CH0_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_IN_SUC_EOF_CH0_INT_ENA = 0x2
	// Position of IN_ERR_EOF_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_ERR_EOF_CH0_INT_ENA_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_ERR_EOF_CH0_INT_ENA_Msk = 0x4
	// Bit IN_ERR_EOF_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_IN_ERR_EOF_CH0_INT_ENA = 0x4
	// Position of IN_DSCR_ERR_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_ERR_CH0_INT_ENA_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_ERR_CH0_INT_ENA_Msk = 0x8
	// Bit IN_DSCR_ERR_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_ERR_CH0_INT_ENA = 0x8
	// Position of INFIFO_OVF_L1_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_OVF_L1_CH0_INT_ENA_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_OVF_L1_CH0_INT_ENA_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_OVF_L1_CH0_INT_ENA = 0x10
	// Position of INFIFO_UDF_L1_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_UDF_L1_CH0_INT_ENA_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_UDF_L1_CH0_INT_ENA_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_UDF_L1_CH0_INT_ENA = 0x20
	// Position of INFIFO_OVF_L2_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_OVF_L2_CH0_INT_ENA_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_OVF_L2_CH0_INT_ENA_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_OVF_L2_CH0_INT_ENA = 0x40
	// Position of INFIFO_UDF_L2_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_UDF_L2_CH0_INT_ENA_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_UDF_L2_CH0_INT_ENA_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_INFIFO_UDF_L2_CH0_INT_ENA = 0x80
	// Position of IN_DSCR_EMPTY_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_EMPTY_CH0_INT_ENA_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_EMPTY_CH0_INT_ENA_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_EMPTY_CH0_INT_ENA = 0x100
	// Position of IN_DSCR_TASK_OVF_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_TASK_OVF_CH0_INT_ENA_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH0_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_TASK_OVF_CH0_INT_ENA_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH0_INT_ENA.
	H264_DMA_IN_INT_ENA_CH0_IN_DSCR_TASK_OVF_CH0_INT_ENA = 0x200

	// IN_INT_ST_CH0: RX CH0 interrupt st register
	// Position of IN_DONE_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DONE_CH0_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DONE_CH0_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_IN_DONE_CH0_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_SUC_EOF_CH0_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_SUC_EOF_CH0_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_IN_SUC_EOF_CH0_INT_ST = 0x2
	// Position of IN_ERR_EOF_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_ERR_EOF_CH0_INT_ST_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_ERR_EOF_CH0_INT_ST_Msk = 0x4
	// Bit IN_ERR_EOF_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_IN_ERR_EOF_CH0_INT_ST = 0x4
	// Position of IN_DSCR_ERR_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_ERR_CH0_INT_ST_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_ERR_CH0_INT_ST_Msk = 0x8
	// Bit IN_DSCR_ERR_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_ERR_CH0_INT_ST = 0x8
	// Position of INFIFO_OVF_L1_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_OVF_L1_CH0_INT_ST_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_OVF_L1_CH0_INT_ST_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_INFIFO_OVF_L1_CH0_INT_ST = 0x10
	// Position of INFIFO_UDF_L1_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_UDF_L1_CH0_INT_ST_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_UDF_L1_CH0_INT_ST_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_INFIFO_UDF_L1_CH0_INT_ST = 0x20
	// Position of INFIFO_OVF_L2_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_OVF_L2_CH0_INT_ST_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_OVF_L2_CH0_INT_ST_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_INFIFO_OVF_L2_CH0_INT_ST = 0x40
	// Position of INFIFO_UDF_L2_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_UDF_L2_CH0_INT_ST_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_INFIFO_UDF_L2_CH0_INT_ST_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_INFIFO_UDF_L2_CH0_INT_ST = 0x80
	// Position of IN_DSCR_EMPTY_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_EMPTY_CH0_INT_ST_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_EMPTY_CH0_INT_ST_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_EMPTY_CH0_INT_ST = 0x100
	// Position of IN_DSCR_TASK_OVF_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_TASK_OVF_CH0_INT_ST_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH0_INT_ST field.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_TASK_OVF_CH0_INT_ST_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH0_INT_ST.
	H264_DMA_IN_INT_ST_CH0_IN_DSCR_TASK_OVF_CH0_INT_ST = 0x200

	// IN_INT_CLR_CH0: RX CH0 interrupt clr register
	// Position of IN_DONE_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DONE_CH0_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DONE_CH0_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_IN_DONE_CH0_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_SUC_EOF_CH0_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_SUC_EOF_CH0_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_IN_SUC_EOF_CH0_INT_CLR = 0x2
	// Position of IN_ERR_EOF_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_ERR_EOF_CH0_INT_CLR_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_ERR_EOF_CH0_INT_CLR_Msk = 0x4
	// Bit IN_ERR_EOF_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_IN_ERR_EOF_CH0_INT_CLR = 0x4
	// Position of IN_DSCR_ERR_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_ERR_CH0_INT_CLR_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_ERR_CH0_INT_CLR_Msk = 0x8
	// Bit IN_DSCR_ERR_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_ERR_CH0_INT_CLR = 0x8
	// Position of INFIFO_OVF_L1_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_OVF_L1_CH0_INT_CLR_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_OVF_L1_CH0_INT_CLR_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_OVF_L1_CH0_INT_CLR = 0x10
	// Position of INFIFO_UDF_L1_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_UDF_L1_CH0_INT_CLR_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_UDF_L1_CH0_INT_CLR_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_UDF_L1_CH0_INT_CLR = 0x20
	// Position of INFIFO_OVF_L2_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_OVF_L2_CH0_INT_CLR_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_OVF_L2_CH0_INT_CLR_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_OVF_L2_CH0_INT_CLR = 0x40
	// Position of INFIFO_UDF_L2_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_UDF_L2_CH0_INT_CLR_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_UDF_L2_CH0_INT_CLR_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_INFIFO_UDF_L2_CH0_INT_CLR = 0x80
	// Position of IN_DSCR_EMPTY_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_EMPTY_CH0_INT_CLR_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_EMPTY_CH0_INT_CLR_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_EMPTY_CH0_INT_CLR = 0x100
	// Position of IN_DSCR_TASK_OVF_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_TASK_OVF_CH0_INT_CLR_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH0_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_TASK_OVF_CH0_INT_CLR_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH0_INT_CLR.
	H264_DMA_IN_INT_CLR_CH0_IN_DSCR_TASK_OVF_CH0_INT_CLR = 0x200

	// INFIFO_STATUS_CH0: RX CH0 INFIFO status register
	// Position of INFIFO_FULL_L2_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L2_CH0_Pos = 0x0
	// Bit mask of INFIFO_FULL_L2_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L2_CH0_Msk = 0x1
	// Bit INFIFO_FULL_L2_CH0.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L2_CH0 = 0x1
	// Position of INFIFO_EMPTY_L2_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L2_CH0_Pos = 0x1
	// Bit mask of INFIFO_EMPTY_L2_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L2_CH0_Msk = 0x2
	// Bit INFIFO_EMPTY_L2_CH0.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L2_CH0 = 0x2
	// Position of INFIFO_CNT_L2_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_CNT_L2_CH0_Pos = 0x2
	// Bit mask of INFIFO_CNT_L2_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_CNT_L2_CH0_Msk = 0x3c
	// Position of INFIFO_FULL_L1_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L1_CH0_Pos = 0x6
	// Bit mask of INFIFO_FULL_L1_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L1_CH0_Msk = 0x40
	// Bit INFIFO_FULL_L1_CH0.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L1_CH0 = 0x40
	// Position of INFIFO_EMPTY_L1_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L1_CH0_Pos = 0x7
	// Bit mask of INFIFO_EMPTY_L1_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L1_CH0_Msk = 0x80
	// Bit INFIFO_EMPTY_L1_CH0.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L1_CH0 = 0x80
	// Position of INFIFO_CNT_L1_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_CNT_L1_CH0_Pos = 0x8
	// Bit mask of INFIFO_CNT_L1_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_CNT_L1_CH0_Msk = 0x1f00
	// Position of INFIFO_FULL_L3_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L3_CH0_Pos = 0x10
	// Bit mask of INFIFO_FULL_L3_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L3_CH0_Msk = 0x10000
	// Bit INFIFO_FULL_L3_CH0.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_FULL_L3_CH0 = 0x10000
	// Position of INFIFO_EMPTY_L3_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L3_CH0_Pos = 0x11
	// Bit mask of INFIFO_EMPTY_L3_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L3_CH0_Msk = 0x20000
	// Bit INFIFO_EMPTY_L3_CH0.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_EMPTY_L3_CH0 = 0x20000
	// Position of INFIFO_CNT_L3_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_CNT_L3_CH0_Pos = 0x12
	// Bit mask of INFIFO_CNT_L3_CH0 field.
	H264_DMA_INFIFO_STATUS_CH0_INFIFO_CNT_L3_CH0_Msk = 0xc0000

	// IN_POP_CH0: RX CH0 INFIFO pop register
	// Position of INFIFO_RDATA_CH0 field.
	H264_DMA_IN_POP_CH0_INFIFO_RDATA_CH0_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH0 field.
	H264_DMA_IN_POP_CH0_INFIFO_RDATA_CH0_Msk = 0x7ff
	// Position of INFIFO_POP_CH0 field.
	H264_DMA_IN_POP_CH0_INFIFO_POP_CH0_Pos = 0xb
	// Bit mask of INFIFO_POP_CH0 field.
	H264_DMA_IN_POP_CH0_INFIFO_POP_CH0_Msk = 0x800
	// Bit INFIFO_POP_CH0.
	H264_DMA_IN_POP_CH0_INFIFO_POP_CH0 = 0x800

	// IN_LINK_CONF_CH0: RX CH0 in_link dscr ctrl register
	// Position of INLINK_AUTO_RET_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_AUTO_RET_CH0_Pos = 0x14
	// Bit mask of INLINK_AUTO_RET_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_AUTO_RET_CH0_Msk = 0x100000
	// Bit INLINK_AUTO_RET_CH0.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_AUTO_RET_CH0 = 0x100000
	// Position of INLINK_STOP_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_STOP_CH0_Pos = 0x15
	// Bit mask of INLINK_STOP_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_STOP_CH0_Msk = 0x200000
	// Bit INLINK_STOP_CH0.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_STOP_CH0 = 0x200000
	// Position of INLINK_START_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_START_CH0_Pos = 0x16
	// Bit mask of INLINK_START_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_START_CH0_Msk = 0x400000
	// Bit INLINK_START_CH0.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_START_CH0 = 0x400000
	// Position of INLINK_RESTART_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_RESTART_CH0_Pos = 0x17
	// Bit mask of INLINK_RESTART_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_RESTART_CH0_Msk = 0x800000
	// Bit INLINK_RESTART_CH0.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_RESTART_CH0 = 0x800000
	// Position of INLINK_PARK_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_PARK_CH0_Pos = 0x18
	// Bit mask of INLINK_PARK_CH0 field.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_PARK_CH0_Msk = 0x1000000
	// Bit INLINK_PARK_CH0.
	H264_DMA_IN_LINK_CONF_CH0_INLINK_PARK_CH0 = 0x1000000

	// IN_LINK_ADDR_CH0: RX CH0 in_link dscr addr register
	// Position of INLINK_ADDR_CH0 field.
	H264_DMA_IN_LINK_ADDR_CH0_INLINK_ADDR_CH0_Pos = 0x0
	// Bit mask of INLINK_ADDR_CH0 field.
	H264_DMA_IN_LINK_ADDR_CH0_INLINK_ADDR_CH0_Msk = 0xffffffff

	// IN_STATE_CH0: RX CH0 state register
	// Position of INLINK_DSCR_ADDR_CH0 field.
	H264_DMA_IN_STATE_CH0_INLINK_DSCR_ADDR_CH0_Pos = 0x0
	// Bit mask of INLINK_DSCR_ADDR_CH0 field.
	H264_DMA_IN_STATE_CH0_INLINK_DSCR_ADDR_CH0_Msk = 0x3ffff
	// Position of IN_DSCR_STATE_CH0 field.
	H264_DMA_IN_STATE_CH0_IN_DSCR_STATE_CH0_Pos = 0x12
	// Bit mask of IN_DSCR_STATE_CH0 field.
	H264_DMA_IN_STATE_CH0_IN_DSCR_STATE_CH0_Msk = 0xc0000
	// Position of IN_STATE_CH0 field.
	H264_DMA_IN_STATE_CH0_IN_STATE_CH0_Pos = 0x14
	// Bit mask of IN_STATE_CH0 field.
	H264_DMA_IN_STATE_CH0_IN_STATE_CH0_Msk = 0x700000
	// Position of IN_RESET_AVAIL_CH0 field.
	H264_DMA_IN_STATE_CH0_IN_RESET_AVAIL_CH0_Pos = 0x17
	// Bit mask of IN_RESET_AVAIL_CH0 field.
	H264_DMA_IN_STATE_CH0_IN_RESET_AVAIL_CH0_Msk = 0x800000
	// Bit IN_RESET_AVAIL_CH0.
	H264_DMA_IN_STATE_CH0_IN_RESET_AVAIL_CH0 = 0x800000

	// IN_SUC_EOF_DES_ADDR_CH0: RX CH0 eof des addr register
	// Position of IN_SUC_EOF_DES_ADDR_CH0 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_IN_SUC_EOF_DES_ADDR_CH0_Pos = 0x0
	// Bit mask of IN_SUC_EOF_DES_ADDR_CH0 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_IN_SUC_EOF_DES_ADDR_CH0_Msk = 0xffffffff

	// IN_ERR_EOF_DES_ADDR_CH0: RX CH0 err eof des addr register
	// Position of IN_ERR_EOF_DES_ADDR_CH0 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_IN_ERR_EOF_DES_ADDR_CH0_Pos = 0x0
	// Bit mask of IN_ERR_EOF_DES_ADDR_CH0 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_IN_ERR_EOF_DES_ADDR_CH0_Msk = 0xffffffff

	// IN_DSCR_CH0: RX CH0 next dscr addr register
	// Position of INLINK_DSCR_CH0 field.
	H264_DMA_IN_DSCR_CH0_INLINK_DSCR_CH0_Pos = 0x0
	// Bit mask of INLINK_DSCR_CH0 field.
	H264_DMA_IN_DSCR_CH0_INLINK_DSCR_CH0_Msk = 0xffffffff

	// IN_DSCR_BF0_CH0: RX CH0 last dscr addr register
	// Position of INLINK_DSCR_BF0_CH0 field.
	H264_DMA_IN_DSCR_BF0_CH0_INLINK_DSCR_BF0_CH0_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF0_CH0 field.
	H264_DMA_IN_DSCR_BF0_CH0_INLINK_DSCR_BF0_CH0_Msk = 0xffffffff

	// IN_DSCR_BF1_CH0: RX CH0 second-to-last dscr addr register
	// Position of INLINK_DSCR_BF1_CH0 field.
	H264_DMA_IN_DSCR_BF1_CH0_INLINK_DSCR_BF1_CH0_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF1_CH0 field.
	H264_DMA_IN_DSCR_BF1_CH0_INLINK_DSCR_BF1_CH0_Msk = 0xffffffff

	// IN_ARB_CH0: RX CH0 arb register
	// Position of IN_ARB_TOKEN_NUM_CH0 field.
	H264_DMA_IN_ARB_CH0_IN_ARB_TOKEN_NUM_CH0_Pos = 0x0
	// Bit mask of IN_ARB_TOKEN_NUM_CH0 field.
	H264_DMA_IN_ARB_CH0_IN_ARB_TOKEN_NUM_CH0_Msk = 0xf
	// Position of EXTER_IN_ARB_PRIORITY_CH0 field.
	H264_DMA_IN_ARB_CH0_EXTER_IN_ARB_PRIORITY_CH0_Pos = 0x4
	// Bit mask of EXTER_IN_ARB_PRIORITY_CH0 field.
	H264_DMA_IN_ARB_CH0_EXTER_IN_ARB_PRIORITY_CH0_Msk = 0x30
	// Position of INTER_IN_ARB_PRIORITY_CH0 field.
	H264_DMA_IN_ARB_CH0_INTER_IN_ARB_PRIORITY_CH0_Pos = 0x6
	// Bit mask of INTER_IN_ARB_PRIORITY_CH0 field.
	H264_DMA_IN_ARB_CH0_INTER_IN_ARB_PRIORITY_CH0_Msk = 0x1c0

	// IN_RO_PD_CONF_CH0: RX CH0 reorder power config register
	// Position of IN_RO_RAM_CLK_FO_CH0 field.
	H264_DMA_IN_RO_PD_CONF_CH0_IN_RO_RAM_CLK_FO_CH0_Pos = 0x6
	// Bit mask of IN_RO_RAM_CLK_FO_CH0 field.
	H264_DMA_IN_RO_PD_CONF_CH0_IN_RO_RAM_CLK_FO_CH0_Msk = 0x40
	// Bit IN_RO_RAM_CLK_FO_CH0.
	H264_DMA_IN_RO_PD_CONF_CH0_IN_RO_RAM_CLK_FO_CH0 = 0x40

	// IN_ETM_CONF_CH0: RX CH0 ETM config register
	// Position of IN_ETM_EN_CH0 field.
	H264_DMA_IN_ETM_CONF_CH0_IN_ETM_EN_CH0_Pos = 0x0
	// Bit mask of IN_ETM_EN_CH0 field.
	H264_DMA_IN_ETM_CONF_CH0_IN_ETM_EN_CH0_Msk = 0x1
	// Bit IN_ETM_EN_CH0.
	H264_DMA_IN_ETM_CONF_CH0_IN_ETM_EN_CH0 = 0x1
	// Position of IN_ETM_LOOP_EN_CH0 field.
	H264_DMA_IN_ETM_CONF_CH0_IN_ETM_LOOP_EN_CH0_Pos = 0x1
	// Bit mask of IN_ETM_LOOP_EN_CH0 field.
	H264_DMA_IN_ETM_CONF_CH0_IN_ETM_LOOP_EN_CH0_Msk = 0x2
	// Bit IN_ETM_LOOP_EN_CH0.
	H264_DMA_IN_ETM_CONF_CH0_IN_ETM_LOOP_EN_CH0 = 0x2
	// Position of IN_DSCR_TASK_MAK_CH0 field.
	H264_DMA_IN_ETM_CONF_CH0_IN_DSCR_TASK_MAK_CH0_Pos = 0x2
	// Bit mask of IN_DSCR_TASK_MAK_CH0 field.
	H264_DMA_IN_ETM_CONF_CH0_IN_DSCR_TASK_MAK_CH0_Msk = 0xc

	// IN_FIFO_CNT_CH0: rx CH0 fifo cnt register
	// Position of IN_CMDFIFO_INFIFO_CNT_CH0 field.
	H264_DMA_IN_FIFO_CNT_CH0_IN_CMDFIFO_INFIFO_CNT_CH0_Pos = 0x0
	// Bit mask of IN_CMDFIFO_INFIFO_CNT_CH0 field.
	H264_DMA_IN_FIFO_CNT_CH0_IN_CMDFIFO_INFIFO_CNT_CH0_Msk = 0x3ff

	// IN_POP_DATA_CNT_CH0: rx CH0 pop data cnt register
	// Position of IN_CMDFIFO_POP_DATA_CNT_CH0 field.
	H264_DMA_IN_POP_DATA_CNT_CH0_IN_CMDFIFO_POP_DATA_CNT_CH0_Pos = 0x0
	// Bit mask of IN_CMDFIFO_POP_DATA_CNT_CH0 field.
	H264_DMA_IN_POP_DATA_CNT_CH0_IN_CMDFIFO_POP_DATA_CNT_CH0_Msk = 0xff

	// IN_XADDR_CH0: rx CH0 xaddr register
	// Position of IN_CMDFIFO_XADDR_CH0 field.
	H264_DMA_IN_XADDR_CH0_IN_CMDFIFO_XADDR_CH0_Pos = 0x0
	// Bit mask of IN_CMDFIFO_XADDR_CH0 field.
	H264_DMA_IN_XADDR_CH0_IN_CMDFIFO_XADDR_CH0_Msk = 0xffffffff

	// IN_BUF_HB_RCV_CH0: rx CH0 buf len hb rcv register
	// Position of IN_CMDFIFO_BUF_HB_RCV_CH0 field.
	H264_DMA_IN_BUF_HB_RCV_CH0_IN_CMDFIFO_BUF_HB_RCV_CH0_Pos = 0x0
	// Bit mask of IN_CMDFIFO_BUF_HB_RCV_CH0 field.
	H264_DMA_IN_BUF_HB_RCV_CH0_IN_CMDFIFO_BUF_HB_RCV_CH0_Msk = 0x1fffffff

	// IN_CONF0_CH1: RX CH1 config0 register
	// Position of INDSCR_BURST_EN_CH1 field.
	H264_DMA_IN_CONF0_CH1_INDSCR_BURST_EN_CH1_Pos = 0x2
	// Bit mask of INDSCR_BURST_EN_CH1 field.
	H264_DMA_IN_CONF0_CH1_INDSCR_BURST_EN_CH1_Msk = 0x4
	// Bit INDSCR_BURST_EN_CH1.
	H264_DMA_IN_CONF0_CH1_INDSCR_BURST_EN_CH1 = 0x4
	// Position of IN_ECC_AES_EN_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_ECC_AES_EN_CH1_Pos = 0x3
	// Bit mask of IN_ECC_AES_EN_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_ECC_AES_EN_CH1_Msk = 0x8
	// Bit IN_ECC_AES_EN_CH1.
	H264_DMA_IN_CONF0_CH1_IN_ECC_AES_EN_CH1 = 0x8
	// Position of IN_CHECK_OWNER_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_CHECK_OWNER_CH1_Pos = 0x4
	// Bit mask of IN_CHECK_OWNER_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_CHECK_OWNER_CH1_Msk = 0x10
	// Bit IN_CHECK_OWNER_CH1.
	H264_DMA_IN_CONF0_CH1_IN_CHECK_OWNER_CH1 = 0x10
	// Position of IN_MEM_BURST_LENGTH_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_MEM_BURST_LENGTH_CH1_Pos = 0x6
	// Bit mask of IN_MEM_BURST_LENGTH_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_MEM_BURST_LENGTH_CH1_Msk = 0x1c0
	// Position of IN_PAGE_BOUND_EN_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_PAGE_BOUND_EN_CH1_Pos = 0xc
	// Bit mask of IN_PAGE_BOUND_EN_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_PAGE_BOUND_EN_CH1_Msk = 0x1000
	// Bit IN_PAGE_BOUND_EN_CH1.
	H264_DMA_IN_CONF0_CH1_IN_PAGE_BOUND_EN_CH1 = 0x1000
	// Position of IN_RST_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_RST_CH1_Pos = 0x18
	// Bit mask of IN_RST_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_RST_CH1_Msk = 0x1000000
	// Bit IN_RST_CH1.
	H264_DMA_IN_CONF0_CH1_IN_RST_CH1 = 0x1000000
	// Position of IN_CMD_DISABLE_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_CMD_DISABLE_CH1_Pos = 0x19
	// Bit mask of IN_CMD_DISABLE_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_CMD_DISABLE_CH1_Msk = 0x2000000
	// Bit IN_CMD_DISABLE_CH1.
	H264_DMA_IN_CONF0_CH1_IN_CMD_DISABLE_CH1 = 0x2000000
	// Position of IN_ARB_WEIGHT_OPT_DIS_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_ARB_WEIGHT_OPT_DIS_CH1_Pos = 0x1a
	// Bit mask of IN_ARB_WEIGHT_OPT_DIS_CH1 field.
	H264_DMA_IN_CONF0_CH1_IN_ARB_WEIGHT_OPT_DIS_CH1_Msk = 0x4000000
	// Bit IN_ARB_WEIGHT_OPT_DIS_CH1.
	H264_DMA_IN_CONF0_CH1_IN_ARB_WEIGHT_OPT_DIS_CH1 = 0x4000000

	// IN_INT_RAW_CH1: RX CH1 interrupt raw register
	// Position of IN_DONE_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DONE_CH1_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DONE_CH1_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_IN_DONE_CH1_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_SUC_EOF_CH1_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_SUC_EOF_CH1_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_IN_SUC_EOF_CH1_INT_RAW = 0x2
	// Position of IN_ERR_EOF_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_ERR_EOF_CH1_INT_RAW_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_ERR_EOF_CH1_INT_RAW_Msk = 0x4
	// Bit IN_ERR_EOF_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_IN_ERR_EOF_CH1_INT_RAW = 0x4
	// Position of IN_DSCR_ERR_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_ERR_CH1_INT_RAW_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_ERR_CH1_INT_RAW_Msk = 0x8
	// Bit IN_DSCR_ERR_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_ERR_CH1_INT_RAW = 0x8
	// Position of INFIFO_OVF_L1_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_OVF_L1_CH1_INT_RAW_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_OVF_L1_CH1_INT_RAW_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_OVF_L1_CH1_INT_RAW = 0x10
	// Position of INFIFO_UDF_L1_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_UDF_L1_CH1_INT_RAW_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_UDF_L1_CH1_INT_RAW_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_UDF_L1_CH1_INT_RAW = 0x20
	// Position of INFIFO_OVF_L2_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_OVF_L2_CH1_INT_RAW_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_OVF_L2_CH1_INT_RAW_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_OVF_L2_CH1_INT_RAW = 0x40
	// Position of INFIFO_UDF_L2_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_UDF_L2_CH1_INT_RAW_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_UDF_L2_CH1_INT_RAW_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_INFIFO_UDF_L2_CH1_INT_RAW = 0x80
	// Position of IN_DSCR_EMPTY_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_EMPTY_CH1_INT_RAW_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_EMPTY_CH1_INT_RAW_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_EMPTY_CH1_INT_RAW = 0x100
	// Position of IN_DSCR_TASK_OVF_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_TASK_OVF_CH1_INT_RAW_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH1_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_TASK_OVF_CH1_INT_RAW_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH1_INT_RAW.
	H264_DMA_IN_INT_RAW_CH1_IN_DSCR_TASK_OVF_CH1_INT_RAW = 0x200

	// IN_INT_ENA_CH1: RX CH1 interrupt ena register
	// Position of IN_DONE_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DONE_CH1_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DONE_CH1_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_IN_DONE_CH1_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_SUC_EOF_CH1_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_SUC_EOF_CH1_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_IN_SUC_EOF_CH1_INT_ENA = 0x2
	// Position of IN_ERR_EOF_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_ERR_EOF_CH1_INT_ENA_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_ERR_EOF_CH1_INT_ENA_Msk = 0x4
	// Bit IN_ERR_EOF_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_IN_ERR_EOF_CH1_INT_ENA = 0x4
	// Position of IN_DSCR_ERR_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_ERR_CH1_INT_ENA_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_ERR_CH1_INT_ENA_Msk = 0x8
	// Bit IN_DSCR_ERR_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_ERR_CH1_INT_ENA = 0x8
	// Position of INFIFO_OVF_L1_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_OVF_L1_CH1_INT_ENA_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_OVF_L1_CH1_INT_ENA_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_OVF_L1_CH1_INT_ENA = 0x10
	// Position of INFIFO_UDF_L1_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_UDF_L1_CH1_INT_ENA_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_UDF_L1_CH1_INT_ENA_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_UDF_L1_CH1_INT_ENA = 0x20
	// Position of INFIFO_OVF_L2_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_OVF_L2_CH1_INT_ENA_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_OVF_L2_CH1_INT_ENA_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_OVF_L2_CH1_INT_ENA = 0x40
	// Position of INFIFO_UDF_L2_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_UDF_L2_CH1_INT_ENA_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_UDF_L2_CH1_INT_ENA_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_INFIFO_UDF_L2_CH1_INT_ENA = 0x80
	// Position of IN_DSCR_EMPTY_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_EMPTY_CH1_INT_ENA_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_EMPTY_CH1_INT_ENA_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_EMPTY_CH1_INT_ENA = 0x100
	// Position of IN_DSCR_TASK_OVF_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_TASK_OVF_CH1_INT_ENA_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH1_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_TASK_OVF_CH1_INT_ENA_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH1_INT_ENA.
	H264_DMA_IN_INT_ENA_CH1_IN_DSCR_TASK_OVF_CH1_INT_ENA = 0x200

	// IN_INT_ST_CH1: RX CH1 interrupt st register
	// Position of IN_DONE_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DONE_CH1_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DONE_CH1_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_IN_DONE_CH1_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_SUC_EOF_CH1_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_SUC_EOF_CH1_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_IN_SUC_EOF_CH1_INT_ST = 0x2
	// Position of IN_ERR_EOF_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_ERR_EOF_CH1_INT_ST_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_ERR_EOF_CH1_INT_ST_Msk = 0x4
	// Bit IN_ERR_EOF_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_IN_ERR_EOF_CH1_INT_ST = 0x4
	// Position of IN_DSCR_ERR_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_ERR_CH1_INT_ST_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_ERR_CH1_INT_ST_Msk = 0x8
	// Bit IN_DSCR_ERR_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_ERR_CH1_INT_ST = 0x8
	// Position of INFIFO_OVF_L1_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_OVF_L1_CH1_INT_ST_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_OVF_L1_CH1_INT_ST_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_INFIFO_OVF_L1_CH1_INT_ST = 0x10
	// Position of INFIFO_UDF_L1_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_UDF_L1_CH1_INT_ST_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_UDF_L1_CH1_INT_ST_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_INFIFO_UDF_L1_CH1_INT_ST = 0x20
	// Position of INFIFO_OVF_L2_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_OVF_L2_CH1_INT_ST_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_OVF_L2_CH1_INT_ST_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_INFIFO_OVF_L2_CH1_INT_ST = 0x40
	// Position of INFIFO_UDF_L2_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_UDF_L2_CH1_INT_ST_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_INFIFO_UDF_L2_CH1_INT_ST_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_INFIFO_UDF_L2_CH1_INT_ST = 0x80
	// Position of IN_DSCR_EMPTY_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_EMPTY_CH1_INT_ST_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_EMPTY_CH1_INT_ST_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_EMPTY_CH1_INT_ST = 0x100
	// Position of IN_DSCR_TASK_OVF_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_TASK_OVF_CH1_INT_ST_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH1_INT_ST field.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_TASK_OVF_CH1_INT_ST_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH1_INT_ST.
	H264_DMA_IN_INT_ST_CH1_IN_DSCR_TASK_OVF_CH1_INT_ST = 0x200

	// IN_INT_CLR_CH1: RX CH1 interrupt clr register
	// Position of IN_DONE_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DONE_CH1_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DONE_CH1_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_IN_DONE_CH1_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_SUC_EOF_CH1_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_SUC_EOF_CH1_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_IN_SUC_EOF_CH1_INT_CLR = 0x2
	// Position of IN_ERR_EOF_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_ERR_EOF_CH1_INT_CLR_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_ERR_EOF_CH1_INT_CLR_Msk = 0x4
	// Bit IN_ERR_EOF_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_IN_ERR_EOF_CH1_INT_CLR = 0x4
	// Position of IN_DSCR_ERR_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_ERR_CH1_INT_CLR_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_ERR_CH1_INT_CLR_Msk = 0x8
	// Bit IN_DSCR_ERR_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_ERR_CH1_INT_CLR = 0x8
	// Position of INFIFO_OVF_L1_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_OVF_L1_CH1_INT_CLR_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_OVF_L1_CH1_INT_CLR_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_OVF_L1_CH1_INT_CLR = 0x10
	// Position of INFIFO_UDF_L1_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_UDF_L1_CH1_INT_CLR_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_UDF_L1_CH1_INT_CLR_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_UDF_L1_CH1_INT_CLR = 0x20
	// Position of INFIFO_OVF_L2_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_OVF_L2_CH1_INT_CLR_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_OVF_L2_CH1_INT_CLR_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_OVF_L2_CH1_INT_CLR = 0x40
	// Position of INFIFO_UDF_L2_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_UDF_L2_CH1_INT_CLR_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_UDF_L2_CH1_INT_CLR_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_INFIFO_UDF_L2_CH1_INT_CLR = 0x80
	// Position of IN_DSCR_EMPTY_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_EMPTY_CH1_INT_CLR_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_EMPTY_CH1_INT_CLR_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_EMPTY_CH1_INT_CLR = 0x100
	// Position of IN_DSCR_TASK_OVF_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_TASK_OVF_CH1_INT_CLR_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH1_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_TASK_OVF_CH1_INT_CLR_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH1_INT_CLR.
	H264_DMA_IN_INT_CLR_CH1_IN_DSCR_TASK_OVF_CH1_INT_CLR = 0x200

	// INFIFO_STATUS_CH1: RX CH1 INFIFO status register
	// Position of INFIFO_FULL_L2_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L2_CH1_Pos = 0x0
	// Bit mask of INFIFO_FULL_L2_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L2_CH1_Msk = 0x1
	// Bit INFIFO_FULL_L2_CH1.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L2_CH1 = 0x1
	// Position of INFIFO_EMPTY_L2_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L2_CH1_Pos = 0x1
	// Bit mask of INFIFO_EMPTY_L2_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L2_CH1_Msk = 0x2
	// Bit INFIFO_EMPTY_L2_CH1.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L2_CH1 = 0x2
	// Position of INFIFO_CNT_L2_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_CNT_L2_CH1_Pos = 0x2
	// Bit mask of INFIFO_CNT_L2_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_CNT_L2_CH1_Msk = 0x3c
	// Position of INFIFO_FULL_L1_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L1_CH1_Pos = 0x6
	// Bit mask of INFIFO_FULL_L1_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L1_CH1_Msk = 0x40
	// Bit INFIFO_FULL_L1_CH1.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L1_CH1 = 0x40
	// Position of INFIFO_EMPTY_L1_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L1_CH1_Pos = 0x7
	// Bit mask of INFIFO_EMPTY_L1_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L1_CH1_Msk = 0x80
	// Bit INFIFO_EMPTY_L1_CH1.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L1_CH1 = 0x80
	// Position of INFIFO_CNT_L1_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_CNT_L1_CH1_Pos = 0x8
	// Bit mask of INFIFO_CNT_L1_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_CNT_L1_CH1_Msk = 0x1f00
	// Position of INFIFO_FULL_L3_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L3_CH1_Pos = 0x10
	// Bit mask of INFIFO_FULL_L3_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L3_CH1_Msk = 0x10000
	// Bit INFIFO_FULL_L3_CH1.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_FULL_L3_CH1 = 0x10000
	// Position of INFIFO_EMPTY_L3_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L3_CH1_Pos = 0x11
	// Bit mask of INFIFO_EMPTY_L3_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L3_CH1_Msk = 0x20000
	// Bit INFIFO_EMPTY_L3_CH1.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_EMPTY_L3_CH1 = 0x20000
	// Position of INFIFO_CNT_L3_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_CNT_L3_CH1_Pos = 0x12
	// Bit mask of INFIFO_CNT_L3_CH1 field.
	H264_DMA_INFIFO_STATUS_CH1_INFIFO_CNT_L3_CH1_Msk = 0xc0000

	// IN_POP_CH1: RX CH1 INFIFO pop register
	// Position of INFIFO_RDATA_CH1 field.
	H264_DMA_IN_POP_CH1_INFIFO_RDATA_CH1_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH1 field.
	H264_DMA_IN_POP_CH1_INFIFO_RDATA_CH1_Msk = 0x7ff
	// Position of INFIFO_POP_CH1 field.
	H264_DMA_IN_POP_CH1_INFIFO_POP_CH1_Pos = 0xb
	// Bit mask of INFIFO_POP_CH1 field.
	H264_DMA_IN_POP_CH1_INFIFO_POP_CH1_Msk = 0x800
	// Bit INFIFO_POP_CH1.
	H264_DMA_IN_POP_CH1_INFIFO_POP_CH1 = 0x800

	// IN_LINK_CONF_CH1: RX CH1 in_link dscr ctrl register
	// Position of INLINK_AUTO_RET_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_AUTO_RET_CH1_Pos = 0x14
	// Bit mask of INLINK_AUTO_RET_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_AUTO_RET_CH1_Msk = 0x100000
	// Bit INLINK_AUTO_RET_CH1.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_AUTO_RET_CH1 = 0x100000
	// Position of INLINK_STOP_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_STOP_CH1_Pos = 0x15
	// Bit mask of INLINK_STOP_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_STOP_CH1_Msk = 0x200000
	// Bit INLINK_STOP_CH1.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_STOP_CH1 = 0x200000
	// Position of INLINK_START_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_START_CH1_Pos = 0x16
	// Bit mask of INLINK_START_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_START_CH1_Msk = 0x400000
	// Bit INLINK_START_CH1.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_START_CH1 = 0x400000
	// Position of INLINK_RESTART_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_RESTART_CH1_Pos = 0x17
	// Bit mask of INLINK_RESTART_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_RESTART_CH1_Msk = 0x800000
	// Bit INLINK_RESTART_CH1.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_RESTART_CH1 = 0x800000
	// Position of INLINK_PARK_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_PARK_CH1_Pos = 0x18
	// Bit mask of INLINK_PARK_CH1 field.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_PARK_CH1_Msk = 0x1000000
	// Bit INLINK_PARK_CH1.
	H264_DMA_IN_LINK_CONF_CH1_INLINK_PARK_CH1 = 0x1000000

	// IN_LINK_ADDR_CH1: RX CH1 in_link dscr addr register
	// Position of INLINK_ADDR_CH1 field.
	H264_DMA_IN_LINK_ADDR_CH1_INLINK_ADDR_CH1_Pos = 0x0
	// Bit mask of INLINK_ADDR_CH1 field.
	H264_DMA_IN_LINK_ADDR_CH1_INLINK_ADDR_CH1_Msk = 0xffffffff

	// IN_STATE_CH1: RX CH1 state register
	// Position of INLINK_DSCR_ADDR_CH1 field.
	H264_DMA_IN_STATE_CH1_INLINK_DSCR_ADDR_CH1_Pos = 0x0
	// Bit mask of INLINK_DSCR_ADDR_CH1 field.
	H264_DMA_IN_STATE_CH1_INLINK_DSCR_ADDR_CH1_Msk = 0x3ffff
	// Position of IN_DSCR_STATE_CH1 field.
	H264_DMA_IN_STATE_CH1_IN_DSCR_STATE_CH1_Pos = 0x12
	// Bit mask of IN_DSCR_STATE_CH1 field.
	H264_DMA_IN_STATE_CH1_IN_DSCR_STATE_CH1_Msk = 0xc0000
	// Position of IN_STATE_CH1 field.
	H264_DMA_IN_STATE_CH1_IN_STATE_CH1_Pos = 0x14
	// Bit mask of IN_STATE_CH1 field.
	H264_DMA_IN_STATE_CH1_IN_STATE_CH1_Msk = 0x700000
	// Position of IN_RESET_AVAIL_CH1 field.
	H264_DMA_IN_STATE_CH1_IN_RESET_AVAIL_CH1_Pos = 0x17
	// Bit mask of IN_RESET_AVAIL_CH1 field.
	H264_DMA_IN_STATE_CH1_IN_RESET_AVAIL_CH1_Msk = 0x800000
	// Bit IN_RESET_AVAIL_CH1.
	H264_DMA_IN_STATE_CH1_IN_RESET_AVAIL_CH1 = 0x800000

	// IN_SUC_EOF_DES_ADDR_CH1: RX CH1 eof des addr register
	// Position of IN_SUC_EOF_DES_ADDR_CH1 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_IN_SUC_EOF_DES_ADDR_CH1_Pos = 0x0
	// Bit mask of IN_SUC_EOF_DES_ADDR_CH1 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_IN_SUC_EOF_DES_ADDR_CH1_Msk = 0xffffffff

	// IN_ERR_EOF_DES_ADDR_CH1: RX CH1 err eof des addr register
	// Position of IN_ERR_EOF_DES_ADDR_CH1 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_IN_ERR_EOF_DES_ADDR_CH1_Pos = 0x0
	// Bit mask of IN_ERR_EOF_DES_ADDR_CH1 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_IN_ERR_EOF_DES_ADDR_CH1_Msk = 0xffffffff

	// IN_DSCR_CH1: RX CH1 next dscr addr register
	// Position of INLINK_DSCR_CH1 field.
	H264_DMA_IN_DSCR_CH1_INLINK_DSCR_CH1_Pos = 0x0
	// Bit mask of INLINK_DSCR_CH1 field.
	H264_DMA_IN_DSCR_CH1_INLINK_DSCR_CH1_Msk = 0xffffffff

	// IN_DSCR_BF0_CH1: RX CH1 last dscr addr register
	// Position of INLINK_DSCR_BF0_CH1 field.
	H264_DMA_IN_DSCR_BF0_CH1_INLINK_DSCR_BF0_CH1_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF0_CH1 field.
	H264_DMA_IN_DSCR_BF0_CH1_INLINK_DSCR_BF0_CH1_Msk = 0xffffffff

	// IN_DSCR_BF1_CH1: RX CH1 second-to-last dscr addr register
	// Position of INLINK_DSCR_BF1_CH1 field.
	H264_DMA_IN_DSCR_BF1_CH1_INLINK_DSCR_BF1_CH1_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF1_CH1 field.
	H264_DMA_IN_DSCR_BF1_CH1_INLINK_DSCR_BF1_CH1_Msk = 0xffffffff

	// IN_ARB_CH1: RX CH1 arb register
	// Position of IN_ARB_TOKEN_NUM_CH1 field.
	H264_DMA_IN_ARB_CH1_IN_ARB_TOKEN_NUM_CH1_Pos = 0x0
	// Bit mask of IN_ARB_TOKEN_NUM_CH1 field.
	H264_DMA_IN_ARB_CH1_IN_ARB_TOKEN_NUM_CH1_Msk = 0xf
	// Position of EXTER_IN_ARB_PRIORITY_CH1 field.
	H264_DMA_IN_ARB_CH1_EXTER_IN_ARB_PRIORITY_CH1_Pos = 0x4
	// Bit mask of EXTER_IN_ARB_PRIORITY_CH1 field.
	H264_DMA_IN_ARB_CH1_EXTER_IN_ARB_PRIORITY_CH1_Msk = 0x30
	// Position of INTER_IN_ARB_PRIORITY_CH1 field.
	H264_DMA_IN_ARB_CH1_INTER_IN_ARB_PRIORITY_CH1_Pos = 0x6
	// Bit mask of INTER_IN_ARB_PRIORITY_CH1 field.
	H264_DMA_IN_ARB_CH1_INTER_IN_ARB_PRIORITY_CH1_Msk = 0x1c0

	// IN_ETM_CONF_CH1: RX CH1 ETM config register
	// Position of IN_ETM_EN_CH1 field.
	H264_DMA_IN_ETM_CONF_CH1_IN_ETM_EN_CH1_Pos = 0x0
	// Bit mask of IN_ETM_EN_CH1 field.
	H264_DMA_IN_ETM_CONF_CH1_IN_ETM_EN_CH1_Msk = 0x1
	// Bit IN_ETM_EN_CH1.
	H264_DMA_IN_ETM_CONF_CH1_IN_ETM_EN_CH1 = 0x1
	// Position of IN_ETM_LOOP_EN_CH1 field.
	H264_DMA_IN_ETM_CONF_CH1_IN_ETM_LOOP_EN_CH1_Pos = 0x1
	// Bit mask of IN_ETM_LOOP_EN_CH1 field.
	H264_DMA_IN_ETM_CONF_CH1_IN_ETM_LOOP_EN_CH1_Msk = 0x2
	// Bit IN_ETM_LOOP_EN_CH1.
	H264_DMA_IN_ETM_CONF_CH1_IN_ETM_LOOP_EN_CH1 = 0x2
	// Position of IN_DSCR_TASK_MAK_CH1 field.
	H264_DMA_IN_ETM_CONF_CH1_IN_DSCR_TASK_MAK_CH1_Pos = 0x2
	// Bit mask of IN_DSCR_TASK_MAK_CH1 field.
	H264_DMA_IN_ETM_CONF_CH1_IN_DSCR_TASK_MAK_CH1_Msk = 0xc

	// IN_FIFO_CNT_CH1: rx CH1 fifo cnt register
	// Position of IN_CMDFIFO_INFIFO_CNT_CH1 field.
	H264_DMA_IN_FIFO_CNT_CH1_IN_CMDFIFO_INFIFO_CNT_CH1_Pos = 0x0
	// Bit mask of IN_CMDFIFO_INFIFO_CNT_CH1 field.
	H264_DMA_IN_FIFO_CNT_CH1_IN_CMDFIFO_INFIFO_CNT_CH1_Msk = 0x3ff

	// IN_POP_DATA_CNT_CH1: rx CH1 pop data cnt register
	// Position of IN_CMDFIFO_POP_DATA_CNT_CH1 field.
	H264_DMA_IN_POP_DATA_CNT_CH1_IN_CMDFIFO_POP_DATA_CNT_CH1_Pos = 0x0
	// Bit mask of IN_CMDFIFO_POP_DATA_CNT_CH1 field.
	H264_DMA_IN_POP_DATA_CNT_CH1_IN_CMDFIFO_POP_DATA_CNT_CH1_Msk = 0xff

	// IN_XADDR_CH1: rx CH1 xaddr register
	// Position of IN_CMDFIFO_XADDR_CH1 field.
	H264_DMA_IN_XADDR_CH1_IN_CMDFIFO_XADDR_CH1_Pos = 0x0
	// Bit mask of IN_CMDFIFO_XADDR_CH1 field.
	H264_DMA_IN_XADDR_CH1_IN_CMDFIFO_XADDR_CH1_Msk = 0xffffffff

	// IN_BUF_HB_RCV_CH1: rx CH1 buf len hb rcv register
	// Position of IN_CMDFIFO_BUF_HB_RCV_CH1 field.
	H264_DMA_IN_BUF_HB_RCV_CH1_IN_CMDFIFO_BUF_HB_RCV_CH1_Pos = 0x0
	// Bit mask of IN_CMDFIFO_BUF_HB_RCV_CH1 field.
	H264_DMA_IN_BUF_HB_RCV_CH1_IN_CMDFIFO_BUF_HB_RCV_CH1_Msk = 0x1fffffff

	// IN_CONF0_CH2: RX CH2 config0 register
	// Position of INDSCR_BURST_EN_CH2 field.
	H264_DMA_IN_CONF0_CH2_INDSCR_BURST_EN_CH2_Pos = 0x2
	// Bit mask of INDSCR_BURST_EN_CH2 field.
	H264_DMA_IN_CONF0_CH2_INDSCR_BURST_EN_CH2_Msk = 0x4
	// Bit INDSCR_BURST_EN_CH2.
	H264_DMA_IN_CONF0_CH2_INDSCR_BURST_EN_CH2 = 0x4
	// Position of IN_ECC_AES_EN_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_ECC_AES_EN_CH2_Pos = 0x3
	// Bit mask of IN_ECC_AES_EN_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_ECC_AES_EN_CH2_Msk = 0x8
	// Bit IN_ECC_AES_EN_CH2.
	H264_DMA_IN_CONF0_CH2_IN_ECC_AES_EN_CH2 = 0x8
	// Position of IN_CHECK_OWNER_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_CHECK_OWNER_CH2_Pos = 0x4
	// Bit mask of IN_CHECK_OWNER_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_CHECK_OWNER_CH2_Msk = 0x10
	// Bit IN_CHECK_OWNER_CH2.
	H264_DMA_IN_CONF0_CH2_IN_CHECK_OWNER_CH2 = 0x10
	// Position of IN_MEM_BURST_LENGTH_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_MEM_BURST_LENGTH_CH2_Pos = 0x6
	// Bit mask of IN_MEM_BURST_LENGTH_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_MEM_BURST_LENGTH_CH2_Msk = 0x1c0
	// Position of IN_PAGE_BOUND_EN_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_PAGE_BOUND_EN_CH2_Pos = 0xc
	// Bit mask of IN_PAGE_BOUND_EN_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_PAGE_BOUND_EN_CH2_Msk = 0x1000
	// Bit IN_PAGE_BOUND_EN_CH2.
	H264_DMA_IN_CONF0_CH2_IN_PAGE_BOUND_EN_CH2 = 0x1000
	// Position of IN_RST_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_RST_CH2_Pos = 0x18
	// Bit mask of IN_RST_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_RST_CH2_Msk = 0x1000000
	// Bit IN_RST_CH2.
	H264_DMA_IN_CONF0_CH2_IN_RST_CH2 = 0x1000000
	// Position of IN_CMD_DISABLE_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_CMD_DISABLE_CH2_Pos = 0x19
	// Bit mask of IN_CMD_DISABLE_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_CMD_DISABLE_CH2_Msk = 0x2000000
	// Bit IN_CMD_DISABLE_CH2.
	H264_DMA_IN_CONF0_CH2_IN_CMD_DISABLE_CH2 = 0x2000000
	// Position of IN_ARB_WEIGHT_OPT_DIS_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_ARB_WEIGHT_OPT_DIS_CH2_Pos = 0x1a
	// Bit mask of IN_ARB_WEIGHT_OPT_DIS_CH2 field.
	H264_DMA_IN_CONF0_CH2_IN_ARB_WEIGHT_OPT_DIS_CH2_Msk = 0x4000000
	// Bit IN_ARB_WEIGHT_OPT_DIS_CH2.
	H264_DMA_IN_CONF0_CH2_IN_ARB_WEIGHT_OPT_DIS_CH2 = 0x4000000

	// IN_INT_RAW_CH2: RX CH2 interrupt raw register
	// Position of IN_DONE_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DONE_CH2_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DONE_CH2_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_IN_DONE_CH2_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_SUC_EOF_CH2_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_SUC_EOF_CH2_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_IN_SUC_EOF_CH2_INT_RAW = 0x2
	// Position of IN_ERR_EOF_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_ERR_EOF_CH2_INT_RAW_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_ERR_EOF_CH2_INT_RAW_Msk = 0x4
	// Bit IN_ERR_EOF_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_IN_ERR_EOF_CH2_INT_RAW = 0x4
	// Position of IN_DSCR_ERR_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_ERR_CH2_INT_RAW_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_ERR_CH2_INT_RAW_Msk = 0x8
	// Bit IN_DSCR_ERR_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_ERR_CH2_INT_RAW = 0x8
	// Position of INFIFO_OVF_L1_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_OVF_L1_CH2_INT_RAW_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_OVF_L1_CH2_INT_RAW_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_OVF_L1_CH2_INT_RAW = 0x10
	// Position of INFIFO_UDF_L1_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_UDF_L1_CH2_INT_RAW_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_UDF_L1_CH2_INT_RAW_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_UDF_L1_CH2_INT_RAW = 0x20
	// Position of INFIFO_OVF_L2_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_OVF_L2_CH2_INT_RAW_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_OVF_L2_CH2_INT_RAW_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_OVF_L2_CH2_INT_RAW = 0x40
	// Position of INFIFO_UDF_L2_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_UDF_L2_CH2_INT_RAW_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_UDF_L2_CH2_INT_RAW_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_INFIFO_UDF_L2_CH2_INT_RAW = 0x80
	// Position of IN_DSCR_EMPTY_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_EMPTY_CH2_INT_RAW_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_EMPTY_CH2_INT_RAW_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_EMPTY_CH2_INT_RAW = 0x100
	// Position of IN_DSCR_TASK_OVF_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_TASK_OVF_CH2_INT_RAW_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH2_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_TASK_OVF_CH2_INT_RAW_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH2_INT_RAW.
	H264_DMA_IN_INT_RAW_CH2_IN_DSCR_TASK_OVF_CH2_INT_RAW = 0x200

	// IN_INT_ENA_CH2: RX CH2 interrupt ena register
	// Position of IN_DONE_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DONE_CH2_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DONE_CH2_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_IN_DONE_CH2_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_SUC_EOF_CH2_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_SUC_EOF_CH2_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_IN_SUC_EOF_CH2_INT_ENA = 0x2
	// Position of IN_ERR_EOF_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_ERR_EOF_CH2_INT_ENA_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_ERR_EOF_CH2_INT_ENA_Msk = 0x4
	// Bit IN_ERR_EOF_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_IN_ERR_EOF_CH2_INT_ENA = 0x4
	// Position of IN_DSCR_ERR_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_ERR_CH2_INT_ENA_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_ERR_CH2_INT_ENA_Msk = 0x8
	// Bit IN_DSCR_ERR_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_ERR_CH2_INT_ENA = 0x8
	// Position of INFIFO_OVF_L1_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_OVF_L1_CH2_INT_ENA_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_OVF_L1_CH2_INT_ENA_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_OVF_L1_CH2_INT_ENA = 0x10
	// Position of INFIFO_UDF_L1_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_UDF_L1_CH2_INT_ENA_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_UDF_L1_CH2_INT_ENA_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_UDF_L1_CH2_INT_ENA = 0x20
	// Position of INFIFO_OVF_L2_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_OVF_L2_CH2_INT_ENA_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_OVF_L2_CH2_INT_ENA_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_OVF_L2_CH2_INT_ENA = 0x40
	// Position of INFIFO_UDF_L2_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_UDF_L2_CH2_INT_ENA_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_UDF_L2_CH2_INT_ENA_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_INFIFO_UDF_L2_CH2_INT_ENA = 0x80
	// Position of IN_DSCR_EMPTY_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_EMPTY_CH2_INT_ENA_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_EMPTY_CH2_INT_ENA_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_EMPTY_CH2_INT_ENA = 0x100
	// Position of IN_DSCR_TASK_OVF_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_TASK_OVF_CH2_INT_ENA_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH2_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_TASK_OVF_CH2_INT_ENA_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH2_INT_ENA.
	H264_DMA_IN_INT_ENA_CH2_IN_DSCR_TASK_OVF_CH2_INT_ENA = 0x200

	// IN_INT_ST_CH2: RX CH2 interrupt st register
	// Position of IN_DONE_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DONE_CH2_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DONE_CH2_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_IN_DONE_CH2_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_SUC_EOF_CH2_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_SUC_EOF_CH2_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_IN_SUC_EOF_CH2_INT_ST = 0x2
	// Position of IN_ERR_EOF_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_ERR_EOF_CH2_INT_ST_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_ERR_EOF_CH2_INT_ST_Msk = 0x4
	// Bit IN_ERR_EOF_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_IN_ERR_EOF_CH2_INT_ST = 0x4
	// Position of IN_DSCR_ERR_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_ERR_CH2_INT_ST_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_ERR_CH2_INT_ST_Msk = 0x8
	// Bit IN_DSCR_ERR_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_ERR_CH2_INT_ST = 0x8
	// Position of INFIFO_OVF_L1_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_OVF_L1_CH2_INT_ST_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_OVF_L1_CH2_INT_ST_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_INFIFO_OVF_L1_CH2_INT_ST = 0x10
	// Position of INFIFO_UDF_L1_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_UDF_L1_CH2_INT_ST_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_UDF_L1_CH2_INT_ST_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_INFIFO_UDF_L1_CH2_INT_ST = 0x20
	// Position of INFIFO_OVF_L2_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_OVF_L2_CH2_INT_ST_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_OVF_L2_CH2_INT_ST_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_INFIFO_OVF_L2_CH2_INT_ST = 0x40
	// Position of INFIFO_UDF_L2_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_UDF_L2_CH2_INT_ST_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_INFIFO_UDF_L2_CH2_INT_ST_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_INFIFO_UDF_L2_CH2_INT_ST = 0x80
	// Position of IN_DSCR_EMPTY_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_EMPTY_CH2_INT_ST_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_EMPTY_CH2_INT_ST_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_EMPTY_CH2_INT_ST = 0x100
	// Position of IN_DSCR_TASK_OVF_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_TASK_OVF_CH2_INT_ST_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH2_INT_ST field.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_TASK_OVF_CH2_INT_ST_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH2_INT_ST.
	H264_DMA_IN_INT_ST_CH2_IN_DSCR_TASK_OVF_CH2_INT_ST = 0x200

	// IN_INT_CLR_CH2: RX CH2 interrupt clr register
	// Position of IN_DONE_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DONE_CH2_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DONE_CH2_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_IN_DONE_CH2_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_SUC_EOF_CH2_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_SUC_EOF_CH2_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_IN_SUC_EOF_CH2_INT_CLR = 0x2
	// Position of IN_ERR_EOF_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_ERR_EOF_CH2_INT_CLR_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_ERR_EOF_CH2_INT_CLR_Msk = 0x4
	// Bit IN_ERR_EOF_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_IN_ERR_EOF_CH2_INT_CLR = 0x4
	// Position of IN_DSCR_ERR_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_ERR_CH2_INT_CLR_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_ERR_CH2_INT_CLR_Msk = 0x8
	// Bit IN_DSCR_ERR_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_ERR_CH2_INT_CLR = 0x8
	// Position of INFIFO_OVF_L1_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_OVF_L1_CH2_INT_CLR_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_OVF_L1_CH2_INT_CLR_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_OVF_L1_CH2_INT_CLR = 0x10
	// Position of INFIFO_UDF_L1_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_UDF_L1_CH2_INT_CLR_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_UDF_L1_CH2_INT_CLR_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_UDF_L1_CH2_INT_CLR = 0x20
	// Position of INFIFO_OVF_L2_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_OVF_L2_CH2_INT_CLR_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_OVF_L2_CH2_INT_CLR_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_OVF_L2_CH2_INT_CLR = 0x40
	// Position of INFIFO_UDF_L2_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_UDF_L2_CH2_INT_CLR_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_UDF_L2_CH2_INT_CLR_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_INFIFO_UDF_L2_CH2_INT_CLR = 0x80
	// Position of IN_DSCR_EMPTY_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_EMPTY_CH2_INT_CLR_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_EMPTY_CH2_INT_CLR_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_EMPTY_CH2_INT_CLR = 0x100
	// Position of IN_DSCR_TASK_OVF_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_TASK_OVF_CH2_INT_CLR_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH2_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_TASK_OVF_CH2_INT_CLR_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH2_INT_CLR.
	H264_DMA_IN_INT_CLR_CH2_IN_DSCR_TASK_OVF_CH2_INT_CLR = 0x200

	// INFIFO_STATUS_CH2: RX CH2 INFIFO status register
	// Position of INFIFO_FULL_L2_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L2_CH2_Pos = 0x0
	// Bit mask of INFIFO_FULL_L2_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L2_CH2_Msk = 0x1
	// Bit INFIFO_FULL_L2_CH2.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L2_CH2 = 0x1
	// Position of INFIFO_EMPTY_L2_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L2_CH2_Pos = 0x1
	// Bit mask of INFIFO_EMPTY_L2_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L2_CH2_Msk = 0x2
	// Bit INFIFO_EMPTY_L2_CH2.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L2_CH2 = 0x2
	// Position of INFIFO_CNT_L2_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_CNT_L2_CH2_Pos = 0x2
	// Bit mask of INFIFO_CNT_L2_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_CNT_L2_CH2_Msk = 0x3c
	// Position of INFIFO_FULL_L1_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L1_CH2_Pos = 0x6
	// Bit mask of INFIFO_FULL_L1_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L1_CH2_Msk = 0x40
	// Bit INFIFO_FULL_L1_CH2.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L1_CH2 = 0x40
	// Position of INFIFO_EMPTY_L1_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L1_CH2_Pos = 0x7
	// Bit mask of INFIFO_EMPTY_L1_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L1_CH2_Msk = 0x80
	// Bit INFIFO_EMPTY_L1_CH2.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L1_CH2 = 0x80
	// Position of INFIFO_CNT_L1_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_CNT_L1_CH2_Pos = 0x8
	// Bit mask of INFIFO_CNT_L1_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_CNT_L1_CH2_Msk = 0x1f00
	// Position of INFIFO_FULL_L3_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L3_CH2_Pos = 0x10
	// Bit mask of INFIFO_FULL_L3_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L3_CH2_Msk = 0x10000
	// Bit INFIFO_FULL_L3_CH2.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_FULL_L3_CH2 = 0x10000
	// Position of INFIFO_EMPTY_L3_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L3_CH2_Pos = 0x11
	// Bit mask of INFIFO_EMPTY_L3_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L3_CH2_Msk = 0x20000
	// Bit INFIFO_EMPTY_L3_CH2.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_EMPTY_L3_CH2 = 0x20000
	// Position of INFIFO_CNT_L3_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_CNT_L3_CH2_Pos = 0x12
	// Bit mask of INFIFO_CNT_L3_CH2 field.
	H264_DMA_INFIFO_STATUS_CH2_INFIFO_CNT_L3_CH2_Msk = 0xc0000

	// IN_POP_CH2: RX CH2 INFIFO pop register
	// Position of INFIFO_RDATA_CH2 field.
	H264_DMA_IN_POP_CH2_INFIFO_RDATA_CH2_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH2 field.
	H264_DMA_IN_POP_CH2_INFIFO_RDATA_CH2_Msk = 0x7ff
	// Position of INFIFO_POP_CH2 field.
	H264_DMA_IN_POP_CH2_INFIFO_POP_CH2_Pos = 0xb
	// Bit mask of INFIFO_POP_CH2 field.
	H264_DMA_IN_POP_CH2_INFIFO_POP_CH2_Msk = 0x800
	// Bit INFIFO_POP_CH2.
	H264_DMA_IN_POP_CH2_INFIFO_POP_CH2 = 0x800

	// IN_LINK_CONF_CH2: RX CH2 in_link dscr ctrl register
	// Position of INLINK_AUTO_RET_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_AUTO_RET_CH2_Pos = 0x14
	// Bit mask of INLINK_AUTO_RET_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_AUTO_RET_CH2_Msk = 0x100000
	// Bit INLINK_AUTO_RET_CH2.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_AUTO_RET_CH2 = 0x100000
	// Position of INLINK_STOP_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_STOP_CH2_Pos = 0x15
	// Bit mask of INLINK_STOP_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_STOP_CH2_Msk = 0x200000
	// Bit INLINK_STOP_CH2.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_STOP_CH2 = 0x200000
	// Position of INLINK_START_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_START_CH2_Pos = 0x16
	// Bit mask of INLINK_START_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_START_CH2_Msk = 0x400000
	// Bit INLINK_START_CH2.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_START_CH2 = 0x400000
	// Position of INLINK_RESTART_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_RESTART_CH2_Pos = 0x17
	// Bit mask of INLINK_RESTART_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_RESTART_CH2_Msk = 0x800000
	// Bit INLINK_RESTART_CH2.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_RESTART_CH2 = 0x800000
	// Position of INLINK_PARK_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_PARK_CH2_Pos = 0x18
	// Bit mask of INLINK_PARK_CH2 field.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_PARK_CH2_Msk = 0x1000000
	// Bit INLINK_PARK_CH2.
	H264_DMA_IN_LINK_CONF_CH2_INLINK_PARK_CH2 = 0x1000000

	// IN_LINK_ADDR_CH2: RX CH2 in_link dscr addr register
	// Position of INLINK_ADDR_CH2 field.
	H264_DMA_IN_LINK_ADDR_CH2_INLINK_ADDR_CH2_Pos = 0x0
	// Bit mask of INLINK_ADDR_CH2 field.
	H264_DMA_IN_LINK_ADDR_CH2_INLINK_ADDR_CH2_Msk = 0xffffffff

	// IN_STATE_CH2: RX CH2 state register
	// Position of INLINK_DSCR_ADDR_CH2 field.
	H264_DMA_IN_STATE_CH2_INLINK_DSCR_ADDR_CH2_Pos = 0x0
	// Bit mask of INLINK_DSCR_ADDR_CH2 field.
	H264_DMA_IN_STATE_CH2_INLINK_DSCR_ADDR_CH2_Msk = 0x3ffff
	// Position of IN_DSCR_STATE_CH2 field.
	H264_DMA_IN_STATE_CH2_IN_DSCR_STATE_CH2_Pos = 0x12
	// Bit mask of IN_DSCR_STATE_CH2 field.
	H264_DMA_IN_STATE_CH2_IN_DSCR_STATE_CH2_Msk = 0xc0000
	// Position of IN_STATE_CH2 field.
	H264_DMA_IN_STATE_CH2_IN_STATE_CH2_Pos = 0x14
	// Bit mask of IN_STATE_CH2 field.
	H264_DMA_IN_STATE_CH2_IN_STATE_CH2_Msk = 0x700000
	// Position of IN_RESET_AVAIL_CH2 field.
	H264_DMA_IN_STATE_CH2_IN_RESET_AVAIL_CH2_Pos = 0x17
	// Bit mask of IN_RESET_AVAIL_CH2 field.
	H264_DMA_IN_STATE_CH2_IN_RESET_AVAIL_CH2_Msk = 0x800000
	// Bit IN_RESET_AVAIL_CH2.
	H264_DMA_IN_STATE_CH2_IN_RESET_AVAIL_CH2 = 0x800000

	// IN_SUC_EOF_DES_ADDR_CH2: RX CH2 eof des addr register
	// Position of IN_SUC_EOF_DES_ADDR_CH2 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_IN_SUC_EOF_DES_ADDR_CH2_Pos = 0x0
	// Bit mask of IN_SUC_EOF_DES_ADDR_CH2 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_IN_SUC_EOF_DES_ADDR_CH2_Msk = 0xffffffff

	// IN_ERR_EOF_DES_ADDR_CH2: RX CH2 err eof des addr register
	// Position of IN_ERR_EOF_DES_ADDR_CH2 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_IN_ERR_EOF_DES_ADDR_CH2_Pos = 0x0
	// Bit mask of IN_ERR_EOF_DES_ADDR_CH2 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_IN_ERR_EOF_DES_ADDR_CH2_Msk = 0xffffffff

	// IN_DSCR_CH2: RX CH2 next dscr addr register
	// Position of INLINK_DSCR_CH2 field.
	H264_DMA_IN_DSCR_CH2_INLINK_DSCR_CH2_Pos = 0x0
	// Bit mask of INLINK_DSCR_CH2 field.
	H264_DMA_IN_DSCR_CH2_INLINK_DSCR_CH2_Msk = 0xffffffff

	// IN_DSCR_BF0_CH2: RX CH2 last dscr addr register
	// Position of INLINK_DSCR_BF0_CH2 field.
	H264_DMA_IN_DSCR_BF0_CH2_INLINK_DSCR_BF0_CH2_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF0_CH2 field.
	H264_DMA_IN_DSCR_BF0_CH2_INLINK_DSCR_BF0_CH2_Msk = 0xffffffff

	// IN_DSCR_BF1_CH2: RX CH2 second-to-last dscr addr register
	// Position of INLINK_DSCR_BF1_CH2 field.
	H264_DMA_IN_DSCR_BF1_CH2_INLINK_DSCR_BF1_CH2_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF1_CH2 field.
	H264_DMA_IN_DSCR_BF1_CH2_INLINK_DSCR_BF1_CH2_Msk = 0xffffffff

	// IN_ARB_CH2: RX CH2 arb register
	// Position of IN_ARB_TOKEN_NUM_CH2 field.
	H264_DMA_IN_ARB_CH2_IN_ARB_TOKEN_NUM_CH2_Pos = 0x0
	// Bit mask of IN_ARB_TOKEN_NUM_CH2 field.
	H264_DMA_IN_ARB_CH2_IN_ARB_TOKEN_NUM_CH2_Msk = 0xf
	// Position of INTER_IN_ARB_PRIORITY_CH2 field.
	H264_DMA_IN_ARB_CH2_INTER_IN_ARB_PRIORITY_CH2_Pos = 0x6
	// Bit mask of INTER_IN_ARB_PRIORITY_CH2 field.
	H264_DMA_IN_ARB_CH2_INTER_IN_ARB_PRIORITY_CH2_Msk = 0x1c0

	// IN_ETM_CONF_CH2: RX CH2 ETM config register
	// Position of IN_ETM_EN_CH2 field.
	H264_DMA_IN_ETM_CONF_CH2_IN_ETM_EN_CH2_Pos = 0x0
	// Bit mask of IN_ETM_EN_CH2 field.
	H264_DMA_IN_ETM_CONF_CH2_IN_ETM_EN_CH2_Msk = 0x1
	// Bit IN_ETM_EN_CH2.
	H264_DMA_IN_ETM_CONF_CH2_IN_ETM_EN_CH2 = 0x1
	// Position of IN_ETM_LOOP_EN_CH2 field.
	H264_DMA_IN_ETM_CONF_CH2_IN_ETM_LOOP_EN_CH2_Pos = 0x1
	// Bit mask of IN_ETM_LOOP_EN_CH2 field.
	H264_DMA_IN_ETM_CONF_CH2_IN_ETM_LOOP_EN_CH2_Msk = 0x2
	// Bit IN_ETM_LOOP_EN_CH2.
	H264_DMA_IN_ETM_CONF_CH2_IN_ETM_LOOP_EN_CH2 = 0x2
	// Position of IN_DSCR_TASK_MAK_CH2 field.
	H264_DMA_IN_ETM_CONF_CH2_IN_DSCR_TASK_MAK_CH2_Pos = 0x2
	// Bit mask of IN_DSCR_TASK_MAK_CH2 field.
	H264_DMA_IN_ETM_CONF_CH2_IN_DSCR_TASK_MAK_CH2_Msk = 0xc

	// IN_FIFO_CNT_CH2: rx CH2 fifo cnt register
	// Position of IN_CMDFIFO_INFIFO_CNT_CH2 field.
	H264_DMA_IN_FIFO_CNT_CH2_IN_CMDFIFO_INFIFO_CNT_CH2_Pos = 0x0
	// Bit mask of IN_CMDFIFO_INFIFO_CNT_CH2 field.
	H264_DMA_IN_FIFO_CNT_CH2_IN_CMDFIFO_INFIFO_CNT_CH2_Msk = 0x3ff

	// IN_POP_DATA_CNT_CH2: rx CH2 pop data cnt register
	// Position of IN_CMDFIFO_POP_DATA_CNT_CH2 field.
	H264_DMA_IN_POP_DATA_CNT_CH2_IN_CMDFIFO_POP_DATA_CNT_CH2_Pos = 0x0
	// Bit mask of IN_CMDFIFO_POP_DATA_CNT_CH2 field.
	H264_DMA_IN_POP_DATA_CNT_CH2_IN_CMDFIFO_POP_DATA_CNT_CH2_Msk = 0xff

	// IN_XADDR_CH2: rx CH2 xaddr register
	// Position of IN_CMDFIFO_XADDR_CH2 field.
	H264_DMA_IN_XADDR_CH2_IN_CMDFIFO_XADDR_CH2_Pos = 0x0
	// Bit mask of IN_CMDFIFO_XADDR_CH2 field.
	H264_DMA_IN_XADDR_CH2_IN_CMDFIFO_XADDR_CH2_Msk = 0xffffffff

	// IN_BUF_HB_RCV_CH2: rx CH2 buf len hb rcv register
	// Position of IN_CMDFIFO_BUF_HB_RCV_CH2 field.
	H264_DMA_IN_BUF_HB_RCV_CH2_IN_CMDFIFO_BUF_HB_RCV_CH2_Pos = 0x0
	// Bit mask of IN_CMDFIFO_BUF_HB_RCV_CH2 field.
	H264_DMA_IN_BUF_HB_RCV_CH2_IN_CMDFIFO_BUF_HB_RCV_CH2_Msk = 0x1fffffff

	// IN_CONF0_CH3: RX CH3 config0 register
	// Position of INDSCR_BURST_EN_CH3 field.
	H264_DMA_IN_CONF0_CH3_INDSCR_BURST_EN_CH3_Pos = 0x2
	// Bit mask of INDSCR_BURST_EN_CH3 field.
	H264_DMA_IN_CONF0_CH3_INDSCR_BURST_EN_CH3_Msk = 0x4
	// Bit INDSCR_BURST_EN_CH3.
	H264_DMA_IN_CONF0_CH3_INDSCR_BURST_EN_CH3 = 0x4
	// Position of IN_ECC_AES_EN_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_ECC_AES_EN_CH3_Pos = 0x3
	// Bit mask of IN_ECC_AES_EN_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_ECC_AES_EN_CH3_Msk = 0x8
	// Bit IN_ECC_AES_EN_CH3.
	H264_DMA_IN_CONF0_CH3_IN_ECC_AES_EN_CH3 = 0x8
	// Position of IN_CHECK_OWNER_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_CHECK_OWNER_CH3_Pos = 0x4
	// Bit mask of IN_CHECK_OWNER_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_CHECK_OWNER_CH3_Msk = 0x10
	// Bit IN_CHECK_OWNER_CH3.
	H264_DMA_IN_CONF0_CH3_IN_CHECK_OWNER_CH3 = 0x10
	// Position of IN_MEM_BURST_LENGTH_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_MEM_BURST_LENGTH_CH3_Pos = 0x6
	// Bit mask of IN_MEM_BURST_LENGTH_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_MEM_BURST_LENGTH_CH3_Msk = 0x1c0
	// Position of IN_PAGE_BOUND_EN_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_PAGE_BOUND_EN_CH3_Pos = 0xc
	// Bit mask of IN_PAGE_BOUND_EN_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_PAGE_BOUND_EN_CH3_Msk = 0x1000
	// Bit IN_PAGE_BOUND_EN_CH3.
	H264_DMA_IN_CONF0_CH3_IN_PAGE_BOUND_EN_CH3 = 0x1000
	// Position of IN_RST_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_RST_CH3_Pos = 0x18
	// Bit mask of IN_RST_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_RST_CH3_Msk = 0x1000000
	// Bit IN_RST_CH3.
	H264_DMA_IN_CONF0_CH3_IN_RST_CH3 = 0x1000000
	// Position of IN_CMD_DISABLE_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_CMD_DISABLE_CH3_Pos = 0x19
	// Bit mask of IN_CMD_DISABLE_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_CMD_DISABLE_CH3_Msk = 0x2000000
	// Bit IN_CMD_DISABLE_CH3.
	H264_DMA_IN_CONF0_CH3_IN_CMD_DISABLE_CH3 = 0x2000000
	// Position of IN_ARB_WEIGHT_OPT_DIS_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_ARB_WEIGHT_OPT_DIS_CH3_Pos = 0x1a
	// Bit mask of IN_ARB_WEIGHT_OPT_DIS_CH3 field.
	H264_DMA_IN_CONF0_CH3_IN_ARB_WEIGHT_OPT_DIS_CH3_Msk = 0x4000000
	// Bit IN_ARB_WEIGHT_OPT_DIS_CH3.
	H264_DMA_IN_CONF0_CH3_IN_ARB_WEIGHT_OPT_DIS_CH3 = 0x4000000

	// IN_INT_RAW_CH3: RX CH3 interrupt raw register
	// Position of IN_DONE_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DONE_CH3_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DONE_CH3_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_IN_DONE_CH3_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_SUC_EOF_CH3_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_SUC_EOF_CH3_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_IN_SUC_EOF_CH3_INT_RAW = 0x2
	// Position of IN_ERR_EOF_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_ERR_EOF_CH3_INT_RAW_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_ERR_EOF_CH3_INT_RAW_Msk = 0x4
	// Bit IN_ERR_EOF_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_IN_ERR_EOF_CH3_INT_RAW = 0x4
	// Position of IN_DSCR_ERR_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_ERR_CH3_INT_RAW_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_ERR_CH3_INT_RAW_Msk = 0x8
	// Bit IN_DSCR_ERR_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_ERR_CH3_INT_RAW = 0x8
	// Position of INFIFO_OVF_L1_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_OVF_L1_CH3_INT_RAW_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_OVF_L1_CH3_INT_RAW_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_OVF_L1_CH3_INT_RAW = 0x10
	// Position of INFIFO_UDF_L1_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_UDF_L1_CH3_INT_RAW_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_UDF_L1_CH3_INT_RAW_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_UDF_L1_CH3_INT_RAW = 0x20
	// Position of INFIFO_OVF_L2_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_OVF_L2_CH3_INT_RAW_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_OVF_L2_CH3_INT_RAW_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_OVF_L2_CH3_INT_RAW = 0x40
	// Position of INFIFO_UDF_L2_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_UDF_L2_CH3_INT_RAW_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_UDF_L2_CH3_INT_RAW_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_INFIFO_UDF_L2_CH3_INT_RAW = 0x80
	// Position of IN_DSCR_EMPTY_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_EMPTY_CH3_INT_RAW_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_EMPTY_CH3_INT_RAW_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_EMPTY_CH3_INT_RAW = 0x100
	// Position of IN_DSCR_TASK_OVF_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_TASK_OVF_CH3_INT_RAW_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH3_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_TASK_OVF_CH3_INT_RAW_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH3_INT_RAW.
	H264_DMA_IN_INT_RAW_CH3_IN_DSCR_TASK_OVF_CH3_INT_RAW = 0x200

	// IN_INT_ENA_CH3: RX CH3 interrupt ena register
	// Position of IN_DONE_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DONE_CH3_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DONE_CH3_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_IN_DONE_CH3_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_SUC_EOF_CH3_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_SUC_EOF_CH3_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_IN_SUC_EOF_CH3_INT_ENA = 0x2
	// Position of IN_ERR_EOF_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_ERR_EOF_CH3_INT_ENA_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_ERR_EOF_CH3_INT_ENA_Msk = 0x4
	// Bit IN_ERR_EOF_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_IN_ERR_EOF_CH3_INT_ENA = 0x4
	// Position of IN_DSCR_ERR_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_ERR_CH3_INT_ENA_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_ERR_CH3_INT_ENA_Msk = 0x8
	// Bit IN_DSCR_ERR_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_ERR_CH3_INT_ENA = 0x8
	// Position of INFIFO_OVF_L1_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_OVF_L1_CH3_INT_ENA_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_OVF_L1_CH3_INT_ENA_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_OVF_L1_CH3_INT_ENA = 0x10
	// Position of INFIFO_UDF_L1_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_UDF_L1_CH3_INT_ENA_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_UDF_L1_CH3_INT_ENA_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_UDF_L1_CH3_INT_ENA = 0x20
	// Position of INFIFO_OVF_L2_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_OVF_L2_CH3_INT_ENA_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_OVF_L2_CH3_INT_ENA_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_OVF_L2_CH3_INT_ENA = 0x40
	// Position of INFIFO_UDF_L2_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_UDF_L2_CH3_INT_ENA_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_UDF_L2_CH3_INT_ENA_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_INFIFO_UDF_L2_CH3_INT_ENA = 0x80
	// Position of IN_DSCR_EMPTY_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_EMPTY_CH3_INT_ENA_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_EMPTY_CH3_INT_ENA_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_EMPTY_CH3_INT_ENA = 0x100
	// Position of IN_DSCR_TASK_OVF_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_TASK_OVF_CH3_INT_ENA_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH3_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_TASK_OVF_CH3_INT_ENA_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH3_INT_ENA.
	H264_DMA_IN_INT_ENA_CH3_IN_DSCR_TASK_OVF_CH3_INT_ENA = 0x200

	// IN_INT_ST_CH3: RX CH3 interrupt st register
	// Position of IN_DONE_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DONE_CH3_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DONE_CH3_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_IN_DONE_CH3_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_SUC_EOF_CH3_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_SUC_EOF_CH3_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_IN_SUC_EOF_CH3_INT_ST = 0x2
	// Position of IN_ERR_EOF_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_ERR_EOF_CH3_INT_ST_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_ERR_EOF_CH3_INT_ST_Msk = 0x4
	// Bit IN_ERR_EOF_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_IN_ERR_EOF_CH3_INT_ST = 0x4
	// Position of IN_DSCR_ERR_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_ERR_CH3_INT_ST_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_ERR_CH3_INT_ST_Msk = 0x8
	// Bit IN_DSCR_ERR_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_ERR_CH3_INT_ST = 0x8
	// Position of INFIFO_OVF_L1_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_OVF_L1_CH3_INT_ST_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_OVF_L1_CH3_INT_ST_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_INFIFO_OVF_L1_CH3_INT_ST = 0x10
	// Position of INFIFO_UDF_L1_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_UDF_L1_CH3_INT_ST_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_UDF_L1_CH3_INT_ST_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_INFIFO_UDF_L1_CH3_INT_ST = 0x20
	// Position of INFIFO_OVF_L2_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_OVF_L2_CH3_INT_ST_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_OVF_L2_CH3_INT_ST_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_INFIFO_OVF_L2_CH3_INT_ST = 0x40
	// Position of INFIFO_UDF_L2_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_UDF_L2_CH3_INT_ST_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_INFIFO_UDF_L2_CH3_INT_ST_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_INFIFO_UDF_L2_CH3_INT_ST = 0x80
	// Position of IN_DSCR_EMPTY_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_EMPTY_CH3_INT_ST_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_EMPTY_CH3_INT_ST_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_EMPTY_CH3_INT_ST = 0x100
	// Position of IN_DSCR_TASK_OVF_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_TASK_OVF_CH3_INT_ST_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH3_INT_ST field.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_TASK_OVF_CH3_INT_ST_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH3_INT_ST.
	H264_DMA_IN_INT_ST_CH3_IN_DSCR_TASK_OVF_CH3_INT_ST = 0x200

	// IN_INT_CLR_CH3: RX CH3 interrupt clr register
	// Position of IN_DONE_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DONE_CH3_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DONE_CH3_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_IN_DONE_CH3_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_SUC_EOF_CH3_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_SUC_EOF_CH3_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_IN_SUC_EOF_CH3_INT_CLR = 0x2
	// Position of IN_ERR_EOF_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_ERR_EOF_CH3_INT_CLR_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_ERR_EOF_CH3_INT_CLR_Msk = 0x4
	// Bit IN_ERR_EOF_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_IN_ERR_EOF_CH3_INT_CLR = 0x4
	// Position of IN_DSCR_ERR_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_ERR_CH3_INT_CLR_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_ERR_CH3_INT_CLR_Msk = 0x8
	// Bit IN_DSCR_ERR_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_ERR_CH3_INT_CLR = 0x8
	// Position of INFIFO_OVF_L1_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_OVF_L1_CH3_INT_CLR_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_OVF_L1_CH3_INT_CLR_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_OVF_L1_CH3_INT_CLR = 0x10
	// Position of INFIFO_UDF_L1_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_UDF_L1_CH3_INT_CLR_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_UDF_L1_CH3_INT_CLR_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_UDF_L1_CH3_INT_CLR = 0x20
	// Position of INFIFO_OVF_L2_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_OVF_L2_CH3_INT_CLR_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_OVF_L2_CH3_INT_CLR_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_OVF_L2_CH3_INT_CLR = 0x40
	// Position of INFIFO_UDF_L2_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_UDF_L2_CH3_INT_CLR_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_UDF_L2_CH3_INT_CLR_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_INFIFO_UDF_L2_CH3_INT_CLR = 0x80
	// Position of IN_DSCR_EMPTY_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_EMPTY_CH3_INT_CLR_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_EMPTY_CH3_INT_CLR_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_EMPTY_CH3_INT_CLR = 0x100
	// Position of IN_DSCR_TASK_OVF_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_TASK_OVF_CH3_INT_CLR_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH3_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_TASK_OVF_CH3_INT_CLR_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH3_INT_CLR.
	H264_DMA_IN_INT_CLR_CH3_IN_DSCR_TASK_OVF_CH3_INT_CLR = 0x200

	// INFIFO_STATUS_CH3: RX CH3 INFIFO status register
	// Position of INFIFO_FULL_L2_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L2_CH3_Pos = 0x0
	// Bit mask of INFIFO_FULL_L2_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L2_CH3_Msk = 0x1
	// Bit INFIFO_FULL_L2_CH3.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L2_CH3 = 0x1
	// Position of INFIFO_EMPTY_L2_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L2_CH3_Pos = 0x1
	// Bit mask of INFIFO_EMPTY_L2_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L2_CH3_Msk = 0x2
	// Bit INFIFO_EMPTY_L2_CH3.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L2_CH3 = 0x2
	// Position of INFIFO_CNT_L2_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_CNT_L2_CH3_Pos = 0x2
	// Bit mask of INFIFO_CNT_L2_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_CNT_L2_CH3_Msk = 0x3c
	// Position of INFIFO_FULL_L1_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L1_CH3_Pos = 0x6
	// Bit mask of INFIFO_FULL_L1_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L1_CH3_Msk = 0x40
	// Bit INFIFO_FULL_L1_CH3.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L1_CH3 = 0x40
	// Position of INFIFO_EMPTY_L1_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L1_CH3_Pos = 0x7
	// Bit mask of INFIFO_EMPTY_L1_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L1_CH3_Msk = 0x80
	// Bit INFIFO_EMPTY_L1_CH3.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L1_CH3 = 0x80
	// Position of INFIFO_CNT_L1_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_CNT_L1_CH3_Pos = 0x8
	// Bit mask of INFIFO_CNT_L1_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_CNT_L1_CH3_Msk = 0x1f00
	// Position of INFIFO_FULL_L3_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L3_CH3_Pos = 0x10
	// Bit mask of INFIFO_FULL_L3_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L3_CH3_Msk = 0x10000
	// Bit INFIFO_FULL_L3_CH3.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_FULL_L3_CH3 = 0x10000
	// Position of INFIFO_EMPTY_L3_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L3_CH3_Pos = 0x11
	// Bit mask of INFIFO_EMPTY_L3_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L3_CH3_Msk = 0x20000
	// Bit INFIFO_EMPTY_L3_CH3.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_EMPTY_L3_CH3 = 0x20000
	// Position of INFIFO_CNT_L3_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_CNT_L3_CH3_Pos = 0x12
	// Bit mask of INFIFO_CNT_L3_CH3 field.
	H264_DMA_INFIFO_STATUS_CH3_INFIFO_CNT_L3_CH3_Msk = 0xc0000

	// IN_POP_CH3: RX CH3 INFIFO pop register
	// Position of INFIFO_RDATA_CH3 field.
	H264_DMA_IN_POP_CH3_INFIFO_RDATA_CH3_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH3 field.
	H264_DMA_IN_POP_CH3_INFIFO_RDATA_CH3_Msk = 0x7ff
	// Position of INFIFO_POP_CH3 field.
	H264_DMA_IN_POP_CH3_INFIFO_POP_CH3_Pos = 0xb
	// Bit mask of INFIFO_POP_CH3 field.
	H264_DMA_IN_POP_CH3_INFIFO_POP_CH3_Msk = 0x800
	// Bit INFIFO_POP_CH3.
	H264_DMA_IN_POP_CH3_INFIFO_POP_CH3 = 0x800

	// IN_LINK_CONF_CH3: RX CH3 in_link dscr ctrl register
	// Position of INLINK_AUTO_RET_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_AUTO_RET_CH3_Pos = 0x14
	// Bit mask of INLINK_AUTO_RET_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_AUTO_RET_CH3_Msk = 0x100000
	// Bit INLINK_AUTO_RET_CH3.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_AUTO_RET_CH3 = 0x100000
	// Position of INLINK_STOP_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_STOP_CH3_Pos = 0x15
	// Bit mask of INLINK_STOP_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_STOP_CH3_Msk = 0x200000
	// Bit INLINK_STOP_CH3.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_STOP_CH3 = 0x200000
	// Position of INLINK_START_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_START_CH3_Pos = 0x16
	// Bit mask of INLINK_START_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_START_CH3_Msk = 0x400000
	// Bit INLINK_START_CH3.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_START_CH3 = 0x400000
	// Position of INLINK_RESTART_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_RESTART_CH3_Pos = 0x17
	// Bit mask of INLINK_RESTART_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_RESTART_CH3_Msk = 0x800000
	// Bit INLINK_RESTART_CH3.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_RESTART_CH3 = 0x800000
	// Position of INLINK_PARK_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_PARK_CH3_Pos = 0x18
	// Bit mask of INLINK_PARK_CH3 field.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_PARK_CH3_Msk = 0x1000000
	// Bit INLINK_PARK_CH3.
	H264_DMA_IN_LINK_CONF_CH3_INLINK_PARK_CH3 = 0x1000000

	// IN_LINK_ADDR_CH3: RX CH3 in_link dscr addr register
	// Position of INLINK_ADDR_CH3 field.
	H264_DMA_IN_LINK_ADDR_CH3_INLINK_ADDR_CH3_Pos = 0x0
	// Bit mask of INLINK_ADDR_CH3 field.
	H264_DMA_IN_LINK_ADDR_CH3_INLINK_ADDR_CH3_Msk = 0xffffffff

	// IN_STATE_CH3: RX CH3 state register
	// Position of INLINK_DSCR_ADDR_CH3 field.
	H264_DMA_IN_STATE_CH3_INLINK_DSCR_ADDR_CH3_Pos = 0x0
	// Bit mask of INLINK_DSCR_ADDR_CH3 field.
	H264_DMA_IN_STATE_CH3_INLINK_DSCR_ADDR_CH3_Msk = 0x3ffff
	// Position of IN_DSCR_STATE_CH3 field.
	H264_DMA_IN_STATE_CH3_IN_DSCR_STATE_CH3_Pos = 0x12
	// Bit mask of IN_DSCR_STATE_CH3 field.
	H264_DMA_IN_STATE_CH3_IN_DSCR_STATE_CH3_Msk = 0xc0000
	// Position of IN_STATE_CH3 field.
	H264_DMA_IN_STATE_CH3_IN_STATE_CH3_Pos = 0x14
	// Bit mask of IN_STATE_CH3 field.
	H264_DMA_IN_STATE_CH3_IN_STATE_CH3_Msk = 0x700000
	// Position of IN_RESET_AVAIL_CH3 field.
	H264_DMA_IN_STATE_CH3_IN_RESET_AVAIL_CH3_Pos = 0x17
	// Bit mask of IN_RESET_AVAIL_CH3 field.
	H264_DMA_IN_STATE_CH3_IN_RESET_AVAIL_CH3_Msk = 0x800000
	// Bit IN_RESET_AVAIL_CH3.
	H264_DMA_IN_STATE_CH3_IN_RESET_AVAIL_CH3 = 0x800000

	// IN_SUC_EOF_DES_ADDR_CH3: RX CH3 eof des addr register
	// Position of IN_SUC_EOF_DES_ADDR_CH3 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_IN_SUC_EOF_DES_ADDR_CH3_Pos = 0x0
	// Bit mask of IN_SUC_EOF_DES_ADDR_CH3 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_IN_SUC_EOF_DES_ADDR_CH3_Msk = 0xffffffff

	// IN_ERR_EOF_DES_ADDR_CH3: RX CH3 err eof des addr register
	// Position of IN_ERR_EOF_DES_ADDR_CH3 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_IN_ERR_EOF_DES_ADDR_CH3_Pos = 0x0
	// Bit mask of IN_ERR_EOF_DES_ADDR_CH3 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_IN_ERR_EOF_DES_ADDR_CH3_Msk = 0xffffffff

	// IN_DSCR_CH3: RX CH3 next dscr addr register
	// Position of INLINK_DSCR_CH3 field.
	H264_DMA_IN_DSCR_CH3_INLINK_DSCR_CH3_Pos = 0x0
	// Bit mask of INLINK_DSCR_CH3 field.
	H264_DMA_IN_DSCR_CH3_INLINK_DSCR_CH3_Msk = 0xffffffff

	// IN_DSCR_BF0_CH3: RX CH3 last dscr addr register
	// Position of INLINK_DSCR_BF0_CH3 field.
	H264_DMA_IN_DSCR_BF0_CH3_INLINK_DSCR_BF0_CH3_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF0_CH3 field.
	H264_DMA_IN_DSCR_BF0_CH3_INLINK_DSCR_BF0_CH3_Msk = 0xffffffff

	// IN_DSCR_BF1_CH3: RX CH3 second-to-last dscr addr register
	// Position of INLINK_DSCR_BF1_CH3 field.
	H264_DMA_IN_DSCR_BF1_CH3_INLINK_DSCR_BF1_CH3_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF1_CH3 field.
	H264_DMA_IN_DSCR_BF1_CH3_INLINK_DSCR_BF1_CH3_Msk = 0xffffffff

	// IN_ARB_CH3: RX CH3 arb register
	// Position of IN_ARB_TOKEN_NUM_CH3 field.
	H264_DMA_IN_ARB_CH3_IN_ARB_TOKEN_NUM_CH3_Pos = 0x0
	// Bit mask of IN_ARB_TOKEN_NUM_CH3 field.
	H264_DMA_IN_ARB_CH3_IN_ARB_TOKEN_NUM_CH3_Msk = 0xf
	// Position of INTER_IN_ARB_PRIORITY_CH3 field.
	H264_DMA_IN_ARB_CH3_INTER_IN_ARB_PRIORITY_CH3_Pos = 0x6
	// Bit mask of INTER_IN_ARB_PRIORITY_CH3 field.
	H264_DMA_IN_ARB_CH3_INTER_IN_ARB_PRIORITY_CH3_Msk = 0x1c0

	// IN_ETM_CONF_CH3: RX CH3 ETM config register
	// Position of IN_ETM_EN_CH3 field.
	H264_DMA_IN_ETM_CONF_CH3_IN_ETM_EN_CH3_Pos = 0x0
	// Bit mask of IN_ETM_EN_CH3 field.
	H264_DMA_IN_ETM_CONF_CH3_IN_ETM_EN_CH3_Msk = 0x1
	// Bit IN_ETM_EN_CH3.
	H264_DMA_IN_ETM_CONF_CH3_IN_ETM_EN_CH3 = 0x1
	// Position of IN_ETM_LOOP_EN_CH3 field.
	H264_DMA_IN_ETM_CONF_CH3_IN_ETM_LOOP_EN_CH3_Pos = 0x1
	// Bit mask of IN_ETM_LOOP_EN_CH3 field.
	H264_DMA_IN_ETM_CONF_CH3_IN_ETM_LOOP_EN_CH3_Msk = 0x2
	// Bit IN_ETM_LOOP_EN_CH3.
	H264_DMA_IN_ETM_CONF_CH3_IN_ETM_LOOP_EN_CH3 = 0x2
	// Position of IN_DSCR_TASK_MAK_CH3 field.
	H264_DMA_IN_ETM_CONF_CH3_IN_DSCR_TASK_MAK_CH3_Pos = 0x2
	// Bit mask of IN_DSCR_TASK_MAK_CH3 field.
	H264_DMA_IN_ETM_CONF_CH3_IN_DSCR_TASK_MAK_CH3_Msk = 0xc

	// IN_FIFO_CNT_CH3: rx CH3 fifo cnt register
	// Position of IN_CMDFIFO_INFIFO_CNT_CH3 field.
	H264_DMA_IN_FIFO_CNT_CH3_IN_CMDFIFO_INFIFO_CNT_CH3_Pos = 0x0
	// Bit mask of IN_CMDFIFO_INFIFO_CNT_CH3 field.
	H264_DMA_IN_FIFO_CNT_CH3_IN_CMDFIFO_INFIFO_CNT_CH3_Msk = 0x3ff

	// IN_POP_DATA_CNT_CH3: rx CH3 pop data cnt register
	// Position of IN_CMDFIFO_POP_DATA_CNT_CH3 field.
	H264_DMA_IN_POP_DATA_CNT_CH3_IN_CMDFIFO_POP_DATA_CNT_CH3_Pos = 0x0
	// Bit mask of IN_CMDFIFO_POP_DATA_CNT_CH3 field.
	H264_DMA_IN_POP_DATA_CNT_CH3_IN_CMDFIFO_POP_DATA_CNT_CH3_Msk = 0xff

	// IN_XADDR_CH3: rx CH3 xaddr register
	// Position of IN_CMDFIFO_XADDR_CH3 field.
	H264_DMA_IN_XADDR_CH3_IN_CMDFIFO_XADDR_CH3_Pos = 0x0
	// Bit mask of IN_CMDFIFO_XADDR_CH3 field.
	H264_DMA_IN_XADDR_CH3_IN_CMDFIFO_XADDR_CH3_Msk = 0xffffffff

	// IN_BUF_HB_RCV_CH3: rx CH3 buf len hb rcv register
	// Position of IN_CMDFIFO_BUF_HB_RCV_CH3 field.
	H264_DMA_IN_BUF_HB_RCV_CH3_IN_CMDFIFO_BUF_HB_RCV_CH3_Pos = 0x0
	// Bit mask of IN_CMDFIFO_BUF_HB_RCV_CH3 field.
	H264_DMA_IN_BUF_HB_RCV_CH3_IN_CMDFIFO_BUF_HB_RCV_CH3_Msk = 0x1fffffff

	// IN_CONF0_CH4: RX CH4 config0 register
	// Position of INDSCR_BURST_EN_CH4 field.
	H264_DMA_IN_CONF0_CH4_INDSCR_BURST_EN_CH4_Pos = 0x2
	// Bit mask of INDSCR_BURST_EN_CH4 field.
	H264_DMA_IN_CONF0_CH4_INDSCR_BURST_EN_CH4_Msk = 0x4
	// Bit INDSCR_BURST_EN_CH4.
	H264_DMA_IN_CONF0_CH4_INDSCR_BURST_EN_CH4 = 0x4
	// Position of IN_ECC_AES_EN_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_ECC_AES_EN_CH4_Pos = 0x3
	// Bit mask of IN_ECC_AES_EN_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_ECC_AES_EN_CH4_Msk = 0x8
	// Bit IN_ECC_AES_EN_CH4.
	H264_DMA_IN_CONF0_CH4_IN_ECC_AES_EN_CH4 = 0x8
	// Position of IN_CHECK_OWNER_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_CHECK_OWNER_CH4_Pos = 0x4
	// Bit mask of IN_CHECK_OWNER_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_CHECK_OWNER_CH4_Msk = 0x10
	// Bit IN_CHECK_OWNER_CH4.
	H264_DMA_IN_CONF0_CH4_IN_CHECK_OWNER_CH4 = 0x10
	// Position of IN_MEM_BURST_LENGTH_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_MEM_BURST_LENGTH_CH4_Pos = 0x6
	// Bit mask of IN_MEM_BURST_LENGTH_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_MEM_BURST_LENGTH_CH4_Msk = 0x1c0
	// Position of IN_PAGE_BOUND_EN_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_PAGE_BOUND_EN_CH4_Pos = 0xc
	// Bit mask of IN_PAGE_BOUND_EN_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_PAGE_BOUND_EN_CH4_Msk = 0x1000
	// Bit IN_PAGE_BOUND_EN_CH4.
	H264_DMA_IN_CONF0_CH4_IN_PAGE_BOUND_EN_CH4 = 0x1000
	// Position of IN_RST_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_RST_CH4_Pos = 0x18
	// Bit mask of IN_RST_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_RST_CH4_Msk = 0x1000000
	// Bit IN_RST_CH4.
	H264_DMA_IN_CONF0_CH4_IN_RST_CH4 = 0x1000000
	// Position of IN_CMD_DISABLE_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_CMD_DISABLE_CH4_Pos = 0x19
	// Bit mask of IN_CMD_DISABLE_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_CMD_DISABLE_CH4_Msk = 0x2000000
	// Bit IN_CMD_DISABLE_CH4.
	H264_DMA_IN_CONF0_CH4_IN_CMD_DISABLE_CH4 = 0x2000000
	// Position of IN_ARB_WEIGHT_OPT_DIS_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_ARB_WEIGHT_OPT_DIS_CH4_Pos = 0x1a
	// Bit mask of IN_ARB_WEIGHT_OPT_DIS_CH4 field.
	H264_DMA_IN_CONF0_CH4_IN_ARB_WEIGHT_OPT_DIS_CH4_Msk = 0x4000000
	// Bit IN_ARB_WEIGHT_OPT_DIS_CH4.
	H264_DMA_IN_CONF0_CH4_IN_ARB_WEIGHT_OPT_DIS_CH4 = 0x4000000

	// IN_INT_RAW_CH4: RX CH4 interrupt raw register
	// Position of IN_DONE_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DONE_CH4_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DONE_CH4_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_IN_DONE_CH4_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_SUC_EOF_CH4_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_SUC_EOF_CH4_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_IN_SUC_EOF_CH4_INT_RAW = 0x2
	// Position of IN_ERR_EOF_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_ERR_EOF_CH4_INT_RAW_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_ERR_EOF_CH4_INT_RAW_Msk = 0x4
	// Bit IN_ERR_EOF_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_IN_ERR_EOF_CH4_INT_RAW = 0x4
	// Position of IN_DSCR_ERR_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_ERR_CH4_INT_RAW_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_ERR_CH4_INT_RAW_Msk = 0x8
	// Bit IN_DSCR_ERR_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_ERR_CH4_INT_RAW = 0x8
	// Position of INFIFO_OVF_L1_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_OVF_L1_CH4_INT_RAW_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_OVF_L1_CH4_INT_RAW_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_OVF_L1_CH4_INT_RAW = 0x10
	// Position of INFIFO_UDF_L1_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_UDF_L1_CH4_INT_RAW_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_UDF_L1_CH4_INT_RAW_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_UDF_L1_CH4_INT_RAW = 0x20
	// Position of INFIFO_OVF_L2_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_OVF_L2_CH4_INT_RAW_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_OVF_L2_CH4_INT_RAW_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_OVF_L2_CH4_INT_RAW = 0x40
	// Position of INFIFO_UDF_L2_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_UDF_L2_CH4_INT_RAW_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_UDF_L2_CH4_INT_RAW_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_INFIFO_UDF_L2_CH4_INT_RAW = 0x80
	// Position of IN_DSCR_EMPTY_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_EMPTY_CH4_INT_RAW_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_EMPTY_CH4_INT_RAW_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_EMPTY_CH4_INT_RAW = 0x100
	// Position of IN_DSCR_TASK_OVF_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_TASK_OVF_CH4_INT_RAW_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH4_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_TASK_OVF_CH4_INT_RAW_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH4_INT_RAW.
	H264_DMA_IN_INT_RAW_CH4_IN_DSCR_TASK_OVF_CH4_INT_RAW = 0x200

	// IN_INT_ENA_CH4: RX CH4 interrupt ena register
	// Position of IN_DONE_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DONE_CH4_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DONE_CH4_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_IN_DONE_CH4_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_SUC_EOF_CH4_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_SUC_EOF_CH4_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_IN_SUC_EOF_CH4_INT_ENA = 0x2
	// Position of IN_ERR_EOF_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_ERR_EOF_CH4_INT_ENA_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_ERR_EOF_CH4_INT_ENA_Msk = 0x4
	// Bit IN_ERR_EOF_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_IN_ERR_EOF_CH4_INT_ENA = 0x4
	// Position of IN_DSCR_ERR_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_ERR_CH4_INT_ENA_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_ERR_CH4_INT_ENA_Msk = 0x8
	// Bit IN_DSCR_ERR_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_ERR_CH4_INT_ENA = 0x8
	// Position of INFIFO_OVF_L1_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_OVF_L1_CH4_INT_ENA_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_OVF_L1_CH4_INT_ENA_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_OVF_L1_CH4_INT_ENA = 0x10
	// Position of INFIFO_UDF_L1_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_UDF_L1_CH4_INT_ENA_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_UDF_L1_CH4_INT_ENA_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_UDF_L1_CH4_INT_ENA = 0x20
	// Position of INFIFO_OVF_L2_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_OVF_L2_CH4_INT_ENA_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_OVF_L2_CH4_INT_ENA_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_OVF_L2_CH4_INT_ENA = 0x40
	// Position of INFIFO_UDF_L2_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_UDF_L2_CH4_INT_ENA_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_UDF_L2_CH4_INT_ENA_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_INFIFO_UDF_L2_CH4_INT_ENA = 0x80
	// Position of IN_DSCR_EMPTY_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_EMPTY_CH4_INT_ENA_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_EMPTY_CH4_INT_ENA_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_EMPTY_CH4_INT_ENA = 0x100
	// Position of IN_DSCR_TASK_OVF_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_TASK_OVF_CH4_INT_ENA_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH4_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_TASK_OVF_CH4_INT_ENA_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH4_INT_ENA.
	H264_DMA_IN_INT_ENA_CH4_IN_DSCR_TASK_OVF_CH4_INT_ENA = 0x200

	// IN_INT_ST_CH4: RX CH4 interrupt st register
	// Position of IN_DONE_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DONE_CH4_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DONE_CH4_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_IN_DONE_CH4_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_SUC_EOF_CH4_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_SUC_EOF_CH4_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_IN_SUC_EOF_CH4_INT_ST = 0x2
	// Position of IN_ERR_EOF_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_ERR_EOF_CH4_INT_ST_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_ERR_EOF_CH4_INT_ST_Msk = 0x4
	// Bit IN_ERR_EOF_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_IN_ERR_EOF_CH4_INT_ST = 0x4
	// Position of IN_DSCR_ERR_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_ERR_CH4_INT_ST_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_ERR_CH4_INT_ST_Msk = 0x8
	// Bit IN_DSCR_ERR_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_ERR_CH4_INT_ST = 0x8
	// Position of INFIFO_OVF_L1_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_OVF_L1_CH4_INT_ST_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_OVF_L1_CH4_INT_ST_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_INFIFO_OVF_L1_CH4_INT_ST = 0x10
	// Position of INFIFO_UDF_L1_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_UDF_L1_CH4_INT_ST_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_UDF_L1_CH4_INT_ST_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_INFIFO_UDF_L1_CH4_INT_ST = 0x20
	// Position of INFIFO_OVF_L2_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_OVF_L2_CH4_INT_ST_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_OVF_L2_CH4_INT_ST_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_INFIFO_OVF_L2_CH4_INT_ST = 0x40
	// Position of INFIFO_UDF_L2_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_UDF_L2_CH4_INT_ST_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_INFIFO_UDF_L2_CH4_INT_ST_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_INFIFO_UDF_L2_CH4_INT_ST = 0x80
	// Position of IN_DSCR_EMPTY_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_EMPTY_CH4_INT_ST_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_EMPTY_CH4_INT_ST_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_EMPTY_CH4_INT_ST = 0x100
	// Position of IN_DSCR_TASK_OVF_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_TASK_OVF_CH4_INT_ST_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH4_INT_ST field.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_TASK_OVF_CH4_INT_ST_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH4_INT_ST.
	H264_DMA_IN_INT_ST_CH4_IN_DSCR_TASK_OVF_CH4_INT_ST = 0x200

	// IN_INT_CLR_CH4: RX CH4 interrupt clr register
	// Position of IN_DONE_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DONE_CH4_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DONE_CH4_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_IN_DONE_CH4_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_SUC_EOF_CH4_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_SUC_EOF_CH4_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_IN_SUC_EOF_CH4_INT_CLR = 0x2
	// Position of IN_ERR_EOF_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_ERR_EOF_CH4_INT_CLR_Pos = 0x2
	// Bit mask of IN_ERR_EOF_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_ERR_EOF_CH4_INT_CLR_Msk = 0x4
	// Bit IN_ERR_EOF_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_IN_ERR_EOF_CH4_INT_CLR = 0x4
	// Position of IN_DSCR_ERR_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_ERR_CH4_INT_CLR_Pos = 0x3
	// Bit mask of IN_DSCR_ERR_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_ERR_CH4_INT_CLR_Msk = 0x8
	// Bit IN_DSCR_ERR_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_ERR_CH4_INT_CLR = 0x8
	// Position of INFIFO_OVF_L1_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_OVF_L1_CH4_INT_CLR_Pos = 0x4
	// Bit mask of INFIFO_OVF_L1_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_OVF_L1_CH4_INT_CLR_Msk = 0x10
	// Bit INFIFO_OVF_L1_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_OVF_L1_CH4_INT_CLR = 0x10
	// Position of INFIFO_UDF_L1_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_UDF_L1_CH4_INT_CLR_Pos = 0x5
	// Bit mask of INFIFO_UDF_L1_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_UDF_L1_CH4_INT_CLR_Msk = 0x20
	// Bit INFIFO_UDF_L1_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_UDF_L1_CH4_INT_CLR = 0x20
	// Position of INFIFO_OVF_L2_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_OVF_L2_CH4_INT_CLR_Pos = 0x6
	// Bit mask of INFIFO_OVF_L2_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_OVF_L2_CH4_INT_CLR_Msk = 0x40
	// Bit INFIFO_OVF_L2_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_OVF_L2_CH4_INT_CLR = 0x40
	// Position of INFIFO_UDF_L2_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_UDF_L2_CH4_INT_CLR_Pos = 0x7
	// Bit mask of INFIFO_UDF_L2_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_UDF_L2_CH4_INT_CLR_Msk = 0x80
	// Bit INFIFO_UDF_L2_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_INFIFO_UDF_L2_CH4_INT_CLR = 0x80
	// Position of IN_DSCR_EMPTY_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_EMPTY_CH4_INT_CLR_Pos = 0x8
	// Bit mask of IN_DSCR_EMPTY_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_EMPTY_CH4_INT_CLR_Msk = 0x100
	// Bit IN_DSCR_EMPTY_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_EMPTY_CH4_INT_CLR = 0x100
	// Position of IN_DSCR_TASK_OVF_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_TASK_OVF_CH4_INT_CLR_Pos = 0x9
	// Bit mask of IN_DSCR_TASK_OVF_CH4_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_TASK_OVF_CH4_INT_CLR_Msk = 0x200
	// Bit IN_DSCR_TASK_OVF_CH4_INT_CLR.
	H264_DMA_IN_INT_CLR_CH4_IN_DSCR_TASK_OVF_CH4_INT_CLR = 0x200

	// INFIFO_STATUS_CH4: RX CH4 INFIFO status register
	// Position of INFIFO_FULL_L2_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L2_CH4_Pos = 0x0
	// Bit mask of INFIFO_FULL_L2_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L2_CH4_Msk = 0x1
	// Bit INFIFO_FULL_L2_CH4.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L2_CH4 = 0x1
	// Position of INFIFO_EMPTY_L2_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L2_CH4_Pos = 0x1
	// Bit mask of INFIFO_EMPTY_L2_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L2_CH4_Msk = 0x2
	// Bit INFIFO_EMPTY_L2_CH4.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L2_CH4 = 0x2
	// Position of INFIFO_CNT_L2_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_CNT_L2_CH4_Pos = 0x2
	// Bit mask of INFIFO_CNT_L2_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_CNT_L2_CH4_Msk = 0x3c
	// Position of INFIFO_FULL_L1_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L1_CH4_Pos = 0x6
	// Bit mask of INFIFO_FULL_L1_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L1_CH4_Msk = 0x40
	// Bit INFIFO_FULL_L1_CH4.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L1_CH4 = 0x40
	// Position of INFIFO_EMPTY_L1_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L1_CH4_Pos = 0x7
	// Bit mask of INFIFO_EMPTY_L1_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L1_CH4_Msk = 0x80
	// Bit INFIFO_EMPTY_L1_CH4.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L1_CH4 = 0x80
	// Position of INFIFO_CNT_L1_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_CNT_L1_CH4_Pos = 0x8
	// Bit mask of INFIFO_CNT_L1_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_CNT_L1_CH4_Msk = 0x1f00
	// Position of INFIFO_FULL_L3_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L3_CH4_Pos = 0x10
	// Bit mask of INFIFO_FULL_L3_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L3_CH4_Msk = 0x10000
	// Bit INFIFO_FULL_L3_CH4.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_FULL_L3_CH4 = 0x10000
	// Position of INFIFO_EMPTY_L3_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L3_CH4_Pos = 0x11
	// Bit mask of INFIFO_EMPTY_L3_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L3_CH4_Msk = 0x20000
	// Bit INFIFO_EMPTY_L3_CH4.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_EMPTY_L3_CH4 = 0x20000
	// Position of INFIFO_CNT_L3_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_CNT_L3_CH4_Pos = 0x12
	// Bit mask of INFIFO_CNT_L3_CH4 field.
	H264_DMA_INFIFO_STATUS_CH4_INFIFO_CNT_L3_CH4_Msk = 0xc0000

	// IN_POP_CH4: RX CH4 INFIFO pop register
	// Position of INFIFO_RDATA_CH4 field.
	H264_DMA_IN_POP_CH4_INFIFO_RDATA_CH4_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH4 field.
	H264_DMA_IN_POP_CH4_INFIFO_RDATA_CH4_Msk = 0x7ff
	// Position of INFIFO_POP_CH4 field.
	H264_DMA_IN_POP_CH4_INFIFO_POP_CH4_Pos = 0xb
	// Bit mask of INFIFO_POP_CH4 field.
	H264_DMA_IN_POP_CH4_INFIFO_POP_CH4_Msk = 0x800
	// Bit INFIFO_POP_CH4.
	H264_DMA_IN_POP_CH4_INFIFO_POP_CH4 = 0x800

	// IN_LINK_CONF_CH4: RX CH4 in_link dscr ctrl register
	// Position of INLINK_AUTO_RET_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_AUTO_RET_CH4_Pos = 0x14
	// Bit mask of INLINK_AUTO_RET_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_AUTO_RET_CH4_Msk = 0x100000
	// Bit INLINK_AUTO_RET_CH4.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_AUTO_RET_CH4 = 0x100000
	// Position of INLINK_STOP_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_STOP_CH4_Pos = 0x15
	// Bit mask of INLINK_STOP_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_STOP_CH4_Msk = 0x200000
	// Bit INLINK_STOP_CH4.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_STOP_CH4 = 0x200000
	// Position of INLINK_START_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_START_CH4_Pos = 0x16
	// Bit mask of INLINK_START_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_START_CH4_Msk = 0x400000
	// Bit INLINK_START_CH4.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_START_CH4 = 0x400000
	// Position of INLINK_RESTART_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_RESTART_CH4_Pos = 0x17
	// Bit mask of INLINK_RESTART_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_RESTART_CH4_Msk = 0x800000
	// Bit INLINK_RESTART_CH4.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_RESTART_CH4 = 0x800000
	// Position of INLINK_PARK_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_PARK_CH4_Pos = 0x18
	// Bit mask of INLINK_PARK_CH4 field.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_PARK_CH4_Msk = 0x1000000
	// Bit INLINK_PARK_CH4.
	H264_DMA_IN_LINK_CONF_CH4_INLINK_PARK_CH4 = 0x1000000

	// IN_LINK_ADDR_CH4: RX CH4 in_link dscr addr register
	// Position of INLINK_ADDR_CH4 field.
	H264_DMA_IN_LINK_ADDR_CH4_INLINK_ADDR_CH4_Pos = 0x0
	// Bit mask of INLINK_ADDR_CH4 field.
	H264_DMA_IN_LINK_ADDR_CH4_INLINK_ADDR_CH4_Msk = 0xffffffff

	// IN_STATE_CH4: RX CH4 state register
	// Position of INLINK_DSCR_ADDR_CH4 field.
	H264_DMA_IN_STATE_CH4_INLINK_DSCR_ADDR_CH4_Pos = 0x0
	// Bit mask of INLINK_DSCR_ADDR_CH4 field.
	H264_DMA_IN_STATE_CH4_INLINK_DSCR_ADDR_CH4_Msk = 0x3ffff
	// Position of IN_DSCR_STATE_CH4 field.
	H264_DMA_IN_STATE_CH4_IN_DSCR_STATE_CH4_Pos = 0x12
	// Bit mask of IN_DSCR_STATE_CH4 field.
	H264_DMA_IN_STATE_CH4_IN_DSCR_STATE_CH4_Msk = 0xc0000
	// Position of IN_STATE_CH4 field.
	H264_DMA_IN_STATE_CH4_IN_STATE_CH4_Pos = 0x14
	// Bit mask of IN_STATE_CH4 field.
	H264_DMA_IN_STATE_CH4_IN_STATE_CH4_Msk = 0x700000
	// Position of IN_RESET_AVAIL_CH4 field.
	H264_DMA_IN_STATE_CH4_IN_RESET_AVAIL_CH4_Pos = 0x17
	// Bit mask of IN_RESET_AVAIL_CH4 field.
	H264_DMA_IN_STATE_CH4_IN_RESET_AVAIL_CH4_Msk = 0x800000
	// Bit IN_RESET_AVAIL_CH4.
	H264_DMA_IN_STATE_CH4_IN_RESET_AVAIL_CH4 = 0x800000

	// IN_SUC_EOF_DES_ADDR_CH4: RX CH4 eof des addr register
	// Position of IN_SUC_EOF_DES_ADDR_CH4 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_IN_SUC_EOF_DES_ADDR_CH4_Pos = 0x0
	// Bit mask of IN_SUC_EOF_DES_ADDR_CH4 field.
	H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_IN_SUC_EOF_DES_ADDR_CH4_Msk = 0xffffffff

	// IN_ERR_EOF_DES_ADDR_CH4: RX CH4 err eof des addr register
	// Position of IN_ERR_EOF_DES_ADDR_CH4 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_IN_ERR_EOF_DES_ADDR_CH4_Pos = 0x0
	// Bit mask of IN_ERR_EOF_DES_ADDR_CH4 field.
	H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_IN_ERR_EOF_DES_ADDR_CH4_Msk = 0xffffffff

	// IN_DSCR_CH4: RX CH4 next dscr addr register
	// Position of INLINK_DSCR_CH4 field.
	H264_DMA_IN_DSCR_CH4_INLINK_DSCR_CH4_Pos = 0x0
	// Bit mask of INLINK_DSCR_CH4 field.
	H264_DMA_IN_DSCR_CH4_INLINK_DSCR_CH4_Msk = 0xffffffff

	// IN_DSCR_BF0_CH4: RX CH4 last dscr addr register
	// Position of INLINK_DSCR_BF0_CH4 field.
	H264_DMA_IN_DSCR_BF0_CH4_INLINK_DSCR_BF0_CH4_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF0_CH4 field.
	H264_DMA_IN_DSCR_BF0_CH4_INLINK_DSCR_BF0_CH4_Msk = 0xffffffff

	// IN_DSCR_BF1_CH4: RX CH4 second-to-last dscr addr register
	// Position of INLINK_DSCR_BF1_CH4 field.
	H264_DMA_IN_DSCR_BF1_CH4_INLINK_DSCR_BF1_CH4_Pos = 0x0
	// Bit mask of INLINK_DSCR_BF1_CH4 field.
	H264_DMA_IN_DSCR_BF1_CH4_INLINK_DSCR_BF1_CH4_Msk = 0xffffffff

	// IN_ARB_CH4: RX CH4 arb register
	// Position of IN_ARB_TOKEN_NUM_CH4 field.
	H264_DMA_IN_ARB_CH4_IN_ARB_TOKEN_NUM_CH4_Pos = 0x0
	// Bit mask of IN_ARB_TOKEN_NUM_CH4 field.
	H264_DMA_IN_ARB_CH4_IN_ARB_TOKEN_NUM_CH4_Msk = 0xf
	// Position of EXTER_IN_ARB_PRIORITY_CH4 field.
	H264_DMA_IN_ARB_CH4_EXTER_IN_ARB_PRIORITY_CH4_Pos = 0x4
	// Bit mask of EXTER_IN_ARB_PRIORITY_CH4 field.
	H264_DMA_IN_ARB_CH4_EXTER_IN_ARB_PRIORITY_CH4_Msk = 0x30
	// Position of INTER_IN_ARB_PRIORITY_CH4 field.
	H264_DMA_IN_ARB_CH4_INTER_IN_ARB_PRIORITY_CH4_Pos = 0x6
	// Bit mask of INTER_IN_ARB_PRIORITY_CH4 field.
	H264_DMA_IN_ARB_CH4_INTER_IN_ARB_PRIORITY_CH4_Msk = 0x1c0

	// IN_ETM_CONF_CH4: RX CH4 ETM config register
	// Position of IN_ETM_EN_CH4 field.
	H264_DMA_IN_ETM_CONF_CH4_IN_ETM_EN_CH4_Pos = 0x0
	// Bit mask of IN_ETM_EN_CH4 field.
	H264_DMA_IN_ETM_CONF_CH4_IN_ETM_EN_CH4_Msk = 0x1
	// Bit IN_ETM_EN_CH4.
	H264_DMA_IN_ETM_CONF_CH4_IN_ETM_EN_CH4 = 0x1
	// Position of IN_ETM_LOOP_EN_CH4 field.
	H264_DMA_IN_ETM_CONF_CH4_IN_ETM_LOOP_EN_CH4_Pos = 0x1
	// Bit mask of IN_ETM_LOOP_EN_CH4 field.
	H264_DMA_IN_ETM_CONF_CH4_IN_ETM_LOOP_EN_CH4_Msk = 0x2
	// Bit IN_ETM_LOOP_EN_CH4.
	H264_DMA_IN_ETM_CONF_CH4_IN_ETM_LOOP_EN_CH4 = 0x2
	// Position of IN_DSCR_TASK_MAK_CH4 field.
	H264_DMA_IN_ETM_CONF_CH4_IN_DSCR_TASK_MAK_CH4_Pos = 0x2
	// Bit mask of IN_DSCR_TASK_MAK_CH4 field.
	H264_DMA_IN_ETM_CONF_CH4_IN_DSCR_TASK_MAK_CH4_Msk = 0xc

	// IN_FIFO_CNT_CH4: rx CH4 fifo cnt register
	// Position of IN_CMDFIFO_INFIFO_CNT_CH4 field.
	H264_DMA_IN_FIFO_CNT_CH4_IN_CMDFIFO_INFIFO_CNT_CH4_Pos = 0x0
	// Bit mask of IN_CMDFIFO_INFIFO_CNT_CH4 field.
	H264_DMA_IN_FIFO_CNT_CH4_IN_CMDFIFO_INFIFO_CNT_CH4_Msk = 0x3ff

	// IN_POP_DATA_CNT_CH4: rx CH4 pop data cnt register
	// Position of IN_CMDFIFO_POP_DATA_CNT_CH4 field.
	H264_DMA_IN_POP_DATA_CNT_CH4_IN_CMDFIFO_POP_DATA_CNT_CH4_Pos = 0x0
	// Bit mask of IN_CMDFIFO_POP_DATA_CNT_CH4 field.
	H264_DMA_IN_POP_DATA_CNT_CH4_IN_CMDFIFO_POP_DATA_CNT_CH4_Msk = 0xff

	// IN_XADDR_CH4: rx CH4 xaddr register
	// Position of IN_CMDFIFO_XADDR_CH4 field.
	H264_DMA_IN_XADDR_CH4_IN_CMDFIFO_XADDR_CH4_Pos = 0x0
	// Bit mask of IN_CMDFIFO_XADDR_CH4 field.
	H264_DMA_IN_XADDR_CH4_IN_CMDFIFO_XADDR_CH4_Msk = 0xffffffff

	// IN_BUF_HB_RCV_CH4: rx CH4 buf len hb rcv register
	// Position of IN_CMDFIFO_BUF_HB_RCV_CH4 field.
	H264_DMA_IN_BUF_HB_RCV_CH4_IN_CMDFIFO_BUF_HB_RCV_CH4_Pos = 0x0
	// Bit mask of IN_CMDFIFO_BUF_HB_RCV_CH4 field.
	H264_DMA_IN_BUF_HB_RCV_CH4_IN_CMDFIFO_BUF_HB_RCV_CH4_Msk = 0x1fffffff

	// IN_CONF0_CH5: RX CH5 config0 register
	// Position of IN_ECC_AES_EN_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_ECC_AES_EN_CH5_Pos = 0x3
	// Bit mask of IN_ECC_AES_EN_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_ECC_AES_EN_CH5_Msk = 0x8
	// Bit IN_ECC_AES_EN_CH5.
	H264_DMA_IN_CONF0_CH5_IN_ECC_AES_EN_CH5 = 0x8
	// Position of IN_MEM_BURST_LENGTH_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_MEM_BURST_LENGTH_CH5_Pos = 0x6
	// Bit mask of IN_MEM_BURST_LENGTH_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_MEM_BURST_LENGTH_CH5_Msk = 0x1c0
	// Position of IN_PAGE_BOUND_EN_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_PAGE_BOUND_EN_CH5_Pos = 0xc
	// Bit mask of IN_PAGE_BOUND_EN_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_PAGE_BOUND_EN_CH5_Msk = 0x1000
	// Bit IN_PAGE_BOUND_EN_CH5.
	H264_DMA_IN_CONF0_CH5_IN_PAGE_BOUND_EN_CH5 = 0x1000
	// Position of IN_RST_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_RST_CH5_Pos = 0x18
	// Bit mask of IN_RST_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_RST_CH5_Msk = 0x1000000
	// Bit IN_RST_CH5.
	H264_DMA_IN_CONF0_CH5_IN_RST_CH5 = 0x1000000
	// Position of IN_CMD_DISABLE_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_CMD_DISABLE_CH5_Pos = 0x19
	// Bit mask of IN_CMD_DISABLE_CH5 field.
	H264_DMA_IN_CONF0_CH5_IN_CMD_DISABLE_CH5_Msk = 0x2000000
	// Bit IN_CMD_DISABLE_CH5.
	H264_DMA_IN_CONF0_CH5_IN_CMD_DISABLE_CH5 = 0x2000000

	// IN_CONF1_CH5: RX CH5 config1 register
	// Position of BLOCK_START_ADDR_CH5 field.
	H264_DMA_IN_CONF1_CH5_BLOCK_START_ADDR_CH5_Pos = 0x0
	// Bit mask of BLOCK_START_ADDR_CH5 field.
	H264_DMA_IN_CONF1_CH5_BLOCK_START_ADDR_CH5_Msk = 0xffffffff

	// IN_CONF2_CH5: RX CH5 config2 register
	// Position of BLOCK_ROW_LENGTH_12LINE_CH5 field.
	H264_DMA_IN_CONF2_CH5_BLOCK_ROW_LENGTH_12LINE_CH5_Pos = 0x0
	// Bit mask of BLOCK_ROW_LENGTH_12LINE_CH5 field.
	H264_DMA_IN_CONF2_CH5_BLOCK_ROW_LENGTH_12LINE_CH5_Msk = 0xffff
	// Position of BLOCK_ROW_LENGTH_4LINE_CH5 field.
	H264_DMA_IN_CONF2_CH5_BLOCK_ROW_LENGTH_4LINE_CH5_Pos = 0x10
	// Bit mask of BLOCK_ROW_LENGTH_4LINE_CH5 field.
	H264_DMA_IN_CONF2_CH5_BLOCK_ROW_LENGTH_4LINE_CH5_Msk = 0xffff0000

	// IN_CONF3_CH5: RX CH5 config3 register
	// Position of BLOCK_LENGTH_12LINE_CH5 field.
	H264_DMA_IN_CONF3_CH5_BLOCK_LENGTH_12LINE_CH5_Pos = 0x0
	// Bit mask of BLOCK_LENGTH_12LINE_CH5 field.
	H264_DMA_IN_CONF3_CH5_BLOCK_LENGTH_12LINE_CH5_Msk = 0x3fff
	// Position of BLOCK_LENGTH_4LINE_CH5 field.
	H264_DMA_IN_CONF3_CH5_BLOCK_LENGTH_4LINE_CH5_Pos = 0xe
	// Bit mask of BLOCK_LENGTH_4LINE_CH5 field.
	H264_DMA_IN_CONF3_CH5_BLOCK_LENGTH_4LINE_CH5_Msk = 0xfffc000

	// IN_INT_RAW_CH5: RX CH5 interrupt raw register
	// Position of IN_DONE_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_IN_DONE_CH5_INT_RAW_Pos = 0x0
	// Bit mask of IN_DONE_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_IN_DONE_CH5_INT_RAW_Msk = 0x1
	// Bit IN_DONE_CH5_INT_RAW.
	H264_DMA_IN_INT_RAW_CH5_IN_DONE_CH5_INT_RAW = 0x1
	// Position of IN_SUC_EOF_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_IN_SUC_EOF_CH5_INT_RAW_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_IN_SUC_EOF_CH5_INT_RAW_Msk = 0x2
	// Bit IN_SUC_EOF_CH5_INT_RAW.
	H264_DMA_IN_INT_RAW_CH5_IN_SUC_EOF_CH5_INT_RAW = 0x2
	// Position of INFIFO_OVF_L1_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_INFIFO_OVF_L1_CH5_INT_RAW_Pos = 0x2
	// Bit mask of INFIFO_OVF_L1_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_INFIFO_OVF_L1_CH5_INT_RAW_Msk = 0x4
	// Bit INFIFO_OVF_L1_CH5_INT_RAW.
	H264_DMA_IN_INT_RAW_CH5_INFIFO_OVF_L1_CH5_INT_RAW = 0x4
	// Position of INFIFO_UDF_L1_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_INFIFO_UDF_L1_CH5_INT_RAW_Pos = 0x3
	// Bit mask of INFIFO_UDF_L1_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_INFIFO_UDF_L1_CH5_INT_RAW_Msk = 0x8
	// Bit INFIFO_UDF_L1_CH5_INT_RAW.
	H264_DMA_IN_INT_RAW_CH5_INFIFO_UDF_L1_CH5_INT_RAW = 0x8
	// Position of FETCH_MB_COL_CNT_OVF_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_Pos = 0x4
	// Bit mask of FETCH_MB_COL_CNT_OVF_CH5_INT_RAW field.
	H264_DMA_IN_INT_RAW_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_Msk = 0x10
	// Bit FETCH_MB_COL_CNT_OVF_CH5_INT_RAW.
	H264_DMA_IN_INT_RAW_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW = 0x10

	// IN_INT_ENA_CH5: RX CH5 interrupt ena register
	// Position of IN_DONE_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_IN_DONE_CH5_INT_ENA_Pos = 0x0
	// Bit mask of IN_DONE_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_IN_DONE_CH5_INT_ENA_Msk = 0x1
	// Bit IN_DONE_CH5_INT_ENA.
	H264_DMA_IN_INT_ENA_CH5_IN_DONE_CH5_INT_ENA = 0x1
	// Position of IN_SUC_EOF_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_IN_SUC_EOF_CH5_INT_ENA_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_IN_SUC_EOF_CH5_INT_ENA_Msk = 0x2
	// Bit IN_SUC_EOF_CH5_INT_ENA.
	H264_DMA_IN_INT_ENA_CH5_IN_SUC_EOF_CH5_INT_ENA = 0x2
	// Position of INFIFO_OVF_L1_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_INFIFO_OVF_L1_CH5_INT_ENA_Pos = 0x2
	// Bit mask of INFIFO_OVF_L1_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_INFIFO_OVF_L1_CH5_INT_ENA_Msk = 0x4
	// Bit INFIFO_OVF_L1_CH5_INT_ENA.
	H264_DMA_IN_INT_ENA_CH5_INFIFO_OVF_L1_CH5_INT_ENA = 0x4
	// Position of INFIFO_UDF_L1_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_INFIFO_UDF_L1_CH5_INT_ENA_Pos = 0x3
	// Bit mask of INFIFO_UDF_L1_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_INFIFO_UDF_L1_CH5_INT_ENA_Msk = 0x8
	// Bit INFIFO_UDF_L1_CH5_INT_ENA.
	H264_DMA_IN_INT_ENA_CH5_INFIFO_UDF_L1_CH5_INT_ENA = 0x8
	// Position of FETCH_MB_COL_CNT_OVF_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_Pos = 0x4
	// Bit mask of FETCH_MB_COL_CNT_OVF_CH5_INT_ENA field.
	H264_DMA_IN_INT_ENA_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_Msk = 0x10
	// Bit FETCH_MB_COL_CNT_OVF_CH5_INT_ENA.
	H264_DMA_IN_INT_ENA_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA = 0x10

	// IN_INT_ST_CH5: RX CH5 interrupt st register
	// Position of IN_DONE_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_IN_DONE_CH5_INT_ST_Pos = 0x0
	// Bit mask of IN_DONE_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_IN_DONE_CH5_INT_ST_Msk = 0x1
	// Bit IN_DONE_CH5_INT_ST.
	H264_DMA_IN_INT_ST_CH5_IN_DONE_CH5_INT_ST = 0x1
	// Position of IN_SUC_EOF_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_IN_SUC_EOF_CH5_INT_ST_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_IN_SUC_EOF_CH5_INT_ST_Msk = 0x2
	// Bit IN_SUC_EOF_CH5_INT_ST.
	H264_DMA_IN_INT_ST_CH5_IN_SUC_EOF_CH5_INT_ST = 0x2
	// Position of INFIFO_OVF_L1_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_INFIFO_OVF_L1_CH5_INT_ST_Pos = 0x2
	// Bit mask of INFIFO_OVF_L1_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_INFIFO_OVF_L1_CH5_INT_ST_Msk = 0x4
	// Bit INFIFO_OVF_L1_CH5_INT_ST.
	H264_DMA_IN_INT_ST_CH5_INFIFO_OVF_L1_CH5_INT_ST = 0x4
	// Position of INFIFO_UDF_L1_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_INFIFO_UDF_L1_CH5_INT_ST_Pos = 0x3
	// Bit mask of INFIFO_UDF_L1_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_INFIFO_UDF_L1_CH5_INT_ST_Msk = 0x8
	// Bit INFIFO_UDF_L1_CH5_INT_ST.
	H264_DMA_IN_INT_ST_CH5_INFIFO_UDF_L1_CH5_INT_ST = 0x8
	// Position of FETCH_MB_COL_CNT_OVF_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_Pos = 0x4
	// Bit mask of FETCH_MB_COL_CNT_OVF_CH5_INT_ST field.
	H264_DMA_IN_INT_ST_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_Msk = 0x10
	// Bit FETCH_MB_COL_CNT_OVF_CH5_INT_ST.
	H264_DMA_IN_INT_ST_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_ST = 0x10

	// IN_INT_CLR_CH5: RX CH5 interrupt clr register
	// Position of IN_DONE_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_IN_DONE_CH5_INT_CLR_Pos = 0x0
	// Bit mask of IN_DONE_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_IN_DONE_CH5_INT_CLR_Msk = 0x1
	// Bit IN_DONE_CH5_INT_CLR.
	H264_DMA_IN_INT_CLR_CH5_IN_DONE_CH5_INT_CLR = 0x1
	// Position of IN_SUC_EOF_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_IN_SUC_EOF_CH5_INT_CLR_Pos = 0x1
	// Bit mask of IN_SUC_EOF_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_IN_SUC_EOF_CH5_INT_CLR_Msk = 0x2
	// Bit IN_SUC_EOF_CH5_INT_CLR.
	H264_DMA_IN_INT_CLR_CH5_IN_SUC_EOF_CH5_INT_CLR = 0x2
	// Position of INFIFO_OVF_L1_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_INFIFO_OVF_L1_CH5_INT_CLR_Pos = 0x2
	// Bit mask of INFIFO_OVF_L1_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_INFIFO_OVF_L1_CH5_INT_CLR_Msk = 0x4
	// Bit INFIFO_OVF_L1_CH5_INT_CLR.
	H264_DMA_IN_INT_CLR_CH5_INFIFO_OVF_L1_CH5_INT_CLR = 0x4
	// Position of INFIFO_UDF_L1_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_INFIFO_UDF_L1_CH5_INT_CLR_Pos = 0x3
	// Bit mask of INFIFO_UDF_L1_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_INFIFO_UDF_L1_CH5_INT_CLR_Msk = 0x8
	// Bit INFIFO_UDF_L1_CH5_INT_CLR.
	H264_DMA_IN_INT_CLR_CH5_INFIFO_UDF_L1_CH5_INT_CLR = 0x8
	// Position of FETCH_MB_COL_CNT_OVF_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_Pos = 0x4
	// Bit mask of FETCH_MB_COL_CNT_OVF_CH5_INT_CLR field.
	H264_DMA_IN_INT_CLR_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_Msk = 0x10
	// Bit FETCH_MB_COL_CNT_OVF_CH5_INT_CLR.
	H264_DMA_IN_INT_CLR_CH5_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR = 0x10

	// INFIFO_STATUS_CH5: RX CH5 INFIFO status register
	// Position of INFIFO_FULL_L1_CH5 field.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_FULL_L1_CH5_Pos = 0x0
	// Bit mask of INFIFO_FULL_L1_CH5 field.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_FULL_L1_CH5_Msk = 0x1
	// Bit INFIFO_FULL_L1_CH5.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_FULL_L1_CH5 = 0x1
	// Position of INFIFO_EMPTY_L1_CH5 field.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_EMPTY_L1_CH5_Pos = 0x1
	// Bit mask of INFIFO_EMPTY_L1_CH5 field.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_EMPTY_L1_CH5_Msk = 0x2
	// Bit INFIFO_EMPTY_L1_CH5.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_EMPTY_L1_CH5 = 0x2
	// Position of INFIFO_CNT_L1_CH5 field.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_CNT_L1_CH5_Pos = 0x2
	// Bit mask of INFIFO_CNT_L1_CH5 field.
	H264_DMA_INFIFO_STATUS_CH5_INFIFO_CNT_L1_CH5_Msk = 0x7c

	// IN_POP_CH5: RX CH5 INFIFO pop register
	// Position of INFIFO_RDATA_CH5 field.
	H264_DMA_IN_POP_CH5_INFIFO_RDATA_CH5_Pos = 0x0
	// Bit mask of INFIFO_RDATA_CH5 field.
	H264_DMA_IN_POP_CH5_INFIFO_RDATA_CH5_Msk = 0x7ff
	// Position of INFIFO_POP_CH5 field.
	H264_DMA_IN_POP_CH5_INFIFO_POP_CH5_Pos = 0xb
	// Bit mask of INFIFO_POP_CH5 field.
	H264_DMA_IN_POP_CH5_INFIFO_POP_CH5_Msk = 0x800
	// Bit INFIFO_POP_CH5.
	H264_DMA_IN_POP_CH5_INFIFO_POP_CH5 = 0x800

	// IN_STATE_CH5: RX CH5 state register
	// Position of IN_STATE_CH5 field.
	H264_DMA_IN_STATE_CH5_IN_STATE_CH5_Pos = 0x0
	// Bit mask of IN_STATE_CH5 field.
	H264_DMA_IN_STATE_CH5_IN_STATE_CH5_Msk = 0x7
	// Position of IN_RESET_AVAIL_CH5 field.
	H264_DMA_IN_STATE_CH5_IN_RESET_AVAIL_CH5_Pos = 0x3
	// Bit mask of IN_RESET_AVAIL_CH5 field.
	H264_DMA_IN_STATE_CH5_IN_RESET_AVAIL_CH5_Msk = 0x8
	// Bit IN_RESET_AVAIL_CH5.
	H264_DMA_IN_STATE_CH5_IN_RESET_AVAIL_CH5 = 0x8

	// IN_ARB_CH5: RX CH5 arb register
	// Position of IN_ARB_TOKEN_NUM_CH5 field.
	H264_DMA_IN_ARB_CH5_IN_ARB_TOKEN_NUM_CH5_Pos = 0x0
	// Bit mask of IN_ARB_TOKEN_NUM_CH5 field.
	H264_DMA_IN_ARB_CH5_IN_ARB_TOKEN_NUM_CH5_Msk = 0xf
	// Position of INTER_IN_ARB_PRIORITY_CH5 field.
	H264_DMA_IN_ARB_CH5_INTER_IN_ARB_PRIORITY_CH5_Pos = 0x6
	// Bit mask of INTER_IN_ARB_PRIORITY_CH5 field.
	H264_DMA_IN_ARB_CH5_INTER_IN_ARB_PRIORITY_CH5_Msk = 0x1c0

	// IN_FIFO_CNT_CH5: rx CH5 fifo cnt register
	// Position of IN_CMDFIFO_INFIFO_CNT_CH5 field.
	H264_DMA_IN_FIFO_CNT_CH5_IN_CMDFIFO_INFIFO_CNT_CH5_Pos = 0x0
	// Bit mask of IN_CMDFIFO_INFIFO_CNT_CH5 field.
	H264_DMA_IN_FIFO_CNT_CH5_IN_CMDFIFO_INFIFO_CNT_CH5_Msk = 0x3ff

	// IN_POP_DATA_CNT_CH5: rx CH5 pop data cnt register
	// Position of IN_CMDFIFO_POP_DATA_CNT_CH5 field.
	H264_DMA_IN_POP_DATA_CNT_CH5_IN_CMDFIFO_POP_DATA_CNT_CH5_Pos = 0x0
	// Bit mask of IN_CMDFIFO_POP_DATA_CNT_CH5 field.
	H264_DMA_IN_POP_DATA_CNT_CH5_IN_CMDFIFO_POP_DATA_CNT_CH5_Msk = 0xff

	// IN_XADDR_CH5: rx CH5 xaddr register
	// Position of IN_CMDFIFO_XADDR_CH5 field.
	H264_DMA_IN_XADDR_CH5_IN_CMDFIFO_XADDR_CH5_Pos = 0x0
	// Bit mask of IN_CMDFIFO_XADDR_CH5 field.
	H264_DMA_IN_XADDR_CH5_IN_CMDFIFO_XADDR_CH5_Msk = 0xffffffff

	// IN_BUF_HB_RCV_CH5: rx CH5 buf len hb rcv register
	// Position of IN_CMDFIFO_BUF_HB_RCV_CH5 field.
	H264_DMA_IN_BUF_HB_RCV_CH5_IN_CMDFIFO_BUF_HB_RCV_CH5_Pos = 0x0
	// Bit mask of IN_CMDFIFO_BUF_HB_RCV_CH5 field.
	H264_DMA_IN_BUF_HB_RCV_CH5_IN_CMDFIFO_BUF_HB_RCV_CH5_Msk = 0x1fffffff

	// INTER_AXI_ERR: inter memory axi err register
	// Position of INTER_RID_ERR_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RID_ERR_CNT_Pos = 0x0
	// Bit mask of INTER_RID_ERR_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RID_ERR_CNT_Msk = 0xf
	// Position of INTER_RRESP_ERR_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RRESP_ERR_CNT_Pos = 0x4
	// Bit mask of INTER_RRESP_ERR_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RRESP_ERR_CNT_Msk = 0xf0
	// Position of INTER_WRESP_ERR_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_WRESP_ERR_CNT_Pos = 0x8
	// Bit mask of INTER_WRESP_ERR_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_WRESP_ERR_CNT_Msk = 0xf00
	// Position of INTER_RD_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RD_FIFO_CNT_Pos = 0xc
	// Bit mask of INTER_RD_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RD_FIFO_CNT_Msk = 0x7000
	// Position of INTER_RD_BAK_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RD_BAK_FIFO_CNT_Pos = 0xf
	// Bit mask of INTER_RD_BAK_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_RD_BAK_FIFO_CNT_Msk = 0x78000
	// Position of INTER_WR_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_WR_FIFO_CNT_Pos = 0x13
	// Bit mask of INTER_WR_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_WR_FIFO_CNT_Msk = 0x380000
	// Position of INTER_WR_BAK_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_WR_BAK_FIFO_CNT_Pos = 0x16
	// Bit mask of INTER_WR_BAK_FIFO_CNT field.
	H264_DMA_INTER_AXI_ERR_INTER_WR_BAK_FIFO_CNT_Msk = 0x3c00000

	// EXTER_AXI_ERR: exter memory axi err register
	// Position of EXTER_RID_ERR_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RID_ERR_CNT_Pos = 0x0
	// Bit mask of EXTER_RID_ERR_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RID_ERR_CNT_Msk = 0xf
	// Position of EXTER_RRESP_ERR_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RRESP_ERR_CNT_Pos = 0x4
	// Bit mask of EXTER_RRESP_ERR_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RRESP_ERR_CNT_Msk = 0xf0
	// Position of EXTER_WRESP_ERR_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_WRESP_ERR_CNT_Pos = 0x8
	// Bit mask of EXTER_WRESP_ERR_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_WRESP_ERR_CNT_Msk = 0xf00
	// Position of EXTER_RD_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RD_FIFO_CNT_Pos = 0xc
	// Bit mask of EXTER_RD_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RD_FIFO_CNT_Msk = 0x7000
	// Position of EXTER_RD_BAK_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RD_BAK_FIFO_CNT_Pos = 0xf
	// Bit mask of EXTER_RD_BAK_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_RD_BAK_FIFO_CNT_Msk = 0x78000
	// Position of EXTER_WR_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_WR_FIFO_CNT_Pos = 0x13
	// Bit mask of EXTER_WR_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_WR_FIFO_CNT_Msk = 0x380000
	// Position of EXTER_WR_BAK_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_WR_BAK_FIFO_CNT_Pos = 0x16
	// Bit mask of EXTER_WR_BAK_FIFO_CNT field.
	H264_DMA_EXTER_AXI_ERR_EXTER_WR_BAK_FIFO_CNT_Msk = 0x3c00000

	// RST_CONF: axi reset config register
	// Position of INTER_AXIM_RD_RST field.
	H264_DMA_RST_CONF_INTER_AXIM_RD_RST_Pos = 0x0
	// Bit mask of INTER_AXIM_RD_RST field.
	H264_DMA_RST_CONF_INTER_AXIM_RD_RST_Msk = 0x1
	// Bit INTER_AXIM_RD_RST.
	H264_DMA_RST_CONF_INTER_AXIM_RD_RST = 0x1
	// Position of INTER_AXIM_WR_RST field.
	H264_DMA_RST_CONF_INTER_AXIM_WR_RST_Pos = 0x1
	// Bit mask of INTER_AXIM_WR_RST field.
	H264_DMA_RST_CONF_INTER_AXIM_WR_RST_Msk = 0x2
	// Bit INTER_AXIM_WR_RST.
	H264_DMA_RST_CONF_INTER_AXIM_WR_RST = 0x2
	// Position of EXTER_AXIM_RD_RST field.
	H264_DMA_RST_CONF_EXTER_AXIM_RD_RST_Pos = 0x2
	// Bit mask of EXTER_AXIM_RD_RST field.
	H264_DMA_RST_CONF_EXTER_AXIM_RD_RST_Msk = 0x4
	// Bit EXTER_AXIM_RD_RST.
	H264_DMA_RST_CONF_EXTER_AXIM_RD_RST = 0x4
	// Position of EXTER_AXIM_WR_RST field.
	H264_DMA_RST_CONF_EXTER_AXIM_WR_RST_Pos = 0x3
	// Bit mask of EXTER_AXIM_WR_RST field.
	H264_DMA_RST_CONF_EXTER_AXIM_WR_RST_Msk = 0x8
	// Bit EXTER_AXIM_WR_RST.
	H264_DMA_RST_CONF_EXTER_AXIM_WR_RST = 0x8
	// Position of CLK_EN field.
	H264_DMA_RST_CONF_CLK_EN_Pos = 0x4
	// Bit mask of CLK_EN field.
	H264_DMA_RST_CONF_CLK_EN_Msk = 0x10
	// Bit CLK_EN.
	H264_DMA_RST_CONF_CLK_EN = 0x10

	// INTER_MEM_START_ADDR0: Start address of inter memory range0 register
	// Position of ACCESS_INTER_MEM_START_ADDR0 field.
	H264_DMA_INTER_MEM_START_ADDR0_ACCESS_INTER_MEM_START_ADDR0_Pos = 0x0
	// Bit mask of ACCESS_INTER_MEM_START_ADDR0 field.
	H264_DMA_INTER_MEM_START_ADDR0_ACCESS_INTER_MEM_START_ADDR0_Msk = 0xffffffff

	// INTER_MEM_END_ADDR0: end address of inter memory range0 register
	// Position of ACCESS_INTER_MEM_END_ADDR0 field.
	H264_DMA_INTER_MEM_END_ADDR0_ACCESS_INTER_MEM_END_ADDR0_Pos = 0x0
	// Bit mask of ACCESS_INTER_MEM_END_ADDR0 field.
	H264_DMA_INTER_MEM_END_ADDR0_ACCESS_INTER_MEM_END_ADDR0_Msk = 0xffffffff

	// INTER_MEM_START_ADDR1: Start address of inter memory range1 register
	// Position of ACCESS_INTER_MEM_START_ADDR1 field.
	H264_DMA_INTER_MEM_START_ADDR1_ACCESS_INTER_MEM_START_ADDR1_Pos = 0x0
	// Bit mask of ACCESS_INTER_MEM_START_ADDR1 field.
	H264_DMA_INTER_MEM_START_ADDR1_ACCESS_INTER_MEM_START_ADDR1_Msk = 0xffffffff

	// INTER_MEM_END_ADDR1: end address of inter memory range1 register
	// Position of ACCESS_INTER_MEM_END_ADDR1 field.
	H264_DMA_INTER_MEM_END_ADDR1_ACCESS_INTER_MEM_END_ADDR1_Pos = 0x0
	// Bit mask of ACCESS_INTER_MEM_END_ADDR1 field.
	H264_DMA_INTER_MEM_END_ADDR1_ACCESS_INTER_MEM_END_ADDR1_Msk = 0xffffffff

	// EXTER_MEM_START_ADDR0: Start address of exter memory range0 register
	// Position of ACCESS_EXTER_MEM_START_ADDR0 field.
	H264_DMA_EXTER_MEM_START_ADDR0_ACCESS_EXTER_MEM_START_ADDR0_Pos = 0x0
	// Bit mask of ACCESS_EXTER_MEM_START_ADDR0 field.
	H264_DMA_EXTER_MEM_START_ADDR0_ACCESS_EXTER_MEM_START_ADDR0_Msk = 0xffffffff

	// EXTER_MEM_END_ADDR0: end address of exter memory range0 register
	// Position of ACCESS_EXTER_MEM_END_ADDR0 field.
	H264_DMA_EXTER_MEM_END_ADDR0_ACCESS_EXTER_MEM_END_ADDR0_Pos = 0x0
	// Bit mask of ACCESS_EXTER_MEM_END_ADDR0 field.
	H264_DMA_EXTER_MEM_END_ADDR0_ACCESS_EXTER_MEM_END_ADDR0_Msk = 0xffffffff

	// EXTER_MEM_START_ADDR1: Start address of exter memory range1 register
	// Position of ACCESS_EXTER_MEM_START_ADDR1 field.
	H264_DMA_EXTER_MEM_START_ADDR1_ACCESS_EXTER_MEM_START_ADDR1_Pos = 0x0
	// Bit mask of ACCESS_EXTER_MEM_START_ADDR1 field.
	H264_DMA_EXTER_MEM_START_ADDR1_ACCESS_EXTER_MEM_START_ADDR1_Msk = 0xffffffff

	// EXTER_MEM_END_ADDR1: end address of exter memory range1 register
	// Position of ACCESS_EXTER_MEM_END_ADDR1 field.
	H264_DMA_EXTER_MEM_END_ADDR1_ACCESS_EXTER_MEM_END_ADDR1_Pos = 0x0
	// Bit mask of ACCESS_EXTER_MEM_END_ADDR1 field.
	H264_DMA_EXTER_MEM_END_ADDR1_ACCESS_EXTER_MEM_END_ADDR1_Msk = 0xffffffff

	// OUT_ARB_CONFIG: reserved
	// Position of OUT_ARB_TIMEOUT_NUM field.
	H264_DMA_OUT_ARB_CONFIG_OUT_ARB_TIMEOUT_NUM_Pos = 0x0
	// Bit mask of OUT_ARB_TIMEOUT_NUM field.
	H264_DMA_OUT_ARB_CONFIG_OUT_ARB_TIMEOUT_NUM_Msk = 0xffff
	// Position of OUT_WEIGHT_EN field.
	H264_DMA_OUT_ARB_CONFIG_OUT_WEIGHT_EN_Pos = 0x10
	// Bit mask of OUT_WEIGHT_EN field.
	H264_DMA_OUT_ARB_CONFIG_OUT_WEIGHT_EN_Msk = 0x10000
	// Bit OUT_WEIGHT_EN.
	H264_DMA_OUT_ARB_CONFIG_OUT_WEIGHT_EN = 0x10000

	// IN_ARB_CONFIG: reserved
	// Position of IN_ARB_TIMEOUT_NUM field.
	H264_DMA_IN_ARB_CONFIG_IN_ARB_TIMEOUT_NUM_Pos = 0x0
	// Bit mask of IN_ARB_TIMEOUT_NUM field.
	H264_DMA_IN_ARB_CONFIG_IN_ARB_TIMEOUT_NUM_Msk = 0xffff
	// Position of IN_WEIGHT_EN field.
	H264_DMA_IN_ARB_CONFIG_IN_WEIGHT_EN_Pos = 0x10
	// Bit mask of IN_WEIGHT_EN field.
	H264_DMA_IN_ARB_CONFIG_IN_WEIGHT_EN_Msk = 0x10000
	// Bit IN_WEIGHT_EN.
	H264_DMA_IN_ARB_CONFIG_IN_WEIGHT_EN = 0x10000

	// DATE: reserved
	// Position of DATE field.
	H264_DMA_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	H264_DMA_DATE_DATE_Msk = 0xffffffff

	// COUNTER_RST: counter reset register
	// Position of RX_CH0_EXTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH0_EXTER_COUNTER_RST_Pos = 0x0
	// Bit mask of RX_CH0_EXTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH0_EXTER_COUNTER_RST_Msk = 0x1
	// Bit RX_CH0_EXTER_COUNTER_RST.
	H264_DMA_COUNTER_RST_RX_CH0_EXTER_COUNTER_RST = 0x1
	// Position of RX_CH1_EXTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH1_EXTER_COUNTER_RST_Pos = 0x1
	// Bit mask of RX_CH1_EXTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH1_EXTER_COUNTER_RST_Msk = 0x2
	// Bit RX_CH1_EXTER_COUNTER_RST.
	H264_DMA_COUNTER_RST_RX_CH1_EXTER_COUNTER_RST = 0x2
	// Position of RX_CH2_INTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH2_INTER_COUNTER_RST_Pos = 0x2
	// Bit mask of RX_CH2_INTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH2_INTER_COUNTER_RST_Msk = 0x4
	// Bit RX_CH2_INTER_COUNTER_RST.
	H264_DMA_COUNTER_RST_RX_CH2_INTER_COUNTER_RST = 0x4
	// Position of RX_CH5_INTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH5_INTER_COUNTER_RST_Pos = 0x3
	// Bit mask of RX_CH5_INTER_COUNTER_RST field.
	H264_DMA_COUNTER_RST_RX_CH5_INTER_COUNTER_RST_Msk = 0x8
	// Bit RX_CH5_INTER_COUNTER_RST.
	H264_DMA_COUNTER_RST_RX_CH5_INTER_COUNTER_RST = 0x8

	// RX_CH0_COUNTER: rx ch0 counter register
	// Position of RX_CH0_CNT field.
	H264_DMA_RX_CH0_COUNTER_RX_CH0_CNT_Pos = 0x0
	// Bit mask of RX_CH0_CNT field.
	H264_DMA_RX_CH0_COUNTER_RX_CH0_CNT_Msk = 0x7fffff

	// RX_CH1_COUNTER: rx ch1 counter register
	// Position of RX_CH1_CNT field.
	H264_DMA_RX_CH1_COUNTER_RX_CH1_CNT_Pos = 0x0
	// Bit mask of RX_CH1_CNT field.
	H264_DMA_RX_CH1_COUNTER_RX_CH1_CNT_Msk = 0x1fffff

	// RX_CH2_COUNTER: rx ch2 counter register
	// Position of RX_CH2_CNT field.
	H264_DMA_RX_CH2_COUNTER_RX_CH2_CNT_Pos = 0x0
	// Bit mask of RX_CH2_CNT field.
	H264_DMA_RX_CH2_COUNTER_RX_CH2_CNT_Msk = 0x7ff

	// RX_CH5_COUNTER: rx ch5 counter register
	// Position of RX_CH5_CNT field.
	H264_DMA_RX_CH5_COUNTER_RX_CH5_CNT_Pos = 0x0
	// Bit mask of RX_CH5_CNT field.
	H264_DMA_RX_CH5_COUNTER_RX_CH5_CNT_Msk = 0x1ffff
)

// Constants for HMAC: HMAC (Hash-based Message Authentication Code) Accelerator
const (
	// SET_START: Process control register 0.
	// Position of SET_START field.
	HMAC_SET_START_SET_START_Pos = 0x0
	// Bit mask of SET_START field.
	HMAC_SET_START_SET_START_Msk = 0x1
	// Bit SET_START.
	HMAC_SET_START_SET_START = 0x1

	// SET_PARA_PURPOSE: Configure purpose.
	// Position of PURPOSE_SET field.
	HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Pos = 0x0
	// Bit mask of PURPOSE_SET field.
	HMAC_SET_PARA_PURPOSE_PURPOSE_SET_Msk = 0xf

	// SET_PARA_KEY: Configure key.
	// Position of KEY_SET field.
	HMAC_SET_PARA_KEY_KEY_SET_Pos = 0x0
	// Bit mask of KEY_SET field.
	HMAC_SET_PARA_KEY_KEY_SET_Msk = 0x7

	// SET_PARA_FINISH: Finish initial configuration.
	// Position of SET_PARA_END field.
	HMAC_SET_PARA_FINISH_SET_PARA_END_Pos = 0x0
	// Bit mask of SET_PARA_END field.
	HMAC_SET_PARA_FINISH_SET_PARA_END_Msk = 0x1
	// Bit SET_PARA_END.
	HMAC_SET_PARA_FINISH_SET_PARA_END = 0x1

	// SET_MESSAGE_ONE: Process control register 1.
	// Position of SET_TEXT_ONE field.
	HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Pos = 0x0
	// Bit mask of SET_TEXT_ONE field.
	HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE_Msk = 0x1
	// Bit SET_TEXT_ONE.
	HMAC_SET_MESSAGE_ONE_SET_TEXT_ONE = 0x1

	// SET_MESSAGE_ING: Process control register 2.
	// Position of SET_TEXT_ING field.
	HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Pos = 0x0
	// Bit mask of SET_TEXT_ING field.
	HMAC_SET_MESSAGE_ING_SET_TEXT_ING_Msk = 0x1
	// Bit SET_TEXT_ING.
	HMAC_SET_MESSAGE_ING_SET_TEXT_ING = 0x1

	// SET_MESSAGE_END: Process control register 3.
	// Position of SET_TEXT_END field.
	HMAC_SET_MESSAGE_END_SET_TEXT_END_Pos = 0x0
	// Bit mask of SET_TEXT_END field.
	HMAC_SET_MESSAGE_END_SET_TEXT_END_Msk = 0x1
	// Bit SET_TEXT_END.
	HMAC_SET_MESSAGE_END_SET_TEXT_END = 0x1

	// SET_RESULT_FINISH: Process control register 4.
	// Position of SET_RESULT_END field.
	HMAC_SET_RESULT_FINISH_SET_RESULT_END_Pos = 0x0
	// Bit mask of SET_RESULT_END field.
	HMAC_SET_RESULT_FINISH_SET_RESULT_END_Msk = 0x1
	// Bit SET_RESULT_END.
	HMAC_SET_RESULT_FINISH_SET_RESULT_END = 0x1

	// SET_INVALIDATE_JTAG: Invalidate register 0.
	// Position of SET_INVALIDATE_JTAG field.
	HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Pos = 0x0
	// Bit mask of SET_INVALIDATE_JTAG field.
	HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG_Msk = 0x1
	// Bit SET_INVALIDATE_JTAG.
	HMAC_SET_INVALIDATE_JTAG_SET_INVALIDATE_JTAG = 0x1

	// SET_INVALIDATE_DS: Invalidate register 1.
	// Position of SET_INVALIDATE_DS field.
	HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Pos = 0x0
	// Bit mask of SET_INVALIDATE_DS field.
	HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS_Msk = 0x1
	// Bit SET_INVALIDATE_DS.
	HMAC_SET_INVALIDATE_DS_SET_INVALIDATE_DS = 0x1

	// QUERY_ERROR: Error register.
	// Position of QUERY_CHECK field.
	HMAC_QUERY_ERROR_QUERY_CHECK_Pos = 0x0
	// Bit mask of QUERY_CHECK field.
	HMAC_QUERY_ERROR_QUERY_CHECK_Msk = 0x1
	// Bit QUERY_CHECK.
	HMAC_QUERY_ERROR_QUERY_CHECK = 0x1

	// QUERY_BUSY: Busy register.
	// Position of BUSY_STATE field.
	HMAC_QUERY_BUSY_BUSY_STATE_Pos = 0x0
	// Bit mask of BUSY_STATE field.
	HMAC_QUERY_BUSY_BUSY_STATE_Msk = 0x1
	// Bit BUSY_STATE.
	HMAC_QUERY_BUSY_BUSY_STATE = 0x1

	// SET_MESSAGE_PAD: Process control register 5.
	// Position of SET_TEXT_PAD field.
	HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Pos = 0x0
	// Bit mask of SET_TEXT_PAD field.
	HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD_Msk = 0x1
	// Bit SET_TEXT_PAD.
	HMAC_SET_MESSAGE_PAD_SET_TEXT_PAD = 0x1

	// ONE_BLOCK: Process control register 6.
	// Position of SET_ONE_BLOCK field.
	HMAC_ONE_BLOCK_SET_ONE_BLOCK_Pos = 0x0
	// Bit mask of SET_ONE_BLOCK field.
	HMAC_ONE_BLOCK_SET_ONE_BLOCK_Msk = 0x1
	// Bit SET_ONE_BLOCK.
	HMAC_ONE_BLOCK_SET_ONE_BLOCK = 0x1

	// SOFT_JTAG_CTRL: Jtag register 0.
	// Position of SOFT_JTAG_CTRL field.
	HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Pos = 0x0
	// Bit mask of SOFT_JTAG_CTRL field.
	HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL_Msk = 0x1
	// Bit SOFT_JTAG_CTRL.
	HMAC_SOFT_JTAG_CTRL_SOFT_JTAG_CTRL = 0x1

	// WR_JTAG: Jtag register 1.
	// Position of WR_JTAG field.
	HMAC_WR_JTAG_WR_JTAG_Pos = 0x0
	// Bit mask of WR_JTAG field.
	HMAC_WR_JTAG_WR_JTAG_Msk = 0xffffffff

	// DATE: Date register.
	// Position of DATE field.
	HMAC_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	HMAC_DATE_DATE_Msk = 0x3fffffff
)

// Constants for HP_SYS: High-Power System
const (
	// VER_DATE: NA
	// Position of REG_VER_DATE field.
	HP_SYS_VER_DATE_REG_VER_DATE_Pos = 0x0
	// Bit mask of REG_VER_DATE field.
	HP_SYS_VER_DATE_REG_VER_DATE_Msk = 0xffffffff

	// CLK_EN: NA
	// Position of REG_CLK_EN field.
	HP_SYS_CLK_EN_REG_CLK_EN_Pos = 0x0
	// Bit mask of REG_CLK_EN field.
	HP_SYS_CLK_EN_REG_CLK_EN_Msk = 0x1
	// Bit REG_CLK_EN.
	HP_SYS_CLK_EN_REG_CLK_EN = 0x1

	// CPU_INTR_FROM_CPU_0: NA
	// Position of CPU_INTR_FROM_CPU_0 field.
	HP_SYS_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Pos = 0x0
	// Bit mask of CPU_INTR_FROM_CPU_0 field.
	HP_SYS_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0_Msk = 0x1
	// Bit CPU_INTR_FROM_CPU_0.
	HP_SYS_CPU_INTR_FROM_CPU_0_CPU_INTR_FROM_CPU_0 = 0x1

	// CPU_INTR_FROM_CPU_1: NA
	// Position of CPU_INTR_FROM_CPU_1 field.
	HP_SYS_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Pos = 0x0
	// Bit mask of CPU_INTR_FROM_CPU_1 field.
	HP_SYS_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1_Msk = 0x1
	// Bit CPU_INTR_FROM_CPU_1.
	HP_SYS_CPU_INTR_FROM_CPU_1_CPU_INTR_FROM_CPU_1 = 0x1

	// CPU_INTR_FROM_CPU_2: NA
	// Position of CPU_INTR_FROM_CPU_2 field.
	HP_SYS_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Pos = 0x0
	// Bit mask of CPU_INTR_FROM_CPU_2 field.
	HP_SYS_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2_Msk = 0x1
	// Bit CPU_INTR_FROM_CPU_2.
	HP_SYS_CPU_INTR_FROM_CPU_2_CPU_INTR_FROM_CPU_2 = 0x1

	// CPU_INTR_FROM_CPU_3: NA
	// Position of CPU_INTR_FROM_CPU_3 field.
	HP_SYS_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Pos = 0x0
	// Bit mask of CPU_INTR_FROM_CPU_3 field.
	HP_SYS_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3_Msk = 0x1
	// Bit CPU_INTR_FROM_CPU_3.
	HP_SYS_CPU_INTR_FROM_CPU_3_CPU_INTR_FROM_CPU_3 = 0x1

	// CACHE_CLK_CONFIG: NA
	// Position of REG_L2_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L2_CACHE_CLK_ON_Pos = 0x0
	// Bit mask of REG_L2_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L2_CACHE_CLK_ON_Msk = 0x1
	// Bit REG_L2_CACHE_CLK_ON.
	HP_SYS_CACHE_CLK_CONFIG_REG_L2_CACHE_CLK_ON = 0x1
	// Position of REG_L1_D_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_D_CACHE_CLK_ON_Pos = 0x1
	// Bit mask of REG_L1_D_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_D_CACHE_CLK_ON_Msk = 0x2
	// Bit REG_L1_D_CACHE_CLK_ON.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_D_CACHE_CLK_ON = 0x2
	// Position of REG_L1_I1_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_I1_CACHE_CLK_ON_Pos = 0x4
	// Bit mask of REG_L1_I1_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_I1_CACHE_CLK_ON_Msk = 0x10
	// Bit REG_L1_I1_CACHE_CLK_ON.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_I1_CACHE_CLK_ON = 0x10
	// Position of REG_L1_I0_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_I0_CACHE_CLK_ON_Pos = 0x5
	// Bit mask of REG_L1_I0_CACHE_CLK_ON field.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_I0_CACHE_CLK_ON_Msk = 0x20
	// Bit REG_L1_I0_CACHE_CLK_ON.
	HP_SYS_CACHE_CLK_CONFIG_REG_L1_I0_CACHE_CLK_ON = 0x20

	// CACHE_RESET_CONFIG: NA
	// Position of REG_L1_D_CACHE_RESET field.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_D_CACHE_RESET_Pos = 0x1
	// Bit mask of REG_L1_D_CACHE_RESET field.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_D_CACHE_RESET_Msk = 0x2
	// Bit REG_L1_D_CACHE_RESET.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_D_CACHE_RESET = 0x2
	// Position of REG_L1_I1_CACHE_RESET field.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_I1_CACHE_RESET_Pos = 0x4
	// Bit mask of REG_L1_I1_CACHE_RESET field.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_I1_CACHE_RESET_Msk = 0x10
	// Bit REG_L1_I1_CACHE_RESET.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_I1_CACHE_RESET = 0x10
	// Position of REG_L1_I0_CACHE_RESET field.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_I0_CACHE_RESET_Pos = 0x5
	// Bit mask of REG_L1_I0_CACHE_RESET field.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_I0_CACHE_RESET_Msk = 0x20
	// Bit REG_L1_I0_CACHE_RESET.
	HP_SYS_CACHE_RESET_CONFIG_REG_L1_I0_CACHE_RESET = 0x20

	// DMA_ADDR_CTRL: NA
	// Position of REG_SYS_DMA_ADDR_SEL field.
	HP_SYS_DMA_ADDR_CTRL_REG_SYS_DMA_ADDR_SEL_Pos = 0x0
	// Bit mask of REG_SYS_DMA_ADDR_SEL field.
	HP_SYS_DMA_ADDR_CTRL_REG_SYS_DMA_ADDR_SEL_Msk = 0x1
	// Bit REG_SYS_DMA_ADDR_SEL.
	HP_SYS_DMA_ADDR_CTRL_REG_SYS_DMA_ADDR_SEL = 0x1

	// TCM_RAM_WRR_CONFIG: NA
	// Position of REG_TCM_RAM_IBUS0_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS0_WT_Pos = 0x0
	// Bit mask of REG_TCM_RAM_IBUS0_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS0_WT_Msk = 0x7
	// Position of REG_TCM_RAM_IBUS1_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS1_WT_Pos = 0x3
	// Bit mask of REG_TCM_RAM_IBUS1_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS1_WT_Msk = 0x38
	// Position of REG_TCM_RAM_IBUS2_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS2_WT_Pos = 0x6
	// Bit mask of REG_TCM_RAM_IBUS2_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS2_WT_Msk = 0x1c0
	// Position of REG_TCM_RAM_IBUS3_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS3_WT_Pos = 0x9
	// Bit mask of REG_TCM_RAM_IBUS3_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_IBUS3_WT_Msk = 0xe00
	// Position of REG_TCM_RAM_DBUS0_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS0_WT_Pos = 0xc
	// Bit mask of REG_TCM_RAM_DBUS0_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS0_WT_Msk = 0x7000
	// Position of REG_TCM_RAM_DBUS1_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS1_WT_Pos = 0xf
	// Bit mask of REG_TCM_RAM_DBUS1_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS1_WT_Msk = 0x38000
	// Position of REG_TCM_RAM_DBUS2_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS2_WT_Pos = 0x12
	// Bit mask of REG_TCM_RAM_DBUS2_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS2_WT_Msk = 0x1c0000
	// Position of REG_TCM_RAM_DBUS3_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS3_WT_Pos = 0x15
	// Bit mask of REG_TCM_RAM_DBUS3_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DBUS3_WT_Msk = 0xe00000
	// Position of REG_TCM_RAM_DMA_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DMA_WT_Pos = 0x18
	// Bit mask of REG_TCM_RAM_DMA_WT field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_DMA_WT_Msk = 0x7000000
	// Position of REG_TCM_RAM_WRR_HIGH field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_WRR_HIGH_Pos = 0x1f
	// Bit mask of REG_TCM_RAM_WRR_HIGH field.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_WRR_HIGH_Msk = 0x80000000
	// Bit REG_TCM_RAM_WRR_HIGH.
	HP_SYS_TCM_RAM_WRR_CONFIG_REG_TCM_RAM_WRR_HIGH = 0x80000000

	// TCM_SW_PARITY_BWE_MASK: NA
	// Position of REG_TCM_SW_PARITY_BWE_MASK_CTRL field.
	HP_SYS_TCM_SW_PARITY_BWE_MASK_REG_TCM_SW_PARITY_BWE_MASK_CTRL_Pos = 0x0
	// Bit mask of REG_TCM_SW_PARITY_BWE_MASK_CTRL field.
	HP_SYS_TCM_SW_PARITY_BWE_MASK_REG_TCM_SW_PARITY_BWE_MASK_CTRL_Msk = 0x1
	// Bit REG_TCM_SW_PARITY_BWE_MASK_CTRL.
	HP_SYS_TCM_SW_PARITY_BWE_MASK_REG_TCM_SW_PARITY_BWE_MASK_CTRL = 0x1

	// TCM_RAM_PWR_CTRL0: NA
	// Position of REG_HP_TCM_CLK_FORCE_ON field.
	HP_SYS_TCM_RAM_PWR_CTRL0_REG_HP_TCM_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of REG_HP_TCM_CLK_FORCE_ON field.
	HP_SYS_TCM_RAM_PWR_CTRL0_REG_HP_TCM_CLK_FORCE_ON_Msk = 0x1
	// Bit REG_HP_TCM_CLK_FORCE_ON.
	HP_SYS_TCM_RAM_PWR_CTRL0_REG_HP_TCM_CLK_FORCE_ON = 0x1

	// L2_ROM_PWR_CTRL0: NA
	// Position of REG_L2_ROM_CLK_FORCE_ON field.
	HP_SYS_L2_ROM_PWR_CTRL0_REG_L2_ROM_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of REG_L2_ROM_CLK_FORCE_ON field.
	HP_SYS_L2_ROM_PWR_CTRL0_REG_L2_ROM_CLK_FORCE_ON_Msk = 0x1
	// Bit REG_L2_ROM_CLK_FORCE_ON.
	HP_SYS_L2_ROM_PWR_CTRL0_REG_L2_ROM_CLK_FORCE_ON = 0x1

	// PROBEA_CTRL: NA
	// Position of REG_PROBE_A_MOD_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_A_MOD_SEL_Pos = 0x0
	// Bit mask of REG_PROBE_A_MOD_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_A_MOD_SEL_Msk = 0xffff
	// Position of REG_PROBE_A_TOP_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_A_TOP_SEL_Pos = 0x10
	// Bit mask of REG_PROBE_A_TOP_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_A_TOP_SEL_Msk = 0xff0000
	// Position of REG_PROBE_L_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_L_SEL_Pos = 0x18
	// Bit mask of REG_PROBE_L_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_L_SEL_Msk = 0x3000000
	// Position of REG_PROBE_H_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_H_SEL_Pos = 0x1a
	// Bit mask of REG_PROBE_H_SEL field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_H_SEL_Msk = 0xc000000
	// Position of REG_PROBE_GLOBAL_EN field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_GLOBAL_EN_Pos = 0x1c
	// Bit mask of REG_PROBE_GLOBAL_EN field.
	HP_SYS_PROBEA_CTRL_REG_PROBE_GLOBAL_EN_Msk = 0x10000000
	// Bit REG_PROBE_GLOBAL_EN.
	HP_SYS_PROBEA_CTRL_REG_PROBE_GLOBAL_EN = 0x10000000

	// PROBEB_CTRL: NA
	// Position of REG_PROBE_B_MOD_SEL field.
	HP_SYS_PROBEB_CTRL_REG_PROBE_B_MOD_SEL_Pos = 0x0
	// Bit mask of REG_PROBE_B_MOD_SEL field.
	HP_SYS_PROBEB_CTRL_REG_PROBE_B_MOD_SEL_Msk = 0xffff
	// Position of REG_PROBE_B_TOP_SEL field.
	HP_SYS_PROBEB_CTRL_REG_PROBE_B_TOP_SEL_Pos = 0x10
	// Bit mask of REG_PROBE_B_TOP_SEL field.
	HP_SYS_PROBEB_CTRL_REG_PROBE_B_TOP_SEL_Msk = 0xff0000
	// Position of REG_PROBE_B_EN field.
	HP_SYS_PROBEB_CTRL_REG_PROBE_B_EN_Pos = 0x18
	// Bit mask of REG_PROBE_B_EN field.
	HP_SYS_PROBEB_CTRL_REG_PROBE_B_EN_Msk = 0x1000000
	// Bit REG_PROBE_B_EN.
	HP_SYS_PROBEB_CTRL_REG_PROBE_B_EN = 0x1000000

	// PROBE_OUT: NA
	// Position of REG_PROBE_TOP_OUT field.
	HP_SYS_PROBE_OUT_REG_PROBE_TOP_OUT_Pos = 0x0
	// Bit mask of REG_PROBE_TOP_OUT field.
	HP_SYS_PROBE_OUT_REG_PROBE_TOP_OUT_Msk = 0xffffffff

	// L2_MEM_RAM_PWR_CTRL0: NA
	// Position of REG_L2_MEM_CLK_FORCE_ON field.
	HP_SYS_L2_MEM_RAM_PWR_CTRL0_REG_L2_MEM_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of REG_L2_MEM_CLK_FORCE_ON field.
	HP_SYS_L2_MEM_RAM_PWR_CTRL0_REG_L2_MEM_CLK_FORCE_ON_Msk = 0x1
	// Bit REG_L2_MEM_CLK_FORCE_ON.
	HP_SYS_L2_MEM_RAM_PWR_CTRL0_REG_L2_MEM_CLK_FORCE_ON = 0x1

	// CPU_CORESTALLED_ST: NA
	// Position of REG_CORE0_CORESTALLED_ST field.
	HP_SYS_CPU_CORESTALLED_ST_REG_CORE0_CORESTALLED_ST_Pos = 0x0
	// Bit mask of REG_CORE0_CORESTALLED_ST field.
	HP_SYS_CPU_CORESTALLED_ST_REG_CORE0_CORESTALLED_ST_Msk = 0x1
	// Bit REG_CORE0_CORESTALLED_ST.
	HP_SYS_CPU_CORESTALLED_ST_REG_CORE0_CORESTALLED_ST = 0x1
	// Position of REG_CORE1_CORESTALLED_ST field.
	HP_SYS_CPU_CORESTALLED_ST_REG_CORE1_CORESTALLED_ST_Pos = 0x1
	// Bit mask of REG_CORE1_CORESTALLED_ST field.
	HP_SYS_CPU_CORESTALLED_ST_REG_CORE1_CORESTALLED_ST_Msk = 0x2
	// Bit REG_CORE1_CORESTALLED_ST.
	HP_SYS_CPU_CORESTALLED_ST_REG_CORE1_CORESTALLED_ST = 0x2

	// CRYPTO_CTRL: NA
	// Position of REG_ENABLE_SPI_MANUAL_ENCRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_SPI_MANUAL_ENCRYPT_Pos = 0x0
	// Bit mask of REG_ENABLE_SPI_MANUAL_ENCRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_SPI_MANUAL_ENCRYPT_Msk = 0x1
	// Bit REG_ENABLE_SPI_MANUAL_ENCRYPT.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_SPI_MANUAL_ENCRYPT = 0x1
	// Position of REG_ENABLE_DOWNLOAD_DB_ENCRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_Pos = 0x1
	// Bit mask of REG_ENABLE_DOWNLOAD_DB_ENCRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_Msk = 0x2
	// Bit REG_ENABLE_DOWNLOAD_DB_ENCRYPT.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_DB_ENCRYPT = 0x2
	// Position of REG_ENABLE_DOWNLOAD_G0CB_DECRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_Pos = 0x2
	// Bit mask of REG_ENABLE_DOWNLOAD_G0CB_DECRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_Msk = 0x4
	// Bit REG_ENABLE_DOWNLOAD_G0CB_DECRYPT.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT = 0x4
	// Position of REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Pos = 0x3
	// Bit mask of REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT field.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_Msk = 0x8
	// Bit REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT.
	HP_SYS_CRYPTO_CTRL_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT = 0x8

	// GPIO_O_HOLD_CTRL0: NA
	// Position of REG_GPIO_0_HOLD_LOW field.
	HP_SYS_GPIO_O_HOLD_CTRL0_REG_GPIO_0_HOLD_LOW_Pos = 0x0
	// Bit mask of REG_GPIO_0_HOLD_LOW field.
	HP_SYS_GPIO_O_HOLD_CTRL0_REG_GPIO_0_HOLD_LOW_Msk = 0xffffffff

	// GPIO_O_HOLD_CTRL1: NA
	// Position of REG_GPIO_0_HOLD_HIGH field.
	HP_SYS_GPIO_O_HOLD_CTRL1_REG_GPIO_0_HOLD_HIGH_Pos = 0x0
	// Bit mask of REG_GPIO_0_HOLD_HIGH field.
	HP_SYS_GPIO_O_HOLD_CTRL1_REG_GPIO_0_HOLD_HIGH_Msk = 0x1ff

	// RDN_ECO_CS: NA
	// Position of REG_HP_SYS_RDN_ECO_EN field.
	HP_SYS_RDN_ECO_CS_REG_HP_SYS_RDN_ECO_EN_Pos = 0x0
	// Bit mask of REG_HP_SYS_RDN_ECO_EN field.
	HP_SYS_RDN_ECO_CS_REG_HP_SYS_RDN_ECO_EN_Msk = 0x1
	// Bit REG_HP_SYS_RDN_ECO_EN.
	HP_SYS_RDN_ECO_CS_REG_HP_SYS_RDN_ECO_EN = 0x1
	// Position of REG_HP_SYS_RDN_ECO_RESULT field.
	HP_SYS_RDN_ECO_CS_REG_HP_SYS_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of REG_HP_SYS_RDN_ECO_RESULT field.
	HP_SYS_RDN_ECO_CS_REG_HP_SYS_RDN_ECO_RESULT_Msk = 0x2
	// Bit REG_HP_SYS_RDN_ECO_RESULT.
	HP_SYS_RDN_ECO_CS_REG_HP_SYS_RDN_ECO_RESULT = 0x2

	// CACHE_APB_POSTW_EN: NA
	// Position of REG_CACHE_APB_POSTW_EN field.
	HP_SYS_CACHE_APB_POSTW_EN_REG_CACHE_APB_POSTW_EN_Pos = 0x0
	// Bit mask of REG_CACHE_APB_POSTW_EN field.
	HP_SYS_CACHE_APB_POSTW_EN_REG_CACHE_APB_POSTW_EN_Msk = 0x1
	// Bit REG_CACHE_APB_POSTW_EN.
	HP_SYS_CACHE_APB_POSTW_EN_REG_CACHE_APB_POSTW_EN = 0x1

	// L2_MEM_SUBSIZE: NA
	// Position of REG_L2_MEM_SUB_BLKSIZE field.
	HP_SYS_L2_MEM_SUBSIZE_REG_L2_MEM_SUB_BLKSIZE_Pos = 0x0
	// Bit mask of REG_L2_MEM_SUB_BLKSIZE field.
	HP_SYS_L2_MEM_SUBSIZE_REG_L2_MEM_SUB_BLKSIZE_Msk = 0x3

	// L2_MEM_INT_RAW: NA
	// Position of REG_L2_MEM_ECC_ERR_INT_RAW field.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_ECC_ERR_INT_RAW_Pos = 0x0
	// Bit mask of REG_L2_MEM_ECC_ERR_INT_RAW field.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_ECC_ERR_INT_RAW_Msk = 0x1
	// Bit REG_L2_MEM_ECC_ERR_INT_RAW.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_ECC_ERR_INT_RAW = 0x1
	// Position of REG_L2_MEM_EXCEED_ADDR_INT_RAW field.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_EXCEED_ADDR_INT_RAW_Pos = 0x1
	// Bit mask of REG_L2_MEM_EXCEED_ADDR_INT_RAW field.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_EXCEED_ADDR_INT_RAW_Msk = 0x2
	// Bit REG_L2_MEM_EXCEED_ADDR_INT_RAW.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_EXCEED_ADDR_INT_RAW = 0x2
	// Position of REG_L2_MEM_ERR_RESP_INT_RAW field.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_ERR_RESP_INT_RAW_Pos = 0x2
	// Bit mask of REG_L2_MEM_ERR_RESP_INT_RAW field.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_ERR_RESP_INT_RAW_Msk = 0x4
	// Bit REG_L2_MEM_ERR_RESP_INT_RAW.
	HP_SYS_L2_MEM_INT_RAW_REG_L2_MEM_ERR_RESP_INT_RAW = 0x4

	// L2_MEM_INT_ST: NA
	// Position of REG_L2_MEM_ECC_ERR_INT_ST field.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_ECC_ERR_INT_ST_Pos = 0x0
	// Bit mask of REG_L2_MEM_ECC_ERR_INT_ST field.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_ECC_ERR_INT_ST_Msk = 0x1
	// Bit REG_L2_MEM_ECC_ERR_INT_ST.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_ECC_ERR_INT_ST = 0x1
	// Position of REG_L2_MEM_EXCEED_ADDR_INT_ST field.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_EXCEED_ADDR_INT_ST_Pos = 0x1
	// Bit mask of REG_L2_MEM_EXCEED_ADDR_INT_ST field.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_EXCEED_ADDR_INT_ST_Msk = 0x2
	// Bit REG_L2_MEM_EXCEED_ADDR_INT_ST.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_EXCEED_ADDR_INT_ST = 0x2
	// Position of REG_L2_MEM_ERR_RESP_INT_ST field.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_ERR_RESP_INT_ST_Pos = 0x2
	// Bit mask of REG_L2_MEM_ERR_RESP_INT_ST field.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_ERR_RESP_INT_ST_Msk = 0x4
	// Bit REG_L2_MEM_ERR_RESP_INT_ST.
	HP_SYS_L2_MEM_INT_ST_REG_L2_MEM_ERR_RESP_INT_ST = 0x4

	// L2_MEM_INT_ENA: NA
	// Position of REG_L2_MEM_ECC_ERR_INT_ENA field.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_ECC_ERR_INT_ENA_Pos = 0x0
	// Bit mask of REG_L2_MEM_ECC_ERR_INT_ENA field.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_ECC_ERR_INT_ENA_Msk = 0x1
	// Bit REG_L2_MEM_ECC_ERR_INT_ENA.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_ECC_ERR_INT_ENA = 0x1
	// Position of REG_L2_MEM_EXCEED_ADDR_INT_ENA field.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_EXCEED_ADDR_INT_ENA_Pos = 0x1
	// Bit mask of REG_L2_MEM_EXCEED_ADDR_INT_ENA field.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_EXCEED_ADDR_INT_ENA_Msk = 0x2
	// Bit REG_L2_MEM_EXCEED_ADDR_INT_ENA.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_EXCEED_ADDR_INT_ENA = 0x2
	// Position of REG_L2_MEM_ERR_RESP_INT_ENA field.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_ERR_RESP_INT_ENA_Pos = 0x2
	// Bit mask of REG_L2_MEM_ERR_RESP_INT_ENA field.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_ERR_RESP_INT_ENA_Msk = 0x4
	// Bit REG_L2_MEM_ERR_RESP_INT_ENA.
	HP_SYS_L2_MEM_INT_ENA_REG_L2_MEM_ERR_RESP_INT_ENA = 0x4

	// L2_MEM_INT_CLR: NA
	// Position of REG_L2_MEM_ECC_ERR_INT_CLR field.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_ECC_ERR_INT_CLR_Pos = 0x0
	// Bit mask of REG_L2_MEM_ECC_ERR_INT_CLR field.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_ECC_ERR_INT_CLR_Msk = 0x1
	// Bit REG_L2_MEM_ECC_ERR_INT_CLR.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_ECC_ERR_INT_CLR = 0x1
	// Position of REG_L2_MEM_EXCEED_ADDR_INT_CLR field.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_EXCEED_ADDR_INT_CLR_Pos = 0x1
	// Bit mask of REG_L2_MEM_EXCEED_ADDR_INT_CLR field.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_EXCEED_ADDR_INT_CLR_Msk = 0x2
	// Bit REG_L2_MEM_EXCEED_ADDR_INT_CLR.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_EXCEED_ADDR_INT_CLR = 0x2
	// Position of REG_L2_MEM_ERR_RESP_INT_CLR field.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_ERR_RESP_INT_CLR_Pos = 0x2
	// Bit mask of REG_L2_MEM_ERR_RESP_INT_CLR field.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_ERR_RESP_INT_CLR_Msk = 0x4
	// Bit REG_L2_MEM_ERR_RESP_INT_CLR.
	HP_SYS_L2_MEM_INT_CLR_REG_L2_MEM_ERR_RESP_INT_CLR = 0x4

	// L2_MEM_L2_RAM_ECC: NA
	// Position of REG_L2_RAM_UNIT0_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT0_ECC_EN_Pos = 0x0
	// Bit mask of REG_L2_RAM_UNIT0_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT0_ECC_EN_Msk = 0x1
	// Bit REG_L2_RAM_UNIT0_ECC_EN.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT0_ECC_EN = 0x1
	// Position of REG_L2_RAM_UNIT1_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT1_ECC_EN_Pos = 0x1
	// Bit mask of REG_L2_RAM_UNIT1_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT1_ECC_EN_Msk = 0x2
	// Bit REG_L2_RAM_UNIT1_ECC_EN.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT1_ECC_EN = 0x2
	// Position of REG_L2_RAM_UNIT2_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT2_ECC_EN_Pos = 0x2
	// Bit mask of REG_L2_RAM_UNIT2_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT2_ECC_EN_Msk = 0x4
	// Bit REG_L2_RAM_UNIT2_ECC_EN.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT2_ECC_EN = 0x4
	// Position of REG_L2_RAM_UNIT3_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT3_ECC_EN_Pos = 0x3
	// Bit mask of REG_L2_RAM_UNIT3_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT3_ECC_EN_Msk = 0x8
	// Bit REG_L2_RAM_UNIT3_ECC_EN.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT3_ECC_EN = 0x8
	// Position of REG_L2_RAM_UNIT4_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT4_ECC_EN_Pos = 0x4
	// Bit mask of REG_L2_RAM_UNIT4_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT4_ECC_EN_Msk = 0x10
	// Bit REG_L2_RAM_UNIT4_ECC_EN.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT4_ECC_EN = 0x10
	// Position of REG_L2_RAM_UNIT5_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT5_ECC_EN_Pos = 0x5
	// Bit mask of REG_L2_RAM_UNIT5_ECC_EN field.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT5_ECC_EN_Msk = 0x20
	// Bit REG_L2_RAM_UNIT5_ECC_EN.
	HP_SYS_L2_MEM_L2_RAM_ECC_REG_L2_RAM_UNIT5_ECC_EN = 0x20

	// L2_MEM_INT_RECORD0: NA
	// Position of REG_L2_MEM_EXCEED_ADDR_INT_ADDR field.
	HP_SYS_L2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_Pos = 0x0
	// Bit mask of REG_L2_MEM_EXCEED_ADDR_INT_ADDR field.
	HP_SYS_L2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_Msk = 0x1fffff
	// Position of REG_L2_MEM_EXCEED_ADDR_INT_WE field.
	HP_SYS_L2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_WE_Pos = 0x15
	// Bit mask of REG_L2_MEM_EXCEED_ADDR_INT_WE field.
	HP_SYS_L2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_WE_Msk = 0x200000
	// Bit REG_L2_MEM_EXCEED_ADDR_INT_WE.
	HP_SYS_L2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_WE = 0x200000
	// Position of REG_L2_MEM_EXCEED_ADDR_INT_MASTER field.
	HP_SYS_L2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_Pos = 0x16
	// Bit mask of REG_L2_MEM_EXCEED_ADDR_INT_MASTER field.
	HP_SYS_L2_MEM_INT_RECORD0_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_Msk = 0x1c00000

	// L2_MEM_INT_RECORD1: NA
	// Position of REG_L2_MEM_ECC_ERR_INT_ADDR field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_INT_ADDR_Pos = 0x0
	// Bit mask of REG_L2_MEM_ECC_ERR_INT_ADDR field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_INT_ADDR_Msk = 0x7fff
	// Position of REG_L2_MEM_ECC_ONE_BIT_ERR field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ONE_BIT_ERR_Pos = 0xf
	// Bit mask of REG_L2_MEM_ECC_ONE_BIT_ERR field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ONE_BIT_ERR_Msk = 0x8000
	// Bit REG_L2_MEM_ECC_ONE_BIT_ERR.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ONE_BIT_ERR = 0x8000
	// Position of REG_L2_MEM_ECC_TWO_BIT_ERR field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_TWO_BIT_ERR_Pos = 0x10
	// Bit mask of REG_L2_MEM_ECC_TWO_BIT_ERR field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_TWO_BIT_ERR_Msk = 0x10000
	// Bit REG_L2_MEM_ECC_TWO_BIT_ERR.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_TWO_BIT_ERR = 0x10000
	// Position of REG_L2_MEM_ECC_ERR_BIT field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_BIT_Pos = 0x11
	// Bit mask of REG_L2_MEM_ECC_ERR_BIT field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_MEM_ECC_ERR_BIT_Msk = 0x3fe0000
	// Position of REG_L2_CACHE_ERR_BANK field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_CACHE_ERR_BANK_Pos = 0x1a
	// Bit mask of REG_L2_CACHE_ERR_BANK field.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_CACHE_ERR_BANK_Msk = 0x4000000
	// Bit REG_L2_CACHE_ERR_BANK.
	HP_SYS_L2_MEM_INT_RECORD1_REG_L2_CACHE_ERR_BANK = 0x4000000

	// L2_MEM_L2_CACHE_ECC: NA
	// Position of REG_L2_CACHE_ECC_EN field.
	HP_SYS_L2_MEM_L2_CACHE_ECC_REG_L2_CACHE_ECC_EN_Pos = 0x0
	// Bit mask of REG_L2_CACHE_ECC_EN field.
	HP_SYS_L2_MEM_L2_CACHE_ECC_REG_L2_CACHE_ECC_EN_Msk = 0x1
	// Bit REG_L2_CACHE_ECC_EN.
	HP_SYS_L2_MEM_L2_CACHE_ECC_REG_L2_CACHE_ECC_EN = 0x1

	// L1CACHE_BUS0_ID: NA
	// Position of REG_L1_CACHE_BUS0_ID field.
	HP_SYS_L1CACHE_BUS0_ID_REG_L1_CACHE_BUS0_ID_Pos = 0x0
	// Bit mask of REG_L1_CACHE_BUS0_ID field.
	HP_SYS_L1CACHE_BUS0_ID_REG_L1_CACHE_BUS0_ID_Msk = 0xf

	// L1CACHE_BUS1_ID: NA
	// Position of REG_L1_CACHE_BUS1_ID field.
	HP_SYS_L1CACHE_BUS1_ID_REG_L1_CACHE_BUS1_ID_Pos = 0x0
	// Bit mask of REG_L1_CACHE_BUS1_ID field.
	HP_SYS_L1CACHE_BUS1_ID_REG_L1_CACHE_BUS1_ID_Msk = 0xf

	// L2_MEM_RDN_ECO_CS: NA
	// Position of REG_L2_MEM_RDN_ECO_EN field.
	HP_SYS_L2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_EN_Pos = 0x0
	// Bit mask of REG_L2_MEM_RDN_ECO_EN field.
	HP_SYS_L2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_EN_Msk = 0x1
	// Bit REG_L2_MEM_RDN_ECO_EN.
	HP_SYS_L2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_EN = 0x1
	// Position of REG_L2_MEM_RDN_ECO_RESULT field.
	HP_SYS_L2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of REG_L2_MEM_RDN_ECO_RESULT field.
	HP_SYS_L2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_RESULT_Msk = 0x2
	// Bit REG_L2_MEM_RDN_ECO_RESULT.
	HP_SYS_L2_MEM_RDN_ECO_CS_REG_L2_MEM_RDN_ECO_RESULT = 0x2

	// L2_MEM_RDN_ECO_LOW: NA
	// Position of REG_L2_MEM_RDN_ECO_LOW field.
	HP_SYS_L2_MEM_RDN_ECO_LOW_REG_L2_MEM_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of REG_L2_MEM_RDN_ECO_LOW field.
	HP_SYS_L2_MEM_RDN_ECO_LOW_REG_L2_MEM_RDN_ECO_LOW_Msk = 0xffffffff

	// L2_MEM_RDN_ECO_HIGH: NA
	// Position of REG_L2_MEM_RDN_ECO_HIGH field.
	HP_SYS_L2_MEM_RDN_ECO_HIGH_REG_L2_MEM_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of REG_L2_MEM_RDN_ECO_HIGH field.
	HP_SYS_L2_MEM_RDN_ECO_HIGH_REG_L2_MEM_RDN_ECO_HIGH_Msk = 0xffffffff

	// TCM_RDN_ECO_CS: NA
	// Position of REG_HP_TCM_RDN_ECO_EN field.
	HP_SYS_TCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_EN_Pos = 0x0
	// Bit mask of REG_HP_TCM_RDN_ECO_EN field.
	HP_SYS_TCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_EN_Msk = 0x1
	// Bit REG_HP_TCM_RDN_ECO_EN.
	HP_SYS_TCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_EN = 0x1
	// Position of REG_HP_TCM_RDN_ECO_RESULT field.
	HP_SYS_TCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of REG_HP_TCM_RDN_ECO_RESULT field.
	HP_SYS_TCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_RESULT_Msk = 0x2
	// Bit REG_HP_TCM_RDN_ECO_RESULT.
	HP_SYS_TCM_RDN_ECO_CS_REG_HP_TCM_RDN_ECO_RESULT = 0x2

	// TCM_RDN_ECO_LOW: NA
	// Position of REG_HP_TCM_RDN_ECO_LOW field.
	HP_SYS_TCM_RDN_ECO_LOW_REG_HP_TCM_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of REG_HP_TCM_RDN_ECO_LOW field.
	HP_SYS_TCM_RDN_ECO_LOW_REG_HP_TCM_RDN_ECO_LOW_Msk = 0xffffffff

	// TCM_RDN_ECO_HIGH: NA
	// Position of REG_HP_TCM_RDN_ECO_HIGH field.
	HP_SYS_TCM_RDN_ECO_HIGH_REG_HP_TCM_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of REG_HP_TCM_RDN_ECO_HIGH field.
	HP_SYS_TCM_RDN_ECO_HIGH_REG_HP_TCM_RDN_ECO_HIGH_Msk = 0xffffffff

	// GPIO_DED_HOLD_CTRL: NA
	// Position of REG_GPIO_DED_HOLD field.
	HP_SYS_GPIO_DED_HOLD_CTRL_REG_GPIO_DED_HOLD_Pos = 0x0
	// Bit mask of REG_GPIO_DED_HOLD field.
	HP_SYS_GPIO_DED_HOLD_CTRL_REG_GPIO_DED_HOLD_Msk = 0x3ffffff

	// L2_MEM_SW_ECC_BWE_MASK: NA
	// Position of REG_L2_MEM_SW_ECC_BWE_MASK_CTRL field.
	HP_SYS_L2_MEM_SW_ECC_BWE_MASK_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_Pos = 0x0
	// Bit mask of REG_L2_MEM_SW_ECC_BWE_MASK_CTRL field.
	HP_SYS_L2_MEM_SW_ECC_BWE_MASK_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_Msk = 0x1
	// Bit REG_L2_MEM_SW_ECC_BWE_MASK_CTRL.
	HP_SYS_L2_MEM_SW_ECC_BWE_MASK_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL = 0x1

	// USB20OTG_MEM_CTRL: NA
	// Position of REG_USB20_MEM_CLK_FORCE_ON field.
	HP_SYS_USB20OTG_MEM_CTRL_REG_USB20_MEM_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of REG_USB20_MEM_CLK_FORCE_ON field.
	HP_SYS_USB20OTG_MEM_CTRL_REG_USB20_MEM_CLK_FORCE_ON_Msk = 0x1
	// Bit REG_USB20_MEM_CLK_FORCE_ON.
	HP_SYS_USB20OTG_MEM_CTRL_REG_USB20_MEM_CLK_FORCE_ON = 0x1

	// TCM_INT_RAW: need_des
	// Position of TCM_PARITY_ERR_INT_RAW field.
	HP_SYS_TCM_INT_RAW_TCM_PARITY_ERR_INT_RAW_Pos = 0x1f
	// Bit mask of TCM_PARITY_ERR_INT_RAW field.
	HP_SYS_TCM_INT_RAW_TCM_PARITY_ERR_INT_RAW_Msk = 0x80000000
	// Bit TCM_PARITY_ERR_INT_RAW.
	HP_SYS_TCM_INT_RAW_TCM_PARITY_ERR_INT_RAW = 0x80000000

	// TCM_INT_ST: need_des
	// Position of TCM_PARITY_ERR_INT_ST field.
	HP_SYS_TCM_INT_ST_TCM_PARITY_ERR_INT_ST_Pos = 0x1f
	// Bit mask of TCM_PARITY_ERR_INT_ST field.
	HP_SYS_TCM_INT_ST_TCM_PARITY_ERR_INT_ST_Msk = 0x80000000
	// Bit TCM_PARITY_ERR_INT_ST.
	HP_SYS_TCM_INT_ST_TCM_PARITY_ERR_INT_ST = 0x80000000

	// TCM_INT_ENA: need_des
	// Position of TCM_PARITY_ERR_INT_ENA field.
	HP_SYS_TCM_INT_ENA_TCM_PARITY_ERR_INT_ENA_Pos = 0x1f
	// Bit mask of TCM_PARITY_ERR_INT_ENA field.
	HP_SYS_TCM_INT_ENA_TCM_PARITY_ERR_INT_ENA_Msk = 0x80000000
	// Bit TCM_PARITY_ERR_INT_ENA.
	HP_SYS_TCM_INT_ENA_TCM_PARITY_ERR_INT_ENA = 0x80000000

	// TCM_INT_CLR: need_des
	// Position of TCM_PARITY_ERR_INT_CLR field.
	HP_SYS_TCM_INT_CLR_TCM_PARITY_ERR_INT_CLR_Pos = 0x1f
	// Bit mask of TCM_PARITY_ERR_INT_CLR field.
	HP_SYS_TCM_INT_CLR_TCM_PARITY_ERR_INT_CLR_Msk = 0x80000000
	// Bit TCM_PARITY_ERR_INT_CLR.
	HP_SYS_TCM_INT_CLR_TCM_PARITY_ERR_INT_CLR = 0x80000000

	// TCM_PARITY_INT_RECORD: need_des
	// Position of TCM_PARITY_ERR_INT_ADDR field.
	HP_SYS_TCM_PARITY_INT_RECORD_TCM_PARITY_ERR_INT_ADDR_Pos = 0x0
	// Bit mask of TCM_PARITY_ERR_INT_ADDR field.
	HP_SYS_TCM_PARITY_INT_RECORD_TCM_PARITY_ERR_INT_ADDR_Msk = 0x1fff

	// L1_CACHE_PWR_CTRL: NA
	// Position of REG_L1_CACHE_MEM_FO field.
	HP_SYS_L1_CACHE_PWR_CTRL_REG_L1_CACHE_MEM_FO_Pos = 0x0
	// Bit mask of REG_L1_CACHE_MEM_FO field.
	HP_SYS_L1_CACHE_PWR_CTRL_REG_L1_CACHE_MEM_FO_Msk = 0x3f

	// L2_CACHE_PWR_CTRL: NA
	// Position of REG_L2_CACHE_MEM_FO field.
	HP_SYS_L2_CACHE_PWR_CTRL_REG_L2_CACHE_MEM_FO_Pos = 0x0
	// Bit mask of REG_L2_CACHE_MEM_FO field.
	HP_SYS_L2_CACHE_PWR_CTRL_REG_L2_CACHE_MEM_FO_Msk = 0x3

	// CPU_WAITI_CONF: CPU_WAITI configuration register
	// Position of CPU_WAIT_MODE_FORCE_ON field.
	HP_SYS_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON_Pos = 0x0
	// Bit mask of CPU_WAIT_MODE_FORCE_ON field.
	HP_SYS_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON_Msk = 0x1
	// Bit CPU_WAIT_MODE_FORCE_ON.
	HP_SYS_CPU_WAITI_CONF_CPU_WAIT_MODE_FORCE_ON = 0x1
	// Position of CPU_WAITI_DELAY_NUM field.
	HP_SYS_CPU_WAITI_CONF_CPU_WAITI_DELAY_NUM_Pos = 0x1
	// Bit mask of CPU_WAITI_DELAY_NUM field.
	HP_SYS_CPU_WAITI_CONF_CPU_WAITI_DELAY_NUM_Msk = 0x1e

	// CORE_DEBUG_RUNSTALL_CONF: Core Debug runstall configure register
	// Position of CORE_DEBUG_RUNSTALL_ENABLE field.
	HP_SYS_CORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE_Pos = 0x0
	// Bit mask of CORE_DEBUG_RUNSTALL_ENABLE field.
	HP_SYS_CORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE_Msk = 0x1
	// Bit CORE_DEBUG_RUNSTALL_ENABLE.
	HP_SYS_CORE_DEBUG_RUNSTALL_CONF_CORE_DEBUG_RUNSTALL_ENABLE = 0x1

	// CORE_AHB_TIMEOUT: need_des
	// Position of EN field.
	HP_SYS_CORE_AHB_TIMEOUT_EN_Pos = 0x0
	// Bit mask of EN field.
	HP_SYS_CORE_AHB_TIMEOUT_EN_Msk = 0x1
	// Bit EN.
	HP_SYS_CORE_AHB_TIMEOUT_EN = 0x1
	// Position of THRES field.
	HP_SYS_CORE_AHB_TIMEOUT_THRES_Pos = 0x1
	// Bit mask of THRES field.
	HP_SYS_CORE_AHB_TIMEOUT_THRES_Msk = 0x1fffe

	// CORE_IBUS_TIMEOUT: need_des
	// Position of EN field.
	HP_SYS_CORE_IBUS_TIMEOUT_EN_Pos = 0x0
	// Bit mask of EN field.
	HP_SYS_CORE_IBUS_TIMEOUT_EN_Msk = 0x1
	// Bit EN.
	HP_SYS_CORE_IBUS_TIMEOUT_EN = 0x1
	// Position of THRES field.
	HP_SYS_CORE_IBUS_TIMEOUT_THRES_Pos = 0x1
	// Bit mask of THRES field.
	HP_SYS_CORE_IBUS_TIMEOUT_THRES_Msk = 0x1fffe

	// CORE_DBUS_TIMEOUT: need_des
	// Position of EN field.
	HP_SYS_CORE_DBUS_TIMEOUT_EN_Pos = 0x0
	// Bit mask of EN field.
	HP_SYS_CORE_DBUS_TIMEOUT_EN_Msk = 0x1
	// Bit EN.
	HP_SYS_CORE_DBUS_TIMEOUT_EN = 0x1
	// Position of THRES field.
	HP_SYS_CORE_DBUS_TIMEOUT_THRES_Pos = 0x1
	// Bit mask of THRES field.
	HP_SYS_CORE_DBUS_TIMEOUT_THRES_Msk = 0x1fffe

	// ICM_CPU_H2X_CFG: need_des
	// Position of CPU_ICM_H2X_POST_WR_EN field.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_POST_WR_EN_Pos = 0x0
	// Bit mask of CPU_ICM_H2X_POST_WR_EN field.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_POST_WR_EN_Msk = 0x1
	// Bit CPU_ICM_H2X_POST_WR_EN.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_POST_WR_EN = 0x1
	// Position of CPU_ICM_H2X_CUT_THROUGH_EN field.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_CUT_THROUGH_EN_Pos = 0x1
	// Bit mask of CPU_ICM_H2X_CUT_THROUGH_EN field.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_CUT_THROUGH_EN_Msk = 0x2
	// Bit CPU_ICM_H2X_CUT_THROUGH_EN.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_CUT_THROUGH_EN = 0x2
	// Position of CPU_ICM_H2X_BRIDGE_BUSY field.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_BRIDGE_BUSY_Pos = 0x2
	// Bit mask of CPU_ICM_H2X_BRIDGE_BUSY field.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_BRIDGE_BUSY_Msk = 0x4
	// Bit CPU_ICM_H2X_BRIDGE_BUSY.
	HP_SYS_ICM_CPU_H2X_CFG_CPU_ICM_H2X_BRIDGE_BUSY = 0x4

	// PERI1_APB_POSTW_EN: NA
	// Position of PERI1_APB_POSTW_EN field.
	HP_SYS_PERI1_APB_POSTW_EN_PERI1_APB_POSTW_EN_Pos = 0x0
	// Bit mask of PERI1_APB_POSTW_EN field.
	HP_SYS_PERI1_APB_POSTW_EN_PERI1_APB_POSTW_EN_Msk = 0x1
	// Bit PERI1_APB_POSTW_EN.
	HP_SYS_PERI1_APB_POSTW_EN_PERI1_APB_POSTW_EN = 0x1

	// BITSCRAMBLER_PERI_SEL: Bitscrambler Peri Sel
	// Position of BITSCRAMBLER_PERI_RX_SEL field.
	HP_SYS_BITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_RX_SEL_Pos = 0x0
	// Bit mask of BITSCRAMBLER_PERI_RX_SEL field.
	HP_SYS_BITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_RX_SEL_Msk = 0xf
	// Position of BITSCRAMBLER_PERI_TX_SEL field.
	HP_SYS_BITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_TX_SEL_Pos = 0x4
	// Bit mask of BITSCRAMBLER_PERI_TX_SEL field.
	HP_SYS_BITSCRAMBLER_PERI_SEL_BITSCRAMBLER_PERI_TX_SEL_Msk = 0xf0

	// APB_SYNC_POSTW_EN: N/A
	// Position of GMAC_APB_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_GMAC_APB_POSTW_EN_Pos = 0x0
	// Bit mask of GMAC_APB_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_GMAC_APB_POSTW_EN_Msk = 0x1
	// Bit GMAC_APB_POSTW_EN.
	HP_SYS_APB_SYNC_POSTW_EN_GMAC_APB_POSTW_EN = 0x1
	// Position of DSI_HOST_APB_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_DSI_HOST_APB_POSTW_EN_Pos = 0x1
	// Bit mask of DSI_HOST_APB_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_DSI_HOST_APB_POSTW_EN_Msk = 0x2
	// Bit DSI_HOST_APB_POSTW_EN.
	HP_SYS_APB_SYNC_POSTW_EN_DSI_HOST_APB_POSTW_EN = 0x2
	// Position of CSI_HOST_APB_SYNC_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_CSI_HOST_APB_SYNC_POSTW_EN_Pos = 0x2
	// Bit mask of CSI_HOST_APB_SYNC_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_CSI_HOST_APB_SYNC_POSTW_EN_Msk = 0x4
	// Bit CSI_HOST_APB_SYNC_POSTW_EN.
	HP_SYS_APB_SYNC_POSTW_EN_CSI_HOST_APB_SYNC_POSTW_EN = 0x4
	// Position of CSI_HOST_APB_ASYNC_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_CSI_HOST_APB_ASYNC_POSTW_EN_Pos = 0x3
	// Bit mask of CSI_HOST_APB_ASYNC_POSTW_EN field.
	HP_SYS_APB_SYNC_POSTW_EN_CSI_HOST_APB_ASYNC_POSTW_EN_Msk = 0x8
	// Bit CSI_HOST_APB_ASYNC_POSTW_EN.
	HP_SYS_APB_SYNC_POSTW_EN_CSI_HOST_APB_ASYNC_POSTW_EN = 0x8

	// GDMA_CTRL: N/A
	// Position of DEBUG_CH_NUM field.
	HP_SYS_GDMA_CTRL_DEBUG_CH_NUM_Pos = 0x0
	// Bit mask of DEBUG_CH_NUM field.
	HP_SYS_GDMA_CTRL_DEBUG_CH_NUM_Msk = 0x3

	// GMAC_CTRL0: N/A
	// Position of PTP_PPS field.
	HP_SYS_GMAC_CTRL0_PTP_PPS_Pos = 0x0
	// Bit mask of PTP_PPS field.
	HP_SYS_GMAC_CTRL0_PTP_PPS_Msk = 0x1
	// Bit PTP_PPS.
	HP_SYS_GMAC_CTRL0_PTP_PPS = 0x1
	// Position of SBD_FLOWCTRL field.
	HP_SYS_GMAC_CTRL0_SBD_FLOWCTRL_Pos = 0x1
	// Bit mask of SBD_FLOWCTRL field.
	HP_SYS_GMAC_CTRL0_SBD_FLOWCTRL_Msk = 0x2
	// Bit SBD_FLOWCTRL.
	HP_SYS_GMAC_CTRL0_SBD_FLOWCTRL = 0x2
	// Position of PHY_INTF_SEL field.
	HP_SYS_GMAC_CTRL0_PHY_INTF_SEL_Pos = 0x2
	// Bit mask of PHY_INTF_SEL field.
	HP_SYS_GMAC_CTRL0_PHY_INTF_SEL_Msk = 0x1c
	// Position of GMAC_MEM_CLK_FORCE_ON field.
	HP_SYS_GMAC_CTRL0_GMAC_MEM_CLK_FORCE_ON_Pos = 0x5
	// Bit mask of GMAC_MEM_CLK_FORCE_ON field.
	HP_SYS_GMAC_CTRL0_GMAC_MEM_CLK_FORCE_ON_Msk = 0x20
	// Bit GMAC_MEM_CLK_FORCE_ON.
	HP_SYS_GMAC_CTRL0_GMAC_MEM_CLK_FORCE_ON = 0x20
	// Position of GMAC_RST_CLK_TX_N field.
	HP_SYS_GMAC_CTRL0_GMAC_RST_CLK_TX_N_Pos = 0x6
	// Bit mask of GMAC_RST_CLK_TX_N field.
	HP_SYS_GMAC_CTRL0_GMAC_RST_CLK_TX_N_Msk = 0x40
	// Bit GMAC_RST_CLK_TX_N.
	HP_SYS_GMAC_CTRL0_GMAC_RST_CLK_TX_N = 0x40
	// Position of GMAC_RST_CLK_RX_N field.
	HP_SYS_GMAC_CTRL0_GMAC_RST_CLK_RX_N_Pos = 0x7
	// Bit mask of GMAC_RST_CLK_RX_N field.
	HP_SYS_GMAC_CTRL0_GMAC_RST_CLK_RX_N_Msk = 0x80
	// Bit GMAC_RST_CLK_RX_N.
	HP_SYS_GMAC_CTRL0_GMAC_RST_CLK_RX_N = 0x80

	// GMAC_CTRL1: N/A
	// Position of PTP_TIMESTAMP_L field.
	HP_SYS_GMAC_CTRL1_PTP_TIMESTAMP_L_Pos = 0x0
	// Bit mask of PTP_TIMESTAMP_L field.
	HP_SYS_GMAC_CTRL1_PTP_TIMESTAMP_L_Msk = 0xffffffff

	// GMAC_CTRL2: N/A
	// Position of PTP_TIMESTAMP_H field.
	HP_SYS_GMAC_CTRL2_PTP_TIMESTAMP_H_Pos = 0x0
	// Bit mask of PTP_TIMESTAMP_H field.
	HP_SYS_GMAC_CTRL2_PTP_TIMESTAMP_H_Msk = 0xffffffff

	// VPU_CTRL: N/A
	// Position of PPA_LSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_PPA_LSLP_MEM_PD_Pos = 0x0
	// Bit mask of PPA_LSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_PPA_LSLP_MEM_PD_Msk = 0x1
	// Bit PPA_LSLP_MEM_PD.
	HP_SYS_VPU_CTRL_PPA_LSLP_MEM_PD = 0x1
	// Position of JPEG_SDSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_JPEG_SDSLP_MEM_PD_Pos = 0x1
	// Bit mask of JPEG_SDSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_JPEG_SDSLP_MEM_PD_Msk = 0x2
	// Bit JPEG_SDSLP_MEM_PD.
	HP_SYS_VPU_CTRL_JPEG_SDSLP_MEM_PD = 0x2
	// Position of JPEG_LSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_JPEG_LSLP_MEM_PD_Pos = 0x2
	// Bit mask of JPEG_LSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_JPEG_LSLP_MEM_PD_Msk = 0x4
	// Bit JPEG_LSLP_MEM_PD.
	HP_SYS_VPU_CTRL_JPEG_LSLP_MEM_PD = 0x4
	// Position of JPEG_DSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_JPEG_DSLP_MEM_PD_Pos = 0x3
	// Bit mask of JPEG_DSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_JPEG_DSLP_MEM_PD_Msk = 0x8
	// Bit JPEG_DSLP_MEM_PD.
	HP_SYS_VPU_CTRL_JPEG_DSLP_MEM_PD = 0x8
	// Position of DMA2D_LSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_DMA2D_LSLP_MEM_PD_Pos = 0x4
	// Bit mask of DMA2D_LSLP_MEM_PD field.
	HP_SYS_VPU_CTRL_DMA2D_LSLP_MEM_PD_Msk = 0x10
	// Bit DMA2D_LSLP_MEM_PD.
	HP_SYS_VPU_CTRL_DMA2D_LSLP_MEM_PD = 0x10

	// USBOTG20_CTRL: N/A
	// Position of OTG_PHY_TEST_DONE field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_TEST_DONE_Pos = 0x0
	// Bit mask of OTG_PHY_TEST_DONE field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_TEST_DONE_Msk = 0x1
	// Bit OTG_PHY_TEST_DONE.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_TEST_DONE = 0x1
	// Position of USB_MEM_AUX_CTRL field.
	HP_SYS_USBOTG20_CTRL_USB_MEM_AUX_CTRL_Pos = 0x1
	// Bit mask of USB_MEM_AUX_CTRL field.
	HP_SYS_USBOTG20_CTRL_USB_MEM_AUX_CTRL_Msk = 0x7ffe
	// Position of PHY_SUSPENDM field.
	HP_SYS_USBOTG20_CTRL_PHY_SUSPENDM_Pos = 0xf
	// Bit mask of PHY_SUSPENDM field.
	HP_SYS_USBOTG20_CTRL_PHY_SUSPENDM_Msk = 0x8000
	// Bit PHY_SUSPENDM.
	HP_SYS_USBOTG20_CTRL_PHY_SUSPENDM = 0x8000
	// Position of PHY_SUSPEND_FORCE_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_SUSPEND_FORCE_EN_Pos = 0x10
	// Bit mask of PHY_SUSPEND_FORCE_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_SUSPEND_FORCE_EN_Msk = 0x10000
	// Bit PHY_SUSPEND_FORCE_EN.
	HP_SYS_USBOTG20_CTRL_PHY_SUSPEND_FORCE_EN = 0x10000
	// Position of PHY_RSTN field.
	HP_SYS_USBOTG20_CTRL_PHY_RSTN_Pos = 0x11
	// Bit mask of PHY_RSTN field.
	HP_SYS_USBOTG20_CTRL_PHY_RSTN_Msk = 0x20000
	// Bit PHY_RSTN.
	HP_SYS_USBOTG20_CTRL_PHY_RSTN = 0x20000
	// Position of PHY_RESET_FORCE_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_RESET_FORCE_EN_Pos = 0x12
	// Bit mask of PHY_RESET_FORCE_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_RESET_FORCE_EN_Msk = 0x40000
	// Bit PHY_RESET_FORCE_EN.
	HP_SYS_USBOTG20_CTRL_PHY_RESET_FORCE_EN = 0x40000
	// Position of PHY_PLL_FORCE_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_PLL_FORCE_EN_Pos = 0x13
	// Bit mask of PHY_PLL_FORCE_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_PLL_FORCE_EN_Msk = 0x80000
	// Bit PHY_PLL_FORCE_EN.
	HP_SYS_USBOTG20_CTRL_PHY_PLL_FORCE_EN = 0x80000
	// Position of PHY_PLL_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_PLL_EN_Pos = 0x14
	// Bit mask of PHY_PLL_EN field.
	HP_SYS_USBOTG20_CTRL_PHY_PLL_EN_Msk = 0x100000
	// Bit PHY_PLL_EN.
	HP_SYS_USBOTG20_CTRL_PHY_PLL_EN = 0x100000
	// Position of OTG_SUSPENDM field.
	HP_SYS_USBOTG20_CTRL_OTG_SUSPENDM_Pos = 0x15
	// Bit mask of OTG_SUSPENDM field.
	HP_SYS_USBOTG20_CTRL_OTG_SUSPENDM_Msk = 0x200000
	// Bit OTG_SUSPENDM.
	HP_SYS_USBOTG20_CTRL_OTG_SUSPENDM = 0x200000
	// Position of OTG_PHY_TXBITSTUFF_EN field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_TXBITSTUFF_EN_Pos = 0x16
	// Bit mask of OTG_PHY_TXBITSTUFF_EN field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_TXBITSTUFF_EN_Msk = 0x400000
	// Bit OTG_PHY_TXBITSTUFF_EN.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_TXBITSTUFF_EN = 0x400000
	// Position of OTG_PHY_REFCLK_MODE field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_REFCLK_MODE_Pos = 0x17
	// Bit mask of OTG_PHY_REFCLK_MODE field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_REFCLK_MODE_Msk = 0x800000
	// Bit OTG_PHY_REFCLK_MODE.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_REFCLK_MODE = 0x800000
	// Position of OTG_PHY_BISTEN field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_BISTEN_Pos = 0x18
	// Bit mask of OTG_PHY_BISTEN field.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_BISTEN_Msk = 0x1000000
	// Bit OTG_PHY_BISTEN.
	HP_SYS_USBOTG20_CTRL_OTG_PHY_BISTEN = 0x1000000

	// TCM_ERR_RESP_CTRL: need_des
	// Position of TCM_ERR_RESP_EN field.
	HP_SYS_TCM_ERR_RESP_CTRL_TCM_ERR_RESP_EN_Pos = 0x0
	// Bit mask of TCM_ERR_RESP_EN field.
	HP_SYS_TCM_ERR_RESP_CTRL_TCM_ERR_RESP_EN_Msk = 0x1
	// Bit TCM_ERR_RESP_EN.
	HP_SYS_TCM_ERR_RESP_CTRL_TCM_ERR_RESP_EN = 0x1

	// L2_MEM_REFRESH: NA
	// Position of REG_L2_MEM_UNIT0_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFERSH_EN_Pos = 0x0
	// Bit mask of REG_L2_MEM_UNIT0_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFERSH_EN_Msk = 0x1
	// Bit REG_L2_MEM_UNIT0_REFERSH_EN.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFERSH_EN = 0x1
	// Position of REG_L2_MEM_UNIT1_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFERSH_EN_Pos = 0x1
	// Bit mask of REG_L2_MEM_UNIT1_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFERSH_EN_Msk = 0x2
	// Bit REG_L2_MEM_UNIT1_REFERSH_EN.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFERSH_EN = 0x2
	// Position of REG_L2_MEM_UNIT2_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFERSH_EN_Pos = 0x2
	// Bit mask of REG_L2_MEM_UNIT2_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFERSH_EN_Msk = 0x4
	// Bit REG_L2_MEM_UNIT2_REFERSH_EN.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFERSH_EN = 0x4
	// Position of REG_L2_MEM_UNIT3_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFERSH_EN_Pos = 0x3
	// Bit mask of REG_L2_MEM_UNIT3_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFERSH_EN_Msk = 0x8
	// Bit REG_L2_MEM_UNIT3_REFERSH_EN.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFERSH_EN = 0x8
	// Position of REG_L2_MEM_UNIT4_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFERSH_EN_Pos = 0x4
	// Bit mask of REG_L2_MEM_UNIT4_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFERSH_EN_Msk = 0x10
	// Bit REG_L2_MEM_UNIT4_REFERSH_EN.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFERSH_EN = 0x10
	// Position of REG_L2_MEM_UNIT5_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFERSH_EN_Pos = 0x5
	// Bit mask of REG_L2_MEM_UNIT5_REFERSH_EN field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFERSH_EN_Msk = 0x20
	// Bit REG_L2_MEM_UNIT5_REFERSH_EN.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFERSH_EN = 0x20
	// Position of REG_L2_MEM_REFERSH_CNT_RESET field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_REFERSH_CNT_RESET_Pos = 0x6
	// Bit mask of REG_L2_MEM_REFERSH_CNT_RESET field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_REFERSH_CNT_RESET_Msk = 0x40
	// Bit REG_L2_MEM_REFERSH_CNT_RESET.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_REFERSH_CNT_RESET = 0x40
	// Position of REG_L2_MEM_UNIT0_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFRESH_DONE_Pos = 0x7
	// Bit mask of REG_L2_MEM_UNIT0_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFRESH_DONE_Msk = 0x80
	// Bit REG_L2_MEM_UNIT0_REFRESH_DONE.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT0_REFRESH_DONE = 0x80
	// Position of REG_L2_MEM_UNIT1_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFRESH_DONE_Pos = 0x8
	// Bit mask of REG_L2_MEM_UNIT1_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFRESH_DONE_Msk = 0x100
	// Bit REG_L2_MEM_UNIT1_REFRESH_DONE.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT1_REFRESH_DONE = 0x100
	// Position of REG_L2_MEM_UNIT2_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFRESH_DONE_Pos = 0x9
	// Bit mask of REG_L2_MEM_UNIT2_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFRESH_DONE_Msk = 0x200
	// Bit REG_L2_MEM_UNIT2_REFRESH_DONE.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT2_REFRESH_DONE = 0x200
	// Position of REG_L2_MEM_UNIT3_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFRESH_DONE_Pos = 0xa
	// Bit mask of REG_L2_MEM_UNIT3_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFRESH_DONE_Msk = 0x400
	// Bit REG_L2_MEM_UNIT3_REFRESH_DONE.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT3_REFRESH_DONE = 0x400
	// Position of REG_L2_MEM_UNIT4_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFRESH_DONE_Pos = 0xb
	// Bit mask of REG_L2_MEM_UNIT4_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFRESH_DONE_Msk = 0x800
	// Bit REG_L2_MEM_UNIT4_REFRESH_DONE.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT4_REFRESH_DONE = 0x800
	// Position of REG_L2_MEM_UNIT5_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFRESH_DONE_Pos = 0xc
	// Bit mask of REG_L2_MEM_UNIT5_REFRESH_DONE field.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFRESH_DONE_Msk = 0x1000
	// Bit REG_L2_MEM_UNIT5_REFRESH_DONE.
	HP_SYS_L2_MEM_REFRESH_REG_L2_MEM_UNIT5_REFRESH_DONE = 0x1000

	// TCM_INIT: NA
	// Position of REG_TCM_INIT_EN field.
	HP_SYS_TCM_INIT_REG_TCM_INIT_EN_Pos = 0x0
	// Bit mask of REG_TCM_INIT_EN field.
	HP_SYS_TCM_INIT_REG_TCM_INIT_EN_Msk = 0x1
	// Bit REG_TCM_INIT_EN.
	HP_SYS_TCM_INIT_REG_TCM_INIT_EN = 0x1
	// Position of REG_TCM_INIT_CNT_RESET field.
	HP_SYS_TCM_INIT_REG_TCM_INIT_CNT_RESET_Pos = 0x1
	// Bit mask of REG_TCM_INIT_CNT_RESET field.
	HP_SYS_TCM_INIT_REG_TCM_INIT_CNT_RESET_Msk = 0x2
	// Bit REG_TCM_INIT_CNT_RESET.
	HP_SYS_TCM_INIT_REG_TCM_INIT_CNT_RESET = 0x2
	// Position of REG_TCM_INIT_DONE field.
	HP_SYS_TCM_INIT_REG_TCM_INIT_DONE_Pos = 0x2
	// Bit mask of REG_TCM_INIT_DONE field.
	HP_SYS_TCM_INIT_REG_TCM_INIT_DONE_Msk = 0x4
	// Bit REG_TCM_INIT_DONE.
	HP_SYS_TCM_INIT_REG_TCM_INIT_DONE = 0x4

	// TCM_PARITY_CHECK_CTRL: need_des
	// Position of TCM_PARITY_CHECK_EN field.
	HP_SYS_TCM_PARITY_CHECK_CTRL_TCM_PARITY_CHECK_EN_Pos = 0x0
	// Bit mask of TCM_PARITY_CHECK_EN field.
	HP_SYS_TCM_PARITY_CHECK_CTRL_TCM_PARITY_CHECK_EN_Msk = 0x1
	// Bit TCM_PARITY_CHECK_EN.
	HP_SYS_TCM_PARITY_CHECK_CTRL_TCM_PARITY_CHECK_EN = 0x1

	// DESIGN_FOR_VERIFICATION0: need_des
	// Position of DFV0 field.
	HP_SYS_DESIGN_FOR_VERIFICATION0_DFV0_Pos = 0x0
	// Bit mask of DFV0 field.
	HP_SYS_DESIGN_FOR_VERIFICATION0_DFV0_Msk = 0xffffffff

	// DESIGN_FOR_VERIFICATION1: need_des
	// Position of DFV1 field.
	HP_SYS_DESIGN_FOR_VERIFICATION1_DFV1_Pos = 0x0
	// Bit mask of DFV1 field.
	HP_SYS_DESIGN_FOR_VERIFICATION1_DFV1_Msk = 0xffffffff

	// PSRAM_FLASH_ADDR_INTERCHANGE: need_des
	// Position of CPU field.
	HP_SYS_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_Pos = 0x0
	// Bit mask of CPU field.
	HP_SYS_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_Msk = 0x1
	// Bit CPU.
	HP_SYS_PSRAM_FLASH_ADDR_INTERCHANGE_CPU = 0x1
	// Position of DMA field.
	HP_SYS_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_Pos = 0x1
	// Bit mask of DMA field.
	HP_SYS_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_Msk = 0x2
	// Bit DMA.
	HP_SYS_PSRAM_FLASH_ADDR_INTERCHANGE_DMA = 0x2

	// AHB2AXI_BRESP_ERR_INT_RAW: NA
	// Position of CPU_ICM_H2X_BRESP_ERR_INT_RAW field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_RAW_CPU_ICM_H2X_BRESP_ERR_INT_RAW_Pos = 0x0
	// Bit mask of CPU_ICM_H2X_BRESP_ERR_INT_RAW field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_RAW_CPU_ICM_H2X_BRESP_ERR_INT_RAW_Msk = 0x1
	// Bit CPU_ICM_H2X_BRESP_ERR_INT_RAW.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_RAW_CPU_ICM_H2X_BRESP_ERR_INT_RAW = 0x1

	// AHB2AXI_BRESP_ERR_INT_ST: need_des
	// Position of CPU_ICM_H2X_BRESP_ERR_INT_ST field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_ST_CPU_ICM_H2X_BRESP_ERR_INT_ST_Pos = 0x1f
	// Bit mask of CPU_ICM_H2X_BRESP_ERR_INT_ST field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_ST_CPU_ICM_H2X_BRESP_ERR_INT_ST_Msk = 0x80000000
	// Bit CPU_ICM_H2X_BRESP_ERR_INT_ST.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_ST_CPU_ICM_H2X_BRESP_ERR_INT_ST = 0x80000000

	// AHB2AXI_BRESP_ERR_INT_ENA: need_des
	// Position of CPU_ICM_H2X_BRESP_ERR_INT_ENA field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_ENA_CPU_ICM_H2X_BRESP_ERR_INT_ENA_Pos = 0x1f
	// Bit mask of CPU_ICM_H2X_BRESP_ERR_INT_ENA field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_ENA_CPU_ICM_H2X_BRESP_ERR_INT_ENA_Msk = 0x80000000
	// Bit CPU_ICM_H2X_BRESP_ERR_INT_ENA.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_ENA_CPU_ICM_H2X_BRESP_ERR_INT_ENA = 0x80000000

	// AHB2AXI_BRESP_ERR_INT_CLR: need_des
	// Position of CPU_ICM_H2X_BRESP_ERR_INT_CLR field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_CLR_CPU_ICM_H2X_BRESP_ERR_INT_CLR_Pos = 0x1f
	// Bit mask of CPU_ICM_H2X_BRESP_ERR_INT_CLR field.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_CLR_CPU_ICM_H2X_BRESP_ERR_INT_CLR_Msk = 0x80000000
	// Bit CPU_ICM_H2X_BRESP_ERR_INT_CLR.
	HP_SYS_AHB2AXI_BRESP_ERR_INT_CLR_CPU_ICM_H2X_BRESP_ERR_INT_CLR = 0x80000000

	// L2_MEM_ERR_RESP_CTRL: need_des
	// Position of L2_MEM_ERR_RESP_EN field.
	HP_SYS_L2_MEM_ERR_RESP_CTRL_L2_MEM_ERR_RESP_EN_Pos = 0x0
	// Bit mask of L2_MEM_ERR_RESP_EN field.
	HP_SYS_L2_MEM_ERR_RESP_CTRL_L2_MEM_ERR_RESP_EN_Msk = 0x1
	// Bit L2_MEM_ERR_RESP_EN.
	HP_SYS_L2_MEM_ERR_RESP_CTRL_L2_MEM_ERR_RESP_EN = 0x1

	// L2_MEM_AHB_BUFFER_CTRL: need_des
	// Position of L2_MEM_AHB_WRBUFFER_EN field.
	HP_SYS_L2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_WRBUFFER_EN_Pos = 0x0
	// Bit mask of L2_MEM_AHB_WRBUFFER_EN field.
	HP_SYS_L2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_WRBUFFER_EN_Msk = 0x1
	// Bit L2_MEM_AHB_WRBUFFER_EN.
	HP_SYS_L2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_WRBUFFER_EN = 0x1
	// Position of L2_MEM_AHB_RDBUFFER_EN field.
	HP_SYS_L2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_RDBUFFER_EN_Pos = 0x1
	// Bit mask of L2_MEM_AHB_RDBUFFER_EN field.
	HP_SYS_L2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_RDBUFFER_EN_Msk = 0x2
	// Bit L2_MEM_AHB_RDBUFFER_EN.
	HP_SYS_L2_MEM_AHB_BUFFER_CTRL_L2_MEM_AHB_RDBUFFER_EN = 0x2

	// CORE_DMACTIVE_LPCORE: need_des
	// Position of CORE_DMACTIVE_LPCORE field.
	HP_SYS_CORE_DMACTIVE_LPCORE_CORE_DMACTIVE_LPCORE_Pos = 0x0
	// Bit mask of CORE_DMACTIVE_LPCORE field.
	HP_SYS_CORE_DMACTIVE_LPCORE_CORE_DMACTIVE_LPCORE_Msk = 0x1
	// Bit CORE_DMACTIVE_LPCORE.
	HP_SYS_CORE_DMACTIVE_LPCORE_CORE_DMACTIVE_LPCORE = 0x1

	// CORE_ERR_RESP_DIS: need_des
	// Position of CORE_ERR_RESP_DIS field.
	HP_SYS_CORE_ERR_RESP_DIS_CORE_ERR_RESP_DIS_Pos = 0x0
	// Bit mask of CORE_ERR_RESP_DIS field.
	HP_SYS_CORE_ERR_RESP_DIS_CORE_ERR_RESP_DIS_Msk = 0x7

	// CORE_TIMEOUT_INT_RAW: Hp core bus timeout interrupt raw register
	// Position of CORE0_AHB_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_AHB_TIMEOUT_INT_RAW_Pos = 0x0
	// Bit mask of CORE0_AHB_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_AHB_TIMEOUT_INT_RAW_Msk = 0x1
	// Bit CORE0_AHB_TIMEOUT_INT_RAW.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_AHB_TIMEOUT_INT_RAW = 0x1
	// Position of CORE1_AHB_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_AHB_TIMEOUT_INT_RAW_Pos = 0x1
	// Bit mask of CORE1_AHB_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_AHB_TIMEOUT_INT_RAW_Msk = 0x2
	// Bit CORE1_AHB_TIMEOUT_INT_RAW.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_AHB_TIMEOUT_INT_RAW = 0x2
	// Position of CORE0_IBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_IBUS_TIMEOUT_INT_RAW_Pos = 0x2
	// Bit mask of CORE0_IBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_IBUS_TIMEOUT_INT_RAW_Msk = 0x4
	// Bit CORE0_IBUS_TIMEOUT_INT_RAW.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_IBUS_TIMEOUT_INT_RAW = 0x4
	// Position of CORE1_IBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_IBUS_TIMEOUT_INT_RAW_Pos = 0x3
	// Bit mask of CORE1_IBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_IBUS_TIMEOUT_INT_RAW_Msk = 0x8
	// Bit CORE1_IBUS_TIMEOUT_INT_RAW.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_IBUS_TIMEOUT_INT_RAW = 0x8
	// Position of CORE0_DBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_DBUS_TIMEOUT_INT_RAW_Pos = 0x4
	// Bit mask of CORE0_DBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_DBUS_TIMEOUT_INT_RAW_Msk = 0x10
	// Bit CORE0_DBUS_TIMEOUT_INT_RAW.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE0_DBUS_TIMEOUT_INT_RAW = 0x10
	// Position of CORE1_DBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_DBUS_TIMEOUT_INT_RAW_Pos = 0x5
	// Bit mask of CORE1_DBUS_TIMEOUT_INT_RAW field.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_DBUS_TIMEOUT_INT_RAW_Msk = 0x20
	// Bit CORE1_DBUS_TIMEOUT_INT_RAW.
	HP_SYS_CORE_TIMEOUT_INT_RAW_CORE1_DBUS_TIMEOUT_INT_RAW = 0x20

	// CORE_TIMEOUT_INT_ST: masked interrupt register
	// Position of CORE0_AHB_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_AHB_TIMEOUT_INT_ST_Pos = 0x0
	// Bit mask of CORE0_AHB_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_AHB_TIMEOUT_INT_ST_Msk = 0x1
	// Bit CORE0_AHB_TIMEOUT_INT_ST.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_AHB_TIMEOUT_INT_ST = 0x1
	// Position of CORE1_AHB_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_AHB_TIMEOUT_INT_ST_Pos = 0x1
	// Bit mask of CORE1_AHB_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_AHB_TIMEOUT_INT_ST_Msk = 0x2
	// Bit CORE1_AHB_TIMEOUT_INT_ST.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_AHB_TIMEOUT_INT_ST = 0x2
	// Position of CORE0_IBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_IBUS_TIMEOUT_INT_ST_Pos = 0x2
	// Bit mask of CORE0_IBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_IBUS_TIMEOUT_INT_ST_Msk = 0x4
	// Bit CORE0_IBUS_TIMEOUT_INT_ST.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_IBUS_TIMEOUT_INT_ST = 0x4
	// Position of CORE1_IBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_IBUS_TIMEOUT_INT_ST_Pos = 0x3
	// Bit mask of CORE1_IBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_IBUS_TIMEOUT_INT_ST_Msk = 0x8
	// Bit CORE1_IBUS_TIMEOUT_INT_ST.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_IBUS_TIMEOUT_INT_ST = 0x8
	// Position of CORE0_DBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_DBUS_TIMEOUT_INT_ST_Pos = 0x4
	// Bit mask of CORE0_DBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_DBUS_TIMEOUT_INT_ST_Msk = 0x10
	// Bit CORE0_DBUS_TIMEOUT_INT_ST.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE0_DBUS_TIMEOUT_INT_ST = 0x10
	// Position of CORE1_DBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_DBUS_TIMEOUT_INT_ST_Pos = 0x5
	// Bit mask of CORE1_DBUS_TIMEOUT_INT_ST field.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_DBUS_TIMEOUT_INT_ST_Msk = 0x20
	// Bit CORE1_DBUS_TIMEOUT_INT_ST.
	HP_SYS_CORE_TIMEOUT_INT_ST_CORE1_DBUS_TIMEOUT_INT_ST = 0x20

	// CORE_TIMEOUT_INT_ENA: masked interrupt register
	// Position of CORE0_AHB_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_AHB_TIMEOUT_INT_ENA_Pos = 0x0
	// Bit mask of CORE0_AHB_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_AHB_TIMEOUT_INT_ENA_Msk = 0x1
	// Bit CORE0_AHB_TIMEOUT_INT_ENA.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_AHB_TIMEOUT_INT_ENA = 0x1
	// Position of CORE1_AHB_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_AHB_TIMEOUT_INT_ENA_Pos = 0x1
	// Bit mask of CORE1_AHB_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_AHB_TIMEOUT_INT_ENA_Msk = 0x2
	// Bit CORE1_AHB_TIMEOUT_INT_ENA.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_AHB_TIMEOUT_INT_ENA = 0x2
	// Position of CORE0_IBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_IBUS_TIMEOUT_INT_ENA_Pos = 0x2
	// Bit mask of CORE0_IBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_IBUS_TIMEOUT_INT_ENA_Msk = 0x4
	// Bit CORE0_IBUS_TIMEOUT_INT_ENA.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_IBUS_TIMEOUT_INT_ENA = 0x4
	// Position of CORE1_IBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_IBUS_TIMEOUT_INT_ENA_Pos = 0x3
	// Bit mask of CORE1_IBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_IBUS_TIMEOUT_INT_ENA_Msk = 0x8
	// Bit CORE1_IBUS_TIMEOUT_INT_ENA.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_IBUS_TIMEOUT_INT_ENA = 0x8
	// Position of CORE0_DBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_DBUS_TIMEOUT_INT_ENA_Pos = 0x4
	// Bit mask of CORE0_DBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_DBUS_TIMEOUT_INT_ENA_Msk = 0x10
	// Bit CORE0_DBUS_TIMEOUT_INT_ENA.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE0_DBUS_TIMEOUT_INT_ENA = 0x10
	// Position of CORE1_DBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_DBUS_TIMEOUT_INT_ENA_Pos = 0x5
	// Bit mask of CORE1_DBUS_TIMEOUT_INT_ENA field.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_DBUS_TIMEOUT_INT_ENA_Msk = 0x20
	// Bit CORE1_DBUS_TIMEOUT_INT_ENA.
	HP_SYS_CORE_TIMEOUT_INT_ENA_CORE1_DBUS_TIMEOUT_INT_ENA = 0x20

	// CORE_TIMEOUT_INT_CLR: interrupt clear register
	// Position of CORE0_AHB_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_AHB_TIMEOUT_INT_CLR_Pos = 0x0
	// Bit mask of CORE0_AHB_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_AHB_TIMEOUT_INT_CLR_Msk = 0x1
	// Bit CORE0_AHB_TIMEOUT_INT_CLR.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_AHB_TIMEOUT_INT_CLR = 0x1
	// Position of CORE1_AHB_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_AHB_TIMEOUT_INT_CLR_Pos = 0x1
	// Bit mask of CORE1_AHB_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_AHB_TIMEOUT_INT_CLR_Msk = 0x2
	// Bit CORE1_AHB_TIMEOUT_INT_CLR.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_AHB_TIMEOUT_INT_CLR = 0x2
	// Position of CORE0_IBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_IBUS_TIMEOUT_INT_CLR_Pos = 0x2
	// Bit mask of CORE0_IBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_IBUS_TIMEOUT_INT_CLR_Msk = 0x4
	// Bit CORE0_IBUS_TIMEOUT_INT_CLR.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_IBUS_TIMEOUT_INT_CLR = 0x4
	// Position of CORE1_IBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_IBUS_TIMEOUT_INT_CLR_Pos = 0x3
	// Bit mask of CORE1_IBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_IBUS_TIMEOUT_INT_CLR_Msk = 0x8
	// Bit CORE1_IBUS_TIMEOUT_INT_CLR.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_IBUS_TIMEOUT_INT_CLR = 0x8
	// Position of CORE0_DBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_DBUS_TIMEOUT_INT_CLR_Pos = 0x4
	// Bit mask of CORE0_DBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_DBUS_TIMEOUT_INT_CLR_Msk = 0x10
	// Bit CORE0_DBUS_TIMEOUT_INT_CLR.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE0_DBUS_TIMEOUT_INT_CLR = 0x10
	// Position of CORE1_DBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_DBUS_TIMEOUT_INT_CLR_Pos = 0x5
	// Bit mask of CORE1_DBUS_TIMEOUT_INT_CLR field.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_DBUS_TIMEOUT_INT_CLR_Msk = 0x20
	// Bit CORE1_DBUS_TIMEOUT_INT_CLR.
	HP_SYS_CORE_TIMEOUT_INT_CLR_CORE1_DBUS_TIMEOUT_INT_CLR = 0x20

	// GPIO_O_HYS_CTRL0: NA
	// Position of REG_GPIO_0_HYS_LOW field.
	HP_SYS_GPIO_O_HYS_CTRL0_REG_GPIO_0_HYS_LOW_Pos = 0x0
	// Bit mask of REG_GPIO_0_HYS_LOW field.
	HP_SYS_GPIO_O_HYS_CTRL0_REG_GPIO_0_HYS_LOW_Msk = 0xffffffff

	// GPIO_O_HYS_CTRL1: NA
	// Position of REG_GPIO_0_HYS_HIGH field.
	HP_SYS_GPIO_O_HYS_CTRL1_REG_GPIO_0_HYS_HIGH_Pos = 0x0
	// Bit mask of REG_GPIO_0_HYS_HIGH field.
	HP_SYS_GPIO_O_HYS_CTRL1_REG_GPIO_0_HYS_HIGH_Msk = 0x1ff

	// RSA_PD_CTRL: rsa pd ctrl register
	// Position of RSA_MEM_FORCE_PD field.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Pos = 0x0
	// Bit mask of RSA_MEM_FORCE_PD field.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_FORCE_PD_Msk = 0x1
	// Bit RSA_MEM_FORCE_PD.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_FORCE_PD = 0x1
	// Position of RSA_MEM_FORCE_PU field.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Pos = 0x1
	// Bit mask of RSA_MEM_FORCE_PU field.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_FORCE_PU_Msk = 0x2
	// Bit RSA_MEM_FORCE_PU.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_FORCE_PU = 0x2
	// Position of RSA_MEM_PD field.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_PD_Pos = 0x2
	// Bit mask of RSA_MEM_PD field.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_PD_Msk = 0x4
	// Bit RSA_MEM_PD.
	HP_SYS_RSA_PD_CTRL_RSA_MEM_PD = 0x4

	// ECC_PD_CTRL: ecc pd ctrl register
	// Position of ECC_MEM_FORCE_PD field.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_FORCE_PD_Pos = 0x0
	// Bit mask of ECC_MEM_FORCE_PD field.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_FORCE_PD_Msk = 0x1
	// Bit ECC_MEM_FORCE_PD.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_FORCE_PD = 0x1
	// Position of ECC_MEM_FORCE_PU field.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_FORCE_PU_Pos = 0x1
	// Bit mask of ECC_MEM_FORCE_PU field.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_FORCE_PU_Msk = 0x2
	// Bit ECC_MEM_FORCE_PU.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_FORCE_PU = 0x2
	// Position of ECC_MEM_PD field.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_PD_Pos = 0x2
	// Bit mask of ECC_MEM_PD field.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_PD_Msk = 0x4
	// Bit ECC_MEM_PD.
	HP_SYS_ECC_PD_CTRL_ECC_MEM_PD = 0x4

	// RNG_CFG: rng cfg register
	// Position of RNG_SAMPLE_ENABLE field.
	HP_SYS_RNG_CFG_RNG_SAMPLE_ENABLE_Pos = 0x0
	// Bit mask of RNG_SAMPLE_ENABLE field.
	HP_SYS_RNG_CFG_RNG_SAMPLE_ENABLE_Msk = 0x1
	// Bit RNG_SAMPLE_ENABLE.
	HP_SYS_RNG_CFG_RNG_SAMPLE_ENABLE = 0x1
	// Position of RNG_CHAIN_CLK_DIV_NUM field.
	HP_SYS_RNG_CFG_RNG_CHAIN_CLK_DIV_NUM_Pos = 0x10
	// Bit mask of RNG_CHAIN_CLK_DIV_NUM field.
	HP_SYS_RNG_CFG_RNG_CHAIN_CLK_DIV_NUM_Msk = 0xff0000
	// Position of RNG_SAMPLE_CNT field.
	HP_SYS_RNG_CFG_RNG_SAMPLE_CNT_Pos = 0x18
	// Bit mask of RNG_SAMPLE_CNT field.
	HP_SYS_RNG_CFG_RNG_SAMPLE_CNT_Msk = 0xff000000

	// UART_PD_CTRL: ecc pd ctrl register
	// Position of UART_MEM_FORCE_PD field.
	HP_SYS_UART_PD_CTRL_UART_MEM_FORCE_PD_Pos = 0x0
	// Bit mask of UART_MEM_FORCE_PD field.
	HP_SYS_UART_PD_CTRL_UART_MEM_FORCE_PD_Msk = 0x1
	// Bit UART_MEM_FORCE_PD.
	HP_SYS_UART_PD_CTRL_UART_MEM_FORCE_PD = 0x1
	// Position of UART_MEM_FORCE_PU field.
	HP_SYS_UART_PD_CTRL_UART_MEM_FORCE_PU_Pos = 0x1
	// Bit mask of UART_MEM_FORCE_PU field.
	HP_SYS_UART_PD_CTRL_UART_MEM_FORCE_PU_Msk = 0x2
	// Bit UART_MEM_FORCE_PU.
	HP_SYS_UART_PD_CTRL_UART_MEM_FORCE_PU = 0x2

	// PERI_MEM_CLK_FORCE_ON: hp peri mem clk force on regpster
	// Position of RMT_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_RMT_MEM_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of RMT_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_RMT_MEM_CLK_FORCE_ON_Msk = 0x1
	// Bit RMT_MEM_CLK_FORCE_ON.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_RMT_MEM_CLK_FORCE_ON = 0x1
	// Position of BITSCRAMBLER_TX_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_Pos = 0x1
	// Bit mask of BITSCRAMBLER_TX_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_Msk = 0x2
	// Bit BITSCRAMBLER_TX_MEM_CLK_FORCE_ON.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON = 0x2
	// Position of BITSCRAMBLER_RX_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_Pos = 0x2
	// Bit mask of BITSCRAMBLER_RX_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_Msk = 0x4
	// Bit BITSCRAMBLER_RX_MEM_CLK_FORCE_ON.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON = 0x4
	// Position of GDMA_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_GDMA_MEM_CLK_FORCE_ON_Pos = 0x3
	// Bit mask of GDMA_MEM_CLK_FORCE_ON field.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_GDMA_MEM_CLK_FORCE_ON_Msk = 0x8
	// Bit GDMA_MEM_CLK_FORCE_ON.
	HP_SYS_PERI_MEM_CLK_FORCE_ON_GDMA_MEM_CLK_FORCE_ON = 0x8
)

// Constants for HP_SYS_CLKRST: HP_SYS_CLKRST Peripheral
const (
	// CLK_EN0: Reserved
	// Position of REG_CLK_EN field.
	HP_SYS_CLKRST_CLK_EN0_REG_CLK_EN_Pos = 0x0
	// Bit mask of REG_CLK_EN field.
	HP_SYS_CLKRST_CLK_EN0_REG_CLK_EN_Msk = 0x1
	// Bit REG_CLK_EN.
	HP_SYS_CLKRST_CLK_EN0_REG_CLK_EN = 0x1

	// ROOT_CLK_CTRL0: Reserved
	// Position of REG_CPUICM_DELAY_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPUICM_DELAY_NUM_Pos = 0x0
	// Bit mask of REG_CPUICM_DELAY_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPUICM_DELAY_NUM_Msk = 0xf
	// Position of REG_SOC_CLK_DIV_UPDATE field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_SOC_CLK_DIV_UPDATE_Pos = 0x4
	// Bit mask of REG_SOC_CLK_DIV_UPDATE field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_SOC_CLK_DIV_UPDATE_Msk = 0x10
	// Bit REG_SOC_CLK_DIV_UPDATE.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_SOC_CLK_DIV_UPDATE = 0x10
	// Position of REG_CPU_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUM_Pos = 0x5
	// Bit mask of REG_CPU_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUM_Msk = 0x1fe0
	// Position of REG_CPU_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUMERATOR_Pos = 0xd
	// Bit mask of REG_CPU_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPU_CLK_DIV_NUMERATOR_Msk = 0x1fe000
	// Position of REG_CPU_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPU_CLK_DIV_DENOMINATOR_Pos = 0x15
	// Bit mask of REG_CPU_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG_CPU_CLK_DIV_DENOMINATOR_Msk = 0x1fe00000

	// ROOT_CLK_CTRL1: Reserved
	// Position of REG_MEM_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_MEM_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_MEM_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_MEM_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_MEM_CLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_MEM_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_MEM_CLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_MEM_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_MEM_CLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_SYS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_SYS_CLK_DIV_NUM_Pos = 0x18
	// Bit mask of REG_SYS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG_SYS_CLK_DIV_NUM_Msk = 0xff000000

	// ROOT_CLK_CTRL2: Reserved
	// Position of REG_SYS_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_SYS_CLK_DIV_NUMERATOR_Pos = 0x0
	// Bit mask of REG_SYS_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_SYS_CLK_DIV_NUMERATOR_Msk = 0xff
	// Position of REG_SYS_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_SYS_CLK_DIV_DENOMINATOR_Pos = 0x8
	// Bit mask of REG_SYS_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_SYS_CLK_DIV_DENOMINATOR_Msk = 0xff00
	// Position of REG_APB_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUM_Pos = 0x10
	// Bit mask of REG_APB_CLK_DIV_NUM field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUM_Msk = 0xff0000
	// Position of REG_APB_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUMERATOR_Pos = 0x18
	// Bit mask of REG_APB_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG_APB_CLK_DIV_NUMERATOR_Msk = 0xff000000

	// ROOT_CLK_CTRL3: Reserved
	// Position of REG_APB_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL3_REG_APB_CLK_DIV_DENOMINATOR_Pos = 0x0
	// Bit mask of REG_APB_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_ROOT_CLK_CTRL3_REG_APB_CLK_DIV_DENOMINATOR_Msk = 0xff

	// SOC_CLK_CTRL0: Reserved
	// Position of REG_CORE0_CLIC_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE0_CLIC_CLK_EN_Pos = 0x0
	// Bit mask of REG_CORE0_CLIC_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE0_CLIC_CLK_EN_Msk = 0x1
	// Bit REG_CORE0_CLIC_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE0_CLIC_CLK_EN = 0x1
	// Position of REG_CORE1_CLIC_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE1_CLIC_CLK_EN_Pos = 0x1
	// Bit mask of REG_CORE1_CLIC_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE1_CLIC_CLK_EN_Msk = 0x2
	// Bit REG_CORE1_CLIC_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE1_CLIC_CLK_EN = 0x2
	// Position of REG_MISC_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_MISC_CPU_CLK_EN_Pos = 0x2
	// Bit mask of REG_MISC_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_MISC_CPU_CLK_EN_Msk = 0x4
	// Bit REG_MISC_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_MISC_CPU_CLK_EN = 0x4
	// Position of REG_CORE0_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE0_CPU_CLK_EN_Pos = 0x3
	// Bit mask of REG_CORE0_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE0_CPU_CLK_EN_Msk = 0x8
	// Bit REG_CORE0_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE0_CPU_CLK_EN = 0x8
	// Position of REG_CORE1_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE1_CPU_CLK_EN_Pos = 0x4
	// Bit mask of REG_CORE1_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE1_CPU_CLK_EN_Msk = 0x10
	// Bit REG_CORE1_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_CORE1_CPU_CLK_EN = 0x10
	// Position of REG_TCM_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TCM_CPU_CLK_EN_Pos = 0x5
	// Bit mask of REG_TCM_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TCM_CPU_CLK_EN_Msk = 0x20
	// Bit REG_TCM_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TCM_CPU_CLK_EN = 0x20
	// Position of REG_BUSMON_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_BUSMON_CPU_CLK_EN_Pos = 0x6
	// Bit mask of REG_BUSMON_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_BUSMON_CPU_CLK_EN_Msk = 0x40
	// Bit REG_BUSMON_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_BUSMON_CPU_CLK_EN = 0x40
	// Position of REG_L1CACHE_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_CPU_CLK_EN_Pos = 0x7
	// Bit mask of REG_L1CACHE_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_CPU_CLK_EN_Msk = 0x80
	// Bit REG_L1CACHE_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_CPU_CLK_EN = 0x80
	// Position of REG_L1CACHE_D_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_D_CPU_CLK_EN_Pos = 0x8
	// Bit mask of REG_L1CACHE_D_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_D_CPU_CLK_EN_Msk = 0x100
	// Bit REG_L1CACHE_D_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_D_CPU_CLK_EN = 0x100
	// Position of REG_L1CACHE_I0_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I0_CPU_CLK_EN_Pos = 0x9
	// Bit mask of REG_L1CACHE_I0_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I0_CPU_CLK_EN_Msk = 0x200
	// Bit REG_L1CACHE_I0_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I0_CPU_CLK_EN = 0x200
	// Position of REG_L1CACHE_I1_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I1_CPU_CLK_EN_Pos = 0xa
	// Bit mask of REG_L1CACHE_I1_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I1_CPU_CLK_EN_Msk = 0x400
	// Bit REG_L1CACHE_I1_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I1_CPU_CLK_EN = 0x400
	// Position of REG_TRACE_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TRACE_CPU_CLK_EN_Pos = 0xb
	// Bit mask of REG_TRACE_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TRACE_CPU_CLK_EN_Msk = 0x800
	// Bit REG_TRACE_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TRACE_CPU_CLK_EN = 0x800
	// Position of REG_ICM_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_CPU_CLK_EN_Pos = 0xc
	// Bit mask of REG_ICM_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_CPU_CLK_EN_Msk = 0x1000
	// Bit REG_ICM_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_CPU_CLK_EN = 0x1000
	// Position of REG_GDMA_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_GDMA_CPU_CLK_EN_Pos = 0xd
	// Bit mask of REG_GDMA_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_GDMA_CPU_CLK_EN_Msk = 0x2000
	// Bit REG_GDMA_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_GDMA_CPU_CLK_EN = 0x2000
	// Position of REG_VPU_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_VPU_CPU_CLK_EN_Pos = 0xe
	// Bit mask of REG_VPU_CPU_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_VPU_CPU_CLK_EN_Msk = 0x4000
	// Bit REG_VPU_CPU_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_VPU_CPU_CLK_EN = 0x4000
	// Position of REG_L1CACHE_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_MEM_CLK_EN_Pos = 0xf
	// Bit mask of REG_L1CACHE_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_MEM_CLK_EN_Msk = 0x8000
	// Bit REG_L1CACHE_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_MEM_CLK_EN = 0x8000
	// Position of REG_L1CACHE_D_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_D_MEM_CLK_EN_Pos = 0x10
	// Bit mask of REG_L1CACHE_D_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_D_MEM_CLK_EN_Msk = 0x10000
	// Bit REG_L1CACHE_D_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_D_MEM_CLK_EN = 0x10000
	// Position of REG_L1CACHE_I0_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I0_MEM_CLK_EN_Pos = 0x11
	// Bit mask of REG_L1CACHE_I0_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I0_MEM_CLK_EN_Msk = 0x20000
	// Bit REG_L1CACHE_I0_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I0_MEM_CLK_EN = 0x20000
	// Position of REG_L1CACHE_I1_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I1_MEM_CLK_EN_Pos = 0x12
	// Bit mask of REG_L1CACHE_I1_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I1_MEM_CLK_EN_Msk = 0x40000
	// Bit REG_L1CACHE_I1_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L1CACHE_I1_MEM_CLK_EN = 0x40000
	// Position of REG_L2CACHE_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2CACHE_MEM_CLK_EN_Pos = 0x13
	// Bit mask of REG_L2CACHE_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2CACHE_MEM_CLK_EN_Msk = 0x80000
	// Bit REG_L2CACHE_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2CACHE_MEM_CLK_EN = 0x80000
	// Position of REG_L2MEM_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEM_MEM_CLK_EN_Pos = 0x14
	// Bit mask of REG_L2MEM_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEM_MEM_CLK_EN_Msk = 0x100000
	// Bit REG_L2MEM_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEM_MEM_CLK_EN = 0x100000
	// Position of REG_L2MEMMON_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEMMON_MEM_CLK_EN_Pos = 0x15
	// Bit mask of REG_L2MEMMON_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEMMON_MEM_CLK_EN_Msk = 0x200000
	// Bit REG_L2MEMMON_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEMMON_MEM_CLK_EN = 0x200000
	// Position of REG_ICM_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_MEM_CLK_EN_Pos = 0x16
	// Bit mask of REG_ICM_MEM_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_MEM_CLK_EN_Msk = 0x400000
	// Bit REG_ICM_MEM_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_MEM_CLK_EN = 0x400000
	// Position of REG_MISC_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_MISC_SYS_CLK_EN_Pos = 0x17
	// Bit mask of REG_MISC_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_MISC_SYS_CLK_EN_Msk = 0x800000
	// Bit REG_MISC_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_MISC_SYS_CLK_EN = 0x800000
	// Position of REG_TRACE_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TRACE_SYS_CLK_EN_Pos = 0x18
	// Bit mask of REG_TRACE_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TRACE_SYS_CLK_EN_Msk = 0x1000000
	// Bit REG_TRACE_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TRACE_SYS_CLK_EN = 0x1000000
	// Position of REG_L2CACHE_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2CACHE_SYS_CLK_EN_Pos = 0x19
	// Bit mask of REG_L2CACHE_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2CACHE_SYS_CLK_EN_Msk = 0x2000000
	// Bit REG_L2CACHE_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2CACHE_SYS_CLK_EN = 0x2000000
	// Position of REG_L2MEM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEM_SYS_CLK_EN_Pos = 0x1a
	// Bit mask of REG_L2MEM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEM_SYS_CLK_EN_Msk = 0x4000000
	// Bit REG_L2MEM_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEM_SYS_CLK_EN = 0x4000000
	// Position of REG_L2MEMMON_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEMMON_SYS_CLK_EN_Pos = 0x1b
	// Bit mask of REG_L2MEMMON_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEMMON_SYS_CLK_EN_Msk = 0x8000000
	// Bit REG_L2MEMMON_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_L2MEMMON_SYS_CLK_EN = 0x8000000
	// Position of REG_TCMMON_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TCMMON_SYS_CLK_EN_Pos = 0x1c
	// Bit mask of REG_TCMMON_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TCMMON_SYS_CLK_EN_Msk = 0x10000000
	// Bit REG_TCMMON_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_TCMMON_SYS_CLK_EN = 0x10000000
	// Position of REG_ICM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_SYS_CLK_EN_Pos = 0x1d
	// Bit mask of REG_ICM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_SYS_CLK_EN_Msk = 0x20000000
	// Bit REG_ICM_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_ICM_SYS_CLK_EN = 0x20000000
	// Position of REG_FLASH_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_FLASH_SYS_CLK_EN_Pos = 0x1e
	// Bit mask of REG_FLASH_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_FLASH_SYS_CLK_EN_Msk = 0x40000000
	// Bit REG_FLASH_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_FLASH_SYS_CLK_EN = 0x40000000
	// Position of REG_PSRAM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_PSRAM_SYS_CLK_EN_Pos = 0x1f
	// Bit mask of REG_PSRAM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_PSRAM_SYS_CLK_EN_Msk = 0x80000000
	// Bit REG_PSRAM_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL0_REG_PSRAM_SYS_CLK_EN = 0x80000000

	// SOC_CLK_CTRL1: Reserved
	// Position of REG_GPSPI2_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GPSPI2_SYS_CLK_EN_Pos = 0x0
	// Bit mask of REG_GPSPI2_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GPSPI2_SYS_CLK_EN_Msk = 0x1
	// Bit REG_GPSPI2_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GPSPI2_SYS_CLK_EN = 0x1
	// Position of REG_GPSPI3_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GPSPI3_SYS_CLK_EN_Pos = 0x1
	// Bit mask of REG_GPSPI3_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GPSPI3_SYS_CLK_EN_Msk = 0x2
	// Bit REG_GPSPI3_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GPSPI3_SYS_CLK_EN = 0x2
	// Position of REG_REGDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_REGDMA_SYS_CLK_EN_Pos = 0x2
	// Bit mask of REG_REGDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_REGDMA_SYS_CLK_EN_Msk = 0x4
	// Bit REG_REGDMA_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_REGDMA_SYS_CLK_EN = 0x4
	// Position of REG_AHB_PDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_AHB_PDMA_SYS_CLK_EN_Pos = 0x3
	// Bit mask of REG_AHB_PDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_AHB_PDMA_SYS_CLK_EN_Msk = 0x8
	// Bit REG_AHB_PDMA_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_AHB_PDMA_SYS_CLK_EN = 0x8
	// Position of REG_AXI_PDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_AXI_PDMA_SYS_CLK_EN_Pos = 0x4
	// Bit mask of REG_AXI_PDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_AXI_PDMA_SYS_CLK_EN_Msk = 0x10
	// Bit REG_AXI_PDMA_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_AXI_PDMA_SYS_CLK_EN = 0x10
	// Position of REG_GDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GDMA_SYS_CLK_EN_Pos = 0x5
	// Bit mask of REG_GDMA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GDMA_SYS_CLK_EN_Msk = 0x20
	// Bit REG_GDMA_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_GDMA_SYS_CLK_EN = 0x20
	// Position of REG_DMA2D_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_DMA2D_SYS_CLK_EN_Pos = 0x6
	// Bit mask of REG_DMA2D_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_DMA2D_SYS_CLK_EN_Msk = 0x40
	// Bit REG_DMA2D_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_DMA2D_SYS_CLK_EN = 0x40
	// Position of REG_VPU_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_VPU_SYS_CLK_EN_Pos = 0x7
	// Bit mask of REG_VPU_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_VPU_SYS_CLK_EN_Msk = 0x80
	// Bit REG_VPU_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_VPU_SYS_CLK_EN = 0x80
	// Position of REG_JPEG_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_JPEG_SYS_CLK_EN_Pos = 0x8
	// Bit mask of REG_JPEG_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_JPEG_SYS_CLK_EN_Msk = 0x100
	// Bit REG_JPEG_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_JPEG_SYS_CLK_EN = 0x100
	// Position of REG_PPA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PPA_SYS_CLK_EN_Pos = 0x9
	// Bit mask of REG_PPA_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PPA_SYS_CLK_EN_Msk = 0x200
	// Bit REG_PPA_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PPA_SYS_CLK_EN = 0x200
	// Position of REG_CSI_BRG_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CSI_BRG_SYS_CLK_EN_Pos = 0xa
	// Bit mask of REG_CSI_BRG_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CSI_BRG_SYS_CLK_EN_Msk = 0x400
	// Bit REG_CSI_BRG_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CSI_BRG_SYS_CLK_EN = 0x400
	// Position of REG_CSI_HOST_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CSI_HOST_SYS_CLK_EN_Pos = 0xb
	// Bit mask of REG_CSI_HOST_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CSI_HOST_SYS_CLK_EN_Msk = 0x800
	// Bit REG_CSI_HOST_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CSI_HOST_SYS_CLK_EN = 0x800
	// Position of REG_DSI_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_DSI_SYS_CLK_EN_Pos = 0xc
	// Bit mask of REG_DSI_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_DSI_SYS_CLK_EN_Msk = 0x1000
	// Bit REG_DSI_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_DSI_SYS_CLK_EN = 0x1000
	// Position of REG_EMAC_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_EMAC_SYS_CLK_EN_Pos = 0xd
	// Bit mask of REG_EMAC_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_EMAC_SYS_CLK_EN_Msk = 0x2000
	// Bit REG_EMAC_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_EMAC_SYS_CLK_EN = 0x2000
	// Position of REG_SDMMC_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_SDMMC_SYS_CLK_EN_Pos = 0xe
	// Bit mask of REG_SDMMC_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_SDMMC_SYS_CLK_EN_Msk = 0x4000
	// Bit REG_SDMMC_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_SDMMC_SYS_CLK_EN = 0x4000
	// Position of REG_USB_OTG11_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_USB_OTG11_SYS_CLK_EN_Pos = 0xf
	// Bit mask of REG_USB_OTG11_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_USB_OTG11_SYS_CLK_EN_Msk = 0x8000
	// Bit REG_USB_OTG11_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_USB_OTG11_SYS_CLK_EN = 0x8000
	// Position of REG_USB_OTG20_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_USB_OTG20_SYS_CLK_EN_Pos = 0x10
	// Bit mask of REG_USB_OTG20_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_USB_OTG20_SYS_CLK_EN_Msk = 0x10000
	// Bit REG_USB_OTG20_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_USB_OTG20_SYS_CLK_EN = 0x10000
	// Position of REG_UHCI_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UHCI_SYS_CLK_EN_Pos = 0x11
	// Bit mask of REG_UHCI_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UHCI_SYS_CLK_EN_Msk = 0x20000
	// Bit REG_UHCI_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UHCI_SYS_CLK_EN = 0x20000
	// Position of REG_UART0_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART0_SYS_CLK_EN_Pos = 0x12
	// Bit mask of REG_UART0_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART0_SYS_CLK_EN_Msk = 0x40000
	// Bit REG_UART0_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART0_SYS_CLK_EN = 0x40000
	// Position of REG_UART1_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART1_SYS_CLK_EN_Pos = 0x13
	// Bit mask of REG_UART1_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART1_SYS_CLK_EN_Msk = 0x80000
	// Bit REG_UART1_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART1_SYS_CLK_EN = 0x80000
	// Position of REG_UART2_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART2_SYS_CLK_EN_Pos = 0x14
	// Bit mask of REG_UART2_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART2_SYS_CLK_EN_Msk = 0x100000
	// Bit REG_UART2_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART2_SYS_CLK_EN = 0x100000
	// Position of REG_UART3_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART3_SYS_CLK_EN_Pos = 0x15
	// Bit mask of REG_UART3_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART3_SYS_CLK_EN_Msk = 0x200000
	// Bit REG_UART3_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART3_SYS_CLK_EN = 0x200000
	// Position of REG_UART4_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART4_SYS_CLK_EN_Pos = 0x16
	// Bit mask of REG_UART4_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART4_SYS_CLK_EN_Msk = 0x400000
	// Bit REG_UART4_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_UART4_SYS_CLK_EN = 0x400000
	// Position of REG_PARLIO_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PARLIO_SYS_CLK_EN_Pos = 0x17
	// Bit mask of REG_PARLIO_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PARLIO_SYS_CLK_EN_Msk = 0x800000
	// Bit REG_PARLIO_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PARLIO_SYS_CLK_EN = 0x800000
	// Position of REG_ETM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_ETM_SYS_CLK_EN_Pos = 0x18
	// Bit mask of REG_ETM_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_ETM_SYS_CLK_EN_Msk = 0x1000000
	// Bit REG_ETM_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_ETM_SYS_CLK_EN = 0x1000000
	// Position of REG_PVT_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PVT_SYS_CLK_EN_Pos = 0x19
	// Bit mask of REG_PVT_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PVT_SYS_CLK_EN_Msk = 0x2000000
	// Bit REG_PVT_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_PVT_SYS_CLK_EN = 0x2000000
	// Position of REG_CRYPTO_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CRYPTO_SYS_CLK_EN_Pos = 0x1a
	// Bit mask of REG_CRYPTO_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CRYPTO_SYS_CLK_EN_Msk = 0x4000000
	// Bit REG_CRYPTO_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_CRYPTO_SYS_CLK_EN = 0x4000000
	// Position of REG_KEY_MANAGER_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_KEY_MANAGER_SYS_CLK_EN_Pos = 0x1b
	// Bit mask of REG_KEY_MANAGER_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_KEY_MANAGER_SYS_CLK_EN_Msk = 0x8000000
	// Bit REG_KEY_MANAGER_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_KEY_MANAGER_SYS_CLK_EN = 0x8000000
	// Position of REG_BITSRAMBLER_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_SYS_CLK_EN_Pos = 0x1c
	// Bit mask of REG_BITSRAMBLER_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_SYS_CLK_EN_Msk = 0x10000000
	// Bit REG_BITSRAMBLER_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_SYS_CLK_EN = 0x10000000
	// Position of REG_BITSRAMBLER_RX_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_RX_SYS_CLK_EN_Pos = 0x1d
	// Bit mask of REG_BITSRAMBLER_RX_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_RX_SYS_CLK_EN_Msk = 0x20000000
	// Bit REG_BITSRAMBLER_RX_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_RX_SYS_CLK_EN = 0x20000000
	// Position of REG_BITSRAMBLER_TX_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_TX_SYS_CLK_EN_Pos = 0x1e
	// Bit mask of REG_BITSRAMBLER_TX_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_TX_SYS_CLK_EN_Msk = 0x40000000
	// Bit REG_BITSRAMBLER_TX_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_BITSRAMBLER_TX_SYS_CLK_EN = 0x40000000
	// Position of REG_H264_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_H264_SYS_CLK_EN_Pos = 0x1f
	// Bit mask of REG_H264_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_H264_SYS_CLK_EN_Msk = 0x80000000
	// Bit REG_H264_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL1_REG_H264_SYS_CLK_EN = 0x80000000

	// SOC_CLK_CTRL2: Reserved
	// Position of REG_RMT_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_RMT_SYS_CLK_EN_Pos = 0x0
	// Bit mask of REG_RMT_SYS_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_RMT_SYS_CLK_EN_Msk = 0x1
	// Bit REG_RMT_SYS_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_RMT_SYS_CLK_EN = 0x1
	// Position of REG_HP_CLKRST_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_HP_CLKRST_APB_CLK_EN_Pos = 0x1
	// Bit mask of REG_HP_CLKRST_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_HP_CLKRST_APB_CLK_EN_Msk = 0x2
	// Bit REG_HP_CLKRST_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_HP_CLKRST_APB_CLK_EN = 0x2
	// Position of REG_SYSREG_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_SYSREG_APB_CLK_EN_Pos = 0x2
	// Bit mask of REG_SYSREG_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_SYSREG_APB_CLK_EN_Msk = 0x4
	// Bit REG_SYSREG_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_SYSREG_APB_CLK_EN = 0x4
	// Position of REG_ICM_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_ICM_APB_CLK_EN_Pos = 0x3
	// Bit mask of REG_ICM_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_ICM_APB_CLK_EN_Msk = 0x8
	// Bit REG_ICM_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_ICM_APB_CLK_EN = 0x8
	// Position of REG_INTRMTX_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_INTRMTX_APB_CLK_EN_Pos = 0x4
	// Bit mask of REG_INTRMTX_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_INTRMTX_APB_CLK_EN_Msk = 0x10
	// Bit REG_INTRMTX_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_INTRMTX_APB_CLK_EN = 0x10
	// Position of REG_ADC_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_ADC_APB_CLK_EN_Pos = 0x5
	// Bit mask of REG_ADC_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_ADC_APB_CLK_EN_Msk = 0x20
	// Bit REG_ADC_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_ADC_APB_CLK_EN = 0x20
	// Position of REG_UHCI_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UHCI_APB_CLK_EN_Pos = 0x6
	// Bit mask of REG_UHCI_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UHCI_APB_CLK_EN_Msk = 0x40
	// Bit REG_UHCI_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UHCI_APB_CLK_EN = 0x40
	// Position of REG_UART0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART0_APB_CLK_EN_Pos = 0x7
	// Bit mask of REG_UART0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART0_APB_CLK_EN_Msk = 0x80
	// Bit REG_UART0_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART0_APB_CLK_EN = 0x80
	// Position of REG_UART1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART1_APB_CLK_EN_Pos = 0x8
	// Bit mask of REG_UART1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART1_APB_CLK_EN_Msk = 0x100
	// Bit REG_UART1_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART1_APB_CLK_EN = 0x100
	// Position of REG_UART2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART2_APB_CLK_EN_Pos = 0x9
	// Bit mask of REG_UART2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART2_APB_CLK_EN_Msk = 0x200
	// Bit REG_UART2_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART2_APB_CLK_EN = 0x200
	// Position of REG_UART3_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART3_APB_CLK_EN_Pos = 0xa
	// Bit mask of REG_UART3_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART3_APB_CLK_EN_Msk = 0x400
	// Bit REG_UART3_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART3_APB_CLK_EN = 0x400
	// Position of REG_UART4_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART4_APB_CLK_EN_Pos = 0xb
	// Bit mask of REG_UART4_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART4_APB_CLK_EN_Msk = 0x800
	// Bit REG_UART4_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_UART4_APB_CLK_EN = 0x800
	// Position of REG_I2C0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2C0_APB_CLK_EN_Pos = 0xc
	// Bit mask of REG_I2C0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2C0_APB_CLK_EN_Msk = 0x1000
	// Bit REG_I2C0_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2C0_APB_CLK_EN = 0x1000
	// Position of REG_I2C1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2C1_APB_CLK_EN_Pos = 0xd
	// Bit mask of REG_I2C1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2C1_APB_CLK_EN_Msk = 0x2000
	// Bit REG_I2C1_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2C1_APB_CLK_EN = 0x2000
	// Position of REG_I2S0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S0_APB_CLK_EN_Pos = 0xe
	// Bit mask of REG_I2S0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S0_APB_CLK_EN_Msk = 0x4000
	// Bit REG_I2S0_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S0_APB_CLK_EN = 0x4000
	// Position of REG_I2S1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S1_APB_CLK_EN_Pos = 0xf
	// Bit mask of REG_I2S1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S1_APB_CLK_EN_Msk = 0x8000
	// Bit REG_I2S1_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S1_APB_CLK_EN = 0x8000
	// Position of REG_I2S2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S2_APB_CLK_EN_Pos = 0x10
	// Bit mask of REG_I2S2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S2_APB_CLK_EN_Msk = 0x10000
	// Bit REG_I2S2_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I2S2_APB_CLK_EN = 0x10000
	// Position of REG_I3C_MST_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I3C_MST_APB_CLK_EN_Pos = 0x11
	// Bit mask of REG_I3C_MST_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I3C_MST_APB_CLK_EN_Msk = 0x20000
	// Bit REG_I3C_MST_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I3C_MST_APB_CLK_EN = 0x20000
	// Position of REG_I3C_SLV_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I3C_SLV_APB_CLK_EN_Pos = 0x12
	// Bit mask of REG_I3C_SLV_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I3C_SLV_APB_CLK_EN_Msk = 0x40000
	// Bit REG_I3C_SLV_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_I3C_SLV_APB_CLK_EN = 0x40000
	// Position of REG_GPSPI2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_GPSPI2_APB_CLK_EN_Pos = 0x13
	// Bit mask of REG_GPSPI2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_GPSPI2_APB_CLK_EN_Msk = 0x80000
	// Bit REG_GPSPI2_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_GPSPI2_APB_CLK_EN = 0x80000
	// Position of REG_GPSPI3_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_GPSPI3_APB_CLK_EN_Pos = 0x14
	// Bit mask of REG_GPSPI3_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_GPSPI3_APB_CLK_EN_Msk = 0x100000
	// Bit REG_GPSPI3_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_GPSPI3_APB_CLK_EN = 0x100000
	// Position of REG_TIMERGRP0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TIMERGRP0_APB_CLK_EN_Pos = 0x15
	// Bit mask of REG_TIMERGRP0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TIMERGRP0_APB_CLK_EN_Msk = 0x200000
	// Bit REG_TIMERGRP0_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TIMERGRP0_APB_CLK_EN = 0x200000
	// Position of REG_TIMERGRP1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TIMERGRP1_APB_CLK_EN_Pos = 0x16
	// Bit mask of REG_TIMERGRP1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TIMERGRP1_APB_CLK_EN_Msk = 0x400000
	// Bit REG_TIMERGRP1_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TIMERGRP1_APB_CLK_EN = 0x400000
	// Position of REG_SYSTIMER_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_SYSTIMER_APB_CLK_EN_Pos = 0x17
	// Bit mask of REG_SYSTIMER_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_SYSTIMER_APB_CLK_EN_Msk = 0x800000
	// Bit REG_SYSTIMER_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_SYSTIMER_APB_CLK_EN = 0x800000
	// Position of REG_TWAI0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI0_APB_CLK_EN_Pos = 0x18
	// Bit mask of REG_TWAI0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI0_APB_CLK_EN_Msk = 0x1000000
	// Bit REG_TWAI0_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI0_APB_CLK_EN = 0x1000000
	// Position of REG_TWAI1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI1_APB_CLK_EN_Pos = 0x19
	// Bit mask of REG_TWAI1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI1_APB_CLK_EN_Msk = 0x2000000
	// Bit REG_TWAI1_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI1_APB_CLK_EN = 0x2000000
	// Position of REG_TWAI2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI2_APB_CLK_EN_Pos = 0x1a
	// Bit mask of REG_TWAI2_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI2_APB_CLK_EN_Msk = 0x4000000
	// Bit REG_TWAI2_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_TWAI2_APB_CLK_EN = 0x4000000
	// Position of REG_MCPWM0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_MCPWM0_APB_CLK_EN_Pos = 0x1b
	// Bit mask of REG_MCPWM0_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_MCPWM0_APB_CLK_EN_Msk = 0x8000000
	// Bit REG_MCPWM0_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_MCPWM0_APB_CLK_EN = 0x8000000
	// Position of REG_MCPWM1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_MCPWM1_APB_CLK_EN_Pos = 0x1c
	// Bit mask of REG_MCPWM1_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_MCPWM1_APB_CLK_EN_Msk = 0x10000000
	// Bit REG_MCPWM1_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_MCPWM1_APB_CLK_EN = 0x10000000
	// Position of REG_USB_DEVICE_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_USB_DEVICE_APB_CLK_EN_Pos = 0x1d
	// Bit mask of REG_USB_DEVICE_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_USB_DEVICE_APB_CLK_EN_Msk = 0x20000000
	// Bit REG_USB_DEVICE_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_USB_DEVICE_APB_CLK_EN = 0x20000000
	// Position of REG_PCNT_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_PCNT_APB_CLK_EN_Pos = 0x1e
	// Bit mask of REG_PCNT_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_PCNT_APB_CLK_EN_Msk = 0x40000000
	// Bit REG_PCNT_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_PCNT_APB_CLK_EN = 0x40000000
	// Position of REG_PARLIO_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_PARLIO_APB_CLK_EN_Pos = 0x1f
	// Bit mask of REG_PARLIO_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_PARLIO_APB_CLK_EN_Msk = 0x80000000
	// Bit REG_PARLIO_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL2_REG_PARLIO_APB_CLK_EN = 0x80000000

	// SOC_CLK_CTRL3: Reserved
	// Position of REG_LEDC_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_LEDC_APB_CLK_EN_Pos = 0x0
	// Bit mask of REG_LEDC_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_LEDC_APB_CLK_EN_Msk = 0x1
	// Bit REG_LEDC_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_LEDC_APB_CLK_EN = 0x1
	// Position of REG_LCDCAM_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_LCDCAM_APB_CLK_EN_Pos = 0x1
	// Bit mask of REG_LCDCAM_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_LCDCAM_APB_CLK_EN_Msk = 0x2
	// Bit REG_LCDCAM_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_LCDCAM_APB_CLK_EN = 0x2
	// Position of REG_ETM_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_ETM_APB_CLK_EN_Pos = 0x2
	// Bit mask of REG_ETM_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_ETM_APB_CLK_EN_Msk = 0x4
	// Bit REG_ETM_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_ETM_APB_CLK_EN = 0x4
	// Position of REG_IOMUX_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_IOMUX_APB_CLK_EN_Pos = 0x3
	// Bit mask of REG_IOMUX_APB_CLK_EN field.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_IOMUX_APB_CLK_EN_Msk = 0x8
	// Bit REG_IOMUX_APB_CLK_EN.
	HP_SYS_CLKRST_SOC_CLK_CTRL3_REG_IOMUX_APB_CLK_EN = 0x8

	// REF_CLK_CTRL0: Reserved
	// Position of REG_REF_50M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_50M_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_REF_50M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_50M_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_REF_25M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_25M_CLK_DIV_NUM_Pos = 0x8
	// Bit mask of REG_REF_25M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_25M_CLK_DIV_NUM_Msk = 0xff00
	// Position of REG_REF_240M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_240M_CLK_DIV_NUM_Pos = 0x10
	// Bit mask of REG_REF_240M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_240M_CLK_DIV_NUM_Msk = 0xff0000
	// Position of REG_REF_160M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_160M_CLK_DIV_NUM_Pos = 0x18
	// Bit mask of REG_REF_160M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL0_REG_REF_160M_CLK_DIV_NUM_Msk = 0xff000000

	// REF_CLK_CTRL1: Reserved
	// Position of REG_REF_120M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_120M_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_REF_120M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_120M_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_REF_80M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_80M_CLK_DIV_NUM_Pos = 0x8
	// Bit mask of REG_REF_80M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_80M_CLK_DIV_NUM_Msk = 0xff00
	// Position of REG_REF_20M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_20M_CLK_DIV_NUM_Pos = 0x10
	// Bit mask of REG_REF_20M_CLK_DIV_NUM field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_20M_CLK_DIV_NUM_Msk = 0xff0000
	// Position of REG_TM_400M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_400M_CLK_EN_Pos = 0x18
	// Bit mask of REG_TM_400M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_400M_CLK_EN_Msk = 0x1000000
	// Bit REG_TM_400M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_400M_CLK_EN = 0x1000000
	// Position of REG_TM_200M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_200M_CLK_EN_Pos = 0x19
	// Bit mask of REG_TM_200M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_200M_CLK_EN_Msk = 0x2000000
	// Bit REG_TM_200M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_200M_CLK_EN = 0x2000000
	// Position of REG_TM_100M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_100M_CLK_EN_Pos = 0x1a
	// Bit mask of REG_TM_100M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_100M_CLK_EN_Msk = 0x4000000
	// Bit REG_TM_100M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_100M_CLK_EN = 0x4000000
	// Position of REG_REF_50M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_50M_CLK_EN_Pos = 0x1b
	// Bit mask of REG_REF_50M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_50M_CLK_EN_Msk = 0x8000000
	// Bit REG_REF_50M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_50M_CLK_EN = 0x8000000
	// Position of REG_REF_25M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_25M_CLK_EN_Pos = 0x1c
	// Bit mask of REG_REF_25M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_25M_CLK_EN_Msk = 0x10000000
	// Bit REG_REF_25M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_25M_CLK_EN = 0x10000000
	// Position of REG_TM_480M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_480M_CLK_EN_Pos = 0x1d
	// Bit mask of REG_TM_480M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_480M_CLK_EN_Msk = 0x20000000
	// Bit REG_TM_480M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_480M_CLK_EN = 0x20000000
	// Position of REG_REF_240M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_240M_CLK_EN_Pos = 0x1e
	// Bit mask of REG_REF_240M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_240M_CLK_EN_Msk = 0x40000000
	// Bit REG_REF_240M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_REF_240M_CLK_EN = 0x40000000
	// Position of REG_TM_240M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_240M_CLK_EN_Pos = 0x1f
	// Bit mask of REG_TM_240M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_240M_CLK_EN_Msk = 0x80000000
	// Bit REG_TM_240M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL1_REG_TM_240M_CLK_EN = 0x80000000

	// REF_CLK_CTRL2: Reserved
	// Position of REG_REF_160M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_160M_CLK_EN_Pos = 0x0
	// Bit mask of REG_REF_160M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_160M_CLK_EN_Msk = 0x1
	// Bit REG_REF_160M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_160M_CLK_EN = 0x1
	// Position of REG_TM_160M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_160M_CLK_EN_Pos = 0x1
	// Bit mask of REG_TM_160M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_160M_CLK_EN_Msk = 0x2
	// Bit REG_TM_160M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_160M_CLK_EN = 0x2
	// Position of REG_REF_120M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_120M_CLK_EN_Pos = 0x2
	// Bit mask of REG_REF_120M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_120M_CLK_EN_Msk = 0x4
	// Bit REG_REF_120M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_120M_CLK_EN = 0x4
	// Position of REG_TM_120M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_120M_CLK_EN_Pos = 0x3
	// Bit mask of REG_TM_120M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_120M_CLK_EN_Msk = 0x8
	// Bit REG_TM_120M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_120M_CLK_EN = 0x8
	// Position of REG_REF_80M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_80M_CLK_EN_Pos = 0x4
	// Bit mask of REG_REF_80M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_80M_CLK_EN_Msk = 0x10
	// Bit REG_REF_80M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_80M_CLK_EN = 0x10
	// Position of REG_TM_80M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_80M_CLK_EN_Pos = 0x5
	// Bit mask of REG_TM_80M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_80M_CLK_EN_Msk = 0x20
	// Bit REG_TM_80M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_80M_CLK_EN = 0x20
	// Position of REG_TM_60M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_60M_CLK_EN_Pos = 0x6
	// Bit mask of REG_TM_60M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_60M_CLK_EN_Msk = 0x40
	// Bit REG_TM_60M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_60M_CLK_EN = 0x40
	// Position of REG_TM_48M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_48M_CLK_EN_Pos = 0x7
	// Bit mask of REG_TM_48M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_48M_CLK_EN_Msk = 0x80
	// Bit REG_TM_48M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_48M_CLK_EN = 0x80
	// Position of REG_REF_20M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_20M_CLK_EN_Pos = 0x8
	// Bit mask of REG_REF_20M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_20M_CLK_EN_Msk = 0x100
	// Bit REG_REF_20M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_REF_20M_CLK_EN = 0x100
	// Position of REG_TM_20M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_20M_CLK_EN_Pos = 0x9
	// Bit mask of REG_TM_20M_CLK_EN field.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_20M_CLK_EN_Msk = 0x200
	// Bit REG_TM_20M_CLK_EN.
	HP_SYS_CLKRST_REF_CLK_CTRL2_REG_TM_20M_CLK_EN = 0x200

	// PERI_CLK_CTRL00: Reserved
	// Position of REG_FLASH_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_CLK_SRC_SEL_Pos = 0x0
	// Bit mask of REG_FLASH_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_CLK_SRC_SEL_Msk = 0x3
	// Position of REG_FLASH_PLL_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_PLL_CLK_EN_Pos = 0x2
	// Bit mask of REG_FLASH_PLL_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_PLL_CLK_EN_Msk = 0x4
	// Bit REG_FLASH_PLL_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_PLL_CLK_EN = 0x4
	// Position of REG_FLASH_CORE_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_CORE_CLK_EN_Pos = 0x3
	// Bit mask of REG_FLASH_CORE_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_CORE_CLK_EN_Msk = 0x8
	// Bit REG_FLASH_CORE_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_CORE_CLK_EN = 0x8
	// Position of REG_FLASH_CORE_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_CORE_CLK_DIV_NUM_Pos = 0x4
	// Bit mask of REG_FLASH_CORE_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_FLASH_CORE_CLK_DIV_NUM_Msk = 0xff0
	// Position of REG_PSRAM_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_CLK_SRC_SEL_Pos = 0xc
	// Bit mask of REG_PSRAM_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_CLK_SRC_SEL_Msk = 0x3000
	// Position of REG_PSRAM_PLL_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_PLL_CLK_EN_Pos = 0xe
	// Bit mask of REG_PSRAM_PLL_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_PLL_CLK_EN_Msk = 0x4000
	// Bit REG_PSRAM_PLL_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_PLL_CLK_EN = 0x4000
	// Position of REG_PSRAM_CORE_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_EN_Pos = 0xf
	// Bit mask of REG_PSRAM_CORE_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_EN_Msk = 0x8000
	// Bit REG_PSRAM_CORE_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_EN = 0x8000
	// Position of REG_PSRAM_CORE_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_DIV_NUM_Pos = 0x10
	// Bit mask of REG_PSRAM_CORE_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PSRAM_CORE_CLK_DIV_NUM_Msk = 0xff0000
	// Position of REG_PAD_EMAC_REF_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PAD_EMAC_REF_CLK_EN_Pos = 0x18
	// Bit mask of REG_PAD_EMAC_REF_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PAD_EMAC_REF_CLK_EN_Msk = 0x1000000
	// Bit REG_PAD_EMAC_REF_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_PAD_EMAC_REF_CLK_EN = 0x1000000
	// Position of REG_EMAC_RMII_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RMII_CLK_SRC_SEL_Pos = 0x19
	// Bit mask of REG_EMAC_RMII_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RMII_CLK_SRC_SEL_Msk = 0x6000000
	// Position of REG_EMAC_RMII_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RMII_CLK_EN_Pos = 0x1b
	// Bit mask of REG_EMAC_RMII_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RMII_CLK_EN_Msk = 0x8000000
	// Bit REG_EMAC_RMII_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RMII_CLK_EN = 0x8000000
	// Position of REG_EMAC_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RX_CLK_SRC_SEL_Pos = 0x1c
	// Bit mask of REG_EMAC_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RX_CLK_SRC_SEL_Msk = 0x10000000
	// Bit REG_EMAC_RX_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RX_CLK_SRC_SEL = 0x10000000
	// Position of REG_EMAC_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RX_CLK_EN_Pos = 0x1d
	// Bit mask of REG_EMAC_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RX_CLK_EN_Msk = 0x20000000
	// Bit REG_EMAC_RX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL00_REG_EMAC_RX_CLK_EN = 0x20000000

	// PERI_CLK_CTRL01: Reserved
	// Position of REG_EMAC_RX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_RX_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_EMAC_RX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_RX_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_EMAC_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_SRC_SEL_Pos = 0x8
	// Bit mask of REG_EMAC_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_SRC_SEL_Msk = 0x100
	// Bit REG_EMAC_TX_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_SRC_SEL = 0x100
	// Position of REG_EMAC_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_EN_Pos = 0x9
	// Bit mask of REG_EMAC_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_EN_Msk = 0x200
	// Bit REG_EMAC_TX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_EN = 0x200
	// Position of REG_EMAC_TX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_DIV_NUM_Pos = 0xa
	// Bit mask of REG_EMAC_TX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_TX_CLK_DIV_NUM_Msk = 0x3fc00
	// Position of REG_EMAC_PTP_REF_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_SRC_SEL_Pos = 0x12
	// Bit mask of REG_EMAC_PTP_REF_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_SRC_SEL_Msk = 0x40000
	// Bit REG_EMAC_PTP_REF_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_SRC_SEL = 0x40000
	// Position of REG_EMAC_PTP_REF_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_EN_Pos = 0x13
	// Bit mask of REG_EMAC_PTP_REF_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_EN_Msk = 0x80000
	// Bit REG_EMAC_PTP_REF_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_PTP_REF_CLK_EN = 0x80000
	// Position of REG_EMAC_UNUSED0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_UNUSED0_CLK_EN_Pos = 0x14
	// Bit mask of REG_EMAC_UNUSED0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_UNUSED0_CLK_EN_Msk = 0x100000
	// Bit REG_EMAC_UNUSED0_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_UNUSED0_CLK_EN = 0x100000
	// Position of REG_EMAC_UNUSED1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_UNUSED1_CLK_EN_Pos = 0x15
	// Bit mask of REG_EMAC_UNUSED1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_UNUSED1_CLK_EN_Msk = 0x200000
	// Bit REG_EMAC_UNUSED1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_EMAC_UNUSED1_CLK_EN = 0x200000
	// Position of REG_SDIO_HS_MODE field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_HS_MODE_Pos = 0x16
	// Bit mask of REG_SDIO_HS_MODE field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_HS_MODE_Msk = 0x400000
	// Bit REG_SDIO_HS_MODE.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_HS_MODE = 0x400000
	// Position of REG_SDIO_LS_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_LS_CLK_SRC_SEL_Pos = 0x17
	// Bit mask of REG_SDIO_LS_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_LS_CLK_SRC_SEL_Msk = 0x800000
	// Bit REG_SDIO_LS_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_LS_CLK_SRC_SEL = 0x800000
	// Position of REG_SDIO_LS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_LS_CLK_EN_Pos = 0x18
	// Bit mask of REG_SDIO_LS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_LS_CLK_EN_Msk = 0x1000000
	// Bit REG_SDIO_LS_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL01_REG_SDIO_LS_CLK_EN = 0x1000000

	// PERI_CLK_CTRL02: Reserved
	// Position of REG_SDIO_LS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_SDIO_LS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_SDIO_LS_CLK_EDGE_CFG_UPDATE field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_Pos = 0x8
	// Bit mask of REG_SDIO_LS_CLK_EDGE_CFG_UPDATE field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_Msk = 0x100
	// Bit REG_SDIO_LS_CLK_EDGE_CFG_UPDATE.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE = 0x100
	// Position of REG_SDIO_LS_CLK_EDGE_L field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_L_Pos = 0x9
	// Bit mask of REG_SDIO_LS_CLK_EDGE_L field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_L_Msk = 0x1e00
	// Position of REG_SDIO_LS_CLK_EDGE_H field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_H_Pos = 0xd
	// Bit mask of REG_SDIO_LS_CLK_EDGE_H field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_H_Msk = 0x1e000
	// Position of REG_SDIO_LS_CLK_EDGE_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_N_Pos = 0x11
	// Bit mask of REG_SDIO_LS_CLK_EDGE_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_CLK_EDGE_N_Msk = 0x1e0000
	// Position of REG_SDIO_LS_SLF_CLK_EDGE_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EDGE_SEL_Pos = 0x15
	// Bit mask of REG_SDIO_LS_SLF_CLK_EDGE_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EDGE_SEL_Msk = 0x600000
	// Position of REG_SDIO_LS_DRV_CLK_EDGE_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EDGE_SEL_Pos = 0x17
	// Bit mask of REG_SDIO_LS_DRV_CLK_EDGE_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EDGE_SEL_Msk = 0x1800000
	// Position of REG_SDIO_LS_SAM_CLK_EDGE_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EDGE_SEL_Pos = 0x19
	// Bit mask of REG_SDIO_LS_SAM_CLK_EDGE_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EDGE_SEL_Msk = 0x6000000
	// Position of REG_SDIO_LS_SLF_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EN_Pos = 0x1b
	// Bit mask of REG_SDIO_LS_SLF_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EN_Msk = 0x8000000
	// Bit REG_SDIO_LS_SLF_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SLF_CLK_EN = 0x8000000
	// Position of REG_SDIO_LS_DRV_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EN_Pos = 0x1c
	// Bit mask of REG_SDIO_LS_DRV_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EN_Msk = 0x10000000
	// Bit REG_SDIO_LS_DRV_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_DRV_CLK_EN = 0x10000000
	// Position of REG_SDIO_LS_SAM_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EN_Pos = 0x1d
	// Bit mask of REG_SDIO_LS_SAM_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EN_Msk = 0x20000000
	// Bit REG_SDIO_LS_SAM_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_SDIO_LS_SAM_CLK_EN = 0x20000000
	// Position of REG_MIPI_DSI_DPHY_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_Pos = 0x1e
	// Bit mask of REG_MIPI_DSI_DPHY_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL02_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_Msk = 0xc0000000

	// PERI_CLK_CTRL03: Reserved
	// Position of REG_MIPI_DSI_DPHY_CFG_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_CFG_CLK_EN_Pos = 0x0
	// Bit mask of REG_MIPI_DSI_DPHY_CFG_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_CFG_CLK_EN_Msk = 0x1
	// Bit REG_MIPI_DSI_DPHY_CFG_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_CFG_CLK_EN = 0x1
	// Position of REG_MIPI_DSI_DPHY_PLL_REFCLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_Pos = 0x1
	// Bit mask of REG_MIPI_DSI_DPHY_PLL_REFCLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_Msk = 0x2
	// Bit REG_MIPI_DSI_DPHY_PLL_REFCLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN = 0x2
	// Position of REG_MIPI_CSI_DPHY_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_Pos = 0x2
	// Bit mask of REG_MIPI_CSI_DPHY_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_Msk = 0xc
	// Position of REG_MIPI_CSI_DPHY_CFG_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CFG_CLK_EN_Pos = 0x4
	// Bit mask of REG_MIPI_CSI_DPHY_CFG_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CFG_CLK_EN_Msk = 0x10
	// Bit REG_MIPI_CSI_DPHY_CFG_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_CSI_DPHY_CFG_CLK_EN = 0x10
	// Position of REG_MIPI_DSI_DPICLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_SRC_SEL_Pos = 0x5
	// Bit mask of REG_MIPI_DSI_DPICLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_SRC_SEL_Msk = 0x60
	// Position of REG_MIPI_DSI_DPICLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_EN_Pos = 0x7
	// Bit mask of REG_MIPI_DSI_DPICLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_EN_Msk = 0x80
	// Bit REG_MIPI_DSI_DPICLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_EN = 0x80
	// Position of REG_MIPI_DSI_DPICLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_DIV_NUM_Pos = 0x8
	// Bit mask of REG_MIPI_DSI_DPICLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL03_REG_MIPI_DSI_DPICLK_DIV_NUM_Msk = 0xff00

	// PERI_CLK_CTRL10: Reserved
	// Position of REG_I2C0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_SRC_SEL_Pos = 0x0
	// Bit mask of REG_I2C0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_SRC_SEL_Msk = 0x1
	// Bit REG_I2C0_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_SRC_SEL = 0x1
	// Position of REG_I2C0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_EN_Pos = 0x1
	// Bit mask of REG_I2C0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_EN_Msk = 0x2
	// Bit REG_I2C0_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_EN = 0x2
	// Position of REG_I2C0_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUM_Pos = 0x2
	// Bit mask of REG_I2C0_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUM_Msk = 0x3fc
	// Position of REG_I2C0_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUMERATOR_Pos = 0xa
	// Bit mask of REG_I2C0_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_DIV_NUMERATOR_Msk = 0x3fc00
	// Position of REG_I2C0_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_DIV_DENOMINATOR_Pos = 0x12
	// Bit mask of REG_I2C0_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C0_CLK_DIV_DENOMINATOR_Msk = 0x3fc0000
	// Position of REG_I2C1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C1_CLK_SRC_SEL_Pos = 0x1a
	// Bit mask of REG_I2C1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C1_CLK_SRC_SEL_Msk = 0x4000000
	// Bit REG_I2C1_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C1_CLK_SRC_SEL = 0x4000000
	// Position of REG_I2C1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C1_CLK_EN_Pos = 0x1b
	// Bit mask of REG_I2C1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C1_CLK_EN_Msk = 0x8000000
	// Bit REG_I2C1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL10_REG_I2C1_CLK_EN = 0x8000000

	// PERI_CLK_CTRL11: Reserved
	// Position of REG_I2C1_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_I2C1_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_I2C1_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_I2C1_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2C1_CLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_I2C1_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2C1_CLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_I2C1_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2C1_CLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_I2S0_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2S0_RX_CLK_EN_Pos = 0x18
	// Bit mask of REG_I2S0_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2S0_RX_CLK_EN_Msk = 0x1000000
	// Bit REG_I2S0_RX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2S0_RX_CLK_EN = 0x1000000
	// Position of REG_I2S0_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2S0_RX_CLK_SRC_SEL_Pos = 0x19
	// Bit mask of REG_I2S0_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL11_REG_I2S0_RX_CLK_SRC_SEL_Msk = 0x6000000

	// PERI_CLK_CTRL12: Reserved
	// Position of REG_I2S0_RX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL12_REG_I2S0_RX_DIV_N_Pos = 0x0
	// Bit mask of REG_I2S0_RX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL12_REG_I2S0_RX_DIV_N_Msk = 0xff
	// Position of REG_I2S0_RX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL12_REG_I2S0_RX_DIV_X_Pos = 0x8
	// Bit mask of REG_I2S0_RX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL12_REG_I2S0_RX_DIV_X_Msk = 0x1ff00
	// Position of REG_I2S0_RX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL12_REG_I2S0_RX_DIV_Y_Pos = 0x11
	// Bit mask of REG_I2S0_RX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL12_REG_I2S0_RX_DIV_Y_Msk = 0x3fe0000

	// PERI_CLK_CTRL13: Reserved
	// Position of REG_I2S0_RX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_RX_DIV_Z_Pos = 0x0
	// Bit mask of REG_I2S0_RX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_RX_DIV_Z_Msk = 0x1ff
	// Position of REG_I2S0_RX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_RX_DIV_YN1_Pos = 0x9
	// Bit mask of REG_I2S0_RX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_RX_DIV_YN1_Msk = 0x200
	// Bit REG_I2S0_RX_DIV_YN1.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_RX_DIV_YN1 = 0x200
	// Position of REG_I2S0_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_CLK_EN_Pos = 0xa
	// Bit mask of REG_I2S0_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_CLK_EN_Msk = 0x400
	// Bit REG_I2S0_TX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_CLK_EN = 0x400
	// Position of REG_I2S0_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_CLK_SRC_SEL_Pos = 0xb
	// Bit mask of REG_I2S0_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_CLK_SRC_SEL_Msk = 0x1800
	// Position of REG_I2S0_TX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_DIV_N_Pos = 0xd
	// Bit mask of REG_I2S0_TX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_DIV_N_Msk = 0x1fe000
	// Position of REG_I2S0_TX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_DIV_X_Pos = 0x15
	// Bit mask of REG_I2S0_TX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL13_REG_I2S0_TX_DIV_X_Msk = 0x3fe00000

	// PERI_CLK_CTRL14: Reserved
	// Position of REG_I2S0_TX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_TX_DIV_Y_Pos = 0x0
	// Bit mask of REG_I2S0_TX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_TX_DIV_Y_Msk = 0x1ff
	// Position of REG_I2S0_TX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_TX_DIV_Z_Pos = 0x9
	// Bit mask of REG_I2S0_TX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_TX_DIV_Z_Msk = 0x3fe00
	// Position of REG_I2S0_TX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_TX_DIV_YN1_Pos = 0x12
	// Bit mask of REG_I2S0_TX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_TX_DIV_YN1_Msk = 0x40000
	// Bit REG_I2S0_TX_DIV_YN1.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_TX_DIV_YN1 = 0x40000
	// Position of REG_I2S0_MST_CLK_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_MST_CLK_SEL_Pos = 0x13
	// Bit mask of REG_I2S0_MST_CLK_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_MST_CLK_SEL_Msk = 0x80000
	// Bit REG_I2S0_MST_CLK_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S0_MST_CLK_SEL = 0x80000
	// Position of REG_I2S1_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S1_RX_CLK_EN_Pos = 0x14
	// Bit mask of REG_I2S1_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S1_RX_CLK_EN_Msk = 0x100000
	// Bit REG_I2S1_RX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S1_RX_CLK_EN = 0x100000
	// Position of REG_I2S1_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S1_RX_CLK_SRC_SEL_Pos = 0x15
	// Bit mask of REG_I2S1_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S1_RX_CLK_SRC_SEL_Msk = 0x600000
	// Position of REG_I2S1_RX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S1_RX_DIV_N_Pos = 0x17
	// Bit mask of REG_I2S1_RX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL14_REG_I2S1_RX_DIV_N_Msk = 0x7f800000

	// PERI_CLK_CTRL15: Reserved
	// Position of REG_I2S1_RX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_X_Pos = 0x0
	// Bit mask of REG_I2S1_RX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_X_Msk = 0x1ff
	// Position of REG_I2S1_RX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_Y_Pos = 0x9
	// Bit mask of REG_I2S1_RX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_Y_Msk = 0x3fe00
	// Position of REG_I2S1_RX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_Z_Pos = 0x12
	// Bit mask of REG_I2S1_RX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_Z_Msk = 0x7fc0000
	// Position of REG_I2S1_RX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_YN1_Pos = 0x1b
	// Bit mask of REG_I2S1_RX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_YN1_Msk = 0x8000000
	// Bit REG_I2S1_RX_DIV_YN1.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_RX_DIV_YN1 = 0x8000000
	// Position of REG_I2S1_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_TX_CLK_EN_Pos = 0x1c
	// Bit mask of REG_I2S1_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_TX_CLK_EN_Msk = 0x10000000
	// Bit REG_I2S1_TX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_TX_CLK_EN = 0x10000000
	// Position of REG_I2S1_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_TX_CLK_SRC_SEL_Pos = 0x1d
	// Bit mask of REG_I2S1_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL15_REG_I2S1_TX_CLK_SRC_SEL_Msk = 0x60000000

	// PERI_CLK_CTRL16: Reserved
	// Position of REG_I2S1_TX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL16_REG_I2S1_TX_DIV_N_Pos = 0x0
	// Bit mask of REG_I2S1_TX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL16_REG_I2S1_TX_DIV_N_Msk = 0xff
	// Position of REG_I2S1_TX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL16_REG_I2S1_TX_DIV_X_Pos = 0x8
	// Bit mask of REG_I2S1_TX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL16_REG_I2S1_TX_DIV_X_Msk = 0x1ff00
	// Position of REG_I2S1_TX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL16_REG_I2S1_TX_DIV_Y_Pos = 0x11
	// Bit mask of REG_I2S1_TX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL16_REG_I2S1_TX_DIV_Y_Msk = 0x3fe0000

	// PERI_CLK_CTRL17: Reserved
	// Position of REG_I2S1_TX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_TX_DIV_Z_Pos = 0x0
	// Bit mask of REG_I2S1_TX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_TX_DIV_Z_Msk = 0x1ff
	// Position of REG_I2S1_TX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_TX_DIV_YN1_Pos = 0x9
	// Bit mask of REG_I2S1_TX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_TX_DIV_YN1_Msk = 0x200
	// Bit REG_I2S1_TX_DIV_YN1.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_TX_DIV_YN1 = 0x200
	// Position of REG_I2S1_MST_CLK_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_MST_CLK_SEL_Pos = 0xa
	// Bit mask of REG_I2S1_MST_CLK_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_MST_CLK_SEL_Msk = 0x400
	// Bit REG_I2S1_MST_CLK_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S1_MST_CLK_SEL = 0x400
	// Position of REG_I2S2_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_CLK_EN_Pos = 0xb
	// Bit mask of REG_I2S2_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_CLK_EN_Msk = 0x800
	// Bit REG_I2S2_RX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_CLK_EN = 0x800
	// Position of REG_I2S2_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_CLK_SRC_SEL_Pos = 0xc
	// Bit mask of REG_I2S2_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_CLK_SRC_SEL_Msk = 0x3000
	// Position of REG_I2S2_RX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_DIV_N_Pos = 0xe
	// Bit mask of REG_I2S2_RX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_DIV_N_Msk = 0x3fc000
	// Position of REG_I2S2_RX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_DIV_X_Pos = 0x16
	// Bit mask of REG_I2S2_RX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL17_REG_I2S2_RX_DIV_X_Msk = 0x7fc00000

	// PERI_CLK_CTRL18: Reserved
	// Position of REG_I2S2_RX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_RX_DIV_Y_Pos = 0x0
	// Bit mask of REG_I2S2_RX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_RX_DIV_Y_Msk = 0x1ff
	// Position of REG_I2S2_RX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_RX_DIV_Z_Pos = 0x9
	// Bit mask of REG_I2S2_RX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_RX_DIV_Z_Msk = 0x3fe00
	// Position of REG_I2S2_RX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_RX_DIV_YN1_Pos = 0x12
	// Bit mask of REG_I2S2_RX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_RX_DIV_YN1_Msk = 0x40000
	// Bit REG_I2S2_RX_DIV_YN1.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_RX_DIV_YN1 = 0x40000
	// Position of REG_I2S2_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_TX_CLK_EN_Pos = 0x13
	// Bit mask of REG_I2S2_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_TX_CLK_EN_Msk = 0x80000
	// Bit REG_I2S2_TX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_TX_CLK_EN = 0x80000
	// Position of REG_I2S2_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_TX_CLK_SRC_SEL_Pos = 0x14
	// Bit mask of REG_I2S2_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_TX_CLK_SRC_SEL_Msk = 0x300000
	// Position of REG_I2S2_TX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_TX_DIV_N_Pos = 0x16
	// Bit mask of REG_I2S2_TX_DIV_N field.
	HP_SYS_CLKRST_PERI_CLK_CTRL18_REG_I2S2_TX_DIV_N_Msk = 0x3fc00000

	// PERI_CLK_CTRL19: Reserved
	// Position of REG_I2S2_TX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_X_Pos = 0x0
	// Bit mask of REG_I2S2_TX_DIV_X field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_X_Msk = 0x1ff
	// Position of REG_I2S2_TX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_Y_Pos = 0x9
	// Bit mask of REG_I2S2_TX_DIV_Y field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_Y_Msk = 0x3fe00
	// Position of REG_I2S2_TX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_Z_Pos = 0x12
	// Bit mask of REG_I2S2_TX_DIV_Z field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_Z_Msk = 0x7fc0000
	// Position of REG_I2S2_TX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_YN1_Pos = 0x1b
	// Bit mask of REG_I2S2_TX_DIV_YN1 field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_YN1_Msk = 0x8000000
	// Bit REG_I2S2_TX_DIV_YN1.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_TX_DIV_YN1 = 0x8000000
	// Position of REG_I2S2_MST_CLK_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_MST_CLK_SEL_Pos = 0x1c
	// Bit mask of REG_I2S2_MST_CLK_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_MST_CLK_SEL_Msk = 0x10000000
	// Bit REG_I2S2_MST_CLK_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_I2S2_MST_CLK_SEL = 0x10000000
	// Position of REG_LCD_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_LCD_CLK_SRC_SEL_Pos = 0x1d
	// Bit mask of REG_LCD_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_LCD_CLK_SRC_SEL_Msk = 0x60000000
	// Position of REG_LCD_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_LCD_CLK_EN_Pos = 0x1f
	// Bit mask of REG_LCD_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_LCD_CLK_EN_Msk = 0x80000000
	// Bit REG_LCD_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL19_REG_LCD_CLK_EN = 0x80000000

	// PERI_CLK_CTRL110: Reserved
	// Position of REG_LCD_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_LCD_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_LCD_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_LCD_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_LCD_CLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_LCD_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_LCD_CLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_LCD_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_LCD_CLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_UART0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_UART0_CLK_SRC_SEL_Pos = 0x18
	// Bit mask of REG_UART0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_UART0_CLK_SRC_SEL_Msk = 0x3000000
	// Position of REG_UART0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_UART0_CLK_EN_Pos = 0x1a
	// Bit mask of REG_UART0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_UART0_CLK_EN_Msk = 0x4000000
	// Bit REG_UART0_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL110_REG_UART0_CLK_EN = 0x4000000

	// PERI_CLK_CTRL111: Reserved
	// Position of REG_UART0_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_UART0_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUM_Msk = 0xff
	// Position of REG_UART0_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_UART0_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART0_SCLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_UART0_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART0_SCLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_UART0_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART0_SCLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_UART1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART1_CLK_SRC_SEL_Pos = 0x18
	// Bit mask of REG_UART1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART1_CLK_SRC_SEL_Msk = 0x3000000
	// Position of REG_UART1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART1_CLK_EN_Pos = 0x1a
	// Bit mask of REG_UART1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART1_CLK_EN_Msk = 0x4000000
	// Bit REG_UART1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL111_REG_UART1_CLK_EN = 0x4000000

	// PERI_CLK_CTRL112: Reserved
	// Position of REG_UART1_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_UART1_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUM_Msk = 0xff
	// Position of REG_UART1_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_UART1_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART1_SCLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_UART1_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART1_SCLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_UART1_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART1_SCLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_UART2_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART2_CLK_SRC_SEL_Pos = 0x18
	// Bit mask of REG_UART2_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART2_CLK_SRC_SEL_Msk = 0x3000000
	// Position of REG_UART2_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART2_CLK_EN_Pos = 0x1a
	// Bit mask of REG_UART2_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART2_CLK_EN_Msk = 0x4000000
	// Bit REG_UART2_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL112_REG_UART2_CLK_EN = 0x4000000

	// PERI_CLK_CTRL113: Reserved
	// Position of REG_UART2_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_UART2_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUM_Msk = 0xff
	// Position of REG_UART2_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_UART2_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART2_SCLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_UART2_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART2_SCLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_UART2_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART2_SCLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_UART3_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART3_CLK_SRC_SEL_Pos = 0x18
	// Bit mask of REG_UART3_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART3_CLK_SRC_SEL_Msk = 0x3000000
	// Position of REG_UART3_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART3_CLK_EN_Pos = 0x1a
	// Bit mask of REG_UART3_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART3_CLK_EN_Msk = 0x4000000
	// Bit REG_UART3_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL113_REG_UART3_CLK_EN = 0x4000000

	// PERI_CLK_CTRL114: Reserved
	// Position of REG_UART3_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_UART3_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUM_Msk = 0xff
	// Position of REG_UART3_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_UART3_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART3_SCLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_UART3_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART3_SCLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_UART3_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART3_SCLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_UART4_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART4_CLK_SRC_SEL_Pos = 0x18
	// Bit mask of REG_UART4_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART4_CLK_SRC_SEL_Msk = 0x3000000
	// Position of REG_UART4_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART4_CLK_EN_Pos = 0x1a
	// Bit mask of REG_UART4_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART4_CLK_EN_Msk = 0x4000000
	// Bit REG_UART4_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL114_REG_UART4_CLK_EN = 0x4000000

	// PERI_CLK_CTRL115: Reserved
	// Position of REG_UART4_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_UART4_SCLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUM_Msk = 0xff
	// Position of REG_UART4_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_UART4_SCLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_UART4_SCLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_UART4_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_UART4_SCLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_UART4_SCLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_UART4_SCLK_DIV_DENOMINATOR_Msk = 0xff0000
	// Position of REG_TWAI0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI0_CLK_SRC_SEL_Pos = 0x18
	// Bit mask of REG_TWAI0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI0_CLK_SRC_SEL_Msk = 0x1000000
	// Bit REG_TWAI0_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI0_CLK_SRC_SEL = 0x1000000
	// Position of REG_TWAI0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI0_CLK_EN_Pos = 0x19
	// Bit mask of REG_TWAI0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI0_CLK_EN_Msk = 0x2000000
	// Bit REG_TWAI0_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI0_CLK_EN = 0x2000000
	// Position of REG_TWAI1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI1_CLK_SRC_SEL_Pos = 0x1a
	// Bit mask of REG_TWAI1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI1_CLK_SRC_SEL_Msk = 0x4000000
	// Bit REG_TWAI1_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI1_CLK_SRC_SEL = 0x4000000
	// Position of REG_TWAI1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI1_CLK_EN_Pos = 0x1b
	// Bit mask of REG_TWAI1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI1_CLK_EN_Msk = 0x8000000
	// Bit REG_TWAI1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI1_CLK_EN = 0x8000000
	// Position of REG_TWAI2_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI2_CLK_SRC_SEL_Pos = 0x1c
	// Bit mask of REG_TWAI2_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI2_CLK_SRC_SEL_Msk = 0x10000000
	// Bit REG_TWAI2_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI2_CLK_SRC_SEL = 0x10000000
	// Position of REG_TWAI2_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI2_CLK_EN_Pos = 0x1d
	// Bit mask of REG_TWAI2_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI2_CLK_EN_Msk = 0x20000000
	// Bit REG_TWAI2_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL115_REG_TWAI2_CLK_EN = 0x20000000

	// PERI_CLK_CTRL116: Reserved
	// Position of REG_GPSPI2_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_CLK_SRC_SEL_Pos = 0x0
	// Bit mask of REG_GPSPI2_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_CLK_SRC_SEL_Msk = 0x7
	// Position of REG_GPSPI2_HS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_EN_Pos = 0x3
	// Bit mask of REG_GPSPI2_HS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_EN_Msk = 0x8
	// Bit REG_GPSPI2_HS_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_EN = 0x8
	// Position of REG_GPSPI2_HS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_DIV_NUM_Pos = 0x4
	// Bit mask of REG_GPSPI2_HS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_HS_CLK_DIV_NUM_Msk = 0xff0
	// Position of REG_GPSPI2_MST_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_DIV_NUM_Pos = 0xc
	// Bit mask of REG_GPSPI2_MST_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_DIV_NUM_Msk = 0xff000
	// Position of REG_GPSPI2_MST_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_EN_Pos = 0x14
	// Bit mask of REG_GPSPI2_MST_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_EN_Msk = 0x100000
	// Bit REG_GPSPI2_MST_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI2_MST_CLK_EN = 0x100000
	// Position of REG_GPSPI3_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI3_CLK_SRC_SEL_Pos = 0x15
	// Bit mask of REG_GPSPI3_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI3_CLK_SRC_SEL_Msk = 0xe00000
	// Position of REG_GPSPI3_HS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI3_HS_CLK_EN_Pos = 0x18
	// Bit mask of REG_GPSPI3_HS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI3_HS_CLK_EN_Msk = 0x1000000
	// Bit REG_GPSPI3_HS_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL116_REG_GPSPI3_HS_CLK_EN = 0x1000000

	// PERI_CLK_CTRL117: Reserved
	// Position of REG_GPSPI3_HS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_GPSPI3_HS_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_GPSPI3_HS_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_GPSPI3_HS_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_GPSPI3_MST_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_DIV_NUM_Pos = 0x8
	// Bit mask of REG_GPSPI3_MST_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_DIV_NUM_Msk = 0xff00
	// Position of REG_GPSPI3_MST_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_EN_Pos = 0x10
	// Bit mask of REG_GPSPI3_MST_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_EN_Msk = 0x10000
	// Bit REG_GPSPI3_MST_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_GPSPI3_MST_CLK_EN = 0x10000
	// Position of REG_PARLIO_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_PARLIO_RX_CLK_SRC_SEL_Pos = 0x11
	// Bit mask of REG_PARLIO_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_PARLIO_RX_CLK_SRC_SEL_Msk = 0x60000
	// Position of REG_PARLIO_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_PARLIO_RX_CLK_EN_Pos = 0x13
	// Bit mask of REG_PARLIO_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_PARLIO_RX_CLK_EN_Msk = 0x80000
	// Bit REG_PARLIO_RX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_PARLIO_RX_CLK_EN = 0x80000
	// Position of REG_PARLIO_RX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_PARLIO_RX_CLK_DIV_NUM_Pos = 0x14
	// Bit mask of REG_PARLIO_RX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL117_REG_PARLIO_RX_CLK_DIV_NUM_Msk = 0xff00000

	// PERI_CLK_CTRL118: Reserved
	// Position of REG_PARLIO_RX_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_NUMERATOR_Pos = 0x0
	// Bit mask of REG_PARLIO_RX_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_NUMERATOR_Msk = 0xff
	// Position of REG_PARLIO_RX_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_Pos = 0x8
	// Bit mask of REG_PARLIO_RX_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_Msk = 0xff00
	// Position of REG_PARLIO_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_TX_CLK_SRC_SEL_Pos = 0x10
	// Bit mask of REG_PARLIO_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_TX_CLK_SRC_SEL_Msk = 0x30000
	// Position of REG_PARLIO_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_TX_CLK_EN_Pos = 0x12
	// Bit mask of REG_PARLIO_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_TX_CLK_EN_Msk = 0x40000
	// Bit REG_PARLIO_TX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_TX_CLK_EN = 0x40000
	// Position of REG_PARLIO_TX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_TX_CLK_DIV_NUM_Pos = 0x13
	// Bit mask of REG_PARLIO_TX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL118_REG_PARLIO_TX_CLK_DIV_NUM_Msk = 0x7f80000

	// PERI_CLK_CTRL119: Reserved
	// Position of REG_PARLIO_TX_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_NUMERATOR_Pos = 0x0
	// Bit mask of REG_PARLIO_TX_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_NUMERATOR_Msk = 0xff
	// Position of REG_PARLIO_TX_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_Pos = 0x8
	// Bit mask of REG_PARLIO_TX_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_Msk = 0xff00
	// Position of REG_I3C_MST_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_I3C_MST_CLK_SRC_SEL_Pos = 0x10
	// Bit mask of REG_I3C_MST_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_I3C_MST_CLK_SRC_SEL_Msk = 0x30000
	// Position of REG_I3C_MST_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_I3C_MST_CLK_EN_Pos = 0x12
	// Bit mask of REG_I3C_MST_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_I3C_MST_CLK_EN_Msk = 0x40000
	// Bit REG_I3C_MST_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_I3C_MST_CLK_EN = 0x40000
	// Position of REG_I3C_MST_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_I3C_MST_CLK_DIV_NUM_Pos = 0x13
	// Bit mask of REG_I3C_MST_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_I3C_MST_CLK_DIV_NUM_Msk = 0x7f80000
	// Position of REG_CAM_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_CAM_CLK_SRC_SEL_Pos = 0x1b
	// Bit mask of REG_CAM_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_CAM_CLK_SRC_SEL_Msk = 0x18000000
	// Position of REG_CAM_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_CAM_CLK_EN_Pos = 0x1d
	// Bit mask of REG_CAM_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_CAM_CLK_EN_Msk = 0x20000000
	// Bit REG_CAM_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL119_REG_CAM_CLK_EN = 0x20000000

	// PERI_CLK_CTRL120: Reserved
	// Position of REG_CAM_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_CAM_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_CAM_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUMERATOR_Pos = 0x8
	// Bit mask of REG_CAM_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL120_REG_CAM_CLK_DIV_NUMERATOR_Msk = 0xff00
	// Position of REG_CAM_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL120_REG_CAM_CLK_DIV_DENOMINATOR_Pos = 0x10
	// Bit mask of REG_CAM_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL120_REG_CAM_CLK_DIV_DENOMINATOR_Msk = 0xff0000

	// PERI_CLK_CTRL20: Reserved
	// Position of REG_MCPWM0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM0_CLK_SRC_SEL_Pos = 0x0
	// Bit mask of REG_MCPWM0_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM0_CLK_SRC_SEL_Msk = 0x3
	// Position of REG_MCPWM0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM0_CLK_EN_Pos = 0x2
	// Bit mask of REG_MCPWM0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM0_CLK_EN_Msk = 0x4
	// Bit REG_MCPWM0_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM0_CLK_EN = 0x4
	// Position of REG_MCPWM0_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM0_CLK_DIV_NUM_Pos = 0x3
	// Bit mask of REG_MCPWM0_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM0_CLK_DIV_NUM_Msk = 0x7f8
	// Position of REG_MCPWM1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM1_CLK_SRC_SEL_Pos = 0xb
	// Bit mask of REG_MCPWM1_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM1_CLK_SRC_SEL_Msk = 0x1800
	// Position of REG_MCPWM1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM1_CLK_EN_Pos = 0xd
	// Bit mask of REG_MCPWM1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM1_CLK_EN_Msk = 0x2000
	// Bit REG_MCPWM1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM1_CLK_EN = 0x2000
	// Position of REG_MCPWM1_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM1_CLK_DIV_NUM_Pos = 0xe
	// Bit mask of REG_MCPWM1_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_MCPWM1_CLK_DIV_NUM_Msk = 0x3fc000
	// Position of REG_TIMERGRP0_T0_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T0_SRC_SEL_Pos = 0x16
	// Bit mask of REG_TIMERGRP0_T0_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T0_SRC_SEL_Msk = 0xc00000
	// Position of REG_TIMERGRP0_T0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T0_CLK_EN_Pos = 0x18
	// Bit mask of REG_TIMERGRP0_T0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T0_CLK_EN_Msk = 0x1000000
	// Bit REG_TIMERGRP0_T0_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T0_CLK_EN = 0x1000000
	// Position of REG_TIMERGRP0_T1_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T1_SRC_SEL_Pos = 0x19
	// Bit mask of REG_TIMERGRP0_T1_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T1_SRC_SEL_Msk = 0x6000000
	// Position of REG_TIMERGRP0_T1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T1_CLK_EN_Pos = 0x1b
	// Bit mask of REG_TIMERGRP0_T1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T1_CLK_EN_Msk = 0x8000000
	// Bit REG_TIMERGRP0_T1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_T1_CLK_EN = 0x8000000
	// Position of REG_TIMERGRP0_WDT_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_WDT_SRC_SEL_Pos = 0x1c
	// Bit mask of REG_TIMERGRP0_WDT_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_WDT_SRC_SEL_Msk = 0x30000000
	// Position of REG_TIMERGRP0_WDT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_WDT_CLK_EN_Pos = 0x1e
	// Bit mask of REG_TIMERGRP0_WDT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_WDT_CLK_EN_Msk = 0x40000000
	// Bit REG_TIMERGRP0_WDT_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_WDT_CLK_EN = 0x40000000
	// Position of REG_TIMERGRP0_TGRT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_TGRT_CLK_EN_Pos = 0x1f
	// Bit mask of REG_TIMERGRP0_TGRT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_TGRT_CLK_EN_Msk = 0x80000000
	// Bit REG_TIMERGRP0_TGRT_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL20_REG_TIMERGRP0_TGRT_CLK_EN = 0x80000000

	// PERI_CLK_CTRL21: Reserved
	// Position of REG_TIMERGRP0_TGRT_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_Pos = 0x0
	// Bit mask of REG_TIMERGRP0_TGRT_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_Msk = 0xf
	// Position of REG_TIMERGRP0_TGRT_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_Pos = 0x4
	// Bit mask of REG_TIMERGRP0_TGRT_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_Msk = 0xffff0
	// Position of REG_TIMERGRP1_T0_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T0_SRC_SEL_Pos = 0x14
	// Bit mask of REG_TIMERGRP1_T0_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T0_SRC_SEL_Msk = 0x300000
	// Position of REG_TIMERGRP1_T0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T0_CLK_EN_Pos = 0x16
	// Bit mask of REG_TIMERGRP1_T0_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T0_CLK_EN_Msk = 0x400000
	// Bit REG_TIMERGRP1_T0_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T0_CLK_EN = 0x400000
	// Position of REG_TIMERGRP1_T1_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T1_SRC_SEL_Pos = 0x17
	// Bit mask of REG_TIMERGRP1_T1_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T1_SRC_SEL_Msk = 0x1800000
	// Position of REG_TIMERGRP1_T1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T1_CLK_EN_Pos = 0x19
	// Bit mask of REG_TIMERGRP1_T1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T1_CLK_EN_Msk = 0x2000000
	// Bit REG_TIMERGRP1_T1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_T1_CLK_EN = 0x2000000
	// Position of REG_TIMERGRP1_WDT_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_WDT_SRC_SEL_Pos = 0x1a
	// Bit mask of REG_TIMERGRP1_WDT_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_WDT_SRC_SEL_Msk = 0xc000000
	// Position of REG_TIMERGRP1_WDT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_WDT_CLK_EN_Pos = 0x1c
	// Bit mask of REG_TIMERGRP1_WDT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_WDT_CLK_EN_Msk = 0x10000000
	// Bit REG_TIMERGRP1_WDT_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_TIMERGRP1_WDT_CLK_EN = 0x10000000
	// Position of REG_SYSTIMER_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_SYSTIMER_CLK_SRC_SEL_Pos = 0x1d
	// Bit mask of REG_SYSTIMER_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_SYSTIMER_CLK_SRC_SEL_Msk = 0x20000000
	// Bit REG_SYSTIMER_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_SYSTIMER_CLK_SRC_SEL = 0x20000000
	// Position of REG_SYSTIMER_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_SYSTIMER_CLK_EN_Pos = 0x1e
	// Bit mask of REG_SYSTIMER_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_SYSTIMER_CLK_EN_Msk = 0x40000000
	// Bit REG_SYSTIMER_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL21_REG_SYSTIMER_CLK_EN = 0x40000000

	// PERI_CLK_CTRL22: Reserved
	// Position of REG_LEDC_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_LEDC_CLK_SRC_SEL_Pos = 0x0
	// Bit mask of REG_LEDC_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_LEDC_CLK_SRC_SEL_Msk = 0x3
	// Position of REG_LEDC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_LEDC_CLK_EN_Pos = 0x2
	// Bit mask of REG_LEDC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_LEDC_CLK_EN_Msk = 0x4
	// Bit REG_LEDC_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_LEDC_CLK_EN = 0x4
	// Position of REG_RMT_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_SRC_SEL_Pos = 0x3
	// Bit mask of REG_RMT_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_SRC_SEL_Msk = 0x18
	// Position of REG_RMT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_EN_Pos = 0x5
	// Bit mask of REG_RMT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_EN_Msk = 0x20
	// Bit REG_RMT_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_EN = 0x20
	// Position of REG_RMT_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUM_Pos = 0x6
	// Bit mask of REG_RMT_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUM_Msk = 0x3fc0
	// Position of REG_RMT_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUMERATOR_Pos = 0xe
	// Bit mask of REG_RMT_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_DIV_NUMERATOR_Msk = 0x3fc000
	// Position of REG_RMT_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_DIV_DENOMINATOR_Pos = 0x16
	// Bit mask of REG_RMT_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_RMT_CLK_DIV_DENOMINATOR_Msk = 0x3fc00000
	// Position of REG_ADC_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_ADC_CLK_SRC_SEL_Pos = 0x1e
	// Bit mask of REG_ADC_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL22_REG_ADC_CLK_SRC_SEL_Msk = 0xc0000000

	// PERI_CLK_CTRL23: Reserved
	// Position of REG_ADC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_EN_Pos = 0x0
	// Bit mask of REG_ADC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_EN_Msk = 0x1
	// Bit REG_ADC_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_EN = 0x1
	// Position of REG_ADC_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUM_Pos = 0x1
	// Bit mask of REG_ADC_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUM_Msk = 0x1fe
	// Position of REG_ADC_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUMERATOR_Pos = 0x9
	// Bit mask of REG_ADC_CLK_DIV_NUMERATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_DIV_NUMERATOR_Msk = 0x1fe00
	// Position of REG_ADC_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_DIV_DENOMINATOR_Pos = 0x11
	// Bit mask of REG_ADC_CLK_DIV_DENOMINATOR field.
	HP_SYS_CLKRST_PERI_CLK_CTRL23_REG_ADC_CLK_DIV_DENOMINATOR_Msk = 0x1fe0000

	// PERI_CLK_CTRL24: Reserved
	// Position of REG_ADC_SAR1_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_ADC_SAR1_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_ADC_SAR1_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_ADC_SAR1_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_ADC_SAR2_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_ADC_SAR2_CLK_DIV_NUM_Pos = 0x8
	// Bit mask of REG_ADC_SAR2_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_ADC_SAR2_CLK_DIV_NUM_Msk = 0xff00
	// Position of REG_PVT_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_PVT_CLK_DIV_NUM_Pos = 0x10
	// Bit mask of REG_PVT_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_PVT_CLK_DIV_NUM_Msk = 0xff0000
	// Position of REG_PVT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_PVT_CLK_EN_Pos = 0x18
	// Bit mask of REG_PVT_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_PVT_CLK_EN_Msk = 0x1000000
	// Bit REG_PVT_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL24_REG_PVT_CLK_EN = 0x1000000

	// PERI_CLK_CTRL25: Reserved
	// Position of REG_PVT_PERI_GROUP_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_PVT_PERI_GROUP_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_PVT_PERI_GROUP1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP1_CLK_EN_Pos = 0x8
	// Bit mask of REG_PVT_PERI_GROUP1_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP1_CLK_EN_Msk = 0x100
	// Bit REG_PVT_PERI_GROUP1_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP1_CLK_EN = 0x100
	// Position of REG_PVT_PERI_GROUP2_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP2_CLK_EN_Pos = 0x9
	// Bit mask of REG_PVT_PERI_GROUP2_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP2_CLK_EN_Msk = 0x200
	// Bit REG_PVT_PERI_GROUP2_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP2_CLK_EN = 0x200
	// Position of REG_PVT_PERI_GROUP3_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP3_CLK_EN_Pos = 0xa
	// Bit mask of REG_PVT_PERI_GROUP3_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP3_CLK_EN_Msk = 0x400
	// Bit REG_PVT_PERI_GROUP3_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP3_CLK_EN = 0x400
	// Position of REG_PVT_PERI_GROUP4_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP4_CLK_EN_Pos = 0xb
	// Bit mask of REG_PVT_PERI_GROUP4_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP4_CLK_EN_Msk = 0x800
	// Bit REG_PVT_PERI_GROUP4_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_PVT_PERI_GROUP4_CLK_EN = 0x800
	// Position of REG_CRYPTO_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_CLK_SRC_SEL_Pos = 0xc
	// Bit mask of REG_CRYPTO_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_CLK_SRC_SEL_Msk = 0x3000
	// Position of REG_CRYPTO_AES_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_AES_CLK_EN_Pos = 0xe
	// Bit mask of REG_CRYPTO_AES_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_AES_CLK_EN_Msk = 0x4000
	// Bit REG_CRYPTO_AES_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_AES_CLK_EN = 0x4000
	// Position of REG_CRYPTO_DS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_DS_CLK_EN_Pos = 0xf
	// Bit mask of REG_CRYPTO_DS_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_DS_CLK_EN_Msk = 0x8000
	// Bit REG_CRYPTO_DS_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_DS_CLK_EN = 0x8000
	// Position of REG_CRYPTO_ECC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_ECC_CLK_EN_Pos = 0x10
	// Bit mask of REG_CRYPTO_ECC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_ECC_CLK_EN_Msk = 0x10000
	// Bit REG_CRYPTO_ECC_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_ECC_CLK_EN = 0x10000
	// Position of REG_CRYPTO_HMAC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_HMAC_CLK_EN_Pos = 0x11
	// Bit mask of REG_CRYPTO_HMAC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_HMAC_CLK_EN_Msk = 0x20000
	// Bit REG_CRYPTO_HMAC_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_HMAC_CLK_EN = 0x20000
	// Position of REG_CRYPTO_RSA_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_RSA_CLK_EN_Pos = 0x12
	// Bit mask of REG_CRYPTO_RSA_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_RSA_CLK_EN_Msk = 0x40000
	// Bit REG_CRYPTO_RSA_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_RSA_CLK_EN = 0x40000
	// Position of REG_CRYPTO_SEC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_SEC_CLK_EN_Pos = 0x13
	// Bit mask of REG_CRYPTO_SEC_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_SEC_CLK_EN_Msk = 0x80000
	// Bit REG_CRYPTO_SEC_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_SEC_CLK_EN = 0x80000
	// Position of REG_CRYPTO_SHA_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_SHA_CLK_EN_Pos = 0x14
	// Bit mask of REG_CRYPTO_SHA_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_SHA_CLK_EN_Msk = 0x100000
	// Bit REG_CRYPTO_SHA_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_SHA_CLK_EN = 0x100000
	// Position of REG_CRYPTO_ECDSA_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_ECDSA_CLK_EN_Pos = 0x15
	// Bit mask of REG_CRYPTO_ECDSA_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_ECDSA_CLK_EN_Msk = 0x200000
	// Bit REG_CRYPTO_ECDSA_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_ECDSA_CLK_EN = 0x200000
	// Position of REG_CRYPTO_KM_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_KM_CLK_EN_Pos = 0x16
	// Bit mask of REG_CRYPTO_KM_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_KM_CLK_EN_Msk = 0x400000
	// Bit REG_CRYPTO_KM_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_CRYPTO_KM_CLK_EN = 0x400000
	// Position of REG_ISP_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_ISP_CLK_SRC_SEL_Pos = 0x17
	// Bit mask of REG_ISP_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_ISP_CLK_SRC_SEL_Msk = 0x1800000
	// Position of REG_ISP_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_ISP_CLK_EN_Pos = 0x19
	// Bit mask of REG_ISP_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_ISP_CLK_EN_Msk = 0x2000000
	// Bit REG_ISP_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL25_REG_ISP_CLK_EN = 0x2000000

	// PERI_CLK_CTRL26: Reserved
	// Position of REG_ISP_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_ISP_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_ISP_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_ISP_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_IOMUX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_SRC_SEL_Pos = 0x8
	// Bit mask of REG_IOMUX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_SRC_SEL_Msk = 0x100
	// Bit REG_IOMUX_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_SRC_SEL = 0x100
	// Position of REG_IOMUX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_EN_Pos = 0x9
	// Bit mask of REG_IOMUX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_EN_Msk = 0x200
	// Bit REG_IOMUX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_EN = 0x200
	// Position of REG_IOMUX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_DIV_NUM_Pos = 0xa
	// Bit mask of REG_IOMUX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_IOMUX_CLK_DIV_NUM_Msk = 0x3fc00
	// Position of REG_H264_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_SRC_SEL_Pos = 0x12
	// Bit mask of REG_H264_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_SRC_SEL_Msk = 0x40000
	// Bit REG_H264_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_SRC_SEL = 0x40000
	// Position of REG_H264_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_EN_Pos = 0x13
	// Bit mask of REG_H264_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_EN_Msk = 0x80000
	// Bit REG_H264_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_EN = 0x80000
	// Position of REG_H264_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_DIV_NUM_Pos = 0x14
	// Bit mask of REG_H264_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_H264_CLK_DIV_NUM_Msk = 0xff00000
	// Position of REG_PADBIST_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_PADBIST_RX_CLK_SRC_SEL_Pos = 0x1c
	// Bit mask of REG_PADBIST_RX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_PADBIST_RX_CLK_SRC_SEL_Msk = 0x10000000
	// Bit REG_PADBIST_RX_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_PADBIST_RX_CLK_SRC_SEL = 0x10000000
	// Position of REG_PADBIST_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_PADBIST_RX_CLK_EN_Pos = 0x1d
	// Bit mask of REG_PADBIST_RX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_PADBIST_RX_CLK_EN_Msk = 0x20000000
	// Bit REG_PADBIST_RX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL26_REG_PADBIST_RX_CLK_EN = 0x20000000

	// PERI_CLK_CTRL27: Reserved
	// Position of REG_PADBIST_RX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_RX_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of REG_PADBIST_RX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_RX_CLK_DIV_NUM_Msk = 0xff
	// Position of REG_PADBIST_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_SRC_SEL_Pos = 0x8
	// Bit mask of REG_PADBIST_TX_CLK_SRC_SEL field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_SRC_SEL_Msk = 0x100
	// Bit REG_PADBIST_TX_CLK_SRC_SEL.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_SRC_SEL = 0x100
	// Position of REG_PADBIST_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_EN_Pos = 0x9
	// Bit mask of REG_PADBIST_TX_CLK_EN field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_EN_Msk = 0x200
	// Bit REG_PADBIST_TX_CLK_EN.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_EN = 0x200
	// Position of REG_PADBIST_TX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_DIV_NUM_Pos = 0xa
	// Bit mask of REG_PADBIST_TX_CLK_DIV_NUM field.
	HP_SYS_CLKRST_PERI_CLK_CTRL27_REG_PADBIST_TX_CLK_DIV_NUM_Msk = 0x3fc00

	// CLK_FORCE_ON_CTRL0: Reserved
	// Position of REG_CPUICM_GATED_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_CPUICM_GATED_CLK_FORCE_ON_Pos = 0x0
	// Bit mask of REG_CPUICM_GATED_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_CPUICM_GATED_CLK_FORCE_ON_Msk = 0x1
	// Bit REG_CPUICM_GATED_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_CPUICM_GATED_CLK_FORCE_ON = 0x1
	// Position of REG_TCM_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TCM_CPU_CLK_FORCE_ON_Pos = 0x1
	// Bit mask of REG_TCM_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TCM_CPU_CLK_FORCE_ON_Msk = 0x2
	// Bit REG_TCM_CPU_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TCM_CPU_CLK_FORCE_ON = 0x2
	// Position of REG_BUSMON_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_BUSMON_CPU_CLK_FORCE_ON_Pos = 0x2
	// Bit mask of REG_BUSMON_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_BUSMON_CPU_CLK_FORCE_ON_Msk = 0x4
	// Bit REG_BUSMON_CPU_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_BUSMON_CPU_CLK_FORCE_ON = 0x4
	// Position of REG_L1CACHE_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_CPU_CLK_FORCE_ON_Pos = 0x3
	// Bit mask of REG_L1CACHE_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_CPU_CLK_FORCE_ON_Msk = 0x8
	// Bit REG_L1CACHE_CPU_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_CPU_CLK_FORCE_ON = 0x8
	// Position of REG_L1CACHE_D_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_D_CPU_CLK_FORCE_ON_Pos = 0x4
	// Bit mask of REG_L1CACHE_D_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_D_CPU_CLK_FORCE_ON_Msk = 0x10
	// Bit REG_L1CACHE_D_CPU_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_D_CPU_CLK_FORCE_ON = 0x10
	// Position of REG_L1CACHE_I0_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_Pos = 0x5
	// Bit mask of REG_L1CACHE_I0_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_Msk = 0x20
	// Bit REG_L1CACHE_I0_CPU_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_CPU_CLK_FORCE_ON = 0x20
	// Position of REG_L1CACHE_I1_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_Pos = 0x6
	// Bit mask of REG_L1CACHE_I1_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_Msk = 0x40
	// Bit REG_L1CACHE_I1_CPU_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_CPU_CLK_FORCE_ON = 0x40
	// Position of REG_TRACE_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TRACE_CPU_CLK_FORCE_ON_Pos = 0x7
	// Bit mask of REG_TRACE_CPU_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TRACE_CPU_CLK_FORCE_ON_Msk = 0x80
	// Bit REG_TRACE_CPU_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TRACE_CPU_CLK_FORCE_ON = 0x80
	// Position of REG_TRACE_SYS_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TRACE_SYS_CLK_FORCE_ON_Pos = 0x8
	// Bit mask of REG_TRACE_SYS_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TRACE_SYS_CLK_FORCE_ON_Msk = 0x100
	// Bit REG_TRACE_SYS_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_TRACE_SYS_CLK_FORCE_ON = 0x100
	// Position of REG_L1CACHE_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_MEM_CLK_FORCE_ON_Pos = 0x9
	// Bit mask of REG_L1CACHE_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_MEM_CLK_FORCE_ON_Msk = 0x200
	// Bit REG_L1CACHE_MEM_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_MEM_CLK_FORCE_ON = 0x200
	// Position of REG_L1CACHE_D_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_D_MEM_CLK_FORCE_ON_Pos = 0xa
	// Bit mask of REG_L1CACHE_D_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_D_MEM_CLK_FORCE_ON_Msk = 0x400
	// Bit REG_L1CACHE_D_MEM_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_D_MEM_CLK_FORCE_ON = 0x400
	// Position of REG_L1CACHE_I0_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_Pos = 0xb
	// Bit mask of REG_L1CACHE_I0_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_Msk = 0x800
	// Bit REG_L1CACHE_I0_MEM_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I0_MEM_CLK_FORCE_ON = 0x800
	// Position of REG_L1CACHE_I1_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_Pos = 0xc
	// Bit mask of REG_L1CACHE_I1_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_Msk = 0x1000
	// Bit REG_L1CACHE_I1_MEM_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L1CACHE_I1_MEM_CLK_FORCE_ON = 0x1000
	// Position of REG_L2CACHE_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L2CACHE_MEM_CLK_FORCE_ON_Pos = 0xd
	// Bit mask of REG_L2CACHE_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L2CACHE_MEM_CLK_FORCE_ON_Msk = 0x2000
	// Bit REG_L2CACHE_MEM_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L2CACHE_MEM_CLK_FORCE_ON = 0x2000
	// Position of REG_L2MEM_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L2MEM_MEM_CLK_FORCE_ON_Pos = 0xe
	// Bit mask of REG_L2MEM_MEM_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L2MEM_MEM_CLK_FORCE_ON_Msk = 0x4000
	// Bit REG_L2MEM_MEM_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_L2MEM_MEM_CLK_FORCE_ON = 0x4000
	// Position of REG_SAR1_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_SAR1_CLK_FORCE_ON_Pos = 0xf
	// Bit mask of REG_SAR1_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_SAR1_CLK_FORCE_ON_Msk = 0x8000
	// Bit REG_SAR1_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_SAR1_CLK_FORCE_ON = 0x8000
	// Position of REG_SAR2_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_SAR2_CLK_FORCE_ON_Pos = 0x10
	// Bit mask of REG_SAR2_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_SAR2_CLK_FORCE_ON_Msk = 0x10000
	// Bit REG_SAR2_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_SAR2_CLK_FORCE_ON = 0x10000
	// Position of REG_GMAC_TX_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_GMAC_TX_CLK_FORCE_ON_Pos = 0x11
	// Bit mask of REG_GMAC_TX_CLK_FORCE_ON field.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_GMAC_TX_CLK_FORCE_ON_Msk = 0x20000
	// Bit REG_GMAC_TX_CLK_FORCE_ON.
	HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG_GMAC_TX_CLK_FORCE_ON = 0x20000

	// DPA_CTRL0: Reserved
	// Position of REG_SEC_DPA_LEVEL field.
	HP_SYS_CLKRST_DPA_CTRL0_REG_SEC_DPA_LEVEL_Pos = 0x0
	// Bit mask of REG_SEC_DPA_LEVEL field.
	HP_SYS_CLKRST_DPA_CTRL0_REG_SEC_DPA_LEVEL_Msk = 0x3
	// Position of REG_SEC_DPA_CFG_SEL field.
	HP_SYS_CLKRST_DPA_CTRL0_REG_SEC_DPA_CFG_SEL_Pos = 0x2
	// Bit mask of REG_SEC_DPA_CFG_SEL field.
	HP_SYS_CLKRST_DPA_CTRL0_REG_SEC_DPA_CFG_SEL_Msk = 0x4
	// Bit REG_SEC_DPA_CFG_SEL.
	HP_SYS_CLKRST_DPA_CTRL0_REG_SEC_DPA_CFG_SEL = 0x4

	// ANA_PLL_CTRL0: Reserved
	// Position of REG_PLLA_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_PLLA_CAL_END_Pos = 0x0
	// Bit mask of REG_PLLA_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_PLLA_CAL_END_Msk = 0x1
	// Bit REG_PLLA_CAL_END.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_PLLA_CAL_END = 0x1
	// Position of REG_PLLA_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_PLLA_CAL_STOP_Pos = 0x1
	// Bit mask of REG_PLLA_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_PLLA_CAL_STOP_Msk = 0x2
	// Bit REG_PLLA_CAL_STOP.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_PLLA_CAL_STOP = 0x2
	// Position of REG_CPU_PLL_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_CPU_PLL_CAL_END_Pos = 0x2
	// Bit mask of REG_CPU_PLL_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_CPU_PLL_CAL_END_Msk = 0x4
	// Bit REG_CPU_PLL_CAL_END.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_CPU_PLL_CAL_END = 0x4
	// Position of REG_CPU_PLL_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_CPU_PLL_CAL_STOP_Pos = 0x3
	// Bit mask of REG_CPU_PLL_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_CPU_PLL_CAL_STOP_Msk = 0x8
	// Bit REG_CPU_PLL_CAL_STOP.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_CPU_PLL_CAL_STOP = 0x8
	// Position of REG_SDIO_PLL_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SDIO_PLL_CAL_END_Pos = 0x4
	// Bit mask of REG_SDIO_PLL_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SDIO_PLL_CAL_END_Msk = 0x10
	// Bit REG_SDIO_PLL_CAL_END.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SDIO_PLL_CAL_END = 0x10
	// Position of REG_SDIO_PLL_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SDIO_PLL_CAL_STOP_Pos = 0x5
	// Bit mask of REG_SDIO_PLL_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SDIO_PLL_CAL_STOP_Msk = 0x20
	// Bit REG_SDIO_PLL_CAL_STOP.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SDIO_PLL_CAL_STOP = 0x20
	// Position of REG_SYS_PLL_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SYS_PLL_CAL_END_Pos = 0x6
	// Bit mask of REG_SYS_PLL_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SYS_PLL_CAL_END_Msk = 0x40
	// Bit REG_SYS_PLL_CAL_END.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SYS_PLL_CAL_END = 0x40
	// Position of REG_SYS_PLL_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SYS_PLL_CAL_STOP_Pos = 0x7
	// Bit mask of REG_SYS_PLL_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SYS_PLL_CAL_STOP_Msk = 0x80
	// Bit REG_SYS_PLL_CAL_STOP.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_SYS_PLL_CAL_STOP = 0x80
	// Position of REG_MSPI_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_MSPI_CAL_END_Pos = 0x8
	// Bit mask of REG_MSPI_CAL_END field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_MSPI_CAL_END_Msk = 0x100
	// Bit REG_MSPI_CAL_END.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_MSPI_CAL_END = 0x100
	// Position of REG_MSPI_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_MSPI_CAL_STOP_Pos = 0x9
	// Bit mask of REG_MSPI_CAL_STOP field.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_MSPI_CAL_STOP_Msk = 0x200
	// Bit REG_MSPI_CAL_STOP.
	HP_SYS_CLKRST_ANA_PLL_CTRL0_REG_MSPI_CAL_STOP = 0x200

	// HP_RST_EN0: Reserved
	// Position of REG_RST_EN_CORECTRL field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORECTRL_Pos = 0x0
	// Bit mask of REG_RST_EN_CORECTRL field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORECTRL_Msk = 0x1
	// Bit REG_RST_EN_CORECTRL.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORECTRL = 0x1
	// Position of REG_RST_EN_PVT_TOP field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_TOP_Pos = 0x1
	// Bit mask of REG_RST_EN_PVT_TOP field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_TOP_Msk = 0x2
	// Bit REG_RST_EN_PVT_TOP.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_TOP = 0x2
	// Position of REG_RST_EN_PVT_PERI_GROUP1 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP1_Pos = 0x2
	// Bit mask of REG_RST_EN_PVT_PERI_GROUP1 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP1_Msk = 0x4
	// Bit REG_RST_EN_PVT_PERI_GROUP1.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP1 = 0x4
	// Position of REG_RST_EN_PVT_PERI_GROUP2 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP2_Pos = 0x3
	// Bit mask of REG_RST_EN_PVT_PERI_GROUP2 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP2_Msk = 0x8
	// Bit REG_RST_EN_PVT_PERI_GROUP2.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP2 = 0x8
	// Position of REG_RST_EN_PVT_PERI_GROUP3 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP3_Pos = 0x4
	// Bit mask of REG_RST_EN_PVT_PERI_GROUP3 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP3_Msk = 0x10
	// Bit REG_RST_EN_PVT_PERI_GROUP3.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP3 = 0x10
	// Position of REG_RST_EN_PVT_PERI_GROUP4 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP4_Pos = 0x5
	// Bit mask of REG_RST_EN_PVT_PERI_GROUP4 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP4_Msk = 0x20
	// Bit REG_RST_EN_PVT_PERI_GROUP4.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_PERI_GROUP4 = 0x20
	// Position of REG_RST_EN_REGDMA field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_REGDMA_Pos = 0x6
	// Bit mask of REG_RST_EN_REGDMA field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_REGDMA_Msk = 0x40
	// Bit REG_RST_EN_REGDMA.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_REGDMA = 0x40
	// Position of REG_RST_EN_CORE0_GLOBAL field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORE0_GLOBAL_Pos = 0x7
	// Bit mask of REG_RST_EN_CORE0_GLOBAL field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORE0_GLOBAL_Msk = 0x80
	// Bit REG_RST_EN_CORE0_GLOBAL.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORE0_GLOBAL = 0x80
	// Position of REG_RST_EN_CORE1_GLOBAL field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORE1_GLOBAL_Pos = 0x8
	// Bit mask of REG_RST_EN_CORE1_GLOBAL field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORE1_GLOBAL_Msk = 0x100
	// Bit REG_RST_EN_CORE1_GLOBAL.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORE1_GLOBAL = 0x100
	// Position of REG_RST_EN_CORETRACE0 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORETRACE0_Pos = 0x9
	// Bit mask of REG_RST_EN_CORETRACE0 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORETRACE0_Msk = 0x200
	// Bit REG_RST_EN_CORETRACE0.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORETRACE0 = 0x200
	// Position of REG_RST_EN_CORETRACE1 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORETRACE1_Pos = 0xa
	// Bit mask of REG_RST_EN_CORETRACE1 field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORETRACE1_Msk = 0x400
	// Bit REG_RST_EN_CORETRACE1.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CORETRACE1 = 0x400
	// Position of REG_RST_EN_HP_TCM field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_HP_TCM_Pos = 0xb
	// Bit mask of REG_RST_EN_HP_TCM field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_HP_TCM_Msk = 0x800
	// Bit REG_RST_EN_HP_TCM.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_HP_TCM = 0x800
	// Position of REG_RST_EN_HP_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_HP_CACHE_Pos = 0xc
	// Bit mask of REG_RST_EN_HP_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_HP_CACHE_Msk = 0x1000
	// Bit REG_RST_EN_HP_CACHE.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_HP_CACHE = 0x1000
	// Position of REG_RST_EN_L1_I0_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_I0_CACHE_Pos = 0xd
	// Bit mask of REG_RST_EN_L1_I0_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_I0_CACHE_Msk = 0x2000
	// Bit REG_RST_EN_L1_I0_CACHE.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_I0_CACHE = 0x2000
	// Position of REG_RST_EN_L1_I1_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_I1_CACHE_Pos = 0xe
	// Bit mask of REG_RST_EN_L1_I1_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_I1_CACHE_Msk = 0x4000
	// Bit REG_RST_EN_L1_I1_CACHE.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_I1_CACHE = 0x4000
	// Position of REG_RST_EN_L1_D_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_D_CACHE_Pos = 0xf
	// Bit mask of REG_RST_EN_L1_D_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_D_CACHE_Msk = 0x8000
	// Bit REG_RST_EN_L1_D_CACHE.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L1_D_CACHE = 0x8000
	// Position of REG_RST_EN_L2_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2_CACHE_Pos = 0x10
	// Bit mask of REG_RST_EN_L2_CACHE field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2_CACHE_Msk = 0x10000
	// Bit REG_RST_EN_L2_CACHE.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2_CACHE = 0x10000
	// Position of REG_RST_EN_L2_MEM field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2_MEM_Pos = 0x11
	// Bit mask of REG_RST_EN_L2_MEM field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2_MEM_Msk = 0x20000
	// Bit REG_RST_EN_L2_MEM.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2_MEM = 0x20000
	// Position of REG_RST_EN_L2MEMMON field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2MEMMON_Pos = 0x12
	// Bit mask of REG_RST_EN_L2MEMMON field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2MEMMON_Msk = 0x40000
	// Bit REG_RST_EN_L2MEMMON.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_L2MEMMON = 0x40000
	// Position of REG_RST_EN_TCMMON field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_TCMMON_Pos = 0x13
	// Bit mask of REG_RST_EN_TCMMON field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_TCMMON_Msk = 0x80000
	// Bit REG_RST_EN_TCMMON.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_TCMMON = 0x80000
	// Position of REG_RST_EN_PVT_APB field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_APB_Pos = 0x14
	// Bit mask of REG_RST_EN_PVT_APB field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_APB_Msk = 0x100000
	// Bit REG_RST_EN_PVT_APB.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_PVT_APB = 0x100000
	// Position of REG_RST_EN_GDMA field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_GDMA_Pos = 0x15
	// Bit mask of REG_RST_EN_GDMA field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_GDMA_Msk = 0x200000
	// Bit REG_RST_EN_GDMA.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_GDMA = 0x200000
	// Position of REG_RST_EN_MSPI_AXI field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_MSPI_AXI_Pos = 0x16
	// Bit mask of REG_RST_EN_MSPI_AXI field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_MSPI_AXI_Msk = 0x400000
	// Bit REG_RST_EN_MSPI_AXI.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_MSPI_AXI = 0x400000
	// Position of REG_RST_EN_DUAL_MSPI_AXI field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DUAL_MSPI_AXI_Pos = 0x17
	// Bit mask of REG_RST_EN_DUAL_MSPI_AXI field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DUAL_MSPI_AXI_Msk = 0x800000
	// Bit REG_RST_EN_DUAL_MSPI_AXI.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DUAL_MSPI_AXI = 0x800000
	// Position of REG_RST_EN_MSPI_APB field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_MSPI_APB_Pos = 0x18
	// Bit mask of REG_RST_EN_MSPI_APB field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_MSPI_APB_Msk = 0x1000000
	// Bit REG_RST_EN_MSPI_APB.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_MSPI_APB = 0x1000000
	// Position of REG_RST_EN_DUAL_MSPI_APB field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DUAL_MSPI_APB_Pos = 0x19
	// Bit mask of REG_RST_EN_DUAL_MSPI_APB field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DUAL_MSPI_APB_Msk = 0x2000000
	// Bit REG_RST_EN_DUAL_MSPI_APB.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DUAL_MSPI_APB = 0x2000000
	// Position of REG_RST_EN_DSI_BRG field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DSI_BRG_Pos = 0x1a
	// Bit mask of REG_RST_EN_DSI_BRG field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DSI_BRG_Msk = 0x4000000
	// Bit REG_RST_EN_DSI_BRG.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DSI_BRG = 0x4000000
	// Position of REG_RST_EN_CSI_HOST field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CSI_HOST_Pos = 0x1b
	// Bit mask of REG_RST_EN_CSI_HOST field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CSI_HOST_Msk = 0x8000000
	// Bit REG_RST_EN_CSI_HOST.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CSI_HOST = 0x8000000
	// Position of REG_RST_EN_CSI_BRG field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CSI_BRG_Pos = 0x1c
	// Bit mask of REG_RST_EN_CSI_BRG field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CSI_BRG_Msk = 0x10000000
	// Bit REG_RST_EN_CSI_BRG.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_CSI_BRG = 0x10000000
	// Position of REG_RST_EN_ISP field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_ISP_Pos = 0x1d
	// Bit mask of REG_RST_EN_ISP field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_ISP_Msk = 0x20000000
	// Bit REG_RST_EN_ISP.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_ISP = 0x20000000
	// Position of REG_RST_EN_JPEG field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_JPEG_Pos = 0x1e
	// Bit mask of REG_RST_EN_JPEG field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_JPEG_Msk = 0x40000000
	// Bit REG_RST_EN_JPEG.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_JPEG = 0x40000000
	// Position of REG_RST_EN_DMA2D field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DMA2D_Pos = 0x1f
	// Bit mask of REG_RST_EN_DMA2D field.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DMA2D_Msk = 0x80000000
	// Bit REG_RST_EN_DMA2D.
	HP_SYS_CLKRST_HP_RST_EN0_REG_RST_EN_DMA2D = 0x80000000

	// HP_RST_EN1: Reserved
	// Position of REG_RST_EN_PPA field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PPA_Pos = 0x0
	// Bit mask of REG_RST_EN_PPA field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PPA_Msk = 0x1
	// Bit REG_RST_EN_PPA.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PPA = 0x1
	// Position of REG_RST_EN_AHB_PDMA field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_AHB_PDMA_Pos = 0x1
	// Bit mask of REG_RST_EN_AHB_PDMA field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_AHB_PDMA_Msk = 0x2
	// Bit REG_RST_EN_AHB_PDMA.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_AHB_PDMA = 0x2
	// Position of REG_RST_EN_AXI_PDMA field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_AXI_PDMA_Pos = 0x2
	// Bit mask of REG_RST_EN_AXI_PDMA field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_AXI_PDMA_Msk = 0x4
	// Bit REG_RST_EN_AXI_PDMA.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_AXI_PDMA = 0x4
	// Position of REG_RST_EN_IOMUX field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_IOMUX_Pos = 0x3
	// Bit mask of REG_RST_EN_IOMUX field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_IOMUX_Msk = 0x8
	// Bit REG_RST_EN_IOMUX.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_IOMUX = 0x8
	// Position of REG_RST_EN_PADBIST field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PADBIST_Pos = 0x4
	// Bit mask of REG_RST_EN_PADBIST field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PADBIST_Msk = 0x10
	// Bit REG_RST_EN_PADBIST.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PADBIST = 0x10
	// Position of REG_RST_EN_STIMER field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_STIMER_Pos = 0x5
	// Bit mask of REG_RST_EN_STIMER field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_STIMER_Msk = 0x20
	// Bit REG_RST_EN_STIMER.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_STIMER = 0x20
	// Position of REG_RST_EN_TIMERGRP0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_TIMERGRP0_Pos = 0x6
	// Bit mask of REG_RST_EN_TIMERGRP0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_TIMERGRP0_Msk = 0x40
	// Bit REG_RST_EN_TIMERGRP0.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_TIMERGRP0 = 0x40
	// Position of REG_RST_EN_TIMERGRP1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_TIMERGRP1_Pos = 0x7
	// Bit mask of REG_RST_EN_TIMERGRP1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_TIMERGRP1_Msk = 0x80
	// Bit REG_RST_EN_TIMERGRP1.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_TIMERGRP1 = 0x80
	// Position of REG_RST_EN_UART0_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART0_CORE_Pos = 0x8
	// Bit mask of REG_RST_EN_UART0_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART0_CORE_Msk = 0x100
	// Bit REG_RST_EN_UART0_CORE.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART0_CORE = 0x100
	// Position of REG_RST_EN_UART1_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART1_CORE_Pos = 0x9
	// Bit mask of REG_RST_EN_UART1_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART1_CORE_Msk = 0x200
	// Bit REG_RST_EN_UART1_CORE.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART1_CORE = 0x200
	// Position of REG_RST_EN_UART2_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART2_CORE_Pos = 0xa
	// Bit mask of REG_RST_EN_UART2_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART2_CORE_Msk = 0x400
	// Bit REG_RST_EN_UART2_CORE.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART2_CORE = 0x400
	// Position of REG_RST_EN_UART3_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART3_CORE_Pos = 0xb
	// Bit mask of REG_RST_EN_UART3_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART3_CORE_Msk = 0x800
	// Bit REG_RST_EN_UART3_CORE.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART3_CORE = 0x800
	// Position of REG_RST_EN_UART4_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART4_CORE_Pos = 0xc
	// Bit mask of REG_RST_EN_UART4_CORE field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART4_CORE_Msk = 0x1000
	// Bit REG_RST_EN_UART4_CORE.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART4_CORE = 0x1000
	// Position of REG_RST_EN_UART0_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART0_APB_Pos = 0xd
	// Bit mask of REG_RST_EN_UART0_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART0_APB_Msk = 0x2000
	// Bit REG_RST_EN_UART0_APB.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART0_APB = 0x2000
	// Position of REG_RST_EN_UART1_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART1_APB_Pos = 0xe
	// Bit mask of REG_RST_EN_UART1_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART1_APB_Msk = 0x4000
	// Bit REG_RST_EN_UART1_APB.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART1_APB = 0x4000
	// Position of REG_RST_EN_UART2_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART2_APB_Pos = 0xf
	// Bit mask of REG_RST_EN_UART2_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART2_APB_Msk = 0x8000
	// Bit REG_RST_EN_UART2_APB.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART2_APB = 0x8000
	// Position of REG_RST_EN_UART3_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART3_APB_Pos = 0x10
	// Bit mask of REG_RST_EN_UART3_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART3_APB_Msk = 0x10000
	// Bit REG_RST_EN_UART3_APB.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART3_APB = 0x10000
	// Position of REG_RST_EN_UART4_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART4_APB_Pos = 0x11
	// Bit mask of REG_RST_EN_UART4_APB field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART4_APB_Msk = 0x20000
	// Bit REG_RST_EN_UART4_APB.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UART4_APB = 0x20000
	// Position of REG_RST_EN_UHCI field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UHCI_Pos = 0x12
	// Bit mask of REG_RST_EN_UHCI field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UHCI_Msk = 0x40000
	// Bit REG_RST_EN_UHCI.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_UHCI = 0x40000
	// Position of REG_RST_EN_I3CMST field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I3CMST_Pos = 0x13
	// Bit mask of REG_RST_EN_I3CMST field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I3CMST_Msk = 0x80000
	// Bit REG_RST_EN_I3CMST.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I3CMST = 0x80000
	// Position of REG_RST_EN_I3CSLV field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I3CSLV_Pos = 0x14
	// Bit mask of REG_RST_EN_I3CSLV field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I3CSLV_Msk = 0x100000
	// Bit REG_RST_EN_I3CSLV.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I3CSLV = 0x100000
	// Position of REG_RST_EN_I2C1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I2C1_Pos = 0x15
	// Bit mask of REG_RST_EN_I2C1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I2C1_Msk = 0x200000
	// Bit REG_RST_EN_I2C1.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I2C1 = 0x200000
	// Position of REG_RST_EN_I2C0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I2C0_Pos = 0x16
	// Bit mask of REG_RST_EN_I2C0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I2C0_Msk = 0x400000
	// Bit REG_RST_EN_I2C0.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_I2C0 = 0x400000
	// Position of REG_RST_EN_RMT field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_RMT_Pos = 0x17
	// Bit mask of REG_RST_EN_RMT field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_RMT_Msk = 0x800000
	// Bit REG_RST_EN_RMT.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_RMT = 0x800000
	// Position of REG_RST_EN_PWM0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PWM0_Pos = 0x18
	// Bit mask of REG_RST_EN_PWM0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PWM0_Msk = 0x1000000
	// Bit REG_RST_EN_PWM0.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PWM0 = 0x1000000
	// Position of REG_RST_EN_PWM1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PWM1_Pos = 0x19
	// Bit mask of REG_RST_EN_PWM1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PWM1_Msk = 0x2000000
	// Bit REG_RST_EN_PWM1.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PWM1 = 0x2000000
	// Position of REG_RST_EN_CAN0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN0_Pos = 0x1a
	// Bit mask of REG_RST_EN_CAN0 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN0_Msk = 0x4000000
	// Bit REG_RST_EN_CAN0.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN0 = 0x4000000
	// Position of REG_RST_EN_CAN1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN1_Pos = 0x1b
	// Bit mask of REG_RST_EN_CAN1 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN1_Msk = 0x8000000
	// Bit REG_RST_EN_CAN1.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN1 = 0x8000000
	// Position of REG_RST_EN_CAN2 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN2_Pos = 0x1c
	// Bit mask of REG_RST_EN_CAN2 field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN2_Msk = 0x10000000
	// Bit REG_RST_EN_CAN2.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_CAN2 = 0x10000000
	// Position of REG_RST_EN_LEDC field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_LEDC_Pos = 0x1d
	// Bit mask of REG_RST_EN_LEDC field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_LEDC_Msk = 0x20000000
	// Bit REG_RST_EN_LEDC.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_LEDC = 0x20000000
	// Position of REG_RST_EN_PCNT field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PCNT_Pos = 0x1e
	// Bit mask of REG_RST_EN_PCNT field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PCNT_Msk = 0x40000000
	// Bit REG_RST_EN_PCNT.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_PCNT = 0x40000000
	// Position of REG_RST_EN_ETM field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_ETM_Pos = 0x1f
	// Bit mask of REG_RST_EN_ETM field.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_ETM_Msk = 0x80000000
	// Bit REG_RST_EN_ETM.
	HP_SYS_CLKRST_HP_RST_EN1_REG_RST_EN_ETM = 0x80000000

	// HP_RST_EN2: Reserved
	// Position of REG_RST_EN_INTRMTX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_INTRMTX_Pos = 0x0
	// Bit mask of REG_RST_EN_INTRMTX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_INTRMTX_Msk = 0x1
	// Bit REG_RST_EN_INTRMTX.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_INTRMTX = 0x1
	// Position of REG_RST_EN_PARLIO field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_Pos = 0x1
	// Bit mask of REG_RST_EN_PARLIO field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_Msk = 0x2
	// Bit REG_RST_EN_PARLIO.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO = 0x2
	// Position of REG_RST_EN_PARLIO_RX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_RX_Pos = 0x2
	// Bit mask of REG_RST_EN_PARLIO_RX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_RX_Msk = 0x4
	// Bit REG_RST_EN_PARLIO_RX.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_RX = 0x4
	// Position of REG_RST_EN_PARLIO_TX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_TX_Pos = 0x3
	// Bit mask of REG_RST_EN_PARLIO_TX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_TX_Msk = 0x8
	// Bit REG_RST_EN_PARLIO_TX.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_PARLIO_TX = 0x8
	// Position of REG_RST_EN_I2S0_APB field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S0_APB_Pos = 0x4
	// Bit mask of REG_RST_EN_I2S0_APB field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S0_APB_Msk = 0x10
	// Bit REG_RST_EN_I2S0_APB.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S0_APB = 0x10
	// Position of REG_RST_EN_I2S1_APB field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S1_APB_Pos = 0x5
	// Bit mask of REG_RST_EN_I2S1_APB field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S1_APB_Msk = 0x20
	// Bit REG_RST_EN_I2S1_APB.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S1_APB = 0x20
	// Position of REG_RST_EN_I2S2_APB field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S2_APB_Pos = 0x6
	// Bit mask of REG_RST_EN_I2S2_APB field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S2_APB_Msk = 0x40
	// Bit REG_RST_EN_I2S2_APB.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_I2S2_APB = 0x40
	// Position of REG_RST_EN_SPI2 field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SPI2_Pos = 0x7
	// Bit mask of REG_RST_EN_SPI2 field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SPI2_Msk = 0x80
	// Bit REG_RST_EN_SPI2.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SPI2 = 0x80
	// Position of REG_RST_EN_SPI3 field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SPI3_Pos = 0x8
	// Bit mask of REG_RST_EN_SPI3 field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SPI3_Msk = 0x100
	// Bit REG_RST_EN_SPI3.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SPI3 = 0x100
	// Position of REG_RST_EN_LCDCAM field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_LCDCAM_Pos = 0x9
	// Bit mask of REG_RST_EN_LCDCAM field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_LCDCAM_Msk = 0x200
	// Bit REG_RST_EN_LCDCAM.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_LCDCAM = 0x200
	// Position of REG_RST_EN_ADC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ADC_Pos = 0xa
	// Bit mask of REG_RST_EN_ADC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ADC_Msk = 0x400
	// Bit REG_RST_EN_ADC.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ADC = 0x400
	// Position of REG_RST_EN_BITSRAMBLER field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_Pos = 0xb
	// Bit mask of REG_RST_EN_BITSRAMBLER field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_Msk = 0x800
	// Bit REG_RST_EN_BITSRAMBLER.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER = 0x800
	// Position of REG_RST_EN_BITSRAMBLER_RX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_RX_Pos = 0xc
	// Bit mask of REG_RST_EN_BITSRAMBLER_RX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_RX_Msk = 0x1000
	// Bit REG_RST_EN_BITSRAMBLER_RX.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_RX = 0x1000
	// Position of REG_RST_EN_BITSRAMBLER_TX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_TX_Pos = 0xd
	// Bit mask of REG_RST_EN_BITSRAMBLER_TX field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_TX_Msk = 0x2000
	// Bit REG_RST_EN_BITSRAMBLER_TX.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_BITSRAMBLER_TX = 0x2000
	// Position of REG_RST_EN_CRYPTO field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_CRYPTO_Pos = 0xe
	// Bit mask of REG_RST_EN_CRYPTO field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_CRYPTO_Msk = 0x4000
	// Bit REG_RST_EN_CRYPTO.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_CRYPTO = 0x4000
	// Position of REG_RST_EN_SEC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SEC_Pos = 0xf
	// Bit mask of REG_RST_EN_SEC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SEC_Msk = 0x8000
	// Bit REG_RST_EN_SEC.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SEC = 0x8000
	// Position of REG_RST_EN_AES field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_AES_Pos = 0x10
	// Bit mask of REG_RST_EN_AES field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_AES_Msk = 0x10000
	// Bit REG_RST_EN_AES.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_AES = 0x10000
	// Position of REG_RST_EN_DS field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_DS_Pos = 0x11
	// Bit mask of REG_RST_EN_DS field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_DS_Msk = 0x20000
	// Bit REG_RST_EN_DS.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_DS = 0x20000
	// Position of REG_RST_EN_SHA field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SHA_Pos = 0x12
	// Bit mask of REG_RST_EN_SHA field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SHA_Msk = 0x40000
	// Bit REG_RST_EN_SHA.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_SHA = 0x40000
	// Position of REG_RST_EN_HMAC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_HMAC_Pos = 0x13
	// Bit mask of REG_RST_EN_HMAC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_HMAC_Msk = 0x80000
	// Bit REG_RST_EN_HMAC.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_HMAC = 0x80000
	// Position of REG_RST_EN_ECDSA field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ECDSA_Pos = 0x14
	// Bit mask of REG_RST_EN_ECDSA field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ECDSA_Msk = 0x100000
	// Bit REG_RST_EN_ECDSA.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ECDSA = 0x100000
	// Position of REG_RST_EN_RSA field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_RSA_Pos = 0x15
	// Bit mask of REG_RST_EN_RSA field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_RSA_Msk = 0x200000
	// Bit REG_RST_EN_RSA.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_RSA = 0x200000
	// Position of REG_RST_EN_ECC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ECC_Pos = 0x16
	// Bit mask of REG_RST_EN_ECC field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ECC_Msk = 0x400000
	// Bit REG_RST_EN_ECC.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_ECC = 0x400000
	// Position of REG_RST_EN_KM field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_KM_Pos = 0x17
	// Bit mask of REG_RST_EN_KM field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_KM_Msk = 0x800000
	// Bit REG_RST_EN_KM.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_KM = 0x800000
	// Position of REG_RST_EN_H264 field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_H264_Pos = 0x18
	// Bit mask of REG_RST_EN_H264 field.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_H264_Msk = 0x1000000
	// Bit REG_RST_EN_H264.
	HP_SYS_CLKRST_HP_RST_EN2_REG_RST_EN_H264 = 0x1000000

	// HP_FORCE_NORST0: Reserved
	// Position of REG_FORCE_NORST_CORE0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORE0_Pos = 0x0
	// Bit mask of REG_FORCE_NORST_CORE0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORE0_Msk = 0x1
	// Bit REG_FORCE_NORST_CORE0.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORE0 = 0x1
	// Position of REG_FORCE_NORST_CORE1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORE1_Pos = 0x1
	// Bit mask of REG_FORCE_NORST_CORE1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORE1_Msk = 0x2
	// Bit REG_FORCE_NORST_CORE1.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORE1 = 0x2
	// Position of REG_FORCE_NORST_CORETRACE0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE0_Pos = 0x2
	// Bit mask of REG_FORCE_NORST_CORETRACE0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE0_Msk = 0x4
	// Bit REG_FORCE_NORST_CORETRACE0.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE0 = 0x4
	// Position of REG_FORCE_NORST_CORETRACE1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE1_Pos = 0x3
	// Bit mask of REG_FORCE_NORST_CORETRACE1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE1_Msk = 0x8
	// Bit REG_FORCE_NORST_CORETRACE1.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CORETRACE1 = 0x8
	// Position of REG_FORCE_NORST_L2MEMMON field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_L2MEMMON_Pos = 0x4
	// Bit mask of REG_FORCE_NORST_L2MEMMON field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_L2MEMMON_Msk = 0x10
	// Bit REG_FORCE_NORST_L2MEMMON.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_L2MEMMON = 0x10
	// Position of REG_FORCE_NORST_TCMMON field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TCMMON_Pos = 0x5
	// Bit mask of REG_FORCE_NORST_TCMMON field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TCMMON_Msk = 0x20
	// Bit REG_FORCE_NORST_TCMMON.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TCMMON = 0x20
	// Position of REG_FORCE_NORST_GDMA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_GDMA_Pos = 0x6
	// Bit mask of REG_FORCE_NORST_GDMA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_GDMA_Msk = 0x40
	// Bit REG_FORCE_NORST_GDMA.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_GDMA = 0x40
	// Position of REG_FORCE_NORST_MSPI_AXI field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_MSPI_AXI_Pos = 0x7
	// Bit mask of REG_FORCE_NORST_MSPI_AXI field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_MSPI_AXI_Msk = 0x80
	// Bit REG_FORCE_NORST_MSPI_AXI.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_MSPI_AXI = 0x80
	// Position of REG_FORCE_NORST_DUAL_MSPI_AXI field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_AXI_Pos = 0x8
	// Bit mask of REG_FORCE_NORST_DUAL_MSPI_AXI field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_AXI_Msk = 0x100
	// Bit REG_FORCE_NORST_DUAL_MSPI_AXI.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_AXI = 0x100
	// Position of REG_FORCE_NORST_MSPI_APB field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_MSPI_APB_Pos = 0x9
	// Bit mask of REG_FORCE_NORST_MSPI_APB field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_MSPI_APB_Msk = 0x200
	// Bit REG_FORCE_NORST_MSPI_APB.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_MSPI_APB = 0x200
	// Position of REG_FORCE_NORST_DUAL_MSPI_APB field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_APB_Pos = 0xa
	// Bit mask of REG_FORCE_NORST_DUAL_MSPI_APB field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_APB_Msk = 0x400
	// Bit REG_FORCE_NORST_DUAL_MSPI_APB.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DUAL_MSPI_APB = 0x400
	// Position of REG_FORCE_NORST_DSI_BRG field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DSI_BRG_Pos = 0xb
	// Bit mask of REG_FORCE_NORST_DSI_BRG field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DSI_BRG_Msk = 0x800
	// Bit REG_FORCE_NORST_DSI_BRG.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DSI_BRG = 0x800
	// Position of REG_FORCE_NORST_CSI_HOST field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CSI_HOST_Pos = 0xc
	// Bit mask of REG_FORCE_NORST_CSI_HOST field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CSI_HOST_Msk = 0x1000
	// Bit REG_FORCE_NORST_CSI_HOST.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CSI_HOST = 0x1000
	// Position of REG_FORCE_NORST_CSI_BRG field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CSI_BRG_Pos = 0xd
	// Bit mask of REG_FORCE_NORST_CSI_BRG field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CSI_BRG_Msk = 0x2000
	// Bit REG_FORCE_NORST_CSI_BRG.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_CSI_BRG = 0x2000
	// Position of REG_FORCE_NORST_ISP field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_ISP_Pos = 0xe
	// Bit mask of REG_FORCE_NORST_ISP field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_ISP_Msk = 0x4000
	// Bit REG_FORCE_NORST_ISP.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_ISP = 0x4000
	// Position of REG_FORCE_NORST_JPEG field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_JPEG_Pos = 0xf
	// Bit mask of REG_FORCE_NORST_JPEG field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_JPEG_Msk = 0x8000
	// Bit REG_FORCE_NORST_JPEG.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_JPEG = 0x8000
	// Position of REG_FORCE_NORST_DMA2D field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DMA2D_Pos = 0x10
	// Bit mask of REG_FORCE_NORST_DMA2D field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DMA2D_Msk = 0x10000
	// Bit REG_FORCE_NORST_DMA2D.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_DMA2D = 0x10000
	// Position of REG_FORCE_NORST_PPA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_PPA_Pos = 0x11
	// Bit mask of REG_FORCE_NORST_PPA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_PPA_Msk = 0x20000
	// Bit REG_FORCE_NORST_PPA.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_PPA = 0x20000
	// Position of REG_FORCE_NORST_AHB_PDMA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_AHB_PDMA_Pos = 0x12
	// Bit mask of REG_FORCE_NORST_AHB_PDMA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_AHB_PDMA_Msk = 0x40000
	// Bit REG_FORCE_NORST_AHB_PDMA.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_AHB_PDMA = 0x40000
	// Position of REG_FORCE_NORST_AXI_PDMA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_AXI_PDMA_Pos = 0x13
	// Bit mask of REG_FORCE_NORST_AXI_PDMA field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_AXI_PDMA_Msk = 0x80000
	// Bit REG_FORCE_NORST_AXI_PDMA.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_AXI_PDMA = 0x80000
	// Position of REG_FORCE_NORST_IOMUX field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_IOMUX_Pos = 0x14
	// Bit mask of REG_FORCE_NORST_IOMUX field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_IOMUX_Msk = 0x100000
	// Bit REG_FORCE_NORST_IOMUX.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_IOMUX = 0x100000
	// Position of REG_FORCE_NORST_PADBIST field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_PADBIST_Pos = 0x15
	// Bit mask of REG_FORCE_NORST_PADBIST field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_PADBIST_Msk = 0x200000
	// Bit REG_FORCE_NORST_PADBIST.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_PADBIST = 0x200000
	// Position of REG_FORCE_NORST_STIMER field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_STIMER_Pos = 0x16
	// Bit mask of REG_FORCE_NORST_STIMER field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_STIMER_Msk = 0x400000
	// Bit REG_FORCE_NORST_STIMER.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_STIMER = 0x400000
	// Position of REG_FORCE_NORST_TIMERGRP0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP0_Pos = 0x17
	// Bit mask of REG_FORCE_NORST_TIMERGRP0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP0_Msk = 0x800000
	// Bit REG_FORCE_NORST_TIMERGRP0.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP0 = 0x800000
	// Position of REG_FORCE_NORST_TIMERGRP1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP1_Pos = 0x18
	// Bit mask of REG_FORCE_NORST_TIMERGRP1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP1_Msk = 0x1000000
	// Bit REG_FORCE_NORST_TIMERGRP1.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_TIMERGRP1 = 0x1000000
	// Position of REG_FORCE_NORST_UART0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART0_Pos = 0x19
	// Bit mask of REG_FORCE_NORST_UART0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART0_Msk = 0x2000000
	// Bit REG_FORCE_NORST_UART0.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART0 = 0x2000000
	// Position of REG_FORCE_NORST_UART1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART1_Pos = 0x1a
	// Bit mask of REG_FORCE_NORST_UART1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART1_Msk = 0x4000000
	// Bit REG_FORCE_NORST_UART1.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART1 = 0x4000000
	// Position of REG_FORCE_NORST_UART2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART2_Pos = 0x1b
	// Bit mask of REG_FORCE_NORST_UART2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART2_Msk = 0x8000000
	// Bit REG_FORCE_NORST_UART2.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART2 = 0x8000000
	// Position of REG_FORCE_NORST_UART3 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART3_Pos = 0x1c
	// Bit mask of REG_FORCE_NORST_UART3 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART3_Msk = 0x10000000
	// Bit REG_FORCE_NORST_UART3.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART3 = 0x10000000
	// Position of REG_FORCE_NORST_UART4 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART4_Pos = 0x1d
	// Bit mask of REG_FORCE_NORST_UART4 field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART4_Msk = 0x20000000
	// Bit REG_FORCE_NORST_UART4.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UART4 = 0x20000000
	// Position of REG_FORCE_NORST_UHCI field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UHCI_Pos = 0x1e
	// Bit mask of REG_FORCE_NORST_UHCI field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UHCI_Msk = 0x40000000
	// Bit REG_FORCE_NORST_UHCI.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_UHCI = 0x40000000
	// Position of REG_FORCE_NORST_I3CMST field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_I3CMST_Pos = 0x1f
	// Bit mask of REG_FORCE_NORST_I3CMST field.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_I3CMST_Msk = 0x80000000
	// Bit REG_FORCE_NORST_I3CMST.
	HP_SYS_CLKRST_HP_FORCE_NORST0_REG_FORCE_NORST_I3CMST = 0x80000000

	// HP_FORCE_NORST1: Reserved
	// Position of REG_FORCE_NORST_I3CSLV field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I3CSLV_Pos = 0x0
	// Bit mask of REG_FORCE_NORST_I3CSLV field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I3CSLV_Msk = 0x1
	// Bit REG_FORCE_NORST_I3CSLV.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I3CSLV = 0x1
	// Position of REG_FORCE_NORST_I2C1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2C1_Pos = 0x1
	// Bit mask of REG_FORCE_NORST_I2C1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2C1_Msk = 0x2
	// Bit REG_FORCE_NORST_I2C1.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2C1 = 0x2
	// Position of REG_FORCE_NORST_I2C0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2C0_Pos = 0x2
	// Bit mask of REG_FORCE_NORST_I2C0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2C0_Msk = 0x4
	// Bit REG_FORCE_NORST_I2C0.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2C0 = 0x4
	// Position of REG_FORCE_NORST_RMT field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_RMT_Pos = 0x3
	// Bit mask of REG_FORCE_NORST_RMT field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_RMT_Msk = 0x8
	// Bit REG_FORCE_NORST_RMT.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_RMT = 0x8
	// Position of REG_FORCE_NORST_PWM0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PWM0_Pos = 0x4
	// Bit mask of REG_FORCE_NORST_PWM0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PWM0_Msk = 0x10
	// Bit REG_FORCE_NORST_PWM0.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PWM0 = 0x10
	// Position of REG_FORCE_NORST_PWM1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PWM1_Pos = 0x5
	// Bit mask of REG_FORCE_NORST_PWM1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PWM1_Msk = 0x20
	// Bit REG_FORCE_NORST_PWM1.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PWM1 = 0x20
	// Position of REG_FORCE_NORST_CAN0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN0_Pos = 0x6
	// Bit mask of REG_FORCE_NORST_CAN0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN0_Msk = 0x40
	// Bit REG_FORCE_NORST_CAN0.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN0 = 0x40
	// Position of REG_FORCE_NORST_CAN1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN1_Pos = 0x7
	// Bit mask of REG_FORCE_NORST_CAN1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN1_Msk = 0x80
	// Bit REG_FORCE_NORST_CAN1.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN1 = 0x80
	// Position of REG_FORCE_NORST_CAN2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN2_Pos = 0x8
	// Bit mask of REG_FORCE_NORST_CAN2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN2_Msk = 0x100
	// Bit REG_FORCE_NORST_CAN2.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_CAN2 = 0x100
	// Position of REG_FORCE_NORST_LEDC field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_LEDC_Pos = 0x9
	// Bit mask of REG_FORCE_NORST_LEDC field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_LEDC_Msk = 0x200
	// Bit REG_FORCE_NORST_LEDC.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_LEDC = 0x200
	// Position of REG_FORCE_NORST_PCNT field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PCNT_Pos = 0xa
	// Bit mask of REG_FORCE_NORST_PCNT field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PCNT_Msk = 0x400
	// Bit REG_FORCE_NORST_PCNT.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PCNT = 0x400
	// Position of REG_FORCE_NORST_ETM field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_ETM_Pos = 0xb
	// Bit mask of REG_FORCE_NORST_ETM field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_ETM_Msk = 0x800
	// Bit REG_FORCE_NORST_ETM.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_ETM = 0x800
	// Position of REG_FORCE_NORST_INTRMTX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_INTRMTX_Pos = 0xc
	// Bit mask of REG_FORCE_NORST_INTRMTX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_INTRMTX_Msk = 0x1000
	// Bit REG_FORCE_NORST_INTRMTX.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_INTRMTX = 0x1000
	// Position of REG_FORCE_NORST_PARLIO field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_Pos = 0xd
	// Bit mask of REG_FORCE_NORST_PARLIO field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_Msk = 0x2000
	// Bit REG_FORCE_NORST_PARLIO.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO = 0x2000
	// Position of REG_FORCE_NORST_PARLIO_RX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_RX_Pos = 0xe
	// Bit mask of REG_FORCE_NORST_PARLIO_RX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_RX_Msk = 0x4000
	// Bit REG_FORCE_NORST_PARLIO_RX.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_RX = 0x4000
	// Position of REG_FORCE_NORST_PARLIO_TX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_TX_Pos = 0xf
	// Bit mask of REG_FORCE_NORST_PARLIO_TX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_TX_Msk = 0x8000
	// Bit REG_FORCE_NORST_PARLIO_TX.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_PARLIO_TX = 0x8000
	// Position of REG_FORCE_NORST_I2S0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S0_Pos = 0x10
	// Bit mask of REG_FORCE_NORST_I2S0 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S0_Msk = 0x10000
	// Bit REG_FORCE_NORST_I2S0.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S0 = 0x10000
	// Position of REG_FORCE_NORST_I2S1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S1_Pos = 0x11
	// Bit mask of REG_FORCE_NORST_I2S1 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S1_Msk = 0x20000
	// Bit REG_FORCE_NORST_I2S1.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S1 = 0x20000
	// Position of REG_FORCE_NORST_I2S2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S2_Pos = 0x12
	// Bit mask of REG_FORCE_NORST_I2S2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S2_Msk = 0x40000
	// Bit REG_FORCE_NORST_I2S2.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_I2S2 = 0x40000
	// Position of REG_FORCE_NORST_SPI2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_SPI2_Pos = 0x13
	// Bit mask of REG_FORCE_NORST_SPI2 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_SPI2_Msk = 0x80000
	// Bit REG_FORCE_NORST_SPI2.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_SPI2 = 0x80000
	// Position of REG_FORCE_NORST_SPI3 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_SPI3_Pos = 0x14
	// Bit mask of REG_FORCE_NORST_SPI3 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_SPI3_Msk = 0x100000
	// Bit REG_FORCE_NORST_SPI3.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_SPI3 = 0x100000
	// Position of REG_FORCE_NORST_LCDCAM field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_LCDCAM_Pos = 0x15
	// Bit mask of REG_FORCE_NORST_LCDCAM field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_LCDCAM_Msk = 0x200000
	// Bit REG_FORCE_NORST_LCDCAM.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_LCDCAM = 0x200000
	// Position of REG_FORCE_NORST_ADC field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_ADC_Pos = 0x16
	// Bit mask of REG_FORCE_NORST_ADC field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_ADC_Msk = 0x400000
	// Bit REG_FORCE_NORST_ADC.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_ADC = 0x400000
	// Position of REG_FORCE_NORST_BITSRAMBLER field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_Pos = 0x17
	// Bit mask of REG_FORCE_NORST_BITSRAMBLER field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_Msk = 0x800000
	// Bit REG_FORCE_NORST_BITSRAMBLER.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER = 0x800000
	// Position of REG_FORCE_NORST_BITSRAMBLER_RX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_RX_Pos = 0x18
	// Bit mask of REG_FORCE_NORST_BITSRAMBLER_RX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_RX_Msk = 0x1000000
	// Bit REG_FORCE_NORST_BITSRAMBLER_RX.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_RX = 0x1000000
	// Position of REG_FORCE_NORST_BITSRAMBLER_TX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_TX_Pos = 0x19
	// Bit mask of REG_FORCE_NORST_BITSRAMBLER_TX field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_TX_Msk = 0x2000000
	// Bit REG_FORCE_NORST_BITSRAMBLER_TX.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_BITSRAMBLER_TX = 0x2000000
	// Position of REG_FORCE_NORST_H264 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_H264_Pos = 0x1a
	// Bit mask of REG_FORCE_NORST_H264 field.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_H264_Msk = 0x4000000
	// Bit REG_FORCE_NORST_H264.
	HP_SYS_CLKRST_HP_FORCE_NORST1_REG_FORCE_NORST_H264 = 0x4000000

	// HPWDT_CORE0_RST_CTRL0: Reserved
	// Position of REG_HPCORE0_STALL_EN field.
	HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_EN_Pos = 0x0
	// Bit mask of REG_HPCORE0_STALL_EN field.
	HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_EN_Msk = 0x1
	// Bit REG_HPCORE0_STALL_EN.
	HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_EN = 0x1
	// Position of REG_HPCORE0_STALL_WAIT_NUM field.
	HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_WAIT_NUM_Pos = 0x1
	// Bit mask of REG_HPCORE0_STALL_WAIT_NUM field.
	HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG_HPCORE0_STALL_WAIT_NUM_Msk = 0x1fe
	// Position of REG_WDT_HPCORE0_RST_LEN field.
	HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG_WDT_HPCORE0_RST_LEN_Pos = 0x9
	// Bit mask of REG_WDT_HPCORE0_RST_LEN field.
	HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG_WDT_HPCORE0_RST_LEN_Msk = 0x1fe00

	// HPWDT_CORE1_RST_CTRL0: Reserved
	// Position of REG_HPCORE1_STALL_EN field.
	HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_EN_Pos = 0x0
	// Bit mask of REG_HPCORE1_STALL_EN field.
	HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_EN_Msk = 0x1
	// Bit REG_HPCORE1_STALL_EN.
	HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_EN = 0x1
	// Position of REG_HPCORE1_STALL_WAIT_NUM field.
	HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_WAIT_NUM_Pos = 0x1
	// Bit mask of REG_HPCORE1_STALL_WAIT_NUM field.
	HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG_HPCORE1_STALL_WAIT_NUM_Msk = 0x1fe
	// Position of REG_WDT_HPCORE1_RST_LEN field.
	HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG_WDT_HPCORE1_RST_LEN_Pos = 0x9
	// Bit mask of REG_WDT_HPCORE1_RST_LEN field.
	HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG_WDT_HPCORE1_RST_LEN_Msk = 0x1fe00

	// CPU_SRC_FREQ0: CPU Source Frequency
	// Position of REG_CPU_SRC_FREQ field.
	HP_SYS_CLKRST_CPU_SRC_FREQ0_REG_CPU_SRC_FREQ_Pos = 0x0
	// Bit mask of REG_CPU_SRC_FREQ field.
	HP_SYS_CLKRST_CPU_SRC_FREQ0_REG_CPU_SRC_FREQ_Msk = 0xffffffff

	// CPU_CLK_STATUS0: CPU Clock Status
	// Position of REG_ASIC_OR_FPGA field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_ASIC_OR_FPGA_Pos = 0x0
	// Bit mask of REG_ASIC_OR_FPGA field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_ASIC_OR_FPGA_Msk = 0x1
	// Bit REG_ASIC_OR_FPGA.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_ASIC_OR_FPGA = 0x1
	// Position of REG_CPU_DIV_EFFECT field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_EFFECT_Pos = 0x1
	// Bit mask of REG_CPU_DIV_EFFECT field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_EFFECT_Msk = 0x2
	// Bit REG_CPU_DIV_EFFECT.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_EFFECT = 0x2
	// Position of REG_CPU_SRC_IS_CPLL field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_SRC_IS_CPLL_Pos = 0x2
	// Bit mask of REG_CPU_SRC_IS_CPLL field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_SRC_IS_CPLL_Msk = 0x4
	// Bit REG_CPU_SRC_IS_CPLL.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_SRC_IS_CPLL = 0x4
	// Position of REG_CPU_DIV_NUM_CUR field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_NUM_CUR_Pos = 0x3
	// Bit mask of REG_CPU_DIV_NUM_CUR field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_NUM_CUR_Msk = 0x7f8
	// Position of REG_CPU_DIV_NUMERATOR_CUR field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_NUMERATOR_CUR_Pos = 0xb
	// Bit mask of REG_CPU_DIV_NUMERATOR_CUR field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_NUMERATOR_CUR_Msk = 0x7f800
	// Position of REG_CPU_DIV_DENOMINATOR_CUR field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_DENOMINATOR_CUR_Pos = 0x13
	// Bit mask of REG_CPU_DIV_DENOMINATOR_CUR field.
	HP_SYS_CLKRST_CPU_CLK_STATUS0_REG_CPU_DIV_DENOMINATOR_CUR_Msk = 0x7f80000

	// DBG_CLK_CTRL0: Reserved
	// Position of REG_DBG_CH0_SEL field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH0_SEL_Pos = 0x0
	// Bit mask of REG_DBG_CH0_SEL field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH0_SEL_Msk = 0xff
	// Position of REG_DBG_CH1_SEL field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH1_SEL_Pos = 0x8
	// Bit mask of REG_DBG_CH1_SEL field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH1_SEL_Msk = 0xff00
	// Position of REG_DBG_CH2_SEL field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH2_SEL_Pos = 0x10
	// Bit mask of REG_DBG_CH2_SEL field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH2_SEL_Msk = 0xff0000
	// Position of REG_DBG_CH0_DIV_NUM field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH0_DIV_NUM_Pos = 0x18
	// Bit mask of REG_DBG_CH0_DIV_NUM field.
	HP_SYS_CLKRST_DBG_CLK_CTRL0_REG_DBG_CH0_DIV_NUM_Msk = 0xff000000

	// DBG_CLK_CTRL1: Reserved
	// Position of REG_DBG_CH1_DIV_NUM field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH1_DIV_NUM_Pos = 0x0
	// Bit mask of REG_DBG_CH1_DIV_NUM field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH1_DIV_NUM_Msk = 0xff
	// Position of REG_DBG_CH2_DIV_NUM field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH2_DIV_NUM_Pos = 0x8
	// Bit mask of REG_DBG_CH2_DIV_NUM field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH2_DIV_NUM_Msk = 0xff00
	// Position of REG_DBG_CH0_EN field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH0_EN_Pos = 0x10
	// Bit mask of REG_DBG_CH0_EN field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH0_EN_Msk = 0x10000
	// Bit REG_DBG_CH0_EN.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH0_EN = 0x10000
	// Position of REG_DBG_CH1_EN field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH1_EN_Pos = 0x11
	// Bit mask of REG_DBG_CH1_EN field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH1_EN_Msk = 0x20000
	// Bit REG_DBG_CH1_EN.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH1_EN = 0x20000
	// Position of REG_DBG_CH2_EN field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH2_EN_Pos = 0x12
	// Bit mask of REG_DBG_CH2_EN field.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH2_EN_Msk = 0x40000
	// Bit REG_DBG_CH2_EN.
	HP_SYS_CLKRST_DBG_CLK_CTRL1_REG_DBG_CH2_EN = 0x40000

	// HPCORE_WDT_RESET_SOURCE0: Reserved
	// Position of REG_HPCORE0_WDT_RESET_SOURCE_SEL field.
	HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG_HPCORE0_WDT_RESET_SOURCE_SEL_Pos = 0x0
	// Bit mask of REG_HPCORE0_WDT_RESET_SOURCE_SEL field.
	HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG_HPCORE0_WDT_RESET_SOURCE_SEL_Msk = 0x1
	// Bit REG_HPCORE0_WDT_RESET_SOURCE_SEL.
	HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG_HPCORE0_WDT_RESET_SOURCE_SEL = 0x1
	// Position of REG_HPCORE1_WDT_RESET_SOURCE_SEL field.
	HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG_HPCORE1_WDT_RESET_SOURCE_SEL_Pos = 0x1
	// Bit mask of REG_HPCORE1_WDT_RESET_SOURCE_SEL field.
	HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG_HPCORE1_WDT_RESET_SOURCE_SEL_Msk = 0x2
	// Bit REG_HPCORE1_WDT_RESET_SOURCE_SEL.
	HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG_HPCORE1_WDT_RESET_SOURCE_SEL = 0x2
)

// Constants for LP_HUK: LP_HUK Peripheral
const (
	// CLK: HUK Generator clock gate control register
	// Position of EN field.
	HUK_CLK_EN_Pos = 0x0
	// Bit mask of EN field.
	HUK_CLK_EN_Msk = 0x1
	// Bit EN.
	HUK_CLK_EN = 0x1
	// Position of MEM_CG_FORCE_ON field.
	HUK_CLK_MEM_CG_FORCE_ON_Pos = 0x1
	// Bit mask of MEM_CG_FORCE_ON field.
	HUK_CLK_MEM_CG_FORCE_ON_Msk = 0x2
	// Bit MEM_CG_FORCE_ON.
	HUK_CLK_MEM_CG_FORCE_ON = 0x2

	// INT_RAW: HUK Generator interrupt raw register, valid in level.
	// Position of PREP_DONE_INT_RAW field.
	HUK_INT_RAW_PREP_DONE_INT_RAW_Pos = 0x0
	// Bit mask of PREP_DONE_INT_RAW field.
	HUK_INT_RAW_PREP_DONE_INT_RAW_Msk = 0x1
	// Bit PREP_DONE_INT_RAW.
	HUK_INT_RAW_PREP_DONE_INT_RAW = 0x1
	// Position of PROC_DONE_INT_RAW field.
	HUK_INT_RAW_PROC_DONE_INT_RAW_Pos = 0x1
	// Bit mask of PROC_DONE_INT_RAW field.
	HUK_INT_RAW_PROC_DONE_INT_RAW_Msk = 0x2
	// Bit PROC_DONE_INT_RAW.
	HUK_INT_RAW_PROC_DONE_INT_RAW = 0x2
	// Position of POST_DONE_INT_RAW field.
	HUK_INT_RAW_POST_DONE_INT_RAW_Pos = 0x2
	// Bit mask of POST_DONE_INT_RAW field.
	HUK_INT_RAW_POST_DONE_INT_RAW_Msk = 0x4
	// Bit POST_DONE_INT_RAW.
	HUK_INT_RAW_POST_DONE_INT_RAW = 0x4

	// INT_ST: HUK Generator interrupt status register.
	// Position of PREP_DONE_INT_ST field.
	HUK_INT_ST_PREP_DONE_INT_ST_Pos = 0x0
	// Bit mask of PREP_DONE_INT_ST field.
	HUK_INT_ST_PREP_DONE_INT_ST_Msk = 0x1
	// Bit PREP_DONE_INT_ST.
	HUK_INT_ST_PREP_DONE_INT_ST = 0x1
	// Position of PROC_DONE_INT_ST field.
	HUK_INT_ST_PROC_DONE_INT_ST_Pos = 0x1
	// Bit mask of PROC_DONE_INT_ST field.
	HUK_INT_ST_PROC_DONE_INT_ST_Msk = 0x2
	// Bit PROC_DONE_INT_ST.
	HUK_INT_ST_PROC_DONE_INT_ST = 0x2
	// Position of POST_DONE_INT_ST field.
	HUK_INT_ST_POST_DONE_INT_ST_Pos = 0x2
	// Bit mask of POST_DONE_INT_ST field.
	HUK_INT_ST_POST_DONE_INT_ST_Msk = 0x4
	// Bit POST_DONE_INT_ST.
	HUK_INT_ST_POST_DONE_INT_ST = 0x4

	// INT_ENA: HUK Generator interrupt enable register.
	// Position of PREP_DONE_INT_ENA field.
	HUK_INT_ENA_PREP_DONE_INT_ENA_Pos = 0x0
	// Bit mask of PREP_DONE_INT_ENA field.
	HUK_INT_ENA_PREP_DONE_INT_ENA_Msk = 0x1
	// Bit PREP_DONE_INT_ENA.
	HUK_INT_ENA_PREP_DONE_INT_ENA = 0x1
	// Position of PROC_DONE_INT_ENA field.
	HUK_INT_ENA_PROC_DONE_INT_ENA_Pos = 0x1
	// Bit mask of PROC_DONE_INT_ENA field.
	HUK_INT_ENA_PROC_DONE_INT_ENA_Msk = 0x2
	// Bit PROC_DONE_INT_ENA.
	HUK_INT_ENA_PROC_DONE_INT_ENA = 0x2
	// Position of POST_DONE_INT_ENA field.
	HUK_INT_ENA_POST_DONE_INT_ENA_Pos = 0x2
	// Bit mask of POST_DONE_INT_ENA field.
	HUK_INT_ENA_POST_DONE_INT_ENA_Msk = 0x4
	// Bit POST_DONE_INT_ENA.
	HUK_INT_ENA_POST_DONE_INT_ENA = 0x4

	// INT_CLR: HUK Generator interrupt clear register.
	// Position of PREP_DONE_INT_CLR field.
	HUK_INT_CLR_PREP_DONE_INT_CLR_Pos = 0x0
	// Bit mask of PREP_DONE_INT_CLR field.
	HUK_INT_CLR_PREP_DONE_INT_CLR_Msk = 0x1
	// Bit PREP_DONE_INT_CLR.
	HUK_INT_CLR_PREP_DONE_INT_CLR = 0x1
	// Position of PROC_DONE_INT_CLR field.
	HUK_INT_CLR_PROC_DONE_INT_CLR_Pos = 0x1
	// Bit mask of PROC_DONE_INT_CLR field.
	HUK_INT_CLR_PROC_DONE_INT_CLR_Msk = 0x2
	// Bit PROC_DONE_INT_CLR.
	HUK_INT_CLR_PROC_DONE_INT_CLR = 0x2
	// Position of POST_DONE_INT_CLR field.
	HUK_INT_CLR_POST_DONE_INT_CLR_Pos = 0x2
	// Bit mask of POST_DONE_INT_CLR field.
	HUK_INT_CLR_POST_DONE_INT_CLR_Msk = 0x4
	// Bit POST_DONE_INT_CLR.
	HUK_INT_CLR_POST_DONE_INT_CLR = 0x4

	// CONF: HUK Generator configuration register
	// Position of MODE field.
	HUK_CONF_MODE_Pos = 0x0
	// Bit mask of MODE field.
	HUK_CONF_MODE_Msk = 0x1
	// Bit MODE.
	HUK_CONF_MODE = 0x1

	// START: HUK Generator control register
	// Position of START field.
	HUK_START_START_Pos = 0x0
	// Bit mask of START field.
	HUK_START_START_Msk = 0x1
	// Bit START.
	HUK_START_START = 0x1
	// Position of CONTINUE field.
	HUK_START_CONTINUE_Pos = 0x1
	// Bit mask of CONTINUE field.
	HUK_START_CONTINUE_Msk = 0x2
	// Bit CONTINUE.
	HUK_START_CONTINUE = 0x2

	// STATE: HUK Generator state register
	// Position of STATE field.
	HUK_STATE_STATE_Pos = 0x0
	// Bit mask of STATE field.
	HUK_STATE_STATE_Msk = 0x3

	// STATUS: HUK Generator HUK status register
	// Position of STATUS field.
	HUK_STATUS_STATUS_Pos = 0x0
	// Bit mask of STATUS field.
	HUK_STATUS_STATUS_Msk = 0x3
	// Position of RISK_LEVEL field.
	HUK_STATUS_RISK_LEVEL_Pos = 0x2
	// Bit mask of RISK_LEVEL field.
	HUK_STATUS_RISK_LEVEL_Msk = 0x1c

	// DATE: Version control register
	// Position of DATE field.
	HUK_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	HUK_DATE_DATE_Msk = 0xfffffff
)

// Constants for I2C0: I2C (Inter-Integrated Circuit) Controller 0
const (
	// SCL_LOW_PERIOD: Configures the low level width of the SCL Clock.
	// Position of SCL_LOW_PERIOD field.
	I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0
	// Bit mask of SCL_LOW_PERIOD field.
	I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff

	// CTR: Transmission setting
	// Position of SDA_FORCE_OUT field.
	I2C_CTR_SDA_FORCE_OUT_Pos = 0x0
	// Bit mask of SDA_FORCE_OUT field.
	I2C_CTR_SDA_FORCE_OUT_Msk = 0x1
	// Bit SDA_FORCE_OUT.
	I2C_CTR_SDA_FORCE_OUT = 0x1
	// Position of SCL_FORCE_OUT field.
	I2C_CTR_SCL_FORCE_OUT_Pos = 0x1
	// Bit mask of SCL_FORCE_OUT field.
	I2C_CTR_SCL_FORCE_OUT_Msk = 0x2
	// Bit SCL_FORCE_OUT.
	I2C_CTR_SCL_FORCE_OUT = 0x2
	// Position of SAMPLE_SCL_LEVEL field.
	I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2
	// Bit mask of SAMPLE_SCL_LEVEL field.
	I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4
	// Bit SAMPLE_SCL_LEVEL.
	I2C_CTR_SAMPLE_SCL_LEVEL = 0x4
	// Position of RX_FULL_ACK_LEVEL field.
	I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3
	// Bit mask of RX_FULL_ACK_LEVEL field.
	I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8
	// Bit RX_FULL_ACK_LEVEL.
	I2C_CTR_RX_FULL_ACK_LEVEL = 0x8
	// Position of MS_MODE field.
	I2C_CTR_MS_MODE_Pos = 0x4
	// Bit mask of MS_MODE field.
	I2C_CTR_MS_MODE_Msk = 0x10
	// Bit MS_MODE.
	I2C_CTR_MS_MODE = 0x10
	// Position of TRANS_START field.
	I2C_CTR_TRANS_START_Pos = 0x5
	// Bit mask of TRANS_START field.
	I2C_CTR_TRANS_START_Msk = 0x20
	// Bit TRANS_START.
	I2C_CTR_TRANS_START = 0x20
	// Position of TX_LSB_FIRST field.
	I2C_CTR_TX_LSB_FIRST_Pos = 0x6
	// Bit mask of TX_LSB_FIRST field.
	I2C_CTR_TX_LSB_FIRST_Msk = 0x40
	// Bit TX_LSB_FIRST.
	I2C_CTR_TX_LSB_FIRST = 0x40
	// Position of RX_LSB_FIRST field.
	I2C_CTR_RX_LSB_FIRST_Pos = 0x7
	// Bit mask of RX_LSB_FIRST field.
	I2C_CTR_RX_LSB_FIRST_Msk = 0x80
	// Bit RX_LSB_FIRST.
	I2C_CTR_RX_LSB_FIRST = 0x80
	// Position of CLK_EN field.
	I2C_CTR_CLK_EN_Pos = 0x8
	// Bit mask of CLK_EN field.
	I2C_CTR_CLK_EN_Msk = 0x100
	// Bit CLK_EN.
	I2C_CTR_CLK_EN = 0x100
	// Position of ARBITRATION_EN field.
	I2C_CTR_ARBITRATION_EN_Pos = 0x9
	// Bit mask of ARBITRATION_EN field.
	I2C_CTR_ARBITRATION_EN_Msk = 0x200
	// Bit ARBITRATION_EN.
	I2C_CTR_ARBITRATION_EN = 0x200
	// Position of FSM_RST field.
	I2C_CTR_FSM_RST_Pos = 0xa
	// Bit mask of FSM_RST field.
	I2C_CTR_FSM_RST_Msk = 0x400
	// Bit FSM_RST.
	I2C_CTR_FSM_RST = 0x400
	// Position of CONF_UPGATE field.
	I2C_CTR_CONF_UPGATE_Pos = 0xb
	// Bit mask of CONF_UPGATE field.
	I2C_CTR_CONF_UPGATE_Msk = 0x800
	// Bit CONF_UPGATE.
	I2C_CTR_CONF_UPGATE = 0x800
	// Position of SLV_TX_AUTO_START_EN field.
	I2C_CTR_SLV_TX_AUTO_START_EN_Pos = 0xc
	// Bit mask of SLV_TX_AUTO_START_EN field.
	I2C_CTR_SLV_TX_AUTO_START_EN_Msk = 0x1000
	// Bit SLV_TX_AUTO_START_EN.
	I2C_CTR_SLV_TX_AUTO_START_EN = 0x1000
	// Position of ADDR_10BIT_RW_CHECK_EN field.
	I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Pos = 0xd
	// Bit mask of ADDR_10BIT_RW_CHECK_EN field.
	I2C_CTR_ADDR_10BIT_RW_CHECK_EN_Msk = 0x2000
	// Bit ADDR_10BIT_RW_CHECK_EN.
	I2C_CTR_ADDR_10BIT_RW_CHECK_EN = 0x2000
	// Position of ADDR_BROADCASTING_EN field.
	I2C_CTR_ADDR_BROADCASTING_EN_Pos = 0xe
	// Bit mask of ADDR_BROADCASTING_EN field.
	I2C_CTR_ADDR_BROADCASTING_EN_Msk = 0x4000
	// Bit ADDR_BROADCASTING_EN.
	I2C_CTR_ADDR_BROADCASTING_EN = 0x4000

	// SR: Describe I2C work status.
	// Position of RESP_REC field.
	I2C_SR_RESP_REC_Pos = 0x0
	// Bit mask of RESP_REC field.
	I2C_SR_RESP_REC_Msk = 0x1
	// Bit RESP_REC.
	I2C_SR_RESP_REC = 0x1
	// Position of SLAVE_RW field.
	I2C_SR_SLAVE_RW_Pos = 0x1
	// Bit mask of SLAVE_RW field.
	I2C_SR_SLAVE_RW_Msk = 0x2
	// Bit SLAVE_RW.
	I2C_SR_SLAVE_RW = 0x2
	// Position of ARB_LOST field.
	I2C_SR_ARB_LOST_Pos = 0x3
	// Bit mask of ARB_LOST field.
	I2C_SR_ARB_LOST_Msk = 0x8
	// Bit ARB_LOST.
	I2C_SR_ARB_LOST = 0x8
	// Position of BUS_BUSY field.
	I2C_SR_BUS_BUSY_Pos = 0x4
	// Bit mask of BUS_BUSY field.
	I2C_SR_BUS_BUSY_Msk = 0x10
	// Bit BUS_BUSY.
	I2C_SR_BUS_BUSY = 0x10
	// Position of SLAVE_ADDRESSED field.
	I2C_SR_SLAVE_ADDRESSED_Pos = 0x5
	// Bit mask of SLAVE_ADDRESSED field.
	I2C_SR_SLAVE_ADDRESSED_Msk = 0x20
	// Bit SLAVE_ADDRESSED.
	I2C_SR_SLAVE_ADDRESSED = 0x20
	// Position of RXFIFO_CNT field.
	I2C_SR_RXFIFO_CNT_Pos = 0x8
	// Bit mask of RXFIFO_CNT field.
	I2C_SR_RXFIFO_CNT_Msk = 0x3f00
	// Position of STRETCH_CAUSE field.
	I2C_SR_STRETCH_CAUSE_Pos = 0xe
	// Bit mask of STRETCH_CAUSE field.
	I2C_SR_STRETCH_CAUSE_Msk = 0xc000
	// Position of TXFIFO_CNT field.
	I2C_SR_TXFIFO_CNT_Pos = 0x12
	// Bit mask of TXFIFO_CNT field.
	I2C_SR_TXFIFO_CNT_Msk = 0xfc0000
	// Position of SCL_MAIN_STATE_LAST field.
	I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18
	// Bit mask of SCL_MAIN_STATE_LAST field.
	I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000
	// Position of SCL_STATE_LAST field.
	I2C_SR_SCL_STATE_LAST_Pos = 0x1c
	// Bit mask of SCL_STATE_LAST field.
	I2C_SR_SCL_STATE_LAST_Msk = 0x70000000

	// TO: Setting time out control for receiving data.
	// Position of TIME_OUT_VALUE field.
	I2C_TO_TIME_OUT_VALUE_Pos = 0x0
	// Bit mask of TIME_OUT_VALUE field.
	I2C_TO_TIME_OUT_VALUE_Msk = 0x1f
	// Position of TIME_OUT_EN field.
	I2C_TO_TIME_OUT_EN_Pos = 0x5
	// Bit mask of TIME_OUT_EN field.
	I2C_TO_TIME_OUT_EN_Msk = 0x20
	// Bit TIME_OUT_EN.
	I2C_TO_TIME_OUT_EN = 0x20

	// SLAVE_ADDR: Local slave address setting
	// Position of SLAVE_ADDR field.
	I2C_SLAVE_ADDR_SLAVE_ADDR_Pos = 0x0
	// Bit mask of SLAVE_ADDR field.
	I2C_SLAVE_ADDR_SLAVE_ADDR_Msk = 0x7fff
	// Position of ADDR_10BIT_EN field.
	I2C_SLAVE_ADDR_ADDR_10BIT_EN_Pos = 0x1f
	// Bit mask of ADDR_10BIT_EN field.
	I2C_SLAVE_ADDR_ADDR_10BIT_EN_Msk = 0x80000000
	// Bit ADDR_10BIT_EN.
	I2C_SLAVE_ADDR_ADDR_10BIT_EN = 0x80000000

	// FIFO_ST: FIFO status register.
	// Position of RXFIFO_RADDR field.
	I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0
	// Bit mask of RXFIFO_RADDR field.
	I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0x1f
	// Position of RXFIFO_WADDR field.
	I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5
	// Bit mask of RXFIFO_WADDR field.
	I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x3e0
	// Position of TXFIFO_RADDR field.
	I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa
	// Bit mask of TXFIFO_RADDR field.
	I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x7c00
	// Position of TXFIFO_WADDR field.
	I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf
	// Bit mask of TXFIFO_WADDR field.
	I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0xf8000
	// Position of SLAVE_RW_POINT field.
	I2C_FIFO_ST_SLAVE_RW_POINT_Pos = 0x16
	// Bit mask of SLAVE_RW_POINT field.
	I2C_FIFO_ST_SLAVE_RW_POINT_Msk = 0x3fc00000

	// FIFO_CONF: FIFO configuration register.
	// Position of RXFIFO_WM_THRHD field.
	I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0
	// Bit mask of RXFIFO_WM_THRHD field.
	I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0x1f
	// Position of TXFIFO_WM_THRHD field.
	I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5
	// Bit mask of TXFIFO_WM_THRHD field.
	I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x3e0
	// Position of NONFIFO_EN field.
	I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa
	// Bit mask of NONFIFO_EN field.
	I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400
	// Bit NONFIFO_EN.
	I2C_FIFO_CONF_NONFIFO_EN = 0x400
	// Position of FIFO_ADDR_CFG_EN field.
	I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Pos = 0xb
	// Bit mask of FIFO_ADDR_CFG_EN field.
	I2C_FIFO_CONF_FIFO_ADDR_CFG_EN_Msk = 0x800
	// Bit FIFO_ADDR_CFG_EN.
	I2C_FIFO_CONF_FIFO_ADDR_CFG_EN = 0x800
	// Position of RX_FIFO_RST field.
	I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc
	// Bit mask of RX_FIFO_RST field.
	I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000
	// Bit RX_FIFO_RST.
	I2C_FIFO_CONF_RX_FIFO_RST = 0x1000
	// Position of TX_FIFO_RST field.
	I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd
	// Bit mask of TX_FIFO_RST field.
	I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000
	// Bit TX_FIFO_RST.
	I2C_FIFO_CONF_TX_FIFO_RST = 0x2000
	// Position of FIFO_PRT_EN field.
	I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe
	// Bit mask of FIFO_PRT_EN field.
	I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000
	// Bit FIFO_PRT_EN.
	I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000

	// DATA: Rx FIFO read data.
	// Position of FIFO_RDATA field.
	I2C_DATA_FIFO_RDATA_Pos = 0x0
	// Bit mask of FIFO_RDATA field.
	I2C_DATA_FIFO_RDATA_Msk = 0xff

	// INT_RAW: Raw interrupt status
	// Position of RXFIFO_WM_INT_RAW field.
	I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_RAW field.
	I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1
	// Bit RXFIFO_WM_INT_RAW.
	I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1
	// Position of TXFIFO_WM_INT_RAW field.
	I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_RAW field.
	I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2
	// Bit TXFIFO_WM_INT_RAW.
	I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2
	// Position of RXFIFO_OVF_INT_RAW field.
	I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_RAW field.
	I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4
	// Bit RXFIFO_OVF_INT_RAW.
	I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4
	// Position of END_DETECT_INT_RAW field.
	I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3
	// Bit mask of END_DETECT_INT_RAW field.
	I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8
	// Bit END_DETECT_INT_RAW.
	I2C_INT_RAW_END_DETECT_INT_RAW = 0x8
	// Position of BYTE_TRANS_DONE_INT_RAW field.
	I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_RAW field.
	I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_RAW.
	I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10
	// Position of ARBITRATION_LOST_INT_RAW field.
	I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_RAW field.
	I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_RAW.
	I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20
	// Position of MST_TXFIFO_UDF_INT_RAW field.
	I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_RAW field.
	I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_RAW.
	I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40
	// Position of TRANS_COMPLETE_INT_RAW field.
	I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_RAW field.
	I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_RAW.
	I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80
	// Position of TIME_OUT_INT_RAW field.
	I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8
	// Bit mask of TIME_OUT_INT_RAW field.
	I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100
	// Bit TIME_OUT_INT_RAW.
	I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100
	// Position of TRANS_START_INT_RAW field.
	I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9
	// Bit mask of TRANS_START_INT_RAW field.
	I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200
	// Bit TRANS_START_INT_RAW.
	I2C_INT_RAW_TRANS_START_INT_RAW = 0x200
	// Position of NACK_INT_RAW field.
	I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa
	// Bit mask of NACK_INT_RAW field.
	I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400
	// Bit NACK_INT_RAW.
	I2C_INT_RAW_NACK_INT_RAW = 0x400
	// Position of TXFIFO_OVF_INT_RAW field.
	I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_RAW field.
	I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800
	// Bit TXFIFO_OVF_INT_RAW.
	I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800
	// Position of RXFIFO_UDF_INT_RAW field.
	I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_RAW field.
	I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_RAW.
	I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000
	// Position of SCL_ST_TO_INT_RAW field.
	I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_RAW field.
	I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000
	// Bit SCL_ST_TO_INT_RAW.
	I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_RAW field.
	I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_RAW field.
	I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_RAW.
	I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000
	// Position of DET_START_INT_RAW field.
	I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf
	// Bit mask of DET_START_INT_RAW field.
	I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000
	// Bit DET_START_INT_RAW.
	I2C_INT_RAW_DET_START_INT_RAW = 0x8000
	// Position of SLAVE_STRETCH_INT_RAW field.
	I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Pos = 0x10
	// Bit mask of SLAVE_STRETCH_INT_RAW field.
	I2C_INT_RAW_SLAVE_STRETCH_INT_RAW_Msk = 0x10000
	// Bit SLAVE_STRETCH_INT_RAW.
	I2C_INT_RAW_SLAVE_STRETCH_INT_RAW = 0x10000
	// Position of GENERAL_CALL_INT_RAW field.
	I2C_INT_RAW_GENERAL_CALL_INT_RAW_Pos = 0x11
	// Bit mask of GENERAL_CALL_INT_RAW field.
	I2C_INT_RAW_GENERAL_CALL_INT_RAW_Msk = 0x20000
	// Bit GENERAL_CALL_INT_RAW.
	I2C_INT_RAW_GENERAL_CALL_INT_RAW = 0x20000
	// Position of SLAVE_ADDR_UNMATCH_INT_RAW field.
	I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW_Pos = 0x12
	// Bit mask of SLAVE_ADDR_UNMATCH_INT_RAW field.
	I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW_Msk = 0x40000
	// Bit SLAVE_ADDR_UNMATCH_INT_RAW.
	I2C_INT_RAW_SLAVE_ADDR_UNMATCH_INT_RAW = 0x40000

	// INT_CLR: Interrupt clear bits
	// Position of RXFIFO_WM_INT_CLR field.
	I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_CLR field.
	I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1
	// Bit RXFIFO_WM_INT_CLR.
	I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1
	// Position of TXFIFO_WM_INT_CLR field.
	I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_CLR field.
	I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2
	// Bit TXFIFO_WM_INT_CLR.
	I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2
	// Position of RXFIFO_OVF_INT_CLR field.
	I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_CLR field.
	I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4
	// Bit RXFIFO_OVF_INT_CLR.
	I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4
	// Position of END_DETECT_INT_CLR field.
	I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3
	// Bit mask of END_DETECT_INT_CLR field.
	I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8
	// Bit END_DETECT_INT_CLR.
	I2C_INT_CLR_END_DETECT_INT_CLR = 0x8
	// Position of BYTE_TRANS_DONE_INT_CLR field.
	I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_CLR field.
	I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_CLR.
	I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10
	// Position of ARBITRATION_LOST_INT_CLR field.
	I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_CLR field.
	I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_CLR.
	I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20
	// Position of MST_TXFIFO_UDF_INT_CLR field.
	I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_CLR field.
	I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_CLR.
	I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40
	// Position of TRANS_COMPLETE_INT_CLR field.
	I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_CLR field.
	I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_CLR.
	I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80
	// Position of TIME_OUT_INT_CLR field.
	I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8
	// Bit mask of TIME_OUT_INT_CLR field.
	I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100
	// Bit TIME_OUT_INT_CLR.
	I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100
	// Position of TRANS_START_INT_CLR field.
	I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9
	// Bit mask of TRANS_START_INT_CLR field.
	I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200
	// Bit TRANS_START_INT_CLR.
	I2C_INT_CLR_TRANS_START_INT_CLR = 0x200
	// Position of NACK_INT_CLR field.
	I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa
	// Bit mask of NACK_INT_CLR field.
	I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400
	// Bit NACK_INT_CLR.
	I2C_INT_CLR_NACK_INT_CLR = 0x400
	// Position of TXFIFO_OVF_INT_CLR field.
	I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_CLR field.
	I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800
	// Bit TXFIFO_OVF_INT_CLR.
	I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800
	// Position of RXFIFO_UDF_INT_CLR field.
	I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_CLR field.
	I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_CLR.
	I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000
	// Position of SCL_ST_TO_INT_CLR field.
	I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_CLR field.
	I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000
	// Bit SCL_ST_TO_INT_CLR.
	I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_CLR field.
	I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_CLR field.
	I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_CLR.
	I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000
	// Position of DET_START_INT_CLR field.
	I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf
	// Bit mask of DET_START_INT_CLR field.
	I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000
	// Bit DET_START_INT_CLR.
	I2C_INT_CLR_DET_START_INT_CLR = 0x8000
	// Position of SLAVE_STRETCH_INT_CLR field.
	I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Pos = 0x10
	// Bit mask of SLAVE_STRETCH_INT_CLR field.
	I2C_INT_CLR_SLAVE_STRETCH_INT_CLR_Msk = 0x10000
	// Bit SLAVE_STRETCH_INT_CLR.
	I2C_INT_CLR_SLAVE_STRETCH_INT_CLR = 0x10000
	// Position of GENERAL_CALL_INT_CLR field.
	I2C_INT_CLR_GENERAL_CALL_INT_CLR_Pos = 0x11
	// Bit mask of GENERAL_CALL_INT_CLR field.
	I2C_INT_CLR_GENERAL_CALL_INT_CLR_Msk = 0x20000
	// Bit GENERAL_CALL_INT_CLR.
	I2C_INT_CLR_GENERAL_CALL_INT_CLR = 0x20000
	// Position of SLAVE_ADDR_UNMATCH_INT_CLR field.
	I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR_Pos = 0x12
	// Bit mask of SLAVE_ADDR_UNMATCH_INT_CLR field.
	I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR_Msk = 0x40000
	// Bit SLAVE_ADDR_UNMATCH_INT_CLR.
	I2C_INT_CLR_SLAVE_ADDR_UNMATCH_INT_CLR = 0x40000

	// INT_ENA: Interrupt enable bits
	// Position of RXFIFO_WM_INT_ENA field.
	I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_ENA field.
	I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1
	// Bit RXFIFO_WM_INT_ENA.
	I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1
	// Position of TXFIFO_WM_INT_ENA field.
	I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_ENA field.
	I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2
	// Bit TXFIFO_WM_INT_ENA.
	I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2
	// Position of RXFIFO_OVF_INT_ENA field.
	I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_ENA field.
	I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4
	// Bit RXFIFO_OVF_INT_ENA.
	I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4
	// Position of END_DETECT_INT_ENA field.
	I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3
	// Bit mask of END_DETECT_INT_ENA field.
	I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8
	// Bit END_DETECT_INT_ENA.
	I2C_INT_ENA_END_DETECT_INT_ENA = 0x8
	// Position of BYTE_TRANS_DONE_INT_ENA field.
	I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_ENA field.
	I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_ENA.
	I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10
	// Position of ARBITRATION_LOST_INT_ENA field.
	I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_ENA field.
	I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_ENA.
	I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20
	// Position of MST_TXFIFO_UDF_INT_ENA field.
	I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_ENA field.
	I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_ENA.
	I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40
	// Position of TRANS_COMPLETE_INT_ENA field.
	I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_ENA field.
	I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_ENA.
	I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80
	// Position of TIME_OUT_INT_ENA field.
	I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8
	// Bit mask of TIME_OUT_INT_ENA field.
	I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100
	// Bit TIME_OUT_INT_ENA.
	I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100
	// Position of TRANS_START_INT_ENA field.
	I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9
	// Bit mask of TRANS_START_INT_ENA field.
	I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200
	// Bit TRANS_START_INT_ENA.
	I2C_INT_ENA_TRANS_START_INT_ENA = 0x200
	// Position of NACK_INT_ENA field.
	I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa
	// Bit mask of NACK_INT_ENA field.
	I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400
	// Bit NACK_INT_ENA.
	I2C_INT_ENA_NACK_INT_ENA = 0x400
	// Position of TXFIFO_OVF_INT_ENA field.
	I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_ENA field.
	I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800
	// Bit TXFIFO_OVF_INT_ENA.
	I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800
	// Position of RXFIFO_UDF_INT_ENA field.
	I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_ENA field.
	I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_ENA.
	I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000
	// Position of SCL_ST_TO_INT_ENA field.
	I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_ENA field.
	I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000
	// Bit SCL_ST_TO_INT_ENA.
	I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_ENA field.
	I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_ENA field.
	I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_ENA.
	I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000
	// Position of DET_START_INT_ENA field.
	I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf
	// Bit mask of DET_START_INT_ENA field.
	I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000
	// Bit DET_START_INT_ENA.
	I2C_INT_ENA_DET_START_INT_ENA = 0x8000
	// Position of SLAVE_STRETCH_INT_ENA field.
	I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Pos = 0x10
	// Bit mask of SLAVE_STRETCH_INT_ENA field.
	I2C_INT_ENA_SLAVE_STRETCH_INT_ENA_Msk = 0x10000
	// Bit SLAVE_STRETCH_INT_ENA.
	I2C_INT_ENA_SLAVE_STRETCH_INT_ENA = 0x10000
	// Position of GENERAL_CALL_INT_ENA field.
	I2C_INT_ENA_GENERAL_CALL_INT_ENA_Pos = 0x11
	// Bit mask of GENERAL_CALL_INT_ENA field.
	I2C_INT_ENA_GENERAL_CALL_INT_ENA_Msk = 0x20000
	// Bit GENERAL_CALL_INT_ENA.
	I2C_INT_ENA_GENERAL_CALL_INT_ENA = 0x20000
	// Position of SLAVE_ADDR_UNMATCH_INT_ENA field.
	I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA_Pos = 0x12
	// Bit mask of SLAVE_ADDR_UNMATCH_INT_ENA field.
	I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA_Msk = 0x40000
	// Bit SLAVE_ADDR_UNMATCH_INT_ENA.
	I2C_INT_ENA_SLAVE_ADDR_UNMATCH_INT_ENA = 0x40000

	// INT_STATUS: Status of captured I2C communication events
	// Position of RXFIFO_WM_INT_ST field.
	I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_ST field.
	I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1
	// Bit RXFIFO_WM_INT_ST.
	I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1
	// Position of TXFIFO_WM_INT_ST field.
	I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_ST field.
	I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2
	// Bit TXFIFO_WM_INT_ST.
	I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2
	// Position of RXFIFO_OVF_INT_ST field.
	I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_ST field.
	I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4
	// Bit RXFIFO_OVF_INT_ST.
	I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4
	// Position of END_DETECT_INT_ST field.
	I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3
	// Bit mask of END_DETECT_INT_ST field.
	I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8
	// Bit END_DETECT_INT_ST.
	I2C_INT_STATUS_END_DETECT_INT_ST = 0x8
	// Position of BYTE_TRANS_DONE_INT_ST field.
	I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_ST field.
	I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_ST.
	I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10
	// Position of ARBITRATION_LOST_INT_ST field.
	I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_ST field.
	I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_ST.
	I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20
	// Position of MST_TXFIFO_UDF_INT_ST field.
	I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_ST field.
	I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_ST.
	I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40
	// Position of TRANS_COMPLETE_INT_ST field.
	I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_ST field.
	I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_ST.
	I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80
	// Position of TIME_OUT_INT_ST field.
	I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8
	// Bit mask of TIME_OUT_INT_ST field.
	I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100
	// Bit TIME_OUT_INT_ST.
	I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100
	// Position of TRANS_START_INT_ST field.
	I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9
	// Bit mask of TRANS_START_INT_ST field.
	I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200
	// Bit TRANS_START_INT_ST.
	I2C_INT_STATUS_TRANS_START_INT_ST = 0x200
	// Position of NACK_INT_ST field.
	I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa
	// Bit mask of NACK_INT_ST field.
	I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400
	// Bit NACK_INT_ST.
	I2C_INT_STATUS_NACK_INT_ST = 0x400
	// Position of TXFIFO_OVF_INT_ST field.
	I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_ST field.
	I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800
	// Bit TXFIFO_OVF_INT_ST.
	I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800
	// Position of RXFIFO_UDF_INT_ST field.
	I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_ST field.
	I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_ST.
	I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000
	// Position of SCL_ST_TO_INT_ST field.
	I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_ST field.
	I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000
	// Bit SCL_ST_TO_INT_ST.
	I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_ST field.
	I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_ST field.
	I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_ST.
	I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000
	// Position of DET_START_INT_ST field.
	I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf
	// Bit mask of DET_START_INT_ST field.
	I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000
	// Bit DET_START_INT_ST.
	I2C_INT_STATUS_DET_START_INT_ST = 0x8000
	// Position of SLAVE_STRETCH_INT_ST field.
	I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Pos = 0x10
	// Bit mask of SLAVE_STRETCH_INT_ST field.
	I2C_INT_STATUS_SLAVE_STRETCH_INT_ST_Msk = 0x10000
	// Bit SLAVE_STRETCH_INT_ST.
	I2C_INT_STATUS_SLAVE_STRETCH_INT_ST = 0x10000
	// Position of GENERAL_CALL_INT_ST field.
	I2C_INT_STATUS_GENERAL_CALL_INT_ST_Pos = 0x11
	// Bit mask of GENERAL_CALL_INT_ST field.
	I2C_INT_STATUS_GENERAL_CALL_INT_ST_Msk = 0x20000
	// Bit GENERAL_CALL_INT_ST.
	I2C_INT_STATUS_GENERAL_CALL_INT_ST = 0x20000
	// Position of SLAVE_ADDR_UNMATCH_INT_ST field.
	I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST_Pos = 0x12
	// Bit mask of SLAVE_ADDR_UNMATCH_INT_ST field.
	I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST_Msk = 0x40000
	// Bit SLAVE_ADDR_UNMATCH_INT_ST.
	I2C_INT_STATUS_SLAVE_ADDR_UNMATCH_INT_ST = 0x40000

	// SDA_HOLD: Configures the hold time after a negative SCL edge.
	// Position of TIME field.
	I2C_SDA_HOLD_TIME_Pos = 0x0
	// Bit mask of TIME field.
	I2C_SDA_HOLD_TIME_Msk = 0x1ff

	// SDA_SAMPLE: Configures the sample time after a positive SCL edge.
	// Position of TIME field.
	I2C_SDA_SAMPLE_TIME_Pos = 0x0
	// Bit mask of TIME field.
	I2C_SDA_SAMPLE_TIME_Msk = 0x1ff

	// SCL_HIGH_PERIOD: Configures the high level width of SCL
	// Position of SCL_HIGH_PERIOD field.
	I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0
	// Bit mask of SCL_HIGH_PERIOD field.
	I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff
	// Position of SCL_WAIT_HIGH_PERIOD field.
	I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9
	// Bit mask of SCL_WAIT_HIGH_PERIOD field.
	I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00

	// SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition
	// Position of TIME field.
	I2C_SCL_START_HOLD_TIME_Pos = 0x0
	// Bit mask of TIME field.
	I2C_SCL_START_HOLD_TIME_Msk = 0x1ff

	// SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA
	// Position of TIME field.
	I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0
	// Bit mask of TIME field.
	I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff

	// SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition
	// Position of TIME field.
	I2C_SCL_STOP_HOLD_TIME_Pos = 0x0
	// Bit mask of TIME field.
	I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff

	// SCL_STOP_SETUP: Configures the delay between the SDA and SCL rising edge for a stop condition. Measurement unit: i2c_sclk
	// Position of TIME field.
	I2C_SCL_STOP_SETUP_TIME_Pos = 0x0
	// Bit mask of TIME field.
	I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff

	// FILTER_CFG: SCL and SDA filter configuration register
	// Position of SCL_FILTER_THRES field.
	I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0
	// Bit mask of SCL_FILTER_THRES field.
	I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf
	// Position of SDA_FILTER_THRES field.
	I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4
	// Bit mask of SDA_FILTER_THRES field.
	I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0
	// Position of SCL_FILTER_EN field.
	I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8
	// Bit mask of SCL_FILTER_EN field.
	I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100
	// Bit SCL_FILTER_EN.
	I2C_FILTER_CFG_SCL_FILTER_EN = 0x100
	// Position of SDA_FILTER_EN field.
	I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9
	// Bit mask of SDA_FILTER_EN field.
	I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200
	// Bit SDA_FILTER_EN.
	I2C_FILTER_CFG_SDA_FILTER_EN = 0x200

	// CLK_CONF: I2C CLK configuration register
	// Position of SCLK_DIV_NUM field.
	I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0
	// Bit mask of SCLK_DIV_NUM field.
	I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff
	// Position of SCLK_DIV_A field.
	I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8
	// Bit mask of SCLK_DIV_A field.
	I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00
	// Position of SCLK_DIV_B field.
	I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe
	// Bit mask of SCLK_DIV_B field.
	I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000
	// Position of SCLK_SEL field.
	I2C_CLK_CONF_SCLK_SEL_Pos = 0x14
	// Bit mask of SCLK_SEL field.
	I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000
	// Bit SCLK_SEL.
	I2C_CLK_CONF_SCLK_SEL = 0x100000
	// Position of SCLK_ACTIVE field.
	I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15
	// Bit mask of SCLK_ACTIVE field.
	I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000
	// Bit SCLK_ACTIVE.
	I2C_CLK_CONF_SCLK_ACTIVE = 0x200000

	// COMD0: I2C command register 0
	// Position of COMMAND0 field.
	I2C_COMD0_COMMAND0_Pos = 0x0
	// Bit mask of COMMAND0 field.
	I2C_COMD0_COMMAND0_Msk = 0x3fff
	// Position of COMMAND0_DONE field.
	I2C_COMD0_COMMAND0_DONE_Pos = 0x1f
	// Bit mask of COMMAND0_DONE field.
	I2C_COMD0_COMMAND0_DONE_Msk = 0x80000000
	// Bit COMMAND0_DONE.
	I2C_COMD0_COMMAND0_DONE = 0x80000000

	// COMD1: I2C command register 1
	// Position of COMMAND1 field.
	I2C_COMD1_COMMAND1_Pos = 0x0
	// Bit mask of COMMAND1 field.
	I2C_COMD1_COMMAND1_Msk = 0x3fff
	// Position of COMMAND1_DONE field.
	I2C_COMD1_COMMAND1_DONE_Pos = 0x1f
	// Bit mask of COMMAND1_DONE field.
	I2C_COMD1_COMMAND1_DONE_Msk = 0x80000000
	// Bit COMMAND1_DONE.
	I2C_COMD1_COMMAND1_DONE = 0x80000000

	// COMD2: I2C command register 2
	// Position of COMMAND2 field.
	I2C_COMD2_COMMAND2_Pos = 0x0
	// Bit mask of COMMAND2 field.
	I2C_COMD2_COMMAND2_Msk = 0x3fff
	// Position of COMMAND2_DONE field.
	I2C_COMD2_COMMAND2_DONE_Pos = 0x1f
	// Bit mask of COMMAND2_DONE field.
	I2C_COMD2_COMMAND2_DONE_Msk = 0x80000000
	// Bit COMMAND2_DONE.
	I2C_COMD2_COMMAND2_DONE = 0x80000000

	// COMD3: I2C command register 3
	// Position of COMMAND3 field.
	I2C_COMD3_COMMAND3_Pos = 0x0
	// Bit mask of COMMAND3 field.
	I2C_COMD3_COMMAND3_Msk = 0x3fff
	// Position of COMMAND3_DONE field.
	I2C_COMD3_COMMAND3_DONE_Pos = 0x1f
	// Bit mask of COMMAND3_DONE field.
	I2C_COMD3_COMMAND3_DONE_Msk = 0x80000000
	// Bit COMMAND3_DONE.
	I2C_COMD3_COMMAND3_DONE = 0x80000000

	// COMD4: I2C command register 4
	// Position of COMMAND4 field.
	I2C_COMD4_COMMAND4_Pos = 0x0
	// Bit mask of COMMAND4 field.
	I2C_COMD4_COMMAND4_Msk = 0x3fff
	// Position of COMMAND4_DONE field.
	I2C_COMD4_COMMAND4_DONE_Pos = 0x1f
	// Bit mask of COMMAND4_DONE field.
	I2C_COMD4_COMMAND4_DONE_Msk = 0x80000000
	// Bit COMMAND4_DONE.
	I2C_COMD4_COMMAND4_DONE = 0x80000000

	// COMD5: I2C command register 5
	// Position of COMMAND5 field.
	I2C_COMD5_COMMAND5_Pos = 0x0
	// Bit mask of COMMAND5 field.
	I2C_COMD5_COMMAND5_Msk = 0x3fff
	// Position of COMMAND5_DONE field.
	I2C_COMD5_COMMAND5_DONE_Pos = 0x1f
	// Bit mask of COMMAND5_DONE field.
	I2C_COMD5_COMMAND5_DONE_Msk = 0x80000000
	// Bit COMMAND5_DONE.
	I2C_COMD5_COMMAND5_DONE = 0x80000000

	// COMD6: I2C command register 6
	// Position of COMMAND6 field.
	I2C_COMD6_COMMAND6_Pos = 0x0
	// Bit mask of COMMAND6 field.
	I2C_COMD6_COMMAND6_Msk = 0x3fff
	// Position of COMMAND6_DONE field.
	I2C_COMD6_COMMAND6_DONE_Pos = 0x1f
	// Bit mask of COMMAND6_DONE field.
	I2C_COMD6_COMMAND6_DONE_Msk = 0x80000000
	// Bit COMMAND6_DONE.
	I2C_COMD6_COMMAND6_DONE = 0x80000000

	// COMD7: I2C command register 7
	// Position of COMMAND7 field.
	I2C_COMD7_COMMAND7_Pos = 0x0
	// Bit mask of COMMAND7 field.
	I2C_COMD7_COMMAND7_Msk = 0x3fff
	// Position of COMMAND7_DONE field.
	I2C_COMD7_COMMAND7_DONE_Pos = 0x1f
	// Bit mask of COMMAND7_DONE field.
	I2C_COMD7_COMMAND7_DONE_Msk = 0x80000000
	// Bit COMMAND7_DONE.
	I2C_COMD7_COMMAND7_DONE = 0x80000000

	// SCL_ST_TIME_OUT: SCL status time out register
	// Position of SCL_ST_TO_I2C field.
	I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0
	// Bit mask of SCL_ST_TO_I2C field.
	I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f

	// SCL_MAIN_ST_TIME_OUT: SCL main status time out register
	// Position of SCL_MAIN_ST_TO_I2C field.
	I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0
	// Bit mask of SCL_MAIN_ST_TO_I2C field.
	I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f

	// SCL_SP_CONF: Power configuration register
	// Position of SCL_RST_SLV_EN field.
	I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0
	// Bit mask of SCL_RST_SLV_EN field.
	I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1
	// Bit SCL_RST_SLV_EN.
	I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1
	// Position of SCL_RST_SLV_NUM field.
	I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1
	// Bit mask of SCL_RST_SLV_NUM field.
	I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e
	// Position of SCL_PD_EN field.
	I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6
	// Bit mask of SCL_PD_EN field.
	I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40
	// Bit SCL_PD_EN.
	I2C_SCL_SP_CONF_SCL_PD_EN = 0x40
	// Position of SDA_PD_EN field.
	I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7
	// Bit mask of SDA_PD_EN field.
	I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80
	// Bit SDA_PD_EN.
	I2C_SCL_SP_CONF_SDA_PD_EN = 0x80

	// SCL_STRETCH_CONF: Set SCL stretch of I2C slave
	// Position of STRETCH_PROTECT_NUM field.
	I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Pos = 0x0
	// Bit mask of STRETCH_PROTECT_NUM field.
	I2C_SCL_STRETCH_CONF_STRETCH_PROTECT_NUM_Msk = 0x3ff
	// Position of SLAVE_SCL_STRETCH_EN field.
	I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Pos = 0xa
	// Bit mask of SLAVE_SCL_STRETCH_EN field.
	I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN_Msk = 0x400
	// Bit SLAVE_SCL_STRETCH_EN.
	I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_EN = 0x400
	// Position of SLAVE_SCL_STRETCH_CLR field.
	I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Pos = 0xb
	// Bit mask of SLAVE_SCL_STRETCH_CLR field.
	I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR_Msk = 0x800
	// Bit SLAVE_SCL_STRETCH_CLR.
	I2C_SCL_STRETCH_CONF_SLAVE_SCL_STRETCH_CLR = 0x800
	// Position of SLAVE_BYTE_ACK_CTL_EN field.
	I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Pos = 0xc
	// Bit mask of SLAVE_BYTE_ACK_CTL_EN field.
	I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN_Msk = 0x1000
	// Bit SLAVE_BYTE_ACK_CTL_EN.
	I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_CTL_EN = 0x1000
	// Position of SLAVE_BYTE_ACK_LVL field.
	I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Pos = 0xd
	// Bit mask of SLAVE_BYTE_ACK_LVL field.
	I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL_Msk = 0x2000
	// Bit SLAVE_BYTE_ACK_LVL.
	I2C_SCL_STRETCH_CONF_SLAVE_BYTE_ACK_LVL = 0x2000

	// DATE: Version register
	// Position of DATE field.
	I2C_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	I2C_DATE_DATE_Msk = 0xffffffff

	// TXFIFO_START_ADDR: I2C TXFIFO base address register
	// Position of TXFIFO_START_ADDR field.
	I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0
	// Bit mask of TXFIFO_START_ADDR field.
	I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff

	// RXFIFO_START_ADDR: I2C RXFIFO base address register
	// Position of RXFIFO_START_ADDR field.
	I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0
	// Bit mask of RXFIFO_START_ADDR field.
	I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff
)

// Constants for I2S0: I2S (Inter-IC Sound) Controller 0
const (
	// INT_RAW: I2S interrupt raw register, valid in level.
	// Position of RX_DONE_INT_RAW field.
	I2S_INT_RAW_RX_DONE_INT_RAW_Pos = 0x0
	// Bit mask of RX_DONE_INT_RAW field.
	I2S_INT_RAW_RX_DONE_INT_RAW_Msk = 0x1
	// Bit RX_DONE_INT_RAW.
	I2S_INT_RAW_RX_DONE_INT_RAW = 0x1
	// Position of TX_DONE_INT_RAW field.
	I2S_INT_RAW_TX_DONE_INT_RAW_Pos = 0x1
	// Bit mask of TX_DONE_INT_RAW field.
	I2S_INT_RAW_TX_DONE_INT_RAW_Msk = 0x2
	// Bit TX_DONE_INT_RAW.
	I2S_INT_RAW_TX_DONE_INT_RAW = 0x2
	// Position of RX_HUNG_INT_RAW field.
	I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2
	// Bit mask of RX_HUNG_INT_RAW field.
	I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4
	// Bit RX_HUNG_INT_RAW.
	I2S_INT_RAW_RX_HUNG_INT_RAW = 0x4
	// Position of TX_HUNG_INT_RAW field.
	I2S_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3
	// Bit mask of TX_HUNG_INT_RAW field.
	I2S_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8
	// Bit TX_HUNG_INT_RAW.
	I2S_INT_RAW_TX_HUNG_INT_RAW = 0x8

	// INT_ST: I2S interrupt status register.
	// Position of RX_DONE_INT_ST field.
	I2S_INT_ST_RX_DONE_INT_ST_Pos = 0x0
	// Bit mask of RX_DONE_INT_ST field.
	I2S_INT_ST_RX_DONE_INT_ST_Msk = 0x1
	// Bit RX_DONE_INT_ST.
	I2S_INT_ST_RX_DONE_INT_ST = 0x1
	// Position of TX_DONE_INT_ST field.
	I2S_INT_ST_TX_DONE_INT_ST_Pos = 0x1
	// Bit mask of TX_DONE_INT_ST field.
	I2S_INT_ST_TX_DONE_INT_ST_Msk = 0x2
	// Bit TX_DONE_INT_ST.
	I2S_INT_ST_TX_DONE_INT_ST = 0x2
	// Position of RX_HUNG_INT_ST field.
	I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x2
	// Bit mask of RX_HUNG_INT_ST field.
	I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x4
	// Bit RX_HUNG_INT_ST.
	I2S_INT_ST_RX_HUNG_INT_ST = 0x4
	// Position of TX_HUNG_INT_ST field.
	I2S_INT_ST_TX_HUNG_INT_ST_Pos = 0x3
	// Bit mask of TX_HUNG_INT_ST field.
	I2S_INT_ST_TX_HUNG_INT_ST_Msk = 0x8
	// Bit TX_HUNG_INT_ST.
	I2S_INT_ST_TX_HUNG_INT_ST = 0x8

	// INT_ENA: I2S interrupt enable register.
	// Position of RX_DONE_INT_ENA field.
	I2S_INT_ENA_RX_DONE_INT_ENA_Pos = 0x0
	// Bit mask of RX_DONE_INT_ENA field.
	I2S_INT_ENA_RX_DONE_INT_ENA_Msk = 0x1
	// Bit RX_DONE_INT_ENA.
	I2S_INT_ENA_RX_DONE_INT_ENA = 0x1
	// Position of TX_DONE_INT_ENA field.
	I2S_INT_ENA_TX_DONE_INT_ENA_Pos = 0x1
	// Bit mask of TX_DONE_INT_ENA field.
	I2S_INT_ENA_TX_DONE_INT_ENA_Msk = 0x2
	// Bit TX_DONE_INT_ENA.
	I2S_INT_ENA_TX_DONE_INT_ENA = 0x2
	// Position of RX_HUNG_INT_ENA field.
	I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2
	// Bit mask of RX_HUNG_INT_ENA field.
	I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4
	// Bit RX_HUNG_INT_ENA.
	I2S_INT_ENA_RX_HUNG_INT_ENA = 0x4
	// Position of TX_HUNG_INT_ENA field.
	I2S_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3
	// Bit mask of TX_HUNG_INT_ENA field.
	I2S_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8
	// Bit TX_HUNG_INT_ENA.
	I2S_INT_ENA_TX_HUNG_INT_ENA = 0x8

	// INT_CLR: I2S interrupt clear register.
	// Position of RX_DONE_INT_CLR field.
	I2S_INT_CLR_RX_DONE_INT_CLR_Pos = 0x0
	// Bit mask of RX_DONE_INT_CLR field.
	I2S_INT_CLR_RX_DONE_INT_CLR_Msk = 0x1
	// Bit RX_DONE_INT_CLR.
	I2S_INT_CLR_RX_DONE_INT_CLR = 0x1
	// Position of TX_DONE_INT_CLR field.
	I2S_INT_CLR_TX_DONE_INT_CLR_Pos = 0x1
	// Bit mask of TX_DONE_INT_CLR field.
	I2S_INT_CLR_TX_DONE_INT_CLR_Msk = 0x2
	// Bit TX_DONE_INT_CLR.
	I2S_INT_CLR_TX_DONE_INT_CLR = 0x2
	// Position of RX_HUNG_INT_CLR field.
	I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2
	// Bit mask of RX_HUNG_INT_CLR field.
	I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4
	// Bit RX_HUNG_INT_CLR.
	I2S_INT_CLR_RX_HUNG_INT_CLR = 0x4
	// Position of TX_HUNG_INT_CLR field.
	I2S_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3
	// Bit mask of TX_HUNG_INT_CLR field.
	I2S_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8
	// Bit TX_HUNG_INT_CLR.
	I2S_INT_CLR_TX_HUNG_INT_CLR = 0x8

	// RX_CONF: I2S RX configure register
	// Position of RX_RESET field.
	I2S_RX_CONF_RX_RESET_Pos = 0x0
	// Bit mask of RX_RESET field.
	I2S_RX_CONF_RX_RESET_Msk = 0x1
	// Bit RX_RESET.
	I2S_RX_CONF_RX_RESET = 0x1
	// Position of RX_FIFO_RESET field.
	I2S_RX_CONF_RX_FIFO_RESET_Pos = 0x1
	// Bit mask of RX_FIFO_RESET field.
	I2S_RX_CONF_RX_FIFO_RESET_Msk = 0x2
	// Bit RX_FIFO_RESET.
	I2S_RX_CONF_RX_FIFO_RESET = 0x2
	// Position of RX_START field.
	I2S_RX_CONF_RX_START_Pos = 0x2
	// Bit mask of RX_START field.
	I2S_RX_CONF_RX_START_Msk = 0x4
	// Bit RX_START.
	I2S_RX_CONF_RX_START = 0x4
	// Position of RX_SLAVE_MOD field.
	I2S_RX_CONF_RX_SLAVE_MOD_Pos = 0x3
	// Bit mask of RX_SLAVE_MOD field.
	I2S_RX_CONF_RX_SLAVE_MOD_Msk = 0x8
	// Bit RX_SLAVE_MOD.
	I2S_RX_CONF_RX_SLAVE_MOD = 0x8
	// Position of RX_STOP_MODE field.
	I2S_RX_CONF_RX_STOP_MODE_Pos = 0x4
	// Bit mask of RX_STOP_MODE field.
	I2S_RX_CONF_RX_STOP_MODE_Msk = 0x30
	// Position of RX_MONO field.
	I2S_RX_CONF_RX_MONO_Pos = 0x6
	// Bit mask of RX_MONO field.
	I2S_RX_CONF_RX_MONO_Msk = 0x40
	// Bit RX_MONO.
	I2S_RX_CONF_RX_MONO = 0x40
	// Position of RX_BIG_ENDIAN field.
	I2S_RX_CONF_RX_BIG_ENDIAN_Pos = 0x7
	// Bit mask of RX_BIG_ENDIAN field.
	I2S_RX_CONF_RX_BIG_ENDIAN_Msk = 0x80
	// Bit RX_BIG_ENDIAN.
	I2S_RX_CONF_RX_BIG_ENDIAN = 0x80
	// Position of RX_UPDATE field.
	I2S_RX_CONF_RX_UPDATE_Pos = 0x8
	// Bit mask of RX_UPDATE field.
	I2S_RX_CONF_RX_UPDATE_Msk = 0x100
	// Bit RX_UPDATE.
	I2S_RX_CONF_RX_UPDATE = 0x100
	// Position of RX_MONO_FST_VLD field.
	I2S_RX_CONF_RX_MONO_FST_VLD_Pos = 0x9
	// Bit mask of RX_MONO_FST_VLD field.
	I2S_RX_CONF_RX_MONO_FST_VLD_Msk = 0x200
	// Bit RX_MONO_FST_VLD.
	I2S_RX_CONF_RX_MONO_FST_VLD = 0x200
	// Position of RX_PCM_CONF field.
	I2S_RX_CONF_RX_PCM_CONF_Pos = 0xa
	// Bit mask of RX_PCM_CONF field.
	I2S_RX_CONF_RX_PCM_CONF_Msk = 0xc00
	// Position of RX_PCM_BYPASS field.
	I2S_RX_CONF_RX_PCM_BYPASS_Pos = 0xc
	// Bit mask of RX_PCM_BYPASS field.
	I2S_RX_CONF_RX_PCM_BYPASS_Msk = 0x1000
	// Bit RX_PCM_BYPASS.
	I2S_RX_CONF_RX_PCM_BYPASS = 0x1000
	// Position of RX_MSB_SHIFT field.
	I2S_RX_CONF_RX_MSB_SHIFT_Pos = 0xd
	// Bit mask of RX_MSB_SHIFT field.
	I2S_RX_CONF_RX_MSB_SHIFT_Msk = 0x2000
	// Bit RX_MSB_SHIFT.
	I2S_RX_CONF_RX_MSB_SHIFT = 0x2000
	// Position of RX_LEFT_ALIGN field.
	I2S_RX_CONF_RX_LEFT_ALIGN_Pos = 0xf
	// Bit mask of RX_LEFT_ALIGN field.
	I2S_RX_CONF_RX_LEFT_ALIGN_Msk = 0x8000
	// Bit RX_LEFT_ALIGN.
	I2S_RX_CONF_RX_LEFT_ALIGN = 0x8000
	// Position of RX_24_FILL_EN field.
	I2S_RX_CONF_RX_24_FILL_EN_Pos = 0x10
	// Bit mask of RX_24_FILL_EN field.
	I2S_RX_CONF_RX_24_FILL_EN_Msk = 0x10000
	// Bit RX_24_FILL_EN.
	I2S_RX_CONF_RX_24_FILL_EN = 0x10000
	// Position of RX_WS_IDLE_POL field.
	I2S_RX_CONF_RX_WS_IDLE_POL_Pos = 0x11
	// Bit mask of RX_WS_IDLE_POL field.
	I2S_RX_CONF_RX_WS_IDLE_POL_Msk = 0x20000
	// Bit RX_WS_IDLE_POL.
	I2S_RX_CONF_RX_WS_IDLE_POL = 0x20000
	// Position of RX_BIT_ORDER field.
	I2S_RX_CONF_RX_BIT_ORDER_Pos = 0x12
	// Bit mask of RX_BIT_ORDER field.
	I2S_RX_CONF_RX_BIT_ORDER_Msk = 0x40000
	// Bit RX_BIT_ORDER.
	I2S_RX_CONF_RX_BIT_ORDER = 0x40000
	// Position of RX_TDM_EN field.
	I2S_RX_CONF_RX_TDM_EN_Pos = 0x13
	// Bit mask of RX_TDM_EN field.
	I2S_RX_CONF_RX_TDM_EN_Msk = 0x80000
	// Bit RX_TDM_EN.
	I2S_RX_CONF_RX_TDM_EN = 0x80000
	// Position of RX_PDM_EN field.
	I2S_RX_CONF_RX_PDM_EN_Pos = 0x14
	// Bit mask of RX_PDM_EN field.
	I2S_RX_CONF_RX_PDM_EN_Msk = 0x100000
	// Bit RX_PDM_EN.
	I2S_RX_CONF_RX_PDM_EN = 0x100000
	// Position of RX_BCK_DIV_NUM field.
	I2S_RX_CONF_RX_BCK_DIV_NUM_Pos = 0x15
	// Bit mask of RX_BCK_DIV_NUM field.
	I2S_RX_CONF_RX_BCK_DIV_NUM_Msk = 0x7e00000

	// TX_CONF: I2S TX configure register
	// Position of TX_RESET field.
	I2S_TX_CONF_TX_RESET_Pos = 0x0
	// Bit mask of TX_RESET field.
	I2S_TX_CONF_TX_RESET_Msk = 0x1
	// Bit TX_RESET.
	I2S_TX_CONF_TX_RESET = 0x1
	// Position of TX_FIFO_RESET field.
	I2S_TX_CONF_TX_FIFO_RESET_Pos = 0x1
	// Bit mask of TX_FIFO_RESET field.
	I2S_TX_CONF_TX_FIFO_RESET_Msk = 0x2
	// Bit TX_FIFO_RESET.
	I2S_TX_CONF_TX_FIFO_RESET = 0x2
	// Position of TX_START field.
	I2S_TX_CONF_TX_START_Pos = 0x2
	// Bit mask of TX_START field.
	I2S_TX_CONF_TX_START_Msk = 0x4
	// Bit TX_START.
	I2S_TX_CONF_TX_START = 0x4
	// Position of TX_SLAVE_MOD field.
	I2S_TX_CONF_TX_SLAVE_MOD_Pos = 0x3
	// Bit mask of TX_SLAVE_MOD field.
	I2S_TX_CONF_TX_SLAVE_MOD_Msk = 0x8
	// Bit TX_SLAVE_MOD.
	I2S_TX_CONF_TX_SLAVE_MOD = 0x8
	// Position of TX_STOP_EN field.
	I2S_TX_CONF_TX_STOP_EN_Pos = 0x4
	// Bit mask of TX_STOP_EN field.
	I2S_TX_CONF_TX_STOP_EN_Msk = 0x10
	// Bit TX_STOP_EN.
	I2S_TX_CONF_TX_STOP_EN = 0x10
	// Position of TX_CHAN_EQUAL field.
	I2S_TX_CONF_TX_CHAN_EQUAL_Pos = 0x5
	// Bit mask of TX_CHAN_EQUAL field.
	I2S_TX_CONF_TX_CHAN_EQUAL_Msk = 0x20
	// Bit TX_CHAN_EQUAL.
	I2S_TX_CONF_TX_CHAN_EQUAL = 0x20
	// Position of TX_MONO field.
	I2S_TX_CONF_TX_MONO_Pos = 0x6
	// Bit mask of TX_MONO field.
	I2S_TX_CONF_TX_MONO_Msk = 0x40
	// Bit TX_MONO.
	I2S_TX_CONF_TX_MONO = 0x40
	// Position of TX_BIG_ENDIAN field.
	I2S_TX_CONF_TX_BIG_ENDIAN_Pos = 0x7
	// Bit mask of TX_BIG_ENDIAN field.
	I2S_TX_CONF_TX_BIG_ENDIAN_Msk = 0x80
	// Bit TX_BIG_ENDIAN.
	I2S_TX_CONF_TX_BIG_ENDIAN = 0x80
	// Position of TX_UPDATE field.
	I2S_TX_CONF_TX_UPDATE_Pos = 0x8
	// Bit mask of TX_UPDATE field.
	I2S_TX_CONF_TX_UPDATE_Msk = 0x100
	// Bit TX_UPDATE.
	I2S_TX_CONF_TX_UPDATE = 0x100
	// Position of TX_MONO_FST_VLD field.
	I2S_TX_CONF_TX_MONO_FST_VLD_Pos = 0x9
	// Bit mask of TX_MONO_FST_VLD field.
	I2S_TX_CONF_TX_MONO_FST_VLD_Msk = 0x200
	// Bit TX_MONO_FST_VLD.
	I2S_TX_CONF_TX_MONO_FST_VLD = 0x200
	// Position of TX_PCM_CONF field.
	I2S_TX_CONF_TX_PCM_CONF_Pos = 0xa
	// Bit mask of TX_PCM_CONF field.
	I2S_TX_CONF_TX_PCM_CONF_Msk = 0xc00
	// Position of TX_PCM_BYPASS field.
	I2S_TX_CONF_TX_PCM_BYPASS_Pos = 0xc
	// Bit mask of TX_PCM_BYPASS field.
	I2S_TX_CONF_TX_PCM_BYPASS_Msk = 0x1000
	// Bit TX_PCM_BYPASS.
	I2S_TX_CONF_TX_PCM_BYPASS = 0x1000
	// Position of TX_MSB_SHIFT field.
	I2S_TX_CONF_TX_MSB_SHIFT_Pos = 0xd
	// Bit mask of TX_MSB_SHIFT field.
	I2S_TX_CONF_TX_MSB_SHIFT_Msk = 0x2000
	// Bit TX_MSB_SHIFT.
	I2S_TX_CONF_TX_MSB_SHIFT = 0x2000
	// Position of TX_BCK_NO_DLY field.
	I2S_TX_CONF_TX_BCK_NO_DLY_Pos = 0xe
	// Bit mask of TX_BCK_NO_DLY field.
	I2S_TX_CONF_TX_BCK_NO_DLY_Msk = 0x4000
	// Bit TX_BCK_NO_DLY.
	I2S_TX_CONF_TX_BCK_NO_DLY = 0x4000
	// Position of TX_LEFT_ALIGN field.
	I2S_TX_CONF_TX_LEFT_ALIGN_Pos = 0xf
	// Bit mask of TX_LEFT_ALIGN field.
	I2S_TX_CONF_TX_LEFT_ALIGN_Msk = 0x8000
	// Bit TX_LEFT_ALIGN.
	I2S_TX_CONF_TX_LEFT_ALIGN = 0x8000
	// Position of TX_24_FILL_EN field.
	I2S_TX_CONF_TX_24_FILL_EN_Pos = 0x10
	// Bit mask of TX_24_FILL_EN field.
	I2S_TX_CONF_TX_24_FILL_EN_Msk = 0x10000
	// Bit TX_24_FILL_EN.
	I2S_TX_CONF_TX_24_FILL_EN = 0x10000
	// Position of TX_WS_IDLE_POL field.
	I2S_TX_CONF_TX_WS_IDLE_POL_Pos = 0x11
	// Bit mask of TX_WS_IDLE_POL field.
	I2S_TX_CONF_TX_WS_IDLE_POL_Msk = 0x20000
	// Bit TX_WS_IDLE_POL.
	I2S_TX_CONF_TX_WS_IDLE_POL = 0x20000
	// Position of TX_BIT_ORDER field.
	I2S_TX_CONF_TX_BIT_ORDER_Pos = 0x12
	// Bit mask of TX_BIT_ORDER field.
	I2S_TX_CONF_TX_BIT_ORDER_Msk = 0x40000
	// Bit TX_BIT_ORDER.
	I2S_TX_CONF_TX_BIT_ORDER = 0x40000
	// Position of TX_TDM_EN field.
	I2S_TX_CONF_TX_TDM_EN_Pos = 0x13
	// Bit mask of TX_TDM_EN field.
	I2S_TX_CONF_TX_TDM_EN_Msk = 0x80000
	// Bit TX_TDM_EN.
	I2S_TX_CONF_TX_TDM_EN = 0x80000
	// Position of TX_PDM_EN field.
	I2S_TX_CONF_TX_PDM_EN_Pos = 0x14
	// Bit mask of TX_PDM_EN field.
	I2S_TX_CONF_TX_PDM_EN_Msk = 0x100000
	// Bit TX_PDM_EN.
	I2S_TX_CONF_TX_PDM_EN = 0x100000
	// Position of TX_BCK_DIV_NUM field.
	I2S_TX_CONF_TX_BCK_DIV_NUM_Pos = 0x15
	// Bit mask of TX_BCK_DIV_NUM field.
	I2S_TX_CONF_TX_BCK_DIV_NUM_Msk = 0x7e00000
	// Position of TX_CHAN_MOD field.
	I2S_TX_CONF_TX_CHAN_MOD_Pos = 0x1b
	// Bit mask of TX_CHAN_MOD field.
	I2S_TX_CONF_TX_CHAN_MOD_Msk = 0x38000000
	// Position of SIG_LOOPBACK field.
	I2S_TX_CONF_SIG_LOOPBACK_Pos = 0x1e
	// Bit mask of SIG_LOOPBACK field.
	I2S_TX_CONF_SIG_LOOPBACK_Msk = 0x40000000
	// Bit SIG_LOOPBACK.
	I2S_TX_CONF_SIG_LOOPBACK = 0x40000000

	// RX_CONF1: I2S RX configure register 1
	// Position of RX_TDM_WS_WIDTH field.
	I2S_RX_CONF1_RX_TDM_WS_WIDTH_Pos = 0x0
	// Bit mask of RX_TDM_WS_WIDTH field.
	I2S_RX_CONF1_RX_TDM_WS_WIDTH_Msk = 0x1ff
	// Position of RX_BITS_MOD field.
	I2S_RX_CONF1_RX_BITS_MOD_Pos = 0xe
	// Bit mask of RX_BITS_MOD field.
	I2S_RX_CONF1_RX_BITS_MOD_Msk = 0x7c000
	// Position of RX_HALF_SAMPLE_BITS field.
	I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Pos = 0x13
	// Bit mask of RX_HALF_SAMPLE_BITS field.
	I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Msk = 0x7f80000
	// Position of RX_TDM_CHAN_BITS field.
	I2S_RX_CONF1_RX_TDM_CHAN_BITS_Pos = 0x1b
	// Bit mask of RX_TDM_CHAN_BITS field.
	I2S_RX_CONF1_RX_TDM_CHAN_BITS_Msk = 0xf8000000

	// TX_CONF1: I2S TX configure register 1
	// Position of TX_TDM_WS_WIDTH field.
	I2S_TX_CONF1_TX_TDM_WS_WIDTH_Pos = 0x0
	// Bit mask of TX_TDM_WS_WIDTH field.
	I2S_TX_CONF1_TX_TDM_WS_WIDTH_Msk = 0x1ff
	// Position of TX_BITS_MOD field.
	I2S_TX_CONF1_TX_BITS_MOD_Pos = 0xe
	// Bit mask of TX_BITS_MOD field.
	I2S_TX_CONF1_TX_BITS_MOD_Msk = 0x7c000
	// Position of TX_HALF_SAMPLE_BITS field.
	I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Pos = 0x13
	// Bit mask of TX_HALF_SAMPLE_BITS field.
	I2S_TX_CONF1_TX_HALF_SAMPLE_BITS_Msk = 0x7f80000
	// Position of TX_TDM_CHAN_BITS field.
	I2S_TX_CONF1_TX_TDM_CHAN_BITS_Pos = 0x1b
	// Bit mask of TX_TDM_CHAN_BITS field.
	I2S_TX_CONF1_TX_TDM_CHAN_BITS_Msk = 0xf8000000

	// TX_PCM2PDM_CONF: I2S TX PCM2PDM configuration register
	// Position of TX_PDM_HP_BYPASS field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Pos = 0x0
	// Bit mask of TX_PDM_HP_BYPASS field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS_Msk = 0x1
	// Bit TX_PDM_HP_BYPASS.
	I2S_TX_PCM2PDM_CONF_TX_PDM_HP_BYPASS = 0x1
	// Position of TX_PDM_SINC_OSR2 field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Pos = 0x1
	// Bit mask of TX_PDM_SINC_OSR2 field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_OSR2_Msk = 0x1e
	// Position of TX_PDM_PRESCALE field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Pos = 0x5
	// Bit mask of TX_PDM_PRESCALE field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_PRESCALE_Msk = 0x1fe0
	// Position of TX_PDM_HP_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Pos = 0xd
	// Bit mask of TX_PDM_HP_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_HP_IN_SHIFT_Msk = 0x6000
	// Position of TX_PDM_LP_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Pos = 0xf
	// Bit mask of TX_PDM_LP_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_LP_IN_SHIFT_Msk = 0x18000
	// Position of TX_PDM_SINC_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Pos = 0x11
	// Bit mask of TX_PDM_SINC_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SINC_IN_SHIFT_Msk = 0x60000
	// Position of TX_PDM_SIGMADELTA_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Pos = 0x13
	// Bit mask of TX_PDM_SIGMADELTA_IN_SHIFT field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_IN_SHIFT_Msk = 0x180000
	// Position of TX_PDM_SIGMADELTA_DITHER2 field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Pos = 0x15
	// Bit mask of TX_PDM_SIGMADELTA_DITHER2 field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2_Msk = 0x200000
	// Bit TX_PDM_SIGMADELTA_DITHER2.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER2 = 0x200000
	// Position of TX_PDM_SIGMADELTA_DITHER field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Pos = 0x16
	// Bit mask of TX_PDM_SIGMADELTA_DITHER field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER_Msk = 0x400000
	// Bit TX_PDM_SIGMADELTA_DITHER.
	I2S_TX_PCM2PDM_CONF_TX_PDM_SIGMADELTA_DITHER = 0x400000
	// Position of TX_PDM_DAC_2OUT_EN field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Pos = 0x17
	// Bit mask of TX_PDM_DAC_2OUT_EN field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN_Msk = 0x800000
	// Bit TX_PDM_DAC_2OUT_EN.
	I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_2OUT_EN = 0x800000
	// Position of TX_PDM_DAC_MODE_EN field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Pos = 0x18
	// Bit mask of TX_PDM_DAC_MODE_EN field.
	I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN_Msk = 0x1000000
	// Bit TX_PDM_DAC_MODE_EN.
	I2S_TX_PCM2PDM_CONF_TX_PDM_DAC_MODE_EN = 0x1000000
	// Position of PCM2PDM_CONV_EN field.
	I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Pos = 0x19
	// Bit mask of PCM2PDM_CONV_EN field.
	I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN_Msk = 0x2000000
	// Bit PCM2PDM_CONV_EN.
	I2S_TX_PCM2PDM_CONF_PCM2PDM_CONV_EN = 0x2000000

	// TX_PCM2PDM_CONF1: I2S TX PCM2PDM configuration register
	// Position of TX_PDM_FP field.
	I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Pos = 0x0
	// Bit mask of TX_PDM_FP field.
	I2S_TX_PCM2PDM_CONF1_TX_PDM_FP_Msk = 0x3ff
	// Position of TX_PDM_FS field.
	I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Pos = 0xa
	// Bit mask of TX_PDM_FS field.
	I2S_TX_PCM2PDM_CONF1_TX_PDM_FS_Msk = 0xffc00
	// Position of TX_IIR_HP_MULT12_5 field.
	I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Pos = 0x14
	// Bit mask of TX_IIR_HP_MULT12_5 field.
	I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_5_Msk = 0x700000
	// Position of TX_IIR_HP_MULT12_0 field.
	I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Pos = 0x17
	// Bit mask of TX_IIR_HP_MULT12_0 field.
	I2S_TX_PCM2PDM_CONF1_TX_IIR_HP_MULT12_0_Msk = 0x3800000

	// RX_PDM2PCM_CONF: I2S RX configure register
	// Position of RX_PDM2PCM_EN field.
	I2S_RX_PDM2PCM_CONF_RX_PDM2PCM_EN_Pos = 0x13
	// Bit mask of RX_PDM2PCM_EN field.
	I2S_RX_PDM2PCM_CONF_RX_PDM2PCM_EN_Msk = 0x80000
	// Bit RX_PDM2PCM_EN.
	I2S_RX_PDM2PCM_CONF_RX_PDM2PCM_EN = 0x80000
	// Position of RX_PDM_SINC_DSR_16_EN field.
	I2S_RX_PDM2PCM_CONF_RX_PDM_SINC_DSR_16_EN_Pos = 0x14
	// Bit mask of RX_PDM_SINC_DSR_16_EN field.
	I2S_RX_PDM2PCM_CONF_RX_PDM_SINC_DSR_16_EN_Msk = 0x100000
	// Bit RX_PDM_SINC_DSR_16_EN.
	I2S_RX_PDM2PCM_CONF_RX_PDM_SINC_DSR_16_EN = 0x100000
	// Position of RX_PDM2PCM_AMPLIFY_NUM field.
	I2S_RX_PDM2PCM_CONF_RX_PDM2PCM_AMPLIFY_NUM_Pos = 0x15
	// Bit mask of RX_PDM2PCM_AMPLIFY_NUM field.
	I2S_RX_PDM2PCM_CONF_RX_PDM2PCM_AMPLIFY_NUM_Msk = 0x1e00000
	// Position of RX_PDM_HP_BYPASS field.
	I2S_RX_PDM2PCM_CONF_RX_PDM_HP_BYPASS_Pos = 0x19
	// Bit mask of RX_PDM_HP_BYPASS field.
	I2S_RX_PDM2PCM_CONF_RX_PDM_HP_BYPASS_Msk = 0x2000000
	// Bit RX_PDM_HP_BYPASS.
	I2S_RX_PDM2PCM_CONF_RX_PDM_HP_BYPASS = 0x2000000
	// Position of RX_IIR_HP_MULT12_5 field.
	I2S_RX_PDM2PCM_CONF_RX_IIR_HP_MULT12_5_Pos = 0x1a
	// Bit mask of RX_IIR_HP_MULT12_5 field.
	I2S_RX_PDM2PCM_CONF_RX_IIR_HP_MULT12_5_Msk = 0x1c000000
	// Position of RX_IIR_HP_MULT12_0 field.
	I2S_RX_PDM2PCM_CONF_RX_IIR_HP_MULT12_0_Pos = 0x1d
	// Bit mask of RX_IIR_HP_MULT12_0 field.
	I2S_RX_PDM2PCM_CONF_RX_IIR_HP_MULT12_0_Msk = 0xe0000000

	// RX_TDM_CTRL: I2S TX TDM mode control register
	// Position of RX_TDM_PDM_CHAN0_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Pos = 0x0
	// Bit mask of RX_TDM_PDM_CHAN0_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Msk = 0x1
	// Bit RX_TDM_PDM_CHAN0_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN = 0x1
	// Position of RX_TDM_PDM_CHAN1_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Pos = 0x1
	// Bit mask of RX_TDM_PDM_CHAN1_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Msk = 0x2
	// Bit RX_TDM_PDM_CHAN1_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN = 0x2
	// Position of RX_TDM_PDM_CHAN2_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Pos = 0x2
	// Bit mask of RX_TDM_PDM_CHAN2_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN_Msk = 0x4
	// Bit RX_TDM_PDM_CHAN2_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN2_EN = 0x4
	// Position of RX_TDM_PDM_CHAN3_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Pos = 0x3
	// Bit mask of RX_TDM_PDM_CHAN3_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN_Msk = 0x8
	// Bit RX_TDM_PDM_CHAN3_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN3_EN = 0x8
	// Position of RX_TDM_PDM_CHAN4_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Pos = 0x4
	// Bit mask of RX_TDM_PDM_CHAN4_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN_Msk = 0x10
	// Bit RX_TDM_PDM_CHAN4_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN4_EN = 0x10
	// Position of RX_TDM_PDM_CHAN5_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Pos = 0x5
	// Bit mask of RX_TDM_PDM_CHAN5_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN_Msk = 0x20
	// Bit RX_TDM_PDM_CHAN5_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN5_EN = 0x20
	// Position of RX_TDM_PDM_CHAN6_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Pos = 0x6
	// Bit mask of RX_TDM_PDM_CHAN6_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN_Msk = 0x40
	// Bit RX_TDM_PDM_CHAN6_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN6_EN = 0x40
	// Position of RX_TDM_PDM_CHAN7_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Pos = 0x7
	// Bit mask of RX_TDM_PDM_CHAN7_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN_Msk = 0x80
	// Bit RX_TDM_PDM_CHAN7_EN.
	I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN7_EN = 0x80
	// Position of RX_TDM_CHAN8_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Pos = 0x8
	// Bit mask of RX_TDM_CHAN8_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN_Msk = 0x100
	// Bit RX_TDM_CHAN8_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN8_EN = 0x100
	// Position of RX_TDM_CHAN9_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Pos = 0x9
	// Bit mask of RX_TDM_CHAN9_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN_Msk = 0x200
	// Bit RX_TDM_CHAN9_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN9_EN = 0x200
	// Position of RX_TDM_CHAN10_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Pos = 0xa
	// Bit mask of RX_TDM_CHAN10_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN_Msk = 0x400
	// Bit RX_TDM_CHAN10_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN10_EN = 0x400
	// Position of RX_TDM_CHAN11_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Pos = 0xb
	// Bit mask of RX_TDM_CHAN11_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN_Msk = 0x800
	// Bit RX_TDM_CHAN11_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN11_EN = 0x800
	// Position of RX_TDM_CHAN12_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Pos = 0xc
	// Bit mask of RX_TDM_CHAN12_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN_Msk = 0x1000
	// Bit RX_TDM_CHAN12_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN12_EN = 0x1000
	// Position of RX_TDM_CHAN13_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Pos = 0xd
	// Bit mask of RX_TDM_CHAN13_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN_Msk = 0x2000
	// Bit RX_TDM_CHAN13_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN13_EN = 0x2000
	// Position of RX_TDM_CHAN14_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Pos = 0xe
	// Bit mask of RX_TDM_CHAN14_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN_Msk = 0x4000
	// Bit RX_TDM_CHAN14_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN14_EN = 0x4000
	// Position of RX_TDM_CHAN15_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Pos = 0xf
	// Bit mask of RX_TDM_CHAN15_EN field.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN_Msk = 0x8000
	// Bit RX_TDM_CHAN15_EN.
	I2S_RX_TDM_CTRL_RX_TDM_CHAN15_EN = 0x8000
	// Position of RX_TDM_TOT_CHAN_NUM field.
	I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Pos = 0x10
	// Bit mask of RX_TDM_TOT_CHAN_NUM field.
	I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Msk = 0xf0000

	// TX_TDM_CTRL: I2S TX TDM mode control register
	// Position of TX_TDM_CHAN0_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Pos = 0x0
	// Bit mask of TX_TDM_CHAN0_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN_Msk = 0x1
	// Bit TX_TDM_CHAN0_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN0_EN = 0x1
	// Position of TX_TDM_CHAN1_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Pos = 0x1
	// Bit mask of TX_TDM_CHAN1_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN_Msk = 0x2
	// Bit TX_TDM_CHAN1_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN1_EN = 0x2
	// Position of TX_TDM_CHAN2_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Pos = 0x2
	// Bit mask of TX_TDM_CHAN2_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN_Msk = 0x4
	// Bit TX_TDM_CHAN2_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN2_EN = 0x4
	// Position of TX_TDM_CHAN3_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Pos = 0x3
	// Bit mask of TX_TDM_CHAN3_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN_Msk = 0x8
	// Bit TX_TDM_CHAN3_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN3_EN = 0x8
	// Position of TX_TDM_CHAN4_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Pos = 0x4
	// Bit mask of TX_TDM_CHAN4_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN_Msk = 0x10
	// Bit TX_TDM_CHAN4_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN4_EN = 0x10
	// Position of TX_TDM_CHAN5_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Pos = 0x5
	// Bit mask of TX_TDM_CHAN5_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN_Msk = 0x20
	// Bit TX_TDM_CHAN5_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN5_EN = 0x20
	// Position of TX_TDM_CHAN6_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Pos = 0x6
	// Bit mask of TX_TDM_CHAN6_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN_Msk = 0x40
	// Bit TX_TDM_CHAN6_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN6_EN = 0x40
	// Position of TX_TDM_CHAN7_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Pos = 0x7
	// Bit mask of TX_TDM_CHAN7_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN_Msk = 0x80
	// Bit TX_TDM_CHAN7_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN7_EN = 0x80
	// Position of TX_TDM_CHAN8_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Pos = 0x8
	// Bit mask of TX_TDM_CHAN8_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN_Msk = 0x100
	// Bit TX_TDM_CHAN8_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN8_EN = 0x100
	// Position of TX_TDM_CHAN9_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Pos = 0x9
	// Bit mask of TX_TDM_CHAN9_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN_Msk = 0x200
	// Bit TX_TDM_CHAN9_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN9_EN = 0x200
	// Position of TX_TDM_CHAN10_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Pos = 0xa
	// Bit mask of TX_TDM_CHAN10_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN_Msk = 0x400
	// Bit TX_TDM_CHAN10_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN10_EN = 0x400
	// Position of TX_TDM_CHAN11_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Pos = 0xb
	// Bit mask of TX_TDM_CHAN11_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN_Msk = 0x800
	// Bit TX_TDM_CHAN11_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN11_EN = 0x800
	// Position of TX_TDM_CHAN12_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Pos = 0xc
	// Bit mask of TX_TDM_CHAN12_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN_Msk = 0x1000
	// Bit TX_TDM_CHAN12_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN12_EN = 0x1000
	// Position of TX_TDM_CHAN13_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Pos = 0xd
	// Bit mask of TX_TDM_CHAN13_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN_Msk = 0x2000
	// Bit TX_TDM_CHAN13_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN13_EN = 0x2000
	// Position of TX_TDM_CHAN14_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Pos = 0xe
	// Bit mask of TX_TDM_CHAN14_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN_Msk = 0x4000
	// Bit TX_TDM_CHAN14_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN14_EN = 0x4000
	// Position of TX_TDM_CHAN15_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Pos = 0xf
	// Bit mask of TX_TDM_CHAN15_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN_Msk = 0x8000
	// Bit TX_TDM_CHAN15_EN.
	I2S_TX_TDM_CTRL_TX_TDM_CHAN15_EN = 0x8000
	// Position of TX_TDM_TOT_CHAN_NUM field.
	I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Pos = 0x10
	// Bit mask of TX_TDM_TOT_CHAN_NUM field.
	I2S_TX_TDM_CTRL_TX_TDM_TOT_CHAN_NUM_Msk = 0xf0000
	// Position of TX_TDM_SKIP_MSK_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Pos = 0x14
	// Bit mask of TX_TDM_SKIP_MSK_EN field.
	I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN_Msk = 0x100000
	// Bit TX_TDM_SKIP_MSK_EN.
	I2S_TX_TDM_CTRL_TX_TDM_SKIP_MSK_EN = 0x100000

	// RX_TIMING: I2S RX timing control register
	// Position of RX_SD_IN_DM field.
	I2S_RX_TIMING_RX_SD_IN_DM_Pos = 0x0
	// Bit mask of RX_SD_IN_DM field.
	I2S_RX_TIMING_RX_SD_IN_DM_Msk = 0x3
	// Position of RX_SD1_IN_DM field.
	I2S_RX_TIMING_RX_SD1_IN_DM_Pos = 0x4
	// Bit mask of RX_SD1_IN_DM field.
	I2S_RX_TIMING_RX_SD1_IN_DM_Msk = 0x30
	// Position of RX_SD2_IN_DM field.
	I2S_RX_TIMING_RX_SD2_IN_DM_Pos = 0x8
	// Bit mask of RX_SD2_IN_DM field.
	I2S_RX_TIMING_RX_SD2_IN_DM_Msk = 0x300
	// Position of RX_SD3_IN_DM field.
	I2S_RX_TIMING_RX_SD3_IN_DM_Pos = 0xc
	// Bit mask of RX_SD3_IN_DM field.
	I2S_RX_TIMING_RX_SD3_IN_DM_Msk = 0x3000
	// Position of RX_WS_OUT_DM field.
	I2S_RX_TIMING_RX_WS_OUT_DM_Pos = 0x10
	// Bit mask of RX_WS_OUT_DM field.
	I2S_RX_TIMING_RX_WS_OUT_DM_Msk = 0x30000
	// Position of RX_BCK_OUT_DM field.
	I2S_RX_TIMING_RX_BCK_OUT_DM_Pos = 0x14
	// Bit mask of RX_BCK_OUT_DM field.
	I2S_RX_TIMING_RX_BCK_OUT_DM_Msk = 0x300000
	// Position of RX_WS_IN_DM field.
	I2S_RX_TIMING_RX_WS_IN_DM_Pos = 0x18
	// Bit mask of RX_WS_IN_DM field.
	I2S_RX_TIMING_RX_WS_IN_DM_Msk = 0x3000000
	// Position of RX_BCK_IN_DM field.
	I2S_RX_TIMING_RX_BCK_IN_DM_Pos = 0x1c
	// Bit mask of RX_BCK_IN_DM field.
	I2S_RX_TIMING_RX_BCK_IN_DM_Msk = 0x30000000

	// TX_TIMING: I2S TX timing control register
	// Position of TX_SD_OUT_DM field.
	I2S_TX_TIMING_TX_SD_OUT_DM_Pos = 0x0
	// Bit mask of TX_SD_OUT_DM field.
	I2S_TX_TIMING_TX_SD_OUT_DM_Msk = 0x3
	// Position of TX_SD1_OUT_DM field.
	I2S_TX_TIMING_TX_SD1_OUT_DM_Pos = 0x4
	// Bit mask of TX_SD1_OUT_DM field.
	I2S_TX_TIMING_TX_SD1_OUT_DM_Msk = 0x30
	// Position of TX_WS_OUT_DM field.
	I2S_TX_TIMING_TX_WS_OUT_DM_Pos = 0x10
	// Bit mask of TX_WS_OUT_DM field.
	I2S_TX_TIMING_TX_WS_OUT_DM_Msk = 0x30000
	// Position of TX_BCK_OUT_DM field.
	I2S_TX_TIMING_TX_BCK_OUT_DM_Pos = 0x14
	// Bit mask of TX_BCK_OUT_DM field.
	I2S_TX_TIMING_TX_BCK_OUT_DM_Msk = 0x300000
	// Position of TX_WS_IN_DM field.
	I2S_TX_TIMING_TX_WS_IN_DM_Pos = 0x18
	// Bit mask of TX_WS_IN_DM field.
	I2S_TX_TIMING_TX_WS_IN_DM_Msk = 0x3000000
	// Position of TX_BCK_IN_DM field.
	I2S_TX_TIMING_TX_BCK_IN_DM_Pos = 0x1c
	// Bit mask of TX_BCK_IN_DM field.
	I2S_TX_TIMING_TX_BCK_IN_DM_Msk = 0x30000000

	// LC_HUNG_CONF: I2S HUNG configure register.
	// Position of LC_FIFO_TIMEOUT field.
	I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0
	// Bit mask of LC_FIFO_TIMEOUT field.
	I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff
	// Position of LC_FIFO_TIMEOUT_SHIFT field.
	I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8
	// Bit mask of LC_FIFO_TIMEOUT_SHIFT field.
	I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700
	// Position of LC_FIFO_TIMEOUT_ENA field.
	I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb
	// Bit mask of LC_FIFO_TIMEOUT_ENA field.
	I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800
	// Bit LC_FIFO_TIMEOUT_ENA.
	I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800

	// RXEOF_NUM: I2S RX data number control register.
	// Position of RX_EOF_NUM field.
	I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0
	// Bit mask of RX_EOF_NUM field.
	I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xfff

	// CONF_SIGLE_DATA: I2S signal data register
	// Position of SINGLE_DATA field.
	I2S_CONF_SIGLE_DATA_SINGLE_DATA_Pos = 0x0
	// Bit mask of SINGLE_DATA field.
	I2S_CONF_SIGLE_DATA_SINGLE_DATA_Msk = 0xffffffff

	// STATE: I2S TX status register
	// Position of TX_IDLE field.
	I2S_STATE_TX_IDLE_Pos = 0x0
	// Bit mask of TX_IDLE field.
	I2S_STATE_TX_IDLE_Msk = 0x1
	// Bit TX_IDLE.
	I2S_STATE_TX_IDLE = 0x1

	// ETM_CONF: I2S ETM configure register
	// Position of ETM_TX_SEND_WORD_NUM field.
	I2S_ETM_CONF_ETM_TX_SEND_WORD_NUM_Pos = 0x0
	// Bit mask of ETM_TX_SEND_WORD_NUM field.
	I2S_ETM_CONF_ETM_TX_SEND_WORD_NUM_Msk = 0x3ff
	// Position of ETM_RX_RECEIVE_WORD_NUM field.
	I2S_ETM_CONF_ETM_RX_RECEIVE_WORD_NUM_Pos = 0xa
	// Bit mask of ETM_RX_RECEIVE_WORD_NUM field.
	I2S_ETM_CONF_ETM_RX_RECEIVE_WORD_NUM_Msk = 0xffc00

	// FIFO_CNT: I2S sync counter register
	// Position of TX_FIFO_CNT field.
	I2S_FIFO_CNT_TX_FIFO_CNT_Pos = 0x0
	// Bit mask of TX_FIFO_CNT field.
	I2S_FIFO_CNT_TX_FIFO_CNT_Msk = 0x7fffffff
	// Position of TX_FIFO_CNT_RST field.
	I2S_FIFO_CNT_TX_FIFO_CNT_RST_Pos = 0x1f
	// Bit mask of TX_FIFO_CNT_RST field.
	I2S_FIFO_CNT_TX_FIFO_CNT_RST_Msk = 0x80000000
	// Bit TX_FIFO_CNT_RST.
	I2S_FIFO_CNT_TX_FIFO_CNT_RST = 0x80000000

	// BCK_CNT: I2S sync counter register
	// Position of TX_BCK_CNT field.
	I2S_BCK_CNT_TX_BCK_CNT_Pos = 0x0
	// Bit mask of TX_BCK_CNT field.
	I2S_BCK_CNT_TX_BCK_CNT_Msk = 0x7fffffff
	// Position of TX_BCK_CNT_RST field.
	I2S_BCK_CNT_TX_BCK_CNT_RST_Pos = 0x1f
	// Bit mask of TX_BCK_CNT_RST field.
	I2S_BCK_CNT_TX_BCK_CNT_RST_Msk = 0x80000000
	// Bit TX_BCK_CNT_RST.
	I2S_BCK_CNT_TX_BCK_CNT_RST = 0x80000000

	// CLK_GATE: Clock gate register
	// Position of CLK_EN field.
	I2S_CLK_GATE_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	I2S_CLK_GATE_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	I2S_CLK_GATE_CLK_EN = 0x1

	// DATE: Version control register
	// Position of DATE field.
	I2S_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	I2S_DATE_DATE_Msk = 0xfffffff
)

// Constants for I3C_MST: I3C Controller (Master)
const (
	// DEVICE_CTRL: DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities.
	// Position of REG_BA_INCLUDE field.
	I3C_MST_DEVICE_CTRL_REG_BA_INCLUDE_Pos = 0x1
	// Bit mask of REG_BA_INCLUDE field.
	I3C_MST_DEVICE_CTRL_REG_BA_INCLUDE_Msk = 0x2
	// Bit REG_BA_INCLUDE.
	I3C_MST_DEVICE_CTRL_REG_BA_INCLUDE = 0x2
	// Position of REG_TRANS_START field.
	I3C_MST_DEVICE_CTRL_REG_TRANS_START_Pos = 0x2
	// Bit mask of REG_TRANS_START field.
	I3C_MST_DEVICE_CTRL_REG_TRANS_START_Msk = 0x4
	// Bit REG_TRANS_START.
	I3C_MST_DEVICE_CTRL_REG_TRANS_START = 0x4
	// Position of REG_CLK_EN field.
	I3C_MST_DEVICE_CTRL_REG_CLK_EN_Pos = 0x3
	// Bit mask of REG_CLK_EN field.
	I3C_MST_DEVICE_CTRL_REG_CLK_EN_Msk = 0x8
	// Bit REG_CLK_EN.
	I3C_MST_DEVICE_CTRL_REG_CLK_EN = 0x8
	// Position of REG_IBI_RSTART_TRANS_EN field.
	I3C_MST_DEVICE_CTRL_REG_IBI_RSTART_TRANS_EN_Pos = 0x4
	// Bit mask of REG_IBI_RSTART_TRANS_EN field.
	I3C_MST_DEVICE_CTRL_REG_IBI_RSTART_TRANS_EN_Msk = 0x10
	// Bit REG_IBI_RSTART_TRANS_EN.
	I3C_MST_DEVICE_CTRL_REG_IBI_RSTART_TRANS_EN = 0x10
	// Position of REG_AUTO_DIS_IBI_EN field.
	I3C_MST_DEVICE_CTRL_REG_AUTO_DIS_IBI_EN_Pos = 0x5
	// Bit mask of REG_AUTO_DIS_IBI_EN field.
	I3C_MST_DEVICE_CTRL_REG_AUTO_DIS_IBI_EN_Msk = 0x20
	// Bit REG_AUTO_DIS_IBI_EN.
	I3C_MST_DEVICE_CTRL_REG_AUTO_DIS_IBI_EN = 0x20
	// Position of REG_DMA_RX_EN field.
	I3C_MST_DEVICE_CTRL_REG_DMA_RX_EN_Pos = 0x6
	// Bit mask of REG_DMA_RX_EN field.
	I3C_MST_DEVICE_CTRL_REG_DMA_RX_EN_Msk = 0x40
	// Bit REG_DMA_RX_EN.
	I3C_MST_DEVICE_CTRL_REG_DMA_RX_EN = 0x40
	// Position of REG_DMA_TX_EN field.
	I3C_MST_DEVICE_CTRL_REG_DMA_TX_EN_Pos = 0x7
	// Bit mask of REG_DMA_TX_EN field.
	I3C_MST_DEVICE_CTRL_REG_DMA_TX_EN_Msk = 0x80
	// Bit REG_DMA_TX_EN.
	I3C_MST_DEVICE_CTRL_REG_DMA_TX_EN = 0x80
	// Position of REG_MULTI_SLV_SINGLE_CCC_EN field.
	I3C_MST_DEVICE_CTRL_REG_MULTI_SLV_SINGLE_CCC_EN_Pos = 0x8
	// Bit mask of REG_MULTI_SLV_SINGLE_CCC_EN field.
	I3C_MST_DEVICE_CTRL_REG_MULTI_SLV_SINGLE_CCC_EN_Msk = 0x100
	// Bit REG_MULTI_SLV_SINGLE_CCC_EN.
	I3C_MST_DEVICE_CTRL_REG_MULTI_SLV_SINGLE_CCC_EN = 0x100
	// Position of REG_RX_BIT_ORDER field.
	I3C_MST_DEVICE_CTRL_REG_RX_BIT_ORDER_Pos = 0x9
	// Bit mask of REG_RX_BIT_ORDER field.
	I3C_MST_DEVICE_CTRL_REG_RX_BIT_ORDER_Msk = 0x200
	// Bit REG_RX_BIT_ORDER.
	I3C_MST_DEVICE_CTRL_REG_RX_BIT_ORDER = 0x200
	// Position of REG_RX_BYTE_ORDER field.
	I3C_MST_DEVICE_CTRL_REG_RX_BYTE_ORDER_Pos = 0xa
	// Bit mask of REG_RX_BYTE_ORDER field.
	I3C_MST_DEVICE_CTRL_REG_RX_BYTE_ORDER_Msk = 0x400
	// Bit REG_RX_BYTE_ORDER.
	I3C_MST_DEVICE_CTRL_REG_RX_BYTE_ORDER = 0x400
	// Position of REG_SCL_PULLUP_FORCE_EN field.
	I3C_MST_DEVICE_CTRL_REG_SCL_PULLUP_FORCE_EN_Pos = 0xb
	// Bit mask of REG_SCL_PULLUP_FORCE_EN field.
	I3C_MST_DEVICE_CTRL_REG_SCL_PULLUP_FORCE_EN_Msk = 0x800
	// Bit REG_SCL_PULLUP_FORCE_EN.
	I3C_MST_DEVICE_CTRL_REG_SCL_PULLUP_FORCE_EN = 0x800
	// Position of REG_SCL_OE_FORCE_EN field.
	I3C_MST_DEVICE_CTRL_REG_SCL_OE_FORCE_EN_Pos = 0xc
	// Bit mask of REG_SCL_OE_FORCE_EN field.
	I3C_MST_DEVICE_CTRL_REG_SCL_OE_FORCE_EN_Msk = 0x1000
	// Bit REG_SCL_OE_FORCE_EN.
	I3C_MST_DEVICE_CTRL_REG_SCL_OE_FORCE_EN = 0x1000
	// Position of REG_SDA_PP_RD_PULLUP_EN field.
	I3C_MST_DEVICE_CTRL_REG_SDA_PP_RD_PULLUP_EN_Pos = 0xd
	// Bit mask of REG_SDA_PP_RD_PULLUP_EN field.
	I3C_MST_DEVICE_CTRL_REG_SDA_PP_RD_PULLUP_EN_Msk = 0x2000
	// Bit REG_SDA_PP_RD_PULLUP_EN.
	I3C_MST_DEVICE_CTRL_REG_SDA_PP_RD_PULLUP_EN = 0x2000
	// Position of REG_SDA_RD_TBIT_HLVL_PULLUP_EN field.
	I3C_MST_DEVICE_CTRL_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_Pos = 0xe
	// Bit mask of REG_SDA_RD_TBIT_HLVL_PULLUP_EN field.
	I3C_MST_DEVICE_CTRL_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_Msk = 0x4000
	// Bit REG_SDA_RD_TBIT_HLVL_PULLUP_EN.
	I3C_MST_DEVICE_CTRL_REG_SDA_RD_TBIT_HLVL_PULLUP_EN = 0x4000
	// Position of REG_SDA_PP_WR_PULLUP_EN field.
	I3C_MST_DEVICE_CTRL_REG_SDA_PP_WR_PULLUP_EN_Pos = 0xf
	// Bit mask of REG_SDA_PP_WR_PULLUP_EN field.
	I3C_MST_DEVICE_CTRL_REG_SDA_PP_WR_PULLUP_EN_Msk = 0x8000
	// Bit REG_SDA_PP_WR_PULLUP_EN.
	I3C_MST_DEVICE_CTRL_REG_SDA_PP_WR_PULLUP_EN = 0x8000
	// Position of REG_DATA_BYTE_CNT_UNLATCH field.
	I3C_MST_DEVICE_CTRL_REG_DATA_BYTE_CNT_UNLATCH_Pos = 0x10
	// Bit mask of REG_DATA_BYTE_CNT_UNLATCH field.
	I3C_MST_DEVICE_CTRL_REG_DATA_BYTE_CNT_UNLATCH_Msk = 0x10000
	// Bit REG_DATA_BYTE_CNT_UNLATCH.
	I3C_MST_DEVICE_CTRL_REG_DATA_BYTE_CNT_UNLATCH = 0x10000
	// Position of REG_MEM_CLK_FORCE_ON field.
	I3C_MST_DEVICE_CTRL_REG_MEM_CLK_FORCE_ON_Pos = 0x11
	// Bit mask of REG_MEM_CLK_FORCE_ON field.
	I3C_MST_DEVICE_CTRL_REG_MEM_CLK_FORCE_ON_Msk = 0x20000
	// Bit REG_MEM_CLK_FORCE_ON.
	I3C_MST_DEVICE_CTRL_REG_MEM_CLK_FORCE_ON = 0x20000

	// BUFFER_THLD_CTRL: In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
	// Position of REG_CMD_BUF_EMPTY_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_CMD_BUF_EMPTY_THLD_Pos = 0x0
	// Bit mask of REG_CMD_BUF_EMPTY_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_CMD_BUF_EMPTY_THLD_Msk = 0xf
	// Position of REG_RESP_BUF_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_RESP_BUF_THLD_Pos = 0x6
	// Bit mask of REG_RESP_BUF_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_RESP_BUF_THLD_Msk = 0x1c0
	// Position of REG_IBI_DATA_BUF_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_IBI_DATA_BUF_THLD_Pos = 0xc
	// Bit mask of REG_IBI_DATA_BUF_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_IBI_DATA_BUF_THLD_Msk = 0x7000
	// Position of REG_IBI_STATUS_BUF_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_IBI_STATUS_BUF_THLD_Pos = 0x12
	// Bit mask of REG_IBI_STATUS_BUF_THLD field.
	I3C_MST_BUFFER_THLD_CTRL_REG_IBI_STATUS_BUF_THLD_Msk = 0x1c0000

	// DATA_BUFFER_THLD_CTRL: NA
	// Position of REG_TX_DATA_BUF_THLD field.
	I3C_MST_DATA_BUFFER_THLD_CTRL_REG_TX_DATA_BUF_THLD_Pos = 0x0
	// Bit mask of REG_TX_DATA_BUF_THLD field.
	I3C_MST_DATA_BUFFER_THLD_CTRL_REG_TX_DATA_BUF_THLD_Msk = 0x7
	// Position of REG_RX_DATA_BUF_THLD field.
	I3C_MST_DATA_BUFFER_THLD_CTRL_REG_RX_DATA_BUF_THLD_Pos = 0x3
	// Bit mask of REG_RX_DATA_BUF_THLD field.
	I3C_MST_DATA_BUFFER_THLD_CTRL_REG_RX_DATA_BUF_THLD_Msk = 0x38

	// IBI_NOTIFY_CTRL: NA
	// Position of REG_NOTIFY_SIR_REJECTED field.
	I3C_MST_IBI_NOTIFY_CTRL_REG_NOTIFY_SIR_REJECTED_Pos = 0x2
	// Bit mask of REG_NOTIFY_SIR_REJECTED field.
	I3C_MST_IBI_NOTIFY_CTRL_REG_NOTIFY_SIR_REJECTED_Msk = 0x4
	// Bit REG_NOTIFY_SIR_REJECTED.
	I3C_MST_IBI_NOTIFY_CTRL_REG_NOTIFY_SIR_REJECTED = 0x4

	// IBI_SIR_REQ_PAYLOAD: NA
	// Position of REG_SIR_REQ_PAYLOAD field.
	I3C_MST_IBI_SIR_REQ_PAYLOAD_REG_SIR_REQ_PAYLOAD_Pos = 0x0
	// Bit mask of REG_SIR_REQ_PAYLOAD field.
	I3C_MST_IBI_SIR_REQ_PAYLOAD_REG_SIR_REQ_PAYLOAD_Msk = 0xffffffff

	// IBI_SIR_REQ_REJECT: NA
	// Position of REG_SIR_REQ_REJECT field.
	I3C_MST_IBI_SIR_REQ_REJECT_REG_SIR_REQ_REJECT_Pos = 0x0
	// Bit mask of REG_SIR_REQ_REJECT field.
	I3C_MST_IBI_SIR_REQ_REJECT_REG_SIR_REQ_REJECT_Msk = 0xffffffff

	// INT_CLR: NA
	// Position of TX_DATA_BUF_THLD_INT_CLR field.
	I3C_MST_INT_CLR_TX_DATA_BUF_THLD_INT_CLR_Pos = 0x0
	// Bit mask of TX_DATA_BUF_THLD_INT_CLR field.
	I3C_MST_INT_CLR_TX_DATA_BUF_THLD_INT_CLR_Msk = 0x1
	// Bit TX_DATA_BUF_THLD_INT_CLR.
	I3C_MST_INT_CLR_TX_DATA_BUF_THLD_INT_CLR = 0x1
	// Position of RX_DATA_BUF_THLD_INT_CLR field.
	I3C_MST_INT_CLR_RX_DATA_BUF_THLD_INT_CLR_Pos = 0x1
	// Bit mask of RX_DATA_BUF_THLD_INT_CLR field.
	I3C_MST_INT_CLR_RX_DATA_BUF_THLD_INT_CLR_Msk = 0x2
	// Bit RX_DATA_BUF_THLD_INT_CLR.
	I3C_MST_INT_CLR_RX_DATA_BUF_THLD_INT_CLR = 0x2
	// Position of IBI_STATUS_THLD_INT_CLR field.
	I3C_MST_INT_CLR_IBI_STATUS_THLD_INT_CLR_Pos = 0x2
	// Bit mask of IBI_STATUS_THLD_INT_CLR field.
	I3C_MST_INT_CLR_IBI_STATUS_THLD_INT_CLR_Msk = 0x4
	// Bit IBI_STATUS_THLD_INT_CLR.
	I3C_MST_INT_CLR_IBI_STATUS_THLD_INT_CLR = 0x4
	// Position of CMD_BUF_EMPTY_THLD_INT_CLR field.
	I3C_MST_INT_CLR_CMD_BUF_EMPTY_THLD_INT_CLR_Pos = 0x3
	// Bit mask of CMD_BUF_EMPTY_THLD_INT_CLR field.
	I3C_MST_INT_CLR_CMD_BUF_EMPTY_THLD_INT_CLR_Msk = 0x8
	// Bit CMD_BUF_EMPTY_THLD_INT_CLR.
	I3C_MST_INT_CLR_CMD_BUF_EMPTY_THLD_INT_CLR = 0x8
	// Position of RESP_READY_INT_CLR field.
	I3C_MST_INT_CLR_RESP_READY_INT_CLR_Pos = 0x4
	// Bit mask of RESP_READY_INT_CLR field.
	I3C_MST_INT_CLR_RESP_READY_INT_CLR_Msk = 0x10
	// Bit RESP_READY_INT_CLR.
	I3C_MST_INT_CLR_RESP_READY_INT_CLR = 0x10
	// Position of NXT_CMD_REQ_ERR_INT_CLR field.
	I3C_MST_INT_CLR_NXT_CMD_REQ_ERR_INT_CLR_Pos = 0x5
	// Bit mask of NXT_CMD_REQ_ERR_INT_CLR field.
	I3C_MST_INT_CLR_NXT_CMD_REQ_ERR_INT_CLR_Msk = 0x20
	// Bit NXT_CMD_REQ_ERR_INT_CLR.
	I3C_MST_INT_CLR_NXT_CMD_REQ_ERR_INT_CLR = 0x20
	// Position of TRANSFER_ERR_INT_CLR field.
	I3C_MST_INT_CLR_TRANSFER_ERR_INT_CLR_Pos = 0x6
	// Bit mask of TRANSFER_ERR_INT_CLR field.
	I3C_MST_INT_CLR_TRANSFER_ERR_INT_CLR_Msk = 0x40
	// Bit TRANSFER_ERR_INT_CLR.
	I3C_MST_INT_CLR_TRANSFER_ERR_INT_CLR = 0x40
	// Position of TRANSFER_COMPLETE_INT_CLR field.
	I3C_MST_INT_CLR_TRANSFER_COMPLETE_INT_CLR_Pos = 0x7
	// Bit mask of TRANSFER_COMPLETE_INT_CLR field.
	I3C_MST_INT_CLR_TRANSFER_COMPLETE_INT_CLR_Msk = 0x80
	// Bit TRANSFER_COMPLETE_INT_CLR.
	I3C_MST_INT_CLR_TRANSFER_COMPLETE_INT_CLR = 0x80
	// Position of COMMAND_DONE_INT_CLR field.
	I3C_MST_INT_CLR_COMMAND_DONE_INT_CLR_Pos = 0x8
	// Bit mask of COMMAND_DONE_INT_CLR field.
	I3C_MST_INT_CLR_COMMAND_DONE_INT_CLR_Msk = 0x100
	// Bit COMMAND_DONE_INT_CLR.
	I3C_MST_INT_CLR_COMMAND_DONE_INT_CLR = 0x100
	// Position of DETECT_START_INT_CLR field.
	I3C_MST_INT_CLR_DETECT_START_INT_CLR_Pos = 0x9
	// Bit mask of DETECT_START_INT_CLR field.
	I3C_MST_INT_CLR_DETECT_START_INT_CLR_Msk = 0x200
	// Bit DETECT_START_INT_CLR.
	I3C_MST_INT_CLR_DETECT_START_INT_CLR = 0x200
	// Position of RESP_BUF_OVF_INT_CLR field.
	I3C_MST_INT_CLR_RESP_BUF_OVF_INT_CLR_Pos = 0xa
	// Bit mask of RESP_BUF_OVF_INT_CLR field.
	I3C_MST_INT_CLR_RESP_BUF_OVF_INT_CLR_Msk = 0x400
	// Bit RESP_BUF_OVF_INT_CLR.
	I3C_MST_INT_CLR_RESP_BUF_OVF_INT_CLR = 0x400
	// Position of IBI_DATA_BUF_OVF_INT_CLR field.
	I3C_MST_INT_CLR_IBI_DATA_BUF_OVF_INT_CLR_Pos = 0xb
	// Bit mask of IBI_DATA_BUF_OVF_INT_CLR field.
	I3C_MST_INT_CLR_IBI_DATA_BUF_OVF_INT_CLR_Msk = 0x800
	// Bit IBI_DATA_BUF_OVF_INT_CLR.
	I3C_MST_INT_CLR_IBI_DATA_BUF_OVF_INT_CLR = 0x800
	// Position of IBI_STATUS_BUF_OVF_INT_CLR field.
	I3C_MST_INT_CLR_IBI_STATUS_BUF_OVF_INT_CLR_Pos = 0xc
	// Bit mask of IBI_STATUS_BUF_OVF_INT_CLR field.
	I3C_MST_INT_CLR_IBI_STATUS_BUF_OVF_INT_CLR_Msk = 0x1000
	// Bit IBI_STATUS_BUF_OVF_INT_CLR.
	I3C_MST_INT_CLR_IBI_STATUS_BUF_OVF_INT_CLR = 0x1000
	// Position of IBI_HANDLE_DONE_INT_CLR field.
	I3C_MST_INT_CLR_IBI_HANDLE_DONE_INT_CLR_Pos = 0xd
	// Bit mask of IBI_HANDLE_DONE_INT_CLR field.
	I3C_MST_INT_CLR_IBI_HANDLE_DONE_INT_CLR_Msk = 0x2000
	// Bit IBI_HANDLE_DONE_INT_CLR.
	I3C_MST_INT_CLR_IBI_HANDLE_DONE_INT_CLR = 0x2000
	// Position of IBI_DETECT_INT_CLR field.
	I3C_MST_INT_CLR_IBI_DETECT_INT_CLR_Pos = 0xe
	// Bit mask of IBI_DETECT_INT_CLR field.
	I3C_MST_INT_CLR_IBI_DETECT_INT_CLR_Msk = 0x4000
	// Bit IBI_DETECT_INT_CLR.
	I3C_MST_INT_CLR_IBI_DETECT_INT_CLR = 0x4000
	// Position of CMD_CCC_MISMATCH_INT_CLR field.
	I3C_MST_INT_CLR_CMD_CCC_MISMATCH_INT_CLR_Pos = 0xf
	// Bit mask of CMD_CCC_MISMATCH_INT_CLR field.
	I3C_MST_INT_CLR_CMD_CCC_MISMATCH_INT_CLR_Msk = 0x8000
	// Bit CMD_CCC_MISMATCH_INT_CLR.
	I3C_MST_INT_CLR_CMD_CCC_MISMATCH_INT_CLR = 0x8000

	// INT_RAW: NA
	// Position of TX_DATA_BUF_THLD_INT_RAW field.
	I3C_MST_INT_RAW_TX_DATA_BUF_THLD_INT_RAW_Pos = 0x0
	// Bit mask of TX_DATA_BUF_THLD_INT_RAW field.
	I3C_MST_INT_RAW_TX_DATA_BUF_THLD_INT_RAW_Msk = 0x1
	// Bit TX_DATA_BUF_THLD_INT_RAW.
	I3C_MST_INT_RAW_TX_DATA_BUF_THLD_INT_RAW = 0x1
	// Position of RX_DATA_BUF_THLD_INT_RAW field.
	I3C_MST_INT_RAW_RX_DATA_BUF_THLD_INT_RAW_Pos = 0x1
	// Bit mask of RX_DATA_BUF_THLD_INT_RAW field.
	I3C_MST_INT_RAW_RX_DATA_BUF_THLD_INT_RAW_Msk = 0x2
	// Bit RX_DATA_BUF_THLD_INT_RAW.
	I3C_MST_INT_RAW_RX_DATA_BUF_THLD_INT_RAW = 0x2
	// Position of IBI_STATUS_THLD_INT_RAW field.
	I3C_MST_INT_RAW_IBI_STATUS_THLD_INT_RAW_Pos = 0x2
	// Bit mask of IBI_STATUS_THLD_INT_RAW field.
	I3C_MST_INT_RAW_IBI_STATUS_THLD_INT_RAW_Msk = 0x4
	// Bit IBI_STATUS_THLD_INT_RAW.
	I3C_MST_INT_RAW_IBI_STATUS_THLD_INT_RAW = 0x4
	// Position of CMD_BUF_EMPTY_THLD_INT_RAW field.
	I3C_MST_INT_RAW_CMD_BUF_EMPTY_THLD_INT_RAW_Pos = 0x3
	// Bit mask of CMD_BUF_EMPTY_THLD_INT_RAW field.
	I3C_MST_INT_RAW_CMD_BUF_EMPTY_THLD_INT_RAW_Msk = 0x8
	// Bit CMD_BUF_EMPTY_THLD_INT_RAW.
	I3C_MST_INT_RAW_CMD_BUF_EMPTY_THLD_INT_RAW = 0x8
	// Position of RESP_READY_INT_RAW field.
	I3C_MST_INT_RAW_RESP_READY_INT_RAW_Pos = 0x4
	// Bit mask of RESP_READY_INT_RAW field.
	I3C_MST_INT_RAW_RESP_READY_INT_RAW_Msk = 0x10
	// Bit RESP_READY_INT_RAW.
	I3C_MST_INT_RAW_RESP_READY_INT_RAW = 0x10
	// Position of NXT_CMD_REQ_ERR_INT_RAW field.
	I3C_MST_INT_RAW_NXT_CMD_REQ_ERR_INT_RAW_Pos = 0x5
	// Bit mask of NXT_CMD_REQ_ERR_INT_RAW field.
	I3C_MST_INT_RAW_NXT_CMD_REQ_ERR_INT_RAW_Msk = 0x20
	// Bit NXT_CMD_REQ_ERR_INT_RAW.
	I3C_MST_INT_RAW_NXT_CMD_REQ_ERR_INT_RAW = 0x20
	// Position of TRANSFER_ERR_INT_RAW field.
	I3C_MST_INT_RAW_TRANSFER_ERR_INT_RAW_Pos = 0x6
	// Bit mask of TRANSFER_ERR_INT_RAW field.
	I3C_MST_INT_RAW_TRANSFER_ERR_INT_RAW_Msk = 0x40
	// Bit TRANSFER_ERR_INT_RAW.
	I3C_MST_INT_RAW_TRANSFER_ERR_INT_RAW = 0x40
	// Position of TRANSFER_COMPLETE_INT_RAW field.
	I3C_MST_INT_RAW_TRANSFER_COMPLETE_INT_RAW_Pos = 0x7
	// Bit mask of TRANSFER_COMPLETE_INT_RAW field.
	I3C_MST_INT_RAW_TRANSFER_COMPLETE_INT_RAW_Msk = 0x80
	// Bit TRANSFER_COMPLETE_INT_RAW.
	I3C_MST_INT_RAW_TRANSFER_COMPLETE_INT_RAW = 0x80
	// Position of COMMAND_DONE_INT_RAW field.
	I3C_MST_INT_RAW_COMMAND_DONE_INT_RAW_Pos = 0x8
	// Bit mask of COMMAND_DONE_INT_RAW field.
	I3C_MST_INT_RAW_COMMAND_DONE_INT_RAW_Msk = 0x100
	// Bit COMMAND_DONE_INT_RAW.
	I3C_MST_INT_RAW_COMMAND_DONE_INT_RAW = 0x100
	// Position of DETECT_START_INT_RAW field.
	I3C_MST_INT_RAW_DETECT_START_INT_RAW_Pos = 0x9
	// Bit mask of DETECT_START_INT_RAW field.
	I3C_MST_INT_RAW_DETECT_START_INT_RAW_Msk = 0x200
	// Bit DETECT_START_INT_RAW.
	I3C_MST_INT_RAW_DETECT_START_INT_RAW = 0x200
	// Position of RESP_BUF_OVF_INT_RAW field.
	I3C_MST_INT_RAW_RESP_BUF_OVF_INT_RAW_Pos = 0xa
	// Bit mask of RESP_BUF_OVF_INT_RAW field.
	I3C_MST_INT_RAW_RESP_BUF_OVF_INT_RAW_Msk = 0x400
	// Bit RESP_BUF_OVF_INT_RAW.
	I3C_MST_INT_RAW_RESP_BUF_OVF_INT_RAW = 0x400
	// Position of IBI_DATA_BUF_OVF_INT_RAW field.
	I3C_MST_INT_RAW_IBI_DATA_BUF_OVF_INT_RAW_Pos = 0xb
	// Bit mask of IBI_DATA_BUF_OVF_INT_RAW field.
	I3C_MST_INT_RAW_IBI_DATA_BUF_OVF_INT_RAW_Msk = 0x800
	// Bit IBI_DATA_BUF_OVF_INT_RAW.
	I3C_MST_INT_RAW_IBI_DATA_BUF_OVF_INT_RAW = 0x800
	// Position of IBI_STATUS_BUF_OVF_INT_RAW field.
	I3C_MST_INT_RAW_IBI_STATUS_BUF_OVF_INT_RAW_Pos = 0xc
	// Bit mask of IBI_STATUS_BUF_OVF_INT_RAW field.
	I3C_MST_INT_RAW_IBI_STATUS_BUF_OVF_INT_RAW_Msk = 0x1000
	// Bit IBI_STATUS_BUF_OVF_INT_RAW.
	I3C_MST_INT_RAW_IBI_STATUS_BUF_OVF_INT_RAW = 0x1000
	// Position of IBI_HANDLE_DONE_INT_RAW field.
	I3C_MST_INT_RAW_IBI_HANDLE_DONE_INT_RAW_Pos = 0xd
	// Bit mask of IBI_HANDLE_DONE_INT_RAW field.
	I3C_MST_INT_RAW_IBI_HANDLE_DONE_INT_RAW_Msk = 0x2000
	// Bit IBI_HANDLE_DONE_INT_RAW.
	I3C_MST_INT_RAW_IBI_HANDLE_DONE_INT_RAW = 0x2000
	// Position of IBI_DETECT_INT_RAW field.
	I3C_MST_INT_RAW_IBI_DETECT_INT_RAW_Pos = 0xe
	// Bit mask of IBI_DETECT_INT_RAW field.
	I3C_MST_INT_RAW_IBI_DETECT_INT_RAW_Msk = 0x4000
	// Bit IBI_DETECT_INT_RAW.
	I3C_MST_INT_RAW_IBI_DETECT_INT_RAW = 0x4000
	// Position of CMD_CCC_MISMATCH_INT_RAW field.
	I3C_MST_INT_RAW_CMD_CCC_MISMATCH_INT_RAW_Pos = 0xf
	// Bit mask of CMD_CCC_MISMATCH_INT_RAW field.
	I3C_MST_INT_RAW_CMD_CCC_MISMATCH_INT_RAW_Msk = 0x8000
	// Bit CMD_CCC_MISMATCH_INT_RAW.
	I3C_MST_INT_RAW_CMD_CCC_MISMATCH_INT_RAW = 0x8000

	// INT_ST: NA
	// Position of TX_DATA_BUF_THLD_INT_ST field.
	I3C_MST_INT_ST_TX_DATA_BUF_THLD_INT_ST_Pos = 0x0
	// Bit mask of TX_DATA_BUF_THLD_INT_ST field.
	I3C_MST_INT_ST_TX_DATA_BUF_THLD_INT_ST_Msk = 0x1
	// Bit TX_DATA_BUF_THLD_INT_ST.
	I3C_MST_INT_ST_TX_DATA_BUF_THLD_INT_ST = 0x1
	// Position of RX_DATA_BUF_THLD_INT_ST field.
	I3C_MST_INT_ST_RX_DATA_BUF_THLD_INT_ST_Pos = 0x1
	// Bit mask of RX_DATA_BUF_THLD_INT_ST field.
	I3C_MST_INT_ST_RX_DATA_BUF_THLD_INT_ST_Msk = 0x2
	// Bit RX_DATA_BUF_THLD_INT_ST.
	I3C_MST_INT_ST_RX_DATA_BUF_THLD_INT_ST = 0x2
	// Position of IBI_STATUS_THLD_INT_ST field.
	I3C_MST_INT_ST_IBI_STATUS_THLD_INT_ST_Pos = 0x2
	// Bit mask of IBI_STATUS_THLD_INT_ST field.
	I3C_MST_INT_ST_IBI_STATUS_THLD_INT_ST_Msk = 0x4
	// Bit IBI_STATUS_THLD_INT_ST.
	I3C_MST_INT_ST_IBI_STATUS_THLD_INT_ST = 0x4
	// Position of CMD_BUF_EMPTY_THLD_INT_ST field.
	I3C_MST_INT_ST_CMD_BUF_EMPTY_THLD_INT_ST_Pos = 0x3
	// Bit mask of CMD_BUF_EMPTY_THLD_INT_ST field.
	I3C_MST_INT_ST_CMD_BUF_EMPTY_THLD_INT_ST_Msk = 0x8
	// Bit CMD_BUF_EMPTY_THLD_INT_ST.
	I3C_MST_INT_ST_CMD_BUF_EMPTY_THLD_INT_ST = 0x8
	// Position of RESP_READY_INT_ST field.
	I3C_MST_INT_ST_RESP_READY_INT_ST_Pos = 0x4
	// Bit mask of RESP_READY_INT_ST field.
	I3C_MST_INT_ST_RESP_READY_INT_ST_Msk = 0x10
	// Bit RESP_READY_INT_ST.
	I3C_MST_INT_ST_RESP_READY_INT_ST = 0x10
	// Position of NXT_CMD_REQ_ERR_INT_ST field.
	I3C_MST_INT_ST_NXT_CMD_REQ_ERR_INT_ST_Pos = 0x5
	// Bit mask of NXT_CMD_REQ_ERR_INT_ST field.
	I3C_MST_INT_ST_NXT_CMD_REQ_ERR_INT_ST_Msk = 0x20
	// Bit NXT_CMD_REQ_ERR_INT_ST.
	I3C_MST_INT_ST_NXT_CMD_REQ_ERR_INT_ST = 0x20
	// Position of TRANSFER_ERR_INT_ST field.
	I3C_MST_INT_ST_TRANSFER_ERR_INT_ST_Pos = 0x6
	// Bit mask of TRANSFER_ERR_INT_ST field.
	I3C_MST_INT_ST_TRANSFER_ERR_INT_ST_Msk = 0x40
	// Bit TRANSFER_ERR_INT_ST.
	I3C_MST_INT_ST_TRANSFER_ERR_INT_ST = 0x40
	// Position of TRANSFER_COMPLETE_INT_ST field.
	I3C_MST_INT_ST_TRANSFER_COMPLETE_INT_ST_Pos = 0x7
	// Bit mask of TRANSFER_COMPLETE_INT_ST field.
	I3C_MST_INT_ST_TRANSFER_COMPLETE_INT_ST_Msk = 0x80
	// Bit TRANSFER_COMPLETE_INT_ST.
	I3C_MST_INT_ST_TRANSFER_COMPLETE_INT_ST = 0x80
	// Position of COMMAND_DONE_INT_ST field.
	I3C_MST_INT_ST_COMMAND_DONE_INT_ST_Pos = 0x8
	// Bit mask of COMMAND_DONE_INT_ST field.
	I3C_MST_INT_ST_COMMAND_DONE_INT_ST_Msk = 0x100
	// Bit COMMAND_DONE_INT_ST.
	I3C_MST_INT_ST_COMMAND_DONE_INT_ST = 0x100
	// Position of DETECT_START_INT_ST field.
	I3C_MST_INT_ST_DETECT_START_INT_ST_Pos = 0x9
	// Bit mask of DETECT_START_INT_ST field.
	I3C_MST_INT_ST_DETECT_START_INT_ST_Msk = 0x200
	// Bit DETECT_START_INT_ST.
	I3C_MST_INT_ST_DETECT_START_INT_ST = 0x200
	// Position of RESP_BUF_OVF_INT_ST field.
	I3C_MST_INT_ST_RESP_BUF_OVF_INT_ST_Pos = 0xa
	// Bit mask of RESP_BUF_OVF_INT_ST field.
	I3C_MST_INT_ST_RESP_BUF_OVF_INT_ST_Msk = 0x400
	// Bit RESP_BUF_OVF_INT_ST.
	I3C_MST_INT_ST_RESP_BUF_OVF_INT_ST = 0x400
	// Position of IBI_DATA_BUF_OVF_INT_ST field.
	I3C_MST_INT_ST_IBI_DATA_BUF_OVF_INT_ST_Pos = 0xb
	// Bit mask of IBI_DATA_BUF_OVF_INT_ST field.
	I3C_MST_INT_ST_IBI_DATA_BUF_OVF_INT_ST_Msk = 0x800
	// Bit IBI_DATA_BUF_OVF_INT_ST.
	I3C_MST_INT_ST_IBI_DATA_BUF_OVF_INT_ST = 0x800
	// Position of IBI_STATUS_BUF_OVF_INT_ST field.
	I3C_MST_INT_ST_IBI_STATUS_BUF_OVF_INT_ST_Pos = 0xc
	// Bit mask of IBI_STATUS_BUF_OVF_INT_ST field.
	I3C_MST_INT_ST_IBI_STATUS_BUF_OVF_INT_ST_Msk = 0x1000
	// Bit IBI_STATUS_BUF_OVF_INT_ST.
	I3C_MST_INT_ST_IBI_STATUS_BUF_OVF_INT_ST = 0x1000
	// Position of IBI_HANDLE_DONE_INT_ST field.
	I3C_MST_INT_ST_IBI_HANDLE_DONE_INT_ST_Pos = 0xd
	// Bit mask of IBI_HANDLE_DONE_INT_ST field.
	I3C_MST_INT_ST_IBI_HANDLE_DONE_INT_ST_Msk = 0x2000
	// Bit IBI_HANDLE_DONE_INT_ST.
	I3C_MST_INT_ST_IBI_HANDLE_DONE_INT_ST = 0x2000
	// Position of IBI_DETECT_INT_ST field.
	I3C_MST_INT_ST_IBI_DETECT_INT_ST_Pos = 0xe
	// Bit mask of IBI_DETECT_INT_ST field.
	I3C_MST_INT_ST_IBI_DETECT_INT_ST_Msk = 0x4000
	// Bit IBI_DETECT_INT_ST.
	I3C_MST_INT_ST_IBI_DETECT_INT_ST = 0x4000
	// Position of CMD_CCC_MISMATCH_INT_ST field.
	I3C_MST_INT_ST_CMD_CCC_MISMATCH_INT_ST_Pos = 0xf
	// Bit mask of CMD_CCC_MISMATCH_INT_ST field.
	I3C_MST_INT_ST_CMD_CCC_MISMATCH_INT_ST_Msk = 0x8000
	// Bit CMD_CCC_MISMATCH_INT_ST.
	I3C_MST_INT_ST_CMD_CCC_MISMATCH_INT_ST = 0x8000

	// INT_ST_ENA: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.
	// Position of TX_DATA_BUF_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_TX_DATA_BUF_THLD_INT_ENA_Pos = 0x0
	// Bit mask of TX_DATA_BUF_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_TX_DATA_BUF_THLD_INT_ENA_Msk = 0x1
	// Bit TX_DATA_BUF_THLD_INT_ENA.
	I3C_MST_INT_ST_ENA_TX_DATA_BUF_THLD_INT_ENA = 0x1
	// Position of RX_DATA_BUF_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_RX_DATA_BUF_THLD_INT_ENA_Pos = 0x1
	// Bit mask of RX_DATA_BUF_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_RX_DATA_BUF_THLD_INT_ENA_Msk = 0x2
	// Bit RX_DATA_BUF_THLD_INT_ENA.
	I3C_MST_INT_ST_ENA_RX_DATA_BUF_THLD_INT_ENA = 0x2
	// Position of IBI_STATUS_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_STATUS_THLD_INT_ENA_Pos = 0x2
	// Bit mask of IBI_STATUS_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_STATUS_THLD_INT_ENA_Msk = 0x4
	// Bit IBI_STATUS_THLD_INT_ENA.
	I3C_MST_INT_ST_ENA_IBI_STATUS_THLD_INT_ENA = 0x4
	// Position of CMD_BUF_EMPTY_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_CMD_BUF_EMPTY_THLD_INT_ENA_Pos = 0x3
	// Bit mask of CMD_BUF_EMPTY_THLD_INT_ENA field.
	I3C_MST_INT_ST_ENA_CMD_BUF_EMPTY_THLD_INT_ENA_Msk = 0x8
	// Bit CMD_BUF_EMPTY_THLD_INT_ENA.
	I3C_MST_INT_ST_ENA_CMD_BUF_EMPTY_THLD_INT_ENA = 0x8
	// Position of RESP_READY_INT_ENA field.
	I3C_MST_INT_ST_ENA_RESP_READY_INT_ENA_Pos = 0x4
	// Bit mask of RESP_READY_INT_ENA field.
	I3C_MST_INT_ST_ENA_RESP_READY_INT_ENA_Msk = 0x10
	// Bit RESP_READY_INT_ENA.
	I3C_MST_INT_ST_ENA_RESP_READY_INT_ENA = 0x10
	// Position of NXT_CMD_REQ_ERR_INT_ENA field.
	I3C_MST_INT_ST_ENA_NXT_CMD_REQ_ERR_INT_ENA_Pos = 0x5
	// Bit mask of NXT_CMD_REQ_ERR_INT_ENA field.
	I3C_MST_INT_ST_ENA_NXT_CMD_REQ_ERR_INT_ENA_Msk = 0x20
	// Bit NXT_CMD_REQ_ERR_INT_ENA.
	I3C_MST_INT_ST_ENA_NXT_CMD_REQ_ERR_INT_ENA = 0x20
	// Position of TRANSFER_ERR_INT_ENA field.
	I3C_MST_INT_ST_ENA_TRANSFER_ERR_INT_ENA_Pos = 0x6
	// Bit mask of TRANSFER_ERR_INT_ENA field.
	I3C_MST_INT_ST_ENA_TRANSFER_ERR_INT_ENA_Msk = 0x40
	// Bit TRANSFER_ERR_INT_ENA.
	I3C_MST_INT_ST_ENA_TRANSFER_ERR_INT_ENA = 0x40
	// Position of TRANSFER_COMPLETE_INT_ENA field.
	I3C_MST_INT_ST_ENA_TRANSFER_COMPLETE_INT_ENA_Pos = 0x7
	// Bit mask of TRANSFER_COMPLETE_INT_ENA field.
	I3C_MST_INT_ST_ENA_TRANSFER_COMPLETE_INT_ENA_Msk = 0x80
	// Bit TRANSFER_COMPLETE_INT_ENA.
	I3C_MST_INT_ST_ENA_TRANSFER_COMPLETE_INT_ENA = 0x80
	// Position of COMMAND_DONE_INT_ENA field.
	I3C_MST_INT_ST_ENA_COMMAND_DONE_INT_ENA_Pos = 0x8
	// Bit mask of COMMAND_DONE_INT_ENA field.
	I3C_MST_INT_ST_ENA_COMMAND_DONE_INT_ENA_Msk = 0x100
	// Bit COMMAND_DONE_INT_ENA.
	I3C_MST_INT_ST_ENA_COMMAND_DONE_INT_ENA = 0x100
	// Position of DETECT_START_INT_ENA field.
	I3C_MST_INT_ST_ENA_DETECT_START_INT_ENA_Pos = 0x9
	// Bit mask of DETECT_START_INT_ENA field.
	I3C_MST_INT_ST_ENA_DETECT_START_INT_ENA_Msk = 0x200
	// Bit DETECT_START_INT_ENA.
	I3C_MST_INT_ST_ENA_DETECT_START_INT_ENA = 0x200
	// Position of RESP_BUF_OVF_INT_ENA field.
	I3C_MST_INT_ST_ENA_RESP_BUF_OVF_INT_ENA_Pos = 0xa
	// Bit mask of RESP_BUF_OVF_INT_ENA field.
	I3C_MST_INT_ST_ENA_RESP_BUF_OVF_INT_ENA_Msk = 0x400
	// Bit RESP_BUF_OVF_INT_ENA.
	I3C_MST_INT_ST_ENA_RESP_BUF_OVF_INT_ENA = 0x400
	// Position of IBI_DATA_BUF_OVF_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_DATA_BUF_OVF_INT_ENA_Pos = 0xb
	// Bit mask of IBI_DATA_BUF_OVF_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_DATA_BUF_OVF_INT_ENA_Msk = 0x800
	// Bit IBI_DATA_BUF_OVF_INT_ENA.
	I3C_MST_INT_ST_ENA_IBI_DATA_BUF_OVF_INT_ENA = 0x800
	// Position of IBI_STATUS_BUF_OVF_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_STATUS_BUF_OVF_INT_ENA_Pos = 0xc
	// Bit mask of IBI_STATUS_BUF_OVF_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_STATUS_BUF_OVF_INT_ENA_Msk = 0x1000
	// Bit IBI_STATUS_BUF_OVF_INT_ENA.
	I3C_MST_INT_ST_ENA_IBI_STATUS_BUF_OVF_INT_ENA = 0x1000
	// Position of IBI_HANDLE_DONE_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_HANDLE_DONE_INT_ENA_Pos = 0xd
	// Bit mask of IBI_HANDLE_DONE_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_HANDLE_DONE_INT_ENA_Msk = 0x2000
	// Bit IBI_HANDLE_DONE_INT_ENA.
	I3C_MST_INT_ST_ENA_IBI_HANDLE_DONE_INT_ENA = 0x2000
	// Position of IBI_DETECT_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_DETECT_INT_ENA_Pos = 0xe
	// Bit mask of IBI_DETECT_INT_ENA field.
	I3C_MST_INT_ST_ENA_IBI_DETECT_INT_ENA_Msk = 0x4000
	// Bit IBI_DETECT_INT_ENA.
	I3C_MST_INT_ST_ENA_IBI_DETECT_INT_ENA = 0x4000
	// Position of CMD_CCC_MISMATCH_INT_ENA field.
	I3C_MST_INT_ST_ENA_CMD_CCC_MISMATCH_INT_ENA_Pos = 0xf
	// Bit mask of CMD_CCC_MISMATCH_INT_ENA field.
	I3C_MST_INT_ST_ENA_CMD_CCC_MISMATCH_INT_ENA_Msk = 0x8000
	// Bit CMD_CCC_MISMATCH_INT_ENA.
	I3C_MST_INT_ST_ENA_CMD_CCC_MISMATCH_INT_ENA = 0x8000

	// RESET_CTRL: NA
	// Position of REG_CORE_SOFT_RST field.
	I3C_MST_RESET_CTRL_REG_CORE_SOFT_RST_Pos = 0x0
	// Bit mask of REG_CORE_SOFT_RST field.
	I3C_MST_RESET_CTRL_REG_CORE_SOFT_RST_Msk = 0x1
	// Bit REG_CORE_SOFT_RST.
	I3C_MST_RESET_CTRL_REG_CORE_SOFT_RST = 0x1
	// Position of REG_CMD_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_CMD_BUF_RST_Pos = 0x1
	// Bit mask of REG_CMD_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_CMD_BUF_RST_Msk = 0x2
	// Bit REG_CMD_BUF_RST.
	I3C_MST_RESET_CTRL_REG_CMD_BUF_RST = 0x2
	// Position of REG_RESP_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_RESP_BUF_RST_Pos = 0x2
	// Bit mask of REG_RESP_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_RESP_BUF_RST_Msk = 0x4
	// Bit REG_RESP_BUF_RST.
	I3C_MST_RESET_CTRL_REG_RESP_BUF_RST = 0x4
	// Position of REG_TX_DATA_BUF_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_TX_DATA_BUF_BUF_RST_Pos = 0x3
	// Bit mask of REG_TX_DATA_BUF_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_TX_DATA_BUF_BUF_RST_Msk = 0x8
	// Bit REG_TX_DATA_BUF_BUF_RST.
	I3C_MST_RESET_CTRL_REG_TX_DATA_BUF_BUF_RST = 0x8
	// Position of REG_RX_DATA_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_RX_DATA_BUF_RST_Pos = 0x4
	// Bit mask of REG_RX_DATA_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_RX_DATA_BUF_RST_Msk = 0x10
	// Bit REG_RX_DATA_BUF_RST.
	I3C_MST_RESET_CTRL_REG_RX_DATA_BUF_RST = 0x10
	// Position of REG_IBI_DATA_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_IBI_DATA_BUF_RST_Pos = 0x5
	// Bit mask of REG_IBI_DATA_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_IBI_DATA_BUF_RST_Msk = 0x20
	// Bit REG_IBI_DATA_BUF_RST.
	I3C_MST_RESET_CTRL_REG_IBI_DATA_BUF_RST = 0x20
	// Position of REG_IBI_STATUS_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_IBI_STATUS_BUF_RST_Pos = 0x6
	// Bit mask of REG_IBI_STATUS_BUF_RST field.
	I3C_MST_RESET_CTRL_REG_IBI_STATUS_BUF_RST_Msk = 0x40
	// Bit REG_IBI_STATUS_BUF_RST.
	I3C_MST_RESET_CTRL_REG_IBI_STATUS_BUF_RST = 0x40

	// BUFFER_STATUS_LEVEL: BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
	// Position of CMD_BUF_EMPTY_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_CMD_BUF_EMPTY_CNT_Pos = 0x0
	// Bit mask of CMD_BUF_EMPTY_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_CMD_BUF_EMPTY_CNT_Msk = 0x1f
	// Position of RESP_BUF_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_RESP_BUF_CNT_Pos = 0x8
	// Bit mask of RESP_BUF_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_RESP_BUF_CNT_Msk = 0xf00
	// Position of IBI_DATA_BUF_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_IBI_DATA_BUF_CNT_Pos = 0x10
	// Bit mask of IBI_DATA_BUF_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_IBI_DATA_BUF_CNT_Msk = 0xf0000
	// Position of IBI_STATUS_BUF_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_IBI_STATUS_BUF_CNT_Pos = 0x18
	// Bit mask of IBI_STATUS_BUF_CNT field.
	I3C_MST_BUFFER_STATUS_LEVEL_IBI_STATUS_BUF_CNT_Msk = 0xf000000

	// DATA_BUFFER_STATUS_LEVEL: DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
	// Position of TX_DATA_BUF_EMPTY_CNT field.
	I3C_MST_DATA_BUFFER_STATUS_LEVEL_TX_DATA_BUF_EMPTY_CNT_Pos = 0x0
	// Bit mask of TX_DATA_BUF_EMPTY_CNT field.
	I3C_MST_DATA_BUFFER_STATUS_LEVEL_TX_DATA_BUF_EMPTY_CNT_Msk = 0x3f
	// Position of RX_DATA_BUF_CNT field.
	I3C_MST_DATA_BUFFER_STATUS_LEVEL_RX_DATA_BUF_CNT_Pos = 0x10
	// Bit mask of RX_DATA_BUF_CNT field.
	I3C_MST_DATA_BUFFER_STATUS_LEVEL_RX_DATA_BUF_CNT_Msk = 0x3f0000

	// PRESENT_STATE0: NA
	// Position of SDA_LVL field.
	I3C_MST_PRESENT_STATE0_SDA_LVL_Pos = 0x0
	// Bit mask of SDA_LVL field.
	I3C_MST_PRESENT_STATE0_SDA_LVL_Msk = 0x1
	// Bit SDA_LVL.
	I3C_MST_PRESENT_STATE0_SDA_LVL = 0x1
	// Position of SCL_LVL field.
	I3C_MST_PRESENT_STATE0_SCL_LVL_Pos = 0x1
	// Bit mask of SCL_LVL field.
	I3C_MST_PRESENT_STATE0_SCL_LVL_Msk = 0x2
	// Bit SCL_LVL.
	I3C_MST_PRESENT_STATE0_SCL_LVL = 0x2
	// Position of BUS_BUSY field.
	I3C_MST_PRESENT_STATE0_BUS_BUSY_Pos = 0x2
	// Bit mask of BUS_BUSY field.
	I3C_MST_PRESENT_STATE0_BUS_BUSY_Msk = 0x4
	// Bit BUS_BUSY.
	I3C_MST_PRESENT_STATE0_BUS_BUSY = 0x4
	// Position of BUS_FREE field.
	I3C_MST_PRESENT_STATE0_BUS_FREE_Pos = 0x3
	// Bit mask of BUS_FREE field.
	I3C_MST_PRESENT_STATE0_BUS_FREE_Msk = 0x8
	// Bit BUS_FREE.
	I3C_MST_PRESENT_STATE0_BUS_FREE = 0x8
	// Position of CMD_TID field.
	I3C_MST_PRESENT_STATE0_CMD_TID_Pos = 0x9
	// Bit mask of CMD_TID field.
	I3C_MST_PRESENT_STATE0_CMD_TID_Msk = 0x1e00
	// Position of SCL_GEN_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_SCL_GEN_FSM_STATE_Pos = 0xd
	// Bit mask of SCL_GEN_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_SCL_GEN_FSM_STATE_Msk = 0xe000
	// Position of IBI_EV_HANDLE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_IBI_EV_HANDLE_FSM_STATE_Pos = 0x10
	// Bit mask of IBI_EV_HANDLE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_IBI_EV_HANDLE_FSM_STATE_Msk = 0x70000
	// Position of I2C_MODE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_I2C_MODE_FSM_STATE_Pos = 0x13
	// Bit mask of I2C_MODE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_I2C_MODE_FSM_STATE_Msk = 0x380000
	// Position of SDR_MODE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_SDR_MODE_FSM_STATE_Pos = 0x16
	// Bit mask of SDR_MODE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_SDR_MODE_FSM_STATE_Msk = 0x3c00000
	// Position of DAA_MODE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_DAA_MODE_FSM_STATE_Pos = 0x1a
	// Bit mask of DAA_MODE_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_DAA_MODE_FSM_STATE_Msk = 0x1c000000
	// Position of MAIN_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_MAIN_FSM_STATE_Pos = 0x1d
	// Bit mask of MAIN_FSM_STATE field.
	I3C_MST_PRESENT_STATE0_MAIN_FSM_STATE_Msk = 0xe0000000

	// PRESENT_STATE1: NA
	// Position of DATA_BYTE_CNT field.
	I3C_MST_PRESENT_STATE1_DATA_BYTE_CNT_Pos = 0x0
	// Bit mask of DATA_BYTE_CNT field.
	I3C_MST_PRESENT_STATE1_DATA_BYTE_CNT_Msk = 0xffff

	// DEVICE_TABLE: Pointer for Device Address Table
	// Position of REG_DCT_DAA_INIT_INDEX field.
	I3C_MST_DEVICE_TABLE_REG_DCT_DAA_INIT_INDEX_Pos = 0x0
	// Bit mask of REG_DCT_DAA_INIT_INDEX field.
	I3C_MST_DEVICE_TABLE_REG_DCT_DAA_INIT_INDEX_Msk = 0xf
	// Position of REG_DAT_DAA_INIT_INDEX field.
	I3C_MST_DEVICE_TABLE_REG_DAT_DAA_INIT_INDEX_Pos = 0x4
	// Bit mask of REG_DAT_DAA_INIT_INDEX field.
	I3C_MST_DEVICE_TABLE_REG_DAT_DAA_INIT_INDEX_Msk = 0xf0
	// Position of PRESENT_DCT_INDEX field.
	I3C_MST_DEVICE_TABLE_PRESENT_DCT_INDEX_Pos = 0x8
	// Bit mask of PRESENT_DCT_INDEX field.
	I3C_MST_DEVICE_TABLE_PRESENT_DCT_INDEX_Msk = 0xf00
	// Position of PRESENT_DAT_INDEX field.
	I3C_MST_DEVICE_TABLE_PRESENT_DAT_INDEX_Pos = 0xc
	// Bit mask of PRESENT_DAT_INDEX field.
	I3C_MST_DEVICE_TABLE_PRESENT_DAT_INDEX_Msk = 0xf000

	// TIME_OUT_VALUE: NA
	// Position of REG_RESP_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_RESP_BUF_TO_VALUE_Pos = 0x0
	// Bit mask of REG_RESP_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_RESP_BUF_TO_VALUE_Msk = 0x1f
	// Position of REG_RESP_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_RESP_BUF_TO_EN_Pos = 0x5
	// Bit mask of REG_RESP_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_RESP_BUF_TO_EN_Msk = 0x20
	// Bit REG_RESP_BUF_TO_EN.
	I3C_MST_TIME_OUT_VALUE_REG_RESP_BUF_TO_EN = 0x20
	// Position of REG_IBI_DATA_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_VALUE_Pos = 0x6
	// Bit mask of REG_IBI_DATA_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_VALUE_Msk = 0x7c0
	// Position of REG_IBI_DATA_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_EN_Pos = 0xb
	// Bit mask of REG_IBI_DATA_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_EN_Msk = 0x800
	// Bit REG_IBI_DATA_BUF_TO_EN.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_DATA_BUF_TO_EN = 0x800
	// Position of REG_IBI_STATUS_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_VALUE_Pos = 0xc
	// Bit mask of REG_IBI_STATUS_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_VALUE_Msk = 0x1f000
	// Position of REG_IBI_STATUS_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_EN_Pos = 0x11
	// Bit mask of REG_IBI_STATUS_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_EN_Msk = 0x20000
	// Bit REG_IBI_STATUS_BUF_TO_EN.
	I3C_MST_TIME_OUT_VALUE_REG_IBI_STATUS_BUF_TO_EN = 0x20000
	// Position of REG_RX_DATA_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_RX_DATA_BUF_TO_VALUE_Pos = 0x12
	// Bit mask of REG_RX_DATA_BUF_TO_VALUE field.
	I3C_MST_TIME_OUT_VALUE_REG_RX_DATA_BUF_TO_VALUE_Msk = 0x7c0000
	// Position of REG_RX_DATA_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_RX_DATA_BUF_TO_EN_Pos = 0x17
	// Bit mask of REG_RX_DATA_BUF_TO_EN field.
	I3C_MST_TIME_OUT_VALUE_REG_RX_DATA_BUF_TO_EN_Msk = 0x800000
	// Bit REG_RX_DATA_BUF_TO_EN.
	I3C_MST_TIME_OUT_VALUE_REG_RX_DATA_BUF_TO_EN = 0x800000

	// SCL_I3C_MST_OD_TIME: NA
	// Position of REG_I3C_MST_OD_LOW_PERIOD field.
	I3C_MST_SCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_LOW_PERIOD_Pos = 0x0
	// Bit mask of REG_I3C_MST_OD_LOW_PERIOD field.
	I3C_MST_SCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_LOW_PERIOD_Msk = 0xffff
	// Position of REG_I3C_MST_OD_HIGH_PERIOD field.
	I3C_MST_SCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_HIGH_PERIOD_Pos = 0x10
	// Bit mask of REG_I3C_MST_OD_HIGH_PERIOD field.
	I3C_MST_SCL_I3C_MST_OD_TIME_REG_I3C_MST_OD_HIGH_PERIOD_Msk = 0xffff0000

	// SCL_I3C_MST_PP_TIME: NA
	// Position of REG_I3C_MST_PP_LOW_PERIOD field.
	I3C_MST_SCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_LOW_PERIOD_Pos = 0x0
	// Bit mask of REG_I3C_MST_PP_LOW_PERIOD field.
	I3C_MST_SCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_LOW_PERIOD_Msk = 0xff
	// Position of REG_I3C_MST_PP_HIGH_PERIOD field.
	I3C_MST_SCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_HIGH_PERIOD_Pos = 0x10
	// Bit mask of REG_I3C_MST_PP_HIGH_PERIOD field.
	I3C_MST_SCL_I3C_MST_PP_TIME_REG_I3C_MST_PP_HIGH_PERIOD_Msk = 0xff0000

	// SCL_I2C_FM_TIME: NA
	// Position of REG_I2C_FM_LOW_PERIOD field.
	I3C_MST_SCL_I2C_FM_TIME_REG_I2C_FM_LOW_PERIOD_Pos = 0x0
	// Bit mask of REG_I2C_FM_LOW_PERIOD field.
	I3C_MST_SCL_I2C_FM_TIME_REG_I2C_FM_LOW_PERIOD_Msk = 0xffff
	// Position of REG_I2C_FM_HIGH_PERIOD field.
	I3C_MST_SCL_I2C_FM_TIME_REG_I2C_FM_HIGH_PERIOD_Pos = 0x10
	// Bit mask of REG_I2C_FM_HIGH_PERIOD field.
	I3C_MST_SCL_I2C_FM_TIME_REG_I2C_FM_HIGH_PERIOD_Msk = 0xffff0000

	// SCL_I2C_FMP_TIME: NA
	// Position of REG_I2C_FMP_LOW_PERIOD field.
	I3C_MST_SCL_I2C_FMP_TIME_REG_I2C_FMP_LOW_PERIOD_Pos = 0x0
	// Bit mask of REG_I2C_FMP_LOW_PERIOD field.
	I3C_MST_SCL_I2C_FMP_TIME_REG_I2C_FMP_LOW_PERIOD_Msk = 0xffff
	// Position of REG_I2C_FMP_HIGH_PERIOD field.
	I3C_MST_SCL_I2C_FMP_TIME_REG_I2C_FMP_HIGH_PERIOD_Pos = 0x10
	// Bit mask of REG_I2C_FMP_HIGH_PERIOD field.
	I3C_MST_SCL_I2C_FMP_TIME_REG_I2C_FMP_HIGH_PERIOD_Msk = 0xff0000

	// SCL_EXT_LOW_TIME: NA
	// Position of REG_I3C_MST_EXT_LOW_PERIOD1 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD1_Pos = 0x0
	// Bit mask of REG_I3C_MST_EXT_LOW_PERIOD1 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD1_Msk = 0xff
	// Position of REG_I3C_MST_EXT_LOW_PERIOD2 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD2_Pos = 0x8
	// Bit mask of REG_I3C_MST_EXT_LOW_PERIOD2 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD2_Msk = 0xff00
	// Position of REG_I3C_MST_EXT_LOW_PERIOD3 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD3_Pos = 0x10
	// Bit mask of REG_I3C_MST_EXT_LOW_PERIOD3 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD3_Msk = 0xff0000
	// Position of REG_I3C_MST_EXT_LOW_PERIOD4 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD4_Pos = 0x18
	// Bit mask of REG_I3C_MST_EXT_LOW_PERIOD4 field.
	I3C_MST_SCL_EXT_LOW_TIME_REG_I3C_MST_EXT_LOW_PERIOD4_Msk = 0xff000000

	// SDA_SAMPLE_TIME: NA
	// Position of REG_SDA_OD_SAMPLE_TIME field.
	I3C_MST_SDA_SAMPLE_TIME_REG_SDA_OD_SAMPLE_TIME_Pos = 0x0
	// Bit mask of REG_SDA_OD_SAMPLE_TIME field.
	I3C_MST_SDA_SAMPLE_TIME_REG_SDA_OD_SAMPLE_TIME_Msk = 0x1ff
	// Position of REG_SDA_PP_SAMPLE_TIME field.
	I3C_MST_SDA_SAMPLE_TIME_REG_SDA_PP_SAMPLE_TIME_Pos = 0x9
	// Bit mask of REG_SDA_PP_SAMPLE_TIME field.
	I3C_MST_SDA_SAMPLE_TIME_REG_SDA_PP_SAMPLE_TIME_Msk = 0x3e00

	// SDA_HOLD_TIME: NA
	// Position of REG_SDA_OD_TX_HOLD_TIME field.
	I3C_MST_SDA_HOLD_TIME_REG_SDA_OD_TX_HOLD_TIME_Pos = 0x0
	// Bit mask of REG_SDA_OD_TX_HOLD_TIME field.
	I3C_MST_SDA_HOLD_TIME_REG_SDA_OD_TX_HOLD_TIME_Msk = 0x1ff
	// Position of REG_SDA_PP_TX_HOLD_TIME field.
	I3C_MST_SDA_HOLD_TIME_REG_SDA_PP_TX_HOLD_TIME_Pos = 0x9
	// Bit mask of REG_SDA_PP_TX_HOLD_TIME field.
	I3C_MST_SDA_HOLD_TIME_REG_SDA_PP_TX_HOLD_TIME_Msk = 0x3e00

	// SCL_START_HOLD: NA
	// Position of REG_SCL_START_HOLD_TIME field.
	I3C_MST_SCL_START_HOLD_REG_SCL_START_HOLD_TIME_Pos = 0x0
	// Bit mask of REG_SCL_START_HOLD_TIME field.
	I3C_MST_SCL_START_HOLD_REG_SCL_START_HOLD_TIME_Msk = 0x1ff
	// Position of REG_START_DET_HOLD_TIME field.
	I3C_MST_SCL_START_HOLD_REG_START_DET_HOLD_TIME_Pos = 0x9
	// Bit mask of REG_START_DET_HOLD_TIME field.
	I3C_MST_SCL_START_HOLD_REG_START_DET_HOLD_TIME_Msk = 0x600

	// SCL_RSTART_SETUP: NA
	// Position of REG_SCL_RSTART_SETUP_TIME field.
	I3C_MST_SCL_RSTART_SETUP_REG_SCL_RSTART_SETUP_TIME_Pos = 0x0
	// Bit mask of REG_SCL_RSTART_SETUP_TIME field.
	I3C_MST_SCL_RSTART_SETUP_REG_SCL_RSTART_SETUP_TIME_Msk = 0x1ff

	// SCL_STOP_HOLD: NA
	// Position of REG_SCL_STOP_HOLD_TIME field.
	I3C_MST_SCL_STOP_HOLD_REG_SCL_STOP_HOLD_TIME_Pos = 0x0
	// Bit mask of REG_SCL_STOP_HOLD_TIME field.
	I3C_MST_SCL_STOP_HOLD_REG_SCL_STOP_HOLD_TIME_Msk = 0x1ff

	// SCL_STOP_SETUP: NA
	// Position of REG_SCL_STOP_SETUP_TIME field.
	I3C_MST_SCL_STOP_SETUP_REG_SCL_STOP_SETUP_TIME_Pos = 0x0
	// Bit mask of REG_SCL_STOP_SETUP_TIME field.
	I3C_MST_SCL_STOP_SETUP_REG_SCL_STOP_SETUP_TIME_Msk = 0x1ff

	// BUS_FREE_TIME: NA
	// Position of REG_BUS_FREE_TIME field.
	I3C_MST_BUS_FREE_TIME_REG_BUS_FREE_TIME_Pos = 0x0
	// Bit mask of REG_BUS_FREE_TIME field.
	I3C_MST_BUS_FREE_TIME_REG_BUS_FREE_TIME_Msk = 0xffff

	// SCL_TERMN_T_EXT_LOW_TIME: NA
	// Position of REG_I3C_MST_TERMN_T_EXT_LOW_TIME field.
	I3C_MST_SCL_TERMN_T_EXT_LOW_TIME_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_Pos = 0x0
	// Bit mask of REG_I3C_MST_TERMN_T_EXT_LOW_TIME field.
	I3C_MST_SCL_TERMN_T_EXT_LOW_TIME_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_Msk = 0xff

	// VER_ID: NA
	// Position of REG_I3C_MST_VER_ID field.
	I3C_MST_VER_ID_REG_I3C_MST_VER_ID_Pos = 0x0
	// Bit mask of REG_I3C_MST_VER_ID field.
	I3C_MST_VER_ID_REG_I3C_MST_VER_ID_Msk = 0xffffffff

	// VER_TYPE: NA
	// Position of REG_I3C_MST_VER_TYPE field.
	I3C_MST_VER_TYPE_REG_I3C_MST_VER_TYPE_Pos = 0x0
	// Bit mask of REG_I3C_MST_VER_TYPE field.
	I3C_MST_VER_TYPE_REG_I3C_MST_VER_TYPE_Msk = 0xffffffff

	// FPGA_DEBUG_PROBE: NA
	// Position of REG_I3C_MST_FPGA_DEBUG_PROBE field.
	I3C_MST_FPGA_DEBUG_PROBE_REG_I3C_MST_FPGA_DEBUG_PROBE_Pos = 0x0
	// Bit mask of REG_I3C_MST_FPGA_DEBUG_PROBE field.
	I3C_MST_FPGA_DEBUG_PROBE_REG_I3C_MST_FPGA_DEBUG_PROBE_Msk = 0xffffffff

	// RND_ECO_CS: NA
	// Position of REG_RND_ECO_EN field.
	I3C_MST_RND_ECO_CS_REG_RND_ECO_EN_Pos = 0x0
	// Bit mask of REG_RND_ECO_EN field.
	I3C_MST_RND_ECO_CS_REG_RND_ECO_EN_Msk = 0x1
	// Bit REG_RND_ECO_EN.
	I3C_MST_RND_ECO_CS_REG_RND_ECO_EN = 0x1
	// Position of RND_ECO_RESULT field.
	I3C_MST_RND_ECO_CS_RND_ECO_RESULT_Pos = 0x1
	// Bit mask of RND_ECO_RESULT field.
	I3C_MST_RND_ECO_CS_RND_ECO_RESULT_Msk = 0x2
	// Bit RND_ECO_RESULT.
	I3C_MST_RND_ECO_CS_RND_ECO_RESULT = 0x2

	// RND_ECO_LOW: NA
	// Position of REG_RND_ECO_LOW field.
	I3C_MST_RND_ECO_LOW_REG_RND_ECO_LOW_Pos = 0x0
	// Bit mask of REG_RND_ECO_LOW field.
	I3C_MST_RND_ECO_LOW_REG_RND_ECO_LOW_Msk = 0xffffffff

	// RND_ECO_HIGH: NA
	// Position of REG_RND_ECO_HIGH field.
	I3C_MST_RND_ECO_HIGH_REG_RND_ECO_HIGH_Pos = 0x0
	// Bit mask of REG_RND_ECO_HIGH field.
	I3C_MST_RND_ECO_HIGH_REG_RND_ECO_HIGH_Msk = 0xffffffff
)

// Constants for I3C_MST_MEM: I3C_MST_MEM Peripheral
const (
	// COMMAND_BUF_PORT: NA
	// Position of REG_COMMAND field.
	I3C_MST_MEM_COMMAND_BUF_PORT_REG_COMMAND_Pos = 0x0
	// Bit mask of REG_COMMAND field.
	I3C_MST_MEM_COMMAND_BUF_PORT_REG_COMMAND_Msk = 0xffffffff

	// RESPONSE_BUF_PORT: NA
	// Position of RESPONSE field.
	I3C_MST_MEM_RESPONSE_BUF_PORT_RESPONSE_Pos = 0x0
	// Bit mask of RESPONSE field.
	I3C_MST_MEM_RESPONSE_BUF_PORT_RESPONSE_Msk = 0xffffffff

	// RX_DATA_PORT: NA
	// Position of RX_DATA_PORT field.
	I3C_MST_MEM_RX_DATA_PORT_RX_DATA_PORT_Pos = 0x0
	// Bit mask of RX_DATA_PORT field.
	I3C_MST_MEM_RX_DATA_PORT_RX_DATA_PORT_Msk = 0xffffffff

	// TX_DATA_PORT: NA
	// Position of REG_TX_DATA_PORT field.
	I3C_MST_MEM_TX_DATA_PORT_REG_TX_DATA_PORT_Pos = 0x0
	// Bit mask of REG_TX_DATA_PORT field.
	I3C_MST_MEM_TX_DATA_PORT_REG_TX_DATA_PORT_Msk = 0xffffffff

	// IBI_STATUS_BUF: In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
	// Position of DATA_LENGTH field.
	I3C_MST_MEM_IBI_STATUS_BUF_DATA_LENGTH_Pos = 0x0
	// Bit mask of DATA_LENGTH field.
	I3C_MST_MEM_IBI_STATUS_BUF_DATA_LENGTH_Msk = 0xff
	// Position of IBI_ID field.
	I3C_MST_MEM_IBI_STATUS_BUF_IBI_ID_Pos = 0x8
	// Bit mask of IBI_ID field.
	I3C_MST_MEM_IBI_STATUS_BUF_IBI_ID_Msk = 0xff00
	// Position of IBI_STS field.
	I3C_MST_MEM_IBI_STATUS_BUF_IBI_STS_Pos = 0x1c
	// Bit mask of IBI_STS field.
	I3C_MST_MEM_IBI_STATUS_BUF_IBI_STS_Msk = 0x10000000
	// Bit IBI_STS.
	I3C_MST_MEM_IBI_STATUS_BUF_IBI_STS = 0x10000000

	// IBI_DATA_BUF: NA
	// Position of IBI_DATA field.
	I3C_MST_MEM_IBI_DATA_BUF_IBI_DATA_Pos = 0x0
	// Bit mask of IBI_DATA field.
	I3C_MST_MEM_IBI_DATA_BUF_IBI_DATA_Msk = 0xffffffff

	// DEV_ADDR_TABLE1_LOC: NA
	// Position of REG_DAT_DEV1_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV1_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV1_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV1_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV1_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV1_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV1_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV1_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV1_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG_DAT_DEV1_I2C = 0x80000000

	// DEV_ADDR_TABLE2_LOC: NA
	// Position of REG_DAT_DEV2_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV2_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV2_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV2_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV2_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV2_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV2_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV2_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV2_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG_DAT_DEV2_I2C = 0x80000000

	// DEV_ADDR_TABLE3_LOC: NA
	// Position of REG_DAT_DEV3_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV3_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV3_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV3_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV3_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV3_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV3_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV3_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV3_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG_DAT_DEV3_I2C = 0x80000000

	// DEV_ADDR_TABLE4_LOC: NA
	// Position of REG_DAT_DEV4_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV4_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV4_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV4_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV4_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV4_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV4_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV4_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV4_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG_DAT_DEV4_I2C = 0x80000000

	// DEV_ADDR_TABLE5_LOC: NA
	// Position of REG_DAT_DEV5_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV5_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV5_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV5_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV5_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV5_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV5_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV5_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV5_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG_DAT_DEV5_I2C = 0x80000000

	// DEV_ADDR_TABLE6_LOC: NA
	// Position of REG_DAT_DEV6_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV6_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV6_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV6_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV6_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV6_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV6_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV6_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV6_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG_DAT_DEV6_I2C = 0x80000000

	// DEV_ADDR_TABLE7_LOC: NA
	// Position of REG_DAT_DEV7_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV7_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV7_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV7_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV7_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV7_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV7_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV7_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV7_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG_DAT_DEV7_I2C = 0x80000000

	// DEV_ADDR_TABLE8_LOC: NA
	// Position of REG_DAT_DEV8_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV8_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV8_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV8_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV8_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV8_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV8_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV8_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV8_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG_DAT_DEV8_I2C = 0x80000000

	// DEV_ADDR_TABLE9_LOC: NA
	// Position of REG_DAT_DEV9_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV9_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV9_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV9_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV9_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV9_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV9_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV9_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV9_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG_DAT_DEV9_I2C = 0x80000000

	// DEV_ADDR_TABLE10_LOC: NA
	// Position of REG_DAT_DEV10_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV10_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV10_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV10_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV10_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV10_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV10_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV10_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV10_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG_DAT_DEV10_I2C = 0x80000000

	// DEV_ADDR_TABLE11_LOC: NA
	// Position of REG_DAT_DEV11_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV11_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV11_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV11_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV11_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV11_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV11_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV11_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV11_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG_DAT_DEV11_I2C = 0x80000000

	// DEV_ADDR_TABLE12_LOC: NA
	// Position of REG_DAT_DEV12_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_STATIC_ADDR_Pos = 0x0
	// Bit mask of REG_DAT_DEV12_STATIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_STATIC_ADDR_Msk = 0x7f
	// Position of REG_DAT_DEV12_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_DYNAMIC_ADDR_Pos = 0x10
	// Bit mask of REG_DAT_DEV12_DYNAMIC_ADDR field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_DYNAMIC_ADDR_Msk = 0xff0000
	// Position of REG_DAT_DEV12_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_NACK_RETRY_CNT_Pos = 0x1d
	// Bit mask of REG_DAT_DEV12_NACK_RETRY_CNT field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_NACK_RETRY_CNT_Msk = 0x60000000
	// Position of REG_DAT_DEV12_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_I2C_Pos = 0x1f
	// Bit mask of REG_DAT_DEV12_I2C field.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_I2C_Msk = 0x80000000
	// Bit REG_DAT_DEV12_I2C.
	I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG_DAT_DEV12_I2C = 0x80000000

	// DEV_CHAR_TABLE1_LOC1: NA
	// Position of DCT_DEV1_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC1_DCT_DEV1_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV1_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC1_DCT_DEV1_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE1_LOC2: NA
	// Position of DCT_DEV1_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC2_DCT_DEV1_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV1_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC2_DCT_DEV1_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE1_LOC3: NA
	// Position of DCT_DEV1_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC3_DCT_DEV1_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV1_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC3_DCT_DEV1_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE1_LOC4: NA
	// Position of DCT_DEV1_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC4_DCT_DEV1_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV1_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE1_LOC4_DCT_DEV1_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE2_LOC1: NA
	// Position of DCT_DEV2_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC1_DCT_DEV2_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV2_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC1_DCT_DEV2_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE2_LOC2: NA
	// Position of DCT_DEV2_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC2_DCT_DEV2_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV2_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC2_DCT_DEV2_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE2_LOC3: NA
	// Position of DCT_DEV2_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC3_DCT_DEV2_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV2_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC3_DCT_DEV2_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE2_LOC4: NA
	// Position of DCT_DEV2_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC4_DCT_DEV2_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV2_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE2_LOC4_DCT_DEV2_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE3_LOC1: NA
	// Position of DCT_DEV3_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC1_DCT_DEV3_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV3_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC1_DCT_DEV3_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE3_LOC2: NA
	// Position of DCT_DEV3_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC2_DCT_DEV3_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV3_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC2_DCT_DEV3_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE3_LOC3: NA
	// Position of DCT_DEV3_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC3_DCT_DEV3_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV3_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC3_DCT_DEV3_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE3_LOC4: NA
	// Position of DCT_DEV3_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC4_DCT_DEV3_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV3_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE3_LOC4_DCT_DEV3_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE4_LOC1: NA
	// Position of DCT_DEV4_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC1_DCT_DEV4_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV4_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC1_DCT_DEV4_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE4_LOC2: NA
	// Position of DCT_DEV4_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC2_DCT_DEV4_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV4_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC2_DCT_DEV4_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE4_LOC3: NA
	// Position of DCT_DEV4_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC3_DCT_DEV4_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV4_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC3_DCT_DEV4_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE4_LOC4: NA
	// Position of DCT_DEV4_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC4_DCT_DEV4_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV4_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE4_LOC4_DCT_DEV4_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE5_LOC1: NA
	// Position of DCT_DEV5_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC1_DCT_DEV5_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV5_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC1_DCT_DEV5_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE5_LOC2: NA
	// Position of DCT_DEV5_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC2_DCT_DEV5_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV5_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC2_DCT_DEV5_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE5_LOC3: NA
	// Position of DCT_DEV5_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC3_DCT_DEV5_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV5_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC3_DCT_DEV5_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE5_LOC4: NA
	// Position of DCT_DEV5_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC4_DCT_DEV5_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV5_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE5_LOC4_DCT_DEV5_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE6_LOC1: NA
	// Position of DCT_DEV6_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC1_DCT_DEV6_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV6_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC1_DCT_DEV6_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE6_LOC2: NA
	// Position of DCT_DEV6_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC2_DCT_DEV6_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV6_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC2_DCT_DEV6_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE6_LOC3: NA
	// Position of DCT_DEV6_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC3_DCT_DEV6_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV6_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC3_DCT_DEV6_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE6_LOC4: NA
	// Position of DCT_DEV6_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC4_DCT_DEV6_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV6_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE6_LOC4_DCT_DEV6_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE7_LOC1: NA
	// Position of DCT_DEV7_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC1_DCT_DEV7_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV7_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC1_DCT_DEV7_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE7_LOC2: NA
	// Position of DCT_DEV7_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC2_DCT_DEV7_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV7_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC2_DCT_DEV7_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE7_LOC3: NA
	// Position of DCT_DEV7_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC3_DCT_DEV7_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV7_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC3_DCT_DEV7_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE7_LOC4: NA
	// Position of DCT_DEV7_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC4_DCT_DEV7_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV7_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE7_LOC4_DCT_DEV7_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE8_LOC1: NA
	// Position of DCT_DEV8_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC1_DCT_DEV8_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV8_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC1_DCT_DEV8_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE8_LOC2: NA
	// Position of DCT_DEV8_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC2_DCT_DEV8_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV8_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC2_DCT_DEV8_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE8_LOC3: NA
	// Position of DCT_DEV8_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC3_DCT_DEV8_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV8_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC3_DCT_DEV8_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE8_LOC4: NA
	// Position of DCT_DEV8_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC4_DCT_DEV8_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV8_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE8_LOC4_DCT_DEV8_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE9_LOC1: NA
	// Position of DCT_DEV9_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC1_DCT_DEV9_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV9_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC1_DCT_DEV9_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE9_LOC2: NA
	// Position of DCT_DEV9_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC2_DCT_DEV9_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV9_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC2_DCT_DEV9_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE9_LOC3: NA
	// Position of DCT_DEV9_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC3_DCT_DEV9_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV9_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC3_DCT_DEV9_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE9_LOC4: NA
	// Position of DCT_DEV9_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC4_DCT_DEV9_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV9_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE9_LOC4_DCT_DEV9_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE10_LOC1: NA
	// Position of DCT_DEV10_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC1_DCT_DEV10_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV10_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC1_DCT_DEV10_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE10_LOC2: NA
	// Position of DCT_DEV10_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC2_DCT_DEV10_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV10_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC2_DCT_DEV10_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE10_LOC3: NA
	// Position of DCT_DEV10_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC3_DCT_DEV10_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV10_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC3_DCT_DEV10_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE10_LOC4: NA
	// Position of DCT_DEV10_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC4_DCT_DEV10_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV10_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE10_LOC4_DCT_DEV10_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE11_LOC1: NA
	// Position of DCT_DEV11_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC1_DCT_DEV11_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV11_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC1_DCT_DEV11_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE11_LOC2: NA
	// Position of DCT_DEV11_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC2_DCT_DEV11_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV11_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC2_DCT_DEV11_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE11_LOC3: NA
	// Position of DCT_DEV11_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC3_DCT_DEV11_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV11_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC3_DCT_DEV11_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE11_LOC4: NA
	// Position of DCT_DEV11_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC4_DCT_DEV11_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV11_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE11_LOC4_DCT_DEV11_LOC4_Msk = 0xffffffff

	// DEV_CHAR_TABLE12_LOC1: NA
	// Position of DCT_DEV12_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC1_DCT_DEV12_LOC1_Pos = 0x0
	// Bit mask of DCT_DEV12_LOC1 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC1_DCT_DEV12_LOC1_Msk = 0xffffffff

	// DEV_CHAR_TABLE12_LOC2: NA
	// Position of DCT_DEV12_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC2_DCT_DEV12_LOC2_Pos = 0x0
	// Bit mask of DCT_DEV12_LOC2 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC2_DCT_DEV12_LOC2_Msk = 0xffffffff

	// DEV_CHAR_TABLE12_LOC3: NA
	// Position of DCT_DEV12_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC3_DCT_DEV12_LOC3_Pos = 0x0
	// Bit mask of DCT_DEV12_LOC3 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC3_DCT_DEV12_LOC3_Msk = 0xffffffff

	// DEV_CHAR_TABLE12_LOC4: NA
	// Position of DCT_DEV12_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC4_DCT_DEV12_LOC4_Pos = 0x0
	// Bit mask of DCT_DEV12_LOC4 field.
	I3C_MST_MEM_DEV_CHAR_TABLE12_LOC4_DCT_DEV12_LOC4_Msk = 0xffffffff
)

// Constants for I3C_SLV: I3C Controller (Slave)
const (
	// CONFIG: NA
	// Position of SLVENA field.
	I3C_SLV_CONFIG_SLVENA_Pos = 0x0
	// Bit mask of SLVENA field.
	I3C_SLV_CONFIG_SLVENA_Msk = 0x1
	// Bit SLVENA.
	I3C_SLV_CONFIG_SLVENA = 0x1
	// Position of NACK field.
	I3C_SLV_CONFIG_NACK_Pos = 0x1
	// Bit mask of NACK field.
	I3C_SLV_CONFIG_NACK_Msk = 0x2
	// Bit NACK.
	I3C_SLV_CONFIG_NACK = 0x2
	// Position of MATCHSS field.
	I3C_SLV_CONFIG_MATCHSS_Pos = 0x2
	// Bit mask of MATCHSS field.
	I3C_SLV_CONFIG_MATCHSS_Msk = 0x4
	// Bit MATCHSS.
	I3C_SLV_CONFIG_MATCHSS = 0x4
	// Position of S0IGNORE field.
	I3C_SLV_CONFIG_S0IGNORE_Pos = 0x3
	// Bit mask of S0IGNORE field.
	I3C_SLV_CONFIG_S0IGNORE_Msk = 0x8
	// Bit S0IGNORE.
	I3C_SLV_CONFIG_S0IGNORE = 0x8
	// Position of DDROK field.
	I3C_SLV_CONFIG_DDROK_Pos = 0x4
	// Bit mask of DDROK field.
	I3C_SLV_CONFIG_DDROK_Msk = 0x10
	// Bit DDROK.
	I3C_SLV_CONFIG_DDROK = 0x10
	// Position of IDRAND field.
	I3C_SLV_CONFIG_IDRAND_Pos = 0x8
	// Bit mask of IDRAND field.
	I3C_SLV_CONFIG_IDRAND_Msk = 0x100
	// Bit IDRAND.
	I3C_SLV_CONFIG_IDRAND = 0x100
	// Position of OFFLINE field.
	I3C_SLV_CONFIG_OFFLINE_Pos = 0x9
	// Bit mask of OFFLINE field.
	I3C_SLV_CONFIG_OFFLINE_Msk = 0x200
	// Bit OFFLINE.
	I3C_SLV_CONFIG_OFFLINE = 0x200
	// Position of BAMATCH field.
	I3C_SLV_CONFIG_BAMATCH_Pos = 0x10
	// Bit mask of BAMATCH field.
	I3C_SLV_CONFIG_BAMATCH_Msk = 0xff0000
	// Position of SADDR field.
	I3C_SLV_CONFIG_SADDR_Pos = 0x19
	// Bit mask of SADDR field.
	I3C_SLV_CONFIG_SADDR_Msk = 0xfe000000

	// STATUS: NA
	// Position of STNOTSTOP field.
	I3C_SLV_STATUS_STNOTSTOP_Pos = 0x0
	// Bit mask of STNOTSTOP field.
	I3C_SLV_STATUS_STNOTSTOP_Msk = 0x1
	// Bit STNOTSTOP.
	I3C_SLV_STATUS_STNOTSTOP = 0x1
	// Position of STMSG field.
	I3C_SLV_STATUS_STMSG_Pos = 0x1
	// Bit mask of STMSG field.
	I3C_SLV_STATUS_STMSG_Msk = 0x2
	// Bit STMSG.
	I3C_SLV_STATUS_STMSG = 0x2
	// Position of STCCCH field.
	I3C_SLV_STATUS_STCCCH_Pos = 0x2
	// Bit mask of STCCCH field.
	I3C_SLV_STATUS_STCCCH_Msk = 0x4
	// Bit STCCCH.
	I3C_SLV_STATUS_STCCCH = 0x4
	// Position of STREQRD field.
	I3C_SLV_STATUS_STREQRD_Pos = 0x3
	// Bit mask of STREQRD field.
	I3C_SLV_STATUS_STREQRD_Msk = 0x8
	// Bit STREQRD.
	I3C_SLV_STATUS_STREQRD = 0x8
	// Position of STREQWR field.
	I3C_SLV_STATUS_STREQWR_Pos = 0x4
	// Bit mask of STREQWR field.
	I3C_SLV_STATUS_STREQWR_Msk = 0x10
	// Bit STREQWR.
	I3C_SLV_STATUS_STREQWR = 0x10
	// Position of STDAA field.
	I3C_SLV_STATUS_STDAA_Pos = 0x5
	// Bit mask of STDAA field.
	I3C_SLV_STATUS_STDAA_Msk = 0x20
	// Bit STDAA.
	I3C_SLV_STATUS_STDAA = 0x20
	// Position of STHDR field.
	I3C_SLV_STATUS_STHDR_Pos = 0x6
	// Bit mask of STHDR field.
	I3C_SLV_STATUS_STHDR_Msk = 0x40
	// Bit STHDR.
	I3C_SLV_STATUS_STHDR = 0x40
	// Position of START field.
	I3C_SLV_STATUS_START_Pos = 0x8
	// Bit mask of START field.
	I3C_SLV_STATUS_START_Msk = 0x100
	// Bit START.
	I3C_SLV_STATUS_START = 0x100
	// Position of MATCHED field.
	I3C_SLV_STATUS_MATCHED_Pos = 0x9
	// Bit mask of MATCHED field.
	I3C_SLV_STATUS_MATCHED_Msk = 0x200
	// Bit MATCHED.
	I3C_SLV_STATUS_MATCHED = 0x200
	// Position of STOP field.
	I3C_SLV_STATUS_STOP_Pos = 0xa
	// Bit mask of STOP field.
	I3C_SLV_STATUS_STOP_Msk = 0x400
	// Bit STOP.
	I3C_SLV_STATUS_STOP = 0x400
	// Position of RXPEND field.
	I3C_SLV_STATUS_RXPEND_Pos = 0xb
	// Bit mask of RXPEND field.
	I3C_SLV_STATUS_RXPEND_Msk = 0x800
	// Bit RXPEND.
	I3C_SLV_STATUS_RXPEND = 0x800
	// Position of TXNOTFULL field.
	I3C_SLV_STATUS_TXNOTFULL_Pos = 0xc
	// Bit mask of TXNOTFULL field.
	I3C_SLV_STATUS_TXNOTFULL_Msk = 0x1000
	// Bit TXNOTFULL.
	I3C_SLV_STATUS_TXNOTFULL = 0x1000
	// Position of DACHG field.
	I3C_SLV_STATUS_DACHG_Pos = 0xd
	// Bit mask of DACHG field.
	I3C_SLV_STATUS_DACHG_Msk = 0x2000
	// Bit DACHG.
	I3C_SLV_STATUS_DACHG = 0x2000
	// Position of CCC field.
	I3C_SLV_STATUS_CCC_Pos = 0xe
	// Bit mask of CCC field.
	I3C_SLV_STATUS_CCC_Msk = 0x4000
	// Bit CCC.
	I3C_SLV_STATUS_CCC = 0x4000
	// Position of ERRWARN field.
	I3C_SLV_STATUS_ERRWARN_Pos = 0xf
	// Bit mask of ERRWARN field.
	I3C_SLV_STATUS_ERRWARN_Msk = 0x8000
	// Bit ERRWARN.
	I3C_SLV_STATUS_ERRWARN = 0x8000
	// Position of HDRMATCH field.
	I3C_SLV_STATUS_HDRMATCH_Pos = 0x10
	// Bit mask of HDRMATCH field.
	I3C_SLV_STATUS_HDRMATCH_Msk = 0x10000
	// Bit HDRMATCH.
	I3C_SLV_STATUS_HDRMATCH = 0x10000

	// CTRL: NA
	// Position of SLV_EVENT field.
	I3C_SLV_CTRL_SLV_EVENT_Pos = 0x0
	// Bit mask of SLV_EVENT field.
	I3C_SLV_CTRL_SLV_EVENT_Msk = 0x3
	// Position of EXTDATA field.
	I3C_SLV_CTRL_EXTDATA_Pos = 0x3
	// Bit mask of EXTDATA field.
	I3C_SLV_CTRL_EXTDATA_Msk = 0x8
	// Bit EXTDATA.
	I3C_SLV_CTRL_EXTDATA = 0x8
	// Position of MAPIDX field.
	I3C_SLV_CTRL_MAPIDX_Pos = 0x4
	// Bit mask of MAPIDX field.
	I3C_SLV_CTRL_MAPIDX_Msk = 0xf0
	// Position of IBIDATA field.
	I3C_SLV_CTRL_IBIDATA_Pos = 0x8
	// Bit mask of IBIDATA field.
	I3C_SLV_CTRL_IBIDATA_Msk = 0xff00
	// Position of PENDINT field.
	I3C_SLV_CTRL_PENDINT_Pos = 0x10
	// Bit mask of PENDINT field.
	I3C_SLV_CTRL_PENDINT_Msk = 0xf0000
	// Position of ACTSTATE field.
	I3C_SLV_CTRL_ACTSTATE_Pos = 0x14
	// Bit mask of ACTSTATE field.
	I3C_SLV_CTRL_ACTSTATE_Msk = 0x300000
	// Position of VENDINFO field.
	I3C_SLV_CTRL_VENDINFO_Pos = 0x18
	// Bit mask of VENDINFO field.
	I3C_SLV_CTRL_VENDINFO_Msk = 0xff000000

	// INTSET: INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor)
	// Position of STOP_ENA field.
	I3C_SLV_INTSET_STOP_ENA_Pos = 0xa
	// Bit mask of STOP_ENA field.
	I3C_SLV_INTSET_STOP_ENA_Msk = 0x400
	// Bit STOP_ENA.
	I3C_SLV_INTSET_STOP_ENA = 0x400
	// Position of RXPEND_ENA field.
	I3C_SLV_INTSET_RXPEND_ENA_Pos = 0xb
	// Bit mask of RXPEND_ENA field.
	I3C_SLV_INTSET_RXPEND_ENA_Msk = 0x800
	// Bit RXPEND_ENA.
	I3C_SLV_INTSET_RXPEND_ENA = 0x800
	// Position of TXSEND_ENA field.
	I3C_SLV_INTSET_TXSEND_ENA_Pos = 0xc
	// Bit mask of TXSEND_ENA field.
	I3C_SLV_INTSET_TXSEND_ENA_Msk = 0x1000
	// Bit TXSEND_ENA.
	I3C_SLV_INTSET_TXSEND_ENA = 0x1000

	// INTCLR: NA
	// Position of STOP_CLR field.
	I3C_SLV_INTCLR_STOP_CLR_Pos = 0xa
	// Bit mask of STOP_CLR field.
	I3C_SLV_INTCLR_STOP_CLR_Msk = 0x400
	// Bit STOP_CLR.
	I3C_SLV_INTCLR_STOP_CLR = 0x400
	// Position of RXPEND_CLR field.
	I3C_SLV_INTCLR_RXPEND_CLR_Pos = 0xb
	// Bit mask of RXPEND_CLR field.
	I3C_SLV_INTCLR_RXPEND_CLR_Msk = 0x800
	// Bit RXPEND_CLR.
	I3C_SLV_INTCLR_RXPEND_CLR = 0x800
	// Position of TXSEND_CLR field.
	I3C_SLV_INTCLR_TXSEND_CLR_Pos = 0xc
	// Bit mask of TXSEND_CLR field.
	I3C_SLV_INTCLR_TXSEND_CLR_Msk = 0x1000
	// Bit TXSEND_CLR.
	I3C_SLV_INTCLR_TXSEND_CLR = 0x1000

	// INTMASKED: NA
	// Position of STOP_MASK field.
	I3C_SLV_INTMASKED_STOP_MASK_Pos = 0xa
	// Bit mask of STOP_MASK field.
	I3C_SLV_INTMASKED_STOP_MASK_Msk = 0x400
	// Bit STOP_MASK.
	I3C_SLV_INTMASKED_STOP_MASK = 0x400
	// Position of RXPEND_MASK field.
	I3C_SLV_INTMASKED_RXPEND_MASK_Pos = 0xb
	// Bit mask of RXPEND_MASK field.
	I3C_SLV_INTMASKED_RXPEND_MASK_Msk = 0x800
	// Bit RXPEND_MASK.
	I3C_SLV_INTMASKED_RXPEND_MASK = 0x800
	// Position of TXSEND_MASK field.
	I3C_SLV_INTMASKED_TXSEND_MASK_Pos = 0xc
	// Bit mask of TXSEND_MASK field.
	I3C_SLV_INTMASKED_TXSEND_MASK_Msk = 0x1000
	// Bit TXSEND_MASK.
	I3C_SLV_INTMASKED_TXSEND_MASK = 0x1000

	// DATACTRL: NA
	// Position of FLUSHTB field.
	I3C_SLV_DATACTRL_FLUSHTB_Pos = 0x0
	// Bit mask of FLUSHTB field.
	I3C_SLV_DATACTRL_FLUSHTB_Msk = 0x1
	// Bit FLUSHTB.
	I3C_SLV_DATACTRL_FLUSHTB = 0x1
	// Position of FLUSHFB field.
	I3C_SLV_DATACTRL_FLUSHFB_Pos = 0x1
	// Bit mask of FLUSHFB field.
	I3C_SLV_DATACTRL_FLUSHFB_Msk = 0x2
	// Bit FLUSHFB.
	I3C_SLV_DATACTRL_FLUSHFB = 0x2
	// Position of UNLOCK field.
	I3C_SLV_DATACTRL_UNLOCK_Pos = 0x3
	// Bit mask of UNLOCK field.
	I3C_SLV_DATACTRL_UNLOCK_Msk = 0x8
	// Bit UNLOCK.
	I3C_SLV_DATACTRL_UNLOCK = 0x8
	// Position of TXTRIG field.
	I3C_SLV_DATACTRL_TXTRIG_Pos = 0x4
	// Bit mask of TXTRIG field.
	I3C_SLV_DATACTRL_TXTRIG_Msk = 0x30
	// Position of RXTRIG field.
	I3C_SLV_DATACTRL_RXTRIG_Pos = 0x6
	// Bit mask of RXTRIG field.
	I3C_SLV_DATACTRL_RXTRIG_Msk = 0xc0
	// Position of TXCOUNT field.
	I3C_SLV_DATACTRL_TXCOUNT_Pos = 0x10
	// Bit mask of TXCOUNT field.
	I3C_SLV_DATACTRL_TXCOUNT_Msk = 0x1f0000
	// Position of RXCOUNT field.
	I3C_SLV_DATACTRL_RXCOUNT_Pos = 0x18
	// Bit mask of RXCOUNT field.
	I3C_SLV_DATACTRL_RXCOUNT_Msk = 0x1f000000
	// Position of TXFULL field.
	I3C_SLV_DATACTRL_TXFULL_Pos = 0x1e
	// Bit mask of TXFULL field.
	I3C_SLV_DATACTRL_TXFULL_Msk = 0x40000000
	// Bit TXFULL.
	I3C_SLV_DATACTRL_TXFULL = 0x40000000
	// Position of RXEMPTY field.
	I3C_SLV_DATACTRL_RXEMPTY_Pos = 0x1f
	// Bit mask of RXEMPTY field.
	I3C_SLV_DATACTRL_RXEMPTY_Msk = 0x80000000
	// Bit RXEMPTY.
	I3C_SLV_DATACTRL_RXEMPTY = 0x80000000

	// WDATAB: NA
	// Position of WDATAB field.
	I3C_SLV_WDATAB_WDATAB_Pos = 0x0
	// Bit mask of WDATAB field.
	I3C_SLV_WDATAB_WDATAB_Msk = 0xff
	// Position of WDATA_END field.
	I3C_SLV_WDATAB_WDATA_END_Pos = 0x8
	// Bit mask of WDATA_END field.
	I3C_SLV_WDATAB_WDATA_END_Msk = 0x100
	// Bit WDATA_END.
	I3C_SLV_WDATAB_WDATA_END = 0x100

	// WDATABE: NA
	// Position of WDATABE field.
	I3C_SLV_WDATABE_WDATABE_Pos = 0x0
	// Bit mask of WDATABE field.
	I3C_SLV_WDATABE_WDATABE_Msk = 0xff

	// RDARAB: Read Byte Data (from-bus) register
	// Position of DATA0 field.
	I3C_SLV_RDARAB_DATA0_Pos = 0x0
	// Bit mask of DATA0 field.
	I3C_SLV_RDARAB_DATA0_Msk = 0xff

	// RDATAH: Read Half-word Data (from-bus) register
	// Position of DATA_LSB field.
	I3C_SLV_RDATAH_DATA_LSB_Pos = 0x0
	// Bit mask of DATA_LSB field.
	I3C_SLV_RDATAH_DATA_LSB_Msk = 0xff
	// Position of DATA_MSB field.
	I3C_SLV_RDATAH_DATA_MSB_Pos = 0x8
	// Bit mask of DATA_MSB field.
	I3C_SLV_RDATAH_DATA_MSB_Msk = 0xff00

	// CAPABILITIES2: NA
	// Position of CAPABLITIES2 field.
	I3C_SLV_CAPABILITIES2_CAPABLITIES2_Pos = 0x0
	// Bit mask of CAPABLITIES2 field.
	I3C_SLV_CAPABILITIES2_CAPABLITIES2_Msk = 0xffffffff

	// CAPABILITIES: NA
	// Position of CAPABLITIES field.
	I3C_SLV_CAPABILITIES_CAPABLITIES_Pos = 0x0
	// Bit mask of CAPABLITIES field.
	I3C_SLV_CAPABILITIES_CAPABLITIES_Msk = 0xffffffff

	// IDPARTNO: NA
	// Position of PARTNO field.
	I3C_SLV_IDPARTNO_PARTNO_Pos = 0x0
	// Bit mask of PARTNO field.
	I3C_SLV_IDPARTNO_PARTNO_Msk = 0xffffffff

	// IDEXT: NA
	// Position of IDEXT field.
	I3C_SLV_IDEXT_IDEXT_Pos = 0x0
	// Bit mask of IDEXT field.
	I3C_SLV_IDEXT_IDEXT_Msk = 0xffffffff

	// VENDORID: NA
	// Position of VID field.
	I3C_SLV_VENDORID_VID_Pos = 0x0
	// Bit mask of VID field.
	I3C_SLV_VENDORID_VID_Msk = 0x7fff
)

// Constants for AXI_ICM: AXI_ICM Peripheral
const (
	// VERID_FILEDS: NA
	// Position of ICM_REG_VERID field.
	ICM_AXI_VERID_FILEDS_ICM_REG_VERID_Pos = 0x0
	// Bit mask of ICM_REG_VERID field.
	ICM_AXI_VERID_FILEDS_ICM_REG_VERID_Msk = 0xffffffff

	// HW_CFG: NA
	// Position of ICM_REG_AXI_HWCFG_QOS_SUPPORT field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_QOS_SUPPORT_Pos = 0x0
	// Bit mask of ICM_REG_AXI_HWCFG_QOS_SUPPORT field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_QOS_SUPPORT_Msk = 0x1
	// Bit ICM_REG_AXI_HWCFG_QOS_SUPPORT.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_QOS_SUPPORT = 0x1
	// Position of ICM_REG_AXI_HWCFG_APB3_SUPPORT field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_APB3_SUPPORT_Pos = 0x1
	// Bit mask of ICM_REG_AXI_HWCFG_APB3_SUPPORT field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_APB3_SUPPORT_Msk = 0x2
	// Bit ICM_REG_AXI_HWCFG_APB3_SUPPORT.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_APB3_SUPPORT = 0x2
	// Position of ICM_REG_AXI_HWCFG_AXI4_SUPPORT field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_AXI4_SUPPORT_Pos = 0x2
	// Bit mask of ICM_REG_AXI_HWCFG_AXI4_SUPPORT field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_AXI4_SUPPORT_Msk = 0x4
	// Bit ICM_REG_AXI_HWCFG_AXI4_SUPPORT.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_AXI4_SUPPORT = 0x4
	// Position of ICM_REG_AXI_HWCFG_LOCK_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_LOCK_EN_Pos = 0x3
	// Bit mask of ICM_REG_AXI_HWCFG_LOCK_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_LOCK_EN_Msk = 0x8
	// Bit ICM_REG_AXI_HWCFG_LOCK_EN.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_LOCK_EN = 0x8
	// Position of ICM_REG_AXI_HWCFG_TRUST_ZONE_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_Pos = 0x4
	// Bit mask of ICM_REG_AXI_HWCFG_TRUST_ZONE_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_Msk = 0x10
	// Bit ICM_REG_AXI_HWCFG_TRUST_ZONE_EN.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_TRUST_ZONE_EN = 0x10
	// Position of ICM_REG_AXI_HWCFG_DECODER_TYPE field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_DECODER_TYPE_Pos = 0x5
	// Bit mask of ICM_REG_AXI_HWCFG_DECODER_TYPE field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_DECODER_TYPE_Msk = 0x20
	// Bit ICM_REG_AXI_HWCFG_DECODER_TYPE.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_DECODER_TYPE = 0x20
	// Position of ICM_REG_AXI_HWCFG_REMAP_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_REMAP_EN_Pos = 0x6
	// Bit mask of ICM_REG_AXI_HWCFG_REMAP_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_REMAP_EN_Msk = 0x40
	// Bit ICM_REG_AXI_HWCFG_REMAP_EN.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_REMAP_EN = 0x40
	// Position of ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_Pos = 0x7
	// Bit mask of ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_Msk = 0x80
	// Bit ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN = 0x80
	// Position of ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_Pos = 0x8
	// Bit mask of ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_Msk = 0x100
	// Bit ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN = 0x100
	// Position of ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_Pos = 0xc
	// Bit mask of ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_Msk = 0x1f000
	// Position of ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_Pos = 0x14
	// Bit mask of ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES field.
	ICM_AXI_HW_CFG_ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_Msk = 0x1f00000

	// CMD: NA
	// Position of ICM_REG_AXI_CMD field.
	ICM_AXI_CMD_ICM_REG_AXI_CMD_Pos = 0x0
	// Bit mask of ICM_REG_AXI_CMD field.
	ICM_AXI_CMD_ICM_REG_AXI_CMD_Msk = 0x7
	// Position of ICM_REG_RD_WR_CHAN field.
	ICM_AXI_CMD_ICM_REG_RD_WR_CHAN_Pos = 0x7
	// Bit mask of ICM_REG_RD_WR_CHAN field.
	ICM_AXI_CMD_ICM_REG_RD_WR_CHAN_Msk = 0x80
	// Bit ICM_REG_RD_WR_CHAN.
	ICM_AXI_CMD_ICM_REG_RD_WR_CHAN = 0x80
	// Position of ICM_REG_AXI_MASTER_PORT field.
	ICM_AXI_CMD_ICM_REG_AXI_MASTER_PORT_Pos = 0x8
	// Bit mask of ICM_REG_AXI_MASTER_PORT field.
	ICM_AXI_CMD_ICM_REG_AXI_MASTER_PORT_Msk = 0xf00
	// Position of ICM_REG_AXI_ERR_BIT field.
	ICM_AXI_CMD_ICM_REG_AXI_ERR_BIT_Pos = 0x1c
	// Bit mask of ICM_REG_AXI_ERR_BIT field.
	ICM_AXI_CMD_ICM_REG_AXI_ERR_BIT_Msk = 0x10000000
	// Bit ICM_REG_AXI_ERR_BIT.
	ICM_AXI_CMD_ICM_REG_AXI_ERR_BIT = 0x10000000
	// Position of ICM_REG_AXI_SOFT_RESET_BIT field.
	ICM_AXI_CMD_ICM_REG_AXI_SOFT_RESET_BIT_Pos = 0x1d
	// Bit mask of ICM_REG_AXI_SOFT_RESET_BIT field.
	ICM_AXI_CMD_ICM_REG_AXI_SOFT_RESET_BIT_Msk = 0x20000000
	// Bit ICM_REG_AXI_SOFT_RESET_BIT.
	ICM_AXI_CMD_ICM_REG_AXI_SOFT_RESET_BIT = 0x20000000
	// Position of ICM_REG_AXI_RD_WR_CMD field.
	ICM_AXI_CMD_ICM_REG_AXI_RD_WR_CMD_Pos = 0x1e
	// Bit mask of ICM_REG_AXI_RD_WR_CMD field.
	ICM_AXI_CMD_ICM_REG_AXI_RD_WR_CMD_Msk = 0x40000000
	// Bit ICM_REG_AXI_RD_WR_CMD.
	ICM_AXI_CMD_ICM_REG_AXI_RD_WR_CMD = 0x40000000
	// Position of ICM_REG_AXI_CMD_EN field.
	ICM_AXI_CMD_ICM_REG_AXI_CMD_EN_Pos = 0x1f
	// Bit mask of ICM_REG_AXI_CMD_EN field.
	ICM_AXI_CMD_ICM_REG_AXI_CMD_EN_Msk = 0x80000000
	// Bit ICM_REG_AXI_CMD_EN.
	ICM_AXI_CMD_ICM_REG_AXI_CMD_EN = 0x80000000

	// DATA: NA
	// Position of ICM_REG_DATA field.
	ICM_AXI_DATA_ICM_REG_DATA_Pos = 0x0
	// Bit mask of ICM_REG_DATA field.
	ICM_AXI_DATA_ICM_REG_DATA_Msk = 0xffffffff
)

// Constants for IO_MUX: Input/Output Multiplexer
const (
	// GPIO0: IO_MUX Control Register
	// Position of MCU_OE field.
	IO_MUX_GPIO_MCU_OE_Pos = 0x0
	// Bit mask of MCU_OE field.
	IO_MUX_GPIO_MCU_OE_Msk = 0x1
	// Bit MCU_OE.
	IO_MUX_GPIO_MCU_OE = 0x1
	// Position of SLP_SEL field.
	IO_MUX_GPIO_SLP_SEL_Pos = 0x1
	// Bit mask of SLP_SEL field.
	IO_MUX_GPIO_SLP_SEL_Msk = 0x2
	// Bit SLP_SEL.
	IO_MUX_GPIO_SLP_SEL = 0x2
	// Position of MCU_WPD field.
	IO_MUX_GPIO_MCU_WPD_Pos = 0x2
	// Bit mask of MCU_WPD field.
	IO_MUX_GPIO_MCU_WPD_Msk = 0x4
	// Bit MCU_WPD.
	IO_MUX_GPIO_MCU_WPD = 0x4
	// Position of MCU_WPU field.
	IO_MUX_GPIO_MCU_WPU_Pos = 0x3
	// Bit mask of MCU_WPU field.
	IO_MUX_GPIO_MCU_WPU_Msk = 0x8
	// Bit MCU_WPU.
	IO_MUX_GPIO_MCU_WPU = 0x8
	// Position of MCU_IE field.
	IO_MUX_GPIO_MCU_IE_Pos = 0x4
	// Bit mask of MCU_IE field.
	IO_MUX_GPIO_MCU_IE_Msk = 0x10
	// Bit MCU_IE.
	IO_MUX_GPIO_MCU_IE = 0x10
	// Position of MCU_DRV field.
	IO_MUX_GPIO_MCU_DRV_Pos = 0x5
	// Bit mask of MCU_DRV field.
	IO_MUX_GPIO_MCU_DRV_Msk = 0x60
	// Position of FUN_WPD field.
	IO_MUX_GPIO_FUN_WPD_Pos = 0x7
	// Bit mask of FUN_WPD field.
	IO_MUX_GPIO_FUN_WPD_Msk = 0x80
	// Bit FUN_WPD.
	IO_MUX_GPIO_FUN_WPD = 0x80
	// Position of FUN_WPU field.
	IO_MUX_GPIO_FUN_WPU_Pos = 0x8
	// Bit mask of FUN_WPU field.
	IO_MUX_GPIO_FUN_WPU_Msk = 0x100
	// Bit FUN_WPU.
	IO_MUX_GPIO_FUN_WPU = 0x100
	// Position of FUN_IE field.
	IO_MUX_GPIO_FUN_IE_Pos = 0x9
	// Bit mask of FUN_IE field.
	IO_MUX_GPIO_FUN_IE_Msk = 0x200
	// Bit FUN_IE.
	IO_MUX_GPIO_FUN_IE = 0x200
	// Position of FUN_DRV field.
	IO_MUX_GPIO_FUN_DRV_Pos = 0xa
	// Bit mask of FUN_DRV field.
	IO_MUX_GPIO_FUN_DRV_Msk = 0xc00
	// Position of MCU_SEL field.
	IO_MUX_GPIO_MCU_SEL_Pos = 0xc
	// Bit mask of MCU_SEL field.
	IO_MUX_GPIO_MCU_SEL_Msk = 0x7000
	// Position of FILTER_EN field.
	IO_MUX_GPIO_FILTER_EN_Pos = 0xf
	// Bit mask of FILTER_EN field.
	IO_MUX_GPIO_FILTER_EN_Msk = 0x8000
	// Bit FILTER_EN.
	IO_MUX_GPIO_FILTER_EN = 0x8000

	// DATE: iomux version
	// Position of DATE field.
	IO_MUX_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	IO_MUX_DATE_DATE_Msk = 0xfffffff
)

// Constants for ISP: ISP Peripheral
const (
	// VER_DATE: version control register
	// Position of VER_DATA field.
	ISP_VER_DATE_VER_DATA_Pos = 0x0
	// Bit mask of VER_DATA field.
	ISP_VER_DATE_VER_DATA_Msk = 0xffffffff

	// CLK_EN: isp clk control register
	// Position of CLK_EN field.
	ISP_CLK_EN_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	ISP_CLK_EN_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	ISP_CLK_EN_CLK_EN = 0x1
	// Position of CLK_BLC_FORCE_ON field.
	ISP_CLK_EN_CLK_BLC_FORCE_ON_Pos = 0x1
	// Bit mask of CLK_BLC_FORCE_ON field.
	ISP_CLK_EN_CLK_BLC_FORCE_ON_Msk = 0x2
	// Bit CLK_BLC_FORCE_ON.
	ISP_CLK_EN_CLK_BLC_FORCE_ON = 0x2
	// Position of CLK_DPC_FORCE_ON field.
	ISP_CLK_EN_CLK_DPC_FORCE_ON_Pos = 0x2
	// Bit mask of CLK_DPC_FORCE_ON field.
	ISP_CLK_EN_CLK_DPC_FORCE_ON_Msk = 0x4
	// Bit CLK_DPC_FORCE_ON.
	ISP_CLK_EN_CLK_DPC_FORCE_ON = 0x4
	// Position of CLK_BF_FORCE_ON field.
	ISP_CLK_EN_CLK_BF_FORCE_ON_Pos = 0x3
	// Bit mask of CLK_BF_FORCE_ON field.
	ISP_CLK_EN_CLK_BF_FORCE_ON_Msk = 0x8
	// Bit CLK_BF_FORCE_ON.
	ISP_CLK_EN_CLK_BF_FORCE_ON = 0x8
	// Position of CLK_LSC_FORCE_ON field.
	ISP_CLK_EN_CLK_LSC_FORCE_ON_Pos = 0x4
	// Bit mask of CLK_LSC_FORCE_ON field.
	ISP_CLK_EN_CLK_LSC_FORCE_ON_Msk = 0x10
	// Bit CLK_LSC_FORCE_ON.
	ISP_CLK_EN_CLK_LSC_FORCE_ON = 0x10
	// Position of CLK_DEMOSAIC_FORCE_ON field.
	ISP_CLK_EN_CLK_DEMOSAIC_FORCE_ON_Pos = 0x5
	// Bit mask of CLK_DEMOSAIC_FORCE_ON field.
	ISP_CLK_EN_CLK_DEMOSAIC_FORCE_ON_Msk = 0x20
	// Bit CLK_DEMOSAIC_FORCE_ON.
	ISP_CLK_EN_CLK_DEMOSAIC_FORCE_ON = 0x20
	// Position of CLK_MEDIAN_FORCE_ON field.
	ISP_CLK_EN_CLK_MEDIAN_FORCE_ON_Pos = 0x6
	// Bit mask of CLK_MEDIAN_FORCE_ON field.
	ISP_CLK_EN_CLK_MEDIAN_FORCE_ON_Msk = 0x40
	// Bit CLK_MEDIAN_FORCE_ON.
	ISP_CLK_EN_CLK_MEDIAN_FORCE_ON = 0x40
	// Position of CLK_CCM_FORCE_ON field.
	ISP_CLK_EN_CLK_CCM_FORCE_ON_Pos = 0x7
	// Bit mask of CLK_CCM_FORCE_ON field.
	ISP_CLK_EN_CLK_CCM_FORCE_ON_Msk = 0x80
	// Bit CLK_CCM_FORCE_ON.
	ISP_CLK_EN_CLK_CCM_FORCE_ON = 0x80
	// Position of CLK_GAMMA_FORCE_ON field.
	ISP_CLK_EN_CLK_GAMMA_FORCE_ON_Pos = 0x8
	// Bit mask of CLK_GAMMA_FORCE_ON field.
	ISP_CLK_EN_CLK_GAMMA_FORCE_ON_Msk = 0x100
	// Bit CLK_GAMMA_FORCE_ON.
	ISP_CLK_EN_CLK_GAMMA_FORCE_ON = 0x100
	// Position of CLK_RGB2YUV_FORCE_ON field.
	ISP_CLK_EN_CLK_RGB2YUV_FORCE_ON_Pos = 0x9
	// Bit mask of CLK_RGB2YUV_FORCE_ON field.
	ISP_CLK_EN_CLK_RGB2YUV_FORCE_ON_Msk = 0x200
	// Bit CLK_RGB2YUV_FORCE_ON.
	ISP_CLK_EN_CLK_RGB2YUV_FORCE_ON = 0x200
	// Position of CLK_SHARP_FORCE_ON field.
	ISP_CLK_EN_CLK_SHARP_FORCE_ON_Pos = 0xa
	// Bit mask of CLK_SHARP_FORCE_ON field.
	ISP_CLK_EN_CLK_SHARP_FORCE_ON_Msk = 0x400
	// Bit CLK_SHARP_FORCE_ON.
	ISP_CLK_EN_CLK_SHARP_FORCE_ON = 0x400
	// Position of CLK_COLOR_FORCE_ON field.
	ISP_CLK_EN_CLK_COLOR_FORCE_ON_Pos = 0xb
	// Bit mask of CLK_COLOR_FORCE_ON field.
	ISP_CLK_EN_CLK_COLOR_FORCE_ON_Msk = 0x800
	// Bit CLK_COLOR_FORCE_ON.
	ISP_CLK_EN_CLK_COLOR_FORCE_ON = 0x800
	// Position of CLK_YUV2RGB_FORCE_ON field.
	ISP_CLK_EN_CLK_YUV2RGB_FORCE_ON_Pos = 0xc
	// Bit mask of CLK_YUV2RGB_FORCE_ON field.
	ISP_CLK_EN_CLK_YUV2RGB_FORCE_ON_Msk = 0x1000
	// Bit CLK_YUV2RGB_FORCE_ON.
	ISP_CLK_EN_CLK_YUV2RGB_FORCE_ON = 0x1000
	// Position of CLK_AE_FORCE_ON field.
	ISP_CLK_EN_CLK_AE_FORCE_ON_Pos = 0xd
	// Bit mask of CLK_AE_FORCE_ON field.
	ISP_CLK_EN_CLK_AE_FORCE_ON_Msk = 0x2000
	// Bit CLK_AE_FORCE_ON.
	ISP_CLK_EN_CLK_AE_FORCE_ON = 0x2000
	// Position of CLK_AF_FORCE_ON field.
	ISP_CLK_EN_CLK_AF_FORCE_ON_Pos = 0xe
	// Bit mask of CLK_AF_FORCE_ON field.
	ISP_CLK_EN_CLK_AF_FORCE_ON_Msk = 0x4000
	// Bit CLK_AF_FORCE_ON.
	ISP_CLK_EN_CLK_AF_FORCE_ON = 0x4000
	// Position of CLK_AWB_FORCE_ON field.
	ISP_CLK_EN_CLK_AWB_FORCE_ON_Pos = 0xf
	// Bit mask of CLK_AWB_FORCE_ON field.
	ISP_CLK_EN_CLK_AWB_FORCE_ON_Msk = 0x8000
	// Bit CLK_AWB_FORCE_ON.
	ISP_CLK_EN_CLK_AWB_FORCE_ON = 0x8000
	// Position of CLK_HIST_FORCE_ON field.
	ISP_CLK_EN_CLK_HIST_FORCE_ON_Pos = 0x10
	// Bit mask of CLK_HIST_FORCE_ON field.
	ISP_CLK_EN_CLK_HIST_FORCE_ON_Msk = 0x10000
	// Bit CLK_HIST_FORCE_ON.
	ISP_CLK_EN_CLK_HIST_FORCE_ON = 0x10000
	// Position of CLK_MIPI_IDI_FORCE_ON field.
	ISP_CLK_EN_CLK_MIPI_IDI_FORCE_ON_Pos = 0x11
	// Bit mask of CLK_MIPI_IDI_FORCE_ON field.
	ISP_CLK_EN_CLK_MIPI_IDI_FORCE_ON_Msk = 0x20000
	// Bit CLK_MIPI_IDI_FORCE_ON.
	ISP_CLK_EN_CLK_MIPI_IDI_FORCE_ON = 0x20000
	// Position of ISP_MEM_CLK_FORCE_ON field.
	ISP_CLK_EN_ISP_MEM_CLK_FORCE_ON_Pos = 0x12
	// Bit mask of ISP_MEM_CLK_FORCE_ON field.
	ISP_CLK_EN_ISP_MEM_CLK_FORCE_ON_Msk = 0x40000
	// Bit ISP_MEM_CLK_FORCE_ON.
	ISP_CLK_EN_ISP_MEM_CLK_FORCE_ON = 0x40000

	// CNTL: isp module enable control register
	// Position of MIPI_DATA_EN field.
	ISP_CNTL_MIPI_DATA_EN_Pos = 0x0
	// Bit mask of MIPI_DATA_EN field.
	ISP_CNTL_MIPI_DATA_EN_Msk = 0x1
	// Bit MIPI_DATA_EN.
	ISP_CNTL_MIPI_DATA_EN = 0x1
	// Position of ISP_EN field.
	ISP_CNTL_ISP_EN_Pos = 0x1
	// Bit mask of ISP_EN field.
	ISP_CNTL_ISP_EN_Msk = 0x2
	// Bit ISP_EN.
	ISP_CNTL_ISP_EN = 0x2
	// Position of BLC_EN field.
	ISP_CNTL_BLC_EN_Pos = 0x2
	// Bit mask of BLC_EN field.
	ISP_CNTL_BLC_EN_Msk = 0x4
	// Bit BLC_EN.
	ISP_CNTL_BLC_EN = 0x4
	// Position of DPC_EN field.
	ISP_CNTL_DPC_EN_Pos = 0x3
	// Bit mask of DPC_EN field.
	ISP_CNTL_DPC_EN_Msk = 0x8
	// Bit DPC_EN.
	ISP_CNTL_DPC_EN = 0x8
	// Position of BF_EN field.
	ISP_CNTL_BF_EN_Pos = 0x4
	// Bit mask of BF_EN field.
	ISP_CNTL_BF_EN_Msk = 0x10
	// Bit BF_EN.
	ISP_CNTL_BF_EN = 0x10
	// Position of LSC_EN field.
	ISP_CNTL_LSC_EN_Pos = 0x5
	// Bit mask of LSC_EN field.
	ISP_CNTL_LSC_EN_Msk = 0x20
	// Bit LSC_EN.
	ISP_CNTL_LSC_EN = 0x20
	// Position of DEMOSAIC_EN field.
	ISP_CNTL_DEMOSAIC_EN_Pos = 0x6
	// Bit mask of DEMOSAIC_EN field.
	ISP_CNTL_DEMOSAIC_EN_Msk = 0x40
	// Bit DEMOSAIC_EN.
	ISP_CNTL_DEMOSAIC_EN = 0x40
	// Position of MEDIAN_EN field.
	ISP_CNTL_MEDIAN_EN_Pos = 0x7
	// Bit mask of MEDIAN_EN field.
	ISP_CNTL_MEDIAN_EN_Msk = 0x80
	// Bit MEDIAN_EN.
	ISP_CNTL_MEDIAN_EN = 0x80
	// Position of CCM_EN field.
	ISP_CNTL_CCM_EN_Pos = 0x8
	// Bit mask of CCM_EN field.
	ISP_CNTL_CCM_EN_Msk = 0x100
	// Bit CCM_EN.
	ISP_CNTL_CCM_EN = 0x100
	// Position of GAMMA_EN field.
	ISP_CNTL_GAMMA_EN_Pos = 0x9
	// Bit mask of GAMMA_EN field.
	ISP_CNTL_GAMMA_EN_Msk = 0x200
	// Bit GAMMA_EN.
	ISP_CNTL_GAMMA_EN = 0x200
	// Position of RGB2YUV_EN field.
	ISP_CNTL_RGB2YUV_EN_Pos = 0xa
	// Bit mask of RGB2YUV_EN field.
	ISP_CNTL_RGB2YUV_EN_Msk = 0x400
	// Bit RGB2YUV_EN.
	ISP_CNTL_RGB2YUV_EN = 0x400
	// Position of SHARP_EN field.
	ISP_CNTL_SHARP_EN_Pos = 0xb
	// Bit mask of SHARP_EN field.
	ISP_CNTL_SHARP_EN_Msk = 0x800
	// Bit SHARP_EN.
	ISP_CNTL_SHARP_EN = 0x800
	// Position of COLOR_EN field.
	ISP_CNTL_COLOR_EN_Pos = 0xc
	// Bit mask of COLOR_EN field.
	ISP_CNTL_COLOR_EN_Msk = 0x1000
	// Bit COLOR_EN.
	ISP_CNTL_COLOR_EN = 0x1000
	// Position of YUV2RGB_EN field.
	ISP_CNTL_YUV2RGB_EN_Pos = 0xd
	// Bit mask of YUV2RGB_EN field.
	ISP_CNTL_YUV2RGB_EN_Msk = 0x2000
	// Bit YUV2RGB_EN.
	ISP_CNTL_YUV2RGB_EN = 0x2000
	// Position of AE_EN field.
	ISP_CNTL_AE_EN_Pos = 0xe
	// Bit mask of AE_EN field.
	ISP_CNTL_AE_EN_Msk = 0x4000
	// Bit AE_EN.
	ISP_CNTL_AE_EN = 0x4000
	// Position of AF_EN field.
	ISP_CNTL_AF_EN_Pos = 0xf
	// Bit mask of AF_EN field.
	ISP_CNTL_AF_EN_Msk = 0x8000
	// Bit AF_EN.
	ISP_CNTL_AF_EN = 0x8000
	// Position of AWB_EN field.
	ISP_CNTL_AWB_EN_Pos = 0x10
	// Bit mask of AWB_EN field.
	ISP_CNTL_AWB_EN_Msk = 0x10000
	// Bit AWB_EN.
	ISP_CNTL_AWB_EN = 0x10000
	// Position of HIST_EN field.
	ISP_CNTL_HIST_EN_Pos = 0x11
	// Bit mask of HIST_EN field.
	ISP_CNTL_HIST_EN_Msk = 0x20000
	// Bit HIST_EN.
	ISP_CNTL_HIST_EN = 0x20000
	// Position of BYTE_ENDIAN_ORDER field.
	ISP_CNTL_BYTE_ENDIAN_ORDER_Pos = 0x18
	// Bit mask of BYTE_ENDIAN_ORDER field.
	ISP_CNTL_BYTE_ENDIAN_ORDER_Msk = 0x1000000
	// Bit BYTE_ENDIAN_ORDER.
	ISP_CNTL_BYTE_ENDIAN_ORDER = 0x1000000
	// Position of ISP_DATA_TYPE field.
	ISP_CNTL_ISP_DATA_TYPE_Pos = 0x19
	// Bit mask of ISP_DATA_TYPE field.
	ISP_CNTL_ISP_DATA_TYPE_Msk = 0x6000000
	// Position of ISP_IN_SRC field.
	ISP_CNTL_ISP_IN_SRC_Pos = 0x1b
	// Bit mask of ISP_IN_SRC field.
	ISP_CNTL_ISP_IN_SRC_Msk = 0x18000000
	// Position of ISP_OUT_TYPE field.
	ISP_CNTL_ISP_OUT_TYPE_Pos = 0x1d
	// Bit mask of ISP_OUT_TYPE field.
	ISP_CNTL_ISP_OUT_TYPE_Msk = 0xe0000000

	// HSYNC_CNT: header hsync interval control register
	// Position of HSYNC_CNT field.
	ISP_HSYNC_CNT_HSYNC_CNT_Pos = 0x0
	// Bit mask of HSYNC_CNT field.
	ISP_HSYNC_CNT_HSYNC_CNT_Msk = 0xff

	// FRAME_CFG: frame control parameter register
	// Position of VADR_NUM field.
	ISP_FRAME_CFG_VADR_NUM_Pos = 0x0
	// Bit mask of VADR_NUM field.
	ISP_FRAME_CFG_VADR_NUM_Msk = 0xfff
	// Position of HADR_NUM field.
	ISP_FRAME_CFG_HADR_NUM_Pos = 0xc
	// Bit mask of HADR_NUM field.
	ISP_FRAME_CFG_HADR_NUM_Msk = 0xfff000
	// Position of BAYER_MODE field.
	ISP_FRAME_CFG_BAYER_MODE_Pos = 0x1b
	// Bit mask of BAYER_MODE field.
	ISP_FRAME_CFG_BAYER_MODE_Msk = 0x18000000
	// Position of HSYNC_START_EXIST field.
	ISP_FRAME_CFG_HSYNC_START_EXIST_Pos = 0x1d
	// Bit mask of HSYNC_START_EXIST field.
	ISP_FRAME_CFG_HSYNC_START_EXIST_Msk = 0x20000000
	// Bit HSYNC_START_EXIST.
	ISP_FRAME_CFG_HSYNC_START_EXIST = 0x20000000
	// Position of HSYNC_END_EXIST field.
	ISP_FRAME_CFG_HSYNC_END_EXIST_Pos = 0x1e
	// Bit mask of HSYNC_END_EXIST field.
	ISP_FRAME_CFG_HSYNC_END_EXIST_Msk = 0x40000000
	// Bit HSYNC_END_EXIST.
	ISP_FRAME_CFG_HSYNC_END_EXIST = 0x40000000

	// CCM_COEF0: ccm coef register 0
	// Position of CCM_RR field.
	ISP_CCM_COEF0_CCM_RR_Pos = 0x0
	// Bit mask of CCM_RR field.
	ISP_CCM_COEF0_CCM_RR_Msk = 0x1fff
	// Position of CCM_RG field.
	ISP_CCM_COEF0_CCM_RG_Pos = 0xd
	// Bit mask of CCM_RG field.
	ISP_CCM_COEF0_CCM_RG_Msk = 0x3ffe000

	// CCM_COEF1: ccm coef register 1
	// Position of CCM_RB field.
	ISP_CCM_COEF1_CCM_RB_Pos = 0x0
	// Bit mask of CCM_RB field.
	ISP_CCM_COEF1_CCM_RB_Msk = 0x1fff
	// Position of CCM_GR field.
	ISP_CCM_COEF1_CCM_GR_Pos = 0xd
	// Bit mask of CCM_GR field.
	ISP_CCM_COEF1_CCM_GR_Msk = 0x3ffe000

	// CCM_COEF3: ccm coef register 3
	// Position of CCM_GG field.
	ISP_CCM_COEF3_CCM_GG_Pos = 0x0
	// Bit mask of CCM_GG field.
	ISP_CCM_COEF3_CCM_GG_Msk = 0x1fff
	// Position of CCM_GB field.
	ISP_CCM_COEF3_CCM_GB_Pos = 0xd
	// Bit mask of CCM_GB field.
	ISP_CCM_COEF3_CCM_GB_Msk = 0x3ffe000

	// CCM_COEF4: ccm coef register 4
	// Position of CCM_BR field.
	ISP_CCM_COEF4_CCM_BR_Pos = 0x0
	// Bit mask of CCM_BR field.
	ISP_CCM_COEF4_CCM_BR_Msk = 0x1fff
	// Position of CCM_BG field.
	ISP_CCM_COEF4_CCM_BG_Pos = 0xd
	// Bit mask of CCM_BG field.
	ISP_CCM_COEF4_CCM_BG_Msk = 0x3ffe000

	// CCM_COEF5: ccm coef register 5
	// Position of CCM_BB field.
	ISP_CCM_COEF5_CCM_BB_Pos = 0x0
	// Bit mask of CCM_BB field.
	ISP_CCM_COEF5_CCM_BB_Msk = 0x1fff

	// BF_MATRIX_CTRL: bf pix2matrix ctrl
	// Position of BF_TAIL_PIXEN_PULSE_TL field.
	ISP_BF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TL_Pos = 0x0
	// Bit mask of BF_TAIL_PIXEN_PULSE_TL field.
	ISP_BF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TL_Msk = 0xff
	// Position of BF_TAIL_PIXEN_PULSE_TH field.
	ISP_BF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TH_Pos = 0x8
	// Bit mask of BF_TAIL_PIXEN_PULSE_TH field.
	ISP_BF_MATRIX_CTRL_BF_TAIL_PIXEN_PULSE_TH_Msk = 0xff00
	// Position of BF_PADDING_DATA field.
	ISP_BF_MATRIX_CTRL_BF_PADDING_DATA_Pos = 0x10
	// Bit mask of BF_PADDING_DATA field.
	ISP_BF_MATRIX_CTRL_BF_PADDING_DATA_Msk = 0xff0000
	// Position of BF_PADDING_MODE field.
	ISP_BF_MATRIX_CTRL_BF_PADDING_MODE_Pos = 0x18
	// Bit mask of BF_PADDING_MODE field.
	ISP_BF_MATRIX_CTRL_BF_PADDING_MODE_Msk = 0x1000000
	// Bit BF_PADDING_MODE.
	ISP_BF_MATRIX_CTRL_BF_PADDING_MODE = 0x1000000

	// BF_SIGMA: bf denoising level control register
	// Position of SIGMA field.
	ISP_BF_SIGMA_SIGMA_Pos = 0x0
	// Bit mask of SIGMA field.
	ISP_BF_SIGMA_SIGMA_Msk = 0x3f

	// BF_GAU0: bf gau template register 0
	// Position of GAU_TEMPLATE21 field.
	ISP_BF_GAU0_GAU_TEMPLATE21_Pos = 0x0
	// Bit mask of GAU_TEMPLATE21 field.
	ISP_BF_GAU0_GAU_TEMPLATE21_Msk = 0xf
	// Position of GAU_TEMPLATE20 field.
	ISP_BF_GAU0_GAU_TEMPLATE20_Pos = 0x4
	// Bit mask of GAU_TEMPLATE20 field.
	ISP_BF_GAU0_GAU_TEMPLATE20_Msk = 0xf0
	// Position of GAU_TEMPLATE12 field.
	ISP_BF_GAU0_GAU_TEMPLATE12_Pos = 0x8
	// Bit mask of GAU_TEMPLATE12 field.
	ISP_BF_GAU0_GAU_TEMPLATE12_Msk = 0xf00
	// Position of GAU_TEMPLATE11 field.
	ISP_BF_GAU0_GAU_TEMPLATE11_Pos = 0xc
	// Bit mask of GAU_TEMPLATE11 field.
	ISP_BF_GAU0_GAU_TEMPLATE11_Msk = 0xf000
	// Position of GAU_TEMPLATE10 field.
	ISP_BF_GAU0_GAU_TEMPLATE10_Pos = 0x10
	// Bit mask of GAU_TEMPLATE10 field.
	ISP_BF_GAU0_GAU_TEMPLATE10_Msk = 0xf0000
	// Position of GAU_TEMPLATE02 field.
	ISP_BF_GAU0_GAU_TEMPLATE02_Pos = 0x14
	// Bit mask of GAU_TEMPLATE02 field.
	ISP_BF_GAU0_GAU_TEMPLATE02_Msk = 0xf00000
	// Position of GAU_TEMPLATE01 field.
	ISP_BF_GAU0_GAU_TEMPLATE01_Pos = 0x18
	// Bit mask of GAU_TEMPLATE01 field.
	ISP_BF_GAU0_GAU_TEMPLATE01_Msk = 0xf000000
	// Position of GAU_TEMPLATE00 field.
	ISP_BF_GAU0_GAU_TEMPLATE00_Pos = 0x1c
	// Bit mask of GAU_TEMPLATE00 field.
	ISP_BF_GAU0_GAU_TEMPLATE00_Msk = 0xf0000000

	// BF_GAU1: bf gau template register 1
	// Position of GAU_TEMPLATE22 field.
	ISP_BF_GAU1_GAU_TEMPLATE22_Pos = 0x0
	// Bit mask of GAU_TEMPLATE22 field.
	ISP_BF_GAU1_GAU_TEMPLATE22_Msk = 0xf

	// DPC_CTRL: DPC mode control register
	// Position of DPC_CHECK_EN field.
	ISP_DPC_CTRL_DPC_CHECK_EN_Pos = 0x0
	// Bit mask of DPC_CHECK_EN field.
	ISP_DPC_CTRL_DPC_CHECK_EN_Msk = 0x1
	// Bit DPC_CHECK_EN.
	ISP_DPC_CTRL_DPC_CHECK_EN = 0x1
	// Position of STA_EN field.
	ISP_DPC_CTRL_STA_EN_Pos = 0x1
	// Bit mask of STA_EN field.
	ISP_DPC_CTRL_STA_EN_Msk = 0x2
	// Bit STA_EN.
	ISP_DPC_CTRL_STA_EN = 0x2
	// Position of DYN_EN field.
	ISP_DPC_CTRL_DYN_EN_Pos = 0x2
	// Bit mask of DYN_EN field.
	ISP_DPC_CTRL_DYN_EN_Msk = 0x4
	// Bit DYN_EN.
	ISP_DPC_CTRL_DYN_EN = 0x4
	// Position of DPC_BLACK_EN field.
	ISP_DPC_CTRL_DPC_BLACK_EN_Pos = 0x3
	// Bit mask of DPC_BLACK_EN field.
	ISP_DPC_CTRL_DPC_BLACK_EN_Msk = 0x8
	// Bit DPC_BLACK_EN.
	ISP_DPC_CTRL_DPC_BLACK_EN = 0x8
	// Position of DPC_METHOD_SEL field.
	ISP_DPC_CTRL_DPC_METHOD_SEL_Pos = 0x4
	// Bit mask of DPC_METHOD_SEL field.
	ISP_DPC_CTRL_DPC_METHOD_SEL_Msk = 0x10
	// Bit DPC_METHOD_SEL.
	ISP_DPC_CTRL_DPC_METHOD_SEL = 0x10
	// Position of DPC_CHECK_OD_EN field.
	ISP_DPC_CTRL_DPC_CHECK_OD_EN_Pos = 0x5
	// Bit mask of DPC_CHECK_OD_EN field.
	ISP_DPC_CTRL_DPC_CHECK_OD_EN_Msk = 0x20
	// Bit DPC_CHECK_OD_EN.
	ISP_DPC_CTRL_DPC_CHECK_OD_EN = 0x20

	// DPC_CONF: DPC parameter config register
	// Position of DPC_THRESHOLD_L field.
	ISP_DPC_CONF_DPC_THRESHOLD_L_Pos = 0x0
	// Bit mask of DPC_THRESHOLD_L field.
	ISP_DPC_CONF_DPC_THRESHOLD_L_Msk = 0xff
	// Position of DPC_THRESHOLD_H field.
	ISP_DPC_CONF_DPC_THRESHOLD_H_Pos = 0x8
	// Bit mask of DPC_THRESHOLD_H field.
	ISP_DPC_CONF_DPC_THRESHOLD_H_Msk = 0xff00
	// Position of DPC_FACTOR_DARK field.
	ISP_DPC_CONF_DPC_FACTOR_DARK_Pos = 0x10
	// Bit mask of DPC_FACTOR_DARK field.
	ISP_DPC_CONF_DPC_FACTOR_DARK_Msk = 0x3f0000
	// Position of DPC_FACTOR_BRIG field.
	ISP_DPC_CONF_DPC_FACTOR_BRIG_Pos = 0x16
	// Bit mask of DPC_FACTOR_BRIG field.
	ISP_DPC_CONF_DPC_FACTOR_BRIG_Msk = 0xfc00000

	// DPC_MATRIX_CTRL: dpc pix2matrix ctrl
	// Position of DPC_TAIL_PIXEN_PULSE_TL field.
	ISP_DPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TL_Pos = 0x0
	// Bit mask of DPC_TAIL_PIXEN_PULSE_TL field.
	ISP_DPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TL_Msk = 0xff
	// Position of DPC_TAIL_PIXEN_PULSE_TH field.
	ISP_DPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TH_Pos = 0x8
	// Bit mask of DPC_TAIL_PIXEN_PULSE_TH field.
	ISP_DPC_MATRIX_CTRL_DPC_TAIL_PIXEN_PULSE_TH_Msk = 0xff00
	// Position of DPC_PADDING_DATA field.
	ISP_DPC_MATRIX_CTRL_DPC_PADDING_DATA_Pos = 0x10
	// Bit mask of DPC_PADDING_DATA field.
	ISP_DPC_MATRIX_CTRL_DPC_PADDING_DATA_Msk = 0xff0000
	// Position of DPC_PADDING_MODE field.
	ISP_DPC_MATRIX_CTRL_DPC_PADDING_MODE_Pos = 0x18
	// Bit mask of DPC_PADDING_MODE field.
	ISP_DPC_MATRIX_CTRL_DPC_PADDING_MODE_Msk = 0x1000000
	// Bit DPC_PADDING_MODE.
	ISP_DPC_MATRIX_CTRL_DPC_PADDING_MODE = 0x1000000

	// DPC_DEADPIX_CNT: DPC dead-pix number register
	// Position of DPC_DEADPIX_CNT field.
	ISP_DPC_DEADPIX_CNT_DPC_DEADPIX_CNT_Pos = 0x0
	// Bit mask of DPC_DEADPIX_CNT field.
	ISP_DPC_DEADPIX_CNT_DPC_DEADPIX_CNT_Msk = 0x3ff

	// LUT_CMD: LUT command register
	// Position of LUT_ADDR field.
	ISP_LUT_CMD_LUT_ADDR_Pos = 0x0
	// Bit mask of LUT_ADDR field.
	ISP_LUT_CMD_LUT_ADDR_Msk = 0xfff
	// Position of LUT_NUM field.
	ISP_LUT_CMD_LUT_NUM_Pos = 0xc
	// Bit mask of LUT_NUM field.
	ISP_LUT_CMD_LUT_NUM_Msk = 0xf000
	// Position of LUT_CMD field.
	ISP_LUT_CMD_LUT_CMD_Pos = 0x10
	// Bit mask of LUT_CMD field.
	ISP_LUT_CMD_LUT_CMD_Msk = 0x10000
	// Bit LUT_CMD.
	ISP_LUT_CMD_LUT_CMD = 0x10000

	// LUT_WDATA: LUT write data register
	// Position of LUT_WDATA field.
	ISP_LUT_WDATA_LUT_WDATA_Pos = 0x0
	// Bit mask of LUT_WDATA field.
	ISP_LUT_WDATA_LUT_WDATA_Msk = 0xffffffff

	// LUT_RDATA: LUT read data register
	// Position of LUT_RDATA field.
	ISP_LUT_RDATA_LUT_RDATA_Pos = 0x0
	// Bit mask of LUT_RDATA field.
	ISP_LUT_RDATA_LUT_RDATA_Msk = 0xffffffff

	// LSC_TABLESIZE: LSC point in x-direction
	// Position of LSC_XTABLESIZE field.
	ISP_LSC_TABLESIZE_LSC_XTABLESIZE_Pos = 0x0
	// Bit mask of LSC_XTABLESIZE field.
	ISP_LSC_TABLESIZE_LSC_XTABLESIZE_Msk = 0x1f

	// DEMOSAIC_MATRIX_CTRL: demosaic pix2matrix ctrl
	// Position of DEMOSAIC_TAIL_PIXEN_PULSE_TL field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TL_Pos = 0x0
	// Bit mask of DEMOSAIC_TAIL_PIXEN_PULSE_TL field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TL_Msk = 0xff
	// Position of DEMOSAIC_TAIL_PIXEN_PULSE_TH field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TH_Pos = 0x8
	// Bit mask of DEMOSAIC_TAIL_PIXEN_PULSE_TH field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_TAIL_PIXEN_PULSE_TH_Msk = 0xff00
	// Position of DEMOSAIC_PADDING_DATA field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_DATA_Pos = 0x10
	// Bit mask of DEMOSAIC_PADDING_DATA field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_DATA_Msk = 0xff0000
	// Position of DEMOSAIC_PADDING_MODE field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_MODE_Pos = 0x18
	// Bit mask of DEMOSAIC_PADDING_MODE field.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_MODE_Msk = 0x1000000
	// Bit DEMOSAIC_PADDING_MODE.
	ISP_DEMOSAIC_MATRIX_CTRL_DEMOSAIC_PADDING_MODE = 0x1000000

	// DEMOSAIC_GRAD_RATIO: demosaic gradient select ratio
	// Position of DEMOSAIC_GRAD_RATIO field.
	ISP_DEMOSAIC_GRAD_RATIO_DEMOSAIC_GRAD_RATIO_Pos = 0x0
	// Bit mask of DEMOSAIC_GRAD_RATIO field.
	ISP_DEMOSAIC_GRAD_RATIO_DEMOSAIC_GRAD_RATIO_Msk = 0x3f

	// MEDIAN_MATRIX_CTRL: median pix2matrix ctrl
	// Position of MEDIAN_PADDING_DATA field.
	ISP_MEDIAN_MATRIX_CTRL_MEDIAN_PADDING_DATA_Pos = 0x0
	// Bit mask of MEDIAN_PADDING_DATA field.
	ISP_MEDIAN_MATRIX_CTRL_MEDIAN_PADDING_DATA_Msk = 0xff
	// Position of MEDIAN_PADDING_MODE field.
	ISP_MEDIAN_MATRIX_CTRL_MEDIAN_PADDING_MODE_Pos = 0x8
	// Bit mask of MEDIAN_PADDING_MODE field.
	ISP_MEDIAN_MATRIX_CTRL_MEDIAN_PADDING_MODE_Msk = 0x100
	// Bit MEDIAN_PADDING_MODE.
	ISP_MEDIAN_MATRIX_CTRL_MEDIAN_PADDING_MODE = 0x100

	// INT_RAW: raw interrupt register
	// Position of ISP_DATA_TYPE_ERR_INT_RAW field.
	ISP_INT_RAW_ISP_DATA_TYPE_ERR_INT_RAW_Pos = 0x0
	// Bit mask of ISP_DATA_TYPE_ERR_INT_RAW field.
	ISP_INT_RAW_ISP_DATA_TYPE_ERR_INT_RAW_Msk = 0x1
	// Bit ISP_DATA_TYPE_ERR_INT_RAW.
	ISP_INT_RAW_ISP_DATA_TYPE_ERR_INT_RAW = 0x1
	// Position of ISP_ASYNC_FIFO_OVF_INT_RAW field.
	ISP_INT_RAW_ISP_ASYNC_FIFO_OVF_INT_RAW_Pos = 0x1
	// Bit mask of ISP_ASYNC_FIFO_OVF_INT_RAW field.
	ISP_INT_RAW_ISP_ASYNC_FIFO_OVF_INT_RAW_Msk = 0x2
	// Bit ISP_ASYNC_FIFO_OVF_INT_RAW.
	ISP_INT_RAW_ISP_ASYNC_FIFO_OVF_INT_RAW = 0x2
	// Position of ISP_BUF_FULL_INT_RAW field.
	ISP_INT_RAW_ISP_BUF_FULL_INT_RAW_Pos = 0x2
	// Bit mask of ISP_BUF_FULL_INT_RAW field.
	ISP_INT_RAW_ISP_BUF_FULL_INT_RAW_Msk = 0x4
	// Bit ISP_BUF_FULL_INT_RAW.
	ISP_INT_RAW_ISP_BUF_FULL_INT_RAW = 0x4
	// Position of ISP_HVNUM_SETTING_ERR_INT_RAW field.
	ISP_INT_RAW_ISP_HVNUM_SETTING_ERR_INT_RAW_Pos = 0x3
	// Bit mask of ISP_HVNUM_SETTING_ERR_INT_RAW field.
	ISP_INT_RAW_ISP_HVNUM_SETTING_ERR_INT_RAW_Msk = 0x8
	// Bit ISP_HVNUM_SETTING_ERR_INT_RAW.
	ISP_INT_RAW_ISP_HVNUM_SETTING_ERR_INT_RAW = 0x8
	// Position of ISP_DATA_TYPE_SETTING_ERR_INT_RAW field.
	ISP_INT_RAW_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_Pos = 0x4
	// Bit mask of ISP_DATA_TYPE_SETTING_ERR_INT_RAW field.
	ISP_INT_RAW_ISP_DATA_TYPE_SETTING_ERR_INT_RAW_Msk = 0x10
	// Bit ISP_DATA_TYPE_SETTING_ERR_INT_RAW.
	ISP_INT_RAW_ISP_DATA_TYPE_SETTING_ERR_INT_RAW = 0x10
	// Position of ISP_MIPI_HNUM_UNMATCH_INT_RAW field.
	ISP_INT_RAW_ISP_MIPI_HNUM_UNMATCH_INT_RAW_Pos = 0x5
	// Bit mask of ISP_MIPI_HNUM_UNMATCH_INT_RAW field.
	ISP_INT_RAW_ISP_MIPI_HNUM_UNMATCH_INT_RAW_Msk = 0x20
	// Bit ISP_MIPI_HNUM_UNMATCH_INT_RAW.
	ISP_INT_RAW_ISP_MIPI_HNUM_UNMATCH_INT_RAW = 0x20
	// Position of DPC_CHECK_DONE_INT_RAW field.
	ISP_INT_RAW_DPC_CHECK_DONE_INT_RAW_Pos = 0x6
	// Bit mask of DPC_CHECK_DONE_INT_RAW field.
	ISP_INT_RAW_DPC_CHECK_DONE_INT_RAW_Msk = 0x40
	// Bit DPC_CHECK_DONE_INT_RAW.
	ISP_INT_RAW_DPC_CHECK_DONE_INT_RAW = 0x40
	// Position of GAMMA_XCOORD_ERR_INT_RAW field.
	ISP_INT_RAW_GAMMA_XCOORD_ERR_INT_RAW_Pos = 0x7
	// Bit mask of GAMMA_XCOORD_ERR_INT_RAW field.
	ISP_INT_RAW_GAMMA_XCOORD_ERR_INT_RAW_Msk = 0x80
	// Bit GAMMA_XCOORD_ERR_INT_RAW.
	ISP_INT_RAW_GAMMA_XCOORD_ERR_INT_RAW = 0x80
	// Position of AE_MONITOR_INT_RAW field.
	ISP_INT_RAW_AE_MONITOR_INT_RAW_Pos = 0x8
	// Bit mask of AE_MONITOR_INT_RAW field.
	ISP_INT_RAW_AE_MONITOR_INT_RAW_Msk = 0x100
	// Bit AE_MONITOR_INT_RAW.
	ISP_INT_RAW_AE_MONITOR_INT_RAW = 0x100
	// Position of AE_FRAME_DONE_INT_RAW field.
	ISP_INT_RAW_AE_FRAME_DONE_INT_RAW_Pos = 0x9
	// Bit mask of AE_FRAME_DONE_INT_RAW field.
	ISP_INT_RAW_AE_FRAME_DONE_INT_RAW_Msk = 0x200
	// Bit AE_FRAME_DONE_INT_RAW.
	ISP_INT_RAW_AE_FRAME_DONE_INT_RAW = 0x200
	// Position of AF_FDONE_INT_RAW field.
	ISP_INT_RAW_AF_FDONE_INT_RAW_Pos = 0xa
	// Bit mask of AF_FDONE_INT_RAW field.
	ISP_INT_RAW_AF_FDONE_INT_RAW_Msk = 0x400
	// Bit AF_FDONE_INT_RAW.
	ISP_INT_RAW_AF_FDONE_INT_RAW = 0x400
	// Position of AF_ENV_INT_RAW field.
	ISP_INT_RAW_AF_ENV_INT_RAW_Pos = 0xb
	// Bit mask of AF_ENV_INT_RAW field.
	ISP_INT_RAW_AF_ENV_INT_RAW_Msk = 0x800
	// Bit AF_ENV_INT_RAW.
	ISP_INT_RAW_AF_ENV_INT_RAW = 0x800
	// Position of AWB_FDONE_INT_RAW field.
	ISP_INT_RAW_AWB_FDONE_INT_RAW_Pos = 0xc
	// Bit mask of AWB_FDONE_INT_RAW field.
	ISP_INT_RAW_AWB_FDONE_INT_RAW_Msk = 0x1000
	// Bit AWB_FDONE_INT_RAW.
	ISP_INT_RAW_AWB_FDONE_INT_RAW = 0x1000
	// Position of HIST_FDONE_INT_RAW field.
	ISP_INT_RAW_HIST_FDONE_INT_RAW_Pos = 0xd
	// Bit mask of HIST_FDONE_INT_RAW field.
	ISP_INT_RAW_HIST_FDONE_INT_RAW_Msk = 0x2000
	// Bit HIST_FDONE_INT_RAW.
	ISP_INT_RAW_HIST_FDONE_INT_RAW = 0x2000
	// Position of FRAME_INT_RAW field.
	ISP_INT_RAW_FRAME_INT_RAW_Pos = 0xe
	// Bit mask of FRAME_INT_RAW field.
	ISP_INT_RAW_FRAME_INT_RAW_Msk = 0x4000
	// Bit FRAME_INT_RAW.
	ISP_INT_RAW_FRAME_INT_RAW = 0x4000
	// Position of BLC_FRAME_INT_RAW field.
	ISP_INT_RAW_BLC_FRAME_INT_RAW_Pos = 0xf
	// Bit mask of BLC_FRAME_INT_RAW field.
	ISP_INT_RAW_BLC_FRAME_INT_RAW_Msk = 0x8000
	// Bit BLC_FRAME_INT_RAW.
	ISP_INT_RAW_BLC_FRAME_INT_RAW = 0x8000
	// Position of LSC_FRAME_INT_RAW field.
	ISP_INT_RAW_LSC_FRAME_INT_RAW_Pos = 0x10
	// Bit mask of LSC_FRAME_INT_RAW field.
	ISP_INT_RAW_LSC_FRAME_INT_RAW_Msk = 0x10000
	// Bit LSC_FRAME_INT_RAW.
	ISP_INT_RAW_LSC_FRAME_INT_RAW = 0x10000
	// Position of DPC_FRAME_INT_RAW field.
	ISP_INT_RAW_DPC_FRAME_INT_RAW_Pos = 0x11
	// Bit mask of DPC_FRAME_INT_RAW field.
	ISP_INT_RAW_DPC_FRAME_INT_RAW_Msk = 0x20000
	// Bit DPC_FRAME_INT_RAW.
	ISP_INT_RAW_DPC_FRAME_INT_RAW = 0x20000
	// Position of BF_FRAME_INT_RAW field.
	ISP_INT_RAW_BF_FRAME_INT_RAW_Pos = 0x12
	// Bit mask of BF_FRAME_INT_RAW field.
	ISP_INT_RAW_BF_FRAME_INT_RAW_Msk = 0x40000
	// Bit BF_FRAME_INT_RAW.
	ISP_INT_RAW_BF_FRAME_INT_RAW = 0x40000
	// Position of DEMOSAIC_FRAME_INT_RAW field.
	ISP_INT_RAW_DEMOSAIC_FRAME_INT_RAW_Pos = 0x13
	// Bit mask of DEMOSAIC_FRAME_INT_RAW field.
	ISP_INT_RAW_DEMOSAIC_FRAME_INT_RAW_Msk = 0x80000
	// Bit DEMOSAIC_FRAME_INT_RAW.
	ISP_INT_RAW_DEMOSAIC_FRAME_INT_RAW = 0x80000
	// Position of MEDIAN_FRAME_INT_RAW field.
	ISP_INT_RAW_MEDIAN_FRAME_INT_RAW_Pos = 0x14
	// Bit mask of MEDIAN_FRAME_INT_RAW field.
	ISP_INT_RAW_MEDIAN_FRAME_INT_RAW_Msk = 0x100000
	// Bit MEDIAN_FRAME_INT_RAW.
	ISP_INT_RAW_MEDIAN_FRAME_INT_RAW = 0x100000
	// Position of CCM_FRAME_INT_RAW field.
	ISP_INT_RAW_CCM_FRAME_INT_RAW_Pos = 0x15
	// Bit mask of CCM_FRAME_INT_RAW field.
	ISP_INT_RAW_CCM_FRAME_INT_RAW_Msk = 0x200000
	// Bit CCM_FRAME_INT_RAW.
	ISP_INT_RAW_CCM_FRAME_INT_RAW = 0x200000
	// Position of GAMMA_FRAME_INT_RAW field.
	ISP_INT_RAW_GAMMA_FRAME_INT_RAW_Pos = 0x16
	// Bit mask of GAMMA_FRAME_INT_RAW field.
	ISP_INT_RAW_GAMMA_FRAME_INT_RAW_Msk = 0x400000
	// Bit GAMMA_FRAME_INT_RAW.
	ISP_INT_RAW_GAMMA_FRAME_INT_RAW = 0x400000
	// Position of RGB2YUV_FRAME_INT_RAW field.
	ISP_INT_RAW_RGB2YUV_FRAME_INT_RAW_Pos = 0x17
	// Bit mask of RGB2YUV_FRAME_INT_RAW field.
	ISP_INT_RAW_RGB2YUV_FRAME_INT_RAW_Msk = 0x800000
	// Bit RGB2YUV_FRAME_INT_RAW.
	ISP_INT_RAW_RGB2YUV_FRAME_INT_RAW = 0x800000
	// Position of SHARP_FRAME_INT_RAW field.
	ISP_INT_RAW_SHARP_FRAME_INT_RAW_Pos = 0x18
	// Bit mask of SHARP_FRAME_INT_RAW field.
	ISP_INT_RAW_SHARP_FRAME_INT_RAW_Msk = 0x1000000
	// Bit SHARP_FRAME_INT_RAW.
	ISP_INT_RAW_SHARP_FRAME_INT_RAW = 0x1000000
	// Position of COLOR_FRAME_INT_RAW field.
	ISP_INT_RAW_COLOR_FRAME_INT_RAW_Pos = 0x19
	// Bit mask of COLOR_FRAME_INT_RAW field.
	ISP_INT_RAW_COLOR_FRAME_INT_RAW_Msk = 0x2000000
	// Bit COLOR_FRAME_INT_RAW.
	ISP_INT_RAW_COLOR_FRAME_INT_RAW = 0x2000000
	// Position of YUV2RGB_FRAME_INT_RAW field.
	ISP_INT_RAW_YUV2RGB_FRAME_INT_RAW_Pos = 0x1a
	// Bit mask of YUV2RGB_FRAME_INT_RAW field.
	ISP_INT_RAW_YUV2RGB_FRAME_INT_RAW_Msk = 0x4000000
	// Bit YUV2RGB_FRAME_INT_RAW.
	ISP_INT_RAW_YUV2RGB_FRAME_INT_RAW = 0x4000000
	// Position of TAIL_IDI_FRAME_INT_RAW field.
	ISP_INT_RAW_TAIL_IDI_FRAME_INT_RAW_Pos = 0x1b
	// Bit mask of TAIL_IDI_FRAME_INT_RAW field.
	ISP_INT_RAW_TAIL_IDI_FRAME_INT_RAW_Msk = 0x8000000
	// Bit TAIL_IDI_FRAME_INT_RAW.
	ISP_INT_RAW_TAIL_IDI_FRAME_INT_RAW = 0x8000000
	// Position of HEADER_IDI_FRAME_INT_RAW field.
	ISP_INT_RAW_HEADER_IDI_FRAME_INT_RAW_Pos = 0x1c
	// Bit mask of HEADER_IDI_FRAME_INT_RAW field.
	ISP_INT_RAW_HEADER_IDI_FRAME_INT_RAW_Msk = 0x10000000
	// Bit HEADER_IDI_FRAME_INT_RAW.
	ISP_INT_RAW_HEADER_IDI_FRAME_INT_RAW = 0x10000000

	// INT_ST: masked interrupt register
	// Position of ISP_DATA_TYPE_ERR_INT_ST field.
	ISP_INT_ST_ISP_DATA_TYPE_ERR_INT_ST_Pos = 0x0
	// Bit mask of ISP_DATA_TYPE_ERR_INT_ST field.
	ISP_INT_ST_ISP_DATA_TYPE_ERR_INT_ST_Msk = 0x1
	// Bit ISP_DATA_TYPE_ERR_INT_ST.
	ISP_INT_ST_ISP_DATA_TYPE_ERR_INT_ST = 0x1
	// Position of ISP_ASYNC_FIFO_OVF_INT_ST field.
	ISP_INT_ST_ISP_ASYNC_FIFO_OVF_INT_ST_Pos = 0x1
	// Bit mask of ISP_ASYNC_FIFO_OVF_INT_ST field.
	ISP_INT_ST_ISP_ASYNC_FIFO_OVF_INT_ST_Msk = 0x2
	// Bit ISP_ASYNC_FIFO_OVF_INT_ST.
	ISP_INT_ST_ISP_ASYNC_FIFO_OVF_INT_ST = 0x2
	// Position of ISP_BUF_FULL_INT_ST field.
	ISP_INT_ST_ISP_BUF_FULL_INT_ST_Pos = 0x2
	// Bit mask of ISP_BUF_FULL_INT_ST field.
	ISP_INT_ST_ISP_BUF_FULL_INT_ST_Msk = 0x4
	// Bit ISP_BUF_FULL_INT_ST.
	ISP_INT_ST_ISP_BUF_FULL_INT_ST = 0x4
	// Position of ISP_HVNUM_SETTING_ERR_INT_ST field.
	ISP_INT_ST_ISP_HVNUM_SETTING_ERR_INT_ST_Pos = 0x3
	// Bit mask of ISP_HVNUM_SETTING_ERR_INT_ST field.
	ISP_INT_ST_ISP_HVNUM_SETTING_ERR_INT_ST_Msk = 0x8
	// Bit ISP_HVNUM_SETTING_ERR_INT_ST.
	ISP_INT_ST_ISP_HVNUM_SETTING_ERR_INT_ST = 0x8
	// Position of ISP_DATA_TYPE_SETTING_ERR_INT_ST field.
	ISP_INT_ST_ISP_DATA_TYPE_SETTING_ERR_INT_ST_Pos = 0x4
	// Bit mask of ISP_DATA_TYPE_SETTING_ERR_INT_ST field.
	ISP_INT_ST_ISP_DATA_TYPE_SETTING_ERR_INT_ST_Msk = 0x10
	// Bit ISP_DATA_TYPE_SETTING_ERR_INT_ST.
	ISP_INT_ST_ISP_DATA_TYPE_SETTING_ERR_INT_ST = 0x10
	// Position of ISP_MIPI_HNUM_UNMATCH_INT_ST field.
	ISP_INT_ST_ISP_MIPI_HNUM_UNMATCH_INT_ST_Pos = 0x5
	// Bit mask of ISP_MIPI_HNUM_UNMATCH_INT_ST field.
	ISP_INT_ST_ISP_MIPI_HNUM_UNMATCH_INT_ST_Msk = 0x20
	// Bit ISP_MIPI_HNUM_UNMATCH_INT_ST.
	ISP_INT_ST_ISP_MIPI_HNUM_UNMATCH_INT_ST = 0x20
	// Position of DPC_CHECK_DONE_INT_ST field.
	ISP_INT_ST_DPC_CHECK_DONE_INT_ST_Pos = 0x6
	// Bit mask of DPC_CHECK_DONE_INT_ST field.
	ISP_INT_ST_DPC_CHECK_DONE_INT_ST_Msk = 0x40
	// Bit DPC_CHECK_DONE_INT_ST.
	ISP_INT_ST_DPC_CHECK_DONE_INT_ST = 0x40
	// Position of GAMMA_XCOORD_ERR_INT_ST field.
	ISP_INT_ST_GAMMA_XCOORD_ERR_INT_ST_Pos = 0x7
	// Bit mask of GAMMA_XCOORD_ERR_INT_ST field.
	ISP_INT_ST_GAMMA_XCOORD_ERR_INT_ST_Msk = 0x80
	// Bit GAMMA_XCOORD_ERR_INT_ST.
	ISP_INT_ST_GAMMA_XCOORD_ERR_INT_ST = 0x80
	// Position of AE_MONITOR_INT_ST field.
	ISP_INT_ST_AE_MONITOR_INT_ST_Pos = 0x8
	// Bit mask of AE_MONITOR_INT_ST field.
	ISP_INT_ST_AE_MONITOR_INT_ST_Msk = 0x100
	// Bit AE_MONITOR_INT_ST.
	ISP_INT_ST_AE_MONITOR_INT_ST = 0x100
	// Position of AE_FRAME_DONE_INT_ST field.
	ISP_INT_ST_AE_FRAME_DONE_INT_ST_Pos = 0x9
	// Bit mask of AE_FRAME_DONE_INT_ST field.
	ISP_INT_ST_AE_FRAME_DONE_INT_ST_Msk = 0x200
	// Bit AE_FRAME_DONE_INT_ST.
	ISP_INT_ST_AE_FRAME_DONE_INT_ST = 0x200
	// Position of AF_FDONE_INT_ST field.
	ISP_INT_ST_AF_FDONE_INT_ST_Pos = 0xa
	// Bit mask of AF_FDONE_INT_ST field.
	ISP_INT_ST_AF_FDONE_INT_ST_Msk = 0x400
	// Bit AF_FDONE_INT_ST.
	ISP_INT_ST_AF_FDONE_INT_ST = 0x400
	// Position of AF_ENV_INT_ST field.
	ISP_INT_ST_AF_ENV_INT_ST_Pos = 0xb
	// Bit mask of AF_ENV_INT_ST field.
	ISP_INT_ST_AF_ENV_INT_ST_Msk = 0x800
	// Bit AF_ENV_INT_ST.
	ISP_INT_ST_AF_ENV_INT_ST = 0x800
	// Position of AWB_FDONE_INT_ST field.
	ISP_INT_ST_AWB_FDONE_INT_ST_Pos = 0xc
	// Bit mask of AWB_FDONE_INT_ST field.
	ISP_INT_ST_AWB_FDONE_INT_ST_Msk = 0x1000
	// Bit AWB_FDONE_INT_ST.
	ISP_INT_ST_AWB_FDONE_INT_ST = 0x1000
	// Position of HIST_FDONE_INT_ST field.
	ISP_INT_ST_HIST_FDONE_INT_ST_Pos = 0xd
	// Bit mask of HIST_FDONE_INT_ST field.
	ISP_INT_ST_HIST_FDONE_INT_ST_Msk = 0x2000
	// Bit HIST_FDONE_INT_ST.
	ISP_INT_ST_HIST_FDONE_INT_ST = 0x2000
	// Position of FRAME_INT_ST field.
	ISP_INT_ST_FRAME_INT_ST_Pos = 0xe
	// Bit mask of FRAME_INT_ST field.
	ISP_INT_ST_FRAME_INT_ST_Msk = 0x4000
	// Bit FRAME_INT_ST.
	ISP_INT_ST_FRAME_INT_ST = 0x4000
	// Position of BLC_FRAME_INT_ST field.
	ISP_INT_ST_BLC_FRAME_INT_ST_Pos = 0xf
	// Bit mask of BLC_FRAME_INT_ST field.
	ISP_INT_ST_BLC_FRAME_INT_ST_Msk = 0x8000
	// Bit BLC_FRAME_INT_ST.
	ISP_INT_ST_BLC_FRAME_INT_ST = 0x8000
	// Position of LSC_FRAME_INT_ST field.
	ISP_INT_ST_LSC_FRAME_INT_ST_Pos = 0x10
	// Bit mask of LSC_FRAME_INT_ST field.
	ISP_INT_ST_LSC_FRAME_INT_ST_Msk = 0x10000
	// Bit LSC_FRAME_INT_ST.
	ISP_INT_ST_LSC_FRAME_INT_ST = 0x10000
	// Position of DPC_FRAME_INT_ST field.
	ISP_INT_ST_DPC_FRAME_INT_ST_Pos = 0x11
	// Bit mask of DPC_FRAME_INT_ST field.
	ISP_INT_ST_DPC_FRAME_INT_ST_Msk = 0x20000
	// Bit DPC_FRAME_INT_ST.
	ISP_INT_ST_DPC_FRAME_INT_ST = 0x20000
	// Position of BF_FRAME_INT_ST field.
	ISP_INT_ST_BF_FRAME_INT_ST_Pos = 0x12
	// Bit mask of BF_FRAME_INT_ST field.
	ISP_INT_ST_BF_FRAME_INT_ST_Msk = 0x40000
	// Bit BF_FRAME_INT_ST.
	ISP_INT_ST_BF_FRAME_INT_ST = 0x40000
	// Position of DEMOSAIC_FRAME_INT_ST field.
	ISP_INT_ST_DEMOSAIC_FRAME_INT_ST_Pos = 0x13
	// Bit mask of DEMOSAIC_FRAME_INT_ST field.
	ISP_INT_ST_DEMOSAIC_FRAME_INT_ST_Msk = 0x80000
	// Bit DEMOSAIC_FRAME_INT_ST.
	ISP_INT_ST_DEMOSAIC_FRAME_INT_ST = 0x80000
	// Position of MEDIAN_FRAME_INT_ST field.
	ISP_INT_ST_MEDIAN_FRAME_INT_ST_Pos = 0x14
	// Bit mask of MEDIAN_FRAME_INT_ST field.
	ISP_INT_ST_MEDIAN_FRAME_INT_ST_Msk = 0x100000
	// Bit MEDIAN_FRAME_INT_ST.
	ISP_INT_ST_MEDIAN_FRAME_INT_ST = 0x100000
	// Position of CCM_FRAME_INT_ST field.
	ISP_INT_ST_CCM_FRAME_INT_ST_Pos = 0x15
	// Bit mask of CCM_FRAME_INT_ST field.
	ISP_INT_ST_CCM_FRAME_INT_ST_Msk = 0x200000
	// Bit CCM_FRAME_INT_ST.
	ISP_INT_ST_CCM_FRAME_INT_ST = 0x200000
	// Position of GAMMA_FRAME_INT_ST field.
	ISP_INT_ST_GAMMA_FRAME_INT_ST_Pos = 0x16
	// Bit mask of GAMMA_FRAME_INT_ST field.
	ISP_INT_ST_GAMMA_FRAME_INT_ST_Msk = 0x400000
	// Bit GAMMA_FRAME_INT_ST.
	ISP_INT_ST_GAMMA_FRAME_INT_ST = 0x400000
	// Position of RGB2YUV_FRAME_INT_ST field.
	ISP_INT_ST_RGB2YUV_FRAME_INT_ST_Pos = 0x17
	// Bit mask of RGB2YUV_FRAME_INT_ST field.
	ISP_INT_ST_RGB2YUV_FRAME_INT_ST_Msk = 0x800000
	// Bit RGB2YUV_FRAME_INT_ST.
	ISP_INT_ST_RGB2YUV_FRAME_INT_ST = 0x800000
	// Position of SHARP_FRAME_INT_ST field.
	ISP_INT_ST_SHARP_FRAME_INT_ST_Pos = 0x18
	// Bit mask of SHARP_FRAME_INT_ST field.
	ISP_INT_ST_SHARP_FRAME_INT_ST_Msk = 0x1000000
	// Bit SHARP_FRAME_INT_ST.
	ISP_INT_ST_SHARP_FRAME_INT_ST = 0x1000000
	// Position of COLOR_FRAME_INT_ST field.
	ISP_INT_ST_COLOR_FRAME_INT_ST_Pos = 0x19
	// Bit mask of COLOR_FRAME_INT_ST field.
	ISP_INT_ST_COLOR_FRAME_INT_ST_Msk = 0x2000000
	// Bit COLOR_FRAME_INT_ST.
	ISP_INT_ST_COLOR_FRAME_INT_ST = 0x2000000
	// Position of YUV2RGB_FRAME_INT_ST field.
	ISP_INT_ST_YUV2RGB_FRAME_INT_ST_Pos = 0x1a
	// Bit mask of YUV2RGB_FRAME_INT_ST field.
	ISP_INT_ST_YUV2RGB_FRAME_INT_ST_Msk = 0x4000000
	// Bit YUV2RGB_FRAME_INT_ST.
	ISP_INT_ST_YUV2RGB_FRAME_INT_ST = 0x4000000
	// Position of TAIL_IDI_FRAME_INT_ST field.
	ISP_INT_ST_TAIL_IDI_FRAME_INT_ST_Pos = 0x1b
	// Bit mask of TAIL_IDI_FRAME_INT_ST field.
	ISP_INT_ST_TAIL_IDI_FRAME_INT_ST_Msk = 0x8000000
	// Bit TAIL_IDI_FRAME_INT_ST.
	ISP_INT_ST_TAIL_IDI_FRAME_INT_ST = 0x8000000
	// Position of HEADER_IDI_FRAME_INT_ST field.
	ISP_INT_ST_HEADER_IDI_FRAME_INT_ST_Pos = 0x1c
	// Bit mask of HEADER_IDI_FRAME_INT_ST field.
	ISP_INT_ST_HEADER_IDI_FRAME_INT_ST_Msk = 0x10000000
	// Bit HEADER_IDI_FRAME_INT_ST.
	ISP_INT_ST_HEADER_IDI_FRAME_INT_ST = 0x10000000

	// INT_ENA: interrupt enable register
	// Position of ISP_DATA_TYPE_ERR_INT_ENA field.
	ISP_INT_ENA_ISP_DATA_TYPE_ERR_INT_ENA_Pos = 0x0
	// Bit mask of ISP_DATA_TYPE_ERR_INT_ENA field.
	ISP_INT_ENA_ISP_DATA_TYPE_ERR_INT_ENA_Msk = 0x1
	// Bit ISP_DATA_TYPE_ERR_INT_ENA.
	ISP_INT_ENA_ISP_DATA_TYPE_ERR_INT_ENA = 0x1
	// Position of ISP_ASYNC_FIFO_OVF_INT_ENA field.
	ISP_INT_ENA_ISP_ASYNC_FIFO_OVF_INT_ENA_Pos = 0x1
	// Bit mask of ISP_ASYNC_FIFO_OVF_INT_ENA field.
	ISP_INT_ENA_ISP_ASYNC_FIFO_OVF_INT_ENA_Msk = 0x2
	// Bit ISP_ASYNC_FIFO_OVF_INT_ENA.
	ISP_INT_ENA_ISP_ASYNC_FIFO_OVF_INT_ENA = 0x2
	// Position of ISP_BUF_FULL_INT_ENA field.
	ISP_INT_ENA_ISP_BUF_FULL_INT_ENA_Pos = 0x2
	// Bit mask of ISP_BUF_FULL_INT_ENA field.
	ISP_INT_ENA_ISP_BUF_FULL_INT_ENA_Msk = 0x4
	// Bit ISP_BUF_FULL_INT_ENA.
	ISP_INT_ENA_ISP_BUF_FULL_INT_ENA = 0x4
	// Position of ISP_HVNUM_SETTING_ERR_INT_ENA field.
	ISP_INT_ENA_ISP_HVNUM_SETTING_ERR_INT_ENA_Pos = 0x3
	// Bit mask of ISP_HVNUM_SETTING_ERR_INT_ENA field.
	ISP_INT_ENA_ISP_HVNUM_SETTING_ERR_INT_ENA_Msk = 0x8
	// Bit ISP_HVNUM_SETTING_ERR_INT_ENA.
	ISP_INT_ENA_ISP_HVNUM_SETTING_ERR_INT_ENA = 0x8
	// Position of ISP_DATA_TYPE_SETTING_ERR_INT_ENA field.
	ISP_INT_ENA_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_Pos = 0x4
	// Bit mask of ISP_DATA_TYPE_SETTING_ERR_INT_ENA field.
	ISP_INT_ENA_ISP_DATA_TYPE_SETTING_ERR_INT_ENA_Msk = 0x10
	// Bit ISP_DATA_TYPE_SETTING_ERR_INT_ENA.
	ISP_INT_ENA_ISP_DATA_TYPE_SETTING_ERR_INT_ENA = 0x10
	// Position of ISP_MIPI_HNUM_UNMATCH_INT_ENA field.
	ISP_INT_ENA_ISP_MIPI_HNUM_UNMATCH_INT_ENA_Pos = 0x5
	// Bit mask of ISP_MIPI_HNUM_UNMATCH_INT_ENA field.
	ISP_INT_ENA_ISP_MIPI_HNUM_UNMATCH_INT_ENA_Msk = 0x20
	// Bit ISP_MIPI_HNUM_UNMATCH_INT_ENA.
	ISP_INT_ENA_ISP_MIPI_HNUM_UNMATCH_INT_ENA = 0x20
	// Position of DPC_CHECK_DONE_INT_ENA field.
	ISP_INT_ENA_DPC_CHECK_DONE_INT_ENA_Pos = 0x6
	// Bit mask of DPC_CHECK_DONE_INT_ENA field.
	ISP_INT_ENA_DPC_CHECK_DONE_INT_ENA_Msk = 0x40
	// Bit DPC_CHECK_DONE_INT_ENA.
	ISP_INT_ENA_DPC_CHECK_DONE_INT_ENA = 0x40
	// Position of GAMMA_XCOORD_ERR_INT_ENA field.
	ISP_INT_ENA_GAMMA_XCOORD_ERR_INT_ENA_Pos = 0x7
	// Bit mask of GAMMA_XCOORD_ERR_INT_ENA field.
	ISP_INT_ENA_GAMMA_XCOORD_ERR_INT_ENA_Msk = 0x80
	// Bit GAMMA_XCOORD_ERR_INT_ENA.
	ISP_INT_ENA_GAMMA_XCOORD_ERR_INT_ENA = 0x80
	// Position of AE_MONITOR_INT_ENA field.
	ISP_INT_ENA_AE_MONITOR_INT_ENA_Pos = 0x8
	// Bit mask of AE_MONITOR_INT_ENA field.
	ISP_INT_ENA_AE_MONITOR_INT_ENA_Msk = 0x100
	// Bit AE_MONITOR_INT_ENA.
	ISP_INT_ENA_AE_MONITOR_INT_ENA = 0x100
	// Position of AE_FRAME_DONE_INT_ENA field.
	ISP_INT_ENA_AE_FRAME_DONE_INT_ENA_Pos = 0x9
	// Bit mask of AE_FRAME_DONE_INT_ENA field.
	ISP_INT_ENA_AE_FRAME_DONE_INT_ENA_Msk = 0x200
	// Bit AE_FRAME_DONE_INT_ENA.
	ISP_INT_ENA_AE_FRAME_DONE_INT_ENA = 0x200
	// Position of AF_FDONE_INT_ENA field.
	ISP_INT_ENA_AF_FDONE_INT_ENA_Pos = 0xa
	// Bit mask of AF_FDONE_INT_ENA field.
	ISP_INT_ENA_AF_FDONE_INT_ENA_Msk = 0x400
	// Bit AF_FDONE_INT_ENA.
	ISP_INT_ENA_AF_FDONE_INT_ENA = 0x400
	// Position of AF_ENV_INT_ENA field.
	ISP_INT_ENA_AF_ENV_INT_ENA_Pos = 0xb
	// Bit mask of AF_ENV_INT_ENA field.
	ISP_INT_ENA_AF_ENV_INT_ENA_Msk = 0x800
	// Bit AF_ENV_INT_ENA.
	ISP_INT_ENA_AF_ENV_INT_ENA = 0x800
	// Position of AWB_FDONE_INT_ENA field.
	ISP_INT_ENA_AWB_FDONE_INT_ENA_Pos = 0xc
	// Bit mask of AWB_FDONE_INT_ENA field.
	ISP_INT_ENA_AWB_FDONE_INT_ENA_Msk = 0x1000
	// Bit AWB_FDONE_INT_ENA.
	ISP_INT_ENA_AWB_FDONE_INT_ENA = 0x1000
	// Position of HIST_FDONE_INT_ENA field.
	ISP_INT_ENA_HIST_FDONE_INT_ENA_Pos = 0xd
	// Bit mask of HIST_FDONE_INT_ENA field.
	ISP_INT_ENA_HIST_FDONE_INT_ENA_Msk = 0x2000
	// Bit HIST_FDONE_INT_ENA.
	ISP_INT_ENA_HIST_FDONE_INT_ENA = 0x2000
	// Position of FRAME_INT_ENA field.
	ISP_INT_ENA_FRAME_INT_ENA_Pos = 0xe
	// Bit mask of FRAME_INT_ENA field.
	ISP_INT_ENA_FRAME_INT_ENA_Msk = 0x4000
	// Bit FRAME_INT_ENA.
	ISP_INT_ENA_FRAME_INT_ENA = 0x4000
	// Position of BLC_FRAME_INT_ENA field.
	ISP_INT_ENA_BLC_FRAME_INT_ENA_Pos = 0xf
	// Bit mask of BLC_FRAME_INT_ENA field.
	ISP_INT_ENA_BLC_FRAME_INT_ENA_Msk = 0x8000
	// Bit BLC_FRAME_INT_ENA.
	ISP_INT_ENA_BLC_FRAME_INT_ENA = 0x8000
	// Position of LSC_FRAME_INT_ENA field.
	ISP_INT_ENA_LSC_FRAME_INT_ENA_Pos = 0x10
	// Bit mask of LSC_FRAME_INT_ENA field.
	ISP_INT_ENA_LSC_FRAME_INT_ENA_Msk = 0x10000
	// Bit LSC_FRAME_INT_ENA.
	ISP_INT_ENA_LSC_FRAME_INT_ENA = 0x10000
	// Position of DPC_FRAME_INT_ENA field.
	ISP_INT_ENA_DPC_FRAME_INT_ENA_Pos = 0x11
	// Bit mask of DPC_FRAME_INT_ENA field.
	ISP_INT_ENA_DPC_FRAME_INT_ENA_Msk = 0x20000
	// Bit DPC_FRAME_INT_ENA.
	ISP_INT_ENA_DPC_FRAME_INT_ENA = 0x20000
	// Position of BF_FRAME_INT_ENA field.
	ISP_INT_ENA_BF_FRAME_INT_ENA_Pos = 0x12
	// Bit mask of BF_FRAME_INT_ENA field.
	ISP_INT_ENA_BF_FRAME_INT_ENA_Msk = 0x40000
	// Bit BF_FRAME_INT_ENA.
	ISP_INT_ENA_BF_FRAME_INT_ENA = 0x40000
	// Position of DEMOSAIC_FRAME_INT_ENA field.
	ISP_INT_ENA_DEMOSAIC_FRAME_INT_ENA_Pos = 0x13
	// Bit mask of DEMOSAIC_FRAME_INT_ENA field.
	ISP_INT_ENA_DEMOSAIC_FRAME_INT_ENA_Msk = 0x80000
	// Bit DEMOSAIC_FRAME_INT_ENA.
	ISP_INT_ENA_DEMOSAIC_FRAME_INT_ENA = 0x80000
	// Position of MEDIAN_FRAME_INT_ENA field.
	ISP_INT_ENA_MEDIAN_FRAME_INT_ENA_Pos = 0x14
	// Bit mask of MEDIAN_FRAME_INT_ENA field.
	ISP_INT_ENA_MEDIAN_FRAME_INT_ENA_Msk = 0x100000
	// Bit MEDIAN_FRAME_INT_ENA.
	ISP_INT_ENA_MEDIAN_FRAME_INT_ENA = 0x100000
	// Position of CCM_FRAME_INT_ENA field.
	ISP_INT_ENA_CCM_FRAME_INT_ENA_Pos = 0x15
	// Bit mask of CCM_FRAME_INT_ENA field.
	ISP_INT_ENA_CCM_FRAME_INT_ENA_Msk = 0x200000
	// Bit CCM_FRAME_INT_ENA.
	ISP_INT_ENA_CCM_FRAME_INT_ENA = 0x200000
	// Position of GAMMA_FRAME_INT_ENA field.
	ISP_INT_ENA_GAMMA_FRAME_INT_ENA_Pos = 0x16
	// Bit mask of GAMMA_FRAME_INT_ENA field.
	ISP_INT_ENA_GAMMA_FRAME_INT_ENA_Msk = 0x400000
	// Bit GAMMA_FRAME_INT_ENA.
	ISP_INT_ENA_GAMMA_FRAME_INT_ENA = 0x400000
	// Position of RGB2YUV_FRAME_INT_ENA field.
	ISP_INT_ENA_RGB2YUV_FRAME_INT_ENA_Pos = 0x17
	// Bit mask of RGB2YUV_FRAME_INT_ENA field.
	ISP_INT_ENA_RGB2YUV_FRAME_INT_ENA_Msk = 0x800000
	// Bit RGB2YUV_FRAME_INT_ENA.
	ISP_INT_ENA_RGB2YUV_FRAME_INT_ENA = 0x800000
	// Position of SHARP_FRAME_INT_ENA field.
	ISP_INT_ENA_SHARP_FRAME_INT_ENA_Pos = 0x18
	// Bit mask of SHARP_FRAME_INT_ENA field.
	ISP_INT_ENA_SHARP_FRAME_INT_ENA_Msk = 0x1000000
	// Bit SHARP_FRAME_INT_ENA.
	ISP_INT_ENA_SHARP_FRAME_INT_ENA = 0x1000000
	// Position of COLOR_FRAME_INT_ENA field.
	ISP_INT_ENA_COLOR_FRAME_INT_ENA_Pos = 0x19
	// Bit mask of COLOR_FRAME_INT_ENA field.
	ISP_INT_ENA_COLOR_FRAME_INT_ENA_Msk = 0x2000000
	// Bit COLOR_FRAME_INT_ENA.
	ISP_INT_ENA_COLOR_FRAME_INT_ENA = 0x2000000
	// Position of YUV2RGB_FRAME_INT_ENA field.
	ISP_INT_ENA_YUV2RGB_FRAME_INT_ENA_Pos = 0x1a
	// Bit mask of YUV2RGB_FRAME_INT_ENA field.
	ISP_INT_ENA_YUV2RGB_FRAME_INT_ENA_Msk = 0x4000000
	// Bit YUV2RGB_FRAME_INT_ENA.
	ISP_INT_ENA_YUV2RGB_FRAME_INT_ENA = 0x4000000
	// Position of TAIL_IDI_FRAME_INT_ENA field.
	ISP_INT_ENA_TAIL_IDI_FRAME_INT_ENA_Pos = 0x1b
	// Bit mask of TAIL_IDI_FRAME_INT_ENA field.
	ISP_INT_ENA_TAIL_IDI_FRAME_INT_ENA_Msk = 0x8000000
	// Bit TAIL_IDI_FRAME_INT_ENA.
	ISP_INT_ENA_TAIL_IDI_FRAME_INT_ENA = 0x8000000
	// Position of HEADER_IDI_FRAME_INT_ENA field.
	ISP_INT_ENA_HEADER_IDI_FRAME_INT_ENA_Pos = 0x1c
	// Bit mask of HEADER_IDI_FRAME_INT_ENA field.
	ISP_INT_ENA_HEADER_IDI_FRAME_INT_ENA_Msk = 0x10000000
	// Bit HEADER_IDI_FRAME_INT_ENA.
	ISP_INT_ENA_HEADER_IDI_FRAME_INT_ENA = 0x10000000

	// INT_CLR: interrupt clear register
	// Position of ISP_DATA_TYPE_ERR_INT_CLR field.
	ISP_INT_CLR_ISP_DATA_TYPE_ERR_INT_CLR_Pos = 0x0
	// Bit mask of ISP_DATA_TYPE_ERR_INT_CLR field.
	ISP_INT_CLR_ISP_DATA_TYPE_ERR_INT_CLR_Msk = 0x1
	// Bit ISP_DATA_TYPE_ERR_INT_CLR.
	ISP_INT_CLR_ISP_DATA_TYPE_ERR_INT_CLR = 0x1
	// Position of ISP_ASYNC_FIFO_OVF_INT_CLR field.
	ISP_INT_CLR_ISP_ASYNC_FIFO_OVF_INT_CLR_Pos = 0x1
	// Bit mask of ISP_ASYNC_FIFO_OVF_INT_CLR field.
	ISP_INT_CLR_ISP_ASYNC_FIFO_OVF_INT_CLR_Msk = 0x2
	// Bit ISP_ASYNC_FIFO_OVF_INT_CLR.
	ISP_INT_CLR_ISP_ASYNC_FIFO_OVF_INT_CLR = 0x2
	// Position of ISP_BUF_FULL_INT_CLR field.
	ISP_INT_CLR_ISP_BUF_FULL_INT_CLR_Pos = 0x2
	// Bit mask of ISP_BUF_FULL_INT_CLR field.
	ISP_INT_CLR_ISP_BUF_FULL_INT_CLR_Msk = 0x4
	// Bit ISP_BUF_FULL_INT_CLR.
	ISP_INT_CLR_ISP_BUF_FULL_INT_CLR = 0x4
	// Position of ISP_HVNUM_SETTING_ERR_INT_CLR field.
	ISP_INT_CLR_ISP_HVNUM_SETTING_ERR_INT_CLR_Pos = 0x3
	// Bit mask of ISP_HVNUM_SETTING_ERR_INT_CLR field.
	ISP_INT_CLR_ISP_HVNUM_SETTING_ERR_INT_CLR_Msk = 0x8
	// Bit ISP_HVNUM_SETTING_ERR_INT_CLR.
	ISP_INT_CLR_ISP_HVNUM_SETTING_ERR_INT_CLR = 0x8
	// Position of ISP_DATA_TYPE_SETTING_ERR_INT_CLR field.
	ISP_INT_CLR_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_Pos = 0x4
	// Bit mask of ISP_DATA_TYPE_SETTING_ERR_INT_CLR field.
	ISP_INT_CLR_ISP_DATA_TYPE_SETTING_ERR_INT_CLR_Msk = 0x10
	// Bit ISP_DATA_TYPE_SETTING_ERR_INT_CLR.
	ISP_INT_CLR_ISP_DATA_TYPE_SETTING_ERR_INT_CLR = 0x10
	// Position of ISP_MIPI_HNUM_UNMATCH_INT_CLR field.
	ISP_INT_CLR_ISP_MIPI_HNUM_UNMATCH_INT_CLR_Pos = 0x5
	// Bit mask of ISP_MIPI_HNUM_UNMATCH_INT_CLR field.
	ISP_INT_CLR_ISP_MIPI_HNUM_UNMATCH_INT_CLR_Msk = 0x20
	// Bit ISP_MIPI_HNUM_UNMATCH_INT_CLR.
	ISP_INT_CLR_ISP_MIPI_HNUM_UNMATCH_INT_CLR = 0x20
	// Position of DPC_CHECK_DONE_INT_CLR field.
	ISP_INT_CLR_DPC_CHECK_DONE_INT_CLR_Pos = 0x6
	// Bit mask of DPC_CHECK_DONE_INT_CLR field.
	ISP_INT_CLR_DPC_CHECK_DONE_INT_CLR_Msk = 0x40
	// Bit DPC_CHECK_DONE_INT_CLR.
	ISP_INT_CLR_DPC_CHECK_DONE_INT_CLR = 0x40
	// Position of GAMMA_XCOORD_ERR_INT_CLR field.
	ISP_INT_CLR_GAMMA_XCOORD_ERR_INT_CLR_Pos = 0x7
	// Bit mask of GAMMA_XCOORD_ERR_INT_CLR field.
	ISP_INT_CLR_GAMMA_XCOORD_ERR_INT_CLR_Msk = 0x80
	// Bit GAMMA_XCOORD_ERR_INT_CLR.
	ISP_INT_CLR_GAMMA_XCOORD_ERR_INT_CLR = 0x80
	// Position of AE_MONITOR_INT_CLR field.
	ISP_INT_CLR_AE_MONITOR_INT_CLR_Pos = 0x8
	// Bit mask of AE_MONITOR_INT_CLR field.
	ISP_INT_CLR_AE_MONITOR_INT_CLR_Msk = 0x100
	// Bit AE_MONITOR_INT_CLR.
	ISP_INT_CLR_AE_MONITOR_INT_CLR = 0x100
	// Position of AE_FRAME_DONE_INT_CLR field.
	ISP_INT_CLR_AE_FRAME_DONE_INT_CLR_Pos = 0x9
	// Bit mask of AE_FRAME_DONE_INT_CLR field.
	ISP_INT_CLR_AE_FRAME_DONE_INT_CLR_Msk = 0x200
	// Bit AE_FRAME_DONE_INT_CLR.
	ISP_INT_CLR_AE_FRAME_DONE_INT_CLR = 0x200
	// Position of AF_FDONE_INT_CLR field.
	ISP_INT_CLR_AF_FDONE_INT_CLR_Pos = 0xa
	// Bit mask of AF_FDONE_INT_CLR field.
	ISP_INT_CLR_AF_FDONE_INT_CLR_Msk = 0x400
	// Bit AF_FDONE_INT_CLR.
	ISP_INT_CLR_AF_FDONE_INT_CLR = 0x400
	// Position of AF_ENV_INT_CLR field.
	ISP_INT_CLR_AF_ENV_INT_CLR_Pos = 0xb
	// Bit mask of AF_ENV_INT_CLR field.
	ISP_INT_CLR_AF_ENV_INT_CLR_Msk = 0x800
	// Bit AF_ENV_INT_CLR.
	ISP_INT_CLR_AF_ENV_INT_CLR = 0x800
	// Position of AWB_FDONE_INT_CLR field.
	ISP_INT_CLR_AWB_FDONE_INT_CLR_Pos = 0xc
	// Bit mask of AWB_FDONE_INT_CLR field.
	ISP_INT_CLR_AWB_FDONE_INT_CLR_Msk = 0x1000
	// Bit AWB_FDONE_INT_CLR.
	ISP_INT_CLR_AWB_FDONE_INT_CLR = 0x1000
	// Position of HIST_FDONE_INT_CLR field.
	ISP_INT_CLR_HIST_FDONE_INT_CLR_Pos = 0xd
	// Bit mask of HIST_FDONE_INT_CLR field.
	ISP_INT_CLR_HIST_FDONE_INT_CLR_Msk = 0x2000
	// Bit HIST_FDONE_INT_CLR.
	ISP_INT_CLR_HIST_FDONE_INT_CLR = 0x2000
	// Position of FRAME_INT_CLR field.
	ISP_INT_CLR_FRAME_INT_CLR_Pos = 0xe
	// Bit mask of FRAME_INT_CLR field.
	ISP_INT_CLR_FRAME_INT_CLR_Msk = 0x4000
	// Bit FRAME_INT_CLR.
	ISP_INT_CLR_FRAME_INT_CLR = 0x4000
	// Position of BLC_FRAME_INT_CLR field.
	ISP_INT_CLR_BLC_FRAME_INT_CLR_Pos = 0xf
	// Bit mask of BLC_FRAME_INT_CLR field.
	ISP_INT_CLR_BLC_FRAME_INT_CLR_Msk = 0x8000
	// Bit BLC_FRAME_INT_CLR.
	ISP_INT_CLR_BLC_FRAME_INT_CLR = 0x8000
	// Position of LSC_FRAME_INT_CLR field.
	ISP_INT_CLR_LSC_FRAME_INT_CLR_Pos = 0x10
	// Bit mask of LSC_FRAME_INT_CLR field.
	ISP_INT_CLR_LSC_FRAME_INT_CLR_Msk = 0x10000
	// Bit LSC_FRAME_INT_CLR.
	ISP_INT_CLR_LSC_FRAME_INT_CLR = 0x10000
	// Position of DPC_FRAME_INT_CLR field.
	ISP_INT_CLR_DPC_FRAME_INT_CLR_Pos = 0x11
	// Bit mask of DPC_FRAME_INT_CLR field.
	ISP_INT_CLR_DPC_FRAME_INT_CLR_Msk = 0x20000
	// Bit DPC_FRAME_INT_CLR.
	ISP_INT_CLR_DPC_FRAME_INT_CLR = 0x20000
	// Position of BF_FRAME_INT_CLR field.
	ISP_INT_CLR_BF_FRAME_INT_CLR_Pos = 0x12
	// Bit mask of BF_FRAME_INT_CLR field.
	ISP_INT_CLR_BF_FRAME_INT_CLR_Msk = 0x40000
	// Bit BF_FRAME_INT_CLR.
	ISP_INT_CLR_BF_FRAME_INT_CLR = 0x40000
	// Position of DEMOSAIC_FRAME_INT_CLR field.
	ISP_INT_CLR_DEMOSAIC_FRAME_INT_CLR_Pos = 0x13
	// Bit mask of DEMOSAIC_FRAME_INT_CLR field.
	ISP_INT_CLR_DEMOSAIC_FRAME_INT_CLR_Msk = 0x80000
	// Bit DEMOSAIC_FRAME_INT_CLR.
	ISP_INT_CLR_DEMOSAIC_FRAME_INT_CLR = 0x80000
	// Position of MEDIAN_FRAME_INT_CLR field.
	ISP_INT_CLR_MEDIAN_FRAME_INT_CLR_Pos = 0x14
	// Bit mask of MEDIAN_FRAME_INT_CLR field.
	ISP_INT_CLR_MEDIAN_FRAME_INT_CLR_Msk = 0x100000
	// Bit MEDIAN_FRAME_INT_CLR.
	ISP_INT_CLR_MEDIAN_FRAME_INT_CLR = 0x100000
	// Position of CCM_FRAME_INT_CLR field.
	ISP_INT_CLR_CCM_FRAME_INT_CLR_Pos = 0x15
	// Bit mask of CCM_FRAME_INT_CLR field.
	ISP_INT_CLR_CCM_FRAME_INT_CLR_Msk = 0x200000
	// Bit CCM_FRAME_INT_CLR.
	ISP_INT_CLR_CCM_FRAME_INT_CLR = 0x200000
	// Position of GAMMA_FRAME_INT_CLR field.
	ISP_INT_CLR_GAMMA_FRAME_INT_CLR_Pos = 0x16
	// Bit mask of GAMMA_FRAME_INT_CLR field.
	ISP_INT_CLR_GAMMA_FRAME_INT_CLR_Msk = 0x400000
	// Bit GAMMA_FRAME_INT_CLR.
	ISP_INT_CLR_GAMMA_FRAME_INT_CLR = 0x400000
	// Position of RGB2YUV_FRAME_INT_CLR field.
	ISP_INT_CLR_RGB2YUV_FRAME_INT_CLR_Pos = 0x17
	// Bit mask of RGB2YUV_FRAME_INT_CLR field.
	ISP_INT_CLR_RGB2YUV_FRAME_INT_CLR_Msk = 0x800000
	// Bit RGB2YUV_FRAME_INT_CLR.
	ISP_INT_CLR_RGB2YUV_FRAME_INT_CLR = 0x800000
	// Position of SHARP_FRAME_INT_CLR field.
	ISP_INT_CLR_SHARP_FRAME_INT_CLR_Pos = 0x18
	// Bit mask of SHARP_FRAME_INT_CLR field.
	ISP_INT_CLR_SHARP_FRAME_INT_CLR_Msk = 0x1000000
	// Bit SHARP_FRAME_INT_CLR.
	ISP_INT_CLR_SHARP_FRAME_INT_CLR = 0x1000000
	// Position of COLOR_FRAME_INT_CLR field.
	ISP_INT_CLR_COLOR_FRAME_INT_CLR_Pos = 0x19
	// Bit mask of COLOR_FRAME_INT_CLR field.
	ISP_INT_CLR_COLOR_FRAME_INT_CLR_Msk = 0x2000000
	// Bit COLOR_FRAME_INT_CLR.
	ISP_INT_CLR_COLOR_FRAME_INT_CLR = 0x2000000
	// Position of YUV2RGB_FRAME_INT_CLR field.
	ISP_INT_CLR_YUV2RGB_FRAME_INT_CLR_Pos = 0x1a
	// Bit mask of YUV2RGB_FRAME_INT_CLR field.
	ISP_INT_CLR_YUV2RGB_FRAME_INT_CLR_Msk = 0x4000000
	// Bit YUV2RGB_FRAME_INT_CLR.
	ISP_INT_CLR_YUV2RGB_FRAME_INT_CLR = 0x4000000
	// Position of TAIL_IDI_FRAME_INT_CLR field.
	ISP_INT_CLR_TAIL_IDI_FRAME_INT_CLR_Pos = 0x1b
	// Bit mask of TAIL_IDI_FRAME_INT_CLR field.
	ISP_INT_CLR_TAIL_IDI_FRAME_INT_CLR_Msk = 0x8000000
	// Bit TAIL_IDI_FRAME_INT_CLR.
	ISP_INT_CLR_TAIL_IDI_FRAME_INT_CLR = 0x8000000
	// Position of HEADER_IDI_FRAME_INT_CLR field.
	ISP_INT_CLR_HEADER_IDI_FRAME_INT_CLR_Pos = 0x1c
	// Bit mask of HEADER_IDI_FRAME_INT_CLR field.
	ISP_INT_CLR_HEADER_IDI_FRAME_INT_CLR_Msk = 0x10000000
	// Bit HEADER_IDI_FRAME_INT_CLR.
	ISP_INT_CLR_HEADER_IDI_FRAME_INT_CLR = 0x10000000

	// GAMMA_CTRL: gamma control register
	// Position of GAMMA_UPDATE field.
	ISP_GAMMA_CTRL_GAMMA_UPDATE_Pos = 0x0
	// Bit mask of GAMMA_UPDATE field.
	ISP_GAMMA_CTRL_GAMMA_UPDATE_Msk = 0x1
	// Bit GAMMA_UPDATE.
	ISP_GAMMA_CTRL_GAMMA_UPDATE = 0x1
	// Position of GAMMA_B_LAST_CORRECT field.
	ISP_GAMMA_CTRL_GAMMA_B_LAST_CORRECT_Pos = 0x1
	// Bit mask of GAMMA_B_LAST_CORRECT field.
	ISP_GAMMA_CTRL_GAMMA_B_LAST_CORRECT_Msk = 0x2
	// Bit GAMMA_B_LAST_CORRECT.
	ISP_GAMMA_CTRL_GAMMA_B_LAST_CORRECT = 0x2
	// Position of GAMMA_G_LAST_CORRECT field.
	ISP_GAMMA_CTRL_GAMMA_G_LAST_CORRECT_Pos = 0x2
	// Bit mask of GAMMA_G_LAST_CORRECT field.
	ISP_GAMMA_CTRL_GAMMA_G_LAST_CORRECT_Msk = 0x4
	// Bit GAMMA_G_LAST_CORRECT.
	ISP_GAMMA_CTRL_GAMMA_G_LAST_CORRECT = 0x4
	// Position of GAMMA_R_LAST_CORRECT field.
	ISP_GAMMA_CTRL_GAMMA_R_LAST_CORRECT_Pos = 0x3
	// Bit mask of GAMMA_R_LAST_CORRECT field.
	ISP_GAMMA_CTRL_GAMMA_R_LAST_CORRECT_Msk = 0x8
	// Bit GAMMA_R_LAST_CORRECT.
	ISP_GAMMA_CTRL_GAMMA_R_LAST_CORRECT = 0x8

	// GAMMA_RY1: point of Y-axis of r channel gamma curve register 1
	// Position of GAMMA_R_Y03 field.
	ISP_GAMMA_RY1_GAMMA_R_Y03_Pos = 0x0
	// Bit mask of GAMMA_R_Y03 field.
	ISP_GAMMA_RY1_GAMMA_R_Y03_Msk = 0xff
	// Position of GAMMA_R_Y02 field.
	ISP_GAMMA_RY1_GAMMA_R_Y02_Pos = 0x8
	// Bit mask of GAMMA_R_Y02 field.
	ISP_GAMMA_RY1_GAMMA_R_Y02_Msk = 0xff00
	// Position of GAMMA_R_Y01 field.
	ISP_GAMMA_RY1_GAMMA_R_Y01_Pos = 0x10
	// Bit mask of GAMMA_R_Y01 field.
	ISP_GAMMA_RY1_GAMMA_R_Y01_Msk = 0xff0000
	// Position of GAMMA_R_Y00 field.
	ISP_GAMMA_RY1_GAMMA_R_Y00_Pos = 0x18
	// Bit mask of GAMMA_R_Y00 field.
	ISP_GAMMA_RY1_GAMMA_R_Y00_Msk = 0xff000000

	// GAMMA_RY2: point of Y-axis of r channel gamma curve register 2
	// Position of GAMMA_R_Y07 field.
	ISP_GAMMA_RY2_GAMMA_R_Y07_Pos = 0x0
	// Bit mask of GAMMA_R_Y07 field.
	ISP_GAMMA_RY2_GAMMA_R_Y07_Msk = 0xff
	// Position of GAMMA_R_Y06 field.
	ISP_GAMMA_RY2_GAMMA_R_Y06_Pos = 0x8
	// Bit mask of GAMMA_R_Y06 field.
	ISP_GAMMA_RY2_GAMMA_R_Y06_Msk = 0xff00
	// Position of GAMMA_R_Y05 field.
	ISP_GAMMA_RY2_GAMMA_R_Y05_Pos = 0x10
	// Bit mask of GAMMA_R_Y05 field.
	ISP_GAMMA_RY2_GAMMA_R_Y05_Msk = 0xff0000
	// Position of GAMMA_R_Y04 field.
	ISP_GAMMA_RY2_GAMMA_R_Y04_Pos = 0x18
	// Bit mask of GAMMA_R_Y04 field.
	ISP_GAMMA_RY2_GAMMA_R_Y04_Msk = 0xff000000

	// GAMMA_RY3: point of Y-axis of r channel gamma curve register 3
	// Position of GAMMA_R_Y0B field.
	ISP_GAMMA_RY3_GAMMA_R_Y0B_Pos = 0x0
	// Bit mask of GAMMA_R_Y0B field.
	ISP_GAMMA_RY3_GAMMA_R_Y0B_Msk = 0xff
	// Position of GAMMA_R_Y0A field.
	ISP_GAMMA_RY3_GAMMA_R_Y0A_Pos = 0x8
	// Bit mask of GAMMA_R_Y0A field.
	ISP_GAMMA_RY3_GAMMA_R_Y0A_Msk = 0xff00
	// Position of GAMMA_R_Y09 field.
	ISP_GAMMA_RY3_GAMMA_R_Y09_Pos = 0x10
	// Bit mask of GAMMA_R_Y09 field.
	ISP_GAMMA_RY3_GAMMA_R_Y09_Msk = 0xff0000
	// Position of GAMMA_R_Y08 field.
	ISP_GAMMA_RY3_GAMMA_R_Y08_Pos = 0x18
	// Bit mask of GAMMA_R_Y08 field.
	ISP_GAMMA_RY3_GAMMA_R_Y08_Msk = 0xff000000

	// GAMMA_RY4: point of Y-axis of r channel gamma curve register 4
	// Position of GAMMA_R_Y0F field.
	ISP_GAMMA_RY4_GAMMA_R_Y0F_Pos = 0x0
	// Bit mask of GAMMA_R_Y0F field.
	ISP_GAMMA_RY4_GAMMA_R_Y0F_Msk = 0xff
	// Position of GAMMA_R_Y0E field.
	ISP_GAMMA_RY4_GAMMA_R_Y0E_Pos = 0x8
	// Bit mask of GAMMA_R_Y0E field.
	ISP_GAMMA_RY4_GAMMA_R_Y0E_Msk = 0xff00
	// Position of GAMMA_R_Y0D field.
	ISP_GAMMA_RY4_GAMMA_R_Y0D_Pos = 0x10
	// Bit mask of GAMMA_R_Y0D field.
	ISP_GAMMA_RY4_GAMMA_R_Y0D_Msk = 0xff0000
	// Position of GAMMA_R_Y0C field.
	ISP_GAMMA_RY4_GAMMA_R_Y0C_Pos = 0x18
	// Bit mask of GAMMA_R_Y0C field.
	ISP_GAMMA_RY4_GAMMA_R_Y0C_Msk = 0xff000000

	// GAMMA_GY1: point of Y-axis of g channel gamma curve register 1
	// Position of GAMMA_G_Y03 field.
	ISP_GAMMA_GY1_GAMMA_G_Y03_Pos = 0x0
	// Bit mask of GAMMA_G_Y03 field.
	ISP_GAMMA_GY1_GAMMA_G_Y03_Msk = 0xff
	// Position of GAMMA_G_Y02 field.
	ISP_GAMMA_GY1_GAMMA_G_Y02_Pos = 0x8
	// Bit mask of GAMMA_G_Y02 field.
	ISP_GAMMA_GY1_GAMMA_G_Y02_Msk = 0xff00
	// Position of GAMMA_G_Y01 field.
	ISP_GAMMA_GY1_GAMMA_G_Y01_Pos = 0x10
	// Bit mask of GAMMA_G_Y01 field.
	ISP_GAMMA_GY1_GAMMA_G_Y01_Msk = 0xff0000
	// Position of GAMMA_G_Y00 field.
	ISP_GAMMA_GY1_GAMMA_G_Y00_Pos = 0x18
	// Bit mask of GAMMA_G_Y00 field.
	ISP_GAMMA_GY1_GAMMA_G_Y00_Msk = 0xff000000

	// GAMMA_GY2: point of Y-axis of g channel gamma curve register 2
	// Position of GAMMA_G_Y07 field.
	ISP_GAMMA_GY2_GAMMA_G_Y07_Pos = 0x0
	// Bit mask of GAMMA_G_Y07 field.
	ISP_GAMMA_GY2_GAMMA_G_Y07_Msk = 0xff
	// Position of GAMMA_G_Y06 field.
	ISP_GAMMA_GY2_GAMMA_G_Y06_Pos = 0x8
	// Bit mask of GAMMA_G_Y06 field.
	ISP_GAMMA_GY2_GAMMA_G_Y06_Msk = 0xff00
	// Position of GAMMA_G_Y05 field.
	ISP_GAMMA_GY2_GAMMA_G_Y05_Pos = 0x10
	// Bit mask of GAMMA_G_Y05 field.
	ISP_GAMMA_GY2_GAMMA_G_Y05_Msk = 0xff0000
	// Position of GAMMA_G_Y04 field.
	ISP_GAMMA_GY2_GAMMA_G_Y04_Pos = 0x18
	// Bit mask of GAMMA_G_Y04 field.
	ISP_GAMMA_GY2_GAMMA_G_Y04_Msk = 0xff000000

	// GAMMA_GY3: point of Y-axis of g channel gamma curve register 3
	// Position of GAMMA_G_Y0B field.
	ISP_GAMMA_GY3_GAMMA_G_Y0B_Pos = 0x0
	// Bit mask of GAMMA_G_Y0B field.
	ISP_GAMMA_GY3_GAMMA_G_Y0B_Msk = 0xff
	// Position of GAMMA_G_Y0A field.
	ISP_GAMMA_GY3_GAMMA_G_Y0A_Pos = 0x8
	// Bit mask of GAMMA_G_Y0A field.
	ISP_GAMMA_GY3_GAMMA_G_Y0A_Msk = 0xff00
	// Position of GAMMA_G_Y09 field.
	ISP_GAMMA_GY3_GAMMA_G_Y09_Pos = 0x10
	// Bit mask of GAMMA_G_Y09 field.
	ISP_GAMMA_GY3_GAMMA_G_Y09_Msk = 0xff0000
	// Position of GAMMA_G_Y08 field.
	ISP_GAMMA_GY3_GAMMA_G_Y08_Pos = 0x18
	// Bit mask of GAMMA_G_Y08 field.
	ISP_GAMMA_GY3_GAMMA_G_Y08_Msk = 0xff000000

	// GAMMA_GY4: point of Y-axis of g channel gamma curve register 4
	// Position of GAMMA_G_Y0F field.
	ISP_GAMMA_GY4_GAMMA_G_Y0F_Pos = 0x0
	// Bit mask of GAMMA_G_Y0F field.
	ISP_GAMMA_GY4_GAMMA_G_Y0F_Msk = 0xff
	// Position of GAMMA_G_Y0E field.
	ISP_GAMMA_GY4_GAMMA_G_Y0E_Pos = 0x8
	// Bit mask of GAMMA_G_Y0E field.
	ISP_GAMMA_GY4_GAMMA_G_Y0E_Msk = 0xff00
	// Position of GAMMA_G_Y0D field.
	ISP_GAMMA_GY4_GAMMA_G_Y0D_Pos = 0x10
	// Bit mask of GAMMA_G_Y0D field.
	ISP_GAMMA_GY4_GAMMA_G_Y0D_Msk = 0xff0000
	// Position of GAMMA_G_Y0C field.
	ISP_GAMMA_GY4_GAMMA_G_Y0C_Pos = 0x18
	// Bit mask of GAMMA_G_Y0C field.
	ISP_GAMMA_GY4_GAMMA_G_Y0C_Msk = 0xff000000

	// GAMMA_BY1: point of Y-axis of b channel gamma curve register 1
	// Position of GAMMA_B_Y03 field.
	ISP_GAMMA_BY1_GAMMA_B_Y03_Pos = 0x0
	// Bit mask of GAMMA_B_Y03 field.
	ISP_GAMMA_BY1_GAMMA_B_Y03_Msk = 0xff
	// Position of GAMMA_B_Y02 field.
	ISP_GAMMA_BY1_GAMMA_B_Y02_Pos = 0x8
	// Bit mask of GAMMA_B_Y02 field.
	ISP_GAMMA_BY1_GAMMA_B_Y02_Msk = 0xff00
	// Position of GAMMA_B_Y01 field.
	ISP_GAMMA_BY1_GAMMA_B_Y01_Pos = 0x10
	// Bit mask of GAMMA_B_Y01 field.
	ISP_GAMMA_BY1_GAMMA_B_Y01_Msk = 0xff0000
	// Position of GAMMA_B_Y00 field.
	ISP_GAMMA_BY1_GAMMA_B_Y00_Pos = 0x18
	// Bit mask of GAMMA_B_Y00 field.
	ISP_GAMMA_BY1_GAMMA_B_Y00_Msk = 0xff000000

	// GAMMA_BY2: point of Y-axis of b channel gamma curve register 2
	// Position of GAMMA_B_Y07 field.
	ISP_GAMMA_BY2_GAMMA_B_Y07_Pos = 0x0
	// Bit mask of GAMMA_B_Y07 field.
	ISP_GAMMA_BY2_GAMMA_B_Y07_Msk = 0xff
	// Position of GAMMA_B_Y06 field.
	ISP_GAMMA_BY2_GAMMA_B_Y06_Pos = 0x8
	// Bit mask of GAMMA_B_Y06 field.
	ISP_GAMMA_BY2_GAMMA_B_Y06_Msk = 0xff00
	// Position of GAMMA_B_Y05 field.
	ISP_GAMMA_BY2_GAMMA_B_Y05_Pos = 0x10
	// Bit mask of GAMMA_B_Y05 field.
	ISP_GAMMA_BY2_GAMMA_B_Y05_Msk = 0xff0000
	// Position of GAMMA_B_Y04 field.
	ISP_GAMMA_BY2_GAMMA_B_Y04_Pos = 0x18
	// Bit mask of GAMMA_B_Y04 field.
	ISP_GAMMA_BY2_GAMMA_B_Y04_Msk = 0xff000000

	// GAMMA_BY3: point of Y-axis of b channel gamma curve register 3
	// Position of GAMMA_B_Y0B field.
	ISP_GAMMA_BY3_GAMMA_B_Y0B_Pos = 0x0
	// Bit mask of GAMMA_B_Y0B field.
	ISP_GAMMA_BY3_GAMMA_B_Y0B_Msk = 0xff
	// Position of GAMMA_B_Y0A field.
	ISP_GAMMA_BY3_GAMMA_B_Y0A_Pos = 0x8
	// Bit mask of GAMMA_B_Y0A field.
	ISP_GAMMA_BY3_GAMMA_B_Y0A_Msk = 0xff00
	// Position of GAMMA_B_Y09 field.
	ISP_GAMMA_BY3_GAMMA_B_Y09_Pos = 0x10
	// Bit mask of GAMMA_B_Y09 field.
	ISP_GAMMA_BY3_GAMMA_B_Y09_Msk = 0xff0000
	// Position of GAMMA_B_Y08 field.
	ISP_GAMMA_BY3_GAMMA_B_Y08_Pos = 0x18
	// Bit mask of GAMMA_B_Y08 field.
	ISP_GAMMA_BY3_GAMMA_B_Y08_Msk = 0xff000000

	// GAMMA_BY4: point of Y-axis of b channel gamma curve register 4
	// Position of GAMMA_B_Y0F field.
	ISP_GAMMA_BY4_GAMMA_B_Y0F_Pos = 0x0
	// Bit mask of GAMMA_B_Y0F field.
	ISP_GAMMA_BY4_GAMMA_B_Y0F_Msk = 0xff
	// Position of GAMMA_B_Y0E field.
	ISP_GAMMA_BY4_GAMMA_B_Y0E_Pos = 0x8
	// Bit mask of GAMMA_B_Y0E field.
	ISP_GAMMA_BY4_GAMMA_B_Y0E_Msk = 0xff00
	// Position of GAMMA_B_Y0D field.
	ISP_GAMMA_BY4_GAMMA_B_Y0D_Pos = 0x10
	// Bit mask of GAMMA_B_Y0D field.
	ISP_GAMMA_BY4_GAMMA_B_Y0D_Msk = 0xff0000
	// Position of GAMMA_B_Y0C field.
	ISP_GAMMA_BY4_GAMMA_B_Y0C_Pos = 0x18
	// Bit mask of GAMMA_B_Y0C field.
	ISP_GAMMA_BY4_GAMMA_B_Y0C_Msk = 0xff000000

	// GAMMA_RX1: point of X-axis of r channel gamma curve register 1
	// Position of GAMMA_R_X07 field.
	ISP_GAMMA_RX1_GAMMA_R_X07_Pos = 0x0
	// Bit mask of GAMMA_R_X07 field.
	ISP_GAMMA_RX1_GAMMA_R_X07_Msk = 0x7
	// Position of GAMMA_R_X06 field.
	ISP_GAMMA_RX1_GAMMA_R_X06_Pos = 0x3
	// Bit mask of GAMMA_R_X06 field.
	ISP_GAMMA_RX1_GAMMA_R_X06_Msk = 0x38
	// Position of GAMMA_R_X05 field.
	ISP_GAMMA_RX1_GAMMA_R_X05_Pos = 0x6
	// Bit mask of GAMMA_R_X05 field.
	ISP_GAMMA_RX1_GAMMA_R_X05_Msk = 0x1c0
	// Position of GAMMA_R_X04 field.
	ISP_GAMMA_RX1_GAMMA_R_X04_Pos = 0x9
	// Bit mask of GAMMA_R_X04 field.
	ISP_GAMMA_RX1_GAMMA_R_X04_Msk = 0xe00
	// Position of GAMMA_R_X03 field.
	ISP_GAMMA_RX1_GAMMA_R_X03_Pos = 0xc
	// Bit mask of GAMMA_R_X03 field.
	ISP_GAMMA_RX1_GAMMA_R_X03_Msk = 0x7000
	// Position of GAMMA_R_X02 field.
	ISP_GAMMA_RX1_GAMMA_R_X02_Pos = 0xf
	// Bit mask of GAMMA_R_X02 field.
	ISP_GAMMA_RX1_GAMMA_R_X02_Msk = 0x38000
	// Position of GAMMA_R_X01 field.
	ISP_GAMMA_RX1_GAMMA_R_X01_Pos = 0x12
	// Bit mask of GAMMA_R_X01 field.
	ISP_GAMMA_RX1_GAMMA_R_X01_Msk = 0x1c0000
	// Position of GAMMA_R_X00 field.
	ISP_GAMMA_RX1_GAMMA_R_X00_Pos = 0x15
	// Bit mask of GAMMA_R_X00 field.
	ISP_GAMMA_RX1_GAMMA_R_X00_Msk = 0xe00000

	// GAMMA_RX2: point of X-axis of r channel gamma curve register 2
	// Position of GAMMA_R_X0F field.
	ISP_GAMMA_RX2_GAMMA_R_X0F_Pos = 0x0
	// Bit mask of GAMMA_R_X0F field.
	ISP_GAMMA_RX2_GAMMA_R_X0F_Msk = 0x7
	// Position of GAMMA_R_X0E field.
	ISP_GAMMA_RX2_GAMMA_R_X0E_Pos = 0x3
	// Bit mask of GAMMA_R_X0E field.
	ISP_GAMMA_RX2_GAMMA_R_X0E_Msk = 0x38
	// Position of GAMMA_R_X0D field.
	ISP_GAMMA_RX2_GAMMA_R_X0D_Pos = 0x6
	// Bit mask of GAMMA_R_X0D field.
	ISP_GAMMA_RX2_GAMMA_R_X0D_Msk = 0x1c0
	// Position of GAMMA_R_X0C field.
	ISP_GAMMA_RX2_GAMMA_R_X0C_Pos = 0x9
	// Bit mask of GAMMA_R_X0C field.
	ISP_GAMMA_RX2_GAMMA_R_X0C_Msk = 0xe00
	// Position of GAMMA_R_X0B field.
	ISP_GAMMA_RX2_GAMMA_R_X0B_Pos = 0xc
	// Bit mask of GAMMA_R_X0B field.
	ISP_GAMMA_RX2_GAMMA_R_X0B_Msk = 0x7000
	// Position of GAMMA_R_X0A field.
	ISP_GAMMA_RX2_GAMMA_R_X0A_Pos = 0xf
	// Bit mask of GAMMA_R_X0A field.
	ISP_GAMMA_RX2_GAMMA_R_X0A_Msk = 0x38000
	// Position of GAMMA_R_X09 field.
	ISP_GAMMA_RX2_GAMMA_R_X09_Pos = 0x12
	// Bit mask of GAMMA_R_X09 field.
	ISP_GAMMA_RX2_GAMMA_R_X09_Msk = 0x1c0000
	// Position of GAMMA_R_X08 field.
	ISP_GAMMA_RX2_GAMMA_R_X08_Pos = 0x15
	// Bit mask of GAMMA_R_X08 field.
	ISP_GAMMA_RX2_GAMMA_R_X08_Msk = 0xe00000

	// GAMMA_GX1: point of X-axis of g channel gamma curve register 1
	// Position of GAMMA_G_X07 field.
	ISP_GAMMA_GX1_GAMMA_G_X07_Pos = 0x0
	// Bit mask of GAMMA_G_X07 field.
	ISP_GAMMA_GX1_GAMMA_G_X07_Msk = 0x7
	// Position of GAMMA_G_X06 field.
	ISP_GAMMA_GX1_GAMMA_G_X06_Pos = 0x3
	// Bit mask of GAMMA_G_X06 field.
	ISP_GAMMA_GX1_GAMMA_G_X06_Msk = 0x38
	// Position of GAMMA_G_X05 field.
	ISP_GAMMA_GX1_GAMMA_G_X05_Pos = 0x6
	// Bit mask of GAMMA_G_X05 field.
	ISP_GAMMA_GX1_GAMMA_G_X05_Msk = 0x1c0
	// Position of GAMMA_G_X04 field.
	ISP_GAMMA_GX1_GAMMA_G_X04_Pos = 0x9
	// Bit mask of GAMMA_G_X04 field.
	ISP_GAMMA_GX1_GAMMA_G_X04_Msk = 0xe00
	// Position of GAMMA_G_X03 field.
	ISP_GAMMA_GX1_GAMMA_G_X03_Pos = 0xc
	// Bit mask of GAMMA_G_X03 field.
	ISP_GAMMA_GX1_GAMMA_G_X03_Msk = 0x7000
	// Position of GAMMA_G_X02 field.
	ISP_GAMMA_GX1_GAMMA_G_X02_Pos = 0xf
	// Bit mask of GAMMA_G_X02 field.
	ISP_GAMMA_GX1_GAMMA_G_X02_Msk = 0x38000
	// Position of GAMMA_G_X01 field.
	ISP_GAMMA_GX1_GAMMA_G_X01_Pos = 0x12
	// Bit mask of GAMMA_G_X01 field.
	ISP_GAMMA_GX1_GAMMA_G_X01_Msk = 0x1c0000
	// Position of GAMMA_G_X00 field.
	ISP_GAMMA_GX1_GAMMA_G_X00_Pos = 0x15
	// Bit mask of GAMMA_G_X00 field.
	ISP_GAMMA_GX1_GAMMA_G_X00_Msk = 0xe00000

	// GAMMA_GX2: point of X-axis of g channel gamma curve register 2
	// Position of GAMMA_G_X0F field.
	ISP_GAMMA_GX2_GAMMA_G_X0F_Pos = 0x0
	// Bit mask of GAMMA_G_X0F field.
	ISP_GAMMA_GX2_GAMMA_G_X0F_Msk = 0x7
	// Position of GAMMA_G_X0E field.
	ISP_GAMMA_GX2_GAMMA_G_X0E_Pos = 0x3
	// Bit mask of GAMMA_G_X0E field.
	ISP_GAMMA_GX2_GAMMA_G_X0E_Msk = 0x38
	// Position of GAMMA_G_X0D field.
	ISP_GAMMA_GX2_GAMMA_G_X0D_Pos = 0x6
	// Bit mask of GAMMA_G_X0D field.
	ISP_GAMMA_GX2_GAMMA_G_X0D_Msk = 0x1c0
	// Position of GAMMA_G_X0C field.
	ISP_GAMMA_GX2_GAMMA_G_X0C_Pos = 0x9
	// Bit mask of GAMMA_G_X0C field.
	ISP_GAMMA_GX2_GAMMA_G_X0C_Msk = 0xe00
	// Position of GAMMA_G_X0B field.
	ISP_GAMMA_GX2_GAMMA_G_X0B_Pos = 0xc
	// Bit mask of GAMMA_G_X0B field.
	ISP_GAMMA_GX2_GAMMA_G_X0B_Msk = 0x7000
	// Position of GAMMA_G_X0A field.
	ISP_GAMMA_GX2_GAMMA_G_X0A_Pos = 0xf
	// Bit mask of GAMMA_G_X0A field.
	ISP_GAMMA_GX2_GAMMA_G_X0A_Msk = 0x38000
	// Position of GAMMA_G_X09 field.
	ISP_GAMMA_GX2_GAMMA_G_X09_Pos = 0x12
	// Bit mask of GAMMA_G_X09 field.
	ISP_GAMMA_GX2_GAMMA_G_X09_Msk = 0x1c0000
	// Position of GAMMA_G_X08 field.
	ISP_GAMMA_GX2_GAMMA_G_X08_Pos = 0x15
	// Bit mask of GAMMA_G_X08 field.
	ISP_GAMMA_GX2_GAMMA_G_X08_Msk = 0xe00000

	// GAMMA_BX1: point of X-axis of b channel gamma curve register 1
	// Position of GAMMA_B_X07 field.
	ISP_GAMMA_BX1_GAMMA_B_X07_Pos = 0x0
	// Bit mask of GAMMA_B_X07 field.
	ISP_GAMMA_BX1_GAMMA_B_X07_Msk = 0x7
	// Position of GAMMA_B_X06 field.
	ISP_GAMMA_BX1_GAMMA_B_X06_Pos = 0x3
	// Bit mask of GAMMA_B_X06 field.
	ISP_GAMMA_BX1_GAMMA_B_X06_Msk = 0x38
	// Position of GAMMA_B_X05 field.
	ISP_GAMMA_BX1_GAMMA_B_X05_Pos = 0x6
	// Bit mask of GAMMA_B_X05 field.
	ISP_GAMMA_BX1_GAMMA_B_X05_Msk = 0x1c0
	// Position of GAMMA_B_X04 field.
	ISP_GAMMA_BX1_GAMMA_B_X04_Pos = 0x9
	// Bit mask of GAMMA_B_X04 field.
	ISP_GAMMA_BX1_GAMMA_B_X04_Msk = 0xe00
	// Position of GAMMA_B_X03 field.
	ISP_GAMMA_BX1_GAMMA_B_X03_Pos = 0xc
	// Bit mask of GAMMA_B_X03 field.
	ISP_GAMMA_BX1_GAMMA_B_X03_Msk = 0x7000
	// Position of GAMMA_B_X02 field.
	ISP_GAMMA_BX1_GAMMA_B_X02_Pos = 0xf
	// Bit mask of GAMMA_B_X02 field.
	ISP_GAMMA_BX1_GAMMA_B_X02_Msk = 0x38000
	// Position of GAMMA_B_X01 field.
	ISP_GAMMA_BX1_GAMMA_B_X01_Pos = 0x12
	// Bit mask of GAMMA_B_X01 field.
	ISP_GAMMA_BX1_GAMMA_B_X01_Msk = 0x1c0000
	// Position of GAMMA_B_X00 field.
	ISP_GAMMA_BX1_GAMMA_B_X00_Pos = 0x15
	// Bit mask of GAMMA_B_X00 field.
	ISP_GAMMA_BX1_GAMMA_B_X00_Msk = 0xe00000

	// GAMMA_BX2: point of X-axis of b channel gamma curve register 2
	// Position of GAMMA_B_X0F field.
	ISP_GAMMA_BX2_GAMMA_B_X0F_Pos = 0x0
	// Bit mask of GAMMA_B_X0F field.
	ISP_GAMMA_BX2_GAMMA_B_X0F_Msk = 0x7
	// Position of GAMMA_B_X0E field.
	ISP_GAMMA_BX2_GAMMA_B_X0E_Pos = 0x3
	// Bit mask of GAMMA_B_X0E field.
	ISP_GAMMA_BX2_GAMMA_B_X0E_Msk = 0x38
	// Position of GAMMA_B_X0D field.
	ISP_GAMMA_BX2_GAMMA_B_X0D_Pos = 0x6
	// Bit mask of GAMMA_B_X0D field.
	ISP_GAMMA_BX2_GAMMA_B_X0D_Msk = 0x1c0
	// Position of GAMMA_B_X0C field.
	ISP_GAMMA_BX2_GAMMA_B_X0C_Pos = 0x9
	// Bit mask of GAMMA_B_X0C field.
	ISP_GAMMA_BX2_GAMMA_B_X0C_Msk = 0xe00
	// Position of GAMMA_B_X0B field.
	ISP_GAMMA_BX2_GAMMA_B_X0B_Pos = 0xc
	// Bit mask of GAMMA_B_X0B field.
	ISP_GAMMA_BX2_GAMMA_B_X0B_Msk = 0x7000
	// Position of GAMMA_B_X0A field.
	ISP_GAMMA_BX2_GAMMA_B_X0A_Pos = 0xf
	// Bit mask of GAMMA_B_X0A field.
	ISP_GAMMA_BX2_GAMMA_B_X0A_Msk = 0x38000
	// Position of GAMMA_B_X09 field.
	ISP_GAMMA_BX2_GAMMA_B_X09_Pos = 0x12
	// Bit mask of GAMMA_B_X09 field.
	ISP_GAMMA_BX2_GAMMA_B_X09_Msk = 0x1c0000
	// Position of GAMMA_B_X08 field.
	ISP_GAMMA_BX2_GAMMA_B_X08_Pos = 0x15
	// Bit mask of GAMMA_B_X08 field.
	ISP_GAMMA_BX2_GAMMA_B_X08_Msk = 0xe00000

	// AE_CTRL: ae control register
	// Position of AE_UPDATE field.
	ISP_AE_CTRL_AE_UPDATE_Pos = 0x0
	// Bit mask of AE_UPDATE field.
	ISP_AE_CTRL_AE_UPDATE_Msk = 0x1
	// Bit AE_UPDATE.
	ISP_AE_CTRL_AE_UPDATE = 0x1
	// Position of AE_SELECT field.
	ISP_AE_CTRL_AE_SELECT_Pos = 0x1
	// Bit mask of AE_SELECT field.
	ISP_AE_CTRL_AE_SELECT_Msk = 0x2
	// Bit AE_SELECT.
	ISP_AE_CTRL_AE_SELECT = 0x2

	// AE_MONITOR: ae monitor control register
	// Position of TL field.
	ISP_AE_MONITOR_TL_Pos = 0x0
	// Bit mask of TL field.
	ISP_AE_MONITOR_TL_Msk = 0xff
	// Position of TH field.
	ISP_AE_MONITOR_TH_Pos = 0x8
	// Bit mask of TH field.
	ISP_AE_MONITOR_TH_Msk = 0xff00
	// Position of PERIOD field.
	ISP_AE_MONITOR_PERIOD_Pos = 0x10
	// Bit mask of PERIOD field.
	ISP_AE_MONITOR_PERIOD_Msk = 0x3f0000

	// AE_BX: ae window register in x-direction
	// Position of AE_X_BSIZE field.
	ISP_AE_BX_AE_X_BSIZE_Pos = 0x0
	// Bit mask of AE_X_BSIZE field.
	ISP_AE_BX_AE_X_BSIZE_Msk = 0x7ff
	// Position of AE_X_START field.
	ISP_AE_BX_AE_X_START_Pos = 0xb
	// Bit mask of AE_X_START field.
	ISP_AE_BX_AE_X_START_Msk = 0x3ff800

	// AE_BY: ae window register in y-direction
	// Position of AE_Y_BSIZE field.
	ISP_AE_BY_AE_Y_BSIZE_Pos = 0x0
	// Bit mask of AE_Y_BSIZE field.
	ISP_AE_BY_AE_Y_BSIZE_Msk = 0x7ff
	// Position of AE_Y_START field.
	ISP_AE_BY_AE_Y_START_Pos = 0xb
	// Bit mask of AE_Y_START field.
	ISP_AE_BY_AE_Y_START_Msk = 0x3ff800

	// AE_WINPIXNUM: ae sub-window pix num register
	// Position of AE_SUBWIN_PIXNUM field.
	ISP_AE_WINPIXNUM_AE_SUBWIN_PIXNUM_Pos = 0x0
	// Bit mask of AE_SUBWIN_PIXNUM field.
	ISP_AE_WINPIXNUM_AE_SUBWIN_PIXNUM_Msk = 0x1ffff

	// AE_WIN_RECIPROCAL: reciprocal of ae sub-window pixel number
	// Position of AE_SUBWIN_RECIP field.
	ISP_AE_WIN_RECIPROCAL_AE_SUBWIN_RECIP_Pos = 0x0
	// Bit mask of AE_SUBWIN_RECIP field.
	ISP_AE_WIN_RECIPROCAL_AE_SUBWIN_RECIP_Msk = 0xfffff

	// AE_BLOCK_MEAN_0: ae statistic result register 0
	// Position of AE_B03_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B03_MEAN_Pos = 0x0
	// Bit mask of AE_B03_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B03_MEAN_Msk = 0xff
	// Position of AE_B02_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B02_MEAN_Pos = 0x8
	// Bit mask of AE_B02_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B02_MEAN_Msk = 0xff00
	// Position of AE_B01_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B01_MEAN_Pos = 0x10
	// Bit mask of AE_B01_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B01_MEAN_Msk = 0xff0000
	// Position of AE_B00_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B00_MEAN_Pos = 0x18
	// Bit mask of AE_B00_MEAN field.
	ISP_AE_BLOCK_MEAN_0_AE_B00_MEAN_Msk = 0xff000000

	// AE_BLOCK_MEAN_1: ae statistic result register 1
	// Position of AE_B12_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B12_MEAN_Pos = 0x0
	// Bit mask of AE_B12_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B12_MEAN_Msk = 0xff
	// Position of AE_B11_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B11_MEAN_Pos = 0x8
	// Bit mask of AE_B11_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B11_MEAN_Msk = 0xff00
	// Position of AE_B10_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B10_MEAN_Pos = 0x10
	// Bit mask of AE_B10_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B10_MEAN_Msk = 0xff0000
	// Position of AE_B04_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B04_MEAN_Pos = 0x18
	// Bit mask of AE_B04_MEAN field.
	ISP_AE_BLOCK_MEAN_1_AE_B04_MEAN_Msk = 0xff000000

	// AE_BLOCK_MEAN_2: ae statistic result register 2
	// Position of AE_B21_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B21_MEAN_Pos = 0x0
	// Bit mask of AE_B21_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B21_MEAN_Msk = 0xff
	// Position of AE_B20_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B20_MEAN_Pos = 0x8
	// Bit mask of AE_B20_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B20_MEAN_Msk = 0xff00
	// Position of AE_B14_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B14_MEAN_Pos = 0x10
	// Bit mask of AE_B14_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B14_MEAN_Msk = 0xff0000
	// Position of AE_B13_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B13_MEAN_Pos = 0x18
	// Bit mask of AE_B13_MEAN field.
	ISP_AE_BLOCK_MEAN_2_AE_B13_MEAN_Msk = 0xff000000

	// AE_BLOCK_MEAN_3: ae statistic result register 3
	// Position of AE_B30_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B30_MEAN_Pos = 0x0
	// Bit mask of AE_B30_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B30_MEAN_Msk = 0xff
	// Position of AE_B24_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B24_MEAN_Pos = 0x8
	// Bit mask of AE_B24_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B24_MEAN_Msk = 0xff00
	// Position of AE_B23_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B23_MEAN_Pos = 0x10
	// Bit mask of AE_B23_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B23_MEAN_Msk = 0xff0000
	// Position of AE_B22_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B22_MEAN_Pos = 0x18
	// Bit mask of AE_B22_MEAN field.
	ISP_AE_BLOCK_MEAN_3_AE_B22_MEAN_Msk = 0xff000000

	// AE_BLOCK_MEAN_4: ae statistic result register 4
	// Position of AE_B34_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B34_MEAN_Pos = 0x0
	// Bit mask of AE_B34_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B34_MEAN_Msk = 0xff
	// Position of AE_B33_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B33_MEAN_Pos = 0x8
	// Bit mask of AE_B33_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B33_MEAN_Msk = 0xff00
	// Position of AE_B32_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B32_MEAN_Pos = 0x10
	// Bit mask of AE_B32_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B32_MEAN_Msk = 0xff0000
	// Position of AE_B31_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B31_MEAN_Pos = 0x18
	// Bit mask of AE_B31_MEAN field.
	ISP_AE_BLOCK_MEAN_4_AE_B31_MEAN_Msk = 0xff000000

	// AE_BLOCK_MEAN_5: ae statistic result register 5
	// Position of AE_B43_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B43_MEAN_Pos = 0x0
	// Bit mask of AE_B43_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B43_MEAN_Msk = 0xff
	// Position of AE_B42_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B42_MEAN_Pos = 0x8
	// Bit mask of AE_B42_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B42_MEAN_Msk = 0xff00
	// Position of AE_B41_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B41_MEAN_Pos = 0x10
	// Bit mask of AE_B41_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B41_MEAN_Msk = 0xff0000
	// Position of AE_B40_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B40_MEAN_Pos = 0x18
	// Bit mask of AE_B40_MEAN field.
	ISP_AE_BLOCK_MEAN_5_AE_B40_MEAN_Msk = 0xff000000

	// AE_BLOCK_MEAN_6: ae statistic result register 6
	// Position of AE_B44_MEAN field.
	ISP_AE_BLOCK_MEAN_6_AE_B44_MEAN_Pos = 0x18
	// Bit mask of AE_B44_MEAN field.
	ISP_AE_BLOCK_MEAN_6_AE_B44_MEAN_Msk = 0xff000000

	// SHARP_CTRL0: sharp control register 0
	// Position of SHARP_THRESHOLD_LOW field.
	ISP_SHARP_CTRL0_SHARP_THRESHOLD_LOW_Pos = 0x0
	// Bit mask of SHARP_THRESHOLD_LOW field.
	ISP_SHARP_CTRL0_SHARP_THRESHOLD_LOW_Msk = 0xff
	// Position of SHARP_THRESHOLD_HIGH field.
	ISP_SHARP_CTRL0_SHARP_THRESHOLD_HIGH_Pos = 0x8
	// Bit mask of SHARP_THRESHOLD_HIGH field.
	ISP_SHARP_CTRL0_SHARP_THRESHOLD_HIGH_Msk = 0xff00
	// Position of SHARP_AMOUNT_LOW field.
	ISP_SHARP_CTRL0_SHARP_AMOUNT_LOW_Pos = 0x10
	// Bit mask of SHARP_AMOUNT_LOW field.
	ISP_SHARP_CTRL0_SHARP_AMOUNT_LOW_Msk = 0xff0000
	// Position of SHARP_AMOUNT_HIGH field.
	ISP_SHARP_CTRL0_SHARP_AMOUNT_HIGH_Pos = 0x18
	// Bit mask of SHARP_AMOUNT_HIGH field.
	ISP_SHARP_CTRL0_SHARP_AMOUNT_HIGH_Msk = 0xff000000

	// SHARP_FILTER0: sharp usm config register 0
	// Position of SHARP_FILTER_COE00 field.
	ISP_SHARP_FILTER0_SHARP_FILTER_COE00_Pos = 0x0
	// Bit mask of SHARP_FILTER_COE00 field.
	ISP_SHARP_FILTER0_SHARP_FILTER_COE00_Msk = 0x1f
	// Position of SHARP_FILTER_COE01 field.
	ISP_SHARP_FILTER0_SHARP_FILTER_COE01_Pos = 0x5
	// Bit mask of SHARP_FILTER_COE01 field.
	ISP_SHARP_FILTER0_SHARP_FILTER_COE01_Msk = 0x3e0
	// Position of SHARP_FILTER_COE02 field.
	ISP_SHARP_FILTER0_SHARP_FILTER_COE02_Pos = 0xa
	// Bit mask of SHARP_FILTER_COE02 field.
	ISP_SHARP_FILTER0_SHARP_FILTER_COE02_Msk = 0x7c00

	// SHARP_FILTER1: sharp usm config register 1
	// Position of SHARP_FILTER_COE10 field.
	ISP_SHARP_FILTER1_SHARP_FILTER_COE10_Pos = 0x0
	// Bit mask of SHARP_FILTER_COE10 field.
	ISP_SHARP_FILTER1_SHARP_FILTER_COE10_Msk = 0x1f
	// Position of SHARP_FILTER_COE11 field.
	ISP_SHARP_FILTER1_SHARP_FILTER_COE11_Pos = 0x5
	// Bit mask of SHARP_FILTER_COE11 field.
	ISP_SHARP_FILTER1_SHARP_FILTER_COE11_Msk = 0x3e0
	// Position of SHARP_FILTER_COE12 field.
	ISP_SHARP_FILTER1_SHARP_FILTER_COE12_Pos = 0xa
	// Bit mask of SHARP_FILTER_COE12 field.
	ISP_SHARP_FILTER1_SHARP_FILTER_COE12_Msk = 0x7c00

	// SHARP_FILTER2: sharp usm config register 2
	// Position of SHARP_FILTER_COE20 field.
	ISP_SHARP_FILTER2_SHARP_FILTER_COE20_Pos = 0x0
	// Bit mask of SHARP_FILTER_COE20 field.
	ISP_SHARP_FILTER2_SHARP_FILTER_COE20_Msk = 0x1f
	// Position of SHARP_FILTER_COE21 field.
	ISP_SHARP_FILTER2_SHARP_FILTER_COE21_Pos = 0x5
	// Bit mask of SHARP_FILTER_COE21 field.
	ISP_SHARP_FILTER2_SHARP_FILTER_COE21_Msk = 0x3e0
	// Position of SHARP_FILTER_COE22 field.
	ISP_SHARP_FILTER2_SHARP_FILTER_COE22_Pos = 0xa
	// Bit mask of SHARP_FILTER_COE22 field.
	ISP_SHARP_FILTER2_SHARP_FILTER_COE22_Msk = 0x7c00

	// SHARP_MATRIX_CTRL: sharp pix2matrix ctrl
	// Position of SHARP_TAIL_PIXEN_PULSE_TL field.
	ISP_SHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TL_Pos = 0x0
	// Bit mask of SHARP_TAIL_PIXEN_PULSE_TL field.
	ISP_SHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TL_Msk = 0xff
	// Position of SHARP_TAIL_PIXEN_PULSE_TH field.
	ISP_SHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TH_Pos = 0x8
	// Bit mask of SHARP_TAIL_PIXEN_PULSE_TH field.
	ISP_SHARP_MATRIX_CTRL_SHARP_TAIL_PIXEN_PULSE_TH_Msk = 0xff00
	// Position of SHARP_PADDING_DATA field.
	ISP_SHARP_MATRIX_CTRL_SHARP_PADDING_DATA_Pos = 0x10
	// Bit mask of SHARP_PADDING_DATA field.
	ISP_SHARP_MATRIX_CTRL_SHARP_PADDING_DATA_Msk = 0xff0000
	// Position of SHARP_PADDING_MODE field.
	ISP_SHARP_MATRIX_CTRL_SHARP_PADDING_MODE_Pos = 0x18
	// Bit mask of SHARP_PADDING_MODE field.
	ISP_SHARP_MATRIX_CTRL_SHARP_PADDING_MODE_Msk = 0x1000000
	// Bit SHARP_PADDING_MODE.
	ISP_SHARP_MATRIX_CTRL_SHARP_PADDING_MODE = 0x1000000

	// SHARP_CTRL1: sharp control register 1
	// Position of SHARP_GRADIENT_MAX field.
	ISP_SHARP_CTRL1_SHARP_GRADIENT_MAX_Pos = 0x0
	// Bit mask of SHARP_GRADIENT_MAX field.
	ISP_SHARP_CTRL1_SHARP_GRADIENT_MAX_Msk = 0xff

	// DMA_CNTL: isp dma source trans control register
	// Position of DMA_EN field.
	ISP_DMA_CNTL_DMA_EN_Pos = 0x0
	// Bit mask of DMA_EN field.
	ISP_DMA_CNTL_DMA_EN_Msk = 0x1
	// Bit DMA_EN.
	ISP_DMA_CNTL_DMA_EN = 0x1
	// Position of DMA_UPDATE field.
	ISP_DMA_CNTL_DMA_UPDATE_Pos = 0x1
	// Bit mask of DMA_UPDATE field.
	ISP_DMA_CNTL_DMA_UPDATE_Msk = 0x2
	// Bit DMA_UPDATE.
	ISP_DMA_CNTL_DMA_UPDATE = 0x2
	// Position of DMA_DATA_TYPE field.
	ISP_DMA_CNTL_DMA_DATA_TYPE_Pos = 0x2
	// Bit mask of DMA_DATA_TYPE field.
	ISP_DMA_CNTL_DMA_DATA_TYPE_Msk = 0xfc
	// Position of DMA_BURST_LEN field.
	ISP_DMA_CNTL_DMA_BURST_LEN_Pos = 0x8
	// Bit mask of DMA_BURST_LEN field.
	ISP_DMA_CNTL_DMA_BURST_LEN_Msk = 0xfff00
	// Position of DMA_INTERVAL field.
	ISP_DMA_CNTL_DMA_INTERVAL_Pos = 0x14
	// Bit mask of DMA_INTERVAL field.
	ISP_DMA_CNTL_DMA_INTERVAL_Msk = 0xfff00000

	// DMA_RAW_DATA: isp dma source total raw number set register
	// Position of DMA_RAW_NUM_TOTAL field.
	ISP_DMA_RAW_DATA_DMA_RAW_NUM_TOTAL_Pos = 0x0
	// Bit mask of DMA_RAW_NUM_TOTAL field.
	ISP_DMA_RAW_DATA_DMA_RAW_NUM_TOTAL_Msk = 0x3fffff
	// Position of DMA_RAW_NUM_TOTAL_SET field.
	ISP_DMA_RAW_DATA_DMA_RAW_NUM_TOTAL_SET_Pos = 0x1f
	// Bit mask of DMA_RAW_NUM_TOTAL_SET field.
	ISP_DMA_RAW_DATA_DMA_RAW_NUM_TOTAL_SET_Msk = 0x80000000
	// Bit DMA_RAW_NUM_TOTAL_SET.
	ISP_DMA_RAW_DATA_DMA_RAW_NUM_TOTAL_SET = 0x80000000

	// CAM_CNTL: isp cam source control register
	// Position of CAM_EN field.
	ISP_CAM_CNTL_CAM_EN_Pos = 0x0
	// Bit mask of CAM_EN field.
	ISP_CAM_CNTL_CAM_EN_Msk = 0x1
	// Bit CAM_EN.
	ISP_CAM_CNTL_CAM_EN = 0x1
	// Position of CAM_UPDATE field.
	ISP_CAM_CNTL_CAM_UPDATE_Pos = 0x1
	// Bit mask of CAM_UPDATE field.
	ISP_CAM_CNTL_CAM_UPDATE_Msk = 0x2
	// Bit CAM_UPDATE.
	ISP_CAM_CNTL_CAM_UPDATE = 0x2
	// Position of CAM_RESET field.
	ISP_CAM_CNTL_CAM_RESET_Pos = 0x2
	// Bit mask of CAM_RESET field.
	ISP_CAM_CNTL_CAM_RESET_Msk = 0x4
	// Bit CAM_RESET.
	ISP_CAM_CNTL_CAM_RESET = 0x4
	// Position of CAM_CLK_INV field.
	ISP_CAM_CNTL_CAM_CLK_INV_Pos = 0x3
	// Bit mask of CAM_CLK_INV field.
	ISP_CAM_CNTL_CAM_CLK_INV_Msk = 0x8
	// Bit CAM_CLK_INV.
	ISP_CAM_CNTL_CAM_CLK_INV = 0x8

	// CAM_CONF: isp cam source config register
	// Position of CAM_DATA_ORDER field.
	ISP_CAM_CONF_CAM_DATA_ORDER_Pos = 0x0
	// Bit mask of CAM_DATA_ORDER field.
	ISP_CAM_CONF_CAM_DATA_ORDER_Msk = 0x1
	// Bit CAM_DATA_ORDER.
	ISP_CAM_CONF_CAM_DATA_ORDER = 0x1
	// Position of CAM_2BYTE_MODE field.
	ISP_CAM_CONF_CAM_2BYTE_MODE_Pos = 0x1
	// Bit mask of CAM_2BYTE_MODE field.
	ISP_CAM_CONF_CAM_2BYTE_MODE_Msk = 0x2
	// Bit CAM_2BYTE_MODE.
	ISP_CAM_CONF_CAM_2BYTE_MODE = 0x2
	// Position of CAM_DATA_TYPE field.
	ISP_CAM_CONF_CAM_DATA_TYPE_Pos = 0x2
	// Bit mask of CAM_DATA_TYPE field.
	ISP_CAM_CONF_CAM_DATA_TYPE_Msk = 0xfc
	// Position of CAM_DE_INV field.
	ISP_CAM_CONF_CAM_DE_INV_Pos = 0x8
	// Bit mask of CAM_DE_INV field.
	ISP_CAM_CONF_CAM_DE_INV_Msk = 0x100
	// Bit CAM_DE_INV.
	ISP_CAM_CONF_CAM_DE_INV = 0x100
	// Position of CAM_HSYNC_INV field.
	ISP_CAM_CONF_CAM_HSYNC_INV_Pos = 0x9
	// Bit mask of CAM_HSYNC_INV field.
	ISP_CAM_CONF_CAM_HSYNC_INV_Msk = 0x200
	// Bit CAM_HSYNC_INV.
	ISP_CAM_CONF_CAM_HSYNC_INV = 0x200
	// Position of CAM_VSYNC_INV field.
	ISP_CAM_CONF_CAM_VSYNC_INV_Pos = 0xa
	// Bit mask of CAM_VSYNC_INV field.
	ISP_CAM_CONF_CAM_VSYNC_INV_Msk = 0x400
	// Bit CAM_VSYNC_INV.
	ISP_CAM_CONF_CAM_VSYNC_INV = 0x400
	// Position of CAM_VSYNC_FILTER_THRES field.
	ISP_CAM_CONF_CAM_VSYNC_FILTER_THRES_Pos = 0xb
	// Bit mask of CAM_VSYNC_FILTER_THRES field.
	ISP_CAM_CONF_CAM_VSYNC_FILTER_THRES_Msk = 0x3800
	// Position of CAM_VSYNC_FILTER_EN field.
	ISP_CAM_CONF_CAM_VSYNC_FILTER_EN_Pos = 0xe
	// Bit mask of CAM_VSYNC_FILTER_EN field.
	ISP_CAM_CONF_CAM_VSYNC_FILTER_EN_Msk = 0x4000
	// Bit CAM_VSYNC_FILTER_EN.
	ISP_CAM_CONF_CAM_VSYNC_FILTER_EN = 0x4000

	// AF_CTRL0: af control register 0
	// Position of AF_AUTO_UPDATE field.
	ISP_AF_CTRL0_AF_AUTO_UPDATE_Pos = 0x0
	// Bit mask of AF_AUTO_UPDATE field.
	ISP_AF_CTRL0_AF_AUTO_UPDATE_Msk = 0x1
	// Bit AF_AUTO_UPDATE.
	ISP_AF_CTRL0_AF_AUTO_UPDATE = 0x1
	// Position of AF_MANUAL_UPDATE field.
	ISP_AF_CTRL0_AF_MANUAL_UPDATE_Pos = 0x4
	// Bit mask of AF_MANUAL_UPDATE field.
	ISP_AF_CTRL0_AF_MANUAL_UPDATE_Msk = 0x10
	// Bit AF_MANUAL_UPDATE.
	ISP_AF_CTRL0_AF_MANUAL_UPDATE = 0x10
	// Position of AF_ENV_THRESHOLD field.
	ISP_AF_CTRL0_AF_ENV_THRESHOLD_Pos = 0x8
	// Bit mask of AF_ENV_THRESHOLD field.
	ISP_AF_CTRL0_AF_ENV_THRESHOLD_Msk = 0xf00
	// Position of AF_ENV_PERIOD field.
	ISP_AF_CTRL0_AF_ENV_PERIOD_Pos = 0x10
	// Bit mask of AF_ENV_PERIOD field.
	ISP_AF_CTRL0_AF_ENV_PERIOD_Msk = 0xff0000

	// AF_CTRL1: af control register 1
	// Position of AF_THPIXNUM field.
	ISP_AF_CTRL1_AF_THPIXNUM_Pos = 0x0
	// Bit mask of AF_THPIXNUM field.
	ISP_AF_CTRL1_AF_THPIXNUM_Msk = 0x3fffff

	// AF_GEN_TH_CTRL: af gen threshold control register
	// Position of AF_GEN_THRESHOLD_MIN field.
	ISP_AF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MIN_Pos = 0x0
	// Bit mask of AF_GEN_THRESHOLD_MIN field.
	ISP_AF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MIN_Msk = 0xffff
	// Position of AF_GEN_THRESHOLD_MAX field.
	ISP_AF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MAX_Pos = 0x10
	// Bit mask of AF_GEN_THRESHOLD_MAX field.
	ISP_AF_GEN_TH_CTRL_AF_GEN_THRESHOLD_MAX_Msk = 0xffff0000

	// AF_ENV_USER_TH_SUM: af monitor user sum threshold register
	// Position of AF_ENV_USER_THRESHOLD_SUM field.
	ISP_AF_ENV_USER_TH_SUM_AF_ENV_USER_THRESHOLD_SUM_Pos = 0x0
	// Bit mask of AF_ENV_USER_THRESHOLD_SUM field.
	ISP_AF_ENV_USER_TH_SUM_AF_ENV_USER_THRESHOLD_SUM_Msk = 0xffffffff

	// AF_ENV_USER_TH_LUM: af monitor user lum threshold register
	// Position of AF_ENV_USER_THRESHOLD_LUM field.
	ISP_AF_ENV_USER_TH_LUM_AF_ENV_USER_THRESHOLD_LUM_Pos = 0x0
	// Bit mask of AF_ENV_USER_THRESHOLD_LUM field.
	ISP_AF_ENV_USER_TH_LUM_AF_ENV_USER_THRESHOLD_LUM_Msk = 0x3fffffff

	// AF_THRESHOLD: af threshold register
	// Position of AF_THRESHOLD field.
	ISP_AF_THRESHOLD_AF_THRESHOLD_Pos = 0x0
	// Bit mask of AF_THRESHOLD field.
	ISP_AF_THRESHOLD_AF_THRESHOLD_Msk = 0xffff
	// Position of AF_GEN_THRESHOLD field.
	ISP_AF_THRESHOLD_AF_GEN_THRESHOLD_Pos = 0x10
	// Bit mask of AF_GEN_THRESHOLD field.
	ISP_AF_THRESHOLD_AF_GEN_THRESHOLD_Msk = 0xffff0000

	// AF_HSCALE_A: h-scale of af window a register
	// Position of AF_RPOINT_A field.
	ISP_AF_HSCALE_A_AF_RPOINT_A_Pos = 0x0
	// Bit mask of AF_RPOINT_A field.
	ISP_AF_HSCALE_A_AF_RPOINT_A_Msk = 0xfff
	// Position of AF_LPOINT_A field.
	ISP_AF_HSCALE_A_AF_LPOINT_A_Pos = 0x10
	// Bit mask of AF_LPOINT_A field.
	ISP_AF_HSCALE_A_AF_LPOINT_A_Msk = 0xfff0000

	// AF_VSCALE_A: v-scale of af window a register
	// Position of AF_BPOINT_A field.
	ISP_AF_VSCALE_A_AF_BPOINT_A_Pos = 0x0
	// Bit mask of AF_BPOINT_A field.
	ISP_AF_VSCALE_A_AF_BPOINT_A_Msk = 0xfff
	// Position of AF_TPOINT_A field.
	ISP_AF_VSCALE_A_AF_TPOINT_A_Pos = 0x10
	// Bit mask of AF_TPOINT_A field.
	ISP_AF_VSCALE_A_AF_TPOINT_A_Msk = 0xfff0000

	// AF_HSCALE_B: h-scale of af window b register
	// Position of AF_RPOINT_B field.
	ISP_AF_HSCALE_B_AF_RPOINT_B_Pos = 0x0
	// Bit mask of AF_RPOINT_B field.
	ISP_AF_HSCALE_B_AF_RPOINT_B_Msk = 0xfff
	// Position of AF_LPOINT_B field.
	ISP_AF_HSCALE_B_AF_LPOINT_B_Pos = 0x10
	// Bit mask of AF_LPOINT_B field.
	ISP_AF_HSCALE_B_AF_LPOINT_B_Msk = 0xfff0000

	// AF_VSCALE_B: v-scale of af window b register
	// Position of AF_BPOINT_B field.
	ISP_AF_VSCALE_B_AF_BPOINT_B_Pos = 0x0
	// Bit mask of AF_BPOINT_B field.
	ISP_AF_VSCALE_B_AF_BPOINT_B_Msk = 0xfff
	// Position of AF_TPOINT_B field.
	ISP_AF_VSCALE_B_AF_TPOINT_B_Pos = 0x10
	// Bit mask of AF_TPOINT_B field.
	ISP_AF_VSCALE_B_AF_TPOINT_B_Msk = 0xfff0000

	// AF_HSCALE_C: v-scale of af window c register
	// Position of AF_RPOINT_C field.
	ISP_AF_HSCALE_C_AF_RPOINT_C_Pos = 0x0
	// Bit mask of AF_RPOINT_C field.
	ISP_AF_HSCALE_C_AF_RPOINT_C_Msk = 0xfff
	// Position of AF_LPOINT_C field.
	ISP_AF_HSCALE_C_AF_LPOINT_C_Pos = 0x10
	// Bit mask of AF_LPOINT_C field.
	ISP_AF_HSCALE_C_AF_LPOINT_C_Msk = 0xfff0000

	// AF_VSCALE_C: v-scale of af window c register
	// Position of AF_BPOINT_C field.
	ISP_AF_VSCALE_C_AF_BPOINT_C_Pos = 0x0
	// Bit mask of AF_BPOINT_C field.
	ISP_AF_VSCALE_C_AF_BPOINT_C_Msk = 0xfff
	// Position of AF_TPOINT_C field.
	ISP_AF_VSCALE_C_AF_TPOINT_C_Pos = 0x10
	// Bit mask of AF_TPOINT_C field.
	ISP_AF_VSCALE_C_AF_TPOINT_C_Msk = 0xfff0000

	// AF_SUM_A: result of sum of af window a
	// Position of AF_SUMA field.
	ISP_AF_SUM_A_AF_SUMA_Pos = 0x0
	// Bit mask of AF_SUMA field.
	ISP_AF_SUM_A_AF_SUMA_Msk = 0x3fffffff

	// AF_SUM_B: result of sum of af window b
	// Position of AF_SUMB field.
	ISP_AF_SUM_B_AF_SUMB_Pos = 0x0
	// Bit mask of AF_SUMB field.
	ISP_AF_SUM_B_AF_SUMB_Msk = 0x3fffffff

	// AF_SUM_C: result of sum of af window c
	// Position of AF_SUMC field.
	ISP_AF_SUM_C_AF_SUMC_Pos = 0x0
	// Bit mask of AF_SUMC field.
	ISP_AF_SUM_C_AF_SUMC_Msk = 0x3fffffff

	// AF_LUM_A: result of lum of af window a
	// Position of AF_LUMA field.
	ISP_AF_LUM_A_AF_LUMA_Pos = 0x0
	// Bit mask of AF_LUMA field.
	ISP_AF_LUM_A_AF_LUMA_Msk = 0xfffffff

	// AF_LUM_B: result of lum of af window b
	// Position of AF_LUMB field.
	ISP_AF_LUM_B_AF_LUMB_Pos = 0x0
	// Bit mask of AF_LUMB field.
	ISP_AF_LUM_B_AF_LUMB_Msk = 0xfffffff

	// AF_LUM_C: result of lum of af window c
	// Position of AF_LUMC field.
	ISP_AF_LUM_C_AF_LUMC_Pos = 0x0
	// Bit mask of AF_LUMC field.
	ISP_AF_LUM_C_AF_LUMC_Msk = 0xfffffff

	// AWB_MODE: awb mode control register
	// Position of AWB_MODE field.
	ISP_AWB_MODE_AWB_MODE_Pos = 0x0
	// Bit mask of AWB_MODE field.
	ISP_AWB_MODE_AWB_MODE_Msk = 0x3
	// Position of AWB_SAMPLE field.
	ISP_AWB_MODE_AWB_SAMPLE_Pos = 0x4
	// Bit mask of AWB_SAMPLE field.
	ISP_AWB_MODE_AWB_SAMPLE_Msk = 0x10
	// Bit AWB_SAMPLE.
	ISP_AWB_MODE_AWB_SAMPLE = 0x10

	// AWB_HSCALE: h-scale of awb window
	// Position of AWB_RPOINT field.
	ISP_AWB_HSCALE_AWB_RPOINT_Pos = 0x0
	// Bit mask of AWB_RPOINT field.
	ISP_AWB_HSCALE_AWB_RPOINT_Msk = 0xfff
	// Position of AWB_LPOINT field.
	ISP_AWB_HSCALE_AWB_LPOINT_Pos = 0x10
	// Bit mask of AWB_LPOINT field.
	ISP_AWB_HSCALE_AWB_LPOINT_Msk = 0xfff0000

	// AWB_VSCALE: v-scale of awb window
	// Position of AWB_BPOINT field.
	ISP_AWB_VSCALE_AWB_BPOINT_Pos = 0x0
	// Bit mask of AWB_BPOINT field.
	ISP_AWB_VSCALE_AWB_BPOINT_Msk = 0xfff
	// Position of AWB_TPOINT field.
	ISP_AWB_VSCALE_AWB_TPOINT_Pos = 0x10
	// Bit mask of AWB_TPOINT field.
	ISP_AWB_VSCALE_AWB_TPOINT_Msk = 0xfff0000

	// AWB_TH_LUM: awb lum threshold register
	// Position of AWB_MIN_LUM field.
	ISP_AWB_TH_LUM_AWB_MIN_LUM_Pos = 0x0
	// Bit mask of AWB_MIN_LUM field.
	ISP_AWB_TH_LUM_AWB_MIN_LUM_Msk = 0x3ff
	// Position of AWB_MAX_LUM field.
	ISP_AWB_TH_LUM_AWB_MAX_LUM_Pos = 0x10
	// Bit mask of AWB_MAX_LUM field.
	ISP_AWB_TH_LUM_AWB_MAX_LUM_Msk = 0x3ff0000

	// AWB_TH_RG: awb r/g threshold register
	// Position of AWB_MIN_RG field.
	ISP_AWB_TH_RG_AWB_MIN_RG_Pos = 0x0
	// Bit mask of AWB_MIN_RG field.
	ISP_AWB_TH_RG_AWB_MIN_RG_Msk = 0x3ff
	// Position of AWB_MAX_RG field.
	ISP_AWB_TH_RG_AWB_MAX_RG_Pos = 0x10
	// Bit mask of AWB_MAX_RG field.
	ISP_AWB_TH_RG_AWB_MAX_RG_Msk = 0x3ff0000

	// AWB_TH_BG: awb b/g threshold register
	// Position of AWB_MIN_BG field.
	ISP_AWB_TH_BG_AWB_MIN_BG_Pos = 0x0
	// Bit mask of AWB_MIN_BG field.
	ISP_AWB_TH_BG_AWB_MIN_BG_Msk = 0x3ff
	// Position of AWB_MAX_BG field.
	ISP_AWB_TH_BG_AWB_MAX_BG_Pos = 0x10
	// Bit mask of AWB_MAX_BG field.
	ISP_AWB_TH_BG_AWB_MAX_BG_Msk = 0x3ff0000

	// AWB0_WHITE_CNT: result of awb white point number
	// Position of AWB0_WHITE_CNT field.
	ISP_AWB0_WHITE_CNT_AWB0_WHITE_CNT_Pos = 0x0
	// Bit mask of AWB0_WHITE_CNT field.
	ISP_AWB0_WHITE_CNT_AWB0_WHITE_CNT_Msk = 0xffffff

	// AWB0_ACC_R: result of accumulate of r channel of all white points
	// Position of AWB0_ACC_R field.
	ISP_AWB0_ACC_R_AWB0_ACC_R_Pos = 0x0
	// Bit mask of AWB0_ACC_R field.
	ISP_AWB0_ACC_R_AWB0_ACC_R_Msk = 0xffffffff

	// AWB0_ACC_G: result of accumulate of g channel of all white points
	// Position of AWB0_ACC_G field.
	ISP_AWB0_ACC_G_AWB0_ACC_G_Pos = 0x0
	// Bit mask of AWB0_ACC_G field.
	ISP_AWB0_ACC_G_AWB0_ACC_G_Msk = 0xffffffff

	// AWB0_ACC_B: result of accumulate of b channel of all white points
	// Position of AWB0_ACC_B field.
	ISP_AWB0_ACC_B_AWB0_ACC_B_Pos = 0x0
	// Bit mask of AWB0_ACC_B field.
	ISP_AWB0_ACC_B_AWB0_ACC_B_Msk = 0xffffffff

	// COLOR_CTRL: color control register
	// Position of COLOR_SATURATION field.
	ISP_COLOR_CTRL_COLOR_SATURATION_Pos = 0x0
	// Bit mask of COLOR_SATURATION field.
	ISP_COLOR_CTRL_COLOR_SATURATION_Msk = 0xff
	// Position of COLOR_HUE field.
	ISP_COLOR_CTRL_COLOR_HUE_Pos = 0x8
	// Bit mask of COLOR_HUE field.
	ISP_COLOR_CTRL_COLOR_HUE_Msk = 0xff00
	// Position of COLOR_CONTRAST field.
	ISP_COLOR_CTRL_COLOR_CONTRAST_Pos = 0x10
	// Bit mask of COLOR_CONTRAST field.
	ISP_COLOR_CTRL_COLOR_CONTRAST_Msk = 0xff0000
	// Position of COLOR_BRIGHTNESS field.
	ISP_COLOR_CTRL_COLOR_BRIGHTNESS_Pos = 0x18
	// Bit mask of COLOR_BRIGHTNESS field.
	ISP_COLOR_CTRL_COLOR_BRIGHTNESS_Msk = 0xff000000

	// BLC_VALUE: blc black level register
	// Position of BLC_R3_VALUE field.
	ISP_BLC_VALUE_BLC_R3_VALUE_Pos = 0x0
	// Bit mask of BLC_R3_VALUE field.
	ISP_BLC_VALUE_BLC_R3_VALUE_Msk = 0xff
	// Position of BLC_R2_VALUE field.
	ISP_BLC_VALUE_BLC_R2_VALUE_Pos = 0x8
	// Bit mask of BLC_R2_VALUE field.
	ISP_BLC_VALUE_BLC_R2_VALUE_Msk = 0xff00
	// Position of BLC_R1_VALUE field.
	ISP_BLC_VALUE_BLC_R1_VALUE_Pos = 0x10
	// Bit mask of BLC_R1_VALUE field.
	ISP_BLC_VALUE_BLC_R1_VALUE_Msk = 0xff0000
	// Position of BLC_R0_VALUE field.
	ISP_BLC_VALUE_BLC_R0_VALUE_Pos = 0x18
	// Bit mask of BLC_R0_VALUE field.
	ISP_BLC_VALUE_BLC_R0_VALUE_Msk = 0xff000000

	// BLC_CTRL0: blc stretch control register
	// Position of BLC_R3_STRETCH field.
	ISP_BLC_CTRL0_BLC_R3_STRETCH_Pos = 0x0
	// Bit mask of BLC_R3_STRETCH field.
	ISP_BLC_CTRL0_BLC_R3_STRETCH_Msk = 0x1
	// Bit BLC_R3_STRETCH.
	ISP_BLC_CTRL0_BLC_R3_STRETCH = 0x1
	// Position of BLC_R2_STRETCH field.
	ISP_BLC_CTRL0_BLC_R2_STRETCH_Pos = 0x1
	// Bit mask of BLC_R2_STRETCH field.
	ISP_BLC_CTRL0_BLC_R2_STRETCH_Msk = 0x2
	// Bit BLC_R2_STRETCH.
	ISP_BLC_CTRL0_BLC_R2_STRETCH = 0x2
	// Position of BLC_R1_STRETCH field.
	ISP_BLC_CTRL0_BLC_R1_STRETCH_Pos = 0x2
	// Bit mask of BLC_R1_STRETCH field.
	ISP_BLC_CTRL0_BLC_R1_STRETCH_Msk = 0x4
	// Bit BLC_R1_STRETCH.
	ISP_BLC_CTRL0_BLC_R1_STRETCH = 0x4
	// Position of BLC_R0_STRETCH field.
	ISP_BLC_CTRL0_BLC_R0_STRETCH_Pos = 0x3
	// Bit mask of BLC_R0_STRETCH field.
	ISP_BLC_CTRL0_BLC_R0_STRETCH_Msk = 0x8
	// Bit BLC_R0_STRETCH.
	ISP_BLC_CTRL0_BLC_R0_STRETCH = 0x8

	// BLC_CTRL1: blc window control register
	// Position of BLC_WINDOW_TOP field.
	ISP_BLC_CTRL1_BLC_WINDOW_TOP_Pos = 0x0
	// Bit mask of BLC_WINDOW_TOP field.
	ISP_BLC_CTRL1_BLC_WINDOW_TOP_Msk = 0x7ff
	// Position of BLC_WINDOW_LEFT field.
	ISP_BLC_CTRL1_BLC_WINDOW_LEFT_Pos = 0xb
	// Bit mask of BLC_WINDOW_LEFT field.
	ISP_BLC_CTRL1_BLC_WINDOW_LEFT_Msk = 0x3ff800
	// Position of BLC_WINDOW_VNUM field.
	ISP_BLC_CTRL1_BLC_WINDOW_VNUM_Pos = 0x16
	// Bit mask of BLC_WINDOW_VNUM field.
	ISP_BLC_CTRL1_BLC_WINDOW_VNUM_Msk = 0x3c00000
	// Position of BLC_WINDOW_HNUM field.
	ISP_BLC_CTRL1_BLC_WINDOW_HNUM_Pos = 0x1a
	// Bit mask of BLC_WINDOW_HNUM field.
	ISP_BLC_CTRL1_BLC_WINDOW_HNUM_Msk = 0x3c000000
	// Position of BLC_FILTER_EN field.
	ISP_BLC_CTRL1_BLC_FILTER_EN_Pos = 0x1e
	// Bit mask of BLC_FILTER_EN field.
	ISP_BLC_CTRL1_BLC_FILTER_EN_Msk = 0x40000000
	// Bit BLC_FILTER_EN.
	ISP_BLC_CTRL1_BLC_FILTER_EN = 0x40000000

	// BLC_CTRL2: blc black threshold control register
	// Position of BLC_R3_TH field.
	ISP_BLC_CTRL2_BLC_R3_TH_Pos = 0x0
	// Bit mask of BLC_R3_TH field.
	ISP_BLC_CTRL2_BLC_R3_TH_Msk = 0xff
	// Position of BLC_R2_TH field.
	ISP_BLC_CTRL2_BLC_R2_TH_Pos = 0x8
	// Bit mask of BLC_R2_TH field.
	ISP_BLC_CTRL2_BLC_R2_TH_Msk = 0xff00
	// Position of BLC_R1_TH field.
	ISP_BLC_CTRL2_BLC_R1_TH_Pos = 0x10
	// Bit mask of BLC_R1_TH field.
	ISP_BLC_CTRL2_BLC_R1_TH_Msk = 0xff0000
	// Position of BLC_R0_TH field.
	ISP_BLC_CTRL2_BLC_R0_TH_Pos = 0x18
	// Bit mask of BLC_R0_TH field.
	ISP_BLC_CTRL2_BLC_R0_TH_Msk = 0xff000000

	// BLC_MEAN: results of the average of black window
	// Position of BLC_R3_MEAN field.
	ISP_BLC_MEAN_BLC_R3_MEAN_Pos = 0x0
	// Bit mask of BLC_R3_MEAN field.
	ISP_BLC_MEAN_BLC_R3_MEAN_Msk = 0xff
	// Position of BLC_R2_MEAN field.
	ISP_BLC_MEAN_BLC_R2_MEAN_Pos = 0x8
	// Bit mask of BLC_R2_MEAN field.
	ISP_BLC_MEAN_BLC_R2_MEAN_Msk = 0xff00
	// Position of BLC_R1_MEAN field.
	ISP_BLC_MEAN_BLC_R1_MEAN_Pos = 0x10
	// Bit mask of BLC_R1_MEAN field.
	ISP_BLC_MEAN_BLC_R1_MEAN_Msk = 0xff0000
	// Position of BLC_R0_MEAN field.
	ISP_BLC_MEAN_BLC_R0_MEAN_Pos = 0x18
	// Bit mask of BLC_R0_MEAN field.
	ISP_BLC_MEAN_BLC_R0_MEAN_Msk = 0xff000000

	// HIST_MODE: histogram mode control register
	// Position of HIST_MODE field.
	ISP_HIST_MODE_HIST_MODE_Pos = 0x0
	// Bit mask of HIST_MODE field.
	ISP_HIST_MODE_HIST_MODE_Msk = 0x7

	// HIST_COEFF: histogram rgb to gray coefficients register
	// Position of B field.
	ISP_HIST_COEFF_B_Pos = 0x0
	// Bit mask of B field.
	ISP_HIST_COEFF_B_Msk = 0xff
	// Position of G field.
	ISP_HIST_COEFF_G_Pos = 0x8
	// Bit mask of G field.
	ISP_HIST_COEFF_G_Msk = 0xff00
	// Position of R field.
	ISP_HIST_COEFF_R_Pos = 0x10
	// Bit mask of R field.
	ISP_HIST_COEFF_R_Msk = 0xff0000

	// HIST_OFFS: histogram window offsets register
	// Position of HIST_Y_OFFS field.
	ISP_HIST_OFFS_HIST_Y_OFFS_Pos = 0x0
	// Bit mask of HIST_Y_OFFS field.
	ISP_HIST_OFFS_HIST_Y_OFFS_Msk = 0xfff
	// Position of HIST_X_OFFS field.
	ISP_HIST_OFFS_HIST_X_OFFS_Pos = 0x10
	// Bit mask of HIST_X_OFFS field.
	ISP_HIST_OFFS_HIST_X_OFFS_Msk = 0xfff0000

	// HIST_SIZE: histogram sub-window size register
	// Position of HIST_Y_SIZE field.
	ISP_HIST_SIZE_HIST_Y_SIZE_Pos = 0x0
	// Bit mask of HIST_Y_SIZE field.
	ISP_HIST_SIZE_HIST_Y_SIZE_Msk = 0x1ff
	// Position of HIST_X_SIZE field.
	ISP_HIST_SIZE_HIST_X_SIZE_Pos = 0x10
	// Bit mask of HIST_X_SIZE field.
	ISP_HIST_SIZE_HIST_X_SIZE_Msk = 0x1ff0000

	// HIST_SEG0: histogram bin control register 0
	// Position of HIST_SEG_3_4 field.
	ISP_HIST_SEG0_HIST_SEG_3_4_Pos = 0x0
	// Bit mask of HIST_SEG_3_4 field.
	ISP_HIST_SEG0_HIST_SEG_3_4_Msk = 0xff
	// Position of HIST_SEG_2_3 field.
	ISP_HIST_SEG0_HIST_SEG_2_3_Pos = 0x8
	// Bit mask of HIST_SEG_2_3 field.
	ISP_HIST_SEG0_HIST_SEG_2_3_Msk = 0xff00
	// Position of HIST_SEG_1_2 field.
	ISP_HIST_SEG0_HIST_SEG_1_2_Pos = 0x10
	// Bit mask of HIST_SEG_1_2 field.
	ISP_HIST_SEG0_HIST_SEG_1_2_Msk = 0xff0000
	// Position of HIST_SEG_0_1 field.
	ISP_HIST_SEG0_HIST_SEG_0_1_Pos = 0x18
	// Bit mask of HIST_SEG_0_1 field.
	ISP_HIST_SEG0_HIST_SEG_0_1_Msk = 0xff000000

	// HIST_SEG1: histogram bin control register 1
	// Position of HIST_SEG_7_8 field.
	ISP_HIST_SEG1_HIST_SEG_7_8_Pos = 0x0
	// Bit mask of HIST_SEG_7_8 field.
	ISP_HIST_SEG1_HIST_SEG_7_8_Msk = 0xff
	// Position of HIST_SEG_6_7 field.
	ISP_HIST_SEG1_HIST_SEG_6_7_Pos = 0x8
	// Bit mask of HIST_SEG_6_7 field.
	ISP_HIST_SEG1_HIST_SEG_6_7_Msk = 0xff00
	// Position of HIST_SEG_5_6 field.
	ISP_HIST_SEG1_HIST_SEG_5_6_Pos = 0x10
	// Bit mask of HIST_SEG_5_6 field.
	ISP_HIST_SEG1_HIST_SEG_5_6_Msk = 0xff0000
	// Position of HIST_SEG_4_5 field.
	ISP_HIST_SEG1_HIST_SEG_4_5_Pos = 0x18
	// Bit mask of HIST_SEG_4_5 field.
	ISP_HIST_SEG1_HIST_SEG_4_5_Msk = 0xff000000

	// HIST_SEG2: histogram bin control register 2
	// Position of HIST_SEG_11_12 field.
	ISP_HIST_SEG2_HIST_SEG_11_12_Pos = 0x0
	// Bit mask of HIST_SEG_11_12 field.
	ISP_HIST_SEG2_HIST_SEG_11_12_Msk = 0xff
	// Position of HIST_SEG_10_11 field.
	ISP_HIST_SEG2_HIST_SEG_10_11_Pos = 0x8
	// Bit mask of HIST_SEG_10_11 field.
	ISP_HIST_SEG2_HIST_SEG_10_11_Msk = 0xff00
	// Position of HIST_SEG_9_10 field.
	ISP_HIST_SEG2_HIST_SEG_9_10_Pos = 0x10
	// Bit mask of HIST_SEG_9_10 field.
	ISP_HIST_SEG2_HIST_SEG_9_10_Msk = 0xff0000
	// Position of HIST_SEG_8_9 field.
	ISP_HIST_SEG2_HIST_SEG_8_9_Pos = 0x18
	// Bit mask of HIST_SEG_8_9 field.
	ISP_HIST_SEG2_HIST_SEG_8_9_Msk = 0xff000000

	// HIST_SEG3: histogram bin control register 3
	// Position of HIST_SEG_14_15 field.
	ISP_HIST_SEG3_HIST_SEG_14_15_Pos = 0x0
	// Bit mask of HIST_SEG_14_15 field.
	ISP_HIST_SEG3_HIST_SEG_14_15_Msk = 0xff
	// Position of HIST_SEG_13_14 field.
	ISP_HIST_SEG3_HIST_SEG_13_14_Pos = 0x8
	// Bit mask of HIST_SEG_13_14 field.
	ISP_HIST_SEG3_HIST_SEG_13_14_Msk = 0xff00
	// Position of HIST_SEG_12_13 field.
	ISP_HIST_SEG3_HIST_SEG_12_13_Pos = 0x10
	// Bit mask of HIST_SEG_12_13 field.
	ISP_HIST_SEG3_HIST_SEG_12_13_Msk = 0xff0000

	// HIST_WEIGHT0: histogram sub-window weight register 0
	// Position of HIST_WEIGHT_03 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_03_Pos = 0x0
	// Bit mask of HIST_WEIGHT_03 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_03_Msk = 0xff
	// Position of HIST_WEIGHT_02 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_02_Pos = 0x8
	// Bit mask of HIST_WEIGHT_02 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_02_Msk = 0xff00
	// Position of HIST_WEIGHT_01 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_01_Pos = 0x10
	// Bit mask of HIST_WEIGHT_01 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_01_Msk = 0xff0000
	// Position of HIST_WEIGHT_00 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_00_Pos = 0x18
	// Bit mask of HIST_WEIGHT_00 field.
	ISP_HIST_WEIGHT0_HIST_WEIGHT_00_Msk = 0xff000000

	// HIST_WEIGHT1: histogram sub-window weight register 1
	// Position of HIST_WEIGHT_12 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_12_Pos = 0x0
	// Bit mask of HIST_WEIGHT_12 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_12_Msk = 0xff
	// Position of HIST_WEIGHT_11 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_11_Pos = 0x8
	// Bit mask of HIST_WEIGHT_11 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_11_Msk = 0xff00
	// Position of HIST_WEIGHT_10 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_10_Pos = 0x10
	// Bit mask of HIST_WEIGHT_10 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_10_Msk = 0xff0000
	// Position of HIST_WEIGHT_04 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_04_Pos = 0x18
	// Bit mask of HIST_WEIGHT_04 field.
	ISP_HIST_WEIGHT1_HIST_WEIGHT_04_Msk = 0xff000000

	// HIST_WEIGHT2: histogram sub-window weight register 2
	// Position of HIST_WEIGHT_21 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_21_Pos = 0x0
	// Bit mask of HIST_WEIGHT_21 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_21_Msk = 0xff
	// Position of HIST_WEIGHT_20 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_20_Pos = 0x8
	// Bit mask of HIST_WEIGHT_20 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_20_Msk = 0xff00
	// Position of HIST_WEIGHT_14 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_14_Pos = 0x10
	// Bit mask of HIST_WEIGHT_14 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_14_Msk = 0xff0000
	// Position of HIST_WEIGHT_13 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_13_Pos = 0x18
	// Bit mask of HIST_WEIGHT_13 field.
	ISP_HIST_WEIGHT2_HIST_WEIGHT_13_Msk = 0xff000000

	// HIST_WEIGHT3: histogram sub-window weight register 3
	// Position of HIST_WEIGHT_30 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_30_Pos = 0x0
	// Bit mask of HIST_WEIGHT_30 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_30_Msk = 0xff
	// Position of HIST_WEIGHT_24 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_24_Pos = 0x8
	// Bit mask of HIST_WEIGHT_24 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_24_Msk = 0xff00
	// Position of HIST_WEIGHT_23 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_23_Pos = 0x10
	// Bit mask of HIST_WEIGHT_23 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_23_Msk = 0xff0000
	// Position of HIST_WEIGHT_22 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_22_Pos = 0x18
	// Bit mask of HIST_WEIGHT_22 field.
	ISP_HIST_WEIGHT3_HIST_WEIGHT_22_Msk = 0xff000000

	// HIST_WEIGHT4: histogram sub-window weight register 4
	// Position of HIST_WEIGHT_34 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_34_Pos = 0x0
	// Bit mask of HIST_WEIGHT_34 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_34_Msk = 0xff
	// Position of HIST_WEIGHT_33 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_33_Pos = 0x8
	// Bit mask of HIST_WEIGHT_33 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_33_Msk = 0xff00
	// Position of HIST_WEIGHT_32 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_32_Pos = 0x10
	// Bit mask of HIST_WEIGHT_32 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_32_Msk = 0xff0000
	// Position of HIST_WEIGHT_31 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_31_Pos = 0x18
	// Bit mask of HIST_WEIGHT_31 field.
	ISP_HIST_WEIGHT4_HIST_WEIGHT_31_Msk = 0xff000000

	// HIST_WEIGHT5: histogram sub-window weight register 5
	// Position of HIST_WEIGHT_43 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_43_Pos = 0x0
	// Bit mask of HIST_WEIGHT_43 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_43_Msk = 0xff
	// Position of HIST_WEIGHT_42 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_42_Pos = 0x8
	// Bit mask of HIST_WEIGHT_42 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_42_Msk = 0xff00
	// Position of HIST_WEIGHT_41 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_41_Pos = 0x10
	// Bit mask of HIST_WEIGHT_41 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_41_Msk = 0xff0000
	// Position of HIST_WEIGHT_40 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_40_Pos = 0x18
	// Bit mask of HIST_WEIGHT_40 field.
	ISP_HIST_WEIGHT5_HIST_WEIGHT_40_Msk = 0xff000000

	// HIST_WEIGHT6: histogram sub-window weight register 6
	// Position of HIST_WEIGHT_44 field.
	ISP_HIST_WEIGHT6_HIST_WEIGHT_44_Pos = 0x0
	// Bit mask of HIST_WEIGHT_44 field.
	ISP_HIST_WEIGHT6_HIST_WEIGHT_44_Msk = 0xff

	// HIST_BIN0: result of histogram bin 0
	// Position of HIST_BIN_0 field.
	ISP_HIST_BIN0_HIST_BIN_0_Pos = 0x0
	// Bit mask of HIST_BIN_0 field.
	ISP_HIST_BIN0_HIST_BIN_0_Msk = 0x1ffff

	// HIST_BIN1: result of histogram bin 1
	// Position of HIST_BIN_1 field.
	ISP_HIST_BIN1_HIST_BIN_1_Pos = 0x0
	// Bit mask of HIST_BIN_1 field.
	ISP_HIST_BIN1_HIST_BIN_1_Msk = 0x1ffff

	// HIST_BIN2: result of histogram bin 2
	// Position of HIST_BIN_2 field.
	ISP_HIST_BIN2_HIST_BIN_2_Pos = 0x0
	// Bit mask of HIST_BIN_2 field.
	ISP_HIST_BIN2_HIST_BIN_2_Msk = 0x1ffff

	// HIST_BIN3: result of histogram bin 3
	// Position of HIST_BIN_3 field.
	ISP_HIST_BIN3_HIST_BIN_3_Pos = 0x0
	// Bit mask of HIST_BIN_3 field.
	ISP_HIST_BIN3_HIST_BIN_3_Msk = 0x1ffff

	// HIST_BIN4: result of histogram bin 4
	// Position of HIST_BIN_4 field.
	ISP_HIST_BIN4_HIST_BIN_4_Pos = 0x0
	// Bit mask of HIST_BIN_4 field.
	ISP_HIST_BIN4_HIST_BIN_4_Msk = 0x1ffff

	// HIST_BIN5: result of histogram bin 5
	// Position of HIST_BIN_5 field.
	ISP_HIST_BIN5_HIST_BIN_5_Pos = 0x0
	// Bit mask of HIST_BIN_5 field.
	ISP_HIST_BIN5_HIST_BIN_5_Msk = 0x1ffff

	// HIST_BIN6: result of histogram bin 6
	// Position of HIST_BIN_6 field.
	ISP_HIST_BIN6_HIST_BIN_6_Pos = 0x0
	// Bit mask of HIST_BIN_6 field.
	ISP_HIST_BIN6_HIST_BIN_6_Msk = 0x1ffff

	// HIST_BIN7: result of histogram bin 7
	// Position of HIST_BIN_7 field.
	ISP_HIST_BIN7_HIST_BIN_7_Pos = 0x0
	// Bit mask of HIST_BIN_7 field.
	ISP_HIST_BIN7_HIST_BIN_7_Msk = 0x1ffff

	// HIST_BIN8: result of histogram bin 8
	// Position of HIST_BIN_8 field.
	ISP_HIST_BIN8_HIST_BIN_8_Pos = 0x0
	// Bit mask of HIST_BIN_8 field.
	ISP_HIST_BIN8_HIST_BIN_8_Msk = 0x1ffff

	// HIST_BIN9: result of histogram bin 9
	// Position of HIST_BIN_9 field.
	ISP_HIST_BIN9_HIST_BIN_9_Pos = 0x0
	// Bit mask of HIST_BIN_9 field.
	ISP_HIST_BIN9_HIST_BIN_9_Msk = 0x1ffff

	// HIST_BIN10: result of histogram bin 10
	// Position of HIST_BIN_10 field.
	ISP_HIST_BIN10_HIST_BIN_10_Pos = 0x0
	// Bit mask of HIST_BIN_10 field.
	ISP_HIST_BIN10_HIST_BIN_10_Msk = 0x1ffff

	// HIST_BIN11: result of histogram bin 11
	// Position of HIST_BIN_11 field.
	ISP_HIST_BIN11_HIST_BIN_11_Pos = 0x0
	// Bit mask of HIST_BIN_11 field.
	ISP_HIST_BIN11_HIST_BIN_11_Msk = 0x1ffff

	// HIST_BIN12: result of histogram bin 12
	// Position of HIST_BIN_12 field.
	ISP_HIST_BIN12_HIST_BIN_12_Pos = 0x0
	// Bit mask of HIST_BIN_12 field.
	ISP_HIST_BIN12_HIST_BIN_12_Msk = 0x1ffff

	// HIST_BIN13: result of histogram bin 13
	// Position of HIST_BIN_13 field.
	ISP_HIST_BIN13_HIST_BIN_13_Pos = 0x0
	// Bit mask of HIST_BIN_13 field.
	ISP_HIST_BIN13_HIST_BIN_13_Msk = 0x1ffff

	// HIST_BIN14: result of histogram bin 14
	// Position of HIST_BIN_14 field.
	ISP_HIST_BIN14_HIST_BIN_14_Pos = 0x0
	// Bit mask of HIST_BIN_14 field.
	ISP_HIST_BIN14_HIST_BIN_14_Msk = 0x1ffff

	// HIST_BIN15: result of histogram bin 15
	// Position of HIST_BIN_15 field.
	ISP_HIST_BIN15_HIST_BIN_15_Pos = 0x0
	// Bit mask of HIST_BIN_15 field.
	ISP_HIST_BIN15_HIST_BIN_15_Msk = 0x1ffff

	// MEM_AUX_CTRL_0: mem aux control register 0
	// Position of HEADER_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_0_HEADER_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of HEADER_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_0_HEADER_MEM_AUX_CTRL_Msk = 0x3fff
	// Position of DPC_LUT_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_0_DPC_LUT_MEM_AUX_CTRL_Pos = 0x10
	// Bit mask of DPC_LUT_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_0_DPC_LUT_MEM_AUX_CTRL_Msk = 0x3fff0000

	// MEM_AUX_CTRL_1: mem aux control register 1
	// Position of LSC_LUT_R_GR_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_1_LSC_LUT_R_GR_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of LSC_LUT_R_GR_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_1_LSC_LUT_R_GR_MEM_AUX_CTRL_Msk = 0x3fff
	// Position of LSC_LUT_GB_B_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_1_LSC_LUT_GB_B_MEM_AUX_CTRL_Pos = 0x10
	// Bit mask of LSC_LUT_GB_B_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_1_LSC_LUT_GB_B_MEM_AUX_CTRL_Msk = 0x3fff0000

	// MEM_AUX_CTRL_2: mem aux control register 2
	// Position of BF_MATRIX_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_2_BF_MATRIX_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of BF_MATRIX_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_2_BF_MATRIX_MEM_AUX_CTRL_Msk = 0x3fff
	// Position of DPC_MATRIX_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_2_DPC_MATRIX_MEM_AUX_CTRL_Pos = 0x10
	// Bit mask of DPC_MATRIX_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_2_DPC_MATRIX_MEM_AUX_CTRL_Msk = 0x3fff0000

	// MEM_AUX_CTRL_3: mem aux control register 3
	// Position of SHARP_MATRIX_Y_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_3_SHARP_MATRIX_Y_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of SHARP_MATRIX_Y_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_3_SHARP_MATRIX_Y_MEM_AUX_CTRL_Msk = 0x3fff
	// Position of DEMOSAIC_MATRIX_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_3_DEMOSAIC_MATRIX_MEM_AUX_CTRL_Pos = 0x10
	// Bit mask of DEMOSAIC_MATRIX_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_3_DEMOSAIC_MATRIX_MEM_AUX_CTRL_Msk = 0x3fff0000

	// MEM_AUX_CTRL_4: mem aux control register 4
	// Position of SHARP_MATRIX_UV_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_4_SHARP_MATRIX_UV_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of SHARP_MATRIX_UV_MEM_AUX_CTRL field.
	ISP_MEM_AUX_CTRL_4_SHARP_MATRIX_UV_MEM_AUX_CTRL_Msk = 0x3fff

	// YUV_FORMAT: yuv format control register
	// Position of YUV_MODE field.
	ISP_YUV_FORMAT_YUV_MODE_Pos = 0x0
	// Bit mask of YUV_MODE field.
	ISP_YUV_FORMAT_YUV_MODE_Msk = 0x1
	// Bit YUV_MODE.
	ISP_YUV_FORMAT_YUV_MODE = 0x1
	// Position of YUV_RANGE field.
	ISP_YUV_FORMAT_YUV_RANGE_Pos = 0x1
	// Bit mask of YUV_RANGE field.
	ISP_YUV_FORMAT_YUV_RANGE_Msk = 0x2
	// Bit YUV_RANGE.
	ISP_YUV_FORMAT_YUV_RANGE = 0x2

	// RDN_ECO_CS: rdn eco cs register
	// Position of RDN_ECO_EN field.
	ISP_RDN_ECO_CS_RDN_ECO_EN_Pos = 0x0
	// Bit mask of RDN_ECO_EN field.
	ISP_RDN_ECO_CS_RDN_ECO_EN_Msk = 0x1
	// Bit RDN_ECO_EN.
	ISP_RDN_ECO_CS_RDN_ECO_EN = 0x1
	// Position of RDN_ECO_RESULT field.
	ISP_RDN_ECO_CS_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of RDN_ECO_RESULT field.
	ISP_RDN_ECO_CS_RDN_ECO_RESULT_Msk = 0x2
	// Bit RDN_ECO_RESULT.
	ISP_RDN_ECO_CS_RDN_ECO_RESULT = 0x2

	// RDN_ECO_LOW: rdn eco all low register
	// Position of RDN_ECO_LOW field.
	ISP_RDN_ECO_LOW_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of RDN_ECO_LOW field.
	ISP_RDN_ECO_LOW_RDN_ECO_LOW_Msk = 0xffffffff

	// RDN_ECO_HIGH: rdn eco all high register
	// Position of RDN_ECO_HIGH field.
	ISP_RDN_ECO_HIGH_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of RDN_ECO_HIGH field.
	ISP_RDN_ECO_HIGH_RDN_ECO_HIGH_Msk = 0xffffffff
)

// Constants for JPEG: JPEG Codec
const (
	// CONFIG: Control and configuration registers
	// Position of FSM_RST field.
	JPEG_CONFIG_FSM_RST_Pos = 0x0
	// Bit mask of FSM_RST field.
	JPEG_CONFIG_FSM_RST_Msk = 0x1
	// Bit FSM_RST.
	JPEG_CONFIG_FSM_RST = 0x1
	// Position of JPEG_START field.
	JPEG_CONFIG_JPEG_START_Pos = 0x1
	// Bit mask of JPEG_START field.
	JPEG_CONFIG_JPEG_START_Msk = 0x2
	// Bit JPEG_START.
	JPEG_CONFIG_JPEG_START = 0x2
	// Position of QNR_PRESITION field.
	JPEG_CONFIG_QNR_PRESITION_Pos = 0x2
	// Bit mask of QNR_PRESITION field.
	JPEG_CONFIG_QNR_PRESITION_Msk = 0x4
	// Bit QNR_PRESITION.
	JPEG_CONFIG_QNR_PRESITION = 0x4
	// Position of FF_CHECK_EN field.
	JPEG_CONFIG_FF_CHECK_EN_Pos = 0x3
	// Bit mask of FF_CHECK_EN field.
	JPEG_CONFIG_FF_CHECK_EN_Msk = 0x8
	// Bit FF_CHECK_EN.
	JPEG_CONFIG_FF_CHECK_EN = 0x8
	// Position of SAMPLE_SEL field.
	JPEG_CONFIG_SAMPLE_SEL_Pos = 0x4
	// Bit mask of SAMPLE_SEL field.
	JPEG_CONFIG_SAMPLE_SEL_Msk = 0x30
	// Position of DMA_LINKLIST_MODE field.
	JPEG_CONFIG_DMA_LINKLIST_MODE_Pos = 0x6
	// Bit mask of DMA_LINKLIST_MODE field.
	JPEG_CONFIG_DMA_LINKLIST_MODE_Msk = 0x40
	// Bit DMA_LINKLIST_MODE.
	JPEG_CONFIG_DMA_LINKLIST_MODE = 0x40
	// Position of DEBUG_DIRECT_OUT_EN field.
	JPEG_CONFIG_DEBUG_DIRECT_OUT_EN_Pos = 0x7
	// Bit mask of DEBUG_DIRECT_OUT_EN field.
	JPEG_CONFIG_DEBUG_DIRECT_OUT_EN_Msk = 0x80
	// Bit DEBUG_DIRECT_OUT_EN.
	JPEG_CONFIG_DEBUG_DIRECT_OUT_EN = 0x80
	// Position of GRAY_SEL field.
	JPEG_CONFIG_GRAY_SEL_Pos = 0x8
	// Bit mask of GRAY_SEL field.
	JPEG_CONFIG_GRAY_SEL_Msk = 0x100
	// Bit GRAY_SEL.
	JPEG_CONFIG_GRAY_SEL = 0x100
	// Position of LQNR_TBL_SEL field.
	JPEG_CONFIG_LQNR_TBL_SEL_Pos = 0x9
	// Bit mask of LQNR_TBL_SEL field.
	JPEG_CONFIG_LQNR_TBL_SEL_Msk = 0x600
	// Position of CQNR_TBL_SEL field.
	JPEG_CONFIG_CQNR_TBL_SEL_Pos = 0xb
	// Bit mask of CQNR_TBL_SEL field.
	JPEG_CONFIG_CQNR_TBL_SEL_Msk = 0x1800
	// Position of COLOR_SPACE field.
	JPEG_CONFIG_COLOR_SPACE_Pos = 0xd
	// Bit mask of COLOR_SPACE field.
	JPEG_CONFIG_COLOR_SPACE_Msk = 0x6000
	// Position of DHT_FIFO_EN field.
	JPEG_CONFIG_DHT_FIFO_EN_Pos = 0xf
	// Bit mask of DHT_FIFO_EN field.
	JPEG_CONFIG_DHT_FIFO_EN_Msk = 0x8000
	// Bit DHT_FIFO_EN.
	JPEG_CONFIG_DHT_FIFO_EN = 0x8000
	// Position of MEM_CLK_FORCE_ON field.
	JPEG_CONFIG_MEM_CLK_FORCE_ON_Pos = 0x10
	// Bit mask of MEM_CLK_FORCE_ON field.
	JPEG_CONFIG_MEM_CLK_FORCE_ON_Msk = 0x10000
	// Bit MEM_CLK_FORCE_ON.
	JPEG_CONFIG_MEM_CLK_FORCE_ON = 0x10000
	// Position of JFIF_VER field.
	JPEG_CONFIG_JFIF_VER_Pos = 0x11
	// Bit mask of JFIF_VER field.
	JPEG_CONFIG_JFIF_VER_Msk = 0x7e0000
	// Position of DECODE_TIMEOUT_TASK_SEL field.
	JPEG_CONFIG_DECODE_TIMEOUT_TASK_SEL_Pos = 0x17
	// Bit mask of DECODE_TIMEOUT_TASK_SEL field.
	JPEG_CONFIG_DECODE_TIMEOUT_TASK_SEL_Msk = 0x800000
	// Bit DECODE_TIMEOUT_TASK_SEL.
	JPEG_CONFIG_DECODE_TIMEOUT_TASK_SEL = 0x800000
	// Position of SOFT_RST field.
	JPEG_CONFIG_SOFT_RST_Pos = 0x18
	// Bit mask of SOFT_RST field.
	JPEG_CONFIG_SOFT_RST_Msk = 0x1000000
	// Bit SOFT_RST.
	JPEG_CONFIG_SOFT_RST = 0x1000000
	// Position of FIFO_RST field.
	JPEG_CONFIG_FIFO_RST_Pos = 0x19
	// Bit mask of FIFO_RST field.
	JPEG_CONFIG_FIFO_RST_Msk = 0x2000000
	// Bit FIFO_RST.
	JPEG_CONFIG_FIFO_RST = 0x2000000
	// Position of PIXEL_REV field.
	JPEG_CONFIG_PIXEL_REV_Pos = 0x1a
	// Bit mask of PIXEL_REV field.
	JPEG_CONFIG_PIXEL_REV_Msk = 0x4000000
	// Bit PIXEL_REV.
	JPEG_CONFIG_PIXEL_REV = 0x4000000
	// Position of TAILER_EN field.
	JPEG_CONFIG_TAILER_EN_Pos = 0x1b
	// Bit mask of TAILER_EN field.
	JPEG_CONFIG_TAILER_EN_Msk = 0x8000000
	// Bit TAILER_EN.
	JPEG_CONFIG_TAILER_EN = 0x8000000
	// Position of PAUSE_EN field.
	JPEG_CONFIG_PAUSE_EN_Pos = 0x1c
	// Bit mask of PAUSE_EN field.
	JPEG_CONFIG_PAUSE_EN_Msk = 0x10000000
	// Bit PAUSE_EN.
	JPEG_CONFIG_PAUSE_EN = 0x10000000
	// Position of MEM_FORCE_PD field.
	JPEG_CONFIG_MEM_FORCE_PD_Pos = 0x1d
	// Bit mask of MEM_FORCE_PD field.
	JPEG_CONFIG_MEM_FORCE_PD_Msk = 0x20000000
	// Bit MEM_FORCE_PD.
	JPEG_CONFIG_MEM_FORCE_PD = 0x20000000
	// Position of MEM_FORCE_PU field.
	JPEG_CONFIG_MEM_FORCE_PU_Pos = 0x1e
	// Bit mask of MEM_FORCE_PU field.
	JPEG_CONFIG_MEM_FORCE_PU_Msk = 0x40000000
	// Bit MEM_FORCE_PU.
	JPEG_CONFIG_MEM_FORCE_PU = 0x40000000
	// Position of MODE field.
	JPEG_CONFIG_MODE_Pos = 0x1f
	// Bit mask of MODE field.
	JPEG_CONFIG_MODE_Msk = 0x80000000
	// Bit MODE.
	JPEG_CONFIG_MODE = 0x80000000

	// DQT_INFO: Control and configuration registers
	// Position of T0_DQT_INFO field.
	JPEG_DQT_INFO_T0_DQT_INFO_Pos = 0x0
	// Bit mask of T0_DQT_INFO field.
	JPEG_DQT_INFO_T0_DQT_INFO_Msk = 0xff
	// Position of T1_DQT_INFO field.
	JPEG_DQT_INFO_T1_DQT_INFO_Pos = 0x8
	// Bit mask of T1_DQT_INFO field.
	JPEG_DQT_INFO_T1_DQT_INFO_Msk = 0xff00
	// Position of T2_DQT_INFO field.
	JPEG_DQT_INFO_T2_DQT_INFO_Pos = 0x10
	// Bit mask of T2_DQT_INFO field.
	JPEG_DQT_INFO_T2_DQT_INFO_Msk = 0xff0000
	// Position of T3_DQT_INFO field.
	JPEG_DQT_INFO_T3_DQT_INFO_Pos = 0x18
	// Bit mask of T3_DQT_INFO field.
	JPEG_DQT_INFO_T3_DQT_INFO_Msk = 0xff000000

	// PIC_SIZE: Control and configuration registers
	// Position of VA field.
	JPEG_PIC_SIZE_VA_Pos = 0x0
	// Bit mask of VA field.
	JPEG_PIC_SIZE_VA_Msk = 0xffff
	// Position of HA field.
	JPEG_PIC_SIZE_HA_Pos = 0x10
	// Bit mask of HA field.
	JPEG_PIC_SIZE_HA_Msk = 0xffff0000

	// T0QNR: Control and configuration registers
	// Position of T0_QNR_VAL field.
	JPEG_T0QNR_T0_QNR_VAL_Pos = 0x0
	// Bit mask of T0_QNR_VAL field.
	JPEG_T0QNR_T0_QNR_VAL_Msk = 0xffffffff

	// T1QNR: Control and configuration registers
	// Position of CHROMINANCE_QNR_VAL field.
	JPEG_T1QNR_CHROMINANCE_QNR_VAL_Pos = 0x0
	// Bit mask of CHROMINANCE_QNR_VAL field.
	JPEG_T1QNR_CHROMINANCE_QNR_VAL_Msk = 0xffffffff

	// T2QNR: Control and configuration registers
	// Position of T2_QNR_VAL field.
	JPEG_T2QNR_T2_QNR_VAL_Pos = 0x0
	// Bit mask of T2_QNR_VAL field.
	JPEG_T2QNR_T2_QNR_VAL_Msk = 0xffffffff

	// T3QNR: Control and configuration registers
	// Position of T3_QNR_VAL field.
	JPEG_T3QNR_T3_QNR_VAL_Pos = 0x0
	// Bit mask of T3_QNR_VAL field.
	JPEG_T3QNR_T3_QNR_VAL_Msk = 0xffffffff

	// DECODE_CONF: Control and configuration registers
	// Position of RESTART_INTERVAL field.
	JPEG_DECODE_CONF_RESTART_INTERVAL_Pos = 0x0
	// Bit mask of RESTART_INTERVAL field.
	JPEG_DECODE_CONF_RESTART_INTERVAL_Msk = 0xffff
	// Position of COMPONENT_NUM field.
	JPEG_DECODE_CONF_COMPONENT_NUM_Pos = 0x10
	// Bit mask of COMPONENT_NUM field.
	JPEG_DECODE_CONF_COMPONENT_NUM_Msk = 0xff0000
	// Position of SW_DHT_EN field.
	JPEG_DECODE_CONF_SW_DHT_EN_Pos = 0x18
	// Bit mask of SW_DHT_EN field.
	JPEG_DECODE_CONF_SW_DHT_EN_Msk = 0x1000000
	// Bit SW_DHT_EN.
	JPEG_DECODE_CONF_SW_DHT_EN = 0x1000000
	// Position of SOS_CHECK_BYTE_NUM field.
	JPEG_DECODE_CONF_SOS_CHECK_BYTE_NUM_Pos = 0x19
	// Bit mask of SOS_CHECK_BYTE_NUM field.
	JPEG_DECODE_CONF_SOS_CHECK_BYTE_NUM_Msk = 0x6000000
	// Position of RST_CHECK_BYTE_NUM field.
	JPEG_DECODE_CONF_RST_CHECK_BYTE_NUM_Pos = 0x1b
	// Bit mask of RST_CHECK_BYTE_NUM field.
	JPEG_DECODE_CONF_RST_CHECK_BYTE_NUM_Msk = 0x18000000
	// Position of MULTI_SCAN_ERR_CHECK field.
	JPEG_DECODE_CONF_MULTI_SCAN_ERR_CHECK_Pos = 0x1d
	// Bit mask of MULTI_SCAN_ERR_CHECK field.
	JPEG_DECODE_CONF_MULTI_SCAN_ERR_CHECK_Msk = 0x20000000
	// Bit MULTI_SCAN_ERR_CHECK.
	JPEG_DECODE_CONF_MULTI_SCAN_ERR_CHECK = 0x20000000
	// Position of DEZIGZAG_READY_CTL field.
	JPEG_DECODE_CONF_DEZIGZAG_READY_CTL_Pos = 0x1e
	// Bit mask of DEZIGZAG_READY_CTL field.
	JPEG_DECODE_CONF_DEZIGZAG_READY_CTL_Msk = 0x40000000
	// Bit DEZIGZAG_READY_CTL.
	JPEG_DECODE_CONF_DEZIGZAG_READY_CTL = 0x40000000

	// C0: Control and configuration registers
	// Position of DQT_TBL_SEL field.
	JPEG_C0_DQT_TBL_SEL_Pos = 0x0
	// Bit mask of DQT_TBL_SEL field.
	JPEG_C0_DQT_TBL_SEL_Msk = 0xff
	// Position of Y_FACTOR field.
	JPEG_C0_Y_FACTOR_Pos = 0x8
	// Bit mask of Y_FACTOR field.
	JPEG_C0_Y_FACTOR_Msk = 0xf00
	// Position of X_FACTOR field.
	JPEG_C0_X_FACTOR_Pos = 0xc
	// Bit mask of X_FACTOR field.
	JPEG_C0_X_FACTOR_Msk = 0xf000
	// Position of ID field.
	JPEG_C0_ID_Pos = 0x10
	// Bit mask of ID field.
	JPEG_C0_ID_Msk = 0xff0000

	// C1: Control and configuration registers
	// Position of DQT_TBL_SEL field.
	JPEG_C1_DQT_TBL_SEL_Pos = 0x0
	// Bit mask of DQT_TBL_SEL field.
	JPEG_C1_DQT_TBL_SEL_Msk = 0xff
	// Position of Y_FACTOR field.
	JPEG_C1_Y_FACTOR_Pos = 0x8
	// Bit mask of Y_FACTOR field.
	JPEG_C1_Y_FACTOR_Msk = 0xf00
	// Position of X_FACTOR field.
	JPEG_C1_X_FACTOR_Pos = 0xc
	// Bit mask of X_FACTOR field.
	JPEG_C1_X_FACTOR_Msk = 0xf000
	// Position of ID field.
	JPEG_C1_ID_Pos = 0x10
	// Bit mask of ID field.
	JPEG_C1_ID_Msk = 0xff0000

	// C2: Control and configuration registers
	// Position of DQT_TBL_SEL field.
	JPEG_C2_DQT_TBL_SEL_Pos = 0x0
	// Bit mask of DQT_TBL_SEL field.
	JPEG_C2_DQT_TBL_SEL_Msk = 0xff
	// Position of Y_FACTOR field.
	JPEG_C2_Y_FACTOR_Pos = 0x8
	// Bit mask of Y_FACTOR field.
	JPEG_C2_Y_FACTOR_Msk = 0xf00
	// Position of X_FACTOR field.
	JPEG_C2_X_FACTOR_Pos = 0xc
	// Bit mask of X_FACTOR field.
	JPEG_C2_X_FACTOR_Msk = 0xf000
	// Position of ID field.
	JPEG_C2_ID_Pos = 0x10
	// Bit mask of ID field.
	JPEG_C2_ID_Msk = 0xff0000

	// C3: Control and configuration registers
	// Position of DQT_TBL_SEL field.
	JPEG_C3_DQT_TBL_SEL_Pos = 0x0
	// Bit mask of DQT_TBL_SEL field.
	JPEG_C3_DQT_TBL_SEL_Msk = 0xff
	// Position of Y_FACTOR field.
	JPEG_C3_Y_FACTOR_Pos = 0x8
	// Bit mask of Y_FACTOR field.
	JPEG_C3_Y_FACTOR_Msk = 0xf00
	// Position of X_FACTOR field.
	JPEG_C3_X_FACTOR_Pos = 0xc
	// Bit mask of X_FACTOR field.
	JPEG_C3_X_FACTOR_Msk = 0xf000
	// Position of ID field.
	JPEG_C3_ID_Pos = 0x10
	// Bit mask of ID field.
	JPEG_C3_ID_Msk = 0xff0000

	// DHT_INFO: Control and configuration registers
	// Position of DC0_DHT_ID field.
	JPEG_DHT_INFO_DC0_DHT_ID_Pos = 0x0
	// Bit mask of DC0_DHT_ID field.
	JPEG_DHT_INFO_DC0_DHT_ID_Msk = 0xf
	// Position of DC1_DHT_ID field.
	JPEG_DHT_INFO_DC1_DHT_ID_Pos = 0x4
	// Bit mask of DC1_DHT_ID field.
	JPEG_DHT_INFO_DC1_DHT_ID_Msk = 0xf0
	// Position of AC0_DHT_ID field.
	JPEG_DHT_INFO_AC0_DHT_ID_Pos = 0x8
	// Bit mask of AC0_DHT_ID field.
	JPEG_DHT_INFO_AC0_DHT_ID_Msk = 0xf00
	// Position of AC1_DHT_ID field.
	JPEG_DHT_INFO_AC1_DHT_ID_Pos = 0xc
	// Bit mask of AC1_DHT_ID field.
	JPEG_DHT_INFO_AC1_DHT_ID_Msk = 0xf000

	// INT_RAW: Interrupt raw registers
	// Position of DONE_INT_RAW field.
	JPEG_INT_RAW_DONE_INT_RAW_Pos = 0x0
	// Bit mask of DONE_INT_RAW field.
	JPEG_INT_RAW_DONE_INT_RAW_Msk = 0x1
	// Bit DONE_INT_RAW.
	JPEG_INT_RAW_DONE_INT_RAW = 0x1
	// Position of RLE_PARALLEL_ERR_INT_RAW field.
	JPEG_INT_RAW_RLE_PARALLEL_ERR_INT_RAW_Pos = 0x1
	// Bit mask of RLE_PARALLEL_ERR_INT_RAW field.
	JPEG_INT_RAW_RLE_PARALLEL_ERR_INT_RAW_Msk = 0x2
	// Bit RLE_PARALLEL_ERR_INT_RAW.
	JPEG_INT_RAW_RLE_PARALLEL_ERR_INT_RAW = 0x2
	// Position of CID_ERR_INT_RAW field.
	JPEG_INT_RAW_CID_ERR_INT_RAW_Pos = 0x2
	// Bit mask of CID_ERR_INT_RAW field.
	JPEG_INT_RAW_CID_ERR_INT_RAW_Msk = 0x4
	// Bit CID_ERR_INT_RAW.
	JPEG_INT_RAW_CID_ERR_INT_RAW = 0x4
	// Position of C_DHT_DC_ID_ERR_INT_RAW field.
	JPEG_INT_RAW_C_DHT_DC_ID_ERR_INT_RAW_Pos = 0x3
	// Bit mask of C_DHT_DC_ID_ERR_INT_RAW field.
	JPEG_INT_RAW_C_DHT_DC_ID_ERR_INT_RAW_Msk = 0x8
	// Bit C_DHT_DC_ID_ERR_INT_RAW.
	JPEG_INT_RAW_C_DHT_DC_ID_ERR_INT_RAW = 0x8
	// Position of C_DHT_AC_ID_ERR_INT_RAW field.
	JPEG_INT_RAW_C_DHT_AC_ID_ERR_INT_RAW_Pos = 0x4
	// Bit mask of C_DHT_AC_ID_ERR_INT_RAW field.
	JPEG_INT_RAW_C_DHT_AC_ID_ERR_INT_RAW_Msk = 0x10
	// Bit C_DHT_AC_ID_ERR_INT_RAW.
	JPEG_INT_RAW_C_DHT_AC_ID_ERR_INT_RAW = 0x10
	// Position of C_DQT_ID_ERR_INT_RAW field.
	JPEG_INT_RAW_C_DQT_ID_ERR_INT_RAW_Pos = 0x5
	// Bit mask of C_DQT_ID_ERR_INT_RAW field.
	JPEG_INT_RAW_C_DQT_ID_ERR_INT_RAW_Msk = 0x20
	// Bit C_DQT_ID_ERR_INT_RAW.
	JPEG_INT_RAW_C_DQT_ID_ERR_INT_RAW = 0x20
	// Position of RST_UXP_ERR_INT_RAW field.
	JPEG_INT_RAW_RST_UXP_ERR_INT_RAW_Pos = 0x6
	// Bit mask of RST_UXP_ERR_INT_RAW field.
	JPEG_INT_RAW_RST_UXP_ERR_INT_RAW_Msk = 0x40
	// Bit RST_UXP_ERR_INT_RAW.
	JPEG_INT_RAW_RST_UXP_ERR_INT_RAW = 0x40
	// Position of RST_CHECK_NONE_ERR_INT_RAW field.
	JPEG_INT_RAW_RST_CHECK_NONE_ERR_INT_RAW_Pos = 0x7
	// Bit mask of RST_CHECK_NONE_ERR_INT_RAW field.
	JPEG_INT_RAW_RST_CHECK_NONE_ERR_INT_RAW_Msk = 0x80
	// Bit RST_CHECK_NONE_ERR_INT_RAW.
	JPEG_INT_RAW_RST_CHECK_NONE_ERR_INT_RAW = 0x80
	// Position of RST_CHECK_POS_ERR_INT_RAW field.
	JPEG_INT_RAW_RST_CHECK_POS_ERR_INT_RAW_Pos = 0x8
	// Bit mask of RST_CHECK_POS_ERR_INT_RAW field.
	JPEG_INT_RAW_RST_CHECK_POS_ERR_INT_RAW_Msk = 0x100
	// Bit RST_CHECK_POS_ERR_INT_RAW.
	JPEG_INT_RAW_RST_CHECK_POS_ERR_INT_RAW = 0x100
	// Position of OUT_EOF_INT_RAW field.
	JPEG_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x9
	// Bit mask of OUT_EOF_INT_RAW field.
	JPEG_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x200
	// Bit OUT_EOF_INT_RAW.
	JPEG_INT_RAW_OUT_EOF_INT_RAW = 0x200
	// Position of SR_COLOR_MODE_ERR_INT_RAW field.
	JPEG_INT_RAW_SR_COLOR_MODE_ERR_INT_RAW_Pos = 0xa
	// Bit mask of SR_COLOR_MODE_ERR_INT_RAW field.
	JPEG_INT_RAW_SR_COLOR_MODE_ERR_INT_RAW_Msk = 0x400
	// Bit SR_COLOR_MODE_ERR_INT_RAW.
	JPEG_INT_RAW_SR_COLOR_MODE_ERR_INT_RAW = 0x400
	// Position of DCT_DONE_INT_RAW field.
	JPEG_INT_RAW_DCT_DONE_INT_RAW_Pos = 0xb
	// Bit mask of DCT_DONE_INT_RAW field.
	JPEG_INT_RAW_DCT_DONE_INT_RAW_Msk = 0x800
	// Bit DCT_DONE_INT_RAW.
	JPEG_INT_RAW_DCT_DONE_INT_RAW = 0x800
	// Position of BS_LAST_BLOCK_EOF_INT_RAW field.
	JPEG_INT_RAW_BS_LAST_BLOCK_EOF_INT_RAW_Pos = 0xc
	// Bit mask of BS_LAST_BLOCK_EOF_INT_RAW field.
	JPEG_INT_RAW_BS_LAST_BLOCK_EOF_INT_RAW_Msk = 0x1000
	// Bit BS_LAST_BLOCK_EOF_INT_RAW.
	JPEG_INT_RAW_BS_LAST_BLOCK_EOF_INT_RAW = 0x1000
	// Position of SCAN_CHECK_NONE_ERR_INT_RAW field.
	JPEG_INT_RAW_SCAN_CHECK_NONE_ERR_INT_RAW_Pos = 0xd
	// Bit mask of SCAN_CHECK_NONE_ERR_INT_RAW field.
	JPEG_INT_RAW_SCAN_CHECK_NONE_ERR_INT_RAW_Msk = 0x2000
	// Bit SCAN_CHECK_NONE_ERR_INT_RAW.
	JPEG_INT_RAW_SCAN_CHECK_NONE_ERR_INT_RAW = 0x2000
	// Position of SCAN_CHECK_POS_ERR_INT_RAW field.
	JPEG_INT_RAW_SCAN_CHECK_POS_ERR_INT_RAW_Pos = 0xe
	// Bit mask of SCAN_CHECK_POS_ERR_INT_RAW field.
	JPEG_INT_RAW_SCAN_CHECK_POS_ERR_INT_RAW_Msk = 0x4000
	// Bit SCAN_CHECK_POS_ERR_INT_RAW.
	JPEG_INT_RAW_SCAN_CHECK_POS_ERR_INT_RAW = 0x4000
	// Position of UXP_DET_INT_RAW field.
	JPEG_INT_RAW_UXP_DET_INT_RAW_Pos = 0xf
	// Bit mask of UXP_DET_INT_RAW field.
	JPEG_INT_RAW_UXP_DET_INT_RAW_Msk = 0x8000
	// Bit UXP_DET_INT_RAW.
	JPEG_INT_RAW_UXP_DET_INT_RAW = 0x8000
	// Position of EN_FRAME_EOF_ERR_INT_RAW field.
	JPEG_INT_RAW_EN_FRAME_EOF_ERR_INT_RAW_Pos = 0x10
	// Bit mask of EN_FRAME_EOF_ERR_INT_RAW field.
	JPEG_INT_RAW_EN_FRAME_EOF_ERR_INT_RAW_Msk = 0x10000
	// Bit EN_FRAME_EOF_ERR_INT_RAW.
	JPEG_INT_RAW_EN_FRAME_EOF_ERR_INT_RAW = 0x10000
	// Position of EN_FRAME_EOF_LACK_INT_RAW field.
	JPEG_INT_RAW_EN_FRAME_EOF_LACK_INT_RAW_Pos = 0x11
	// Bit mask of EN_FRAME_EOF_LACK_INT_RAW field.
	JPEG_INT_RAW_EN_FRAME_EOF_LACK_INT_RAW_Msk = 0x20000
	// Bit EN_FRAME_EOF_LACK_INT_RAW.
	JPEG_INT_RAW_EN_FRAME_EOF_LACK_INT_RAW = 0x20000
	// Position of DE_FRAME_EOF_ERR_INT_RAW field.
	JPEG_INT_RAW_DE_FRAME_EOF_ERR_INT_RAW_Pos = 0x12
	// Bit mask of DE_FRAME_EOF_ERR_INT_RAW field.
	JPEG_INT_RAW_DE_FRAME_EOF_ERR_INT_RAW_Msk = 0x40000
	// Bit DE_FRAME_EOF_ERR_INT_RAW.
	JPEG_INT_RAW_DE_FRAME_EOF_ERR_INT_RAW = 0x40000
	// Position of DE_FRAME_EOF_LACK_INT_RAW field.
	JPEG_INT_RAW_DE_FRAME_EOF_LACK_INT_RAW_Pos = 0x13
	// Bit mask of DE_FRAME_EOF_LACK_INT_RAW field.
	JPEG_INT_RAW_DE_FRAME_EOF_LACK_INT_RAW_Msk = 0x80000
	// Bit DE_FRAME_EOF_LACK_INT_RAW.
	JPEG_INT_RAW_DE_FRAME_EOF_LACK_INT_RAW = 0x80000
	// Position of SOS_UNMATCH_ERR_INT_RAW field.
	JPEG_INT_RAW_SOS_UNMATCH_ERR_INT_RAW_Pos = 0x14
	// Bit mask of SOS_UNMATCH_ERR_INT_RAW field.
	JPEG_INT_RAW_SOS_UNMATCH_ERR_INT_RAW_Msk = 0x100000
	// Bit SOS_UNMATCH_ERR_INT_RAW.
	JPEG_INT_RAW_SOS_UNMATCH_ERR_INT_RAW = 0x100000
	// Position of MARKER_ERR_FST_SCAN_INT_RAW field.
	JPEG_INT_RAW_MARKER_ERR_FST_SCAN_INT_RAW_Pos = 0x15
	// Bit mask of MARKER_ERR_FST_SCAN_INT_RAW field.
	JPEG_INT_RAW_MARKER_ERR_FST_SCAN_INT_RAW_Msk = 0x200000
	// Bit MARKER_ERR_FST_SCAN_INT_RAW.
	JPEG_INT_RAW_MARKER_ERR_FST_SCAN_INT_RAW = 0x200000
	// Position of MARKER_ERR_OTHER_SCAN_INT_RAW field.
	JPEG_INT_RAW_MARKER_ERR_OTHER_SCAN_INT_RAW_Pos = 0x16
	// Bit mask of MARKER_ERR_OTHER_SCAN_INT_RAW field.
	JPEG_INT_RAW_MARKER_ERR_OTHER_SCAN_INT_RAW_Msk = 0x400000
	// Bit MARKER_ERR_OTHER_SCAN_INT_RAW.
	JPEG_INT_RAW_MARKER_ERR_OTHER_SCAN_INT_RAW = 0x400000
	// Position of UNDET_INT_RAW field.
	JPEG_INT_RAW_UNDET_INT_RAW_Pos = 0x17
	// Bit mask of UNDET_INT_RAW field.
	JPEG_INT_RAW_UNDET_INT_RAW_Msk = 0x800000
	// Bit UNDET_INT_RAW.
	JPEG_INT_RAW_UNDET_INT_RAW = 0x800000
	// Position of DECODE_TIMEOUT_INT_RAW field.
	JPEG_INT_RAW_DECODE_TIMEOUT_INT_RAW_Pos = 0x18
	// Bit mask of DECODE_TIMEOUT_INT_RAW field.
	JPEG_INT_RAW_DECODE_TIMEOUT_INT_RAW_Msk = 0x1000000
	// Bit DECODE_TIMEOUT_INT_RAW.
	JPEG_INT_RAW_DECODE_TIMEOUT_INT_RAW = 0x1000000

	// INT_ENA: Interrupt enable registers
	// Position of DONE_INT_ENA field.
	JPEG_INT_ENA_DONE_INT_ENA_Pos = 0x0
	// Bit mask of DONE_INT_ENA field.
	JPEG_INT_ENA_DONE_INT_ENA_Msk = 0x1
	// Bit DONE_INT_ENA.
	JPEG_INT_ENA_DONE_INT_ENA = 0x1
	// Position of RLE_PARALLEL_ERR_INT_ENA field.
	JPEG_INT_ENA_RLE_PARALLEL_ERR_INT_ENA_Pos = 0x1
	// Bit mask of RLE_PARALLEL_ERR_INT_ENA field.
	JPEG_INT_ENA_RLE_PARALLEL_ERR_INT_ENA_Msk = 0x2
	// Bit RLE_PARALLEL_ERR_INT_ENA.
	JPEG_INT_ENA_RLE_PARALLEL_ERR_INT_ENA = 0x2
	// Position of CID_ERR_INT_ENA field.
	JPEG_INT_ENA_CID_ERR_INT_ENA_Pos = 0x2
	// Bit mask of CID_ERR_INT_ENA field.
	JPEG_INT_ENA_CID_ERR_INT_ENA_Msk = 0x4
	// Bit CID_ERR_INT_ENA.
	JPEG_INT_ENA_CID_ERR_INT_ENA = 0x4
	// Position of C_DHT_DC_ID_ERR_INT_ENA field.
	JPEG_INT_ENA_C_DHT_DC_ID_ERR_INT_ENA_Pos = 0x3
	// Bit mask of C_DHT_DC_ID_ERR_INT_ENA field.
	JPEG_INT_ENA_C_DHT_DC_ID_ERR_INT_ENA_Msk = 0x8
	// Bit C_DHT_DC_ID_ERR_INT_ENA.
	JPEG_INT_ENA_C_DHT_DC_ID_ERR_INT_ENA = 0x8
	// Position of C_DHT_AC_ID_ERR_INT_ENA field.
	JPEG_INT_ENA_C_DHT_AC_ID_ERR_INT_ENA_Pos = 0x4
	// Bit mask of C_DHT_AC_ID_ERR_INT_ENA field.
	JPEG_INT_ENA_C_DHT_AC_ID_ERR_INT_ENA_Msk = 0x10
	// Bit C_DHT_AC_ID_ERR_INT_ENA.
	JPEG_INT_ENA_C_DHT_AC_ID_ERR_INT_ENA = 0x10
	// Position of C_DQT_ID_ERR_INT_ENA field.
	JPEG_INT_ENA_C_DQT_ID_ERR_INT_ENA_Pos = 0x5
	// Bit mask of C_DQT_ID_ERR_INT_ENA field.
	JPEG_INT_ENA_C_DQT_ID_ERR_INT_ENA_Msk = 0x20
	// Bit C_DQT_ID_ERR_INT_ENA.
	JPEG_INT_ENA_C_DQT_ID_ERR_INT_ENA = 0x20
	// Position of RST_UXP_ERR_INT_ENA field.
	JPEG_INT_ENA_RST_UXP_ERR_INT_ENA_Pos = 0x6
	// Bit mask of RST_UXP_ERR_INT_ENA field.
	JPEG_INT_ENA_RST_UXP_ERR_INT_ENA_Msk = 0x40
	// Bit RST_UXP_ERR_INT_ENA.
	JPEG_INT_ENA_RST_UXP_ERR_INT_ENA = 0x40
	// Position of RST_CHECK_NONE_ERR_INT_ENA field.
	JPEG_INT_ENA_RST_CHECK_NONE_ERR_INT_ENA_Pos = 0x7
	// Bit mask of RST_CHECK_NONE_ERR_INT_ENA field.
	JPEG_INT_ENA_RST_CHECK_NONE_ERR_INT_ENA_Msk = 0x80
	// Bit RST_CHECK_NONE_ERR_INT_ENA.
	JPEG_INT_ENA_RST_CHECK_NONE_ERR_INT_ENA = 0x80
	// Position of RST_CHECK_POS_ERR_INT_ENA field.
	JPEG_INT_ENA_RST_CHECK_POS_ERR_INT_ENA_Pos = 0x8
	// Bit mask of RST_CHECK_POS_ERR_INT_ENA field.
	JPEG_INT_ENA_RST_CHECK_POS_ERR_INT_ENA_Msk = 0x100
	// Bit RST_CHECK_POS_ERR_INT_ENA.
	JPEG_INT_ENA_RST_CHECK_POS_ERR_INT_ENA = 0x100
	// Position of OUT_EOF_INT_ENA field.
	JPEG_INT_ENA_OUT_EOF_INT_ENA_Pos = 0x9
	// Bit mask of OUT_EOF_INT_ENA field.
	JPEG_INT_ENA_OUT_EOF_INT_ENA_Msk = 0x200
	// Bit OUT_EOF_INT_ENA.
	JPEG_INT_ENA_OUT_EOF_INT_ENA = 0x200
	// Position of SR_COLOR_MODE_ERR_INT_ENA field.
	JPEG_INT_ENA_SR_COLOR_MODE_ERR_INT_ENA_Pos = 0xa
	// Bit mask of SR_COLOR_MODE_ERR_INT_ENA field.
	JPEG_INT_ENA_SR_COLOR_MODE_ERR_INT_ENA_Msk = 0x400
	// Bit SR_COLOR_MODE_ERR_INT_ENA.
	JPEG_INT_ENA_SR_COLOR_MODE_ERR_INT_ENA = 0x400
	// Position of DCT_DONE_INT_ENA field.
	JPEG_INT_ENA_DCT_DONE_INT_ENA_Pos = 0xb
	// Bit mask of DCT_DONE_INT_ENA field.
	JPEG_INT_ENA_DCT_DONE_INT_ENA_Msk = 0x800
	// Bit DCT_DONE_INT_ENA.
	JPEG_INT_ENA_DCT_DONE_INT_ENA = 0x800
	// Position of BS_LAST_BLOCK_EOF_INT_ENA field.
	JPEG_INT_ENA_BS_LAST_BLOCK_EOF_INT_ENA_Pos = 0xc
	// Bit mask of BS_LAST_BLOCK_EOF_INT_ENA field.
	JPEG_INT_ENA_BS_LAST_BLOCK_EOF_INT_ENA_Msk = 0x1000
	// Bit BS_LAST_BLOCK_EOF_INT_ENA.
	JPEG_INT_ENA_BS_LAST_BLOCK_EOF_INT_ENA = 0x1000
	// Position of SCAN_CHECK_NONE_ERR_INT_ENA field.
	JPEG_INT_ENA_SCAN_CHECK_NONE_ERR_INT_ENA_Pos = 0xd
	// Bit mask of SCAN_CHECK_NONE_ERR_INT_ENA field.
	JPEG_INT_ENA_SCAN_CHECK_NONE_ERR_INT_ENA_Msk = 0x2000
	// Bit SCAN_CHECK_NONE_ERR_INT_ENA.
	JPEG_INT_ENA_SCAN_CHECK_NONE_ERR_INT_ENA = 0x2000
	// Position of SCAN_CHECK_POS_ERR_INT_ENA field.
	JPEG_INT_ENA_SCAN_CHECK_POS_ERR_INT_ENA_Pos = 0xe
	// Bit mask of SCAN_CHECK_POS_ERR_INT_ENA field.
	JPEG_INT_ENA_SCAN_CHECK_POS_ERR_INT_ENA_Msk = 0x4000
	// Bit SCAN_CHECK_POS_ERR_INT_ENA.
	JPEG_INT_ENA_SCAN_CHECK_POS_ERR_INT_ENA = 0x4000
	// Position of UXP_DET_INT_ENA field.
	JPEG_INT_ENA_UXP_DET_INT_ENA_Pos = 0xf
	// Bit mask of UXP_DET_INT_ENA field.
	JPEG_INT_ENA_UXP_DET_INT_ENA_Msk = 0x8000
	// Bit UXP_DET_INT_ENA.
	JPEG_INT_ENA_UXP_DET_INT_ENA = 0x8000
	// Position of EN_FRAME_EOF_ERR_INT_ENA field.
	JPEG_INT_ENA_EN_FRAME_EOF_ERR_INT_ENA_Pos = 0x10
	// Bit mask of EN_FRAME_EOF_ERR_INT_ENA field.
	JPEG_INT_ENA_EN_FRAME_EOF_ERR_INT_ENA_Msk = 0x10000
	// Bit EN_FRAME_EOF_ERR_INT_ENA.
	JPEG_INT_ENA_EN_FRAME_EOF_ERR_INT_ENA = 0x10000
	// Position of EN_FRAME_EOF_LACK_INT_ENA field.
	JPEG_INT_ENA_EN_FRAME_EOF_LACK_INT_ENA_Pos = 0x11
	// Bit mask of EN_FRAME_EOF_LACK_INT_ENA field.
	JPEG_INT_ENA_EN_FRAME_EOF_LACK_INT_ENA_Msk = 0x20000
	// Bit EN_FRAME_EOF_LACK_INT_ENA.
	JPEG_INT_ENA_EN_FRAME_EOF_LACK_INT_ENA = 0x20000
	// Position of DE_FRAME_EOF_ERR_INT_ENA field.
	JPEG_INT_ENA_DE_FRAME_EOF_ERR_INT_ENA_Pos = 0x12
	// Bit mask of DE_FRAME_EOF_ERR_INT_ENA field.
	JPEG_INT_ENA_DE_FRAME_EOF_ERR_INT_ENA_Msk = 0x40000
	// Bit DE_FRAME_EOF_ERR_INT_ENA.
	JPEG_INT_ENA_DE_FRAME_EOF_ERR_INT_ENA = 0x40000
	// Position of DE_FRAME_EOF_LACK_INT_ENA field.
	JPEG_INT_ENA_DE_FRAME_EOF_LACK_INT_ENA_Pos = 0x13
	// Bit mask of DE_FRAME_EOF_LACK_INT_ENA field.
	JPEG_INT_ENA_DE_FRAME_EOF_LACK_INT_ENA_Msk = 0x80000
	// Bit DE_FRAME_EOF_LACK_INT_ENA.
	JPEG_INT_ENA_DE_FRAME_EOF_LACK_INT_ENA = 0x80000
	// Position of SOS_UNMATCH_ERR_INT_ENA field.
	JPEG_INT_ENA_SOS_UNMATCH_ERR_INT_ENA_Pos = 0x14
	// Bit mask of SOS_UNMATCH_ERR_INT_ENA field.
	JPEG_INT_ENA_SOS_UNMATCH_ERR_INT_ENA_Msk = 0x100000
	// Bit SOS_UNMATCH_ERR_INT_ENA.
	JPEG_INT_ENA_SOS_UNMATCH_ERR_INT_ENA = 0x100000
	// Position of MARKER_ERR_FST_SCAN_INT_ENA field.
	JPEG_INT_ENA_MARKER_ERR_FST_SCAN_INT_ENA_Pos = 0x15
	// Bit mask of MARKER_ERR_FST_SCAN_INT_ENA field.
	JPEG_INT_ENA_MARKER_ERR_FST_SCAN_INT_ENA_Msk = 0x200000
	// Bit MARKER_ERR_FST_SCAN_INT_ENA.
	JPEG_INT_ENA_MARKER_ERR_FST_SCAN_INT_ENA = 0x200000
	// Position of MARKER_ERR_OTHER_SCAN_INT_ENA field.
	JPEG_INT_ENA_MARKER_ERR_OTHER_SCAN_INT_ENA_Pos = 0x16
	// Bit mask of MARKER_ERR_OTHER_SCAN_INT_ENA field.
	JPEG_INT_ENA_MARKER_ERR_OTHER_SCAN_INT_ENA_Msk = 0x400000
	// Bit MARKER_ERR_OTHER_SCAN_INT_ENA.
	JPEG_INT_ENA_MARKER_ERR_OTHER_SCAN_INT_ENA = 0x400000
	// Position of UNDET_INT_ENA field.
	JPEG_INT_ENA_UNDET_INT_ENA_Pos = 0x17
	// Bit mask of UNDET_INT_ENA field.
	JPEG_INT_ENA_UNDET_INT_ENA_Msk = 0x800000
	// Bit UNDET_INT_ENA.
	JPEG_INT_ENA_UNDET_INT_ENA = 0x800000
	// Position of DECODE_TIMEOUT_INT_ENA field.
	JPEG_INT_ENA_DECODE_TIMEOUT_INT_ENA_Pos = 0x18
	// Bit mask of DECODE_TIMEOUT_INT_ENA field.
	JPEG_INT_ENA_DECODE_TIMEOUT_INT_ENA_Msk = 0x1000000
	// Bit DECODE_TIMEOUT_INT_ENA.
	JPEG_INT_ENA_DECODE_TIMEOUT_INT_ENA = 0x1000000

	// INT_ST: Interrupt status registers
	// Position of DONE_INT_ST field.
	JPEG_INT_ST_DONE_INT_ST_Pos = 0x0
	// Bit mask of DONE_INT_ST field.
	JPEG_INT_ST_DONE_INT_ST_Msk = 0x1
	// Bit DONE_INT_ST.
	JPEG_INT_ST_DONE_INT_ST = 0x1
	// Position of RLE_PARALLEL_ERR_INT_ST field.
	JPEG_INT_ST_RLE_PARALLEL_ERR_INT_ST_Pos = 0x1
	// Bit mask of RLE_PARALLEL_ERR_INT_ST field.
	JPEG_INT_ST_RLE_PARALLEL_ERR_INT_ST_Msk = 0x2
	// Bit RLE_PARALLEL_ERR_INT_ST.
	JPEG_INT_ST_RLE_PARALLEL_ERR_INT_ST = 0x2
	// Position of CID_ERR_INT_ST field.
	JPEG_INT_ST_CID_ERR_INT_ST_Pos = 0x2
	// Bit mask of CID_ERR_INT_ST field.
	JPEG_INT_ST_CID_ERR_INT_ST_Msk = 0x4
	// Bit CID_ERR_INT_ST.
	JPEG_INT_ST_CID_ERR_INT_ST = 0x4
	// Position of C_DHT_DC_ID_ERR_INT_ST field.
	JPEG_INT_ST_C_DHT_DC_ID_ERR_INT_ST_Pos = 0x3
	// Bit mask of C_DHT_DC_ID_ERR_INT_ST field.
	JPEG_INT_ST_C_DHT_DC_ID_ERR_INT_ST_Msk = 0x8
	// Bit C_DHT_DC_ID_ERR_INT_ST.
	JPEG_INT_ST_C_DHT_DC_ID_ERR_INT_ST = 0x8
	// Position of C_DHT_AC_ID_ERR_INT_ST field.
	JPEG_INT_ST_C_DHT_AC_ID_ERR_INT_ST_Pos = 0x4
	// Bit mask of C_DHT_AC_ID_ERR_INT_ST field.
	JPEG_INT_ST_C_DHT_AC_ID_ERR_INT_ST_Msk = 0x10
	// Bit C_DHT_AC_ID_ERR_INT_ST.
	JPEG_INT_ST_C_DHT_AC_ID_ERR_INT_ST = 0x10
	// Position of C_DQT_ID_ERR_INT_ST field.
	JPEG_INT_ST_C_DQT_ID_ERR_INT_ST_Pos = 0x5
	// Bit mask of C_DQT_ID_ERR_INT_ST field.
	JPEG_INT_ST_C_DQT_ID_ERR_INT_ST_Msk = 0x20
	// Bit C_DQT_ID_ERR_INT_ST.
	JPEG_INT_ST_C_DQT_ID_ERR_INT_ST = 0x20
	// Position of RST_UXP_ERR_INT_ST field.
	JPEG_INT_ST_RST_UXP_ERR_INT_ST_Pos = 0x6
	// Bit mask of RST_UXP_ERR_INT_ST field.
	JPEG_INT_ST_RST_UXP_ERR_INT_ST_Msk = 0x40
	// Bit RST_UXP_ERR_INT_ST.
	JPEG_INT_ST_RST_UXP_ERR_INT_ST = 0x40
	// Position of RST_CHECK_NONE_ERR_INT_ST field.
	JPEG_INT_ST_RST_CHECK_NONE_ERR_INT_ST_Pos = 0x7
	// Bit mask of RST_CHECK_NONE_ERR_INT_ST field.
	JPEG_INT_ST_RST_CHECK_NONE_ERR_INT_ST_Msk = 0x80
	// Bit RST_CHECK_NONE_ERR_INT_ST.
	JPEG_INT_ST_RST_CHECK_NONE_ERR_INT_ST = 0x80
	// Position of RST_CHECK_POS_ERR_INT_ST field.
	JPEG_INT_ST_RST_CHECK_POS_ERR_INT_ST_Pos = 0x8
	// Bit mask of RST_CHECK_POS_ERR_INT_ST field.
	JPEG_INT_ST_RST_CHECK_POS_ERR_INT_ST_Msk = 0x100
	// Bit RST_CHECK_POS_ERR_INT_ST.
	JPEG_INT_ST_RST_CHECK_POS_ERR_INT_ST = 0x100
	// Position of OUT_EOF_INT_ST field.
	JPEG_INT_ST_OUT_EOF_INT_ST_Pos = 0x9
	// Bit mask of OUT_EOF_INT_ST field.
	JPEG_INT_ST_OUT_EOF_INT_ST_Msk = 0x200
	// Bit OUT_EOF_INT_ST.
	JPEG_INT_ST_OUT_EOF_INT_ST = 0x200
	// Position of SR_COLOR_MODE_ERR_INT_ST field.
	JPEG_INT_ST_SR_COLOR_MODE_ERR_INT_ST_Pos = 0xa
	// Bit mask of SR_COLOR_MODE_ERR_INT_ST field.
	JPEG_INT_ST_SR_COLOR_MODE_ERR_INT_ST_Msk = 0x400
	// Bit SR_COLOR_MODE_ERR_INT_ST.
	JPEG_INT_ST_SR_COLOR_MODE_ERR_INT_ST = 0x400
	// Position of DCT_DONE_INT_ST field.
	JPEG_INT_ST_DCT_DONE_INT_ST_Pos = 0xb
	// Bit mask of DCT_DONE_INT_ST field.
	JPEG_INT_ST_DCT_DONE_INT_ST_Msk = 0x800
	// Bit DCT_DONE_INT_ST.
	JPEG_INT_ST_DCT_DONE_INT_ST = 0x800
	// Position of BS_LAST_BLOCK_EOF_INT_ST field.
	JPEG_INT_ST_BS_LAST_BLOCK_EOF_INT_ST_Pos = 0xc
	// Bit mask of BS_LAST_BLOCK_EOF_INT_ST field.
	JPEG_INT_ST_BS_LAST_BLOCK_EOF_INT_ST_Msk = 0x1000
	// Bit BS_LAST_BLOCK_EOF_INT_ST.
	JPEG_INT_ST_BS_LAST_BLOCK_EOF_INT_ST = 0x1000
	// Position of SCAN_CHECK_NONE_ERR_INT_ST field.
	JPEG_INT_ST_SCAN_CHECK_NONE_ERR_INT_ST_Pos = 0xd
	// Bit mask of SCAN_CHECK_NONE_ERR_INT_ST field.
	JPEG_INT_ST_SCAN_CHECK_NONE_ERR_INT_ST_Msk = 0x2000
	// Bit SCAN_CHECK_NONE_ERR_INT_ST.
	JPEG_INT_ST_SCAN_CHECK_NONE_ERR_INT_ST = 0x2000
	// Position of SCAN_CHECK_POS_ERR_INT_ST field.
	JPEG_INT_ST_SCAN_CHECK_POS_ERR_INT_ST_Pos = 0xe
	// Bit mask of SCAN_CHECK_POS_ERR_INT_ST field.
	JPEG_INT_ST_SCAN_CHECK_POS_ERR_INT_ST_Msk = 0x4000
	// Bit SCAN_CHECK_POS_ERR_INT_ST.
	JPEG_INT_ST_SCAN_CHECK_POS_ERR_INT_ST = 0x4000
	// Position of UXP_DET_INT_ST field.
	JPEG_INT_ST_UXP_DET_INT_ST_Pos = 0xf
	// Bit mask of UXP_DET_INT_ST field.
	JPEG_INT_ST_UXP_DET_INT_ST_Msk = 0x8000
	// Bit UXP_DET_INT_ST.
	JPEG_INT_ST_UXP_DET_INT_ST = 0x8000
	// Position of EN_FRAME_EOF_ERR_INT_ST field.
	JPEG_INT_ST_EN_FRAME_EOF_ERR_INT_ST_Pos = 0x10
	// Bit mask of EN_FRAME_EOF_ERR_INT_ST field.
	JPEG_INT_ST_EN_FRAME_EOF_ERR_INT_ST_Msk = 0x10000
	// Bit EN_FRAME_EOF_ERR_INT_ST.
	JPEG_INT_ST_EN_FRAME_EOF_ERR_INT_ST = 0x10000
	// Position of EN_FRAME_EOF_LACK_INT_ST field.
	JPEG_INT_ST_EN_FRAME_EOF_LACK_INT_ST_Pos = 0x11
	// Bit mask of EN_FRAME_EOF_LACK_INT_ST field.
	JPEG_INT_ST_EN_FRAME_EOF_LACK_INT_ST_Msk = 0x20000
	// Bit EN_FRAME_EOF_LACK_INT_ST.
	JPEG_INT_ST_EN_FRAME_EOF_LACK_INT_ST = 0x20000
	// Position of DE_FRAME_EOF_ERR_INT_ST field.
	JPEG_INT_ST_DE_FRAME_EOF_ERR_INT_ST_Pos = 0x12
	// Bit mask of DE_FRAME_EOF_ERR_INT_ST field.
	JPEG_INT_ST_DE_FRAME_EOF_ERR_INT_ST_Msk = 0x40000
	// Bit DE_FRAME_EOF_ERR_INT_ST.
	JPEG_INT_ST_DE_FRAME_EOF_ERR_INT_ST = 0x40000
	// Position of DE_FRAME_EOF_LACK_INT_ST field.
	JPEG_INT_ST_DE_FRAME_EOF_LACK_INT_ST_Pos = 0x13
	// Bit mask of DE_FRAME_EOF_LACK_INT_ST field.
	JPEG_INT_ST_DE_FRAME_EOF_LACK_INT_ST_Msk = 0x80000
	// Bit DE_FRAME_EOF_LACK_INT_ST.
	JPEG_INT_ST_DE_FRAME_EOF_LACK_INT_ST = 0x80000
	// Position of SOS_UNMATCH_ERR_INT_ST field.
	JPEG_INT_ST_SOS_UNMATCH_ERR_INT_ST_Pos = 0x14
	// Bit mask of SOS_UNMATCH_ERR_INT_ST field.
	JPEG_INT_ST_SOS_UNMATCH_ERR_INT_ST_Msk = 0x100000
	// Bit SOS_UNMATCH_ERR_INT_ST.
	JPEG_INT_ST_SOS_UNMATCH_ERR_INT_ST = 0x100000
	// Position of MARKER_ERR_FST_SCAN_INT_ST field.
	JPEG_INT_ST_MARKER_ERR_FST_SCAN_INT_ST_Pos = 0x15
	// Bit mask of MARKER_ERR_FST_SCAN_INT_ST field.
	JPEG_INT_ST_MARKER_ERR_FST_SCAN_INT_ST_Msk = 0x200000
	// Bit MARKER_ERR_FST_SCAN_INT_ST.
	JPEG_INT_ST_MARKER_ERR_FST_SCAN_INT_ST = 0x200000
	// Position of MARKER_ERR_OTHER_SCAN_INT_ST field.
	JPEG_INT_ST_MARKER_ERR_OTHER_SCAN_INT_ST_Pos = 0x16
	// Bit mask of MARKER_ERR_OTHER_SCAN_INT_ST field.
	JPEG_INT_ST_MARKER_ERR_OTHER_SCAN_INT_ST_Msk = 0x400000
	// Bit MARKER_ERR_OTHER_SCAN_INT_ST.
	JPEG_INT_ST_MARKER_ERR_OTHER_SCAN_INT_ST = 0x400000
	// Position of UNDET_INT_ST field.
	JPEG_INT_ST_UNDET_INT_ST_Pos = 0x17
	// Bit mask of UNDET_INT_ST field.
	JPEG_INT_ST_UNDET_INT_ST_Msk = 0x800000
	// Bit UNDET_INT_ST.
	JPEG_INT_ST_UNDET_INT_ST = 0x800000
	// Position of DECODE_TIMEOUT_INT_ST field.
	JPEG_INT_ST_DECODE_TIMEOUT_INT_ST_Pos = 0x18
	// Bit mask of DECODE_TIMEOUT_INT_ST field.
	JPEG_INT_ST_DECODE_TIMEOUT_INT_ST_Msk = 0x1000000
	// Bit DECODE_TIMEOUT_INT_ST.
	JPEG_INT_ST_DECODE_TIMEOUT_INT_ST = 0x1000000

	// INT_CLR: Interrupt clear registers
	// Position of DONE_INT_CLR field.
	JPEG_INT_CLR_DONE_INT_CLR_Pos = 0x0
	// Bit mask of DONE_INT_CLR field.
	JPEG_INT_CLR_DONE_INT_CLR_Msk = 0x1
	// Bit DONE_INT_CLR.
	JPEG_INT_CLR_DONE_INT_CLR = 0x1
	// Position of RLE_PARALLEL_ERR_INT_CLR field.
	JPEG_INT_CLR_RLE_PARALLEL_ERR_INT_CLR_Pos = 0x1
	// Bit mask of RLE_PARALLEL_ERR_INT_CLR field.
	JPEG_INT_CLR_RLE_PARALLEL_ERR_INT_CLR_Msk = 0x2
	// Bit RLE_PARALLEL_ERR_INT_CLR.
	JPEG_INT_CLR_RLE_PARALLEL_ERR_INT_CLR = 0x2
	// Position of CID_ERR_INT_CLR field.
	JPEG_INT_CLR_CID_ERR_INT_CLR_Pos = 0x2
	// Bit mask of CID_ERR_INT_CLR field.
	JPEG_INT_CLR_CID_ERR_INT_CLR_Msk = 0x4
	// Bit CID_ERR_INT_CLR.
	JPEG_INT_CLR_CID_ERR_INT_CLR = 0x4
	// Position of C_DHT_DC_ID_ERR_INT_CLR field.
	JPEG_INT_CLR_C_DHT_DC_ID_ERR_INT_CLR_Pos = 0x3
	// Bit mask of C_DHT_DC_ID_ERR_INT_CLR field.
	JPEG_INT_CLR_C_DHT_DC_ID_ERR_INT_CLR_Msk = 0x8
	// Bit C_DHT_DC_ID_ERR_INT_CLR.
	JPEG_INT_CLR_C_DHT_DC_ID_ERR_INT_CLR = 0x8
	// Position of C_DHT_AC_ID_ERR_INT_CLR field.
	JPEG_INT_CLR_C_DHT_AC_ID_ERR_INT_CLR_Pos = 0x4
	// Bit mask of C_DHT_AC_ID_ERR_INT_CLR field.
	JPEG_INT_CLR_C_DHT_AC_ID_ERR_INT_CLR_Msk = 0x10
	// Bit C_DHT_AC_ID_ERR_INT_CLR.
	JPEG_INT_CLR_C_DHT_AC_ID_ERR_INT_CLR = 0x10
	// Position of C_DQT_ID_ERR_INT_CLR field.
	JPEG_INT_CLR_C_DQT_ID_ERR_INT_CLR_Pos = 0x5
	// Bit mask of C_DQT_ID_ERR_INT_CLR field.
	JPEG_INT_CLR_C_DQT_ID_ERR_INT_CLR_Msk = 0x20
	// Bit C_DQT_ID_ERR_INT_CLR.
	JPEG_INT_CLR_C_DQT_ID_ERR_INT_CLR = 0x20
	// Position of RST_UXP_ERR_INT_CLR field.
	JPEG_INT_CLR_RST_UXP_ERR_INT_CLR_Pos = 0x6
	// Bit mask of RST_UXP_ERR_INT_CLR field.
	JPEG_INT_CLR_RST_UXP_ERR_INT_CLR_Msk = 0x40
	// Bit RST_UXP_ERR_INT_CLR.
	JPEG_INT_CLR_RST_UXP_ERR_INT_CLR = 0x40
	// Position of RST_CHECK_NONE_ERR_INT_CLR field.
	JPEG_INT_CLR_RST_CHECK_NONE_ERR_INT_CLR_Pos = 0x7
	// Bit mask of RST_CHECK_NONE_ERR_INT_CLR field.
	JPEG_INT_CLR_RST_CHECK_NONE_ERR_INT_CLR_Msk = 0x80
	// Bit RST_CHECK_NONE_ERR_INT_CLR.
	JPEG_INT_CLR_RST_CHECK_NONE_ERR_INT_CLR = 0x80
	// Position of RST_CHECK_POS_ERR_INT_CLR field.
	JPEG_INT_CLR_RST_CHECK_POS_ERR_INT_CLR_Pos = 0x8
	// Bit mask of RST_CHECK_POS_ERR_INT_CLR field.
	JPEG_INT_CLR_RST_CHECK_POS_ERR_INT_CLR_Msk = 0x100
	// Bit RST_CHECK_POS_ERR_INT_CLR.
	JPEG_INT_CLR_RST_CHECK_POS_ERR_INT_CLR = 0x100
	// Position of OUT_EOF_INT_CLR field.
	JPEG_INT_CLR_OUT_EOF_INT_CLR_Pos = 0x9
	// Bit mask of OUT_EOF_INT_CLR field.
	JPEG_INT_CLR_OUT_EOF_INT_CLR_Msk = 0x200
	// Bit OUT_EOF_INT_CLR.
	JPEG_INT_CLR_OUT_EOF_INT_CLR = 0x200
	// Position of SR_COLOR_MODE_ERR_INT_CLR field.
	JPEG_INT_CLR_SR_COLOR_MODE_ERR_INT_CLR_Pos = 0xa
	// Bit mask of SR_COLOR_MODE_ERR_INT_CLR field.
	JPEG_INT_CLR_SR_COLOR_MODE_ERR_INT_CLR_Msk = 0x400
	// Bit SR_COLOR_MODE_ERR_INT_CLR.
	JPEG_INT_CLR_SR_COLOR_MODE_ERR_INT_CLR = 0x400
	// Position of DCT_DONE_INT_CLR field.
	JPEG_INT_CLR_DCT_DONE_INT_CLR_Pos = 0xb
	// Bit mask of DCT_DONE_INT_CLR field.
	JPEG_INT_CLR_DCT_DONE_INT_CLR_Msk = 0x800
	// Bit DCT_DONE_INT_CLR.
	JPEG_INT_CLR_DCT_DONE_INT_CLR = 0x800
	// Position of BS_LAST_BLOCK_EOF_INT_CLR field.
	JPEG_INT_CLR_BS_LAST_BLOCK_EOF_INT_CLR_Pos = 0xc
	// Bit mask of BS_LAST_BLOCK_EOF_INT_CLR field.
	JPEG_INT_CLR_BS_LAST_BLOCK_EOF_INT_CLR_Msk = 0x1000
	// Bit BS_LAST_BLOCK_EOF_INT_CLR.
	JPEG_INT_CLR_BS_LAST_BLOCK_EOF_INT_CLR = 0x1000
	// Position of SCAN_CHECK_NONE_ERR_INT_CLR field.
	JPEG_INT_CLR_SCAN_CHECK_NONE_ERR_INT_CLR_Pos = 0xd
	// Bit mask of SCAN_CHECK_NONE_ERR_INT_CLR field.
	JPEG_INT_CLR_SCAN_CHECK_NONE_ERR_INT_CLR_Msk = 0x2000
	// Bit SCAN_CHECK_NONE_ERR_INT_CLR.
	JPEG_INT_CLR_SCAN_CHECK_NONE_ERR_INT_CLR = 0x2000
	// Position of SCAN_CHECK_POS_ERR_INT_CLR field.
	JPEG_INT_CLR_SCAN_CHECK_POS_ERR_INT_CLR_Pos = 0xe
	// Bit mask of SCAN_CHECK_POS_ERR_INT_CLR field.
	JPEG_INT_CLR_SCAN_CHECK_POS_ERR_INT_CLR_Msk = 0x4000
	// Bit SCAN_CHECK_POS_ERR_INT_CLR.
	JPEG_INT_CLR_SCAN_CHECK_POS_ERR_INT_CLR = 0x4000
	// Position of UXP_DET_INT_CLR field.
	JPEG_INT_CLR_UXP_DET_INT_CLR_Pos = 0xf
	// Bit mask of UXP_DET_INT_CLR field.
	JPEG_INT_CLR_UXP_DET_INT_CLR_Msk = 0x8000
	// Bit UXP_DET_INT_CLR.
	JPEG_INT_CLR_UXP_DET_INT_CLR = 0x8000
	// Position of EN_FRAME_EOF_ERR_INT_CLR field.
	JPEG_INT_CLR_EN_FRAME_EOF_ERR_INT_CLR_Pos = 0x10
	// Bit mask of EN_FRAME_EOF_ERR_INT_CLR field.
	JPEG_INT_CLR_EN_FRAME_EOF_ERR_INT_CLR_Msk = 0x10000
	// Bit EN_FRAME_EOF_ERR_INT_CLR.
	JPEG_INT_CLR_EN_FRAME_EOF_ERR_INT_CLR = 0x10000
	// Position of EN_FRAME_EOF_LACK_INT_CLR field.
	JPEG_INT_CLR_EN_FRAME_EOF_LACK_INT_CLR_Pos = 0x11
	// Bit mask of EN_FRAME_EOF_LACK_INT_CLR field.
	JPEG_INT_CLR_EN_FRAME_EOF_LACK_INT_CLR_Msk = 0x20000
	// Bit EN_FRAME_EOF_LACK_INT_CLR.
	JPEG_INT_CLR_EN_FRAME_EOF_LACK_INT_CLR = 0x20000
	// Position of DE_FRAME_EOF_ERR_INT_CLR field.
	JPEG_INT_CLR_DE_FRAME_EOF_ERR_INT_CLR_Pos = 0x12
	// Bit mask of DE_FRAME_EOF_ERR_INT_CLR field.
	JPEG_INT_CLR_DE_FRAME_EOF_ERR_INT_CLR_Msk = 0x40000
	// Bit DE_FRAME_EOF_ERR_INT_CLR.
	JPEG_INT_CLR_DE_FRAME_EOF_ERR_INT_CLR = 0x40000
	// Position of DE_FRAME_EOF_LACK_INT_CLR field.
	JPEG_INT_CLR_DE_FRAME_EOF_LACK_INT_CLR_Pos = 0x13
	// Bit mask of DE_FRAME_EOF_LACK_INT_CLR field.
	JPEG_INT_CLR_DE_FRAME_EOF_LACK_INT_CLR_Msk = 0x80000
	// Bit DE_FRAME_EOF_LACK_INT_CLR.
	JPEG_INT_CLR_DE_FRAME_EOF_LACK_INT_CLR = 0x80000
	// Position of SOS_UNMATCH_ERR_INT_CLR field.
	JPEG_INT_CLR_SOS_UNMATCH_ERR_INT_CLR_Pos = 0x14
	// Bit mask of SOS_UNMATCH_ERR_INT_CLR field.
	JPEG_INT_CLR_SOS_UNMATCH_ERR_INT_CLR_Msk = 0x100000
	// Bit SOS_UNMATCH_ERR_INT_CLR.
	JPEG_INT_CLR_SOS_UNMATCH_ERR_INT_CLR = 0x100000
	// Position of MARKER_ERR_FST_SCAN_INT_CLR field.
	JPEG_INT_CLR_MARKER_ERR_FST_SCAN_INT_CLR_Pos = 0x15
	// Bit mask of MARKER_ERR_FST_SCAN_INT_CLR field.
	JPEG_INT_CLR_MARKER_ERR_FST_SCAN_INT_CLR_Msk = 0x200000
	// Bit MARKER_ERR_FST_SCAN_INT_CLR.
	JPEG_INT_CLR_MARKER_ERR_FST_SCAN_INT_CLR = 0x200000
	// Position of MARKER_ERR_OTHER_SCAN_INT_CLR field.
	JPEG_INT_CLR_MARKER_ERR_OTHER_SCAN_INT_CLR_Pos = 0x16
	// Bit mask of MARKER_ERR_OTHER_SCAN_INT_CLR field.
	JPEG_INT_CLR_MARKER_ERR_OTHER_SCAN_INT_CLR_Msk = 0x400000
	// Bit MARKER_ERR_OTHER_SCAN_INT_CLR.
	JPEG_INT_CLR_MARKER_ERR_OTHER_SCAN_INT_CLR = 0x400000
	// Position of UNDET_INT_CLR field.
	JPEG_INT_CLR_UNDET_INT_CLR_Pos = 0x17
	// Bit mask of UNDET_INT_CLR field.
	JPEG_INT_CLR_UNDET_INT_CLR_Msk = 0x800000
	// Bit UNDET_INT_CLR.
	JPEG_INT_CLR_UNDET_INT_CLR = 0x800000
	// Position of DECODE_TIMEOUT_INT_CLR field.
	JPEG_INT_CLR_DECODE_TIMEOUT_INT_CLR_Pos = 0x18
	// Bit mask of DECODE_TIMEOUT_INT_CLR field.
	JPEG_INT_CLR_DECODE_TIMEOUT_INT_CLR_Msk = 0x1000000
	// Bit DECODE_TIMEOUT_INT_CLR.
	JPEG_INT_CLR_DECODE_TIMEOUT_INT_CLR = 0x1000000

	// STATUS0: Trace and Debug registers
	// Position of BITSTREAM_EOF_VLD_CNT field.
	JPEG_STATUS0_BITSTREAM_EOF_VLD_CNT_Pos = 0xb
	// Bit mask of BITSTREAM_EOF_VLD_CNT field.
	JPEG_STATUS0_BITSTREAM_EOF_VLD_CNT_Msk = 0x1f800
	// Position of DCTOUT_ZZSCAN_ADDR field.
	JPEG_STATUS0_DCTOUT_ZZSCAN_ADDR_Pos = 0x11
	// Bit mask of DCTOUT_ZZSCAN_ADDR field.
	JPEG_STATUS0_DCTOUT_ZZSCAN_ADDR_Msk = 0x7e0000
	// Position of QNRVAL_ZZSCAN_ADDR field.
	JPEG_STATUS0_QNRVAL_ZZSCAN_ADDR_Pos = 0x17
	// Bit mask of QNRVAL_ZZSCAN_ADDR field.
	JPEG_STATUS0_QNRVAL_ZZSCAN_ADDR_Msk = 0x1f800000
	// Position of REG_STATE_YUV field.
	JPEG_STATUS0_REG_STATE_YUV_Pos = 0x1d
	// Bit mask of REG_STATE_YUV field.
	JPEG_STATUS0_REG_STATE_YUV_Msk = 0xe0000000

	// STATUS2: Trace and Debug registers
	// Position of SOURCE_PIXEL field.
	JPEG_STATUS2_SOURCE_PIXEL_Pos = 0x0
	// Bit mask of SOURCE_PIXEL field.
	JPEG_STATUS2_SOURCE_PIXEL_Msk = 0xffffff
	// Position of LAST_BLOCK field.
	JPEG_STATUS2_LAST_BLOCK_Pos = 0x18
	// Bit mask of LAST_BLOCK field.
	JPEG_STATUS2_LAST_BLOCK_Msk = 0x1000000
	// Bit LAST_BLOCK.
	JPEG_STATUS2_LAST_BLOCK = 0x1000000
	// Position of LAST_MCU field.
	JPEG_STATUS2_LAST_MCU_Pos = 0x19
	// Bit mask of LAST_MCU field.
	JPEG_STATUS2_LAST_MCU_Msk = 0x2000000
	// Bit LAST_MCU.
	JPEG_STATUS2_LAST_MCU = 0x2000000
	// Position of LAST_DC field.
	JPEG_STATUS2_LAST_DC_Pos = 0x1a
	// Bit mask of LAST_DC field.
	JPEG_STATUS2_LAST_DC_Msk = 0x4000000
	// Bit LAST_DC.
	JPEG_STATUS2_LAST_DC = 0x4000000
	// Position of PACKFIFO_READY field.
	JPEG_STATUS2_PACKFIFO_READY_Pos = 0x1b
	// Bit mask of PACKFIFO_READY field.
	JPEG_STATUS2_PACKFIFO_READY_Msk = 0x8000000
	// Bit PACKFIFO_READY.
	JPEG_STATUS2_PACKFIFO_READY = 0x8000000

	// STATUS3: Trace and Debug registers
	// Position of YO field.
	JPEG_STATUS3_YO_Pos = 0x0
	// Bit mask of YO field.
	JPEG_STATUS3_YO_Msk = 0x1ff
	// Position of Y_READY field.
	JPEG_STATUS3_Y_READY_Pos = 0x9
	// Bit mask of Y_READY field.
	JPEG_STATUS3_Y_READY_Msk = 0x200
	// Bit Y_READY.
	JPEG_STATUS3_Y_READY = 0x200
	// Position of CBO field.
	JPEG_STATUS3_CBO_Pos = 0xa
	// Bit mask of CBO field.
	JPEG_STATUS3_CBO_Msk = 0x7fc00
	// Position of CB_READY field.
	JPEG_STATUS3_CB_READY_Pos = 0x13
	// Bit mask of CB_READY field.
	JPEG_STATUS3_CB_READY_Msk = 0x80000
	// Bit CB_READY.
	JPEG_STATUS3_CB_READY = 0x80000
	// Position of CRO field.
	JPEG_STATUS3_CRO_Pos = 0x14
	// Bit mask of CRO field.
	JPEG_STATUS3_CRO_Msk = 0x1ff00000
	// Position of CR_READY field.
	JPEG_STATUS3_CR_READY_Pos = 0x1d
	// Bit mask of CR_READY field.
	JPEG_STATUS3_CR_READY_Msk = 0x20000000
	// Bit CR_READY.
	JPEG_STATUS3_CR_READY = 0x20000000

	// STATUS4: Trace and Debug registers
	// Position of HFM_BITSTREAM field.
	JPEG_STATUS4_HFM_BITSTREAM_Pos = 0x0
	// Bit mask of HFM_BITSTREAM field.
	JPEG_STATUS4_HFM_BITSTREAM_Msk = 0xffffffff

	// DHT_TOTLEN_DC0: Trace and Debug registers
	// Position of DHT_TOTLEN_DC0 field.
	JPEG_DHT_TOTLEN_DC0_DHT_TOTLEN_DC0_Pos = 0x0
	// Bit mask of DHT_TOTLEN_DC0 field.
	JPEG_DHT_TOTLEN_DC0_DHT_TOTLEN_DC0_Msk = 0xffffffff

	// DHT_VAl_DC0: Trace and Debug registers
	// Position of DHT_VAL_DC0 field.
	JPEG_DHT_VAl_DC0_DHT_VAL_DC0_Pos = 0x0
	// Bit mask of DHT_VAL_DC0 field.
	JPEG_DHT_VAl_DC0_DHT_VAL_DC0_Msk = 0xffffffff

	// DHT_TOTLEN_AC0: Trace and Debug registers
	// Position of DHT_TOTLEN_AC0 field.
	JPEG_DHT_TOTLEN_AC0_DHT_TOTLEN_AC0_Pos = 0x0
	// Bit mask of DHT_TOTLEN_AC0 field.
	JPEG_DHT_TOTLEN_AC0_DHT_TOTLEN_AC0_Msk = 0xffffffff

	// DHT_VAl_AC0: Trace and Debug registers
	// Position of DHT_VAL_AC0 field.
	JPEG_DHT_VAl_AC0_DHT_VAL_AC0_Pos = 0x0
	// Bit mask of DHT_VAL_AC0 field.
	JPEG_DHT_VAl_AC0_DHT_VAL_AC0_Msk = 0xffffffff

	// DHT_TOTLEN_DC1: Trace and Debug registers
	// Position of DHT_TOTLEN_DC1 field.
	JPEG_DHT_TOTLEN_DC1_DHT_TOTLEN_DC1_Pos = 0x0
	// Bit mask of DHT_TOTLEN_DC1 field.
	JPEG_DHT_TOTLEN_DC1_DHT_TOTLEN_DC1_Msk = 0xffffffff

	// DHT_VAl_DC1: Trace and Debug registers
	// Position of DHT_VAL_DC1 field.
	JPEG_DHT_VAl_DC1_DHT_VAL_DC1_Pos = 0x0
	// Bit mask of DHT_VAL_DC1 field.
	JPEG_DHT_VAl_DC1_DHT_VAL_DC1_Msk = 0xffffffff

	// DHT_TOTLEN_AC1: Trace and Debug registers
	// Position of DHT_TOTLEN_AC1 field.
	JPEG_DHT_TOTLEN_AC1_DHT_TOTLEN_AC1_Pos = 0x0
	// Bit mask of DHT_TOTLEN_AC1 field.
	JPEG_DHT_TOTLEN_AC1_DHT_TOTLEN_AC1_Msk = 0xffffffff

	// DHT_VAl_AC1: Trace and Debug registers
	// Position of DHT_VAL_AC1 field.
	JPEG_DHT_VAl_AC1_DHT_VAL_AC1_Pos = 0x0
	// Bit mask of DHT_VAL_AC1 field.
	JPEG_DHT_VAl_AC1_DHT_VAL_AC1_Msk = 0xffffffff

	// DHT_CODEMIN_DC0: Trace and Debug registers
	// Position of DHT_CODEMIN_DC0 field.
	JPEG_DHT_CODEMIN_DC0_DHT_CODEMIN_DC0_Pos = 0x0
	// Bit mask of DHT_CODEMIN_DC0 field.
	JPEG_DHT_CODEMIN_DC0_DHT_CODEMIN_DC0_Msk = 0xffffffff

	// DHT_CODEMIN_AC0: Trace and Debug registers
	// Position of DHT_CODEMIN_AC0 field.
	JPEG_DHT_CODEMIN_AC0_DHT_CODEMIN_AC0_Pos = 0x0
	// Bit mask of DHT_CODEMIN_AC0 field.
	JPEG_DHT_CODEMIN_AC0_DHT_CODEMIN_AC0_Msk = 0xffffffff

	// DHT_CODEMIN_DC1: Trace and Debug registers
	// Position of DHT_CODEMIN_DC1 field.
	JPEG_DHT_CODEMIN_DC1_DHT_CODEMIN_DC1_Pos = 0x0
	// Bit mask of DHT_CODEMIN_DC1 field.
	JPEG_DHT_CODEMIN_DC1_DHT_CODEMIN_DC1_Msk = 0xffffffff

	// DHT_CODEMIN_AC1: Trace and Debug registers
	// Position of DHT_CODEMIN_AC1 field.
	JPEG_DHT_CODEMIN_AC1_DHT_CODEMIN_AC1_Pos = 0x0
	// Bit mask of DHT_CODEMIN_AC1 field.
	JPEG_DHT_CODEMIN_AC1_DHT_CODEMIN_AC1_Msk = 0xffffffff

	// DECODER_STATUS0: Trace and Debug registers
	// Position of DECODE_BYTE_CNT field.
	JPEG_DECODER_STATUS0_DECODE_BYTE_CNT_Pos = 0x0
	// Bit mask of DECODE_BYTE_CNT field.
	JPEG_DECODER_STATUS0_DECODE_BYTE_CNT_Msk = 0x3ffffff
	// Position of HEADER_DEC_ST field.
	JPEG_DECODER_STATUS0_HEADER_DEC_ST_Pos = 0x1a
	// Bit mask of HEADER_DEC_ST field.
	JPEG_DECODER_STATUS0_HEADER_DEC_ST_Msk = 0x3c000000
	// Position of DECODE_SAMPLE_SEL field.
	JPEG_DECODER_STATUS0_DECODE_SAMPLE_SEL_Pos = 0x1e
	// Bit mask of DECODE_SAMPLE_SEL field.
	JPEG_DECODER_STATUS0_DECODE_SAMPLE_SEL_Msk = 0xc0000000

	// DECODER_STATUS1: Trace and Debug registers
	// Position of ENCODE_DATA field.
	JPEG_DECODER_STATUS1_ENCODE_DATA_Pos = 0x0
	// Bit mask of ENCODE_DATA field.
	JPEG_DECODER_STATUS1_ENCODE_DATA_Msk = 0xffff
	// Position of COUNT_Q field.
	JPEG_DECODER_STATUS1_COUNT_Q_Pos = 0x10
	// Bit mask of COUNT_Q field.
	JPEG_DECODER_STATUS1_COUNT_Q_Msk = 0x7f0000
	// Position of MCU_FSM_READY field.
	JPEG_DECODER_STATUS1_MCU_FSM_READY_Pos = 0x17
	// Bit mask of MCU_FSM_READY field.
	JPEG_DECODER_STATUS1_MCU_FSM_READY_Msk = 0x800000
	// Bit MCU_FSM_READY.
	JPEG_DECODER_STATUS1_MCU_FSM_READY = 0x800000
	// Position of DECODE_DATA field.
	JPEG_DECODER_STATUS1_DECODE_DATA_Pos = 0x18
	// Bit mask of DECODE_DATA field.
	JPEG_DECODER_STATUS1_DECODE_DATA_Msk = 0xff000000

	// DECODER_STATUS2: Trace and Debug registers
	// Position of COMP_BLOCK_NUM field.
	JPEG_DECODER_STATUS2_COMP_BLOCK_NUM_Pos = 0x0
	// Bit mask of COMP_BLOCK_NUM field.
	JPEG_DECODER_STATUS2_COMP_BLOCK_NUM_Msk = 0x3ffffff
	// Position of SCAN_NUM field.
	JPEG_DECODER_STATUS2_SCAN_NUM_Pos = 0x1a
	// Bit mask of SCAN_NUM field.
	JPEG_DECODER_STATUS2_SCAN_NUM_Msk = 0x1c000000
	// Position of RST_CHECK_WAIT field.
	JPEG_DECODER_STATUS2_RST_CHECK_WAIT_Pos = 0x1d
	// Bit mask of RST_CHECK_WAIT field.
	JPEG_DECODER_STATUS2_RST_CHECK_WAIT_Msk = 0x20000000
	// Bit RST_CHECK_WAIT.
	JPEG_DECODER_STATUS2_RST_CHECK_WAIT = 0x20000000
	// Position of SCAN_CHECK_WAIT field.
	JPEG_DECODER_STATUS2_SCAN_CHECK_WAIT_Pos = 0x1e
	// Bit mask of SCAN_CHECK_WAIT field.
	JPEG_DECODER_STATUS2_SCAN_CHECK_WAIT_Msk = 0x40000000
	// Bit SCAN_CHECK_WAIT.
	JPEG_DECODER_STATUS2_SCAN_CHECK_WAIT = 0x40000000
	// Position of MCU_IN_PROC field.
	JPEG_DECODER_STATUS2_MCU_IN_PROC_Pos = 0x1f
	// Bit mask of MCU_IN_PROC field.
	JPEG_DECODER_STATUS2_MCU_IN_PROC_Msk = 0x80000000
	// Bit MCU_IN_PROC.
	JPEG_DECODER_STATUS2_MCU_IN_PROC = 0x80000000

	// DECODER_STATUS3: Trace and Debug registers
	// Position of LOOKUP_DATA field.
	JPEG_DECODER_STATUS3_LOOKUP_DATA_Pos = 0x0
	// Bit mask of LOOKUP_DATA field.
	JPEG_DECODER_STATUS3_LOOKUP_DATA_Msk = 0xffffffff

	// DECODER_STATUS4: Trace and Debug registers
	// Position of BLOCK_EOF_CNT field.
	JPEG_DECODER_STATUS4_BLOCK_EOF_CNT_Pos = 0x0
	// Bit mask of BLOCK_EOF_CNT field.
	JPEG_DECODER_STATUS4_BLOCK_EOF_CNT_Msk = 0x3ffffff
	// Position of DEZIGZAG_READY field.
	JPEG_DECODER_STATUS4_DEZIGZAG_READY_Pos = 0x1a
	// Bit mask of DEZIGZAG_READY field.
	JPEG_DECODER_STATUS4_DEZIGZAG_READY_Msk = 0x4000000
	// Bit DEZIGZAG_READY.
	JPEG_DECODER_STATUS4_DEZIGZAG_READY = 0x4000000
	// Position of DE_FRAME_EOF_CHECK field.
	JPEG_DECODER_STATUS4_DE_FRAME_EOF_CHECK_Pos = 0x1b
	// Bit mask of DE_FRAME_EOF_CHECK field.
	JPEG_DECODER_STATUS4_DE_FRAME_EOF_CHECK_Msk = 0x8000000
	// Bit DE_FRAME_EOF_CHECK.
	JPEG_DECODER_STATUS4_DE_FRAME_EOF_CHECK = 0x8000000
	// Position of DE_DMA2D_IN_PUSH field.
	JPEG_DECODER_STATUS4_DE_DMA2D_IN_PUSH_Pos = 0x1c
	// Bit mask of DE_DMA2D_IN_PUSH field.
	JPEG_DECODER_STATUS4_DE_DMA2D_IN_PUSH_Msk = 0x10000000
	// Bit DE_DMA2D_IN_PUSH.
	JPEG_DECODER_STATUS4_DE_DMA2D_IN_PUSH = 0x10000000

	// DECODER_STATUS5: Trace and Debug registers
	// Position of IDCT_HFM_DATA field.
	JPEG_DECODER_STATUS5_IDCT_HFM_DATA_Pos = 0x0
	// Bit mask of IDCT_HFM_DATA field.
	JPEG_DECODER_STATUS5_IDCT_HFM_DATA_Msk = 0xffff
	// Position of NS0 field.
	JPEG_DECODER_STATUS5_NS0_Pos = 0x10
	// Bit mask of NS0 field.
	JPEG_DECODER_STATUS5_NS0_Msk = 0x70000
	// Position of NS1 field.
	JPEG_DECODER_STATUS5_NS1_Pos = 0x13
	// Bit mask of NS1 field.
	JPEG_DECODER_STATUS5_NS1_Msk = 0x380000
	// Position of NS2 field.
	JPEG_DECODER_STATUS5_NS2_Pos = 0x16
	// Bit mask of NS2 field.
	JPEG_DECODER_STATUS5_NS2_Msk = 0x1c00000
	// Position of NS3 field.
	JPEG_DECODER_STATUS5_NS3_Pos = 0x19
	// Bit mask of NS3 field.
	JPEG_DECODER_STATUS5_NS3_Msk = 0xe000000
	// Position of DATA_LAST_O field.
	JPEG_DECODER_STATUS5_DATA_LAST_O_Pos = 0x1c
	// Bit mask of DATA_LAST_O field.
	JPEG_DECODER_STATUS5_DATA_LAST_O_Msk = 0x10000000
	// Bit DATA_LAST_O.
	JPEG_DECODER_STATUS5_DATA_LAST_O = 0x10000000
	// Position of RDN_RESULT field.
	JPEG_DECODER_STATUS5_RDN_RESULT_Pos = 0x1d
	// Bit mask of RDN_RESULT field.
	JPEG_DECODER_STATUS5_RDN_RESULT_Msk = 0x20000000
	// Bit RDN_RESULT.
	JPEG_DECODER_STATUS5_RDN_RESULT = 0x20000000
	// Position of RDN_ENA field.
	JPEG_DECODER_STATUS5_RDN_ENA_Pos = 0x1e
	// Bit mask of RDN_ENA field.
	JPEG_DECODER_STATUS5_RDN_ENA_Msk = 0x40000000
	// Bit RDN_ENA.
	JPEG_DECODER_STATUS5_RDN_ENA = 0x40000000

	// STATUS5: Trace and Debug registers
	// Position of PIC_BLOCK_NUM field.
	JPEG_STATUS5_PIC_BLOCK_NUM_Pos = 0x0
	// Bit mask of PIC_BLOCK_NUM field.
	JPEG_STATUS5_PIC_BLOCK_NUM_Msk = 0xffffff

	// ECO_LOW: Trace and Debug registers
	// Position of RDN_ECO_LOW field.
	JPEG_ECO_LOW_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of RDN_ECO_LOW field.
	JPEG_ECO_LOW_RDN_ECO_LOW_Msk = 0xffffffff

	// ECO_HIGH: Trace and Debug registers
	// Position of RDN_ECO_HIGH field.
	JPEG_ECO_HIGH_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of RDN_ECO_HIGH field.
	JPEG_ECO_HIGH_RDN_ECO_HIGH_Msk = 0xffffffff

	// SYS: Trace and Debug registers
	// Position of CLK_EN field.
	JPEG_SYS_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	JPEG_SYS_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	JPEG_SYS_CLK_EN = 0x80000000

	// VERSION: Trace and Debug registers
	// Position of JPEG_VER field.
	JPEG_VERSION_JPEG_VER_Pos = 0x0
	// Bit mask of JPEG_VER field.
	JPEG_VERSION_JPEG_VER_Msk = 0xfffffff
)

// Constants for LCD_CAM: Camera/LCD Controller
const (
	// LCD_CLOCK: LCD clock config register.
	// Position of LCD_CLKCNT_N field.
	LCDCAM_LCD_CLOCK_LCD_CLKCNT_N_Pos = 0x0
	// Bit mask of LCD_CLKCNT_N field.
	LCDCAM_LCD_CLOCK_LCD_CLKCNT_N_Msk = 0x3f
	// Position of LCD_CLK_EQU_SYSCLK field.
	LCDCAM_LCD_CLOCK_LCD_CLK_EQU_SYSCLK_Pos = 0x6
	// Bit mask of LCD_CLK_EQU_SYSCLK field.
	LCDCAM_LCD_CLOCK_LCD_CLK_EQU_SYSCLK_Msk = 0x40
	// Bit LCD_CLK_EQU_SYSCLK.
	LCDCAM_LCD_CLOCK_LCD_CLK_EQU_SYSCLK = 0x40
	// Position of LCD_CK_IDLE_EDGE field.
	LCDCAM_LCD_CLOCK_LCD_CK_IDLE_EDGE_Pos = 0x7
	// Bit mask of LCD_CK_IDLE_EDGE field.
	LCDCAM_LCD_CLOCK_LCD_CK_IDLE_EDGE_Msk = 0x80
	// Bit LCD_CK_IDLE_EDGE.
	LCDCAM_LCD_CLOCK_LCD_CK_IDLE_EDGE = 0x80
	// Position of LCD_CK_OUT_EDGE field.
	LCDCAM_LCD_CLOCK_LCD_CK_OUT_EDGE_Pos = 0x8
	// Bit mask of LCD_CK_OUT_EDGE field.
	LCDCAM_LCD_CLOCK_LCD_CK_OUT_EDGE_Msk = 0x100
	// Bit LCD_CK_OUT_EDGE.
	LCDCAM_LCD_CLOCK_LCD_CK_OUT_EDGE = 0x100
	// Position of LCD_CLKM_DIV_NUM field.
	LCDCAM_LCD_CLOCK_LCD_CLKM_DIV_NUM_Pos = 0x9
	// Bit mask of LCD_CLKM_DIV_NUM field.
	LCDCAM_LCD_CLOCK_LCD_CLKM_DIV_NUM_Msk = 0x1fe00
	// Position of LCD_CLKM_DIV_B field.
	LCDCAM_LCD_CLOCK_LCD_CLKM_DIV_B_Pos = 0x11
	// Bit mask of LCD_CLKM_DIV_B field.
	LCDCAM_LCD_CLOCK_LCD_CLKM_DIV_B_Msk = 0x7e0000
	// Position of LCD_CLKM_DIV_A field.
	LCDCAM_LCD_CLOCK_LCD_CLKM_DIV_A_Pos = 0x17
	// Bit mask of LCD_CLKM_DIV_A field.
	LCDCAM_LCD_CLOCK_LCD_CLKM_DIV_A_Msk = 0x1f800000
	// Position of LCD_CLK_SEL field.
	LCDCAM_LCD_CLOCK_LCD_CLK_SEL_Pos = 0x1d
	// Bit mask of LCD_CLK_SEL field.
	LCDCAM_LCD_CLOCK_LCD_CLK_SEL_Msk = 0x60000000
	// Position of CLK_EN field.
	LCDCAM_LCD_CLOCK_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	LCDCAM_LCD_CLOCK_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	LCDCAM_LCD_CLOCK_CLK_EN = 0x80000000

	// CAM_CTRL: CAM config register.
	// Position of CAM_STOP_EN field.
	LCDCAM_CAM_CTRL_CAM_STOP_EN_Pos = 0x0
	// Bit mask of CAM_STOP_EN field.
	LCDCAM_CAM_CTRL_CAM_STOP_EN_Msk = 0x1
	// Bit CAM_STOP_EN.
	LCDCAM_CAM_CTRL_CAM_STOP_EN = 0x1
	// Position of CAM_VSYNC_FILTER_THRES field.
	LCDCAM_CAM_CTRL_CAM_VSYNC_FILTER_THRES_Pos = 0x1
	// Bit mask of CAM_VSYNC_FILTER_THRES field.
	LCDCAM_CAM_CTRL_CAM_VSYNC_FILTER_THRES_Msk = 0xe
	// Position of CAM_UPDATE field.
	LCDCAM_CAM_CTRL_CAM_UPDATE_Pos = 0x4
	// Bit mask of CAM_UPDATE field.
	LCDCAM_CAM_CTRL_CAM_UPDATE_Msk = 0x10
	// Bit CAM_UPDATE.
	LCDCAM_CAM_CTRL_CAM_UPDATE = 0x10
	// Position of CAM_BYTE_ORDER field.
	LCDCAM_CAM_CTRL_CAM_BYTE_ORDER_Pos = 0x5
	// Bit mask of CAM_BYTE_ORDER field.
	LCDCAM_CAM_CTRL_CAM_BYTE_ORDER_Msk = 0x20
	// Bit CAM_BYTE_ORDER.
	LCDCAM_CAM_CTRL_CAM_BYTE_ORDER = 0x20
	// Position of CAM_BIT_ORDER field.
	LCDCAM_CAM_CTRL_CAM_BIT_ORDER_Pos = 0x6
	// Bit mask of CAM_BIT_ORDER field.
	LCDCAM_CAM_CTRL_CAM_BIT_ORDER_Msk = 0x40
	// Bit CAM_BIT_ORDER.
	LCDCAM_CAM_CTRL_CAM_BIT_ORDER = 0x40
	// Position of CAM_LINE_INT_EN field.
	LCDCAM_CAM_CTRL_CAM_LINE_INT_EN_Pos = 0x7
	// Bit mask of CAM_LINE_INT_EN field.
	LCDCAM_CAM_CTRL_CAM_LINE_INT_EN_Msk = 0x80
	// Bit CAM_LINE_INT_EN.
	LCDCAM_CAM_CTRL_CAM_LINE_INT_EN = 0x80
	// Position of CAM_VS_EOF_EN field.
	LCDCAM_CAM_CTRL_CAM_VS_EOF_EN_Pos = 0x8
	// Bit mask of CAM_VS_EOF_EN field.
	LCDCAM_CAM_CTRL_CAM_VS_EOF_EN_Msk = 0x100
	// Bit CAM_VS_EOF_EN.
	LCDCAM_CAM_CTRL_CAM_VS_EOF_EN = 0x100
	// Position of CAM_CLKM_DIV_NUM field.
	LCDCAM_CAM_CTRL_CAM_CLKM_DIV_NUM_Pos = 0x9
	// Bit mask of CAM_CLKM_DIV_NUM field.
	LCDCAM_CAM_CTRL_CAM_CLKM_DIV_NUM_Msk = 0x1fe00
	// Position of CAM_CLKM_DIV_B field.
	LCDCAM_CAM_CTRL_CAM_CLKM_DIV_B_Pos = 0x11
	// Bit mask of CAM_CLKM_DIV_B field.
	LCDCAM_CAM_CTRL_CAM_CLKM_DIV_B_Msk = 0x7e0000
	// Position of CAM_CLKM_DIV_A field.
	LCDCAM_CAM_CTRL_CAM_CLKM_DIV_A_Pos = 0x17
	// Bit mask of CAM_CLKM_DIV_A field.
	LCDCAM_CAM_CTRL_CAM_CLKM_DIV_A_Msk = 0x1f800000
	// Position of CAM_CLK_SEL field.
	LCDCAM_CAM_CTRL_CAM_CLK_SEL_Pos = 0x1d
	// Bit mask of CAM_CLK_SEL field.
	LCDCAM_CAM_CTRL_CAM_CLK_SEL_Msk = 0x60000000

	// CAM_CTRL1: CAM config register.
	// Position of CAM_REC_DATA_BYTELEN field.
	LCDCAM_CAM_CTRL1_CAM_REC_DATA_BYTELEN_Pos = 0x0
	// Bit mask of CAM_REC_DATA_BYTELEN field.
	LCDCAM_CAM_CTRL1_CAM_REC_DATA_BYTELEN_Msk = 0xffff
	// Position of CAM_LINE_INT_NUM field.
	LCDCAM_CAM_CTRL1_CAM_LINE_INT_NUM_Pos = 0x10
	// Bit mask of CAM_LINE_INT_NUM field.
	LCDCAM_CAM_CTRL1_CAM_LINE_INT_NUM_Msk = 0x3f0000
	// Position of CAM_CLK_INV field.
	LCDCAM_CAM_CTRL1_CAM_CLK_INV_Pos = 0x16
	// Bit mask of CAM_CLK_INV field.
	LCDCAM_CAM_CTRL1_CAM_CLK_INV_Msk = 0x400000
	// Bit CAM_CLK_INV.
	LCDCAM_CAM_CTRL1_CAM_CLK_INV = 0x400000
	// Position of CAM_VSYNC_FILTER_EN field.
	LCDCAM_CAM_CTRL1_CAM_VSYNC_FILTER_EN_Pos = 0x17
	// Bit mask of CAM_VSYNC_FILTER_EN field.
	LCDCAM_CAM_CTRL1_CAM_VSYNC_FILTER_EN_Msk = 0x800000
	// Bit CAM_VSYNC_FILTER_EN.
	LCDCAM_CAM_CTRL1_CAM_VSYNC_FILTER_EN = 0x800000
	// Position of CAM_2BYTE_EN field.
	LCDCAM_CAM_CTRL1_CAM_2BYTE_EN_Pos = 0x18
	// Bit mask of CAM_2BYTE_EN field.
	LCDCAM_CAM_CTRL1_CAM_2BYTE_EN_Msk = 0x1000000
	// Bit CAM_2BYTE_EN.
	LCDCAM_CAM_CTRL1_CAM_2BYTE_EN = 0x1000000
	// Position of CAM_DE_INV field.
	LCDCAM_CAM_CTRL1_CAM_DE_INV_Pos = 0x19
	// Bit mask of CAM_DE_INV field.
	LCDCAM_CAM_CTRL1_CAM_DE_INV_Msk = 0x2000000
	// Bit CAM_DE_INV.
	LCDCAM_CAM_CTRL1_CAM_DE_INV = 0x2000000
	// Position of CAM_HSYNC_INV field.
	LCDCAM_CAM_CTRL1_CAM_HSYNC_INV_Pos = 0x1a
	// Bit mask of CAM_HSYNC_INV field.
	LCDCAM_CAM_CTRL1_CAM_HSYNC_INV_Msk = 0x4000000
	// Bit CAM_HSYNC_INV.
	LCDCAM_CAM_CTRL1_CAM_HSYNC_INV = 0x4000000
	// Position of CAM_VSYNC_INV field.
	LCDCAM_CAM_CTRL1_CAM_VSYNC_INV_Pos = 0x1b
	// Bit mask of CAM_VSYNC_INV field.
	LCDCAM_CAM_CTRL1_CAM_VSYNC_INV_Msk = 0x8000000
	// Bit CAM_VSYNC_INV.
	LCDCAM_CAM_CTRL1_CAM_VSYNC_INV = 0x8000000
	// Position of CAM_VH_DE_MODE_EN field.
	LCDCAM_CAM_CTRL1_CAM_VH_DE_MODE_EN_Pos = 0x1c
	// Bit mask of CAM_VH_DE_MODE_EN field.
	LCDCAM_CAM_CTRL1_CAM_VH_DE_MODE_EN_Msk = 0x10000000
	// Bit CAM_VH_DE_MODE_EN.
	LCDCAM_CAM_CTRL1_CAM_VH_DE_MODE_EN = 0x10000000
	// Position of CAM_START field.
	LCDCAM_CAM_CTRL1_CAM_START_Pos = 0x1d
	// Bit mask of CAM_START field.
	LCDCAM_CAM_CTRL1_CAM_START_Msk = 0x20000000
	// Bit CAM_START.
	LCDCAM_CAM_CTRL1_CAM_START = 0x20000000
	// Position of CAM_RESET field.
	LCDCAM_CAM_CTRL1_CAM_RESET_Pos = 0x1e
	// Bit mask of CAM_RESET field.
	LCDCAM_CAM_CTRL1_CAM_RESET_Msk = 0x40000000
	// Bit CAM_RESET.
	LCDCAM_CAM_CTRL1_CAM_RESET = 0x40000000
	// Position of CAM_AFIFO_RESET field.
	LCDCAM_CAM_CTRL1_CAM_AFIFO_RESET_Pos = 0x1f
	// Bit mask of CAM_AFIFO_RESET field.
	LCDCAM_CAM_CTRL1_CAM_AFIFO_RESET_Msk = 0x80000000
	// Bit CAM_AFIFO_RESET.
	LCDCAM_CAM_CTRL1_CAM_AFIFO_RESET = 0x80000000

	// CAM_RGB_YUV: CAM YUV/RGB converter configuration register.
	// Position of CAM_CONV_8BITS_DATA_INV field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV_Pos = 0x15
	// Bit mask of CAM_CONV_8BITS_DATA_INV field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV_Msk = 0x200000
	// Bit CAM_CONV_8BITS_DATA_INV.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_8BITS_DATA_INV = 0x200000
	// Position of CAM_CONV_YUV2YUV_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE_Pos = 0x16
	// Bit mask of CAM_CONV_YUV2YUV_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_YUV2YUV_MODE_Msk = 0xc00000
	// Position of CAM_CONV_YUV_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_YUV_MODE_Pos = 0x18
	// Bit mask of CAM_CONV_YUV_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_YUV_MODE_Msk = 0x3000000
	// Position of CAM_CONV_PROTOCOL_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE_Pos = 0x1a
	// Bit mask of CAM_CONV_PROTOCOL_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE_Msk = 0x4000000
	// Bit CAM_CONV_PROTOCOL_MODE.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_PROTOCOL_MODE = 0x4000000
	// Position of CAM_CONV_DATA_OUT_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE_Pos = 0x1b
	// Bit mask of CAM_CONV_DATA_OUT_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE_Msk = 0x8000000
	// Bit CAM_CONV_DATA_OUT_MODE.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_DATA_OUT_MODE = 0x8000000
	// Position of CAM_CONV_DATA_IN_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_DATA_IN_MODE_Pos = 0x1c
	// Bit mask of CAM_CONV_DATA_IN_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_DATA_IN_MODE_Msk = 0x10000000
	// Bit CAM_CONV_DATA_IN_MODE.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_DATA_IN_MODE = 0x10000000
	// Position of CAM_CONV_MODE_8BITS_ON field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON_Pos = 0x1d
	// Bit mask of CAM_CONV_MODE_8BITS_ON field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON_Msk = 0x20000000
	// Bit CAM_CONV_MODE_8BITS_ON.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_MODE_8BITS_ON = 0x20000000
	// Position of CAM_CONV_TRANS_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_TRANS_MODE_Pos = 0x1e
	// Bit mask of CAM_CONV_TRANS_MODE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_TRANS_MODE_Msk = 0x40000000
	// Bit CAM_CONV_TRANS_MODE.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_TRANS_MODE = 0x40000000
	// Position of CAM_CONV_ENABLE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_ENABLE_Pos = 0x1f
	// Bit mask of CAM_CONV_ENABLE field.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_ENABLE_Msk = 0x80000000
	// Bit CAM_CONV_ENABLE.
	LCDCAM_CAM_RGB_YUV_CAM_CONV_ENABLE = 0x80000000

	// LCD_RGB_YUV: LCD YUV/RGB converter configuration register.
	// Position of LCD_CONV_8BITS_DATA_INV field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV_Pos = 0x14
	// Bit mask of LCD_CONV_8BITS_DATA_INV field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV_Msk = 0x100000
	// Bit LCD_CONV_8BITS_DATA_INV.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_8BITS_DATA_INV = 0x100000
	// Position of LCD_CONV_TXTORX field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_TXTORX_Pos = 0x15
	// Bit mask of LCD_CONV_TXTORX field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_TXTORX_Msk = 0x200000
	// Bit LCD_CONV_TXTORX.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_TXTORX = 0x200000
	// Position of LCD_CONV_YUV2YUV_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE_Pos = 0x16
	// Bit mask of LCD_CONV_YUV2YUV_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_YUV2YUV_MODE_Msk = 0xc00000
	// Position of LCD_CONV_YUV_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_YUV_MODE_Pos = 0x18
	// Bit mask of LCD_CONV_YUV_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_YUV_MODE_Msk = 0x3000000
	// Position of LCD_CONV_PROTOCOL_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE_Pos = 0x1a
	// Bit mask of LCD_CONV_PROTOCOL_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE_Msk = 0x4000000
	// Bit LCD_CONV_PROTOCOL_MODE.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_PROTOCOL_MODE = 0x4000000
	// Position of LCD_CONV_DATA_OUT_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE_Pos = 0x1b
	// Bit mask of LCD_CONV_DATA_OUT_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE_Msk = 0x8000000
	// Bit LCD_CONV_DATA_OUT_MODE.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_DATA_OUT_MODE = 0x8000000
	// Position of LCD_CONV_DATA_IN_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_DATA_IN_MODE_Pos = 0x1c
	// Bit mask of LCD_CONV_DATA_IN_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_DATA_IN_MODE_Msk = 0x10000000
	// Bit LCD_CONV_DATA_IN_MODE.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_DATA_IN_MODE = 0x10000000
	// Position of LCD_CONV_MODE_8BITS_ON field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON_Pos = 0x1d
	// Bit mask of LCD_CONV_MODE_8BITS_ON field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON_Msk = 0x20000000
	// Bit LCD_CONV_MODE_8BITS_ON.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_MODE_8BITS_ON = 0x20000000
	// Position of LCD_CONV_TRANS_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_TRANS_MODE_Pos = 0x1e
	// Bit mask of LCD_CONV_TRANS_MODE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_TRANS_MODE_Msk = 0x40000000
	// Bit LCD_CONV_TRANS_MODE.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_TRANS_MODE = 0x40000000
	// Position of LCD_CONV_ENABLE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_ENABLE_Pos = 0x1f
	// Bit mask of LCD_CONV_ENABLE field.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_ENABLE_Msk = 0x80000000
	// Bit LCD_CONV_ENABLE.
	LCDCAM_LCD_RGB_YUV_LCD_CONV_ENABLE = 0x80000000

	// LCD_USER: LCD config register.
	// Position of LCD_DOUT_CYCLELEN field.
	LCDCAM_LCD_USER_LCD_DOUT_CYCLELEN_Pos = 0x0
	// Bit mask of LCD_DOUT_CYCLELEN field.
	LCDCAM_LCD_USER_LCD_DOUT_CYCLELEN_Msk = 0x1fff
	// Position of LCD_ALWAYS_OUT_EN field.
	LCDCAM_LCD_USER_LCD_ALWAYS_OUT_EN_Pos = 0xd
	// Bit mask of LCD_ALWAYS_OUT_EN field.
	LCDCAM_LCD_USER_LCD_ALWAYS_OUT_EN_Msk = 0x2000
	// Bit LCD_ALWAYS_OUT_EN.
	LCDCAM_LCD_USER_LCD_ALWAYS_OUT_EN = 0x2000
	// Position of LCD_DOUT_BYTE_SWIZZLE_MODE field.
	LCDCAM_LCD_USER_LCD_DOUT_BYTE_SWIZZLE_MODE_Pos = 0xe
	// Bit mask of LCD_DOUT_BYTE_SWIZZLE_MODE field.
	LCDCAM_LCD_USER_LCD_DOUT_BYTE_SWIZZLE_MODE_Msk = 0x1c000
	// Position of LCD_DOUT_BYTE_SWIZZLE_ENABLE field.
	LCDCAM_LCD_USER_LCD_DOUT_BYTE_SWIZZLE_ENABLE_Pos = 0x11
	// Bit mask of LCD_DOUT_BYTE_SWIZZLE_ENABLE field.
	LCDCAM_LCD_USER_LCD_DOUT_BYTE_SWIZZLE_ENABLE_Msk = 0x20000
	// Bit LCD_DOUT_BYTE_SWIZZLE_ENABLE.
	LCDCAM_LCD_USER_LCD_DOUT_BYTE_SWIZZLE_ENABLE = 0x20000
	// Position of LCD_DOUT_BIT_ORDER field.
	LCDCAM_LCD_USER_LCD_DOUT_BIT_ORDER_Pos = 0x12
	// Bit mask of LCD_DOUT_BIT_ORDER field.
	LCDCAM_LCD_USER_LCD_DOUT_BIT_ORDER_Msk = 0x40000
	// Bit LCD_DOUT_BIT_ORDER.
	LCDCAM_LCD_USER_LCD_DOUT_BIT_ORDER = 0x40000
	// Position of LCD_BYTE_MODE field.
	LCDCAM_LCD_USER_LCD_BYTE_MODE_Pos = 0x13
	// Bit mask of LCD_BYTE_MODE field.
	LCDCAM_LCD_USER_LCD_BYTE_MODE_Msk = 0x180000
	// Position of LCD_UPDATE field.
	LCDCAM_LCD_USER_LCD_UPDATE_Pos = 0x15
	// Bit mask of LCD_UPDATE field.
	LCDCAM_LCD_USER_LCD_UPDATE_Msk = 0x200000
	// Bit LCD_UPDATE.
	LCDCAM_LCD_USER_LCD_UPDATE = 0x200000
	// Position of LCD_BIT_ORDER field.
	LCDCAM_LCD_USER_LCD_BIT_ORDER_Pos = 0x16
	// Bit mask of LCD_BIT_ORDER field.
	LCDCAM_LCD_USER_LCD_BIT_ORDER_Msk = 0x400000
	// Bit LCD_BIT_ORDER.
	LCDCAM_LCD_USER_LCD_BIT_ORDER = 0x400000
	// Position of LCD_BYTE_ORDER field.
	LCDCAM_LCD_USER_LCD_BYTE_ORDER_Pos = 0x17
	// Bit mask of LCD_BYTE_ORDER field.
	LCDCAM_LCD_USER_LCD_BYTE_ORDER_Msk = 0x800000
	// Bit LCD_BYTE_ORDER.
	LCDCAM_LCD_USER_LCD_BYTE_ORDER = 0x800000
	// Position of LCD_DOUT field.
	LCDCAM_LCD_USER_LCD_DOUT_Pos = 0x18
	// Bit mask of LCD_DOUT field.
	LCDCAM_LCD_USER_LCD_DOUT_Msk = 0x1000000
	// Bit LCD_DOUT.
	LCDCAM_LCD_USER_LCD_DOUT = 0x1000000
	// Position of LCD_DUMMY field.
	LCDCAM_LCD_USER_LCD_DUMMY_Pos = 0x19
	// Bit mask of LCD_DUMMY field.
	LCDCAM_LCD_USER_LCD_DUMMY_Msk = 0x2000000
	// Bit LCD_DUMMY.
	LCDCAM_LCD_USER_LCD_DUMMY = 0x2000000
	// Position of LCD_CMD field.
	LCDCAM_LCD_USER_LCD_CMD_Pos = 0x1a
	// Bit mask of LCD_CMD field.
	LCDCAM_LCD_USER_LCD_CMD_Msk = 0x4000000
	// Bit LCD_CMD.
	LCDCAM_LCD_USER_LCD_CMD = 0x4000000
	// Position of LCD_START field.
	LCDCAM_LCD_USER_LCD_START_Pos = 0x1b
	// Bit mask of LCD_START field.
	LCDCAM_LCD_USER_LCD_START_Msk = 0x8000000
	// Bit LCD_START.
	LCDCAM_LCD_USER_LCD_START = 0x8000000
	// Position of LCD_RESET field.
	LCDCAM_LCD_USER_LCD_RESET_Pos = 0x1c
	// Bit mask of LCD_RESET field.
	LCDCAM_LCD_USER_LCD_RESET_Msk = 0x10000000
	// Bit LCD_RESET.
	LCDCAM_LCD_USER_LCD_RESET = 0x10000000
	// Position of LCD_DUMMY_CYCLELEN field.
	LCDCAM_LCD_USER_LCD_DUMMY_CYCLELEN_Pos = 0x1d
	// Bit mask of LCD_DUMMY_CYCLELEN field.
	LCDCAM_LCD_USER_LCD_DUMMY_CYCLELEN_Msk = 0x60000000
	// Position of LCD_CMD_2_CYCLE_EN field.
	LCDCAM_LCD_USER_LCD_CMD_2_CYCLE_EN_Pos = 0x1f
	// Bit mask of LCD_CMD_2_CYCLE_EN field.
	LCDCAM_LCD_USER_LCD_CMD_2_CYCLE_EN_Msk = 0x80000000
	// Bit LCD_CMD_2_CYCLE_EN.
	LCDCAM_LCD_USER_LCD_CMD_2_CYCLE_EN = 0x80000000

	// LCD_MISC: LCD config register.
	// Position of LCD_WIRE_MODE field.
	LCDCAM_LCD_MISC_LCD_WIRE_MODE_Pos = 0x4
	// Bit mask of LCD_WIRE_MODE field.
	LCDCAM_LCD_MISC_LCD_WIRE_MODE_Msk = 0x30
	// Position of LCD_VFK_CYCLELEN field.
	LCDCAM_LCD_MISC_LCD_VFK_CYCLELEN_Pos = 0x6
	// Bit mask of LCD_VFK_CYCLELEN field.
	LCDCAM_LCD_MISC_LCD_VFK_CYCLELEN_Msk = 0xfc0
	// Position of LCD_VBK_CYCLELEN field.
	LCDCAM_LCD_MISC_LCD_VBK_CYCLELEN_Pos = 0xc
	// Bit mask of LCD_VBK_CYCLELEN field.
	LCDCAM_LCD_MISC_LCD_VBK_CYCLELEN_Msk = 0x1fff000
	// Position of LCD_NEXT_FRAME_EN field.
	LCDCAM_LCD_MISC_LCD_NEXT_FRAME_EN_Pos = 0x19
	// Bit mask of LCD_NEXT_FRAME_EN field.
	LCDCAM_LCD_MISC_LCD_NEXT_FRAME_EN_Msk = 0x2000000
	// Bit LCD_NEXT_FRAME_EN.
	LCDCAM_LCD_MISC_LCD_NEXT_FRAME_EN = 0x2000000
	// Position of LCD_BK_EN field.
	LCDCAM_LCD_MISC_LCD_BK_EN_Pos = 0x1a
	// Bit mask of LCD_BK_EN field.
	LCDCAM_LCD_MISC_LCD_BK_EN_Msk = 0x4000000
	// Bit LCD_BK_EN.
	LCDCAM_LCD_MISC_LCD_BK_EN = 0x4000000
	// Position of LCD_AFIFO_RESET field.
	LCDCAM_LCD_MISC_LCD_AFIFO_RESET_Pos = 0x1b
	// Bit mask of LCD_AFIFO_RESET field.
	LCDCAM_LCD_MISC_LCD_AFIFO_RESET_Msk = 0x8000000
	// Bit LCD_AFIFO_RESET.
	LCDCAM_LCD_MISC_LCD_AFIFO_RESET = 0x8000000
	// Position of LCD_CD_DATA_SET field.
	LCDCAM_LCD_MISC_LCD_CD_DATA_SET_Pos = 0x1c
	// Bit mask of LCD_CD_DATA_SET field.
	LCDCAM_LCD_MISC_LCD_CD_DATA_SET_Msk = 0x10000000
	// Bit LCD_CD_DATA_SET.
	LCDCAM_LCD_MISC_LCD_CD_DATA_SET = 0x10000000
	// Position of LCD_CD_DUMMY_SET field.
	LCDCAM_LCD_MISC_LCD_CD_DUMMY_SET_Pos = 0x1d
	// Bit mask of LCD_CD_DUMMY_SET field.
	LCDCAM_LCD_MISC_LCD_CD_DUMMY_SET_Msk = 0x20000000
	// Bit LCD_CD_DUMMY_SET.
	LCDCAM_LCD_MISC_LCD_CD_DUMMY_SET = 0x20000000
	// Position of LCD_CD_CMD_SET field.
	LCDCAM_LCD_MISC_LCD_CD_CMD_SET_Pos = 0x1e
	// Bit mask of LCD_CD_CMD_SET field.
	LCDCAM_LCD_MISC_LCD_CD_CMD_SET_Msk = 0x40000000
	// Bit LCD_CD_CMD_SET.
	LCDCAM_LCD_MISC_LCD_CD_CMD_SET = 0x40000000
	// Position of LCD_CD_IDLE_EDGE field.
	LCDCAM_LCD_MISC_LCD_CD_IDLE_EDGE_Pos = 0x1f
	// Bit mask of LCD_CD_IDLE_EDGE field.
	LCDCAM_LCD_MISC_LCD_CD_IDLE_EDGE_Msk = 0x80000000
	// Bit LCD_CD_IDLE_EDGE.
	LCDCAM_LCD_MISC_LCD_CD_IDLE_EDGE = 0x80000000

	// LCD_CTRL: LCD config register.
	// Position of LCD_HB_FRONT field.
	LCDCAM_LCD_CTRL_LCD_HB_FRONT_Pos = 0x0
	// Bit mask of LCD_HB_FRONT field.
	LCDCAM_LCD_CTRL_LCD_HB_FRONT_Msk = 0x7ff
	// Position of LCD_VA_HEIGHT field.
	LCDCAM_LCD_CTRL_LCD_VA_HEIGHT_Pos = 0xb
	// Bit mask of LCD_VA_HEIGHT field.
	LCDCAM_LCD_CTRL_LCD_VA_HEIGHT_Msk = 0x1ff800
	// Position of LCD_VT_HEIGHT field.
	LCDCAM_LCD_CTRL_LCD_VT_HEIGHT_Pos = 0x15
	// Bit mask of LCD_VT_HEIGHT field.
	LCDCAM_LCD_CTRL_LCD_VT_HEIGHT_Msk = 0x7fe00000
	// Position of LCD_RGB_MODE_EN field.
	LCDCAM_LCD_CTRL_LCD_RGB_MODE_EN_Pos = 0x1f
	// Bit mask of LCD_RGB_MODE_EN field.
	LCDCAM_LCD_CTRL_LCD_RGB_MODE_EN_Msk = 0x80000000
	// Bit LCD_RGB_MODE_EN.
	LCDCAM_LCD_CTRL_LCD_RGB_MODE_EN = 0x80000000

	// LCD_CTRL1: LCD config register.
	// Position of LCD_VB_FRONT field.
	LCDCAM_LCD_CTRL1_LCD_VB_FRONT_Pos = 0x0
	// Bit mask of LCD_VB_FRONT field.
	LCDCAM_LCD_CTRL1_LCD_VB_FRONT_Msk = 0xff
	// Position of LCD_HA_WIDTH field.
	LCDCAM_LCD_CTRL1_LCD_HA_WIDTH_Pos = 0x8
	// Bit mask of LCD_HA_WIDTH field.
	LCDCAM_LCD_CTRL1_LCD_HA_WIDTH_Msk = 0xfff00
	// Position of LCD_HT_WIDTH field.
	LCDCAM_LCD_CTRL1_LCD_HT_WIDTH_Pos = 0x14
	// Bit mask of LCD_HT_WIDTH field.
	LCDCAM_LCD_CTRL1_LCD_HT_WIDTH_Msk = 0xfff00000

	// LCD_CTRL2: LCD config register.
	// Position of LCD_VSYNC_WIDTH field.
	LCDCAM_LCD_CTRL2_LCD_VSYNC_WIDTH_Pos = 0x0
	// Bit mask of LCD_VSYNC_WIDTH field.
	LCDCAM_LCD_CTRL2_LCD_VSYNC_WIDTH_Msk = 0x7f
	// Position of LCD_VSYNC_IDLE_POL field.
	LCDCAM_LCD_CTRL2_LCD_VSYNC_IDLE_POL_Pos = 0x7
	// Bit mask of LCD_VSYNC_IDLE_POL field.
	LCDCAM_LCD_CTRL2_LCD_VSYNC_IDLE_POL_Msk = 0x80
	// Bit LCD_VSYNC_IDLE_POL.
	LCDCAM_LCD_CTRL2_LCD_VSYNC_IDLE_POL = 0x80
	// Position of LCD_DE_IDLE_POL field.
	LCDCAM_LCD_CTRL2_LCD_DE_IDLE_POL_Pos = 0x8
	// Bit mask of LCD_DE_IDLE_POL field.
	LCDCAM_LCD_CTRL2_LCD_DE_IDLE_POL_Msk = 0x100
	// Bit LCD_DE_IDLE_POL.
	LCDCAM_LCD_CTRL2_LCD_DE_IDLE_POL = 0x100
	// Position of LCD_HS_BLANK_EN field.
	LCDCAM_LCD_CTRL2_LCD_HS_BLANK_EN_Pos = 0x9
	// Bit mask of LCD_HS_BLANK_EN field.
	LCDCAM_LCD_CTRL2_LCD_HS_BLANK_EN_Msk = 0x200
	// Bit LCD_HS_BLANK_EN.
	LCDCAM_LCD_CTRL2_LCD_HS_BLANK_EN = 0x200
	// Position of LCD_HSYNC_WIDTH field.
	LCDCAM_LCD_CTRL2_LCD_HSYNC_WIDTH_Pos = 0x10
	// Bit mask of LCD_HSYNC_WIDTH field.
	LCDCAM_LCD_CTRL2_LCD_HSYNC_WIDTH_Msk = 0x7f0000
	// Position of LCD_HSYNC_IDLE_POL field.
	LCDCAM_LCD_CTRL2_LCD_HSYNC_IDLE_POL_Pos = 0x17
	// Bit mask of LCD_HSYNC_IDLE_POL field.
	LCDCAM_LCD_CTRL2_LCD_HSYNC_IDLE_POL_Msk = 0x800000
	// Bit LCD_HSYNC_IDLE_POL.
	LCDCAM_LCD_CTRL2_LCD_HSYNC_IDLE_POL = 0x800000
	// Position of LCD_HSYNC_POSITION field.
	LCDCAM_LCD_CTRL2_LCD_HSYNC_POSITION_Pos = 0x18
	// Bit mask of LCD_HSYNC_POSITION field.
	LCDCAM_LCD_CTRL2_LCD_HSYNC_POSITION_Msk = 0xff000000

	// LCD_FIRST_CMD_VAL: LCD config register.
	// Position of LCD_FIRST_CMD_VALUE field.
	LCDCAM_LCD_FIRST_CMD_VAL_LCD_FIRST_CMD_VALUE_Pos = 0x0
	// Bit mask of LCD_FIRST_CMD_VALUE field.
	LCDCAM_LCD_FIRST_CMD_VAL_LCD_FIRST_CMD_VALUE_Msk = 0xffffffff

	// LCD_LATTER_CMD_VAL: LCD config register.
	// Position of LCD_LATTER_CMD_VALUE field.
	LCDCAM_LCD_LATTER_CMD_VAL_LCD_LATTER_CMD_VALUE_Pos = 0x0
	// Bit mask of LCD_LATTER_CMD_VALUE field.
	LCDCAM_LCD_LATTER_CMD_VAL_LCD_LATTER_CMD_VALUE_Msk = 0xffffffff

	// LCD_DLY_MODE_CFG1: LCD config register.
	// Position of DOUT16_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT16_MODE_Pos = 0x0
	// Bit mask of DOUT16_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT16_MODE_Msk = 0x3
	// Position of DOUT17_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT17_MODE_Pos = 0x2
	// Bit mask of DOUT17_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT17_MODE_Msk = 0xc
	// Position of DOUT18_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT18_MODE_Pos = 0x4
	// Bit mask of DOUT18_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT18_MODE_Msk = 0x30
	// Position of DOUT19_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT19_MODE_Pos = 0x6
	// Bit mask of DOUT19_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT19_MODE_Msk = 0xc0
	// Position of DOUT20_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT20_MODE_Pos = 0x8
	// Bit mask of DOUT20_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT20_MODE_Msk = 0x300
	// Position of DOUT21_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT21_MODE_Pos = 0xa
	// Bit mask of DOUT21_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT21_MODE_Msk = 0xc00
	// Position of DOUT22_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT22_MODE_Pos = 0xc
	// Bit mask of DOUT22_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT22_MODE_Msk = 0x3000
	// Position of DOUT23_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT23_MODE_Pos = 0xe
	// Bit mask of DOUT23_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_DOUT23_MODE_Msk = 0xc000
	// Position of LCD_CD_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_CD_MODE_Pos = 0x10
	// Bit mask of LCD_CD_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_CD_MODE_Msk = 0x30000
	// Position of LCD_DE_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_DE_MODE_Pos = 0x12
	// Bit mask of LCD_DE_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_DE_MODE_Msk = 0xc0000
	// Position of LCD_HSYNC_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_HSYNC_MODE_Pos = 0x14
	// Bit mask of LCD_HSYNC_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_HSYNC_MODE_Msk = 0x300000
	// Position of LCD_VSYNC_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_VSYNC_MODE_Pos = 0x16
	// Bit mask of LCD_VSYNC_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG1_LCD_VSYNC_MODE_Msk = 0xc00000

	// LCD_DLY_MODE_CFG2: LCD config register.
	// Position of DOUT0_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT0_MODE_Pos = 0x0
	// Bit mask of DOUT0_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT0_MODE_Msk = 0x3
	// Position of DOUT1_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT1_MODE_Pos = 0x2
	// Bit mask of DOUT1_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT1_MODE_Msk = 0xc
	// Position of DOUT2_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT2_MODE_Pos = 0x4
	// Bit mask of DOUT2_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT2_MODE_Msk = 0x30
	// Position of DOUT3_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT3_MODE_Pos = 0x6
	// Bit mask of DOUT3_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT3_MODE_Msk = 0xc0
	// Position of DOUT4_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT4_MODE_Pos = 0x8
	// Bit mask of DOUT4_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT4_MODE_Msk = 0x300
	// Position of DOUT5_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT5_MODE_Pos = 0xa
	// Bit mask of DOUT5_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT5_MODE_Msk = 0xc00
	// Position of DOUT6_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT6_MODE_Pos = 0xc
	// Bit mask of DOUT6_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT6_MODE_Msk = 0x3000
	// Position of DOUT7_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT7_MODE_Pos = 0xe
	// Bit mask of DOUT7_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT7_MODE_Msk = 0xc000
	// Position of DOUT8_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT8_MODE_Pos = 0x10
	// Bit mask of DOUT8_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT8_MODE_Msk = 0x30000
	// Position of DOUT9_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT9_MODE_Pos = 0x12
	// Bit mask of DOUT9_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT9_MODE_Msk = 0xc0000
	// Position of DOUT10_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT10_MODE_Pos = 0x14
	// Bit mask of DOUT10_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT10_MODE_Msk = 0x300000
	// Position of DOUT11_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT11_MODE_Pos = 0x16
	// Bit mask of DOUT11_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT11_MODE_Msk = 0xc00000
	// Position of DOUT12_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT12_MODE_Pos = 0x18
	// Bit mask of DOUT12_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT12_MODE_Msk = 0x3000000
	// Position of DOUT13_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT13_MODE_Pos = 0x1a
	// Bit mask of DOUT13_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT13_MODE_Msk = 0xc000000
	// Position of DOUT14_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT14_MODE_Pos = 0x1c
	// Bit mask of DOUT14_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT14_MODE_Msk = 0x30000000
	// Position of DOUT15_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT15_MODE_Pos = 0x1e
	// Bit mask of DOUT15_MODE field.
	LCDCAM_LCD_DLY_MODE_CFG2_DOUT15_MODE_Msk = 0xc0000000

	// LC_DMA_INT_ENA: LCDCAM interrupt enable register.
	// Position of LCD_VSYNC_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_LCD_VSYNC_INT_ENA_Pos = 0x0
	// Bit mask of LCD_VSYNC_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_LCD_VSYNC_INT_ENA_Msk = 0x1
	// Bit LCD_VSYNC_INT_ENA.
	LCDCAM_LC_DMA_INT_ENA_LCD_VSYNC_INT_ENA = 0x1
	// Position of LCD_TRANS_DONE_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA_Pos = 0x1
	// Bit mask of LCD_TRANS_DONE_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA_Msk = 0x2
	// Bit LCD_TRANS_DONE_INT_ENA.
	LCDCAM_LC_DMA_INT_ENA_LCD_TRANS_DONE_INT_ENA = 0x2
	// Position of CAM_VSYNC_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_CAM_VSYNC_INT_ENA_Pos = 0x2
	// Bit mask of CAM_VSYNC_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_CAM_VSYNC_INT_ENA_Msk = 0x4
	// Bit CAM_VSYNC_INT_ENA.
	LCDCAM_LC_DMA_INT_ENA_CAM_VSYNC_INT_ENA = 0x4
	// Position of CAM_HS_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_CAM_HS_INT_ENA_Pos = 0x3
	// Bit mask of CAM_HS_INT_ENA field.
	LCDCAM_LC_DMA_INT_ENA_CAM_HS_INT_ENA_Msk = 0x8
	// Bit CAM_HS_INT_ENA.
	LCDCAM_LC_DMA_INT_ENA_CAM_HS_INT_ENA = 0x8

	// LC_DMA_INT_RAW: LCDCAM interrupt raw register, valid in level.
	// Position of LCD_VSYNC_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_LCD_VSYNC_INT_RAW_Pos = 0x0
	// Bit mask of LCD_VSYNC_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_LCD_VSYNC_INT_RAW_Msk = 0x1
	// Bit LCD_VSYNC_INT_RAW.
	LCDCAM_LC_DMA_INT_RAW_LCD_VSYNC_INT_RAW = 0x1
	// Position of LCD_TRANS_DONE_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW_Pos = 0x1
	// Bit mask of LCD_TRANS_DONE_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW_Msk = 0x2
	// Bit LCD_TRANS_DONE_INT_RAW.
	LCDCAM_LC_DMA_INT_RAW_LCD_TRANS_DONE_INT_RAW = 0x2
	// Position of CAM_VSYNC_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_CAM_VSYNC_INT_RAW_Pos = 0x2
	// Bit mask of CAM_VSYNC_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_CAM_VSYNC_INT_RAW_Msk = 0x4
	// Bit CAM_VSYNC_INT_RAW.
	LCDCAM_LC_DMA_INT_RAW_CAM_VSYNC_INT_RAW = 0x4
	// Position of CAM_HS_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_CAM_HS_INT_RAW_Pos = 0x3
	// Bit mask of CAM_HS_INT_RAW field.
	LCDCAM_LC_DMA_INT_RAW_CAM_HS_INT_RAW_Msk = 0x8
	// Bit CAM_HS_INT_RAW.
	LCDCAM_LC_DMA_INT_RAW_CAM_HS_INT_RAW = 0x8

	// LC_DMA_INT_ST: LCDCAM interrupt status register.
	// Position of LCD_VSYNC_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_LCD_VSYNC_INT_ST_Pos = 0x0
	// Bit mask of LCD_VSYNC_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_LCD_VSYNC_INT_ST_Msk = 0x1
	// Bit LCD_VSYNC_INT_ST.
	LCDCAM_LC_DMA_INT_ST_LCD_VSYNC_INT_ST = 0x1
	// Position of LCD_TRANS_DONE_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST_Pos = 0x1
	// Bit mask of LCD_TRANS_DONE_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST_Msk = 0x2
	// Bit LCD_TRANS_DONE_INT_ST.
	LCDCAM_LC_DMA_INT_ST_LCD_TRANS_DONE_INT_ST = 0x2
	// Position of CAM_VSYNC_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_CAM_VSYNC_INT_ST_Pos = 0x2
	// Bit mask of CAM_VSYNC_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_CAM_VSYNC_INT_ST_Msk = 0x4
	// Bit CAM_VSYNC_INT_ST.
	LCDCAM_LC_DMA_INT_ST_CAM_VSYNC_INT_ST = 0x4
	// Position of CAM_HS_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_CAM_HS_INT_ST_Pos = 0x3
	// Bit mask of CAM_HS_INT_ST field.
	LCDCAM_LC_DMA_INT_ST_CAM_HS_INT_ST_Msk = 0x8
	// Bit CAM_HS_INT_ST.
	LCDCAM_LC_DMA_INT_ST_CAM_HS_INT_ST = 0x8

	// LC_DMA_INT_CLR: LCDCAM interrupt clear register.
	// Position of LCD_VSYNC_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_LCD_VSYNC_INT_CLR_Pos = 0x0
	// Bit mask of LCD_VSYNC_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_LCD_VSYNC_INT_CLR_Msk = 0x1
	// Bit LCD_VSYNC_INT_CLR.
	LCDCAM_LC_DMA_INT_CLR_LCD_VSYNC_INT_CLR = 0x1
	// Position of LCD_TRANS_DONE_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR_Pos = 0x1
	// Bit mask of LCD_TRANS_DONE_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR_Msk = 0x2
	// Bit LCD_TRANS_DONE_INT_CLR.
	LCDCAM_LC_DMA_INT_CLR_LCD_TRANS_DONE_INT_CLR = 0x2
	// Position of CAM_VSYNC_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_CAM_VSYNC_INT_CLR_Pos = 0x2
	// Bit mask of CAM_VSYNC_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_CAM_VSYNC_INT_CLR_Msk = 0x4
	// Bit CAM_VSYNC_INT_CLR.
	LCDCAM_LC_DMA_INT_CLR_CAM_VSYNC_INT_CLR = 0x4
	// Position of CAM_HS_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_CAM_HS_INT_CLR_Pos = 0x3
	// Bit mask of CAM_HS_INT_CLR field.
	LCDCAM_LC_DMA_INT_CLR_CAM_HS_INT_CLR_Msk = 0x8
	// Bit CAM_HS_INT_CLR.
	LCDCAM_LC_DMA_INT_CLR_CAM_HS_INT_CLR = 0x8

	// LC_REG_DATE: Version register
	// Position of LC_DATE field.
	LCDCAM_LC_REG_DATE_LC_DATE_Pos = 0x0
	// Bit mask of LC_DATE field.
	LCDCAM_LC_REG_DATE_LC_DATE_Msk = 0xfffffff
)

// Constants for LEDC: LED Control PWM (Pulse Width Modulation)
const (
	// CH0_CONF0: Configuration register 0 for channel %s
	// Position of TIMER_SEL_CH field.
	LEDC_CH_CONF0_TIMER_SEL_CH_Pos = 0x0
	// Bit mask of TIMER_SEL_CH field.
	LEDC_CH_CONF0_TIMER_SEL_CH_Msk = 0x3
	// Position of SIG_OUT_EN_CH field.
	LEDC_CH_CONF0_SIG_OUT_EN_CH_Pos = 0x2
	// Bit mask of SIG_OUT_EN_CH field.
	LEDC_CH_CONF0_SIG_OUT_EN_CH_Msk = 0x4
	// Bit SIG_OUT_EN_CH.
	LEDC_CH_CONF0_SIG_OUT_EN_CH = 0x4
	// Position of IDLE_LV_CH field.
	LEDC_CH_CONF0_IDLE_LV_CH_Pos = 0x3
	// Bit mask of IDLE_LV_CH field.
	LEDC_CH_CONF0_IDLE_LV_CH_Msk = 0x8
	// Bit IDLE_LV_CH.
	LEDC_CH_CONF0_IDLE_LV_CH = 0x8
	// Position of PARA_UP_CH field.
	LEDC_CH_CONF0_PARA_UP_CH_Pos = 0x4
	// Bit mask of PARA_UP_CH field.
	LEDC_CH_CONF0_PARA_UP_CH_Msk = 0x10
	// Bit PARA_UP_CH.
	LEDC_CH_CONF0_PARA_UP_CH = 0x10
	// Position of OVF_NUM_CH field.
	LEDC_CH_CONF0_OVF_NUM_CH_Pos = 0x5
	// Bit mask of OVF_NUM_CH field.
	LEDC_CH_CONF0_OVF_NUM_CH_Msk = 0x7fe0
	// Position of OVF_CNT_EN_CH field.
	LEDC_CH_CONF0_OVF_CNT_EN_CH_Pos = 0xf
	// Bit mask of OVF_CNT_EN_CH field.
	LEDC_CH_CONF0_OVF_CNT_EN_CH_Msk = 0x8000
	// Bit OVF_CNT_EN_CH.
	LEDC_CH_CONF0_OVF_CNT_EN_CH = 0x8000
	// Position of OVF_CNT_RESET_CH field.
	LEDC_CH_CONF0_OVF_CNT_RESET_CH_Pos = 0x10
	// Bit mask of OVF_CNT_RESET_CH field.
	LEDC_CH_CONF0_OVF_CNT_RESET_CH_Msk = 0x10000
	// Bit OVF_CNT_RESET_CH.
	LEDC_CH_CONF0_OVF_CNT_RESET_CH = 0x10000

	// CH0_HPOINT: High point register for channel %s
	// Position of HPOINT_CH field.
	LEDC_CH_HPOINT_HPOINT_CH_Pos = 0x0
	// Bit mask of HPOINT_CH field.
	LEDC_CH_HPOINT_HPOINT_CH_Msk = 0xfffff

	// CH0_DUTY: Initial duty cycle register for channel %s
	// Position of DUTY_CH field.
	LEDC_CH_DUTY_DUTY_CH_Pos = 0x0
	// Bit mask of DUTY_CH field.
	LEDC_CH_DUTY_DUTY_CH_Msk = 0x1ffffff

	// CH0_CONF1: Configuration register 1 for channel %s
	// Position of DUTY_START_CH field.
	LEDC_CH_CONF1_DUTY_START_CH_Pos = 0x1f
	// Bit mask of DUTY_START_CH field.
	LEDC_CH_CONF1_DUTY_START_CH_Msk = 0x80000000
	// Bit DUTY_START_CH.
	LEDC_CH_CONF1_DUTY_START_CH = 0x80000000

	// CH0_DUTY_R: Current duty cycle register for channel %s
	// Position of DUTY_CH_R field.
	LEDC_CH_DUTY_R_DUTY_CH_R_Pos = 0x0
	// Bit mask of DUTY_CH_R field.
	LEDC_CH_DUTY_R_DUTY_CH_R_Msk = 0x1ffffff

	// TIMER0_CONF: Timer %s configuration register
	// Position of TIMER_DUTY_RES field.
	LEDC_TIMER_CONF_TIMER_DUTY_RES_Pos = 0x0
	// Bit mask of TIMER_DUTY_RES field.
	LEDC_TIMER_CONF_TIMER_DUTY_RES_Msk = 0x1f
	// Position of CLK_DIV_TIMER field.
	LEDC_TIMER_CONF_CLK_DIV_TIMER_Pos = 0x5
	// Bit mask of CLK_DIV_TIMER field.
	LEDC_TIMER_CONF_CLK_DIV_TIMER_Msk = 0x7fffe0
	// Position of TIMER_PAUSE field.
	LEDC_TIMER_CONF_TIMER_PAUSE_Pos = 0x17
	// Bit mask of TIMER_PAUSE field.
	LEDC_TIMER_CONF_TIMER_PAUSE_Msk = 0x800000
	// Bit TIMER_PAUSE.
	LEDC_TIMER_CONF_TIMER_PAUSE = 0x800000
	// Position of TIMER_RST field.
	LEDC_TIMER_CONF_TIMER_RST_Pos = 0x18
	// Bit mask of TIMER_RST field.
	LEDC_TIMER_CONF_TIMER_RST_Msk = 0x1000000
	// Bit TIMER_RST.
	LEDC_TIMER_CONF_TIMER_RST = 0x1000000
	// Position of TICK_SEL_TIMER field.
	LEDC_TIMER_CONF_TICK_SEL_TIMER_Pos = 0x19
	// Bit mask of TICK_SEL_TIMER field.
	LEDC_TIMER_CONF_TICK_SEL_TIMER_Msk = 0x2000000
	// Bit TICK_SEL_TIMER.
	LEDC_TIMER_CONF_TICK_SEL_TIMER = 0x2000000
	// Position of TIMER_PARA_UP field.
	LEDC_TIMER_CONF_TIMER_PARA_UP_Pos = 0x1a
	// Bit mask of TIMER_PARA_UP field.
	LEDC_TIMER_CONF_TIMER_PARA_UP_Msk = 0x4000000
	// Bit TIMER_PARA_UP.
	LEDC_TIMER_CONF_TIMER_PARA_UP = 0x4000000

	// TIMER0_VALUE: Timer %s current counter value register
	// Position of TIMER_CNT field.
	LEDC_TIMER_VALUE_TIMER_CNT_Pos = 0x0
	// Bit mask of TIMER_CNT field.
	LEDC_TIMER_VALUE_TIMER_CNT_Msk = 0xfffff

	// INT_RAW: Interrupt raw status register
	// Position of TIMER0_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Pos = 0x0
	// Bit mask of TIMER0_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER0_OVF_INT_RAW_Msk = 0x1
	// Bit TIMER0_OVF_INT_RAW.
	LEDC_INT_RAW_TIMER0_OVF_INT_RAW = 0x1
	// Position of TIMER1_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Pos = 0x1
	// Bit mask of TIMER1_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER1_OVF_INT_RAW_Msk = 0x2
	// Bit TIMER1_OVF_INT_RAW.
	LEDC_INT_RAW_TIMER1_OVF_INT_RAW = 0x2
	// Position of TIMER2_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Pos = 0x2
	// Bit mask of TIMER2_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER2_OVF_INT_RAW_Msk = 0x4
	// Bit TIMER2_OVF_INT_RAW.
	LEDC_INT_RAW_TIMER2_OVF_INT_RAW = 0x4
	// Position of TIMER3_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Pos = 0x3
	// Bit mask of TIMER3_OVF_INT_RAW field.
	LEDC_INT_RAW_TIMER3_OVF_INT_RAW_Msk = 0x8
	// Bit TIMER3_OVF_INT_RAW.
	LEDC_INT_RAW_TIMER3_OVF_INT_RAW = 0x8
	// Position of DUTY_CHNG_END_CH0_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Pos = 0x4
	// Bit mask of DUTY_CHNG_END_CH0_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW_Msk = 0x10
	// Bit DUTY_CHNG_END_CH0_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH0_INT_RAW = 0x10
	// Position of DUTY_CHNG_END_CH1_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Pos = 0x5
	// Bit mask of DUTY_CHNG_END_CH1_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW_Msk = 0x20
	// Bit DUTY_CHNG_END_CH1_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH1_INT_RAW = 0x20
	// Position of DUTY_CHNG_END_CH2_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Pos = 0x6
	// Bit mask of DUTY_CHNG_END_CH2_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW_Msk = 0x40
	// Bit DUTY_CHNG_END_CH2_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH2_INT_RAW = 0x40
	// Position of DUTY_CHNG_END_CH3_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Pos = 0x7
	// Bit mask of DUTY_CHNG_END_CH3_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW_Msk = 0x80
	// Bit DUTY_CHNG_END_CH3_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH3_INT_RAW = 0x80
	// Position of DUTY_CHNG_END_CH4_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Pos = 0x8
	// Bit mask of DUTY_CHNG_END_CH4_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW_Msk = 0x100
	// Bit DUTY_CHNG_END_CH4_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH4_INT_RAW = 0x100
	// Position of DUTY_CHNG_END_CH5_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Pos = 0x9
	// Bit mask of DUTY_CHNG_END_CH5_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW_Msk = 0x200
	// Bit DUTY_CHNG_END_CH5_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH5_INT_RAW = 0x200
	// Position of DUTY_CHNG_END_CH6_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW_Pos = 0xa
	// Bit mask of DUTY_CHNG_END_CH6_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW_Msk = 0x400
	// Bit DUTY_CHNG_END_CH6_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH6_INT_RAW = 0x400
	// Position of DUTY_CHNG_END_CH7_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW_Pos = 0xb
	// Bit mask of DUTY_CHNG_END_CH7_INT_RAW field.
	LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW_Msk = 0x800
	// Bit DUTY_CHNG_END_CH7_INT_RAW.
	LEDC_INT_RAW_DUTY_CHNG_END_CH7_INT_RAW = 0x800
	// Position of OVF_CNT_CH0_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Pos = 0xc
	// Bit mask of OVF_CNT_CH0_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW_Msk = 0x1000
	// Bit OVF_CNT_CH0_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH0_INT_RAW = 0x1000
	// Position of OVF_CNT_CH1_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Pos = 0xd
	// Bit mask of OVF_CNT_CH1_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW_Msk = 0x2000
	// Bit OVF_CNT_CH1_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH1_INT_RAW = 0x2000
	// Position of OVF_CNT_CH2_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Pos = 0xe
	// Bit mask of OVF_CNT_CH2_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW_Msk = 0x4000
	// Bit OVF_CNT_CH2_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH2_INT_RAW = 0x4000
	// Position of OVF_CNT_CH3_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Pos = 0xf
	// Bit mask of OVF_CNT_CH3_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW_Msk = 0x8000
	// Bit OVF_CNT_CH3_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH3_INT_RAW = 0x8000
	// Position of OVF_CNT_CH4_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Pos = 0x10
	// Bit mask of OVF_CNT_CH4_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW_Msk = 0x10000
	// Bit OVF_CNT_CH4_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH4_INT_RAW = 0x10000
	// Position of OVF_CNT_CH5_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Pos = 0x11
	// Bit mask of OVF_CNT_CH5_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW_Msk = 0x20000
	// Bit OVF_CNT_CH5_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH5_INT_RAW = 0x20000
	// Position of OVF_CNT_CH6_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW_Pos = 0x12
	// Bit mask of OVF_CNT_CH6_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW_Msk = 0x40000
	// Bit OVF_CNT_CH6_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH6_INT_RAW = 0x40000
	// Position of OVF_CNT_CH7_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW_Pos = 0x13
	// Bit mask of OVF_CNT_CH7_INT_RAW field.
	LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW_Msk = 0x80000
	// Bit OVF_CNT_CH7_INT_RAW.
	LEDC_INT_RAW_OVF_CNT_CH7_INT_RAW = 0x80000

	// INT_ST: Interrupt masked status register
	// Position of TIMER0_OVF_INT_ST field.
	LEDC_INT_ST_TIMER0_OVF_INT_ST_Pos = 0x0
	// Bit mask of TIMER0_OVF_INT_ST field.
	LEDC_INT_ST_TIMER0_OVF_INT_ST_Msk = 0x1
	// Bit TIMER0_OVF_INT_ST.
	LEDC_INT_ST_TIMER0_OVF_INT_ST = 0x1
	// Position of TIMER1_OVF_INT_ST field.
	LEDC_INT_ST_TIMER1_OVF_INT_ST_Pos = 0x1
	// Bit mask of TIMER1_OVF_INT_ST field.
	LEDC_INT_ST_TIMER1_OVF_INT_ST_Msk = 0x2
	// Bit TIMER1_OVF_INT_ST.
	LEDC_INT_ST_TIMER1_OVF_INT_ST = 0x2
	// Position of TIMER2_OVF_INT_ST field.
	LEDC_INT_ST_TIMER2_OVF_INT_ST_Pos = 0x2
	// Bit mask of TIMER2_OVF_INT_ST field.
	LEDC_INT_ST_TIMER2_OVF_INT_ST_Msk = 0x4
	// Bit TIMER2_OVF_INT_ST.
	LEDC_INT_ST_TIMER2_OVF_INT_ST = 0x4
	// Position of TIMER3_OVF_INT_ST field.
	LEDC_INT_ST_TIMER3_OVF_INT_ST_Pos = 0x3
	// Bit mask of TIMER3_OVF_INT_ST field.
	LEDC_INT_ST_TIMER3_OVF_INT_ST_Msk = 0x8
	// Bit TIMER3_OVF_INT_ST.
	LEDC_INT_ST_TIMER3_OVF_INT_ST = 0x8
	// Position of DUTY_CHNG_END_CH0_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Pos = 0x4
	// Bit mask of DUTY_CHNG_END_CH0_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST_Msk = 0x10
	// Bit DUTY_CHNG_END_CH0_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH0_INT_ST = 0x10
	// Position of DUTY_CHNG_END_CH1_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Pos = 0x5
	// Bit mask of DUTY_CHNG_END_CH1_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST_Msk = 0x20
	// Bit DUTY_CHNG_END_CH1_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH1_INT_ST = 0x20
	// Position of DUTY_CHNG_END_CH2_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Pos = 0x6
	// Bit mask of DUTY_CHNG_END_CH2_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST_Msk = 0x40
	// Bit DUTY_CHNG_END_CH2_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH2_INT_ST = 0x40
	// Position of DUTY_CHNG_END_CH3_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Pos = 0x7
	// Bit mask of DUTY_CHNG_END_CH3_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST_Msk = 0x80
	// Bit DUTY_CHNG_END_CH3_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH3_INT_ST = 0x80
	// Position of DUTY_CHNG_END_CH4_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Pos = 0x8
	// Bit mask of DUTY_CHNG_END_CH4_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST_Msk = 0x100
	// Bit DUTY_CHNG_END_CH4_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH4_INT_ST = 0x100
	// Position of DUTY_CHNG_END_CH5_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Pos = 0x9
	// Bit mask of DUTY_CHNG_END_CH5_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST_Msk = 0x200
	// Bit DUTY_CHNG_END_CH5_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH5_INT_ST = 0x200
	// Position of DUTY_CHNG_END_CH6_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST_Pos = 0xa
	// Bit mask of DUTY_CHNG_END_CH6_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST_Msk = 0x400
	// Bit DUTY_CHNG_END_CH6_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH6_INT_ST = 0x400
	// Position of DUTY_CHNG_END_CH7_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST_Pos = 0xb
	// Bit mask of DUTY_CHNG_END_CH7_INT_ST field.
	LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST_Msk = 0x800
	// Bit DUTY_CHNG_END_CH7_INT_ST.
	LEDC_INT_ST_DUTY_CHNG_END_CH7_INT_ST = 0x800
	// Position of OVF_CNT_CH0_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Pos = 0xc
	// Bit mask of OVF_CNT_CH0_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH0_INT_ST_Msk = 0x1000
	// Bit OVF_CNT_CH0_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH0_INT_ST = 0x1000
	// Position of OVF_CNT_CH1_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Pos = 0xd
	// Bit mask of OVF_CNT_CH1_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH1_INT_ST_Msk = 0x2000
	// Bit OVF_CNT_CH1_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH1_INT_ST = 0x2000
	// Position of OVF_CNT_CH2_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Pos = 0xe
	// Bit mask of OVF_CNT_CH2_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH2_INT_ST_Msk = 0x4000
	// Bit OVF_CNT_CH2_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH2_INT_ST = 0x4000
	// Position of OVF_CNT_CH3_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Pos = 0xf
	// Bit mask of OVF_CNT_CH3_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH3_INT_ST_Msk = 0x8000
	// Bit OVF_CNT_CH3_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH3_INT_ST = 0x8000
	// Position of OVF_CNT_CH4_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Pos = 0x10
	// Bit mask of OVF_CNT_CH4_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH4_INT_ST_Msk = 0x10000
	// Bit OVF_CNT_CH4_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH4_INT_ST = 0x10000
	// Position of OVF_CNT_CH5_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Pos = 0x11
	// Bit mask of OVF_CNT_CH5_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH5_INT_ST_Msk = 0x20000
	// Bit OVF_CNT_CH5_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH5_INT_ST = 0x20000
	// Position of OVF_CNT_CH6_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH6_INT_ST_Pos = 0x12
	// Bit mask of OVF_CNT_CH6_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH6_INT_ST_Msk = 0x40000
	// Bit OVF_CNT_CH6_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH6_INT_ST = 0x40000
	// Position of OVF_CNT_CH7_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH7_INT_ST_Pos = 0x13
	// Bit mask of OVF_CNT_CH7_INT_ST field.
	LEDC_INT_ST_OVF_CNT_CH7_INT_ST_Msk = 0x80000
	// Bit OVF_CNT_CH7_INT_ST.
	LEDC_INT_ST_OVF_CNT_CH7_INT_ST = 0x80000

	// INT_ENA: Interrupt enable register
	// Position of TIMER0_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Pos = 0x0
	// Bit mask of TIMER0_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER0_OVF_INT_ENA_Msk = 0x1
	// Bit TIMER0_OVF_INT_ENA.
	LEDC_INT_ENA_TIMER0_OVF_INT_ENA = 0x1
	// Position of TIMER1_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Pos = 0x1
	// Bit mask of TIMER1_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER1_OVF_INT_ENA_Msk = 0x2
	// Bit TIMER1_OVF_INT_ENA.
	LEDC_INT_ENA_TIMER1_OVF_INT_ENA = 0x2
	// Position of TIMER2_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Pos = 0x2
	// Bit mask of TIMER2_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER2_OVF_INT_ENA_Msk = 0x4
	// Bit TIMER2_OVF_INT_ENA.
	LEDC_INT_ENA_TIMER2_OVF_INT_ENA = 0x4
	// Position of TIMER3_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Pos = 0x3
	// Bit mask of TIMER3_OVF_INT_ENA field.
	LEDC_INT_ENA_TIMER3_OVF_INT_ENA_Msk = 0x8
	// Bit TIMER3_OVF_INT_ENA.
	LEDC_INT_ENA_TIMER3_OVF_INT_ENA = 0x8
	// Position of DUTY_CHNG_END_CH0_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Pos = 0x4
	// Bit mask of DUTY_CHNG_END_CH0_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA_Msk = 0x10
	// Bit DUTY_CHNG_END_CH0_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH0_INT_ENA = 0x10
	// Position of DUTY_CHNG_END_CH1_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Pos = 0x5
	// Bit mask of DUTY_CHNG_END_CH1_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA_Msk = 0x20
	// Bit DUTY_CHNG_END_CH1_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH1_INT_ENA = 0x20
	// Position of DUTY_CHNG_END_CH2_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Pos = 0x6
	// Bit mask of DUTY_CHNG_END_CH2_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA_Msk = 0x40
	// Bit DUTY_CHNG_END_CH2_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH2_INT_ENA = 0x40
	// Position of DUTY_CHNG_END_CH3_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Pos = 0x7
	// Bit mask of DUTY_CHNG_END_CH3_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA_Msk = 0x80
	// Bit DUTY_CHNG_END_CH3_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH3_INT_ENA = 0x80
	// Position of DUTY_CHNG_END_CH4_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Pos = 0x8
	// Bit mask of DUTY_CHNG_END_CH4_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA_Msk = 0x100
	// Bit DUTY_CHNG_END_CH4_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH4_INT_ENA = 0x100
	// Position of DUTY_CHNG_END_CH5_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Pos = 0x9
	// Bit mask of DUTY_CHNG_END_CH5_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA_Msk = 0x200
	// Bit DUTY_CHNG_END_CH5_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH5_INT_ENA = 0x200
	// Position of DUTY_CHNG_END_CH6_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA_Pos = 0xa
	// Bit mask of DUTY_CHNG_END_CH6_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA_Msk = 0x400
	// Bit DUTY_CHNG_END_CH6_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH6_INT_ENA = 0x400
	// Position of DUTY_CHNG_END_CH7_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA_Pos = 0xb
	// Bit mask of DUTY_CHNG_END_CH7_INT_ENA field.
	LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA_Msk = 0x800
	// Bit DUTY_CHNG_END_CH7_INT_ENA.
	LEDC_INT_ENA_DUTY_CHNG_END_CH7_INT_ENA = 0x800
	// Position of OVF_CNT_CH0_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Pos = 0xc
	// Bit mask of OVF_CNT_CH0_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA_Msk = 0x1000
	// Bit OVF_CNT_CH0_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH0_INT_ENA = 0x1000
	// Position of OVF_CNT_CH1_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Pos = 0xd
	// Bit mask of OVF_CNT_CH1_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA_Msk = 0x2000
	// Bit OVF_CNT_CH1_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH1_INT_ENA = 0x2000
	// Position of OVF_CNT_CH2_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Pos = 0xe
	// Bit mask of OVF_CNT_CH2_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA_Msk = 0x4000
	// Bit OVF_CNT_CH2_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH2_INT_ENA = 0x4000
	// Position of OVF_CNT_CH3_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Pos = 0xf
	// Bit mask of OVF_CNT_CH3_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA_Msk = 0x8000
	// Bit OVF_CNT_CH3_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH3_INT_ENA = 0x8000
	// Position of OVF_CNT_CH4_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Pos = 0x10
	// Bit mask of OVF_CNT_CH4_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA_Msk = 0x10000
	// Bit OVF_CNT_CH4_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH4_INT_ENA = 0x10000
	// Position of OVF_CNT_CH5_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Pos = 0x11
	// Bit mask of OVF_CNT_CH5_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA_Msk = 0x20000
	// Bit OVF_CNT_CH5_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH5_INT_ENA = 0x20000
	// Position of OVF_CNT_CH6_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA_Pos = 0x12
	// Bit mask of OVF_CNT_CH6_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA_Msk = 0x40000
	// Bit OVF_CNT_CH6_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH6_INT_ENA = 0x40000
	// Position of OVF_CNT_CH7_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA_Pos = 0x13
	// Bit mask of OVF_CNT_CH7_INT_ENA field.
	LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA_Msk = 0x80000
	// Bit OVF_CNT_CH7_INT_ENA.
	LEDC_INT_ENA_OVF_CNT_CH7_INT_ENA = 0x80000

	// INT_CLR: Interrupt clear register
	// Position of TIMER0_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Pos = 0x0
	// Bit mask of TIMER0_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER0_OVF_INT_CLR_Msk = 0x1
	// Bit TIMER0_OVF_INT_CLR.
	LEDC_INT_CLR_TIMER0_OVF_INT_CLR = 0x1
	// Position of TIMER1_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Pos = 0x1
	// Bit mask of TIMER1_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER1_OVF_INT_CLR_Msk = 0x2
	// Bit TIMER1_OVF_INT_CLR.
	LEDC_INT_CLR_TIMER1_OVF_INT_CLR = 0x2
	// Position of TIMER2_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Pos = 0x2
	// Bit mask of TIMER2_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER2_OVF_INT_CLR_Msk = 0x4
	// Bit TIMER2_OVF_INT_CLR.
	LEDC_INT_CLR_TIMER2_OVF_INT_CLR = 0x4
	// Position of TIMER3_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Pos = 0x3
	// Bit mask of TIMER3_OVF_INT_CLR field.
	LEDC_INT_CLR_TIMER3_OVF_INT_CLR_Msk = 0x8
	// Bit TIMER3_OVF_INT_CLR.
	LEDC_INT_CLR_TIMER3_OVF_INT_CLR = 0x8
	// Position of DUTY_CHNG_END_CH0_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Pos = 0x4
	// Bit mask of DUTY_CHNG_END_CH0_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR_Msk = 0x10
	// Bit DUTY_CHNG_END_CH0_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH0_INT_CLR = 0x10
	// Position of DUTY_CHNG_END_CH1_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Pos = 0x5
	// Bit mask of DUTY_CHNG_END_CH1_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR_Msk = 0x20
	// Bit DUTY_CHNG_END_CH1_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH1_INT_CLR = 0x20
	// Position of DUTY_CHNG_END_CH2_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Pos = 0x6
	// Bit mask of DUTY_CHNG_END_CH2_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR_Msk = 0x40
	// Bit DUTY_CHNG_END_CH2_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH2_INT_CLR = 0x40
	// Position of DUTY_CHNG_END_CH3_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Pos = 0x7
	// Bit mask of DUTY_CHNG_END_CH3_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR_Msk = 0x80
	// Bit DUTY_CHNG_END_CH3_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH3_INT_CLR = 0x80
	// Position of DUTY_CHNG_END_CH4_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Pos = 0x8
	// Bit mask of DUTY_CHNG_END_CH4_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR_Msk = 0x100
	// Bit DUTY_CHNG_END_CH4_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH4_INT_CLR = 0x100
	// Position of DUTY_CHNG_END_CH5_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Pos = 0x9
	// Bit mask of DUTY_CHNG_END_CH5_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR_Msk = 0x200
	// Bit DUTY_CHNG_END_CH5_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH5_INT_CLR = 0x200
	// Position of DUTY_CHNG_END_CH6_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR_Pos = 0xa
	// Bit mask of DUTY_CHNG_END_CH6_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR_Msk = 0x400
	// Bit DUTY_CHNG_END_CH6_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH6_INT_CLR = 0x400
	// Position of DUTY_CHNG_END_CH7_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR_Pos = 0xb
	// Bit mask of DUTY_CHNG_END_CH7_INT_CLR field.
	LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR_Msk = 0x800
	// Bit DUTY_CHNG_END_CH7_INT_CLR.
	LEDC_INT_CLR_DUTY_CHNG_END_CH7_INT_CLR = 0x800
	// Position of OVF_CNT_CH0_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Pos = 0xc
	// Bit mask of OVF_CNT_CH0_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR_Msk = 0x1000
	// Bit OVF_CNT_CH0_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH0_INT_CLR = 0x1000
	// Position of OVF_CNT_CH1_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Pos = 0xd
	// Bit mask of OVF_CNT_CH1_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR_Msk = 0x2000
	// Bit OVF_CNT_CH1_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH1_INT_CLR = 0x2000
	// Position of OVF_CNT_CH2_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Pos = 0xe
	// Bit mask of OVF_CNT_CH2_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR_Msk = 0x4000
	// Bit OVF_CNT_CH2_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH2_INT_CLR = 0x4000
	// Position of OVF_CNT_CH3_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Pos = 0xf
	// Bit mask of OVF_CNT_CH3_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR_Msk = 0x8000
	// Bit OVF_CNT_CH3_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH3_INT_CLR = 0x8000
	// Position of OVF_CNT_CH4_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Pos = 0x10
	// Bit mask of OVF_CNT_CH4_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR_Msk = 0x10000
	// Bit OVF_CNT_CH4_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH4_INT_CLR = 0x10000
	// Position of OVF_CNT_CH5_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Pos = 0x11
	// Bit mask of OVF_CNT_CH5_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR_Msk = 0x20000
	// Bit OVF_CNT_CH5_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH5_INT_CLR = 0x20000
	// Position of OVF_CNT_CH6_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR_Pos = 0x12
	// Bit mask of OVF_CNT_CH6_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR_Msk = 0x40000
	// Bit OVF_CNT_CH6_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH6_INT_CLR = 0x40000
	// Position of OVF_CNT_CH7_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR_Pos = 0x13
	// Bit mask of OVF_CNT_CH7_INT_CLR field.
	LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR_Msk = 0x80000
	// Bit OVF_CNT_CH7_INT_CLR.
	LEDC_INT_CLR_OVF_CNT_CH7_INT_CLR = 0x80000

	// CH0_GAMMA_CONF: Ledc ch%s gamma config register.
	// Position of CH_GAMMA_ENTRY_NUM field.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_ENTRY_NUM_Pos = 0x0
	// Bit mask of CH_GAMMA_ENTRY_NUM field.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_ENTRY_NUM_Msk = 0x1f
	// Position of CH_GAMMA_PAUSE field.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE_Pos = 0x5
	// Bit mask of CH_GAMMA_PAUSE field.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE_Msk = 0x20
	// Bit CH_GAMMA_PAUSE.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_PAUSE = 0x20
	// Position of CH_GAMMA_RESUME field.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME_Pos = 0x6
	// Bit mask of CH_GAMMA_RESUME field.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME_Msk = 0x40
	// Bit CH_GAMMA_RESUME.
	LEDC_CH_GAMMA_CONF_CH_GAMMA_RESUME = 0x40

	// EVT_TASK_EN0: Ledc event task enable bit register0.
	// Position of EVT_DUTY_CHNG_END_CH0_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN_Pos = 0x0
	// Bit mask of EVT_DUTY_CHNG_END_CH0_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN_Msk = 0x1
	// Bit EVT_DUTY_CHNG_END_CH0_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH0_EN = 0x1
	// Position of EVT_DUTY_CHNG_END_CH1_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN_Pos = 0x1
	// Bit mask of EVT_DUTY_CHNG_END_CH1_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN_Msk = 0x2
	// Bit EVT_DUTY_CHNG_END_CH1_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH1_EN = 0x2
	// Position of EVT_DUTY_CHNG_END_CH2_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN_Pos = 0x2
	// Bit mask of EVT_DUTY_CHNG_END_CH2_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN_Msk = 0x4
	// Bit EVT_DUTY_CHNG_END_CH2_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH2_EN = 0x4
	// Position of EVT_DUTY_CHNG_END_CH3_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN_Pos = 0x3
	// Bit mask of EVT_DUTY_CHNG_END_CH3_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN_Msk = 0x8
	// Bit EVT_DUTY_CHNG_END_CH3_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH3_EN = 0x8
	// Position of EVT_DUTY_CHNG_END_CH4_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN_Pos = 0x4
	// Bit mask of EVT_DUTY_CHNG_END_CH4_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN_Msk = 0x10
	// Bit EVT_DUTY_CHNG_END_CH4_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH4_EN = 0x10
	// Position of EVT_DUTY_CHNG_END_CH5_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN_Pos = 0x5
	// Bit mask of EVT_DUTY_CHNG_END_CH5_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN_Msk = 0x20
	// Bit EVT_DUTY_CHNG_END_CH5_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH5_EN = 0x20
	// Position of EVT_DUTY_CHNG_END_CH6_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH6_EN_Pos = 0x6
	// Bit mask of EVT_DUTY_CHNG_END_CH6_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH6_EN_Msk = 0x40
	// Bit EVT_DUTY_CHNG_END_CH6_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH6_EN = 0x40
	// Position of EVT_DUTY_CHNG_END_CH7_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH7_EN_Pos = 0x7
	// Bit mask of EVT_DUTY_CHNG_END_CH7_EN field.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH7_EN_Msk = 0x80
	// Bit EVT_DUTY_CHNG_END_CH7_EN.
	LEDC_EVT_TASK_EN0_EVT_DUTY_CHNG_END_CH7_EN = 0x80
	// Position of EVT_OVF_CNT_PLS_CH0_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN_Pos = 0x8
	// Bit mask of EVT_OVF_CNT_PLS_CH0_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN_Msk = 0x100
	// Bit EVT_OVF_CNT_PLS_CH0_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH0_EN = 0x100
	// Position of EVT_OVF_CNT_PLS_CH1_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN_Pos = 0x9
	// Bit mask of EVT_OVF_CNT_PLS_CH1_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN_Msk = 0x200
	// Bit EVT_OVF_CNT_PLS_CH1_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH1_EN = 0x200
	// Position of EVT_OVF_CNT_PLS_CH2_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN_Pos = 0xa
	// Bit mask of EVT_OVF_CNT_PLS_CH2_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN_Msk = 0x400
	// Bit EVT_OVF_CNT_PLS_CH2_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH2_EN = 0x400
	// Position of EVT_OVF_CNT_PLS_CH3_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN_Pos = 0xb
	// Bit mask of EVT_OVF_CNT_PLS_CH3_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN_Msk = 0x800
	// Bit EVT_OVF_CNT_PLS_CH3_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH3_EN = 0x800
	// Position of EVT_OVF_CNT_PLS_CH4_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN_Pos = 0xc
	// Bit mask of EVT_OVF_CNT_PLS_CH4_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN_Msk = 0x1000
	// Bit EVT_OVF_CNT_PLS_CH4_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH4_EN = 0x1000
	// Position of EVT_OVF_CNT_PLS_CH5_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN_Pos = 0xd
	// Bit mask of EVT_OVF_CNT_PLS_CH5_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN_Msk = 0x2000
	// Bit EVT_OVF_CNT_PLS_CH5_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH5_EN = 0x2000
	// Position of EVT_OVF_CNT_PLS_CH6_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH6_EN_Pos = 0xe
	// Bit mask of EVT_OVF_CNT_PLS_CH6_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH6_EN_Msk = 0x4000
	// Bit EVT_OVF_CNT_PLS_CH6_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH6_EN = 0x4000
	// Position of EVT_OVF_CNT_PLS_CH7_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH7_EN_Pos = 0xf
	// Bit mask of EVT_OVF_CNT_PLS_CH7_EN field.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH7_EN_Msk = 0x8000
	// Bit EVT_OVF_CNT_PLS_CH7_EN.
	LEDC_EVT_TASK_EN0_EVT_OVF_CNT_PLS_CH7_EN = 0x8000
	// Position of EVT_TIME_OVF_TIMER0_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN_Pos = 0x10
	// Bit mask of EVT_TIME_OVF_TIMER0_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN_Msk = 0x10000
	// Bit EVT_TIME_OVF_TIMER0_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER0_EN = 0x10000
	// Position of EVT_TIME_OVF_TIMER1_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN_Pos = 0x11
	// Bit mask of EVT_TIME_OVF_TIMER1_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN_Msk = 0x20000
	// Bit EVT_TIME_OVF_TIMER1_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER1_EN = 0x20000
	// Position of EVT_TIME_OVF_TIMER2_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN_Pos = 0x12
	// Bit mask of EVT_TIME_OVF_TIMER2_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN_Msk = 0x40000
	// Bit EVT_TIME_OVF_TIMER2_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER2_EN = 0x40000
	// Position of EVT_TIME_OVF_TIMER3_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN_Pos = 0x13
	// Bit mask of EVT_TIME_OVF_TIMER3_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN_Msk = 0x80000
	// Bit EVT_TIME_OVF_TIMER3_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME_OVF_TIMER3_EN = 0x80000
	// Position of EVT_TIME0_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN_Pos = 0x14
	// Bit mask of EVT_TIME0_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN_Msk = 0x100000
	// Bit EVT_TIME0_CMP_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME0_CMP_EN = 0x100000
	// Position of EVT_TIME1_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN_Pos = 0x15
	// Bit mask of EVT_TIME1_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN_Msk = 0x200000
	// Bit EVT_TIME1_CMP_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME1_CMP_EN = 0x200000
	// Position of EVT_TIME2_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN_Pos = 0x16
	// Bit mask of EVT_TIME2_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN_Msk = 0x400000
	// Bit EVT_TIME2_CMP_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME2_CMP_EN = 0x400000
	// Position of EVT_TIME3_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN_Pos = 0x17
	// Bit mask of EVT_TIME3_CMP_EN field.
	LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN_Msk = 0x800000
	// Bit EVT_TIME3_CMP_EN.
	LEDC_EVT_TASK_EN0_EVT_TIME3_CMP_EN = 0x800000
	// Position of TASK_DUTY_SCALE_UPDATE_CH0_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN_Pos = 0x18
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH0_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN_Msk = 0x1000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH0_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH0_EN = 0x1000000
	// Position of TASK_DUTY_SCALE_UPDATE_CH1_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN_Pos = 0x19
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH1_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN_Msk = 0x2000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH1_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH1_EN = 0x2000000
	// Position of TASK_DUTY_SCALE_UPDATE_CH2_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN_Pos = 0x1a
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH2_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN_Msk = 0x4000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH2_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH2_EN = 0x4000000
	// Position of TASK_DUTY_SCALE_UPDATE_CH3_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN_Pos = 0x1b
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH3_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN_Msk = 0x8000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH3_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH3_EN = 0x8000000
	// Position of TASK_DUTY_SCALE_UPDATE_CH4_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN_Pos = 0x1c
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH4_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN_Msk = 0x10000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH4_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH4_EN = 0x10000000
	// Position of TASK_DUTY_SCALE_UPDATE_CH5_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN_Pos = 0x1d
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH5_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN_Msk = 0x20000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH5_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH5_EN = 0x20000000
	// Position of TASK_DUTY_SCALE_UPDATE_CH6_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH6_EN_Pos = 0x1e
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH6_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH6_EN_Msk = 0x40000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH6_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH6_EN = 0x40000000
	// Position of TASK_DUTY_SCALE_UPDATE_CH7_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH7_EN_Pos = 0x1f
	// Bit mask of TASK_DUTY_SCALE_UPDATE_CH7_EN field.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH7_EN_Msk = 0x80000000
	// Bit TASK_DUTY_SCALE_UPDATE_CH7_EN.
	LEDC_EVT_TASK_EN0_TASK_DUTY_SCALE_UPDATE_CH7_EN = 0x80000000

	// EVT_TASK_EN1: Ledc event task enable bit register1.
	// Position of TASK_TIMER0_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN_Pos = 0x0
	// Bit mask of TASK_TIMER0_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN_Msk = 0x1
	// Bit TASK_TIMER0_RES_UPDATE_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_RES_UPDATE_EN = 0x1
	// Position of TASK_TIMER1_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN_Pos = 0x1
	// Bit mask of TASK_TIMER1_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN_Msk = 0x2
	// Bit TASK_TIMER1_RES_UPDATE_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_RES_UPDATE_EN = 0x2
	// Position of TASK_TIMER2_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN_Pos = 0x2
	// Bit mask of TASK_TIMER2_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN_Msk = 0x4
	// Bit TASK_TIMER2_RES_UPDATE_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_RES_UPDATE_EN = 0x4
	// Position of TASK_TIMER3_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN_Pos = 0x3
	// Bit mask of TASK_TIMER3_RES_UPDATE_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN_Msk = 0x8
	// Bit TASK_TIMER3_RES_UPDATE_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_RES_UPDATE_EN = 0x8
	// Position of TASK_TIMER0_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN_Pos = 0x4
	// Bit mask of TASK_TIMER0_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN_Msk = 0x10
	// Bit TASK_TIMER0_CAP_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_CAP_EN = 0x10
	// Position of TASK_TIMER1_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN_Pos = 0x5
	// Bit mask of TASK_TIMER1_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN_Msk = 0x20
	// Bit TASK_TIMER1_CAP_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_CAP_EN = 0x20
	// Position of TASK_TIMER2_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN_Pos = 0x6
	// Bit mask of TASK_TIMER2_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN_Msk = 0x40
	// Bit TASK_TIMER2_CAP_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_CAP_EN = 0x40
	// Position of TASK_TIMER3_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN_Pos = 0x7
	// Bit mask of TASK_TIMER3_CAP_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN_Msk = 0x80
	// Bit TASK_TIMER3_CAP_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_CAP_EN = 0x80
	// Position of TASK_SIG_OUT_DIS_CH0_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN_Pos = 0x8
	// Bit mask of TASK_SIG_OUT_DIS_CH0_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN_Msk = 0x100
	// Bit TASK_SIG_OUT_DIS_CH0_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH0_EN = 0x100
	// Position of TASK_SIG_OUT_DIS_CH1_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN_Pos = 0x9
	// Bit mask of TASK_SIG_OUT_DIS_CH1_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN_Msk = 0x200
	// Bit TASK_SIG_OUT_DIS_CH1_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH1_EN = 0x200
	// Position of TASK_SIG_OUT_DIS_CH2_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN_Pos = 0xa
	// Bit mask of TASK_SIG_OUT_DIS_CH2_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN_Msk = 0x400
	// Bit TASK_SIG_OUT_DIS_CH2_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH2_EN = 0x400
	// Position of TASK_SIG_OUT_DIS_CH3_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN_Pos = 0xb
	// Bit mask of TASK_SIG_OUT_DIS_CH3_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN_Msk = 0x800
	// Bit TASK_SIG_OUT_DIS_CH3_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH3_EN = 0x800
	// Position of TASK_SIG_OUT_DIS_CH4_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN_Pos = 0xc
	// Bit mask of TASK_SIG_OUT_DIS_CH4_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN_Msk = 0x1000
	// Bit TASK_SIG_OUT_DIS_CH4_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH4_EN = 0x1000
	// Position of TASK_SIG_OUT_DIS_CH5_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN_Pos = 0xd
	// Bit mask of TASK_SIG_OUT_DIS_CH5_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN_Msk = 0x2000
	// Bit TASK_SIG_OUT_DIS_CH5_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH5_EN = 0x2000
	// Position of TASK_SIG_OUT_DIS_CH6_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH6_EN_Pos = 0xe
	// Bit mask of TASK_SIG_OUT_DIS_CH6_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH6_EN_Msk = 0x4000
	// Bit TASK_SIG_OUT_DIS_CH6_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH6_EN = 0x4000
	// Position of TASK_SIG_OUT_DIS_CH7_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH7_EN_Pos = 0xf
	// Bit mask of TASK_SIG_OUT_DIS_CH7_EN field.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH7_EN_Msk = 0x8000
	// Bit TASK_SIG_OUT_DIS_CH7_EN.
	LEDC_EVT_TASK_EN1_TASK_SIG_OUT_DIS_CH7_EN = 0x8000
	// Position of TASK_OVF_CNT_RST_CH0_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN_Pos = 0x10
	// Bit mask of TASK_OVF_CNT_RST_CH0_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN_Msk = 0x10000
	// Bit TASK_OVF_CNT_RST_CH0_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH0_EN = 0x10000
	// Position of TASK_OVF_CNT_RST_CH1_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN_Pos = 0x11
	// Bit mask of TASK_OVF_CNT_RST_CH1_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN_Msk = 0x20000
	// Bit TASK_OVF_CNT_RST_CH1_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH1_EN = 0x20000
	// Position of TASK_OVF_CNT_RST_CH2_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN_Pos = 0x12
	// Bit mask of TASK_OVF_CNT_RST_CH2_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN_Msk = 0x40000
	// Bit TASK_OVF_CNT_RST_CH2_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH2_EN = 0x40000
	// Position of TASK_OVF_CNT_RST_CH3_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN_Pos = 0x13
	// Bit mask of TASK_OVF_CNT_RST_CH3_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN_Msk = 0x80000
	// Bit TASK_OVF_CNT_RST_CH3_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH3_EN = 0x80000
	// Position of TASK_OVF_CNT_RST_CH4_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN_Pos = 0x14
	// Bit mask of TASK_OVF_CNT_RST_CH4_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN_Msk = 0x100000
	// Bit TASK_OVF_CNT_RST_CH4_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH4_EN = 0x100000
	// Position of TASK_OVF_CNT_RST_CH5_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN_Pos = 0x15
	// Bit mask of TASK_OVF_CNT_RST_CH5_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN_Msk = 0x200000
	// Bit TASK_OVF_CNT_RST_CH5_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH5_EN = 0x200000
	// Position of TASK_OVF_CNT_RST_CH6_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH6_EN_Pos = 0x16
	// Bit mask of TASK_OVF_CNT_RST_CH6_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH6_EN_Msk = 0x400000
	// Bit TASK_OVF_CNT_RST_CH6_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH6_EN = 0x400000
	// Position of TASK_OVF_CNT_RST_CH7_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH7_EN_Pos = 0x17
	// Bit mask of TASK_OVF_CNT_RST_CH7_EN field.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH7_EN_Msk = 0x800000
	// Bit TASK_OVF_CNT_RST_CH7_EN.
	LEDC_EVT_TASK_EN1_TASK_OVF_CNT_RST_CH7_EN = 0x800000
	// Position of TASK_TIMER0_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN_Pos = 0x18
	// Bit mask of TASK_TIMER0_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN_Msk = 0x1000000
	// Bit TASK_TIMER0_RST_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_RST_EN = 0x1000000
	// Position of TASK_TIMER1_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN_Pos = 0x19
	// Bit mask of TASK_TIMER1_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN_Msk = 0x2000000
	// Bit TASK_TIMER1_RST_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_RST_EN = 0x2000000
	// Position of TASK_TIMER2_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN_Pos = 0x1a
	// Bit mask of TASK_TIMER2_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN_Msk = 0x4000000
	// Bit TASK_TIMER2_RST_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_RST_EN = 0x4000000
	// Position of TASK_TIMER3_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN_Pos = 0x1b
	// Bit mask of TASK_TIMER3_RST_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN_Msk = 0x8000000
	// Bit TASK_TIMER3_RST_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_RST_EN = 0x8000000
	// Position of TASK_TIMER0_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN_Pos = 0x1c
	// Bit mask of TASK_TIMER0_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN_Msk = 0x10000000
	// Bit TASK_TIMER0_PAUSE_RESUME_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER0_PAUSE_RESUME_EN = 0x10000000
	// Position of TASK_TIMER1_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN_Pos = 0x1d
	// Bit mask of TASK_TIMER1_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN_Msk = 0x20000000
	// Bit TASK_TIMER1_PAUSE_RESUME_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER1_PAUSE_RESUME_EN = 0x20000000
	// Position of TASK_TIMER2_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN_Pos = 0x1e
	// Bit mask of TASK_TIMER2_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN_Msk = 0x40000000
	// Bit TASK_TIMER2_PAUSE_RESUME_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER2_PAUSE_RESUME_EN = 0x40000000
	// Position of TASK_TIMER3_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN_Pos = 0x1f
	// Bit mask of TASK_TIMER3_PAUSE_RESUME_EN field.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN_Msk = 0x80000000
	// Bit TASK_TIMER3_PAUSE_RESUME_EN.
	LEDC_EVT_TASK_EN1_TASK_TIMER3_PAUSE_RESUME_EN = 0x80000000

	// EVT_TASK_EN2: Ledc event task enable bit register2.
	// Position of TASK_GAMMA_RESTART_CH0_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN_Pos = 0x0
	// Bit mask of TASK_GAMMA_RESTART_CH0_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN_Msk = 0x1
	// Bit TASK_GAMMA_RESTART_CH0_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH0_EN = 0x1
	// Position of TASK_GAMMA_RESTART_CH1_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN_Pos = 0x1
	// Bit mask of TASK_GAMMA_RESTART_CH1_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN_Msk = 0x2
	// Bit TASK_GAMMA_RESTART_CH1_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH1_EN = 0x2
	// Position of TASK_GAMMA_RESTART_CH2_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN_Pos = 0x2
	// Bit mask of TASK_GAMMA_RESTART_CH2_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN_Msk = 0x4
	// Bit TASK_GAMMA_RESTART_CH2_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH2_EN = 0x4
	// Position of TASK_GAMMA_RESTART_CH3_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN_Pos = 0x3
	// Bit mask of TASK_GAMMA_RESTART_CH3_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN_Msk = 0x8
	// Bit TASK_GAMMA_RESTART_CH3_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH3_EN = 0x8
	// Position of TASK_GAMMA_RESTART_CH4_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN_Pos = 0x4
	// Bit mask of TASK_GAMMA_RESTART_CH4_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN_Msk = 0x10
	// Bit TASK_GAMMA_RESTART_CH4_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH4_EN = 0x10
	// Position of TASK_GAMMA_RESTART_CH5_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN_Pos = 0x5
	// Bit mask of TASK_GAMMA_RESTART_CH5_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN_Msk = 0x20
	// Bit TASK_GAMMA_RESTART_CH5_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH5_EN = 0x20
	// Position of TASK_GAMMA_RESTART_CH6_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH6_EN_Pos = 0x6
	// Bit mask of TASK_GAMMA_RESTART_CH6_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH6_EN_Msk = 0x40
	// Bit TASK_GAMMA_RESTART_CH6_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH6_EN = 0x40
	// Position of TASK_GAMMA_RESTART_CH7_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH7_EN_Pos = 0x7
	// Bit mask of TASK_GAMMA_RESTART_CH7_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH7_EN_Msk = 0x80
	// Bit TASK_GAMMA_RESTART_CH7_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESTART_CH7_EN = 0x80
	// Position of TASK_GAMMA_PAUSE_CH0_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN_Pos = 0x8
	// Bit mask of TASK_GAMMA_PAUSE_CH0_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN_Msk = 0x100
	// Bit TASK_GAMMA_PAUSE_CH0_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH0_EN = 0x100
	// Position of TASK_GAMMA_PAUSE_CH1_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN_Pos = 0x9
	// Bit mask of TASK_GAMMA_PAUSE_CH1_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN_Msk = 0x200
	// Bit TASK_GAMMA_PAUSE_CH1_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH1_EN = 0x200
	// Position of TASK_GAMMA_PAUSE_CH2_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN_Pos = 0xa
	// Bit mask of TASK_GAMMA_PAUSE_CH2_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN_Msk = 0x400
	// Bit TASK_GAMMA_PAUSE_CH2_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH2_EN = 0x400
	// Position of TASK_GAMMA_PAUSE_CH3_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN_Pos = 0xb
	// Bit mask of TASK_GAMMA_PAUSE_CH3_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN_Msk = 0x800
	// Bit TASK_GAMMA_PAUSE_CH3_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH3_EN = 0x800
	// Position of TASK_GAMMA_PAUSE_CH4_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN_Pos = 0xc
	// Bit mask of TASK_GAMMA_PAUSE_CH4_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN_Msk = 0x1000
	// Bit TASK_GAMMA_PAUSE_CH4_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH4_EN = 0x1000
	// Position of TASK_GAMMA_PAUSE_CH5_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN_Pos = 0xd
	// Bit mask of TASK_GAMMA_PAUSE_CH5_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN_Msk = 0x2000
	// Bit TASK_GAMMA_PAUSE_CH5_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH5_EN = 0x2000
	// Position of TASK_GAMMA_PAUSE_CH6_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH6_EN_Pos = 0xe
	// Bit mask of TASK_GAMMA_PAUSE_CH6_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH6_EN_Msk = 0x4000
	// Bit TASK_GAMMA_PAUSE_CH6_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH6_EN = 0x4000
	// Position of TASK_GAMMA_PAUSE_CH7_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH7_EN_Pos = 0xf
	// Bit mask of TASK_GAMMA_PAUSE_CH7_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH7_EN_Msk = 0x8000
	// Bit TASK_GAMMA_PAUSE_CH7_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_PAUSE_CH7_EN = 0x8000
	// Position of TASK_GAMMA_RESUME_CH0_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN_Pos = 0x10
	// Bit mask of TASK_GAMMA_RESUME_CH0_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN_Msk = 0x10000
	// Bit TASK_GAMMA_RESUME_CH0_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH0_EN = 0x10000
	// Position of TASK_GAMMA_RESUME_CH1_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN_Pos = 0x11
	// Bit mask of TASK_GAMMA_RESUME_CH1_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN_Msk = 0x20000
	// Bit TASK_GAMMA_RESUME_CH1_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH1_EN = 0x20000
	// Position of TASK_GAMMA_RESUME_CH2_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN_Pos = 0x12
	// Bit mask of TASK_GAMMA_RESUME_CH2_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN_Msk = 0x40000
	// Bit TASK_GAMMA_RESUME_CH2_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH2_EN = 0x40000
	// Position of TASK_GAMMA_RESUME_CH3_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN_Pos = 0x13
	// Bit mask of TASK_GAMMA_RESUME_CH3_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN_Msk = 0x80000
	// Bit TASK_GAMMA_RESUME_CH3_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH3_EN = 0x80000
	// Position of TASK_GAMMA_RESUME_CH4_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN_Pos = 0x14
	// Bit mask of TASK_GAMMA_RESUME_CH4_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN_Msk = 0x100000
	// Bit TASK_GAMMA_RESUME_CH4_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH4_EN = 0x100000
	// Position of TASK_GAMMA_RESUME_CH5_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN_Pos = 0x15
	// Bit mask of TASK_GAMMA_RESUME_CH5_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN_Msk = 0x200000
	// Bit TASK_GAMMA_RESUME_CH5_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH5_EN = 0x200000
	// Position of TASK_GAMMA_RESUME_CH6_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH6_EN_Pos = 0x16
	// Bit mask of TASK_GAMMA_RESUME_CH6_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH6_EN_Msk = 0x400000
	// Bit TASK_GAMMA_RESUME_CH6_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH6_EN = 0x400000
	// Position of TASK_GAMMA_RESUME_CH7_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH7_EN_Pos = 0x17
	// Bit mask of TASK_GAMMA_RESUME_CH7_EN field.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH7_EN_Msk = 0x800000
	// Bit TASK_GAMMA_RESUME_CH7_EN.
	LEDC_EVT_TASK_EN2_TASK_GAMMA_RESUME_CH7_EN = 0x800000

	// TIMER0_CMP: Ledc timer%s compare value register.
	// Position of TIMER_CMP field.
	LEDC_TIMER_CMP_TIMER_CMP_Pos = 0x0
	// Bit mask of TIMER_CMP field.
	LEDC_TIMER_CMP_TIMER_CMP_Msk = 0xfffff

	// TIMER0_CNT_CAP: Ledc timer%s captured count value register.
	// Position of TIMER_CNT_CAP field.
	LEDC_TIMER_CNT_CAP_TIMER_CNT_CAP_Pos = 0x0
	// Bit mask of TIMER_CNT_CAP field.
	LEDC_TIMER_CNT_CAP_TIMER_CNT_CAP_Msk = 0xfffff

	// CONF: LEDC global configuration register
	// Position of APB_CLK_SEL field.
	LEDC_CONF_APB_CLK_SEL_Pos = 0x0
	// Bit mask of APB_CLK_SEL field.
	LEDC_CONF_APB_CLK_SEL_Msk = 0x3
	// Position of GAMMA_RAM_CLK_EN_CH0 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH0_Pos = 0x2
	// Bit mask of GAMMA_RAM_CLK_EN_CH0 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH0_Msk = 0x4
	// Bit GAMMA_RAM_CLK_EN_CH0.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH0 = 0x4
	// Position of GAMMA_RAM_CLK_EN_CH1 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH1_Pos = 0x3
	// Bit mask of GAMMA_RAM_CLK_EN_CH1 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH1_Msk = 0x8
	// Bit GAMMA_RAM_CLK_EN_CH1.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH1 = 0x8
	// Position of GAMMA_RAM_CLK_EN_CH2 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH2_Pos = 0x4
	// Bit mask of GAMMA_RAM_CLK_EN_CH2 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH2_Msk = 0x10
	// Bit GAMMA_RAM_CLK_EN_CH2.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH2 = 0x10
	// Position of GAMMA_RAM_CLK_EN_CH3 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH3_Pos = 0x5
	// Bit mask of GAMMA_RAM_CLK_EN_CH3 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH3_Msk = 0x20
	// Bit GAMMA_RAM_CLK_EN_CH3.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH3 = 0x20
	// Position of GAMMA_RAM_CLK_EN_CH4 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH4_Pos = 0x6
	// Bit mask of GAMMA_RAM_CLK_EN_CH4 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH4_Msk = 0x40
	// Bit GAMMA_RAM_CLK_EN_CH4.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH4 = 0x40
	// Position of GAMMA_RAM_CLK_EN_CH5 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH5_Pos = 0x7
	// Bit mask of GAMMA_RAM_CLK_EN_CH5 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH5_Msk = 0x80
	// Bit GAMMA_RAM_CLK_EN_CH5.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH5 = 0x80
	// Position of GAMMA_RAM_CLK_EN_CH6 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH6_Pos = 0x8
	// Bit mask of GAMMA_RAM_CLK_EN_CH6 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH6_Msk = 0x100
	// Bit GAMMA_RAM_CLK_EN_CH6.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH6 = 0x100
	// Position of GAMMA_RAM_CLK_EN_CH7 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH7_Pos = 0x9
	// Bit mask of GAMMA_RAM_CLK_EN_CH7 field.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH7_Msk = 0x200
	// Bit GAMMA_RAM_CLK_EN_CH7.
	LEDC_CONF_GAMMA_RAM_CLK_EN_CH7 = 0x200
	// Position of CLK_EN field.
	LEDC_CONF_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	LEDC_CONF_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	LEDC_CONF_CLK_EN = 0x80000000

	// DATE: Version control register
	// Position of LEDC_DATE field.
	LEDC_DATE_LEDC_DATE_Pos = 0x0
	// Bit mask of LEDC_DATE field.
	LEDC_DATE_LEDC_DATE_Msk = 0xfffffff
)

// Constants for LP_INTR: Low-power Interrupt Controller
const (
	// SW_INT_RAW: need_des
	// Position of LP_SW_INT_RAW field.
	LPINTR_SW_INT_RAW_LP_SW_INT_RAW_Pos = 0x1f
	// Bit mask of LP_SW_INT_RAW field.
	LPINTR_SW_INT_RAW_LP_SW_INT_RAW_Msk = 0x80000000
	// Bit LP_SW_INT_RAW.
	LPINTR_SW_INT_RAW_LP_SW_INT_RAW = 0x80000000

	// SW_INT_ST: need_des
	// Position of LP_SW_INT_ST field.
	LPINTR_SW_INT_ST_LP_SW_INT_ST_Pos = 0x1f
	// Bit mask of LP_SW_INT_ST field.
	LPINTR_SW_INT_ST_LP_SW_INT_ST_Msk = 0x80000000
	// Bit LP_SW_INT_ST.
	LPINTR_SW_INT_ST_LP_SW_INT_ST = 0x80000000

	// SW_INT_ENA: need_des
	// Position of LP_SW_INT_ENA field.
	LPINTR_SW_INT_ENA_LP_SW_INT_ENA_Pos = 0x1f
	// Bit mask of LP_SW_INT_ENA field.
	LPINTR_SW_INT_ENA_LP_SW_INT_ENA_Msk = 0x80000000
	// Bit LP_SW_INT_ENA.
	LPINTR_SW_INT_ENA_LP_SW_INT_ENA = 0x80000000

	// SW_INT_CLR: need_des
	// Position of LP_SW_INT_CLR field.
	LPINTR_SW_INT_CLR_LP_SW_INT_CLR_Pos = 0x1f
	// Bit mask of LP_SW_INT_CLR field.
	LPINTR_SW_INT_CLR_LP_SW_INT_CLR_Msk = 0x80000000
	// Bit LP_SW_INT_CLR.
	LPINTR_SW_INT_CLR_LP_SW_INT_CLR = 0x80000000

	// STATUS: need_des
	// Position of LP_HUK_INTR_ST field.
	LPINTR_STATUS_LP_HUK_INTR_ST_Pos = 0xa
	// Bit mask of LP_HUK_INTR_ST field.
	LPINTR_STATUS_LP_HUK_INTR_ST_Msk = 0x400
	// Bit LP_HUK_INTR_ST.
	LPINTR_STATUS_LP_HUK_INTR_ST = 0x400
	// Position of SYSREG_INTR_ST field.
	LPINTR_STATUS_SYSREG_INTR_ST_Pos = 0xb
	// Bit mask of SYSREG_INTR_ST field.
	LPINTR_STATUS_SYSREG_INTR_ST_Msk = 0x800
	// Bit SYSREG_INTR_ST.
	LPINTR_STATUS_SYSREG_INTR_ST = 0x800
	// Position of LP_SW_INTR_ST field.
	LPINTR_STATUS_LP_SW_INTR_ST_Pos = 0xc
	// Bit mask of LP_SW_INTR_ST field.
	LPINTR_STATUS_LP_SW_INTR_ST_Msk = 0x1000
	// Bit LP_SW_INTR_ST.
	LPINTR_STATUS_LP_SW_INTR_ST = 0x1000
	// Position of LP_EFUSE_INTR_ST field.
	LPINTR_STATUS_LP_EFUSE_INTR_ST_Pos = 0xd
	// Bit mask of LP_EFUSE_INTR_ST field.
	LPINTR_STATUS_LP_EFUSE_INTR_ST_Msk = 0x2000
	// Bit LP_EFUSE_INTR_ST.
	LPINTR_STATUS_LP_EFUSE_INTR_ST = 0x2000
	// Position of LP_UART_INTR_ST field.
	LPINTR_STATUS_LP_UART_INTR_ST_Pos = 0xe
	// Bit mask of LP_UART_INTR_ST field.
	LPINTR_STATUS_LP_UART_INTR_ST_Msk = 0x4000
	// Bit LP_UART_INTR_ST.
	LPINTR_STATUS_LP_UART_INTR_ST = 0x4000
	// Position of LP_TSENS_INTR_ST field.
	LPINTR_STATUS_LP_TSENS_INTR_ST_Pos = 0xf
	// Bit mask of LP_TSENS_INTR_ST field.
	LPINTR_STATUS_LP_TSENS_INTR_ST_Msk = 0x8000
	// Bit LP_TSENS_INTR_ST.
	LPINTR_STATUS_LP_TSENS_INTR_ST = 0x8000
	// Position of LP_TOUCH_INTR_ST field.
	LPINTR_STATUS_LP_TOUCH_INTR_ST_Pos = 0x10
	// Bit mask of LP_TOUCH_INTR_ST field.
	LPINTR_STATUS_LP_TOUCH_INTR_ST_Msk = 0x10000
	// Bit LP_TOUCH_INTR_ST.
	LPINTR_STATUS_LP_TOUCH_INTR_ST = 0x10000
	// Position of LP_SPI_INTR_ST field.
	LPINTR_STATUS_LP_SPI_INTR_ST_Pos = 0x11
	// Bit mask of LP_SPI_INTR_ST field.
	LPINTR_STATUS_LP_SPI_INTR_ST_Msk = 0x20000
	// Bit LP_SPI_INTR_ST.
	LPINTR_STATUS_LP_SPI_INTR_ST = 0x20000
	// Position of LP_I2S_INTR_ST field.
	LPINTR_STATUS_LP_I2S_INTR_ST_Pos = 0x12
	// Bit mask of LP_I2S_INTR_ST field.
	LPINTR_STATUS_LP_I2S_INTR_ST_Msk = 0x40000
	// Bit LP_I2S_INTR_ST.
	LPINTR_STATUS_LP_I2S_INTR_ST = 0x40000
	// Position of LP_I2C_INTR_ST field.
	LPINTR_STATUS_LP_I2C_INTR_ST_Pos = 0x13
	// Bit mask of LP_I2C_INTR_ST field.
	LPINTR_STATUS_LP_I2C_INTR_ST_Msk = 0x80000
	// Bit LP_I2C_INTR_ST.
	LPINTR_STATUS_LP_I2C_INTR_ST = 0x80000
	// Position of LP_GPIO_INTR_ST field.
	LPINTR_STATUS_LP_GPIO_INTR_ST_Pos = 0x14
	// Bit mask of LP_GPIO_INTR_ST field.
	LPINTR_STATUS_LP_GPIO_INTR_ST_Msk = 0x100000
	// Bit LP_GPIO_INTR_ST.
	LPINTR_STATUS_LP_GPIO_INTR_ST = 0x100000
	// Position of LP_ADC_INTR_ST field.
	LPINTR_STATUS_LP_ADC_INTR_ST_Pos = 0x15
	// Bit mask of LP_ADC_INTR_ST field.
	LPINTR_STATUS_LP_ADC_INTR_ST_Msk = 0x200000
	// Bit LP_ADC_INTR_ST.
	LPINTR_STATUS_LP_ADC_INTR_ST = 0x200000
	// Position of ANAPERI_INTR_ST field.
	LPINTR_STATUS_ANAPERI_INTR_ST_Pos = 0x16
	// Bit mask of ANAPERI_INTR_ST field.
	LPINTR_STATUS_ANAPERI_INTR_ST_Msk = 0x400000
	// Bit ANAPERI_INTR_ST.
	LPINTR_STATUS_ANAPERI_INTR_ST = 0x400000
	// Position of PMU_REG_1_INTR_ST field.
	LPINTR_STATUS_PMU_REG_1_INTR_ST_Pos = 0x17
	// Bit mask of PMU_REG_1_INTR_ST field.
	LPINTR_STATUS_PMU_REG_1_INTR_ST_Msk = 0x800000
	// Bit PMU_REG_1_INTR_ST.
	LPINTR_STATUS_PMU_REG_1_INTR_ST = 0x800000
	// Position of PMU_REG_0_INTR_ST field.
	LPINTR_STATUS_PMU_REG_0_INTR_ST_Pos = 0x18
	// Bit mask of PMU_REG_0_INTR_ST field.
	LPINTR_STATUS_PMU_REG_0_INTR_ST_Msk = 0x1000000
	// Bit PMU_REG_0_INTR_ST.
	LPINTR_STATUS_PMU_REG_0_INTR_ST = 0x1000000
	// Position of MB_LP_INTR_ST field.
	LPINTR_STATUS_MB_LP_INTR_ST_Pos = 0x19
	// Bit mask of MB_LP_INTR_ST field.
	LPINTR_STATUS_MB_LP_INTR_ST_Msk = 0x2000000
	// Bit MB_LP_INTR_ST.
	LPINTR_STATUS_MB_LP_INTR_ST = 0x2000000
	// Position of MB_HP_INTR_ST field.
	LPINTR_STATUS_MB_HP_INTR_ST_Pos = 0x1a
	// Bit mask of MB_HP_INTR_ST field.
	LPINTR_STATUS_MB_HP_INTR_ST_Msk = 0x4000000
	// Bit MB_HP_INTR_ST.
	LPINTR_STATUS_MB_HP_INTR_ST = 0x4000000
	// Position of LP_TIMER_REG_1_INTR_ST field.
	LPINTR_STATUS_LP_TIMER_REG_1_INTR_ST_Pos = 0x1b
	// Bit mask of LP_TIMER_REG_1_INTR_ST field.
	LPINTR_STATUS_LP_TIMER_REG_1_INTR_ST_Msk = 0x8000000
	// Bit LP_TIMER_REG_1_INTR_ST.
	LPINTR_STATUS_LP_TIMER_REG_1_INTR_ST = 0x8000000
	// Position of LP_TIMER_REG_0_INTR_ST field.
	LPINTR_STATUS_LP_TIMER_REG_0_INTR_ST_Pos = 0x1c
	// Bit mask of LP_TIMER_REG_0_INTR_ST field.
	LPINTR_STATUS_LP_TIMER_REG_0_INTR_ST_Msk = 0x10000000
	// Bit LP_TIMER_REG_0_INTR_ST.
	LPINTR_STATUS_LP_TIMER_REG_0_INTR_ST = 0x10000000
	// Position of LP_WDT_INTR_ST field.
	LPINTR_STATUS_LP_WDT_INTR_ST_Pos = 0x1d
	// Bit mask of LP_WDT_INTR_ST field.
	LPINTR_STATUS_LP_WDT_INTR_ST_Msk = 0x20000000
	// Bit LP_WDT_INTR_ST.
	LPINTR_STATUS_LP_WDT_INTR_ST = 0x20000000
	// Position of LP_RTC_INTR_ST field.
	LPINTR_STATUS_LP_RTC_INTR_ST_Pos = 0x1e
	// Bit mask of LP_RTC_INTR_ST field.
	LPINTR_STATUS_LP_RTC_INTR_ST_Msk = 0x40000000
	// Bit LP_RTC_INTR_ST.
	LPINTR_STATUS_LP_RTC_INTR_ST = 0x40000000
	// Position of HP_INTR_ST field.
	LPINTR_STATUS_HP_INTR_ST_Pos = 0x1f
	// Bit mask of HP_INTR_ST field.
	LPINTR_STATUS_HP_INTR_ST_Msk = 0x80000000
	// Bit HP_INTR_ST.
	LPINTR_STATUS_HP_INTR_ST = 0x80000000

	// DATE: need_des
	// Position of CLK_EN field.
	LPINTR_DATE_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	LPINTR_DATE_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	LPINTR_DATE_CLK_EN = 0x80000000
)

// Constants for LP_PERI: LP_PERI Peripheral
const (
	// CLK_EN: need_des
	// Position of CK_EN_RNG field.
	LPPERI_CLK_EN_CK_EN_RNG_Pos = 0x10
	// Bit mask of CK_EN_RNG field.
	LPPERI_CLK_EN_CK_EN_RNG_Msk = 0x10000
	// Bit CK_EN_RNG.
	LPPERI_CLK_EN_CK_EN_RNG = 0x10000
	// Position of CK_EN_LP_TSENS field.
	LPPERI_CLK_EN_CK_EN_LP_TSENS_Pos = 0x11
	// Bit mask of CK_EN_LP_TSENS field.
	LPPERI_CLK_EN_CK_EN_LP_TSENS_Msk = 0x20000
	// Bit CK_EN_LP_TSENS.
	LPPERI_CLK_EN_CK_EN_LP_TSENS = 0x20000
	// Position of CK_EN_LP_PMS field.
	LPPERI_CLK_EN_CK_EN_LP_PMS_Pos = 0x12
	// Bit mask of CK_EN_LP_PMS field.
	LPPERI_CLK_EN_CK_EN_LP_PMS_Msk = 0x40000
	// Bit CK_EN_LP_PMS.
	LPPERI_CLK_EN_CK_EN_LP_PMS = 0x40000
	// Position of CK_EN_LP_EFUSE field.
	LPPERI_CLK_EN_CK_EN_LP_EFUSE_Pos = 0x13
	// Bit mask of CK_EN_LP_EFUSE field.
	LPPERI_CLK_EN_CK_EN_LP_EFUSE_Msk = 0x80000
	// Bit CK_EN_LP_EFUSE.
	LPPERI_CLK_EN_CK_EN_LP_EFUSE = 0x80000
	// Position of CK_EN_LP_IOMUX field.
	LPPERI_CLK_EN_CK_EN_LP_IOMUX_Pos = 0x14
	// Bit mask of CK_EN_LP_IOMUX field.
	LPPERI_CLK_EN_CK_EN_LP_IOMUX_Msk = 0x100000
	// Bit CK_EN_LP_IOMUX.
	LPPERI_CLK_EN_CK_EN_LP_IOMUX = 0x100000
	// Position of CK_EN_LP_TOUCH field.
	LPPERI_CLK_EN_CK_EN_LP_TOUCH_Pos = 0x15
	// Bit mask of CK_EN_LP_TOUCH field.
	LPPERI_CLK_EN_CK_EN_LP_TOUCH_Msk = 0x200000
	// Bit CK_EN_LP_TOUCH.
	LPPERI_CLK_EN_CK_EN_LP_TOUCH = 0x200000
	// Position of CK_EN_LP_SPI field.
	LPPERI_CLK_EN_CK_EN_LP_SPI_Pos = 0x16
	// Bit mask of CK_EN_LP_SPI field.
	LPPERI_CLK_EN_CK_EN_LP_SPI_Msk = 0x400000
	// Bit CK_EN_LP_SPI.
	LPPERI_CLK_EN_CK_EN_LP_SPI = 0x400000
	// Position of CK_EN_LP_ADC field.
	LPPERI_CLK_EN_CK_EN_LP_ADC_Pos = 0x17
	// Bit mask of CK_EN_LP_ADC field.
	LPPERI_CLK_EN_CK_EN_LP_ADC_Msk = 0x800000
	// Bit CK_EN_LP_ADC.
	LPPERI_CLK_EN_CK_EN_LP_ADC = 0x800000
	// Position of CK_EN_LP_I2S_TX field.
	LPPERI_CLK_EN_CK_EN_LP_I2S_TX_Pos = 0x18
	// Bit mask of CK_EN_LP_I2S_TX field.
	LPPERI_CLK_EN_CK_EN_LP_I2S_TX_Msk = 0x1000000
	// Bit CK_EN_LP_I2S_TX.
	LPPERI_CLK_EN_CK_EN_LP_I2S_TX = 0x1000000
	// Position of CK_EN_LP_I2S_RX field.
	LPPERI_CLK_EN_CK_EN_LP_I2S_RX_Pos = 0x19
	// Bit mask of CK_EN_LP_I2S_RX field.
	LPPERI_CLK_EN_CK_EN_LP_I2S_RX_Msk = 0x2000000
	// Bit CK_EN_LP_I2S_RX.
	LPPERI_CLK_EN_CK_EN_LP_I2S_RX = 0x2000000
	// Position of CK_EN_LP_I2S field.
	LPPERI_CLK_EN_CK_EN_LP_I2S_Pos = 0x1a
	// Bit mask of CK_EN_LP_I2S field.
	LPPERI_CLK_EN_CK_EN_LP_I2S_Msk = 0x4000000
	// Bit CK_EN_LP_I2S.
	LPPERI_CLK_EN_CK_EN_LP_I2S = 0x4000000
	// Position of CK_EN_LP_I2CMST field.
	LPPERI_CLK_EN_CK_EN_LP_I2CMST_Pos = 0x1b
	// Bit mask of CK_EN_LP_I2CMST field.
	LPPERI_CLK_EN_CK_EN_LP_I2CMST_Msk = 0x8000000
	// Bit CK_EN_LP_I2CMST.
	LPPERI_CLK_EN_CK_EN_LP_I2CMST = 0x8000000
	// Position of CK_EN_LP_I2C field.
	LPPERI_CLK_EN_CK_EN_LP_I2C_Pos = 0x1c
	// Bit mask of CK_EN_LP_I2C field.
	LPPERI_CLK_EN_CK_EN_LP_I2C_Msk = 0x10000000
	// Bit CK_EN_LP_I2C.
	LPPERI_CLK_EN_CK_EN_LP_I2C = 0x10000000
	// Position of CK_EN_LP_UART field.
	LPPERI_CLK_EN_CK_EN_LP_UART_Pos = 0x1d
	// Bit mask of CK_EN_LP_UART field.
	LPPERI_CLK_EN_CK_EN_LP_UART_Msk = 0x20000000
	// Bit CK_EN_LP_UART.
	LPPERI_CLK_EN_CK_EN_LP_UART = 0x20000000
	// Position of CK_EN_LP_INTR field.
	LPPERI_CLK_EN_CK_EN_LP_INTR_Pos = 0x1e
	// Bit mask of CK_EN_LP_INTR field.
	LPPERI_CLK_EN_CK_EN_LP_INTR_Msk = 0x40000000
	// Bit CK_EN_LP_INTR.
	LPPERI_CLK_EN_CK_EN_LP_INTR = 0x40000000
	// Position of CK_EN_LP_CORE field.
	LPPERI_CLK_EN_CK_EN_LP_CORE_Pos = 0x1f
	// Bit mask of CK_EN_LP_CORE field.
	LPPERI_CLK_EN_CK_EN_LP_CORE_Msk = 0x80000000
	// Bit CK_EN_LP_CORE.
	LPPERI_CLK_EN_CK_EN_LP_CORE = 0x80000000

	// CORE_CLK_SEL: need_des
	// Position of LP_I2S_TX_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_I2S_TX_CLK_SEL_Pos = 0x18
	// Bit mask of LP_I2S_TX_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_I2S_TX_CLK_SEL_Msk = 0x3000000
	// Position of LP_I2S_RX_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_I2S_RX_CLK_SEL_Pos = 0x1a
	// Bit mask of LP_I2S_RX_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_I2S_RX_CLK_SEL_Msk = 0xc000000
	// Position of LP_I2C_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_I2C_CLK_SEL_Pos = 0x1c
	// Bit mask of LP_I2C_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_I2C_CLK_SEL_Msk = 0x30000000
	// Position of LP_UART_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_UART_CLK_SEL_Pos = 0x1e
	// Bit mask of LP_UART_CLK_SEL field.
	LPPERI_CORE_CLK_SEL_LP_UART_CLK_SEL_Msk = 0xc0000000

	// RESET_EN: need_des
	// Position of RST_EN_LP_TSENS field.
	LPPERI_RESET_EN_RST_EN_LP_TSENS_Pos = 0x12
	// Bit mask of RST_EN_LP_TSENS field.
	LPPERI_RESET_EN_RST_EN_LP_TSENS_Msk = 0x40000
	// Bit RST_EN_LP_TSENS.
	LPPERI_RESET_EN_RST_EN_LP_TSENS = 0x40000
	// Position of RST_EN_LP_PMS field.
	LPPERI_RESET_EN_RST_EN_LP_PMS_Pos = 0x13
	// Bit mask of RST_EN_LP_PMS field.
	LPPERI_RESET_EN_RST_EN_LP_PMS_Msk = 0x80000
	// Bit RST_EN_LP_PMS.
	LPPERI_RESET_EN_RST_EN_LP_PMS = 0x80000
	// Position of RST_EN_LP_EFUSE field.
	LPPERI_RESET_EN_RST_EN_LP_EFUSE_Pos = 0x14
	// Bit mask of RST_EN_LP_EFUSE field.
	LPPERI_RESET_EN_RST_EN_LP_EFUSE_Msk = 0x100000
	// Bit RST_EN_LP_EFUSE.
	LPPERI_RESET_EN_RST_EN_LP_EFUSE = 0x100000
	// Position of RST_EN_LP_IOMUX field.
	LPPERI_RESET_EN_RST_EN_LP_IOMUX_Pos = 0x15
	// Bit mask of RST_EN_LP_IOMUX field.
	LPPERI_RESET_EN_RST_EN_LP_IOMUX_Msk = 0x200000
	// Bit RST_EN_LP_IOMUX.
	LPPERI_RESET_EN_RST_EN_LP_IOMUX = 0x200000
	// Position of RST_EN_LP_TOUCH field.
	LPPERI_RESET_EN_RST_EN_LP_TOUCH_Pos = 0x16
	// Bit mask of RST_EN_LP_TOUCH field.
	LPPERI_RESET_EN_RST_EN_LP_TOUCH_Msk = 0x400000
	// Bit RST_EN_LP_TOUCH.
	LPPERI_RESET_EN_RST_EN_LP_TOUCH = 0x400000
	// Position of RST_EN_LP_SPI field.
	LPPERI_RESET_EN_RST_EN_LP_SPI_Pos = 0x17
	// Bit mask of RST_EN_LP_SPI field.
	LPPERI_RESET_EN_RST_EN_LP_SPI_Msk = 0x800000
	// Bit RST_EN_LP_SPI.
	LPPERI_RESET_EN_RST_EN_LP_SPI = 0x800000
	// Position of RST_EN_LP_ADC field.
	LPPERI_RESET_EN_RST_EN_LP_ADC_Pos = 0x18
	// Bit mask of RST_EN_LP_ADC field.
	LPPERI_RESET_EN_RST_EN_LP_ADC_Msk = 0x1000000
	// Bit RST_EN_LP_ADC.
	LPPERI_RESET_EN_RST_EN_LP_ADC = 0x1000000
	// Position of RST_EN_LP_I2S field.
	LPPERI_RESET_EN_RST_EN_LP_I2S_Pos = 0x19
	// Bit mask of RST_EN_LP_I2S field.
	LPPERI_RESET_EN_RST_EN_LP_I2S_Msk = 0x2000000
	// Bit RST_EN_LP_I2S.
	LPPERI_RESET_EN_RST_EN_LP_I2S = 0x2000000
	// Position of RST_EN_LP_I2CMST field.
	LPPERI_RESET_EN_RST_EN_LP_I2CMST_Pos = 0x1a
	// Bit mask of RST_EN_LP_I2CMST field.
	LPPERI_RESET_EN_RST_EN_LP_I2CMST_Msk = 0x4000000
	// Bit RST_EN_LP_I2CMST.
	LPPERI_RESET_EN_RST_EN_LP_I2CMST = 0x4000000
	// Position of RST_EN_LP_I2C field.
	LPPERI_RESET_EN_RST_EN_LP_I2C_Pos = 0x1b
	// Bit mask of RST_EN_LP_I2C field.
	LPPERI_RESET_EN_RST_EN_LP_I2C_Msk = 0x8000000
	// Bit RST_EN_LP_I2C.
	LPPERI_RESET_EN_RST_EN_LP_I2C = 0x8000000
	// Position of RST_EN_LP_UART field.
	LPPERI_RESET_EN_RST_EN_LP_UART_Pos = 0x1c
	// Bit mask of RST_EN_LP_UART field.
	LPPERI_RESET_EN_RST_EN_LP_UART_Msk = 0x10000000
	// Bit RST_EN_LP_UART.
	LPPERI_RESET_EN_RST_EN_LP_UART = 0x10000000
	// Position of RST_EN_LP_INTR field.
	LPPERI_RESET_EN_RST_EN_LP_INTR_Pos = 0x1d
	// Bit mask of RST_EN_LP_INTR field.
	LPPERI_RESET_EN_RST_EN_LP_INTR_Msk = 0x20000000
	// Bit RST_EN_LP_INTR.
	LPPERI_RESET_EN_RST_EN_LP_INTR = 0x20000000
	// Position of RST_EN_LP_ROM field.
	LPPERI_RESET_EN_RST_EN_LP_ROM_Pos = 0x1e
	// Bit mask of RST_EN_LP_ROM field.
	LPPERI_RESET_EN_RST_EN_LP_ROM_Msk = 0x40000000
	// Bit RST_EN_LP_ROM.
	LPPERI_RESET_EN_RST_EN_LP_ROM = 0x40000000
	// Position of RST_EN_LP_CORE field.
	LPPERI_RESET_EN_RST_EN_LP_CORE_Pos = 0x1f
	// Bit mask of RST_EN_LP_CORE field.
	LPPERI_RESET_EN_RST_EN_LP_CORE_Msk = 0x80000000
	// Bit RST_EN_LP_CORE.
	LPPERI_RESET_EN_RST_EN_LP_CORE = 0x80000000

	// CPU: need_des
	// Position of LPCORE_DBGM_UNAVAILABLE field.
	LPPERI_CPU_LPCORE_DBGM_UNAVAILABLE_Pos = 0x1f
	// Bit mask of LPCORE_DBGM_UNAVAILABLE field.
	LPPERI_CPU_LPCORE_DBGM_UNAVAILABLE_Msk = 0x80000000
	// Bit LPCORE_DBGM_UNAVAILABLE.
	LPPERI_CPU_LPCORE_DBGM_UNAVAILABLE = 0x80000000

	// MEM_CTRL: need_des
	// Position of LP_UART_WAKEUP_FLAG_CLR field.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_FLAG_CLR_Pos = 0x0
	// Bit mask of LP_UART_WAKEUP_FLAG_CLR field.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_FLAG_CLR_Msk = 0x1
	// Bit LP_UART_WAKEUP_FLAG_CLR.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_FLAG_CLR = 0x1
	// Position of LP_UART_WAKEUP_FLAG field.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_FLAG_Pos = 0x1
	// Bit mask of LP_UART_WAKEUP_FLAG field.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_FLAG_Msk = 0x2
	// Bit LP_UART_WAKEUP_FLAG.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_FLAG = 0x2
	// Position of LP_UART_WAKEUP_EN field.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_EN_Pos = 0x1d
	// Bit mask of LP_UART_WAKEUP_EN field.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_EN_Msk = 0x20000000
	// Bit LP_UART_WAKEUP_EN.
	LPPERI_MEM_CTRL_LP_UART_WAKEUP_EN = 0x20000000
	// Position of LP_UART_MEM_FORCE_PD field.
	LPPERI_MEM_CTRL_LP_UART_MEM_FORCE_PD_Pos = 0x1e
	// Bit mask of LP_UART_MEM_FORCE_PD field.
	LPPERI_MEM_CTRL_LP_UART_MEM_FORCE_PD_Msk = 0x40000000
	// Bit LP_UART_MEM_FORCE_PD.
	LPPERI_MEM_CTRL_LP_UART_MEM_FORCE_PD = 0x40000000
	// Position of LP_UART_MEM_FORCE_PU field.
	LPPERI_MEM_CTRL_LP_UART_MEM_FORCE_PU_Pos = 0x1f
	// Bit mask of LP_UART_MEM_FORCE_PU field.
	LPPERI_MEM_CTRL_LP_UART_MEM_FORCE_PU_Msk = 0x80000000
	// Bit LP_UART_MEM_FORCE_PU.
	LPPERI_MEM_CTRL_LP_UART_MEM_FORCE_PU = 0x80000000

	// ADC_CTRL: need_des
	// Position of SAR2_CLK_FORCE_ON field.
	LPPERI_ADC_CTRL_SAR2_CLK_FORCE_ON_Pos = 0x6
	// Bit mask of SAR2_CLK_FORCE_ON field.
	LPPERI_ADC_CTRL_SAR2_CLK_FORCE_ON_Msk = 0x40
	// Bit SAR2_CLK_FORCE_ON.
	LPPERI_ADC_CTRL_SAR2_CLK_FORCE_ON = 0x40
	// Position of SAR1_CLK_FORCE_ON field.
	LPPERI_ADC_CTRL_SAR1_CLK_FORCE_ON_Pos = 0x7
	// Bit mask of SAR1_CLK_FORCE_ON field.
	LPPERI_ADC_CTRL_SAR1_CLK_FORCE_ON_Msk = 0x80
	// Bit SAR1_CLK_FORCE_ON.
	LPPERI_ADC_CTRL_SAR1_CLK_FORCE_ON = 0x80
	// Position of LPADC_FUNC_DIV_NUM field.
	LPPERI_ADC_CTRL_LPADC_FUNC_DIV_NUM_Pos = 0x8
	// Bit mask of LPADC_FUNC_DIV_NUM field.
	LPPERI_ADC_CTRL_LPADC_FUNC_DIV_NUM_Msk = 0xff00
	// Position of LPADC_SAR2_DIV_NUM field.
	LPPERI_ADC_CTRL_LPADC_SAR2_DIV_NUM_Pos = 0x10
	// Bit mask of LPADC_SAR2_DIV_NUM field.
	LPPERI_ADC_CTRL_LPADC_SAR2_DIV_NUM_Msk = 0xff0000
	// Position of LPADC_SAR1_DIV_NUM field.
	LPPERI_ADC_CTRL_LPADC_SAR1_DIV_NUM_Pos = 0x18
	// Bit mask of LPADC_SAR1_DIV_NUM field.
	LPPERI_ADC_CTRL_LPADC_SAR1_DIV_NUM_Msk = 0xff000000

	// LP_I2S_RXCLK_DIV_NUM: need_des
	// Position of LP_I2S_RX_CLKM_DIV_NUM field.
	LPPERI_LP_I2S_RXCLK_DIV_NUM_LP_I2S_RX_CLKM_DIV_NUM_Pos = 0x18
	// Bit mask of LP_I2S_RX_CLKM_DIV_NUM field.
	LPPERI_LP_I2S_RXCLK_DIV_NUM_LP_I2S_RX_CLKM_DIV_NUM_Msk = 0xff000000

	// LP_I2S_RXCLK_DIV_XYZ: need_des
	// Position of LP_I2S_RX_CLKM_DIV_YN1 field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_YN1_Pos = 0x4
	// Bit mask of LP_I2S_RX_CLKM_DIV_YN1 field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_YN1_Msk = 0x10
	// Bit LP_I2S_RX_CLKM_DIV_YN1.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_YN1 = 0x10
	// Position of LP_I2S_RX_CLKM_DIV_Z field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Z_Pos = 0x5
	// Bit mask of LP_I2S_RX_CLKM_DIV_Z field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Z_Msk = 0x3fe0
	// Position of LP_I2S_RX_CLKM_DIV_Y field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Y_Pos = 0xe
	// Bit mask of LP_I2S_RX_CLKM_DIV_Y field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_Y_Msk = 0x7fc000
	// Position of LP_I2S_RX_CLKM_DIV_X field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_X_Pos = 0x17
	// Bit mask of LP_I2S_RX_CLKM_DIV_X field.
	LPPERI_LP_I2S_RXCLK_DIV_XYZ_LP_I2S_RX_CLKM_DIV_X_Msk = 0xff800000

	// LP_I2S_TXCLK_DIV_NUM: need_des
	// Position of LP_I2S_TX_CLKM_DIV_NUM field.
	LPPERI_LP_I2S_TXCLK_DIV_NUM_LP_I2S_TX_CLKM_DIV_NUM_Pos = 0x18
	// Bit mask of LP_I2S_TX_CLKM_DIV_NUM field.
	LPPERI_LP_I2S_TXCLK_DIV_NUM_LP_I2S_TX_CLKM_DIV_NUM_Msk = 0xff000000

	// LP_I2S_TXCLK_DIV_XYZ: need_des
	// Position of LP_I2S_TX_CLKM_DIV_YN1 field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_YN1_Pos = 0x4
	// Bit mask of LP_I2S_TX_CLKM_DIV_YN1 field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_YN1_Msk = 0x10
	// Bit LP_I2S_TX_CLKM_DIV_YN1.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_YN1 = 0x10
	// Position of LP_I2S_TX_CLKM_DIV_Z field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Z_Pos = 0x5
	// Bit mask of LP_I2S_TX_CLKM_DIV_Z field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Z_Msk = 0x3fe0
	// Position of LP_I2S_TX_CLKM_DIV_Y field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Y_Pos = 0xe
	// Bit mask of LP_I2S_TX_CLKM_DIV_Y field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_Y_Msk = 0x7fc000
	// Position of LP_I2S_TX_CLKM_DIV_X field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_X_Pos = 0x17
	// Bit mask of LP_I2S_TX_CLKM_DIV_X field.
	LPPERI_LP_I2S_TXCLK_DIV_XYZ_LP_I2S_TX_CLKM_DIV_X_Msk = 0xff800000

	// DATE: need_des
	// Position of CLK_EN field.
	LPPERI_DATE_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	LPPERI_DATE_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	LPPERI_DATE_CLK_EN = 0x80000000
)

// Constants for LP_SYS: LP_SYS Peripheral
const (
	// LP_SYS_VER_DATE: need_des
	// Position of VER_DATE field.
	LPSYSREG_LP_SYS_VER_DATE_VER_DATE_Pos = 0x0
	// Bit mask of VER_DATE field.
	LPSYSREG_LP_SYS_VER_DATE_VER_DATE_Msk = 0xffffffff

	// CLK_SEL_CTRL: need_des
	// Position of ENA_SW_SEL_SYS_CLK field.
	LPSYSREG_CLK_SEL_CTRL_ENA_SW_SEL_SYS_CLK_Pos = 0x10
	// Bit mask of ENA_SW_SEL_SYS_CLK field.
	LPSYSREG_CLK_SEL_CTRL_ENA_SW_SEL_SYS_CLK_Msk = 0x10000
	// Bit ENA_SW_SEL_SYS_CLK.
	LPSYSREG_CLK_SEL_CTRL_ENA_SW_SEL_SYS_CLK = 0x10000
	// Position of SW_SYS_CLK_SRC_SEL field.
	LPSYSREG_CLK_SEL_CTRL_SW_SYS_CLK_SRC_SEL_Pos = 0x11
	// Bit mask of SW_SYS_CLK_SRC_SEL field.
	LPSYSREG_CLK_SEL_CTRL_SW_SYS_CLK_SRC_SEL_Msk = 0x20000
	// Bit SW_SYS_CLK_SRC_SEL.
	LPSYSREG_CLK_SEL_CTRL_SW_SYS_CLK_SRC_SEL = 0x20000

	// SYS_CTRL: need_des
	// Position of LP_CORE_DISABLE field.
	LPSYSREG_SYS_CTRL_LP_CORE_DISABLE_Pos = 0x0
	// Bit mask of LP_CORE_DISABLE field.
	LPSYSREG_SYS_CTRL_LP_CORE_DISABLE_Msk = 0x1
	// Bit LP_CORE_DISABLE.
	LPSYSREG_SYS_CTRL_LP_CORE_DISABLE = 0x1
	// Position of SYS_SW_RST field.
	LPSYSREG_SYS_CTRL_SYS_SW_RST_Pos = 0x1
	// Bit mask of SYS_SW_RST field.
	LPSYSREG_SYS_CTRL_SYS_SW_RST_Msk = 0x2
	// Bit SYS_SW_RST.
	LPSYSREG_SYS_CTRL_SYS_SW_RST = 0x2
	// Position of FORCE_DOWNLOAD_BOOT field.
	LPSYSREG_SYS_CTRL_FORCE_DOWNLOAD_BOOT_Pos = 0x2
	// Bit mask of FORCE_DOWNLOAD_BOOT field.
	LPSYSREG_SYS_CTRL_FORCE_DOWNLOAD_BOOT_Msk = 0x4
	// Bit FORCE_DOWNLOAD_BOOT.
	LPSYSREG_SYS_CTRL_FORCE_DOWNLOAD_BOOT = 0x4
	// Position of DIG_FIB field.
	LPSYSREG_SYS_CTRL_DIG_FIB_Pos = 0x3
	// Bit mask of DIG_FIB field.
	LPSYSREG_SYS_CTRL_DIG_FIB_Msk = 0x7f8
	// Position of IO_MUX_RESET_DISABLE field.
	LPSYSREG_SYS_CTRL_IO_MUX_RESET_DISABLE_Pos = 0xb
	// Bit mask of IO_MUX_RESET_DISABLE field.
	LPSYSREG_SYS_CTRL_IO_MUX_RESET_DISABLE_Msk = 0x800
	// Bit IO_MUX_RESET_DISABLE.
	LPSYSREG_SYS_CTRL_IO_MUX_RESET_DISABLE = 0x800
	// Position of ANA_FIB field.
	LPSYSREG_SYS_CTRL_ANA_FIB_Pos = 0xe
	// Bit mask of ANA_FIB field.
	LPSYSREG_SYS_CTRL_ANA_FIB_Msk = 0x1fc000
	// Position of LP_FIB_SEL field.
	LPSYSREG_SYS_CTRL_LP_FIB_SEL_Pos = 0x15
	// Bit mask of LP_FIB_SEL field.
	LPSYSREG_SYS_CTRL_LP_FIB_SEL_Msk = 0x1fe00000
	// Position of LP_CORE_ETM_WAKEUP_FLAG_CLR field.
	LPSYSREG_SYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_CLR_Pos = 0x1d
	// Bit mask of LP_CORE_ETM_WAKEUP_FLAG_CLR field.
	LPSYSREG_SYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_CLR_Msk = 0x20000000
	// Bit LP_CORE_ETM_WAKEUP_FLAG_CLR.
	LPSYSREG_SYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_CLR = 0x20000000
	// Position of LP_CORE_ETM_WAKEUP_FLAG field.
	LPSYSREG_SYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_Pos = 0x1e
	// Bit mask of LP_CORE_ETM_WAKEUP_FLAG field.
	LPSYSREG_SYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG_Msk = 0x40000000
	// Bit LP_CORE_ETM_WAKEUP_FLAG.
	LPSYSREG_SYS_CTRL_LP_CORE_ETM_WAKEUP_FLAG = 0x40000000
	// Position of SYSTIMER_STALL_SEL field.
	LPSYSREG_SYS_CTRL_SYSTIMER_STALL_SEL_Pos = 0x1f
	// Bit mask of SYSTIMER_STALL_SEL field.
	LPSYSREG_SYS_CTRL_SYSTIMER_STALL_SEL_Msk = 0x80000000
	// Bit SYSTIMER_STALL_SEL.
	LPSYSREG_SYS_CTRL_SYSTIMER_STALL_SEL = 0x80000000

	// LP_CLK_CTRL: need_des
	// Position of CLK_EN field.
	LPSYSREG_LP_CLK_CTRL_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	LPSYSREG_LP_CLK_CTRL_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	LPSYSREG_LP_CLK_CTRL_CLK_EN = 0x1
	// Position of LP_FOSC_HP_CKEN field.
	LPSYSREG_LP_CLK_CTRL_LP_FOSC_HP_CKEN_Pos = 0xe
	// Bit mask of LP_FOSC_HP_CKEN field.
	LPSYSREG_LP_CLK_CTRL_LP_FOSC_HP_CKEN_Msk = 0x4000
	// Bit LP_FOSC_HP_CKEN.
	LPSYSREG_LP_CLK_CTRL_LP_FOSC_HP_CKEN = 0x4000

	// LP_RST_CTRL: need_des
	// Position of ANA_RST_BYPASS field.
	LPSYSREG_LP_RST_CTRL_ANA_RST_BYPASS_Pos = 0x0
	// Bit mask of ANA_RST_BYPASS field.
	LPSYSREG_LP_RST_CTRL_ANA_RST_BYPASS_Msk = 0x1
	// Bit ANA_RST_BYPASS.
	LPSYSREG_LP_RST_CTRL_ANA_RST_BYPASS = 0x1
	// Position of SYS_RST_BYPASS field.
	LPSYSREG_LP_RST_CTRL_SYS_RST_BYPASS_Pos = 0x1
	// Bit mask of SYS_RST_BYPASS field.
	LPSYSREG_LP_RST_CTRL_SYS_RST_BYPASS_Msk = 0x2
	// Bit SYS_RST_BYPASS.
	LPSYSREG_LP_RST_CTRL_SYS_RST_BYPASS = 0x2
	// Position of EFUSE_FORCE_NORST field.
	LPSYSREG_LP_RST_CTRL_EFUSE_FORCE_NORST_Pos = 0x2
	// Bit mask of EFUSE_FORCE_NORST field.
	LPSYSREG_LP_RST_CTRL_EFUSE_FORCE_NORST_Msk = 0x4
	// Bit EFUSE_FORCE_NORST.
	LPSYSREG_LP_RST_CTRL_EFUSE_FORCE_NORST = 0x4

	// LP_CORE_BOOT_ADDR: need_des
	// Position of LP_CPU_BOOT_ADDR field.
	LPSYSREG_LP_CORE_BOOT_ADDR_LP_CPU_BOOT_ADDR_Pos = 0x0
	// Bit mask of LP_CPU_BOOT_ADDR field.
	LPSYSREG_LP_CORE_BOOT_ADDR_LP_CPU_BOOT_ADDR_Msk = 0xffffffff

	// EXT_WAKEUP1: need_des
	// Position of SEL field.
	LPSYSREG_EXT_WAKEUP1_SEL_Pos = 0x0
	// Bit mask of SEL field.
	LPSYSREG_EXT_WAKEUP1_SEL_Msk = 0xffff
	// Position of STATUS_CLR field.
	LPSYSREG_EXT_WAKEUP1_STATUS_CLR_Pos = 0x10
	// Bit mask of STATUS_CLR field.
	LPSYSREG_EXT_WAKEUP1_STATUS_CLR_Msk = 0x10000
	// Bit STATUS_CLR.
	LPSYSREG_EXT_WAKEUP1_STATUS_CLR = 0x10000

	// EXT_WAKEUP1_STATUS: need_des
	// Position of EXT_WAKEUP1_STATUS field.
	LPSYSREG_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Pos = 0x0
	// Bit mask of EXT_WAKEUP1_STATUS field.
	LPSYSREG_EXT_WAKEUP1_STATUS_EXT_WAKEUP1_STATUS_Msk = 0xffff

	// LP_TCM_PWR_CTRL: need_des
	// Position of LP_TCM_ROM_CLK_FORCE_ON field.
	LPSYSREG_LP_TCM_PWR_CTRL_LP_TCM_ROM_CLK_FORCE_ON_Pos = 0x5
	// Bit mask of LP_TCM_ROM_CLK_FORCE_ON field.
	LPSYSREG_LP_TCM_PWR_CTRL_LP_TCM_ROM_CLK_FORCE_ON_Msk = 0x20
	// Bit LP_TCM_ROM_CLK_FORCE_ON.
	LPSYSREG_LP_TCM_PWR_CTRL_LP_TCM_ROM_CLK_FORCE_ON = 0x20
	// Position of LP_TCM_RAM_CLK_FORCE_ON field.
	LPSYSREG_LP_TCM_PWR_CTRL_LP_TCM_RAM_CLK_FORCE_ON_Pos = 0x7
	// Bit mask of LP_TCM_RAM_CLK_FORCE_ON field.
	LPSYSREG_LP_TCM_PWR_CTRL_LP_TCM_RAM_CLK_FORCE_ON_Msk = 0x80
	// Bit LP_TCM_RAM_CLK_FORCE_ON.
	LPSYSREG_LP_TCM_PWR_CTRL_LP_TCM_RAM_CLK_FORCE_ON = 0x80

	// BOOT_ADDR_HP_LP: need_des
	// Position of BOOT_ADDR_HP_LP field.
	LPSYSREG_BOOT_ADDR_HP_LP_BOOT_ADDR_HP_LP_Pos = 0x0
	// Bit mask of BOOT_ADDR_HP_LP field.
	LPSYSREG_BOOT_ADDR_HP_LP_BOOT_ADDR_HP_LP_Msk = 0xffffffff

	// LP_STORE0: need_des
	// Position of LP_SCRATCH0 field.
	LPSYSREG_LP_STORE0_LP_SCRATCH0_Pos = 0x0
	// Bit mask of LP_SCRATCH0 field.
	LPSYSREG_LP_STORE0_LP_SCRATCH0_Msk = 0xffffffff

	// LP_STORE1: need_des
	// Position of LP_SCRATCH1 field.
	LPSYSREG_LP_STORE1_LP_SCRATCH1_Pos = 0x0
	// Bit mask of LP_SCRATCH1 field.
	LPSYSREG_LP_STORE1_LP_SCRATCH1_Msk = 0xffffffff

	// LP_STORE2: need_des
	// Position of LP_SCRATCH2 field.
	LPSYSREG_LP_STORE2_LP_SCRATCH2_Pos = 0x0
	// Bit mask of LP_SCRATCH2 field.
	LPSYSREG_LP_STORE2_LP_SCRATCH2_Msk = 0xffffffff

	// LP_STORE3: need_des
	// Position of LP_SCRATCH3 field.
	LPSYSREG_LP_STORE3_LP_SCRATCH3_Pos = 0x0
	// Bit mask of LP_SCRATCH3 field.
	LPSYSREG_LP_STORE3_LP_SCRATCH3_Msk = 0xffffffff

	// LP_STORE4: need_des
	// Position of LP_SCRATCH4 field.
	LPSYSREG_LP_STORE4_LP_SCRATCH4_Pos = 0x0
	// Bit mask of LP_SCRATCH4 field.
	LPSYSREG_LP_STORE4_LP_SCRATCH4_Msk = 0xffffffff

	// LP_STORE5: need_des
	// Position of LP_SCRATCH5 field.
	LPSYSREG_LP_STORE5_LP_SCRATCH5_Pos = 0x0
	// Bit mask of LP_SCRATCH5 field.
	LPSYSREG_LP_STORE5_LP_SCRATCH5_Msk = 0xffffffff

	// LP_STORE6: need_des
	// Position of LP_SCRATCH6 field.
	LPSYSREG_LP_STORE6_LP_SCRATCH6_Pos = 0x0
	// Bit mask of LP_SCRATCH6 field.
	LPSYSREG_LP_STORE6_LP_SCRATCH6_Msk = 0xffffffff

	// LP_STORE7: need_des
	// Position of LP_SCRATCH7 field.
	LPSYSREG_LP_STORE7_LP_SCRATCH7_Pos = 0x0
	// Bit mask of LP_SCRATCH7 field.
	LPSYSREG_LP_STORE7_LP_SCRATCH7_Msk = 0xffffffff

	// LP_STORE8: need_des
	// Position of LP_SCRATCH8 field.
	LPSYSREG_LP_STORE8_LP_SCRATCH8_Pos = 0x0
	// Bit mask of LP_SCRATCH8 field.
	LPSYSREG_LP_STORE8_LP_SCRATCH8_Msk = 0xffffffff

	// LP_STORE9: need_des
	// Position of LP_SCRATCH9 field.
	LPSYSREG_LP_STORE9_LP_SCRATCH9_Pos = 0x0
	// Bit mask of LP_SCRATCH9 field.
	LPSYSREG_LP_STORE9_LP_SCRATCH9_Msk = 0xffffffff

	// LP_STORE10: need_des
	// Position of LP_SCRATCH10 field.
	LPSYSREG_LP_STORE10_LP_SCRATCH10_Pos = 0x0
	// Bit mask of LP_SCRATCH10 field.
	LPSYSREG_LP_STORE10_LP_SCRATCH10_Msk = 0xffffffff

	// LP_STORE11: need_des
	// Position of LP_SCRATCH11 field.
	LPSYSREG_LP_STORE11_LP_SCRATCH11_Pos = 0x0
	// Bit mask of LP_SCRATCH11 field.
	LPSYSREG_LP_STORE11_LP_SCRATCH11_Msk = 0xffffffff

	// LP_STORE12: need_des
	// Position of LP_SCRATCH12 field.
	LPSYSREG_LP_STORE12_LP_SCRATCH12_Pos = 0x0
	// Bit mask of LP_SCRATCH12 field.
	LPSYSREG_LP_STORE12_LP_SCRATCH12_Msk = 0xffffffff

	// LP_STORE13: need_des
	// Position of LP_SCRATCH13 field.
	LPSYSREG_LP_STORE13_LP_SCRATCH13_Pos = 0x0
	// Bit mask of LP_SCRATCH13 field.
	LPSYSREG_LP_STORE13_LP_SCRATCH13_Msk = 0xffffffff

	// LP_STORE14: need_des
	// Position of LP_SCRATCH14 field.
	LPSYSREG_LP_STORE14_LP_SCRATCH14_Pos = 0x0
	// Bit mask of LP_SCRATCH14 field.
	LPSYSREG_LP_STORE14_LP_SCRATCH14_Msk = 0xffffffff

	// LP_STORE15: need_des
	// Position of LP_SCRATCH15 field.
	LPSYSREG_LP_STORE15_LP_SCRATCH15_Pos = 0x0
	// Bit mask of LP_SCRATCH15 field.
	LPSYSREG_LP_STORE15_LP_SCRATCH15_Msk = 0xffffffff

	// LP_PROBEA_CTRL: need_des
	// Position of PROBE_A_MOD_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_A_MOD_SEL_Pos = 0x0
	// Bit mask of PROBE_A_MOD_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_A_MOD_SEL_Msk = 0xffff
	// Position of PROBE_A_TOP_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_A_TOP_SEL_Pos = 0x10
	// Bit mask of PROBE_A_TOP_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_A_TOP_SEL_Msk = 0xff0000
	// Position of PROBE_L_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_L_SEL_Pos = 0x18
	// Bit mask of PROBE_L_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_L_SEL_Msk = 0x3000000
	// Position of PROBE_H_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_H_SEL_Pos = 0x1a
	// Bit mask of PROBE_H_SEL field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_H_SEL_Msk = 0xc000000
	// Position of PROBE_GLOBAL_EN field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_GLOBAL_EN_Pos = 0x1c
	// Bit mask of PROBE_GLOBAL_EN field.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_GLOBAL_EN_Msk = 0x10000000
	// Bit PROBE_GLOBAL_EN.
	LPSYSREG_LP_PROBEA_CTRL_PROBE_GLOBAL_EN = 0x10000000

	// LP_PROBEB_CTRL: need_des
	// Position of PROBE_B_MOD_SEL field.
	LPSYSREG_LP_PROBEB_CTRL_PROBE_B_MOD_SEL_Pos = 0x0
	// Bit mask of PROBE_B_MOD_SEL field.
	LPSYSREG_LP_PROBEB_CTRL_PROBE_B_MOD_SEL_Msk = 0xffff
	// Position of PROBE_B_TOP_SEL field.
	LPSYSREG_LP_PROBEB_CTRL_PROBE_B_TOP_SEL_Pos = 0x10
	// Bit mask of PROBE_B_TOP_SEL field.
	LPSYSREG_LP_PROBEB_CTRL_PROBE_B_TOP_SEL_Msk = 0xff0000
	// Position of PROBE_B_EN field.
	LPSYSREG_LP_PROBEB_CTRL_PROBE_B_EN_Pos = 0x18
	// Bit mask of PROBE_B_EN field.
	LPSYSREG_LP_PROBEB_CTRL_PROBE_B_EN_Msk = 0x1000000
	// Bit PROBE_B_EN.
	LPSYSREG_LP_PROBEB_CTRL_PROBE_B_EN = 0x1000000

	// LP_PROBE_OUT: need_des
	// Position of PROBE_TOP_OUT field.
	LPSYSREG_LP_PROBE_OUT_PROBE_TOP_OUT_Pos = 0x0
	// Bit mask of PROBE_TOP_OUT field.
	LPSYSREG_LP_PROBE_OUT_PROBE_TOP_OUT_Msk = 0xffffffff

	// F2S_APB_BRG_CNTL: need_des
	// Position of F2S_APB_POSTW_EN field.
	LPSYSREG_F2S_APB_BRG_CNTL_F2S_APB_POSTW_EN_Pos = 0x0
	// Bit mask of F2S_APB_POSTW_EN field.
	LPSYSREG_F2S_APB_BRG_CNTL_F2S_APB_POSTW_EN_Msk = 0x1
	// Bit F2S_APB_POSTW_EN.
	LPSYSREG_F2S_APB_BRG_CNTL_F2S_APB_POSTW_EN = 0x1

	// USB_CTRL: need_des
	// Position of SW_HW_USB_PHY_SEL field.
	LPSYSREG_USB_CTRL_SW_HW_USB_PHY_SEL_Pos = 0x0
	// Bit mask of SW_HW_USB_PHY_SEL field.
	LPSYSREG_USB_CTRL_SW_HW_USB_PHY_SEL_Msk = 0x1
	// Bit SW_HW_USB_PHY_SEL.
	LPSYSREG_USB_CTRL_SW_HW_USB_PHY_SEL = 0x1
	// Position of SW_USB_PHY_SEL field.
	LPSYSREG_USB_CTRL_SW_USB_PHY_SEL_Pos = 0x1
	// Bit mask of SW_USB_PHY_SEL field.
	LPSYSREG_USB_CTRL_SW_USB_PHY_SEL_Msk = 0x2
	// Bit SW_USB_PHY_SEL.
	LPSYSREG_USB_CTRL_SW_USB_PHY_SEL = 0x2
	// Position of USBOTG20_WAKEUP_CLR field.
	LPSYSREG_USB_CTRL_USBOTG20_WAKEUP_CLR_Pos = 0x2
	// Bit mask of USBOTG20_WAKEUP_CLR field.
	LPSYSREG_USB_CTRL_USBOTG20_WAKEUP_CLR_Msk = 0x4
	// Bit USBOTG20_WAKEUP_CLR.
	LPSYSREG_USB_CTRL_USBOTG20_WAKEUP_CLR = 0x4
	// Position of USBOTG20_IN_SUSPEND field.
	LPSYSREG_USB_CTRL_USBOTG20_IN_SUSPEND_Pos = 0x3
	// Bit mask of USBOTG20_IN_SUSPEND field.
	LPSYSREG_USB_CTRL_USBOTG20_IN_SUSPEND_Msk = 0x8
	// Bit USBOTG20_IN_SUSPEND.
	LPSYSREG_USB_CTRL_USBOTG20_IN_SUSPEND = 0x8

	// ANA_XPD_PAD_GROUP: need_des
	// Position of ANA_REG_XPD_PAD_GROUP field.
	LPSYSREG_ANA_XPD_PAD_GROUP_ANA_REG_XPD_PAD_GROUP_Pos = 0x0
	// Bit mask of ANA_REG_XPD_PAD_GROUP field.
	LPSYSREG_ANA_XPD_PAD_GROUP_ANA_REG_XPD_PAD_GROUP_Msk = 0xff

	// LP_TCM_RAM_RDN_ECO_CS: need_des
	// Position of LP_TCM_RAM_RDN_ECO_EN field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_EN_Pos = 0x0
	// Bit mask of LP_TCM_RAM_RDN_ECO_EN field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_EN_Msk = 0x1
	// Bit LP_TCM_RAM_RDN_ECO_EN.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_EN = 0x1
	// Position of LP_TCM_RAM_RDN_ECO_RESULT field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of LP_TCM_RAM_RDN_ECO_RESULT field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_RESULT_Msk = 0x2
	// Bit LP_TCM_RAM_RDN_ECO_RESULT.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_LP_TCM_RAM_RDN_ECO_RESULT = 0x2

	// LP_TCM_RAM_RDN_ECO_LOW: need_des
	// Position of LP_TCM_RAM_RDN_ECO_LOW field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_LP_TCM_RAM_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of LP_TCM_RAM_RDN_ECO_LOW field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_LP_TCM_RAM_RDN_ECO_LOW_Msk = 0xffffffff

	// LP_TCM_RAM_RDN_ECO_HIGH: need_des
	// Position of LP_TCM_RAM_RDN_ECO_HIGH field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_LP_TCM_RAM_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of LP_TCM_RAM_RDN_ECO_HIGH field.
	LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_LP_TCM_RAM_RDN_ECO_HIGH_Msk = 0xffffffff

	// LP_TCM_ROM_RDN_ECO_CS: need_des
	// Position of LP_TCM_ROM_RDN_ECO_EN field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_EN_Pos = 0x0
	// Bit mask of LP_TCM_ROM_RDN_ECO_EN field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_EN_Msk = 0x1
	// Bit LP_TCM_ROM_RDN_ECO_EN.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_EN = 0x1
	// Position of LP_TCM_ROM_RDN_ECO_RESULT field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_RESULT_Pos = 0x1
	// Bit mask of LP_TCM_ROM_RDN_ECO_RESULT field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_RESULT_Msk = 0x2
	// Bit LP_TCM_ROM_RDN_ECO_RESULT.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_LP_TCM_ROM_RDN_ECO_RESULT = 0x2

	// LP_TCM_ROM_RDN_ECO_LOW: need_des
	// Position of LP_TCM_ROM_RDN_ECO_LOW field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_LP_TCM_ROM_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of LP_TCM_ROM_RDN_ECO_LOW field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_LP_TCM_ROM_RDN_ECO_LOW_Msk = 0xffffffff

	// LP_TCM_ROM_RDN_ECO_HIGH: need_des
	// Position of LP_TCM_ROM_RDN_ECO_HIGH field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_LP_TCM_ROM_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of LP_TCM_ROM_RDN_ECO_HIGH field.
	LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_LP_TCM_ROM_RDN_ECO_HIGH_Msk = 0xffffffff

	// HP_ROOT_CLK_CTRL: need_des
	// Position of CPU_CLK_EN field.
	LPSYSREG_HP_ROOT_CLK_CTRL_CPU_CLK_EN_Pos = 0x0
	// Bit mask of CPU_CLK_EN field.
	LPSYSREG_HP_ROOT_CLK_CTRL_CPU_CLK_EN_Msk = 0x1
	// Bit CPU_CLK_EN.
	LPSYSREG_HP_ROOT_CLK_CTRL_CPU_CLK_EN = 0x1
	// Position of SYS_CLK_EN field.
	LPSYSREG_HP_ROOT_CLK_CTRL_SYS_CLK_EN_Pos = 0x1
	// Bit mask of SYS_CLK_EN field.
	LPSYSREG_HP_ROOT_CLK_CTRL_SYS_CLK_EN_Msk = 0x2
	// Bit SYS_CLK_EN.
	LPSYSREG_HP_ROOT_CLK_CTRL_SYS_CLK_EN = 0x2

	// LP_PMU_RDN_ECO_LOW: need_des
	// Position of PMU_RDN_ECO_LOW field.
	LPSYSREG_LP_PMU_RDN_ECO_LOW_PMU_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of PMU_RDN_ECO_LOW field.
	LPSYSREG_LP_PMU_RDN_ECO_LOW_PMU_RDN_ECO_LOW_Msk = 0xffffffff

	// LP_PMU_RDN_ECO_HIGH: need_des
	// Position of PMU_RDN_ECO_HIGH field.
	LPSYSREG_LP_PMU_RDN_ECO_HIGH_PMU_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of PMU_RDN_ECO_HIGH field.
	LPSYSREG_LP_PMU_RDN_ECO_HIGH_PMU_RDN_ECO_HIGH_Msk = 0xffffffff

	// PAD_COMP0: need_des
	// Position of DREF_COMP0 field.
	LPSYSREG_PAD_COMP0_DREF_COMP0_Pos = 0x0
	// Bit mask of DREF_COMP0 field.
	LPSYSREG_PAD_COMP0_DREF_COMP0_Msk = 0x7
	// Position of MODE_COMP0 field.
	LPSYSREG_PAD_COMP0_MODE_COMP0_Pos = 0x3
	// Bit mask of MODE_COMP0 field.
	LPSYSREG_PAD_COMP0_MODE_COMP0_Msk = 0x8
	// Bit MODE_COMP0.
	LPSYSREG_PAD_COMP0_MODE_COMP0 = 0x8
	// Position of XPD_COMP0 field.
	LPSYSREG_PAD_COMP0_XPD_COMP0_Pos = 0x4
	// Bit mask of XPD_COMP0 field.
	LPSYSREG_PAD_COMP0_XPD_COMP0_Msk = 0x10
	// Bit XPD_COMP0.
	LPSYSREG_PAD_COMP0_XPD_COMP0 = 0x10

	// PAD_COMP1: need_des
	// Position of DREF_COMP1 field.
	LPSYSREG_PAD_COMP1_DREF_COMP1_Pos = 0x0
	// Bit mask of DREF_COMP1 field.
	LPSYSREG_PAD_COMP1_DREF_COMP1_Msk = 0x7
	// Position of MODE_COMP1 field.
	LPSYSREG_PAD_COMP1_MODE_COMP1_Pos = 0x3
	// Bit mask of MODE_COMP1 field.
	LPSYSREG_PAD_COMP1_MODE_COMP1_Msk = 0x8
	// Bit MODE_COMP1.
	LPSYSREG_PAD_COMP1_MODE_COMP1 = 0x8
	// Position of XPD_COMP1 field.
	LPSYSREG_PAD_COMP1_XPD_COMP1_Pos = 0x4
	// Bit mask of XPD_COMP1 field.
	LPSYSREG_PAD_COMP1_XPD_COMP1_Msk = 0x10
	// Bit XPD_COMP1.
	LPSYSREG_PAD_COMP1_XPD_COMP1 = 0x10

	// BACKUP_DMA_CFG0: need_des
	// Position of BURST_LIMIT_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_BURST_LIMIT_AON_Pos = 0x0
	// Bit mask of BURST_LIMIT_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_BURST_LIMIT_AON_Msk = 0x1f
	// Position of READ_INTERVAL_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_READ_INTERVAL_AON_Pos = 0x5
	// Bit mask of READ_INTERVAL_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_READ_INTERVAL_AON_Msk = 0xfe0
	// Position of LINK_BACKUP_TOUT_THRES_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_LINK_BACKUP_TOUT_THRES_AON_Pos = 0xc
	// Bit mask of LINK_BACKUP_TOUT_THRES_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_LINK_BACKUP_TOUT_THRES_AON_Msk = 0x3ff000
	// Position of LINK_TOUT_THRES_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_LINK_TOUT_THRES_AON_Pos = 0x16
	// Bit mask of LINK_TOUT_THRES_AON field.
	LPSYSREG_BACKUP_DMA_CFG0_LINK_TOUT_THRES_AON_Msk = 0xffc00000

	// BACKUP_DMA_CFG1: need_des
	// Position of AON_BYPASS field.
	LPSYSREG_BACKUP_DMA_CFG1_AON_BYPASS_Pos = 0x1f
	// Bit mask of AON_BYPASS field.
	LPSYSREG_BACKUP_DMA_CFG1_AON_BYPASS_Msk = 0x80000000
	// Bit AON_BYPASS.
	LPSYSREG_BACKUP_DMA_CFG1_AON_BYPASS = 0x80000000

	// BACKUP_DMA_CFG2: need_des
	// Position of LINK_ADDR_AON field.
	LPSYSREG_BACKUP_DMA_CFG2_LINK_ADDR_AON_Pos = 0x0
	// Bit mask of LINK_ADDR_AON field.
	LPSYSREG_BACKUP_DMA_CFG2_LINK_ADDR_AON_Msk = 0xffffffff

	// BOOT_ADDR_HP_CORE1: need_des
	// Position of BOOT_ADDR_HP_CORE1 field.
	LPSYSREG_BOOT_ADDR_HP_CORE1_BOOT_ADDR_HP_CORE1_Pos = 0x0
	// Bit mask of BOOT_ADDR_HP_CORE1 field.
	LPSYSREG_BOOT_ADDR_HP_CORE1_BOOT_ADDR_HP_CORE1_Msk = 0xffffffff

	// LP_ADDRHOLE_ADDR: need_des
	// Position of LP_ADDRHOLE_ADDR field.
	LPSYSREG_LP_ADDRHOLE_ADDR_LP_ADDRHOLE_ADDR_Pos = 0x0
	// Bit mask of LP_ADDRHOLE_ADDR field.
	LPSYSREG_LP_ADDRHOLE_ADDR_LP_ADDRHOLE_ADDR_Msk = 0xffffffff

	// LP_ADDRHOLE_INFO: need_des
	// Position of LP_ADDRHOLE_ID field.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_ID_Pos = 0x0
	// Bit mask of LP_ADDRHOLE_ID field.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_ID_Msk = 0x1f
	// Position of LP_ADDRHOLE_WR field.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_WR_Pos = 0x5
	// Bit mask of LP_ADDRHOLE_WR field.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_WR_Msk = 0x20
	// Bit LP_ADDRHOLE_WR.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_WR = 0x20
	// Position of LP_ADDRHOLE_SECURE field.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_SECURE_Pos = 0x6
	// Bit mask of LP_ADDRHOLE_SECURE field.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_SECURE_Msk = 0x40
	// Bit LP_ADDRHOLE_SECURE.
	LPSYSREG_LP_ADDRHOLE_INFO_LP_ADDRHOLE_SECURE = 0x40

	// INT_RAW: raw interrupt register
	// Position of LP_ADDRHOLE_INT_RAW field.
	LPSYSREG_INT_RAW_LP_ADDRHOLE_INT_RAW_Pos = 0x0
	// Bit mask of LP_ADDRHOLE_INT_RAW field.
	LPSYSREG_INT_RAW_LP_ADDRHOLE_INT_RAW_Msk = 0x1
	// Bit LP_ADDRHOLE_INT_RAW.
	LPSYSREG_INT_RAW_LP_ADDRHOLE_INT_RAW = 0x1
	// Position of IDBUS_ADDRHOLE_INT_RAW field.
	LPSYSREG_INT_RAW_IDBUS_ADDRHOLE_INT_RAW_Pos = 0x1
	// Bit mask of IDBUS_ADDRHOLE_INT_RAW field.
	LPSYSREG_INT_RAW_IDBUS_ADDRHOLE_INT_RAW_Msk = 0x2
	// Bit IDBUS_ADDRHOLE_INT_RAW.
	LPSYSREG_INT_RAW_IDBUS_ADDRHOLE_INT_RAW = 0x2
	// Position of LP_CORE_AHB_TIMEOUT_INT_RAW field.
	LPSYSREG_INT_RAW_LP_CORE_AHB_TIMEOUT_INT_RAW_Pos = 0x2
	// Bit mask of LP_CORE_AHB_TIMEOUT_INT_RAW field.
	LPSYSREG_INT_RAW_LP_CORE_AHB_TIMEOUT_INT_RAW_Msk = 0x4
	// Bit LP_CORE_AHB_TIMEOUT_INT_RAW.
	LPSYSREG_INT_RAW_LP_CORE_AHB_TIMEOUT_INT_RAW = 0x4
	// Position of LP_CORE_IBUS_TIMEOUT_INT_RAW field.
	LPSYSREG_INT_RAW_LP_CORE_IBUS_TIMEOUT_INT_RAW_Pos = 0x3
	// Bit mask of LP_CORE_IBUS_TIMEOUT_INT_RAW field.
	LPSYSREG_INT_RAW_LP_CORE_IBUS_TIMEOUT_INT_RAW_Msk = 0x8
	// Bit LP_CORE_IBUS_TIMEOUT_INT_RAW.
	LPSYSREG_INT_RAW_LP_CORE_IBUS_TIMEOUT_INT_RAW = 0x8
	// Position of LP_CORE_DBUS_TIMEOUT_INT_RAW field.
	LPSYSREG_INT_RAW_LP_CORE_DBUS_TIMEOUT_INT_RAW_Pos = 0x4
	// Bit mask of LP_CORE_DBUS_TIMEOUT_INT_RAW field.
	LPSYSREG_INT_RAW_LP_CORE_DBUS_TIMEOUT_INT_RAW_Msk = 0x10
	// Bit LP_CORE_DBUS_TIMEOUT_INT_RAW.
	LPSYSREG_INT_RAW_LP_CORE_DBUS_TIMEOUT_INT_RAW = 0x10
	// Position of ETM_TASK_ULP_INT_RAW field.
	LPSYSREG_INT_RAW_ETM_TASK_ULP_INT_RAW_Pos = 0x5
	// Bit mask of ETM_TASK_ULP_INT_RAW field.
	LPSYSREG_INT_RAW_ETM_TASK_ULP_INT_RAW_Msk = 0x20
	// Bit ETM_TASK_ULP_INT_RAW.
	LPSYSREG_INT_RAW_ETM_TASK_ULP_INT_RAW = 0x20
	// Position of SLOW_CLK_TICK_INT_RAW field.
	LPSYSREG_INT_RAW_SLOW_CLK_TICK_INT_RAW_Pos = 0x6
	// Bit mask of SLOW_CLK_TICK_INT_RAW field.
	LPSYSREG_INT_RAW_SLOW_CLK_TICK_INT_RAW_Msk = 0x40
	// Bit SLOW_CLK_TICK_INT_RAW.
	LPSYSREG_INT_RAW_SLOW_CLK_TICK_INT_RAW = 0x40

	// INT_ST: masked interrupt register
	// Position of LP_ADDRHOLE_INT_ST field.
	LPSYSREG_INT_ST_LP_ADDRHOLE_INT_ST_Pos = 0x0
	// Bit mask of LP_ADDRHOLE_INT_ST field.
	LPSYSREG_INT_ST_LP_ADDRHOLE_INT_ST_Msk = 0x1
	// Bit LP_ADDRHOLE_INT_ST.
	LPSYSREG_INT_ST_LP_ADDRHOLE_INT_ST = 0x1
	// Position of IDBUS_ADDRHOLE_INT_ST field.
	LPSYSREG_INT_ST_IDBUS_ADDRHOLE_INT_ST_Pos = 0x1
	// Bit mask of IDBUS_ADDRHOLE_INT_ST field.
	LPSYSREG_INT_ST_IDBUS_ADDRHOLE_INT_ST_Msk = 0x2
	// Bit IDBUS_ADDRHOLE_INT_ST.
	LPSYSREG_INT_ST_IDBUS_ADDRHOLE_INT_ST = 0x2
	// Position of LP_CORE_AHB_TIMEOUT_INT_ST field.
	LPSYSREG_INT_ST_LP_CORE_AHB_TIMEOUT_INT_ST_Pos = 0x2
	// Bit mask of LP_CORE_AHB_TIMEOUT_INT_ST field.
	LPSYSREG_INT_ST_LP_CORE_AHB_TIMEOUT_INT_ST_Msk = 0x4
	// Bit LP_CORE_AHB_TIMEOUT_INT_ST.
	LPSYSREG_INT_ST_LP_CORE_AHB_TIMEOUT_INT_ST = 0x4
	// Position of LP_CORE_IBUS_TIMEOUT_INT_ST field.
	LPSYSREG_INT_ST_LP_CORE_IBUS_TIMEOUT_INT_ST_Pos = 0x3
	// Bit mask of LP_CORE_IBUS_TIMEOUT_INT_ST field.
	LPSYSREG_INT_ST_LP_CORE_IBUS_TIMEOUT_INT_ST_Msk = 0x8
	// Bit LP_CORE_IBUS_TIMEOUT_INT_ST.
	LPSYSREG_INT_ST_LP_CORE_IBUS_TIMEOUT_INT_ST = 0x8
	// Position of LP_CORE_DBUS_TIMEOUT_INT_ST field.
	LPSYSREG_INT_ST_LP_CORE_DBUS_TIMEOUT_INT_ST_Pos = 0x4
	// Bit mask of LP_CORE_DBUS_TIMEOUT_INT_ST field.
	LPSYSREG_INT_ST_LP_CORE_DBUS_TIMEOUT_INT_ST_Msk = 0x10
	// Bit LP_CORE_DBUS_TIMEOUT_INT_ST.
	LPSYSREG_INT_ST_LP_CORE_DBUS_TIMEOUT_INT_ST = 0x10
	// Position of ETM_TASK_ULP_INT_ST field.
	LPSYSREG_INT_ST_ETM_TASK_ULP_INT_ST_Pos = 0x5
	// Bit mask of ETM_TASK_ULP_INT_ST field.
	LPSYSREG_INT_ST_ETM_TASK_ULP_INT_ST_Msk = 0x20
	// Bit ETM_TASK_ULP_INT_ST.
	LPSYSREG_INT_ST_ETM_TASK_ULP_INT_ST = 0x20
	// Position of SLOW_CLK_TICK_INT_ST field.
	LPSYSREG_INT_ST_SLOW_CLK_TICK_INT_ST_Pos = 0x6
	// Bit mask of SLOW_CLK_TICK_INT_ST field.
	LPSYSREG_INT_ST_SLOW_CLK_TICK_INT_ST_Msk = 0x40
	// Bit SLOW_CLK_TICK_INT_ST.
	LPSYSREG_INT_ST_SLOW_CLK_TICK_INT_ST = 0x40

	// INT_ENA: masked interrupt register
	// Position of LP_ADDRHOLE_INT_ENA field.
	LPSYSREG_INT_ENA_LP_ADDRHOLE_INT_ENA_Pos = 0x0
	// Bit mask of LP_ADDRHOLE_INT_ENA field.
	LPSYSREG_INT_ENA_LP_ADDRHOLE_INT_ENA_Msk = 0x1
	// Bit LP_ADDRHOLE_INT_ENA.
	LPSYSREG_INT_ENA_LP_ADDRHOLE_INT_ENA = 0x1
	// Position of IDBUS_ADDRHOLE_INT_ENA field.
	LPSYSREG_INT_ENA_IDBUS_ADDRHOLE_INT_ENA_Pos = 0x1
	// Bit mask of IDBUS_ADDRHOLE_INT_ENA field.
	LPSYSREG_INT_ENA_IDBUS_ADDRHOLE_INT_ENA_Msk = 0x2
	// Bit IDBUS_ADDRHOLE_INT_ENA.
	LPSYSREG_INT_ENA_IDBUS_ADDRHOLE_INT_ENA = 0x2
	// Position of LP_CORE_AHB_TIMEOUT_INT_ENA field.
	LPSYSREG_INT_ENA_LP_CORE_AHB_TIMEOUT_INT_ENA_Pos = 0x2
	// Bit mask of LP_CORE_AHB_TIMEOUT_INT_ENA field.
	LPSYSREG_INT_ENA_LP_CORE_AHB_TIMEOUT_INT_ENA_Msk = 0x4
	// Bit LP_CORE_AHB_TIMEOUT_INT_ENA.
	LPSYSREG_INT_ENA_LP_CORE_AHB_TIMEOUT_INT_ENA = 0x4
	// Position of LP_CORE_IBUS_TIMEOUT_INT_ENA field.
	LPSYSREG_INT_ENA_LP_CORE_IBUS_TIMEOUT_INT_ENA_Pos = 0x3
	// Bit mask of LP_CORE_IBUS_TIMEOUT_INT_ENA field.
	LPSYSREG_INT_ENA_LP_CORE_IBUS_TIMEOUT_INT_ENA_Msk = 0x8
	// Bit LP_CORE_IBUS_TIMEOUT_INT_ENA.
	LPSYSREG_INT_ENA_LP_CORE_IBUS_TIMEOUT_INT_ENA = 0x8
	// Position of LP_CORE_DBUS_TIMEOUT_INT_ENA field.
	LPSYSREG_INT_ENA_LP_CORE_DBUS_TIMEOUT_INT_ENA_Pos = 0x4
	// Bit mask of LP_CORE_DBUS_TIMEOUT_INT_ENA field.
	LPSYSREG_INT_ENA_LP_CORE_DBUS_TIMEOUT_INT_ENA_Msk = 0x10
	// Bit LP_CORE_DBUS_TIMEOUT_INT_ENA.
	LPSYSREG_INT_ENA_LP_CORE_DBUS_TIMEOUT_INT_ENA = 0x10
	// Position of ETM_TASK_ULP_INT_ENA field.
	LPSYSREG_INT_ENA_ETM_TASK_ULP_INT_ENA_Pos = 0x5
	// Bit mask of ETM_TASK_ULP_INT_ENA field.
	LPSYSREG_INT_ENA_ETM_TASK_ULP_INT_ENA_Msk = 0x20
	// Bit ETM_TASK_ULP_INT_ENA.
	LPSYSREG_INT_ENA_ETM_TASK_ULP_INT_ENA = 0x20
	// Position of SLOW_CLK_TICK_INT_ENA field.
	LPSYSREG_INT_ENA_SLOW_CLK_TICK_INT_ENA_Pos = 0x6
	// Bit mask of SLOW_CLK_TICK_INT_ENA field.
	LPSYSREG_INT_ENA_SLOW_CLK_TICK_INT_ENA_Msk = 0x40
	// Bit SLOW_CLK_TICK_INT_ENA.
	LPSYSREG_INT_ENA_SLOW_CLK_TICK_INT_ENA = 0x40

	// INT_CLR: interrupt clear register
	// Position of LP_ADDRHOLE_INT_CLR field.
	LPSYSREG_INT_CLR_LP_ADDRHOLE_INT_CLR_Pos = 0x0
	// Bit mask of LP_ADDRHOLE_INT_CLR field.
	LPSYSREG_INT_CLR_LP_ADDRHOLE_INT_CLR_Msk = 0x1
	// Bit LP_ADDRHOLE_INT_CLR.
	LPSYSREG_INT_CLR_LP_ADDRHOLE_INT_CLR = 0x1
	// Position of IDBUS_ADDRHOLE_INT_CLR field.
	LPSYSREG_INT_CLR_IDBUS_ADDRHOLE_INT_CLR_Pos = 0x1
	// Bit mask of IDBUS_ADDRHOLE_INT_CLR field.
	LPSYSREG_INT_CLR_IDBUS_ADDRHOLE_INT_CLR_Msk = 0x2
	// Bit IDBUS_ADDRHOLE_INT_CLR.
	LPSYSREG_INT_CLR_IDBUS_ADDRHOLE_INT_CLR = 0x2
	// Position of LP_CORE_AHB_TIMEOUT_INT_CLR field.
	LPSYSREG_INT_CLR_LP_CORE_AHB_TIMEOUT_INT_CLR_Pos = 0x2
	// Bit mask of LP_CORE_AHB_TIMEOUT_INT_CLR field.
	LPSYSREG_INT_CLR_LP_CORE_AHB_TIMEOUT_INT_CLR_Msk = 0x4
	// Bit LP_CORE_AHB_TIMEOUT_INT_CLR.
	LPSYSREG_INT_CLR_LP_CORE_AHB_TIMEOUT_INT_CLR = 0x4
	// Position of LP_CORE_IBUS_TIMEOUT_INT_CLR field.
	LPSYSREG_INT_CLR_LP_CORE_IBUS_TIMEOUT_INT_CLR_Pos = 0x3
	// Bit mask of LP_CORE_IBUS_TIMEOUT_INT_CLR field.
	LPSYSREG_INT_CLR_LP_CORE_IBUS_TIMEOUT_INT_CLR_Msk = 0x8
	// Bit LP_CORE_IBUS_TIMEOUT_INT_CLR.
	LPSYSREG_INT_CLR_LP_CORE_IBUS_TIMEOUT_INT_CLR = 0x8
	// Position of LP_CORE_DBUS_TIMEOUT_INT_CLR field.
	LPSYSREG_INT_CLR_LP_CORE_DBUS_TIMEOUT_INT_CLR_Pos = 0x4
	// Bit mask of LP_CORE_DBUS_TIMEOUT_INT_CLR field.
	LPSYSREG_INT_CLR_LP_CORE_DBUS_TIMEOUT_INT_CLR_Msk = 0x10
	// Bit LP_CORE_DBUS_TIMEOUT_INT_CLR.
	LPSYSREG_INT_CLR_LP_CORE_DBUS_TIMEOUT_INT_CLR = 0x10
	// Position of ETM_TASK_ULP_INT_CLR field.
	LPSYSREG_INT_CLR_ETM_TASK_ULP_INT_CLR_Pos = 0x5
	// Bit mask of ETM_TASK_ULP_INT_CLR field.
	LPSYSREG_INT_CLR_ETM_TASK_ULP_INT_CLR_Msk = 0x20
	// Bit ETM_TASK_ULP_INT_CLR.
	LPSYSREG_INT_CLR_ETM_TASK_ULP_INT_CLR = 0x20
	// Position of SLOW_CLK_TICK_INT_CLR field.
	LPSYSREG_INT_CLR_SLOW_CLK_TICK_INT_CLR_Pos = 0x6
	// Bit mask of SLOW_CLK_TICK_INT_CLR field.
	LPSYSREG_INT_CLR_SLOW_CLK_TICK_INT_CLR_Msk = 0x40
	// Bit SLOW_CLK_TICK_INT_CLR.
	LPSYSREG_INT_CLR_SLOW_CLK_TICK_INT_CLR = 0x40

	// HP_MEM_AUX_CTRL: need_des
	// Position of HP_MEM_AUX_CTRL field.
	LPSYSREG_HP_MEM_AUX_CTRL_HP_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of HP_MEM_AUX_CTRL field.
	LPSYSREG_HP_MEM_AUX_CTRL_HP_MEM_AUX_CTRL_Msk = 0xffffffff

	// LP_MEM_AUX_CTRL: need_des
	// Position of LP_MEM_AUX_CTRL field.
	LPSYSREG_LP_MEM_AUX_CTRL_LP_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of LP_MEM_AUX_CTRL field.
	LPSYSREG_LP_MEM_AUX_CTRL_LP_MEM_AUX_CTRL_Msk = 0xffffffff

	// HP_ROM_AUX_CTRL: need_des
	// Position of HP_ROM_AUX_CTRL field.
	LPSYSREG_HP_ROM_AUX_CTRL_HP_ROM_AUX_CTRL_Pos = 0x0
	// Bit mask of HP_ROM_AUX_CTRL field.
	LPSYSREG_HP_ROM_AUX_CTRL_HP_ROM_AUX_CTRL_Msk = 0xffffffff

	// LP_ROM_AUX_CTRL: need_des
	// Position of LP_ROM_AUX_CTRL field.
	LPSYSREG_LP_ROM_AUX_CTRL_LP_ROM_AUX_CTRL_Pos = 0x0
	// Bit mask of LP_ROM_AUX_CTRL field.
	LPSYSREG_LP_ROM_AUX_CTRL_LP_ROM_AUX_CTRL_Msk = 0xffffffff

	// LP_CPU_DBG_PC: need_des
	// Position of LP_CPU_DBG_PC field.
	LPSYSREG_LP_CPU_DBG_PC_LP_CPU_DBG_PC_Pos = 0x0
	// Bit mask of LP_CPU_DBG_PC field.
	LPSYSREG_LP_CPU_DBG_PC_LP_CPU_DBG_PC_Msk = 0xffffffff

	// LP_CPU_EXC_PC: need_des
	// Position of LP_CPU_EXC_PC field.
	LPSYSREG_LP_CPU_EXC_PC_LP_CPU_EXC_PC_Pos = 0x0
	// Bit mask of LP_CPU_EXC_PC field.
	LPSYSREG_LP_CPU_EXC_PC_LP_CPU_EXC_PC_Msk = 0xffffffff

	// IDBUS_ADDRHOLE_ADDR: need_des
	// Position of IDBUS_ADDRHOLE_ADDR field.
	LPSYSREG_IDBUS_ADDRHOLE_ADDR_IDBUS_ADDRHOLE_ADDR_Pos = 0x0
	// Bit mask of IDBUS_ADDRHOLE_ADDR field.
	LPSYSREG_IDBUS_ADDRHOLE_ADDR_IDBUS_ADDRHOLE_ADDR_Msk = 0xffffffff

	// IDBUS_ADDRHOLE_INFO: need_des
	// Position of IDBUS_ADDRHOLE_ID field.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_ID_Pos = 0x0
	// Bit mask of IDBUS_ADDRHOLE_ID field.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_ID_Msk = 0x1f
	// Position of IDBUS_ADDRHOLE_WR field.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_WR_Pos = 0x5
	// Bit mask of IDBUS_ADDRHOLE_WR field.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_WR_Msk = 0x20
	// Bit IDBUS_ADDRHOLE_WR.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_WR = 0x20
	// Position of IDBUS_ADDRHOLE_SECURE field.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_SECURE_Pos = 0x6
	// Bit mask of IDBUS_ADDRHOLE_SECURE field.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_SECURE_Msk = 0x40
	// Bit IDBUS_ADDRHOLE_SECURE.
	LPSYSREG_IDBUS_ADDRHOLE_INFO_IDBUS_ADDRHOLE_SECURE = 0x40

	// HP_POR_RST_BYPASS_CTRL: need_des
	// Position of HP_PO_CNNT_RSTN_BYPASS_CTRL field.
	LPSYSREG_HP_POR_RST_BYPASS_CTRL_HP_PO_CNNT_RSTN_BYPASS_CTRL_Pos = 0x8
	// Bit mask of HP_PO_CNNT_RSTN_BYPASS_CTRL field.
	LPSYSREG_HP_POR_RST_BYPASS_CTRL_HP_PO_CNNT_RSTN_BYPASS_CTRL_Msk = 0xff00
	// Position of HP_PO_RSTN_BYPASS_CTRL field.
	LPSYSREG_HP_POR_RST_BYPASS_CTRL_HP_PO_RSTN_BYPASS_CTRL_Pos = 0x18
	// Bit mask of HP_PO_RSTN_BYPASS_CTRL field.
	LPSYSREG_HP_POR_RST_BYPASS_CTRL_HP_PO_RSTN_BYPASS_CTRL_Msk = 0xff000000

	// RNG_DATA: rng data register
	// Position of RND_DATA field.
	LPSYSREG_RNG_DATA_RND_DATA_Pos = 0x0
	// Bit mask of RND_DATA field.
	LPSYSREG_RNG_DATA_RND_DATA_Msk = 0xffffffff

	// LP_CORE_AHB_TIMEOUT: need_des
	// Position of EN field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_EN_Pos = 0x0
	// Bit mask of EN field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_EN_Msk = 0x1
	// Bit EN.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_EN = 0x1
	// Position of THRES field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES_Pos = 0x1
	// Bit mask of THRES field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES_Msk = 0x1fffe
	// Position of LP2HP_AHB_TIMEOUT_EN field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_EN_Pos = 0x11
	// Bit mask of LP2HP_AHB_TIMEOUT_EN field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_EN_Msk = 0x20000
	// Bit LP2HP_AHB_TIMEOUT_EN.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_EN = 0x20000
	// Position of LP2HP_AHB_TIMEOUT_THRES field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_THRES_Pos = 0x12
	// Bit mask of LP2HP_AHB_TIMEOUT_THRES field.
	LPSYSREG_LP_CORE_AHB_TIMEOUT_LP2HP_AHB_TIMEOUT_THRES_Msk = 0x7c0000

	// LP_CORE_IBUS_TIMEOUT: need_des
	// Position of EN field.
	LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN_Pos = 0x0
	// Bit mask of EN field.
	LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN_Msk = 0x1
	// Bit EN.
	LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN = 0x1
	// Position of THRES field.
	LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES_Pos = 0x1
	// Bit mask of THRES field.
	LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES_Msk = 0x1fffe

	// LP_CORE_DBUS_TIMEOUT: need_des
	// Position of EN field.
	LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN_Pos = 0x0
	// Bit mask of EN field.
	LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN_Msk = 0x1
	// Bit EN.
	LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN = 0x1
	// Position of THRES field.
	LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES_Pos = 0x1
	// Bit mask of THRES field.
	LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES_Msk = 0x1fffe

	// LP_CORE_ERR_RESP_DIS: need_des
	// Position of LP_CORE_ERR_RESP_DIS field.
	LPSYSREG_LP_CORE_ERR_RESP_DIS_LP_CORE_ERR_RESP_DIS_Pos = 0x0
	// Bit mask of LP_CORE_ERR_RESP_DIS field.
	LPSYSREG_LP_CORE_ERR_RESP_DIS_LP_CORE_ERR_RESP_DIS_Msk = 0x7

	// RNG_CFG: rng cfg register
	// Position of RNG_TIMER_EN field.
	LPSYSREG_RNG_CFG_RNG_TIMER_EN_Pos = 0x0
	// Bit mask of RNG_TIMER_EN field.
	LPSYSREG_RNG_CFG_RNG_TIMER_EN_Msk = 0x1
	// Bit RNG_TIMER_EN.
	LPSYSREG_RNG_CFG_RNG_TIMER_EN = 0x1
	// Position of RNG_TIMER_PSCALE field.
	LPSYSREG_RNG_CFG_RNG_TIMER_PSCALE_Pos = 0x1
	// Bit mask of RNG_TIMER_PSCALE field.
	LPSYSREG_RNG_CFG_RNG_TIMER_PSCALE_Msk = 0x1fe
	// Position of RNG_SAR_ENABLE field.
	LPSYSREG_RNG_CFG_RNG_SAR_ENABLE_Pos = 0x9
	// Bit mask of RNG_SAR_ENABLE field.
	LPSYSREG_RNG_CFG_RNG_SAR_ENABLE_Msk = 0x200
	// Bit RNG_SAR_ENABLE.
	LPSYSREG_RNG_CFG_RNG_SAR_ENABLE = 0x200
	// Position of RNG_SAR_DATA field.
	LPSYSREG_RNG_CFG_RNG_SAR_DATA_Pos = 0x10
	// Bit mask of RNG_SAR_DATA field.
	LPSYSREG_RNG_CFG_RNG_SAR_DATA_Msk = 0x1fff0000
)

// Constants for LP_ANA_PERI: LP_ANA_PERI Peripheral
const (
	// LP_ANA_BOD_MODE0_CNTL: need_des
	// Position of LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_Pos = 0x6
	// Bit mask of LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_Msk = 0x40
	// Bit LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA = 0x40
	// Position of LP_ANA_BOD_MODE0_PD_RF_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_PD_RF_ENA_Pos = 0x7
	// Bit mask of LP_ANA_BOD_MODE0_PD_RF_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_PD_RF_ENA_Msk = 0x80
	// Bit LP_ANA_BOD_MODE0_PD_RF_ENA.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_PD_RF_ENA = 0x80
	// Position of LP_ANA_BOD_MODE0_INTR_WAIT field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_WAIT_Pos = 0x8
	// Bit mask of LP_ANA_BOD_MODE0_INTR_WAIT field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_WAIT_Msk = 0x3ff00
	// Position of LP_ANA_BOD_MODE0_RESET_WAIT field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_WAIT_Pos = 0x12
	// Bit mask of LP_ANA_BOD_MODE0_RESET_WAIT field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_WAIT_Msk = 0xffc0000
	// Position of LP_ANA_BOD_MODE0_CNT_CLR field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CNT_CLR_Pos = 0x1c
	// Bit mask of LP_ANA_BOD_MODE0_CNT_CLR field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CNT_CLR_Msk = 0x10000000
	// Bit LP_ANA_BOD_MODE0_CNT_CLR.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_CNT_CLR = 0x10000000
	// Position of LP_ANA_BOD_MODE0_INTR_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_ENA_Pos = 0x1d
	// Bit mask of LP_ANA_BOD_MODE0_INTR_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_ENA_Msk = 0x20000000
	// Bit LP_ANA_BOD_MODE0_INTR_ENA.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_INTR_ENA = 0x20000000
	// Position of LP_ANA_BOD_MODE0_RESET_SEL field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_SEL_Pos = 0x1e
	// Bit mask of LP_ANA_BOD_MODE0_RESET_SEL field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_SEL_Msk = 0x40000000
	// Bit LP_ANA_BOD_MODE0_RESET_SEL.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_SEL = 0x40000000
	// Position of LP_ANA_BOD_MODE0_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_ENA_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_ENA_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_RESET_ENA.
	LP_ANA_PERI_LP_ANA_BOD_MODE0_CNTL_LP_ANA_BOD_MODE0_RESET_ENA = 0x80000000

	// LP_ANA_BOD_MODE1_CNTL: need_des
	// Position of LP_ANA_BOD_MODE1_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE1_CNTL_LP_ANA_BOD_MODE1_RESET_ENA_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE1_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_BOD_MODE1_CNTL_LP_ANA_BOD_MODE1_RESET_ENA_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE1_RESET_ENA.
	LP_ANA_PERI_LP_ANA_BOD_MODE1_CNTL_LP_ANA_BOD_MODE1_RESET_ENA = 0x80000000

	// LP_ANA_VDD_SOURCE_CNTL: need_des
	// Position of LP_ANA_DETMODE_SEL field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_DETMODE_SEL_Pos = 0x0
	// Bit mask of LP_ANA_DETMODE_SEL field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_DETMODE_SEL_Msk = 0xff
	// Position of LP_ANA_VGOOD_EVENT_RECORD field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_VGOOD_EVENT_RECORD_Pos = 0x8
	// Bit mask of LP_ANA_VGOOD_EVENT_RECORD field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_VGOOD_EVENT_RECORD_Msk = 0xff00
	// Position of LP_ANA_VBAT_EVENT_RECORD_CLR field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_VBAT_EVENT_RECORD_CLR_Pos = 0x10
	// Bit mask of LP_ANA_VBAT_EVENT_RECORD_CLR field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_VBAT_EVENT_RECORD_CLR_Msk = 0xff0000
	// Position of LP_ANA_BOD_SOURCE_ENA field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_BOD_SOURCE_ENA_Pos = 0x18
	// Bit mask of LP_ANA_BOD_SOURCE_ENA field.
	LP_ANA_PERI_LP_ANA_VDD_SOURCE_CNTL_LP_ANA_BOD_SOURCE_ENA_Msk = 0xff000000

	// LP_ANA_VDDBAT_BOD_CNTL: need_des
	// Position of LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_Pos = 0x0
	// Bit mask of LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_Msk = 0x1
	// Bit LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG = 0x1
	// Position of LP_ANA_VDDBAT_CHARGER field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CHARGER_Pos = 0xa
	// Bit mask of LP_ANA_VDDBAT_CHARGER field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CHARGER_Msk = 0x400
	// Bit LP_ANA_VDDBAT_CHARGER.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CHARGER = 0x400
	// Position of LP_ANA_VDDBAT_CNT_CLR field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CNT_CLR_Pos = 0xb
	// Bit mask of LP_ANA_VDDBAT_CNT_CLR field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CNT_CLR_Msk = 0x800
	// Bit LP_ANA_VDDBAT_CNT_CLR.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_CNT_CLR = 0x800
	// Position of LP_ANA_VDDBAT_UPVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UPVOLTAGE_TARGET_Pos = 0xc
	// Bit mask of LP_ANA_VDDBAT_UPVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UPVOLTAGE_TARGET_Msk = 0x3ff000
	// Position of LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_Pos = 0x16
	// Bit mask of LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_BOD_CNTL_LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_Msk = 0xffc00000

	// LP_ANA_VDDBAT_CHARGE_CNTL: need_des
	// Position of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_Pos = 0x0
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_Msk = 0x1
	// Bit LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG = 0x1
	// Position of LP_ANA_VDDBAT_CHARGE_CHARGER field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CHARGER_Pos = 0xa
	// Bit mask of LP_ANA_VDDBAT_CHARGE_CHARGER field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CHARGER_Msk = 0x400
	// Bit LP_ANA_VDDBAT_CHARGE_CHARGER.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CHARGER = 0x400
	// Position of LP_ANA_VDDBAT_CHARGE_CNT_CLR field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CNT_CLR_Pos = 0xb
	// Bit mask of LP_ANA_VDDBAT_CHARGE_CNT_CLR field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CNT_CLR_Msk = 0x800
	// Bit LP_ANA_VDDBAT_CHARGE_CNT_CLR.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_CNT_CLR = 0x800
	// Position of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_Pos = 0xc
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_Msk = 0x3ff000
	// Position of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_Pos = 0x16
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET field.
	LP_ANA_PERI_LP_ANA_VDDBAT_CHARGE_CNTL_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_Msk = 0xffc00000

	// LP_ANA_CK_GLITCH_CNTL: need_des
	// Position of LP_ANA_CK_GLITCH_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_CK_GLITCH_CNTL_LP_ANA_CK_GLITCH_RESET_ENA_Pos = 0x1f
	// Bit mask of LP_ANA_CK_GLITCH_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_CK_GLITCH_CNTL_LP_ANA_CK_GLITCH_RESET_ENA_Msk = 0x80000000
	// Bit LP_ANA_CK_GLITCH_RESET_ENA.
	LP_ANA_PERI_LP_ANA_CK_GLITCH_CNTL_LP_ANA_CK_GLITCH_RESET_ENA = 0x80000000

	// LP_ANA_PG_GLITCH_CNTL: need_des
	// Position of LP_ANA_POWER_GLITCH_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_PG_GLITCH_CNTL_LP_ANA_POWER_GLITCH_RESET_ENA_Pos = 0x1f
	// Bit mask of LP_ANA_POWER_GLITCH_RESET_ENA field.
	LP_ANA_PERI_LP_ANA_PG_GLITCH_CNTL_LP_ANA_POWER_GLITCH_RESET_ENA_Msk = 0x80000000
	// Bit LP_ANA_POWER_GLITCH_RESET_ENA.
	LP_ANA_PERI_LP_ANA_PG_GLITCH_CNTL_LP_ANA_POWER_GLITCH_RESET_ENA = 0x80000000

	// LP_ANA_FIB_ENABLE: need_des
	// Position of LP_ANA_ANA_FIB_ENA field.
	LP_ANA_PERI_LP_ANA_FIB_ENABLE_LP_ANA_ANA_FIB_ENA_Pos = 0x0
	// Bit mask of LP_ANA_ANA_FIB_ENA field.
	LP_ANA_PERI_LP_ANA_FIB_ENABLE_LP_ANA_ANA_FIB_ENA_Msk = 0xffffffff

	// LP_ANA_INT_RAW: need_des
	// Position of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_Pos = 0x1b
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_Msk = 0x8000000
	// Bit LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW = 0x8000000
	// Position of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_Pos = 0x1c
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_Msk = 0x10000000
	// Bit LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW = 0x10000000
	// Position of LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_Pos = 0x1d
	// Bit mask of LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_Msk = 0x20000000
	// Bit LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW = 0x20000000
	// Position of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_Pos = 0x1e
	// Bit mask of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_Msk = 0x40000000
	// Bit LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW = 0x40000000
	// Position of LP_ANA_BOD_MODE0_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_BOD_MODE0_INT_RAW_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_INT_RAW field.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_BOD_MODE0_INT_RAW_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_INT_RAW.
	LP_ANA_PERI_LP_ANA_INT_RAW_LP_ANA_BOD_MODE0_INT_RAW = 0x80000000

	// LP_ANA_INT_ST: need_des
	// Position of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_Pos = 0x1b
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_Msk = 0x8000000
	// Bit LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST = 0x8000000
	// Position of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_Pos = 0x1c
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_Msk = 0x10000000
	// Bit LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST = 0x10000000
	// Position of LP_ANA_VDDBAT_UPVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_Pos = 0x1d
	// Bit mask of LP_ANA_VDDBAT_UPVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_Msk = 0x20000000
	// Bit LP_ANA_VDDBAT_UPVOLTAGE_INT_ST.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_UPVOLTAGE_INT_ST = 0x20000000
	// Position of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_Pos = 0x1e
	// Bit mask of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_Msk = 0x40000000
	// Bit LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST = 0x40000000
	// Position of LP_ANA_BOD_MODE0_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_BOD_MODE0_INT_ST_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_INT_ST field.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_BOD_MODE0_INT_ST_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_INT_ST.
	LP_ANA_PERI_LP_ANA_INT_ST_LP_ANA_BOD_MODE0_INT_ST = 0x80000000

	// LP_ANA_INT_ENA: need_des
	// Position of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_Pos = 0x1b
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_Msk = 0x8000000
	// Bit LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA = 0x8000000
	// Position of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_Pos = 0x1c
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_Msk = 0x10000000
	// Bit LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA = 0x10000000
	// Position of LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_Pos = 0x1d
	// Bit mask of LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_Msk = 0x20000000
	// Bit LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA = 0x20000000
	// Position of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_Pos = 0x1e
	// Bit mask of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_Msk = 0x40000000
	// Bit LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA = 0x40000000
	// Position of LP_ANA_BOD_MODE0_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_BOD_MODE0_INT_ENA_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_INT_ENA field.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_BOD_MODE0_INT_ENA_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_INT_ENA.
	LP_ANA_PERI_LP_ANA_INT_ENA_LP_ANA_BOD_MODE0_INT_ENA = 0x80000000

	// LP_ANA_INT_CLR: need_des
	// Position of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_Pos = 0x1b
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_Msk = 0x8000000
	// Bit LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR = 0x8000000
	// Position of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_Pos = 0x1c
	// Bit mask of LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_Msk = 0x10000000
	// Bit LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR = 0x10000000
	// Position of LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_Pos = 0x1d
	// Bit mask of LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_Msk = 0x20000000
	// Bit LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR = 0x20000000
	// Position of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_Pos = 0x1e
	// Bit mask of LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_Msk = 0x40000000
	// Bit LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR = 0x40000000
	// Position of LP_ANA_BOD_MODE0_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_BOD_MODE0_INT_CLR_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_INT_CLR field.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_BOD_MODE0_INT_CLR_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_INT_CLR.
	LP_ANA_PERI_LP_ANA_INT_CLR_LP_ANA_BOD_MODE0_INT_CLR = 0x80000000

	// LP_ANA_LP_INT_RAW: need_des
	// Position of LP_ANA_BOD_MODE0_LP_INT_RAW field.
	LP_ANA_PERI_LP_ANA_LP_INT_RAW_LP_ANA_BOD_MODE0_LP_INT_RAW_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_LP_INT_RAW field.
	LP_ANA_PERI_LP_ANA_LP_INT_RAW_LP_ANA_BOD_MODE0_LP_INT_RAW_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_LP_INT_RAW.
	LP_ANA_PERI_LP_ANA_LP_INT_RAW_LP_ANA_BOD_MODE0_LP_INT_RAW = 0x80000000

	// LP_ANA_LP_INT_ST: need_des
	// Position of LP_ANA_BOD_MODE0_LP_INT_ST field.
	LP_ANA_PERI_LP_ANA_LP_INT_ST_LP_ANA_BOD_MODE0_LP_INT_ST_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_LP_INT_ST field.
	LP_ANA_PERI_LP_ANA_LP_INT_ST_LP_ANA_BOD_MODE0_LP_INT_ST_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_LP_INT_ST.
	LP_ANA_PERI_LP_ANA_LP_INT_ST_LP_ANA_BOD_MODE0_LP_INT_ST = 0x80000000

	// LP_ANA_LP_INT_ENA: need_des
	// Position of LP_ANA_BOD_MODE0_LP_INT_ENA field.
	LP_ANA_PERI_LP_ANA_LP_INT_ENA_LP_ANA_BOD_MODE0_LP_INT_ENA_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_LP_INT_ENA field.
	LP_ANA_PERI_LP_ANA_LP_INT_ENA_LP_ANA_BOD_MODE0_LP_INT_ENA_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_LP_INT_ENA.
	LP_ANA_PERI_LP_ANA_LP_INT_ENA_LP_ANA_BOD_MODE0_LP_INT_ENA = 0x80000000

	// LP_ANA_LP_INT_CLR: need_des
	// Position of LP_ANA_BOD_MODE0_LP_INT_CLR field.
	LP_ANA_PERI_LP_ANA_LP_INT_CLR_LP_ANA_BOD_MODE0_LP_INT_CLR_Pos = 0x1f
	// Bit mask of LP_ANA_BOD_MODE0_LP_INT_CLR field.
	LP_ANA_PERI_LP_ANA_LP_INT_CLR_LP_ANA_BOD_MODE0_LP_INT_CLR_Msk = 0x80000000
	// Bit LP_ANA_BOD_MODE0_LP_INT_CLR.
	LP_ANA_PERI_LP_ANA_LP_INT_CLR_LP_ANA_BOD_MODE0_LP_INT_CLR = 0x80000000

	// LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM: need_des
	// Position of LP_ANA_TOUCH_APPROACH_MEAS_NUM2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM2_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_APPROACH_MEAS_NUM2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM2_Msk = 0x3ff
	// Position of LP_ANA_TOUCH_APPROACH_MEAS_NUM1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM1_Pos = 0xa
	// Bit mask of LP_ANA_TOUCH_APPROACH_MEAS_NUM1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM1_Msk = 0xffc00
	// Position of LP_ANA_TOUCH_APPROACH_MEAS_NUM0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM0_Pos = 0x14
	// Bit mask of LP_ANA_TOUCH_APPROACH_MEAS_NUM0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_LP_ANA_TOUCH_APPROACH_MEAS_NUM0_Msk = 0x3ff00000

	// LP_ANA_TOUCH_SCAN_CTRL1: need_des
	// Position of LP_ANA_TOUCH_SHIELD_PAD_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SHIELD_PAD_EN_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_SHIELD_PAD_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SHIELD_PAD_EN_Msk = 0x1
	// Bit LP_ANA_TOUCH_SHIELD_PAD_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SHIELD_PAD_EN = 0x1
	// Position of LP_ANA_TOUCH_INACTIVE_CONNECTION field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_INACTIVE_CONNECTION_Pos = 0x1
	// Bit mask of LP_ANA_TOUCH_INACTIVE_CONNECTION field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_INACTIVE_CONNECTION_Msk = 0x2
	// Bit LP_ANA_TOUCH_INACTIVE_CONNECTION.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_INACTIVE_CONNECTION = 0x2
	// Position of LP_ANA_TOUCH_SCAN_PAD_MAP field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SCAN_PAD_MAP_Pos = 0x2
	// Bit mask of LP_ANA_TOUCH_SCAN_PAD_MAP field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_SCAN_PAD_MAP_Msk = 0x1fffc
	// Position of LP_ANA_TOUCH_XPD_WAIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_XPD_WAIT_Pos = 0x11
	// Bit mask of LP_ANA_TOUCH_XPD_WAIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL1_LP_ANA_TOUCH_XPD_WAIT_Msk = 0xfffe0000

	// LP_ANA_TOUCH_SCAN_CTRL2: need_des
	// Position of LP_ANA_TOUCH_TIMEOUT_NUM field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_NUM_Pos = 0x6
	// Bit mask of LP_ANA_TOUCH_TIMEOUT_NUM field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_NUM_Msk = 0x3fffc0
	// Position of LP_ANA_TOUCH_TIMEOUT_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_EN_Pos = 0x16
	// Bit mask of LP_ANA_TOUCH_TIMEOUT_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_EN_Msk = 0x400000
	// Bit LP_ANA_TOUCH_TIMEOUT_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_TIMEOUT_EN = 0x400000
	// Position of LP_ANA_TOUCH_OUT_RING field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_OUT_RING_Pos = 0x17
	// Bit mask of LP_ANA_TOUCH_OUT_RING field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_TOUCH_OUT_RING_Msk = 0x7800000
	// Position of LP_ANA_FREQ_SCAN_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_EN_Pos = 0x1b
	// Bit mask of LP_ANA_FREQ_SCAN_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_EN_Msk = 0x8000000
	// Bit LP_ANA_FREQ_SCAN_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_EN = 0x8000000
	// Position of LP_ANA_FREQ_SCAN_CNT_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_CNT_LIMIT_Pos = 0x1c
	// Bit mask of LP_ANA_FREQ_SCAN_CNT_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_SCAN_CTRL2_LP_ANA_FREQ_SCAN_CNT_LIMIT_Msk = 0x30000000

	// LP_ANA_TOUCH_WORK: need_des
	// Position of LP_ANA_DIV_NUM2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM2_Pos = 0x10
	// Bit mask of LP_ANA_DIV_NUM2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM2_Msk = 0x70000
	// Position of LP_ANA_DIV_NUM1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM1_Pos = 0x13
	// Bit mask of LP_ANA_DIV_NUM1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM1_Msk = 0x380000
	// Position of LP_ANA_DIV_NUM0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM0_Pos = 0x16
	// Bit mask of LP_ANA_DIV_NUM0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_DIV_NUM0_Msk = 0x1c00000
	// Position of LP_ANA_TOUCH_OUT_SEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_SEL_Pos = 0x19
	// Bit mask of LP_ANA_TOUCH_OUT_SEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_SEL_Msk = 0x2000000
	// Bit LP_ANA_TOUCH_OUT_SEL.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_SEL = 0x2000000
	// Position of LP_ANA_TOUCH_OUT_RESET field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_RESET_Pos = 0x1a
	// Bit mask of LP_ANA_TOUCH_OUT_RESET field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_RESET_Msk = 0x4000000
	// Bit LP_ANA_TOUCH_OUT_RESET.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_RESET = 0x4000000
	// Position of LP_ANA_TOUCH_OUT_GATE field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_GATE_Pos = 0x1b
	// Bit mask of LP_ANA_TOUCH_OUT_GATE field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_GATE_Msk = 0x8000000
	// Bit LP_ANA_TOUCH_OUT_GATE.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_LP_ANA_TOUCH_OUT_GATE = 0x8000000

	// LP_ANA_TOUCH_WORK_MEAS_NUM: need_des
	// Position of LP_ANA_TOUCH_MEAS_NUM2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM2_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_MEAS_NUM2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM2_Msk = 0x3ff
	// Position of LP_ANA_TOUCH_MEAS_NUM1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM1_Pos = 0xa
	// Bit mask of LP_ANA_TOUCH_MEAS_NUM1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM1_Msk = 0xffc00
	// Position of LP_ANA_TOUCH_MEAS_NUM0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM0_Pos = 0x14
	// Bit mask of LP_ANA_TOUCH_MEAS_NUM0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_WORK_MEAS_NUM_LP_ANA_TOUCH_MEAS_NUM0_Msk = 0x3ff00000

	// LP_ANA_TOUCH_FILTER1: need_des
	// Position of LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_Msk = 0x1
	// Bit LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN = 0x1
	// Position of LP_ANA_TOUCH_HYSTERESIS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_HYSTERESIS_Pos = 0x1
	// Bit mask of LP_ANA_TOUCH_HYSTERESIS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_HYSTERESIS_Msk = 0x6
	// Position of LP_ANA_TOUCH_NEG_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_THRES_Pos = 0x3
	// Bit mask of LP_ANA_TOUCH_NEG_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_THRES_Msk = 0x18
	// Position of LP_ANA_TOUCH_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NOISE_THRES_Pos = 0x5
	// Bit mask of LP_ANA_TOUCH_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NOISE_THRES_Msk = 0x60
	// Position of LP_ANA_TOUCH_SMOOTH_LVL field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_SMOOTH_LVL_Pos = 0x7
	// Bit mask of LP_ANA_TOUCH_SMOOTH_LVL field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_SMOOTH_LVL_Msk = 0x180
	// Position of LP_ANA_TOUCH_JITTER_STEP field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_JITTER_STEP_Pos = 0x9
	// Bit mask of LP_ANA_TOUCH_JITTER_STEP field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_JITTER_STEP_Msk = 0x1e00
	// Position of LP_ANA_TOUCH_FILTER_MODE field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_MODE_Pos = 0xd
	// Bit mask of LP_ANA_TOUCH_FILTER_MODE field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_MODE_Msk = 0xe000
	// Position of LP_ANA_TOUCH_FILTER_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_EN_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_FILTER_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_EN_Msk = 0x10000
	// Bit LP_ANA_TOUCH_FILTER_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_FILTER_EN = 0x10000
	// Position of LP_ANA_TOUCH_NEG_NOISE_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_LIMIT_Pos = 0x11
	// Bit mask of LP_ANA_TOUCH_NEG_NOISE_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_NEG_NOISE_LIMIT_Msk = 0x1e0000
	// Position of LP_ANA_TOUCH_APPROACH_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_APPROACH_LIMIT_Pos = 0x15
	// Bit mask of LP_ANA_TOUCH_APPROACH_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_APPROACH_LIMIT_Msk = 0x1fe00000
	// Position of LP_ANA_TOUCH_DEBOUNCE_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_DEBOUNCE_LIMIT_Pos = 0x1d
	// Bit mask of LP_ANA_TOUCH_DEBOUNCE_LIMIT field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER1_LP_ANA_TOUCH_DEBOUNCE_LIMIT_Msk = 0xe0000000

	// LP_ANA_TOUCH_FILTER2: need_des
	// Position of LP_ANA_TOUCH_OUTEN field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_OUTEN_Pos = 0xf
	// Bit mask of LP_ANA_TOUCH_OUTEN field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_OUTEN_Msk = 0x3fff8000
	// Position of LP_ANA_TOUCH_BYPASS_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NOISE_THRES_Pos = 0x1e
	// Bit mask of LP_ANA_TOUCH_BYPASS_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NOISE_THRES_Msk = 0x40000000
	// Bit LP_ANA_TOUCH_BYPASS_NOISE_THRES.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NOISE_THRES = 0x40000000
	// Position of LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_Pos = 0x1f
	// Bit mask of LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_Msk = 0x80000000
	// Bit LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER2_LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES = 0x80000000

	// LP_ANA_TOUCH_FILTER3: need_des
	// Position of LP_ANA_TOUCH_BASELINE_SW field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_BASELINE_SW_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_BASELINE_SW field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_BASELINE_SW_Msk = 0xffff
	// Position of LP_ANA_TOUCH_UPDATE_BASELINE_SW field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_UPDATE_BASELINE_SW_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_UPDATE_BASELINE_SW field.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_UPDATE_BASELINE_SW_Msk = 0x10000
	// Bit LP_ANA_TOUCH_UPDATE_BASELINE_SW.
	LP_ANA_PERI_LP_ANA_TOUCH_FILTER3_LP_ANA_TOUCH_UPDATE_BASELINE_SW = 0x10000

	// LP_ANA_TOUCH_SLP0: need_des
	// Position of LP_ANA_TOUCH_SLP_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_TH0_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_SLP_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_TH0_Msk = 0xffff
	// Position of LP_ANA_TOUCH_SLP_CHANNEL_CLR field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_CHANNEL_CLR_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_SLP_CHANNEL_CLR field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_CHANNEL_CLR_Msk = 0x10000
	// Bit LP_ANA_TOUCH_SLP_CHANNEL_CLR.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_CHANNEL_CLR = 0x10000
	// Position of LP_ANA_TOUCH_SLP_PAD field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_PAD_Pos = 0x11
	// Bit mask of LP_ANA_TOUCH_SLP_PAD field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP0_LP_ANA_TOUCH_SLP_PAD_Msk = 0x1e0000

	// LP_ANA_TOUCH_SLP1: need_des
	// Position of LP_ANA_TOUCH_SLP_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH2_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_SLP_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH2_Msk = 0xffff
	// Position of LP_ANA_TOUCH_SLP_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_SLP_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_SLP1_LP_ANA_TOUCH_SLP_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_CLR: need_des
	// Position of LP_ANA_TOUCH_CHANNEL_CLR field.
	LP_ANA_PERI_LP_ANA_TOUCH_CLR_LP_ANA_TOUCH_CHANNEL_CLR_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_CHANNEL_CLR field.
	LP_ANA_PERI_LP_ANA_TOUCH_CLR_LP_ANA_TOUCH_CHANNEL_CLR_Msk = 0x7fff
	// Position of LP_ANA_TOUCH_STATUS_CLR field.
	LP_ANA_PERI_LP_ANA_TOUCH_CLR_LP_ANA_TOUCH_STATUS_CLR_Pos = 0xf
	// Bit mask of LP_ANA_TOUCH_STATUS_CLR field.
	LP_ANA_PERI_LP_ANA_TOUCH_CLR_LP_ANA_TOUCH_STATUS_CLR_Msk = 0x8000
	// Bit LP_ANA_TOUCH_STATUS_CLR.
	LP_ANA_PERI_LP_ANA_TOUCH_CLR_LP_ANA_TOUCH_STATUS_CLR = 0x8000

	// LP_ANA_TOUCH_APPROACH: need_des
	// Position of PAD0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_PAD0_Pos = 0x0
	// Bit mask of PAD0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_PAD0_Msk = 0xf
	// Position of PAD1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_PAD1_Pos = 0x4
	// Bit mask of PAD1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_PAD1_Msk = 0xf0
	// Position of PAD2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_PAD2_Pos = 0x8
	// Bit mask of PAD2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_PAD2_Msk = 0xf00
	// Position of LP_ANA_TOUCH_SLP_APPROACH_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_LP_ANA_TOUCH_SLP_APPROACH_EN_Pos = 0xc
	// Bit mask of LP_ANA_TOUCH_SLP_APPROACH_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_LP_ANA_TOUCH_SLP_APPROACH_EN_Msk = 0x1000
	// Bit LP_ANA_TOUCH_SLP_APPROACH_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_APPROACH_LP_ANA_TOUCH_SLP_APPROACH_EN = 0x1000

	// LP_ANA_TOUCH_FREQ0_SCAN_PARA: need_des
	// Position of LP_ANA_TOUCH_FREQ0_DCAP_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DCAP_LPF_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_FREQ0_DCAP_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DCAP_LPF_Msk = 0x7f
	// Position of LP_ANA_TOUCH_FREQ0_DRES_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRES_LPF_Pos = 0x7
	// Bit mask of LP_ANA_TOUCH_FREQ0_DRES_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRES_LPF_Msk = 0x180
	// Position of LP_ANA_TOUCH_FREQ0_DRV_LS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_LS_Pos = 0x9
	// Bit mask of LP_ANA_TOUCH_FREQ0_DRV_LS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_LS_Msk = 0x1e00
	// Position of LP_ANA_TOUCH_FREQ0_DRV_HS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_HS_Pos = 0xd
	// Bit mask of LP_ANA_TOUCH_FREQ0_DRV_HS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DRV_HS_Msk = 0x3e000
	// Position of LP_ANA_TOUCH_FREQ0_DBIAS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DBIAS_Pos = 0x12
	// Bit mask of LP_ANA_TOUCH_FREQ0_DBIAS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ0_SCAN_PARA_LP_ANA_TOUCH_FREQ0_DBIAS_Msk = 0x7c0000

	// LP_ANA_TOUCH_FREQ1_SCAN_PARA: need_des
	// Position of LP_ANA_TOUCH_FREQ1_DCAP_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DCAP_LPF_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_FREQ1_DCAP_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DCAP_LPF_Msk = 0x7f
	// Position of LP_ANA_TOUCH_FREQ1_DRES_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRES_LPF_Pos = 0x7
	// Bit mask of LP_ANA_TOUCH_FREQ1_DRES_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRES_LPF_Msk = 0x180
	// Position of LP_ANA_TOUCH_FREQ1_DRV_LS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_LS_Pos = 0x9
	// Bit mask of LP_ANA_TOUCH_FREQ1_DRV_LS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_LS_Msk = 0x1e00
	// Position of LP_ANA_TOUCH_FREQ1_DRV_HS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_HS_Pos = 0xd
	// Bit mask of LP_ANA_TOUCH_FREQ1_DRV_HS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DRV_HS_Msk = 0x3e000
	// Position of LP_ANA_TOUCH_FREQ1_DBIAS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DBIAS_Pos = 0x12
	// Bit mask of LP_ANA_TOUCH_FREQ1_DBIAS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ1_SCAN_PARA_LP_ANA_TOUCH_FREQ1_DBIAS_Msk = 0x7c0000

	// LP_ANA_TOUCH_FREQ2_SCAN_PARA: need_des
	// Position of LP_ANA_TOUCH_FREQ2_DCAP_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DCAP_LPF_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_FREQ2_DCAP_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DCAP_LPF_Msk = 0x7f
	// Position of LP_ANA_TOUCH_FREQ2_DRES_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRES_LPF_Pos = 0x7
	// Bit mask of LP_ANA_TOUCH_FREQ2_DRES_LPF field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRES_LPF_Msk = 0x180
	// Position of LP_ANA_TOUCH_FREQ2_DRV_LS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_LS_Pos = 0x9
	// Bit mask of LP_ANA_TOUCH_FREQ2_DRV_LS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_LS_Msk = 0x1e00
	// Position of LP_ANA_TOUCH_FREQ2_DRV_HS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_HS_Pos = 0xd
	// Bit mask of LP_ANA_TOUCH_FREQ2_DRV_HS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DRV_HS_Msk = 0x3e000
	// Position of LP_ANA_TOUCH_FREQ2_DBIAS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DBIAS_Pos = 0x12
	// Bit mask of LP_ANA_TOUCH_FREQ2_DBIAS field.
	LP_ANA_PERI_LP_ANA_TOUCH_FREQ2_SCAN_PARA_LP_ANA_TOUCH_FREQ2_DBIAS_Msk = 0x7c0000

	// LP_ANA_TOUCH_ANA_PARA: need_des
	// Position of LP_ANA_TOUCH_TOUCH_BUF_DRV field.
	LP_ANA_PERI_LP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_BUF_DRV_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_TOUCH_BUF_DRV field.
	LP_ANA_PERI_LP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_BUF_DRV_Msk = 0x7
	// Position of LP_ANA_TOUCH_TOUCH_EN_CAL field.
	LP_ANA_PERI_LP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_EN_CAL_Pos = 0x3
	// Bit mask of LP_ANA_TOUCH_TOUCH_EN_CAL field.
	LP_ANA_PERI_LP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_EN_CAL_Msk = 0x8
	// Bit LP_ANA_TOUCH_TOUCH_EN_CAL.
	LP_ANA_PERI_LP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_EN_CAL = 0x8
	// Position of LP_ANA_TOUCH_TOUCH_DCAP_CAL field.
	LP_ANA_PERI_LP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_DCAP_CAL_Pos = 0x4
	// Bit mask of LP_ANA_TOUCH_TOUCH_DCAP_CAL field.
	LP_ANA_PERI_LP_ANA_TOUCH_ANA_PARA_LP_ANA_TOUCH_TOUCH_DCAP_CAL_Msk = 0x7f0

	// LP_ANA_TOUCH_MUX0: need_des
	// Position of LP_ANA_TOUCH_DATA_SEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DATA_SEL_Pos = 0x8
	// Bit mask of LP_ANA_TOUCH_DATA_SEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DATA_SEL_Msk = 0x300
	// Position of LP_ANA_TOUCH_FREQ_SEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FREQ_SEL_Pos = 0xa
	// Bit mask of LP_ANA_TOUCH_FREQ_SEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FREQ_SEL_Msk = 0xc00
	// Position of LP_ANA_TOUCH_BUFSEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_BUFSEL_Pos = 0xc
	// Bit mask of LP_ANA_TOUCH_BUFSEL field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_BUFSEL_Msk = 0x7fff000
	// Position of LP_ANA_TOUCH_DONE_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_EN_Pos = 0x1b
	// Bit mask of LP_ANA_TOUCH_DONE_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_EN_Msk = 0x8000000
	// Bit LP_ANA_TOUCH_DONE_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_EN = 0x8000000
	// Position of LP_ANA_TOUCH_DONE_FORCE field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_FORCE_Pos = 0x1c
	// Bit mask of LP_ANA_TOUCH_DONE_FORCE field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_FORCE_Msk = 0x10000000
	// Bit LP_ANA_TOUCH_DONE_FORCE.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_DONE_FORCE = 0x10000000
	// Position of LP_ANA_TOUCH_FSM_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FSM_EN_Pos = 0x1d
	// Bit mask of LP_ANA_TOUCH_FSM_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FSM_EN_Msk = 0x20000000
	// Bit LP_ANA_TOUCH_FSM_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_FSM_EN = 0x20000000
	// Position of LP_ANA_TOUCH_START_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_EN_Pos = 0x1e
	// Bit mask of LP_ANA_TOUCH_START_EN field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_EN_Msk = 0x40000000
	// Bit LP_ANA_TOUCH_START_EN.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_EN = 0x40000000
	// Position of LP_ANA_TOUCH_START_FORCE field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_FORCE_Pos = 0x1f
	// Bit mask of LP_ANA_TOUCH_START_FORCE field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_FORCE_Msk = 0x80000000
	// Bit LP_ANA_TOUCH_START_FORCE.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX0_LP_ANA_TOUCH_START_FORCE = 0x80000000

	// LP_ANA_TOUCH_MUX1: need_des
	// Position of LP_ANA_TOUCH_START field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_START_Pos = 0x0
	// Bit mask of LP_ANA_TOUCH_START field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_START_Msk = 0x7fff
	// Position of LP_ANA_TOUCH_XPD field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_XPD_Pos = 0xf
	// Bit mask of LP_ANA_TOUCH_XPD field.
	LP_ANA_PERI_LP_ANA_TOUCH_MUX1_LP_ANA_TOUCH_XPD_Msk = 0x3fff8000

	// LP_ANA_TOUCH_PAD0_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD0_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD0_TH0_LP_ANA_TOUCH_PAD0_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD0_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD0_TH0_LP_ANA_TOUCH_PAD0_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD0_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD0_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD0_TH1_LP_ANA_TOUCH_PAD0_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD0_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD0_TH1_LP_ANA_TOUCH_PAD0_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD0_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD0_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD0_TH2_LP_ANA_TOUCH_PAD0_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD0_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD0_TH2_LP_ANA_TOUCH_PAD0_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD1_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD1_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD1_TH0_LP_ANA_TOUCH_PAD1_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD1_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD1_TH0_LP_ANA_TOUCH_PAD1_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD1_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD1_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD1_TH1_LP_ANA_TOUCH_PAD1_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD1_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD1_TH1_LP_ANA_TOUCH_PAD1_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD1_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD1_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD1_TH2_LP_ANA_TOUCH_PAD1_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD1_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD1_TH2_LP_ANA_TOUCH_PAD1_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD2_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD2_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD2_TH0_LP_ANA_TOUCH_PAD2_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD2_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD2_TH0_LP_ANA_TOUCH_PAD2_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD2_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD2_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD2_TH1_LP_ANA_TOUCH_PAD2_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD2_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD2_TH1_LP_ANA_TOUCH_PAD2_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD2_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD2_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD2_TH2_LP_ANA_TOUCH_PAD2_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD2_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD2_TH2_LP_ANA_TOUCH_PAD2_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD3_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD3_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD3_TH0_LP_ANA_TOUCH_PAD3_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD3_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD3_TH0_LP_ANA_TOUCH_PAD3_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD3_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD3_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD3_TH1_LP_ANA_TOUCH_PAD3_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD3_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD3_TH1_LP_ANA_TOUCH_PAD3_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD3_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD3_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD3_TH2_LP_ANA_TOUCH_PAD3_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD3_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD3_TH2_LP_ANA_TOUCH_PAD3_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD4_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD4_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD4_TH0_LP_ANA_TOUCH_PAD4_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD4_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD4_TH0_LP_ANA_TOUCH_PAD4_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD4_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD4_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD4_TH1_LP_ANA_TOUCH_PAD4_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD4_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD4_TH1_LP_ANA_TOUCH_PAD4_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD4_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD4_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD4_TH2_LP_ANA_TOUCH_PAD4_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD4_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD4_TH2_LP_ANA_TOUCH_PAD4_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD5_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD5_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD5_TH0_LP_ANA_TOUCH_PAD5_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD5_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD5_TH0_LP_ANA_TOUCH_PAD5_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD5_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD5_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD5_TH1_LP_ANA_TOUCH_PAD5_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD5_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD5_TH1_LP_ANA_TOUCH_PAD5_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD5_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD5_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD5_TH2_LP_ANA_TOUCH_PAD5_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD5_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD5_TH2_LP_ANA_TOUCH_PAD5_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD6_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD6_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD6_TH0_LP_ANA_TOUCH_PAD6_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD6_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD6_TH0_LP_ANA_TOUCH_PAD6_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD6_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD6_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD6_TH1_LP_ANA_TOUCH_PAD6_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD6_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD6_TH1_LP_ANA_TOUCH_PAD6_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD6_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD6_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD6_TH2_LP_ANA_TOUCH_PAD6_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD6_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD6_TH2_LP_ANA_TOUCH_PAD6_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD7_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD7_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD7_TH0_LP_ANA_TOUCH_PAD7_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD7_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD7_TH0_LP_ANA_TOUCH_PAD7_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD7_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD7_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD7_TH1_LP_ANA_TOUCH_PAD7_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD7_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD7_TH1_LP_ANA_TOUCH_PAD7_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD7_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD7_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD7_TH2_LP_ANA_TOUCH_PAD7_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD7_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD7_TH2_LP_ANA_TOUCH_PAD7_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD8_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD8_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD8_TH0_LP_ANA_TOUCH_PAD8_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD8_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD8_TH0_LP_ANA_TOUCH_PAD8_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD8_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD8_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD8_TH1_LP_ANA_TOUCH_PAD8_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD8_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD8_TH1_LP_ANA_TOUCH_PAD8_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD8_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD8_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD8_TH2_LP_ANA_TOUCH_PAD8_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD8_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD8_TH2_LP_ANA_TOUCH_PAD8_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD9_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD9_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD9_TH0_LP_ANA_TOUCH_PAD9_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD9_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD9_TH0_LP_ANA_TOUCH_PAD9_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD9_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD9_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD9_TH1_LP_ANA_TOUCH_PAD9_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD9_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD9_TH1_LP_ANA_TOUCH_PAD9_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD9_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD9_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD9_TH2_LP_ANA_TOUCH_PAD9_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD9_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD9_TH2_LP_ANA_TOUCH_PAD9_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD10_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD10_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD10_TH0_LP_ANA_TOUCH_PAD10_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD10_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD10_TH0_LP_ANA_TOUCH_PAD10_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD10_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD10_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD10_TH1_LP_ANA_TOUCH_PAD10_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD10_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD10_TH1_LP_ANA_TOUCH_PAD10_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD10_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD10_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD10_TH2_LP_ANA_TOUCH_PAD10_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD10_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD10_TH2_LP_ANA_TOUCH_PAD10_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD11_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD11_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD11_TH0_LP_ANA_TOUCH_PAD11_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD11_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD11_TH0_LP_ANA_TOUCH_PAD11_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD11_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD11_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD11_TH1_LP_ANA_TOUCH_PAD11_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD11_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD11_TH1_LP_ANA_TOUCH_PAD11_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD11_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD11_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD11_TH2_LP_ANA_TOUCH_PAD11_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD11_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD11_TH2_LP_ANA_TOUCH_PAD11_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD12_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD12_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD12_TH0_LP_ANA_TOUCH_PAD12_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD12_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD12_TH0_LP_ANA_TOUCH_PAD12_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD12_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD12_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD12_TH1_LP_ANA_TOUCH_PAD12_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD12_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD12_TH1_LP_ANA_TOUCH_PAD12_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD12_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD12_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD12_TH2_LP_ANA_TOUCH_PAD12_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD12_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD12_TH2_LP_ANA_TOUCH_PAD12_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD13_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD13_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD13_TH0_LP_ANA_TOUCH_PAD13_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD13_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD13_TH0_LP_ANA_TOUCH_PAD13_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD13_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD13_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD13_TH1_LP_ANA_TOUCH_PAD13_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD13_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD13_TH1_LP_ANA_TOUCH_PAD13_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD13_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD13_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD13_TH2_LP_ANA_TOUCH_PAD13_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD13_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD13_TH2_LP_ANA_TOUCH_PAD13_TH2_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD14_TH0: need_des
	// Position of LP_ANA_TOUCH_PAD14_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD14_TH0_LP_ANA_TOUCH_PAD14_TH0_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD14_TH0 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD14_TH0_LP_ANA_TOUCH_PAD14_TH0_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD14_TH1: need_des
	// Position of LP_ANA_TOUCH_PAD14_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD14_TH1_LP_ANA_TOUCH_PAD14_TH1_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD14_TH1 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD14_TH1_LP_ANA_TOUCH_PAD14_TH1_Msk = 0xffff0000

	// LP_ANA_TOUCH_PAD14_TH2: need_des
	// Position of LP_ANA_TOUCH_PAD14_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD14_TH2_LP_ANA_TOUCH_PAD14_TH2_Pos = 0x10
	// Bit mask of LP_ANA_TOUCH_PAD14_TH2 field.
	LP_ANA_PERI_LP_ANA_TOUCH_PAD14_TH2_LP_ANA_TOUCH_PAD14_TH2_Msk = 0xffff0000

	// LP_ANA_DATE: need_des
	// Position of LP_ANA_LP_ANA_DATE field.
	LP_ANA_PERI_LP_ANA_DATE_LP_ANA_LP_ANA_DATE_Pos = 0x0
	// Bit mask of LP_ANA_LP_ANA_DATE field.
	LP_ANA_PERI_LP_ANA_DATE_LP_ANA_LP_ANA_DATE_Msk = 0x7fffffff
	// Position of LP_ANA_CLK_EN field.
	LP_ANA_PERI_LP_ANA_DATE_LP_ANA_CLK_EN_Pos = 0x1f
	// Bit mask of LP_ANA_CLK_EN field.
	LP_ANA_PERI_LP_ANA_DATE_LP_ANA_CLK_EN_Msk = 0x80000000
	// Bit LP_ANA_CLK_EN.
	LP_ANA_PERI_LP_ANA_DATE_LP_ANA_CLK_EN = 0x80000000
)

// Constants for LP_AON_CLKRST: LP_AON_CLKRST Peripheral
const (
	// LP_AONCLKRST_LP_CLK_CONF: need_des
	// Position of LP_AONCLKRST_SLOW_CLK_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_SLOW_CLK_SEL_Pos = 0x0
	// Bit mask of LP_AONCLKRST_SLOW_CLK_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_SLOW_CLK_SEL_Msk = 0x3
	// Position of LP_AONCLKRST_FAST_CLK_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_FAST_CLK_SEL_Pos = 0x2
	// Bit mask of LP_AONCLKRST_FAST_CLK_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_FAST_CLK_SEL_Msk = 0xc
	// Position of LP_AONCLKRST_LP_PERI_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_LP_PERI_DIV_NUM_Pos = 0x4
	// Bit mask of LP_AONCLKRST_LP_PERI_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_LP_PERI_DIV_NUM_Msk = 0x3f0
	// Position of LP_AONCLKRST_ANA_SEL_REF_PLL8M field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_ANA_SEL_REF_PLL8M_Pos = 0xa
	// Bit mask of LP_AONCLKRST_ANA_SEL_REF_PLL8M field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_ANA_SEL_REF_PLL8M_Msk = 0x400
	// Bit LP_AONCLKRST_ANA_SEL_REF_PLL8M.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_CONF_LP_AONCLKRST_ANA_SEL_REF_PLL8M = 0x400

	// LP_AONCLKRST_LP_CLK_PO_EN: need_des
	// Position of LP_AONCLKRST_CLK_CORE_EFUSE_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_CORE_EFUSE_OEN_Pos = 0x0
	// Bit mask of LP_AONCLKRST_CLK_CORE_EFUSE_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_CORE_EFUSE_OEN_Msk = 0x1
	// Bit LP_AONCLKRST_CLK_CORE_EFUSE_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_CORE_EFUSE_OEN = 0x1
	// Position of LP_AONCLKRST_CLK_LP_BUS_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_LP_BUS_OEN_Pos = 0x1
	// Bit mask of LP_AONCLKRST_CLK_LP_BUS_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_LP_BUS_OEN_Msk = 0x2
	// Bit LP_AONCLKRST_CLK_LP_BUS_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_LP_BUS_OEN = 0x2
	// Position of LP_AONCLKRST_CLK_AON_SLOW_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_SLOW_OEN_Pos = 0x2
	// Bit mask of LP_AONCLKRST_CLK_AON_SLOW_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_SLOW_OEN_Msk = 0x4
	// Bit LP_AONCLKRST_CLK_AON_SLOW_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_SLOW_OEN = 0x4
	// Position of LP_AONCLKRST_CLK_AON_FAST_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_FAST_OEN_Pos = 0x3
	// Bit mask of LP_AONCLKRST_CLK_AON_FAST_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_FAST_OEN_Msk = 0x8
	// Bit LP_AONCLKRST_CLK_AON_FAST_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_AON_FAST_OEN = 0x8
	// Position of LP_AONCLKRST_CLK_SLOW_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SLOW_OEN_Pos = 0x4
	// Bit mask of LP_AONCLKRST_CLK_SLOW_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SLOW_OEN_Msk = 0x10
	// Bit LP_AONCLKRST_CLK_SLOW_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SLOW_OEN = 0x10
	// Position of LP_AONCLKRST_CLK_FAST_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FAST_OEN_Pos = 0x5
	// Bit mask of LP_AONCLKRST_CLK_FAST_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FAST_OEN_Msk = 0x20
	// Bit LP_AONCLKRST_CLK_FAST_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FAST_OEN = 0x20
	// Position of LP_AONCLKRST_CLK_FOSC_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FOSC_OEN_Pos = 0x6
	// Bit mask of LP_AONCLKRST_CLK_FOSC_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FOSC_OEN_Msk = 0x40
	// Bit LP_AONCLKRST_CLK_FOSC_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_FOSC_OEN = 0x40
	// Position of LP_AONCLKRST_CLK_RC32K_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_RC32K_OEN_Pos = 0x7
	// Bit mask of LP_AONCLKRST_CLK_RC32K_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_RC32K_OEN_Msk = 0x80
	// Bit LP_AONCLKRST_CLK_RC32K_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_RC32K_OEN = 0x80
	// Position of LP_AONCLKRST_CLK_SXTAL_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SXTAL_OEN_Pos = 0x8
	// Bit mask of LP_AONCLKRST_CLK_SXTAL_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SXTAL_OEN_Msk = 0x100
	// Bit LP_AONCLKRST_CLK_SXTAL_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SXTAL_OEN = 0x100
	// Position of LP_AONCLKRST_CLK_SOSC_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SOSC_OEN_Pos = 0x9
	// Bit mask of LP_AONCLKRST_CLK_SOSC_OEN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SOSC_OEN_Msk = 0x200
	// Bit LP_AONCLKRST_CLK_SOSC_OEN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_PO_EN_LP_AONCLKRST_CLK_SOSC_OEN = 0x200

	// LP_AONCLKRST_LP_CLK_EN: need_des
	// Position of LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_Pos = 0x1a
	// Bit mask of LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_Msk = 0x4000000
	// Bit LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON = 0x4000000
	// Position of LP_AONCLKRST_CK_EN_LP_RAM field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_CK_EN_LP_RAM_Pos = 0x1b
	// Bit mask of LP_AONCLKRST_CK_EN_LP_RAM field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_CK_EN_LP_RAM_Msk = 0x8000000
	// Bit LP_AONCLKRST_CK_EN_LP_RAM.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_CK_EN_LP_RAM = 0x8000000
	// Position of LP_AONCLKRST_ETM_EVENT_TICK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_ETM_EVENT_TICK_EN_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_ETM_EVENT_TICK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_ETM_EVENT_TICK_EN_Msk = 0x10000000
	// Bit LP_AONCLKRST_ETM_EVENT_TICK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_ETM_EVENT_TICK_EN = 0x10000000
	// Position of LP_AONCLKRST_PLL8M_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_PLL8M_CLK_FORCE_ON_Pos = 0x1d
	// Bit mask of LP_AONCLKRST_PLL8M_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_PLL8M_CLK_FORCE_ON_Msk = 0x20000000
	// Bit LP_AONCLKRST_PLL8M_CLK_FORCE_ON.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_PLL8M_CLK_FORCE_ON = 0x20000000
	// Position of LP_AONCLKRST_XTAL_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_XTAL_CLK_FORCE_ON_Pos = 0x1e
	// Bit mask of LP_AONCLKRST_XTAL_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_XTAL_CLK_FORCE_ON_Msk = 0x40000000
	// Bit LP_AONCLKRST_XTAL_CLK_FORCE_ON.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_XTAL_CLK_FORCE_ON = 0x40000000
	// Position of LP_AONCLKRST_FOSC_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_FOSC_CLK_FORCE_ON_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_FOSC_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_FOSC_CLK_FORCE_ON_Msk = 0x80000000
	// Bit LP_AONCLKRST_FOSC_CLK_FORCE_ON.
	LP_AON_CLKRST_LP_AONCLKRST_LP_CLK_EN_LP_AONCLKRST_FOSC_CLK_FORCE_ON = 0x80000000

	// LP_AONCLKRST_LP_RST_EN: need_des
	// Position of LP_AONCLKRST_RST_EN_LP_HUK field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_HUK_Pos = 0x18
	// Bit mask of LP_AONCLKRST_RST_EN_LP_HUK field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_HUK_Msk = 0x1000000
	// Bit LP_AONCLKRST_RST_EN_LP_HUK.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_HUK = 0x1000000
	// Position of LP_AONCLKRST_RST_EN_LP_ANAPERI field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_ANAPERI_Pos = 0x19
	// Bit mask of LP_AONCLKRST_RST_EN_LP_ANAPERI field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_ANAPERI_Msk = 0x2000000
	// Bit LP_AONCLKRST_RST_EN_LP_ANAPERI.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_ANAPERI = 0x2000000
	// Position of LP_AONCLKRST_RST_EN_LP_WDT field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_WDT_Pos = 0x1a
	// Bit mask of LP_AONCLKRST_RST_EN_LP_WDT field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_WDT_Msk = 0x4000000
	// Bit LP_AONCLKRST_RST_EN_LP_WDT.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_WDT = 0x4000000
	// Position of LP_AONCLKRST_RST_EN_LP_TIMER field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_TIMER_Pos = 0x1b
	// Bit mask of LP_AONCLKRST_RST_EN_LP_TIMER field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_TIMER_Msk = 0x8000000
	// Bit LP_AONCLKRST_RST_EN_LP_TIMER.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_TIMER = 0x8000000
	// Position of LP_AONCLKRST_RST_EN_LP_RTC field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RTC_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_RST_EN_LP_RTC field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RTC_Msk = 0x10000000
	// Bit LP_AONCLKRST_RST_EN_LP_RTC.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RTC = 0x10000000
	// Position of LP_AONCLKRST_RST_EN_LP_MAILBOX field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_MAILBOX_Pos = 0x1d
	// Bit mask of LP_AONCLKRST_RST_EN_LP_MAILBOX field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_MAILBOX_Msk = 0x20000000
	// Bit LP_AONCLKRST_RST_EN_LP_MAILBOX.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_MAILBOX = 0x20000000
	// Position of LP_AONCLKRST_RST_EN_LP_AONEFUSEREG field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_Pos = 0x1e
	// Bit mask of LP_AONCLKRST_RST_EN_LP_AONEFUSEREG field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_Msk = 0x40000000
	// Bit LP_AONCLKRST_RST_EN_LP_AONEFUSEREG.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_AONEFUSEREG = 0x40000000
	// Position of LP_AONCLKRST_RST_EN_LP_RAM field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RAM_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_RST_EN_LP_RAM field.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RAM_Msk = 0x80000000
	// Bit LP_AONCLKRST_RST_EN_LP_RAM.
	LP_AON_CLKRST_LP_AONCLKRST_LP_RST_EN_LP_AONCLKRST_RST_EN_LP_RAM = 0x80000000

	// LP_AONCLKRST_RESET_CAUSE: need_des
	// Position of LP_AONCLKRST_LPCORE_RESET_CAUSE field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_Pos = 0x0
	// Bit mask of LP_AONCLKRST_LPCORE_RESET_CAUSE field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_Msk = 0x3f
	// Position of LP_AONCLKRST_LPCORE_RESET_FLAG field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_Pos = 0x6
	// Bit mask of LP_AONCLKRST_LPCORE_RESET_FLAG field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_Msk = 0x40
	// Bit LP_AONCLKRST_LPCORE_RESET_FLAG.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG = 0x40
	// Position of LP_AONCLKRST_HPCORE0_RESET_CAUSE field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_Pos = 0x7
	// Bit mask of LP_AONCLKRST_HPCORE0_RESET_CAUSE field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_Msk = 0x1f80
	// Position of LP_AONCLKRST_HPCORE0_RESET_FLAG field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_Pos = 0xd
	// Bit mask of LP_AONCLKRST_HPCORE0_RESET_FLAG field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_Msk = 0x2000
	// Bit LP_AONCLKRST_HPCORE0_RESET_FLAG.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG = 0x2000
	// Position of LP_AONCLKRST_HPCORE1_RESET_CAUSE field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_Pos = 0xe
	// Bit mask of LP_AONCLKRST_HPCORE1_RESET_CAUSE field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_Msk = 0xfc000
	// Position of LP_AONCLKRST_HPCORE1_RESET_FLAG field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_Pos = 0x14
	// Bit mask of LP_AONCLKRST_HPCORE1_RESET_FLAG field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_Msk = 0x100000
	// Bit LP_AONCLKRST_HPCORE1_RESET_FLAG.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG = 0x100000
	// Position of LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_Pos = 0x19
	// Bit mask of LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_Msk = 0x2000000
	// Bit LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK = 0x2000000
	// Position of LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_Pos = 0x1a
	// Bit mask of LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_Msk = 0x4000000
	// Bit LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR = 0x4000000
	// Position of LP_AONCLKRST_LPCORE_RESET_FLAG_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_Pos = 0x1b
	// Bit mask of LP_AONCLKRST_LPCORE_RESET_FLAG_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_Msk = 0x8000000
	// Bit LP_AONCLKRST_LPCORE_RESET_FLAG_CLR.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_LPCORE_RESET_FLAG_CLR = 0x8000000
	// Position of LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_Msk = 0x10000000
	// Bit LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR = 0x10000000
	// Position of LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_Pos = 0x1d
	// Bit mask of LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_Msk = 0x20000000
	// Bit LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR = 0x20000000
	// Position of LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_Pos = 0x1e
	// Bit mask of LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_Msk = 0x40000000
	// Bit LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR = 0x40000000
	// Position of LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR field.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_Msk = 0x80000000
	// Bit LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR.
	LP_AON_CLKRST_LP_AONCLKRST_RESET_CAUSE_LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR = 0x80000000

	// LP_AONCLKRST_HPCPU_RESET_CTRL0: need_des
	// Position of LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_Pos = 0x0
	// Bit mask of LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_Msk = 0x1
	// Bit LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN = 0x1
	// Position of LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_Pos = 0x1
	// Bit mask of LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_Msk = 0xe
	// Position of LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_Pos = 0x4
	// Bit mask of LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_Msk = 0x10
	// Bit LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN = 0x10
	// Position of LP_AONCLKRST_HPCORE0_STALL_WAIT field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_WAIT_Pos = 0x5
	// Bit mask of LP_AONCLKRST_HPCORE0_STALL_WAIT field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_WAIT_Msk = 0xfe0
	// Position of LP_AONCLKRST_HPCORE0_STALL_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_EN_Pos = 0xc
	// Bit mask of LP_AONCLKRST_HPCORE0_STALL_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_EN_Msk = 0x1000
	// Bit LP_AONCLKRST_HPCORE0_STALL_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STALL_EN = 0x1000
	// Position of LP_AONCLKRST_HPCORE0_SW_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_SW_RESET_Pos = 0xd
	// Bit mask of LP_AONCLKRST_HPCORE0_SW_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_SW_RESET_Msk = 0x2000
	// Bit LP_AONCLKRST_HPCORE0_SW_RESET.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_SW_RESET = 0x2000
	// Position of LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_Pos = 0xe
	// Bit mask of LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_Msk = 0x4000
	// Bit LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET = 0x4000
	// Position of LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_Pos = 0xf
	// Bit mask of LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_Msk = 0x8000
	// Bit LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL = 0x8000
	// Position of LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_Pos = 0x10
	// Bit mask of LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_Msk = 0x10000
	// Bit LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN = 0x10000
	// Position of LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_Pos = 0x11
	// Bit mask of LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_Msk = 0xe0000
	// Position of LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_Pos = 0x14
	// Bit mask of LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_Msk = 0x100000
	// Bit LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN = 0x100000
	// Position of LP_AONCLKRST_HPCORE1_STALL_WAIT field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_WAIT_Pos = 0x15
	// Bit mask of LP_AONCLKRST_HPCORE1_STALL_WAIT field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_WAIT_Msk = 0xfe00000
	// Position of LP_AONCLKRST_HPCORE1_STALL_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_EN_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_HPCORE1_STALL_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_EN_Msk = 0x10000000
	// Bit LP_AONCLKRST_HPCORE1_STALL_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STALL_EN = 0x10000000
	// Position of LP_AONCLKRST_HPCORE1_SW_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_SW_RESET_Pos = 0x1d
	// Bit mask of LP_AONCLKRST_HPCORE1_SW_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_SW_RESET_Msk = 0x20000000
	// Bit LP_AONCLKRST_HPCORE1_SW_RESET.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_SW_RESET = 0x20000000
	// Position of LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_Pos = 0x1e
	// Bit mask of LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_Msk = 0x40000000
	// Bit LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET = 0x40000000
	// Position of LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_Msk = 0x80000000
	// Bit LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL0_LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL = 0x80000000

	// LP_AONCLKRST_HPCPU_RESET_CTRL1: need_des
	// Position of LP_AONCLKRST_HPCORE0_SW_STALL_CODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE0_SW_STALL_CODE_Pos = 0x10
	// Bit mask of LP_AONCLKRST_HPCORE0_SW_STALL_CODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE0_SW_STALL_CODE_Msk = 0xff0000
	// Position of LP_AONCLKRST_HPCORE1_SW_STALL_CODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE1_SW_STALL_CODE_Pos = 0x18
	// Bit mask of LP_AONCLKRST_HPCORE1_SW_STALL_CODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HPCPU_RESET_CTRL1_LP_AONCLKRST_HPCORE1_SW_STALL_CODE_Msk = 0xff000000

	// LP_AONCLKRST_FOSC_CNTL: need_des
	// Position of LP_AONCLKRST_FOSC_DFREQ field.
	LP_AON_CLKRST_LP_AONCLKRST_FOSC_CNTL_LP_AONCLKRST_FOSC_DFREQ_Pos = 0x16
	// Bit mask of LP_AONCLKRST_FOSC_DFREQ field.
	LP_AON_CLKRST_LP_AONCLKRST_FOSC_CNTL_LP_AONCLKRST_FOSC_DFREQ_Msk = 0xffc00000

	// LP_AONCLKRST_RC32K_CNTL: need_des
	// Position of LP_AONCLKRST_RC32K_DFREQ field.
	LP_AON_CLKRST_LP_AONCLKRST_RC32K_CNTL_LP_AONCLKRST_RC32K_DFREQ_Pos = 0x0
	// Bit mask of LP_AONCLKRST_RC32K_DFREQ field.
	LP_AON_CLKRST_LP_AONCLKRST_RC32K_CNTL_LP_AONCLKRST_RC32K_DFREQ_Msk = 0xffffffff

	// LP_AONCLKRST_SOSC_CNTL: need_des
	// Position of LP_AONCLKRST_SOSC_DFREQ field.
	LP_AON_CLKRST_LP_AONCLKRST_SOSC_CNTL_LP_AONCLKRST_SOSC_DFREQ_Pos = 0x16
	// Bit mask of LP_AONCLKRST_SOSC_DFREQ field.
	LP_AON_CLKRST_LP_AONCLKRST_SOSC_CNTL_LP_AONCLKRST_SOSC_DFREQ_Msk = 0xffc00000

	// LP_AONCLKRST_CLK_TO_HP: need_des
	// Position of LP_AONCLKRST_ICG_HP_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_XTAL32K_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_ICG_HP_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_XTAL32K_Msk = 0x10000000
	// Bit LP_AONCLKRST_ICG_HP_XTAL32K.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_XTAL32K = 0x10000000
	// Position of LP_AONCLKRST_ICG_HP_SOSC field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_SOSC_Pos = 0x1d
	// Bit mask of LP_AONCLKRST_ICG_HP_SOSC field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_SOSC_Msk = 0x20000000
	// Bit LP_AONCLKRST_ICG_HP_SOSC.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_SOSC = 0x20000000
	// Position of LP_AONCLKRST_ICG_HP_OSC32K field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_OSC32K_Pos = 0x1e
	// Bit mask of LP_AONCLKRST_ICG_HP_OSC32K field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_OSC32K_Msk = 0x40000000
	// Bit LP_AONCLKRST_ICG_HP_OSC32K.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_OSC32K = 0x40000000
	// Position of LP_AONCLKRST_ICG_HP_FOSC field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_FOSC_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_ICG_HP_FOSC field.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_FOSC_Msk = 0x80000000
	// Bit LP_AONCLKRST_ICG_HP_FOSC.
	LP_AON_CLKRST_LP_AONCLKRST_CLK_TO_HP_LP_AONCLKRST_ICG_HP_FOSC = 0x80000000

	// LP_AONCLKRST_LPMEM_FORCE: need_des
	// Position of LP_AONCLKRST_LPMEM_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LPMEM_FORCE_LP_AONCLKRST_LPMEM_CLK_FORCE_ON_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_LPMEM_CLK_FORCE_ON field.
	LP_AON_CLKRST_LP_AONCLKRST_LPMEM_FORCE_LP_AONCLKRST_LPMEM_CLK_FORCE_ON_Msk = 0x80000000
	// Bit LP_AONCLKRST_LPMEM_CLK_FORCE_ON.
	LP_AON_CLKRST_LP_AONCLKRST_LPMEM_FORCE_LP_AONCLKRST_LPMEM_CLK_FORCE_ON = 0x80000000

	// LP_AONCLKRST_XTAL32K: need_des
	// Position of LP_AONCLKRST_DRES_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DRES_XTAL32K_Pos = 0x16
	// Bit mask of LP_AONCLKRST_DRES_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DRES_XTAL32K_Msk = 0x1c00000
	// Position of LP_AONCLKRST_DGM_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DGM_XTAL32K_Pos = 0x19
	// Bit mask of LP_AONCLKRST_DGM_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DGM_XTAL32K_Msk = 0xe000000
	// Position of LP_AONCLKRST_DBUF_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DBUF_XTAL32K_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_DBUF_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DBUF_XTAL32K_Msk = 0x10000000
	// Bit LP_AONCLKRST_DBUF_XTAL32K.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DBUF_XTAL32K = 0x10000000
	// Position of LP_AONCLKRST_DAC_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DAC_XTAL32K_Pos = 0x1d
	// Bit mask of LP_AONCLKRST_DAC_XTAL32K field.
	LP_AON_CLKRST_LP_AONCLKRST_XTAL32K_LP_AONCLKRST_DAC_XTAL32K_Msk = 0xe0000000

	// LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS: need_des
	// Position of LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS field.
	LP_AON_CLKRST_LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_Pos = 0x0
	// Bit mask of LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS field.
	LP_AON_CLKRST_LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_Msk = 0xffffffff

	// LP_AONCLKRST_HPSYS_0_RESET_BYPASS: need_des
	// Position of LP_AONCLKRST_HPSYS_0_RESET_BYPASS field.
	LP_AON_CLKRST_LP_AONCLKRST_HPSYS_0_RESET_BYPASS_LP_AONCLKRST_HPSYS_0_RESET_BYPASS_Pos = 0x0
	// Bit mask of LP_AONCLKRST_HPSYS_0_RESET_BYPASS field.
	LP_AON_CLKRST_LP_AONCLKRST_HPSYS_0_RESET_BYPASS_LP_AONCLKRST_HPSYS_0_RESET_BYPASS_Msk = 0xffffffff

	// LP_AONCLKRST_HPSYS_APM_RESET_BYPASS: need_des
	// Position of LP_AONCLKRST_HPSYS_APM_RESET_BYPASS field.
	LP_AON_CLKRST_LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_Pos = 0x0
	// Bit mask of LP_AONCLKRST_HPSYS_APM_RESET_BYPASS field.
	LP_AON_CLKRST_LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_Msk = 0xffffffff

	// LP_AONCLKRST_HP_CLK_CTRL: HP Clock Control Register.
	// Position of LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_Pos = 0x0
	// Bit mask of LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_Msk = 0x3
	// Position of LP_AONCLKRST_HP_ROOT_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_EN_Pos = 0x2
	// Bit mask of LP_AONCLKRST_HP_ROOT_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_EN_Msk = 0x4
	// Bit LP_AONCLKRST_HP_ROOT_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_ROOT_CLK_EN = 0x4
	// Position of LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_Pos = 0x3
	// Bit mask of LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_Msk = 0x8
	// Bit LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN = 0x8
	// Position of LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_Pos = 0x4
	// Bit mask of LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_Msk = 0x10
	// Bit LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN = 0x10
	// Position of LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_Pos = 0x5
	// Bit mask of LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_Msk = 0x20
	// Bit LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN = 0x20
	// Position of LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_Pos = 0x6
	// Bit mask of LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_Msk = 0x40
	// Bit LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN = 0x40
	// Position of LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_Pos = 0x7
	// Bit mask of LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_Msk = 0x80
	// Bit LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN = 0x80
	// Position of LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_Pos = 0x8
	// Bit mask of LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_Msk = 0x100
	// Bit LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN = 0x100
	// Position of LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_Pos = 0x9
	// Bit mask of LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_Msk = 0x200
	// Bit LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN = 0x200
	// Position of LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_Pos = 0xa
	// Bit mask of LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_Msk = 0x400
	// Bit LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN = 0x400
	// Position of LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_Pos = 0xb
	// Bit mask of LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_Msk = 0x800
	// Bit LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN = 0x800
	// Position of LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_Pos = 0xc
	// Bit mask of LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_Msk = 0x1000
	// Bit LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN = 0x1000
	// Position of LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_Pos = 0xd
	// Bit mask of LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_Msk = 0x2000
	// Bit LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN = 0x2000
	// Position of LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_Pos = 0xe
	// Bit mask of LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_Msk = 0x4000
	// Bit LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN = 0x4000
	// Position of LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_Pos = 0xf
	// Bit mask of LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_Msk = 0x8000
	// Bit LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN = 0x8000
	// Position of LP_AONCLKRST_HP_XTAL_32K_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_32K_CLK_EN_Pos = 0x10
	// Bit mask of LP_AONCLKRST_HP_XTAL_32K_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_32K_CLK_EN_Msk = 0x10000
	// Bit LP_AONCLKRST_HP_XTAL_32K_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_32K_CLK_EN = 0x10000
	// Position of LP_AONCLKRST_HP_RC_32K_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_RC_32K_CLK_EN_Pos = 0x11
	// Bit mask of LP_AONCLKRST_HP_RC_32K_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_RC_32K_CLK_EN_Msk = 0x20000
	// Bit LP_AONCLKRST_HP_RC_32K_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_RC_32K_CLK_EN = 0x20000
	// Position of LP_AONCLKRST_HP_SOSC_150K_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SOSC_150K_CLK_EN_Pos = 0x12
	// Bit mask of LP_AONCLKRST_HP_SOSC_150K_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SOSC_150K_CLK_EN_Msk = 0x40000
	// Bit LP_AONCLKRST_HP_SOSC_150K_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SOSC_150K_CLK_EN = 0x40000
	// Position of LP_AONCLKRST_HP_PLL_8M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PLL_8M_CLK_EN_Pos = 0x13
	// Bit mask of LP_AONCLKRST_HP_PLL_8M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PLL_8M_CLK_EN_Msk = 0x80000
	// Bit LP_AONCLKRST_HP_PLL_8M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_PLL_8M_CLK_EN = 0x80000
	// Position of LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_Pos = 0x14
	// Bit mask of LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_Msk = 0x100000
	// Bit LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN = 0x100000
	// Position of LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_Pos = 0x15
	// Bit mask of LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_Msk = 0x200000
	// Bit LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN = 0x200000
	// Position of LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_Pos = 0x16
	// Bit mask of LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_Msk = 0x400000
	// Bit LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN = 0x400000
	// Position of LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_Pos = 0x17
	// Bit mask of LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_Msk = 0x800000
	// Bit LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN = 0x800000
	// Position of LP_AONCLKRST_HP_FOSC_20M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_FOSC_20M_CLK_EN_Pos = 0x18
	// Bit mask of LP_AONCLKRST_HP_FOSC_20M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_FOSC_20M_CLK_EN_Msk = 0x1000000
	// Bit LP_AONCLKRST_HP_FOSC_20M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_FOSC_20M_CLK_EN = 0x1000000
	// Position of LP_AONCLKRST_HP_XTAL_40M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_40M_CLK_EN_Pos = 0x19
	// Bit mask of LP_AONCLKRST_HP_XTAL_40M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_40M_CLK_EN_Msk = 0x2000000
	// Bit LP_AONCLKRST_HP_XTAL_40M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_XTAL_40M_CLK_EN = 0x2000000
	// Position of LP_AONCLKRST_HP_CPLL_400M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_CPLL_400M_CLK_EN_Pos = 0x1a
	// Bit mask of LP_AONCLKRST_HP_CPLL_400M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_CPLL_400M_CLK_EN_Msk = 0x4000000
	// Bit LP_AONCLKRST_HP_CPLL_400M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_CPLL_400M_CLK_EN = 0x4000000
	// Position of LP_AONCLKRST_HP_SPLL_480M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SPLL_480M_CLK_EN_Pos = 0x1b
	// Bit mask of LP_AONCLKRST_HP_SPLL_480M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SPLL_480M_CLK_EN_Msk = 0x8000000
	// Bit LP_AONCLKRST_HP_SPLL_480M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_SPLL_480M_CLK_EN = 0x8000000
	// Position of LP_AONCLKRST_HP_MPLL_500M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_MPLL_500M_CLK_EN_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_HP_MPLL_500M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_MPLL_500M_CLK_EN_Msk = 0x10000000
	// Bit LP_AONCLKRST_HP_MPLL_500M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_CLK_CTRL_LP_AONCLKRST_HP_MPLL_500M_CLK_EN = 0x10000000

	// LP_AONCLKRST_HP_USB_CLKRST_CTRL0: HP USB Clock Reset Control Register.
	// Position of LP_AONCLKRST_USB_OTG20_SLEEP_MODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_SLEEP_MODE_Pos = 0x0
	// Bit mask of LP_AONCLKRST_USB_OTG20_SLEEP_MODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_SLEEP_MODE_Msk = 0x1
	// Bit LP_AONCLKRST_USB_OTG20_SLEEP_MODE.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_SLEEP_MODE = 0x1
	// Position of LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_Pos = 0x1
	// Bit mask of LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_Msk = 0x2
	// Bit LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN = 0x2
	// Position of LP_AONCLKRST_USB_OTG11_SLEEP_MODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_SLEEP_MODE_Pos = 0x2
	// Bit mask of LP_AONCLKRST_USB_OTG11_SLEEP_MODE field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_SLEEP_MODE_Msk = 0x4
	// Bit LP_AONCLKRST_USB_OTG11_SLEEP_MODE.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_SLEEP_MODE = 0x4
	// Position of LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_Pos = 0x3
	// Bit mask of LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_Msk = 0x8
	// Bit LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN = 0x8
	// Position of LP_AONCLKRST_USB_OTG11_48M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_48M_CLK_EN_Pos = 0x4
	// Bit mask of LP_AONCLKRST_USB_OTG11_48M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_48M_CLK_EN_Msk = 0x10
	// Bit LP_AONCLKRST_USB_OTG11_48M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_OTG11_48M_CLK_EN = 0x10
	// Position of LP_AONCLKRST_USB_DEVICE_48M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_Pos = 0x5
	// Bit mask of LP_AONCLKRST_USB_DEVICE_48M_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_Msk = 0x20
	// Bit LP_AONCLKRST_USB_DEVICE_48M_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_DEVICE_48M_CLK_EN = 0x20
	// Position of LP_AONCLKRST_USB_48M_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_48M_DIV_NUM_Pos = 0x6
	// Bit mask of LP_AONCLKRST_USB_48M_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_48M_DIV_NUM_Msk = 0x3fc0
	// Position of LP_AONCLKRST_USB_25M_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_25M_DIV_NUM_Pos = 0xe
	// Bit mask of LP_AONCLKRST_USB_25M_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_25M_DIV_NUM_Msk = 0x3fc000
	// Position of LP_AONCLKRST_USB_12M_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_12M_DIV_NUM_Pos = 0x16
	// Bit mask of LP_AONCLKRST_USB_12M_DIV_NUM field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL0_LP_AONCLKRST_USB_12M_DIV_NUM_Msk = 0x3fc00000

	// LP_AONCLKRST_HP_USB_CLKRST_CTRL1: HP USB Clock Reset Control Register.
	// Position of LP_AONCLKRST_RST_EN_USB_OTG20_ADP field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_ADP_Pos = 0x0
	// Bit mask of LP_AONCLKRST_RST_EN_USB_OTG20_ADP field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_ADP_Msk = 0x1
	// Bit LP_AONCLKRST_RST_EN_USB_OTG20_ADP.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_ADP = 0x1
	// Position of LP_AONCLKRST_RST_EN_USB_OTG20_PHY field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_PHY_Pos = 0x1
	// Bit mask of LP_AONCLKRST_RST_EN_USB_OTG20_PHY field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_PHY_Msk = 0x2
	// Bit LP_AONCLKRST_RST_EN_USB_OTG20_PHY.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_PHY = 0x2
	// Position of LP_AONCLKRST_RST_EN_USB_OTG20 field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_Pos = 0x2
	// Bit mask of LP_AONCLKRST_RST_EN_USB_OTG20 field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20_Msk = 0x4
	// Bit LP_AONCLKRST_RST_EN_USB_OTG20.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG20 = 0x4
	// Position of LP_AONCLKRST_RST_EN_USB_OTG11 field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG11_Pos = 0x3
	// Bit mask of LP_AONCLKRST_RST_EN_USB_OTG11 field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG11_Msk = 0x8
	// Bit LP_AONCLKRST_RST_EN_USB_OTG11.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_OTG11 = 0x8
	// Position of LP_AONCLKRST_RST_EN_USB_DEVICE field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_DEVICE_Pos = 0x4
	// Bit mask of LP_AONCLKRST_RST_EN_USB_DEVICE field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_DEVICE_Msk = 0x10
	// Bit LP_AONCLKRST_RST_EN_USB_DEVICE.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_RST_EN_USB_DEVICE = 0x10
	// Position of LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_Msk = 0x30000000
	// Position of LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_Pos = 0x1e
	// Bit mask of LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_Msk = 0x40000000
	// Bit LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN = 0x40000000
	// Position of LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_Msk = 0x80000000
	// Bit LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_HP_USB_CLKRST_CTRL1_LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN = 0x80000000

	// LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL: need_des
	// Position of LP_AONCLKRST_RST_EN_SDMMC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_SDMMC_Pos = 0x1c
	// Bit mask of LP_AONCLKRST_RST_EN_SDMMC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_SDMMC_Msk = 0x10000000
	// Bit LP_AONCLKRST_RST_EN_SDMMC.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_SDMMC = 0x10000000
	// Position of LP_AONCLKRST_FORCE_NORST_SDMMC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_SDMMC_Pos = 0x1d
	// Bit mask of LP_AONCLKRST_FORCE_NORST_SDMMC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_SDMMC_Msk = 0x20000000
	// Bit LP_AONCLKRST_FORCE_NORST_SDMMC.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_SDMMC = 0x20000000
	// Position of LP_AONCLKRST_RST_EN_EMAC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_EMAC_Pos = 0x1e
	// Bit mask of LP_AONCLKRST_RST_EN_EMAC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_EMAC_Msk = 0x40000000
	// Bit LP_AONCLKRST_RST_EN_EMAC.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_RST_EN_EMAC = 0x40000000
	// Position of LP_AONCLKRST_FORCE_NORST_EMAC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_EMAC_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_FORCE_NORST_EMAC field.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_EMAC_Msk = 0x80000000
	// Bit LP_AONCLKRST_FORCE_NORST_EMAC.
	LP_AON_CLKRST_LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_LP_AONCLKRST_FORCE_NORST_EMAC = 0x80000000

	// LP_AONCLKRST_DATE: need_des
	// Position of LP_AONCLKRST_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_DATE_LP_AONCLKRST_CLK_EN_Pos = 0x1f
	// Bit mask of LP_AONCLKRST_CLK_EN field.
	LP_AON_CLKRST_LP_AONCLKRST_DATE_LP_AONCLKRST_CLK_EN_Msk = 0x80000000
	// Bit LP_AONCLKRST_CLK_EN.
	LP_AON_CLKRST_LP_AONCLKRST_DATE_LP_AONCLKRST_CLK_EN = 0x80000000
)

// Constants for LP_GPIO: Low-power General Purpose Input/Output
const (
	// CLK_EN: Reserved
	// Position of REG_CLK_EN field.
	LP_GPIO_CLK_EN_REG_CLK_EN_Pos = 0x0
	// Bit mask of REG_CLK_EN field.
	LP_GPIO_CLK_EN_REG_CLK_EN_Msk = 0x1
	// Bit REG_CLK_EN.
	LP_GPIO_CLK_EN_REG_CLK_EN = 0x1

	// VER_DATE: Reserved
	// Position of REG_VER_DATE field.
	LP_GPIO_VER_DATE_REG_VER_DATE_Pos = 0x0
	// Bit mask of REG_VER_DATE field.
	LP_GPIO_VER_DATE_REG_VER_DATE_Msk = 0xfffffff

	// OUT: Reserved
	// Position of REG_GPIO_OUT_DATA field.
	LP_GPIO_OUT_REG_GPIO_OUT_DATA_Pos = 0x0
	// Bit mask of REG_GPIO_OUT_DATA field.
	LP_GPIO_OUT_REG_GPIO_OUT_DATA_Msk = 0xffff

	// OUT_W1TS: Reserved
	// Position of REG_GPIO_OUT_DATA_W1TS field.
	LP_GPIO_OUT_W1TS_REG_GPIO_OUT_DATA_W1TS_Pos = 0x0
	// Bit mask of REG_GPIO_OUT_DATA_W1TS field.
	LP_GPIO_OUT_W1TS_REG_GPIO_OUT_DATA_W1TS_Msk = 0xffff

	// OUT_W1TC: Reserved
	// Position of REG_GPIO_OUT_DATA_W1TC field.
	LP_GPIO_OUT_W1TC_REG_GPIO_OUT_DATA_W1TC_Pos = 0x0
	// Bit mask of REG_GPIO_OUT_DATA_W1TC field.
	LP_GPIO_OUT_W1TC_REG_GPIO_OUT_DATA_W1TC_Msk = 0xffff

	// ENABLE: Reserved
	// Position of REG_GPIO_ENABLE_DATA field.
	LP_GPIO_ENABLE_REG_GPIO_ENABLE_DATA_Pos = 0x0
	// Bit mask of REG_GPIO_ENABLE_DATA field.
	LP_GPIO_ENABLE_REG_GPIO_ENABLE_DATA_Msk = 0xffff

	// ENABLE_W1TS: Reserved
	// Position of REG_GPIO_ENABLE_DATA_W1TS field.
	LP_GPIO_ENABLE_W1TS_REG_GPIO_ENABLE_DATA_W1TS_Pos = 0x0
	// Bit mask of REG_GPIO_ENABLE_DATA_W1TS field.
	LP_GPIO_ENABLE_W1TS_REG_GPIO_ENABLE_DATA_W1TS_Msk = 0xffff

	// ENABLE_W1TC: Reserved
	// Position of REG_GPIO_ENABLE_DATA_W1TC field.
	LP_GPIO_ENABLE_W1TC_REG_GPIO_ENABLE_DATA_W1TC_Pos = 0x0
	// Bit mask of REG_GPIO_ENABLE_DATA_W1TC field.
	LP_GPIO_ENABLE_W1TC_REG_GPIO_ENABLE_DATA_W1TC_Msk = 0xffff

	// STATUS: Reserved
	// Position of REG_GPIO_STATUS_DATA field.
	LP_GPIO_STATUS_REG_GPIO_STATUS_DATA_Pos = 0x0
	// Bit mask of REG_GPIO_STATUS_DATA field.
	LP_GPIO_STATUS_REG_GPIO_STATUS_DATA_Msk = 0xffff

	// STATUS_W1TS: Reserved
	// Position of REG_GPIO_STATUS_DATA_W1TS field.
	LP_GPIO_STATUS_W1TS_REG_GPIO_STATUS_DATA_W1TS_Pos = 0x0
	// Bit mask of REG_GPIO_STATUS_DATA_W1TS field.
	LP_GPIO_STATUS_W1TS_REG_GPIO_STATUS_DATA_W1TS_Msk = 0xffff

	// STATUS_W1TC: Reserved
	// Position of REG_GPIO_STATUS_DATA_W1TC field.
	LP_GPIO_STATUS_W1TC_REG_GPIO_STATUS_DATA_W1TC_Pos = 0x0
	// Bit mask of REG_GPIO_STATUS_DATA_W1TC field.
	LP_GPIO_STATUS_W1TC_REG_GPIO_STATUS_DATA_W1TC_Msk = 0xffff

	// STATUS_NEXT: Reserved
	// Position of REG_GPIO_STATUS_INTERRUPT_NEXT field.
	LP_GPIO_STATUS_NEXT_REG_GPIO_STATUS_INTERRUPT_NEXT_Pos = 0x0
	// Bit mask of REG_GPIO_STATUS_INTERRUPT_NEXT field.
	LP_GPIO_STATUS_NEXT_REG_GPIO_STATUS_INTERRUPT_NEXT_Msk = 0xffff

	// IN: Reserved
	// Position of REG_GPIO_IN_DATA_NEXT field.
	LP_GPIO_IN_REG_GPIO_IN_DATA_NEXT_Pos = 0x0
	// Bit mask of REG_GPIO_IN_DATA_NEXT field.
	LP_GPIO_IN_REG_GPIO_IN_DATA_NEXT_Msk = 0xffff

	// PIN0: Reserved
	// Position of REG_GPIO_PIN0_WAKEUP_ENABLE field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN0_WAKEUP_ENABLE field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN0_WAKEUP_ENABLE.
	LP_GPIO_PIN0_REG_GPIO_PIN0_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN0_INT_TYPE field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN0_INT_TYPE field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN0_PAD_DRIVER field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN0_PAD_DRIVER field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN0_PAD_DRIVER.
	LP_GPIO_PIN0_REG_GPIO_PIN0_PAD_DRIVER = 0x10
	// Position of REG_GPIO_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPIO_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN0_REG_GPIO_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPIO_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN0_REG_GPIO_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN1: Reserved
	// Position of REG_GPIO_PIN1_WAKEUP_ENABLE field.
	LP_GPIO_PIN1_REG_GPIO_PIN1_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN1_WAKEUP_ENABLE field.
	LP_GPIO_PIN1_REG_GPIO_PIN1_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN1_WAKEUP_ENABLE.
	LP_GPIO_PIN1_REG_GPIO_PIN1_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN1_INT_TYPE field.
	LP_GPIO_PIN1_REG_GPIO_PIN1_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN1_INT_TYPE field.
	LP_GPIO_PIN1_REG_GPIO_PIN1_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN1_PAD_DRIVER field.
	LP_GPIO_PIN1_REG_GPIO_PIN1_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN1_PAD_DRIVER field.
	LP_GPIO_PIN1_REG_GPIO_PIN1_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN1_PAD_DRIVER.
	LP_GPIO_PIN1_REG_GPIO_PIN1_PAD_DRIVER = 0x10
	// Position of REG_GPI1_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN1_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI1_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN1_REG_GPI1_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI1_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN1_REG_GPI1_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN2: Reserved
	// Position of REG_GPIO_PIN2_WAKEUP_ENABLE field.
	LP_GPIO_PIN2_REG_GPIO_PIN2_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN2_WAKEUP_ENABLE field.
	LP_GPIO_PIN2_REG_GPIO_PIN2_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN2_WAKEUP_ENABLE.
	LP_GPIO_PIN2_REG_GPIO_PIN2_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN2_INT_TYPE field.
	LP_GPIO_PIN2_REG_GPIO_PIN2_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN2_INT_TYPE field.
	LP_GPIO_PIN2_REG_GPIO_PIN2_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN2_PAD_DRIVER field.
	LP_GPIO_PIN2_REG_GPIO_PIN2_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN2_PAD_DRIVER field.
	LP_GPIO_PIN2_REG_GPIO_PIN2_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN2_PAD_DRIVER.
	LP_GPIO_PIN2_REG_GPIO_PIN2_PAD_DRIVER = 0x10
	// Position of REG_GPI2_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN2_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI2_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN2_REG_GPI2_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI2_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN2_REG_GPI2_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN3: Reserved
	// Position of REG_GPIO_PIN3_WAKEUP_ENABLE field.
	LP_GPIO_PIN3_REG_GPIO_PIN3_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN3_WAKEUP_ENABLE field.
	LP_GPIO_PIN3_REG_GPIO_PIN3_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN3_WAKEUP_ENABLE.
	LP_GPIO_PIN3_REG_GPIO_PIN3_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN3_INT_TYPE field.
	LP_GPIO_PIN3_REG_GPIO_PIN3_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN3_INT_TYPE field.
	LP_GPIO_PIN3_REG_GPIO_PIN3_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN3_PAD_DRIVER field.
	LP_GPIO_PIN3_REG_GPIO_PIN3_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN3_PAD_DRIVER field.
	LP_GPIO_PIN3_REG_GPIO_PIN3_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN3_PAD_DRIVER.
	LP_GPIO_PIN3_REG_GPIO_PIN3_PAD_DRIVER = 0x10
	// Position of REG_GPI3_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN3_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI3_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN3_REG_GPI3_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI3_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN3_REG_GPI3_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN4: Reserved
	// Position of REG_GPIO_PIN4_WAKEUP_ENABLE field.
	LP_GPIO_PIN4_REG_GPIO_PIN4_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN4_WAKEUP_ENABLE field.
	LP_GPIO_PIN4_REG_GPIO_PIN4_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN4_WAKEUP_ENABLE.
	LP_GPIO_PIN4_REG_GPIO_PIN4_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN4_INT_TYPE field.
	LP_GPIO_PIN4_REG_GPIO_PIN4_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN4_INT_TYPE field.
	LP_GPIO_PIN4_REG_GPIO_PIN4_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN4_PAD_DRIVER field.
	LP_GPIO_PIN4_REG_GPIO_PIN4_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN4_PAD_DRIVER field.
	LP_GPIO_PIN4_REG_GPIO_PIN4_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN4_PAD_DRIVER.
	LP_GPIO_PIN4_REG_GPIO_PIN4_PAD_DRIVER = 0x10
	// Position of REG_GPI4_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN4_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI4_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN4_REG_GPI4_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI4_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN4_REG_GPI4_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN5: Reserved
	// Position of REG_GPIO_PIN5_WAKEUP_ENABLE field.
	LP_GPIO_PIN5_REG_GPIO_PIN5_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN5_WAKEUP_ENABLE field.
	LP_GPIO_PIN5_REG_GPIO_PIN5_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN5_WAKEUP_ENABLE.
	LP_GPIO_PIN5_REG_GPIO_PIN5_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN5_INT_TYPE field.
	LP_GPIO_PIN5_REG_GPIO_PIN5_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN5_INT_TYPE field.
	LP_GPIO_PIN5_REG_GPIO_PIN5_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN5_PAD_DRIVER field.
	LP_GPIO_PIN5_REG_GPIO_PIN5_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN5_PAD_DRIVER field.
	LP_GPIO_PIN5_REG_GPIO_PIN5_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN5_PAD_DRIVER.
	LP_GPIO_PIN5_REG_GPIO_PIN5_PAD_DRIVER = 0x10
	// Position of REG_GPI5_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN5_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI5_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN5_REG_GPI5_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI5_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN5_REG_GPI5_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN6: Reserved
	// Position of REG_GPIO_PIN6_WAKEUP_ENABLE field.
	LP_GPIO_PIN6_REG_GPIO_PIN6_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN6_WAKEUP_ENABLE field.
	LP_GPIO_PIN6_REG_GPIO_PIN6_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN6_WAKEUP_ENABLE.
	LP_GPIO_PIN6_REG_GPIO_PIN6_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN6_INT_TYPE field.
	LP_GPIO_PIN6_REG_GPIO_PIN6_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN6_INT_TYPE field.
	LP_GPIO_PIN6_REG_GPIO_PIN6_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN6_PAD_DRIVER field.
	LP_GPIO_PIN6_REG_GPIO_PIN6_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN6_PAD_DRIVER field.
	LP_GPIO_PIN6_REG_GPIO_PIN6_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN6_PAD_DRIVER.
	LP_GPIO_PIN6_REG_GPIO_PIN6_PAD_DRIVER = 0x10
	// Position of REG_GPI6_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN6_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI6_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN6_REG_GPI6_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI6_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN6_REG_GPI6_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN7: Reserved
	// Position of REG_GPIO_PIN7_WAKEUP_ENABLE field.
	LP_GPIO_PIN7_REG_GPIO_PIN7_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN7_WAKEUP_ENABLE field.
	LP_GPIO_PIN7_REG_GPIO_PIN7_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN7_WAKEUP_ENABLE.
	LP_GPIO_PIN7_REG_GPIO_PIN7_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN7_INT_TYPE field.
	LP_GPIO_PIN7_REG_GPIO_PIN7_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN7_INT_TYPE field.
	LP_GPIO_PIN7_REG_GPIO_PIN7_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN7_PAD_DRIVER field.
	LP_GPIO_PIN7_REG_GPIO_PIN7_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN7_PAD_DRIVER field.
	LP_GPIO_PIN7_REG_GPIO_PIN7_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN7_PAD_DRIVER.
	LP_GPIO_PIN7_REG_GPIO_PIN7_PAD_DRIVER = 0x10
	// Position of REG_GPI7_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN7_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI7_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN7_REG_GPI7_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI7_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN7_REG_GPI7_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN8: Reserved
	// Position of REG_GPIO_PIN8_WAKEUP_ENABLE field.
	LP_GPIO_PIN8_REG_GPIO_PIN8_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN8_WAKEUP_ENABLE field.
	LP_GPIO_PIN8_REG_GPIO_PIN8_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN8_WAKEUP_ENABLE.
	LP_GPIO_PIN8_REG_GPIO_PIN8_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN8_INT_TYPE field.
	LP_GPIO_PIN8_REG_GPIO_PIN8_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN8_INT_TYPE field.
	LP_GPIO_PIN8_REG_GPIO_PIN8_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN8_PAD_DRIVER field.
	LP_GPIO_PIN8_REG_GPIO_PIN8_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN8_PAD_DRIVER field.
	LP_GPIO_PIN8_REG_GPIO_PIN8_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN8_PAD_DRIVER.
	LP_GPIO_PIN8_REG_GPIO_PIN8_PAD_DRIVER = 0x10
	// Position of REG_GPI8_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN8_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI8_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN8_REG_GPI8_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI8_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN8_REG_GPI8_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN9: Reserved
	// Position of REG_GPIO_PIN9_WAKEUP_ENABLE field.
	LP_GPIO_PIN9_REG_GPIO_PIN9_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN9_WAKEUP_ENABLE field.
	LP_GPIO_PIN9_REG_GPIO_PIN9_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN9_WAKEUP_ENABLE.
	LP_GPIO_PIN9_REG_GPIO_PIN9_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN9_INT_TYPE field.
	LP_GPIO_PIN9_REG_GPIO_PIN9_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN9_INT_TYPE field.
	LP_GPIO_PIN9_REG_GPIO_PIN9_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN9_PAD_DRIVER field.
	LP_GPIO_PIN9_REG_GPIO_PIN9_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN9_PAD_DRIVER field.
	LP_GPIO_PIN9_REG_GPIO_PIN9_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN9_PAD_DRIVER.
	LP_GPIO_PIN9_REG_GPIO_PIN9_PAD_DRIVER = 0x10
	// Position of REG_GPI9_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN9_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI9_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN9_REG_GPI9_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI9_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN9_REG_GPI9_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN10: Reserved
	// Position of REG_GPIO_PIN10_WAKEUP_ENABLE field.
	LP_GPIO_PIN10_REG_GPIO_PIN10_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN10_WAKEUP_ENABLE field.
	LP_GPIO_PIN10_REG_GPIO_PIN10_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN10_WAKEUP_ENABLE.
	LP_GPIO_PIN10_REG_GPIO_PIN10_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN10_INT_TYPE field.
	LP_GPIO_PIN10_REG_GPIO_PIN10_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN10_INT_TYPE field.
	LP_GPIO_PIN10_REG_GPIO_PIN10_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN10_PAD_DRIVER field.
	LP_GPIO_PIN10_REG_GPIO_PIN10_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN10_PAD_DRIVER field.
	LP_GPIO_PIN10_REG_GPIO_PIN10_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN10_PAD_DRIVER.
	LP_GPIO_PIN10_REG_GPIO_PIN10_PAD_DRIVER = 0x10
	// Position of REG_GPI10_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN10_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI10_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN10_REG_GPI10_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI10_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN10_REG_GPI10_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN11: Reserved
	// Position of REG_GPIO_PIN11_WAKEUP_ENABLE field.
	LP_GPIO_PIN11_REG_GPIO_PIN11_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN11_WAKEUP_ENABLE field.
	LP_GPIO_PIN11_REG_GPIO_PIN11_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN11_WAKEUP_ENABLE.
	LP_GPIO_PIN11_REG_GPIO_PIN11_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN11_INT_TYPE field.
	LP_GPIO_PIN11_REG_GPIO_PIN11_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN11_INT_TYPE field.
	LP_GPIO_PIN11_REG_GPIO_PIN11_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN11_PAD_DRIVER field.
	LP_GPIO_PIN11_REG_GPIO_PIN11_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN11_PAD_DRIVER field.
	LP_GPIO_PIN11_REG_GPIO_PIN11_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN11_PAD_DRIVER.
	LP_GPIO_PIN11_REG_GPIO_PIN11_PAD_DRIVER = 0x10
	// Position of REG_GPI11_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN11_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI11_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN11_REG_GPI11_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI11_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN11_REG_GPI11_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN12: Reserved
	// Position of REG_GPIO_PIN12_WAKEUP_ENABLE field.
	LP_GPIO_PIN12_REG_GPIO_PIN12_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN12_WAKEUP_ENABLE field.
	LP_GPIO_PIN12_REG_GPIO_PIN12_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN12_WAKEUP_ENABLE.
	LP_GPIO_PIN12_REG_GPIO_PIN12_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN12_INT_TYPE field.
	LP_GPIO_PIN12_REG_GPIO_PIN12_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN12_INT_TYPE field.
	LP_GPIO_PIN12_REG_GPIO_PIN12_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN12_PAD_DRIVER field.
	LP_GPIO_PIN12_REG_GPIO_PIN12_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN12_PAD_DRIVER field.
	LP_GPIO_PIN12_REG_GPIO_PIN12_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN12_PAD_DRIVER.
	LP_GPIO_PIN12_REG_GPIO_PIN12_PAD_DRIVER = 0x10
	// Position of REG_GPI12_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN12_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI12_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN12_REG_GPI12_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI12_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN12_REG_GPI12_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN13: Reserved
	// Position of REG_GPIO_PIN13_WAKEUP_ENABLE field.
	LP_GPIO_PIN13_REG_GPIO_PIN13_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN13_WAKEUP_ENABLE field.
	LP_GPIO_PIN13_REG_GPIO_PIN13_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN13_WAKEUP_ENABLE.
	LP_GPIO_PIN13_REG_GPIO_PIN13_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN13_INT_TYPE field.
	LP_GPIO_PIN13_REG_GPIO_PIN13_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN13_INT_TYPE field.
	LP_GPIO_PIN13_REG_GPIO_PIN13_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN13_PAD_DRIVER field.
	LP_GPIO_PIN13_REG_GPIO_PIN13_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN13_PAD_DRIVER field.
	LP_GPIO_PIN13_REG_GPIO_PIN13_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN13_PAD_DRIVER.
	LP_GPIO_PIN13_REG_GPIO_PIN13_PAD_DRIVER = 0x10
	// Position of REG_GPI13_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN13_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI13_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN13_REG_GPI13_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI13_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN13_REG_GPI13_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN14: Reserved
	// Position of REG_GPIO_PIN14_WAKEUP_ENABLE field.
	LP_GPIO_PIN14_REG_GPIO_PIN14_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN14_WAKEUP_ENABLE field.
	LP_GPIO_PIN14_REG_GPIO_PIN14_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN14_WAKEUP_ENABLE.
	LP_GPIO_PIN14_REG_GPIO_PIN14_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN14_INT_TYPE field.
	LP_GPIO_PIN14_REG_GPIO_PIN14_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN14_INT_TYPE field.
	LP_GPIO_PIN14_REG_GPIO_PIN14_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN14_PAD_DRIVER field.
	LP_GPIO_PIN14_REG_GPIO_PIN14_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN14_PAD_DRIVER field.
	LP_GPIO_PIN14_REG_GPIO_PIN14_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN14_PAD_DRIVER.
	LP_GPIO_PIN14_REG_GPIO_PIN14_PAD_DRIVER = 0x10
	// Position of REG_GPI14_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN14_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI14_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN14_REG_GPI14_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI14_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN14_REG_GPI14_PIN0_EDGE_WAKEUP_CLR = 0x20

	// PIN15: Reserved
	// Position of REG_GPIO_PIN15_WAKEUP_ENABLE field.
	LP_GPIO_PIN15_REG_GPIO_PIN15_WAKEUP_ENABLE_Pos = 0x0
	// Bit mask of REG_GPIO_PIN15_WAKEUP_ENABLE field.
	LP_GPIO_PIN15_REG_GPIO_PIN15_WAKEUP_ENABLE_Msk = 0x1
	// Bit REG_GPIO_PIN15_WAKEUP_ENABLE.
	LP_GPIO_PIN15_REG_GPIO_PIN15_WAKEUP_ENABLE = 0x1
	// Position of REG_GPIO_PIN15_INT_TYPE field.
	LP_GPIO_PIN15_REG_GPIO_PIN15_INT_TYPE_Pos = 0x1
	// Bit mask of REG_GPIO_PIN15_INT_TYPE field.
	LP_GPIO_PIN15_REG_GPIO_PIN15_INT_TYPE_Msk = 0xe
	// Position of REG_GPIO_PIN15_PAD_DRIVER field.
	LP_GPIO_PIN15_REG_GPIO_PIN15_PAD_DRIVER_Pos = 0x4
	// Bit mask of REG_GPIO_PIN15_PAD_DRIVER field.
	LP_GPIO_PIN15_REG_GPIO_PIN15_PAD_DRIVER_Msk = 0x10
	// Bit REG_GPIO_PIN15_PAD_DRIVER.
	LP_GPIO_PIN15_REG_GPIO_PIN15_PAD_DRIVER = 0x10
	// Position of REG_GPI15_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN15_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_Pos = 0x5
	// Bit mask of REG_GPI15_PIN0_EDGE_WAKEUP_CLR field.
	LP_GPIO_PIN15_REG_GPI15_PIN0_EDGE_WAKEUP_CLR_Msk = 0x20
	// Bit REG_GPI15_PIN0_EDGE_WAKEUP_CLR.
	LP_GPIO_PIN15_REG_GPI15_PIN0_EDGE_WAKEUP_CLR = 0x20

	// FUNC0_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC0_IN_INV_SEL field.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC0_IN_INV_SEL field.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC0_IN_INV_SEL.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG0_IN_SEL field.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_SIG0_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG0_IN_SEL field.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_SIG0_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG0_IN_SEL.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_SIG0_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC0_IN_SEL field.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC0_IN_SEL field.
	LP_GPIO_FUNC0_IN_SEL_CFG_REG_GPIO_FUNC0_IN_SEL_Msk = 0xfc

	// FUNC1_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC1_IN_INV_SEL field.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC1_IN_INV_SEL field.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC1_IN_INV_SEL.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG1_IN_SEL field.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_SIG1_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG1_IN_SEL field.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_SIG1_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG1_IN_SEL.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_SIG1_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC1_IN_SEL field.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC1_IN_SEL field.
	LP_GPIO_FUNC1_IN_SEL_CFG_REG_GPIO_FUNC1_IN_SEL_Msk = 0xfc

	// FUNC2_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC2_IN_INV_SEL field.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC2_IN_INV_SEL field.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC2_IN_INV_SEL.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG2_IN_SEL field.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_SIG2_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG2_IN_SEL field.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_SIG2_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG2_IN_SEL.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_SIG2_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC2_IN_SEL field.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC2_IN_SEL field.
	LP_GPIO_FUNC2_IN_SEL_CFG_REG_GPIO_FUNC2_IN_SEL_Msk = 0xfc

	// FUNC3_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC3_IN_INV_SEL field.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC3_IN_INV_SEL field.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC3_IN_INV_SEL.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG3_IN_SEL field.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_SIG3_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG3_IN_SEL field.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_SIG3_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG3_IN_SEL.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_SIG3_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC3_IN_SEL field.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC3_IN_SEL field.
	LP_GPIO_FUNC3_IN_SEL_CFG_REG_GPIO_FUNC3_IN_SEL_Msk = 0xfc

	// FUNC4_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC4_IN_INV_SEL field.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC4_IN_INV_SEL field.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC4_IN_INV_SEL.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG4_IN_SEL field.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_SIG4_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG4_IN_SEL field.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_SIG4_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG4_IN_SEL.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_SIG4_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC4_IN_SEL field.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC4_IN_SEL field.
	LP_GPIO_FUNC4_IN_SEL_CFG_REG_GPIO_FUNC4_IN_SEL_Msk = 0xfc

	// FUNC5_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC5_IN_INV_SEL field.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC5_IN_INV_SEL field.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC5_IN_INV_SEL.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG5_IN_SEL field.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_SIG5_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG5_IN_SEL field.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_SIG5_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG5_IN_SEL.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_SIG5_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC5_IN_SEL field.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC5_IN_SEL field.
	LP_GPIO_FUNC5_IN_SEL_CFG_REG_GPIO_FUNC5_IN_SEL_Msk = 0xfc

	// FUNC6_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC6_IN_INV_SEL field.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC6_IN_INV_SEL field.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC6_IN_INV_SEL.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG6_IN_SEL field.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_SIG6_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG6_IN_SEL field.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_SIG6_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG6_IN_SEL.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_SIG6_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC6_IN_SEL field.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC6_IN_SEL field.
	LP_GPIO_FUNC6_IN_SEL_CFG_REG_GPIO_FUNC6_IN_SEL_Msk = 0xfc

	// FUNC7_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC7_IN_INV_SEL field.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC7_IN_INV_SEL field.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC7_IN_INV_SEL.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG7_IN_SEL field.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_SIG7_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG7_IN_SEL field.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_SIG7_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG7_IN_SEL.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_SIG7_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC7_IN_SEL field.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC7_IN_SEL field.
	LP_GPIO_FUNC7_IN_SEL_CFG_REG_GPIO_FUNC7_IN_SEL_Msk = 0xfc

	// FUNC8_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC8_IN_INV_SEL field.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC8_IN_INV_SEL field.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC8_IN_INV_SEL.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG8_IN_SEL field.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_SIG8_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG8_IN_SEL field.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_SIG8_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG8_IN_SEL.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_SIG8_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC8_IN_SEL field.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC8_IN_SEL field.
	LP_GPIO_FUNC8_IN_SEL_CFG_REG_GPIO_FUNC8_IN_SEL_Msk = 0xfc

	// FUNC9_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC9_IN_INV_SEL field.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC9_IN_INV_SEL field.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC9_IN_INV_SEL.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG9_IN_SEL field.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_SIG9_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG9_IN_SEL field.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_SIG9_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG9_IN_SEL.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_SIG9_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC9_IN_SEL field.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC9_IN_SEL field.
	LP_GPIO_FUNC9_IN_SEL_CFG_REG_GPIO_FUNC9_IN_SEL_Msk = 0xfc

	// FUNC10_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC10_IN_INV_SEL field.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC10_IN_INV_SEL field.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC10_IN_INV_SEL.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG10_IN_SEL field.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_SIG10_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG10_IN_SEL field.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_SIG10_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG10_IN_SEL.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_SIG10_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC10_IN_SEL field.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC10_IN_SEL field.
	LP_GPIO_FUNC10_IN_SEL_CFG_REG_GPIO_FUNC10_IN_SEL_Msk = 0xfc

	// FUNC11_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC11_IN_INV_SEL field.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC11_IN_INV_SEL field.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC11_IN_INV_SEL.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG11_IN_SEL field.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_SIG11_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG11_IN_SEL field.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_SIG11_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG11_IN_SEL.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_SIG11_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC11_IN_SEL field.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC11_IN_SEL field.
	LP_GPIO_FUNC11_IN_SEL_CFG_REG_GPIO_FUNC11_IN_SEL_Msk = 0xfc

	// FUNC12_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC12_IN_INV_SEL field.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC12_IN_INV_SEL field.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC12_IN_INV_SEL.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG12_IN_SEL field.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_SIG12_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG12_IN_SEL field.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_SIG12_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG12_IN_SEL.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_SIG12_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC12_IN_SEL field.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC12_IN_SEL field.
	LP_GPIO_FUNC12_IN_SEL_CFG_REG_GPIO_FUNC12_IN_SEL_Msk = 0xfc

	// FUNC13_IN_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC13_IN_INV_SEL field.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC13_IN_INV_SEL field.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC13_IN_INV_SEL.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_INV_SEL = 0x1
	// Position of REG_GPIO_SIG13_IN_SEL field.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_SIG13_IN_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_SIG13_IN_SEL field.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_SIG13_IN_SEL_Msk = 0x2
	// Bit REG_GPIO_SIG13_IN_SEL.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_SIG13_IN_SEL = 0x2
	// Position of REG_GPIO_FUNC13_IN_SEL field.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC13_IN_SEL field.
	LP_GPIO_FUNC13_IN_SEL_CFG_REG_GPIO_FUNC13_IN_SEL_Msk = 0xfc

	// FUNC0_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC0_OE_INV_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC0_OE_INV_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC0_OE_INV_SEL.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC0_OE_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC0_OE_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC0_OE_SEL.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC0_OUT_INV_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC0_OUT_INV_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC0_OUT_INV_SEL.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC0_OUT_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC0_OUT_SEL field.
	LP_GPIO_FUNC0_OUT_SEL_CFG_REG_GPIO_FUNC0_OUT_SEL_Msk = 0x1f8

	// FUNC1_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC1_OE_INV_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC1_OE_INV_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC1_OE_INV_SEL.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC1_OE_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC1_OE_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC1_OE_SEL.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC1_OUT_INV_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC1_OUT_INV_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC1_OUT_INV_SEL.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC1_OUT_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC1_OUT_SEL field.
	LP_GPIO_FUNC1_OUT_SEL_CFG_REG_GPIO_FUNC1_OUT_SEL_Msk = 0x1f8

	// FUNC2_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC2_OE_INV_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC2_OE_INV_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC2_OE_INV_SEL.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC2_OE_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC2_OE_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC2_OE_SEL.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC2_OUT_INV_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC2_OUT_INV_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC2_OUT_INV_SEL.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC2_OUT_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC2_OUT_SEL field.
	LP_GPIO_FUNC2_OUT_SEL_CFG_REG_GPIO_FUNC2_OUT_SEL_Msk = 0x1f8

	// FUNC3_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC3_OE_INV_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC3_OE_INV_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC3_OE_INV_SEL.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC3_OE_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC3_OE_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC3_OE_SEL.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC3_OUT_INV_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC3_OUT_INV_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC3_OUT_INV_SEL.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC3_OUT_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC3_OUT_SEL field.
	LP_GPIO_FUNC3_OUT_SEL_CFG_REG_GPIO_FUNC3_OUT_SEL_Msk = 0x1f8

	// FUNC4_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC4_OE_INV_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC4_OE_INV_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC4_OE_INV_SEL.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC4_OE_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC4_OE_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC4_OE_SEL.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC4_OUT_INV_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC4_OUT_INV_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC4_OUT_INV_SEL.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC4_OUT_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC4_OUT_SEL field.
	LP_GPIO_FUNC4_OUT_SEL_CFG_REG_GPIO_FUNC4_OUT_SEL_Msk = 0x1f8

	// FUNC5_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC5_OE_INV_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC5_OE_INV_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC5_OE_INV_SEL.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC5_OE_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC5_OE_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC5_OE_SEL.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC5_OUT_INV_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC5_OUT_INV_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC5_OUT_INV_SEL.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC5_OUT_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC5_OUT_SEL field.
	LP_GPIO_FUNC5_OUT_SEL_CFG_REG_GPIO_FUNC5_OUT_SEL_Msk = 0x1f8

	// FUNC6_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC6_OE_INV_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC6_OE_INV_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC6_OE_INV_SEL.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC6_OE_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC6_OE_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC6_OE_SEL.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC6_OUT_INV_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC6_OUT_INV_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC6_OUT_INV_SEL.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC6_OUT_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC6_OUT_SEL field.
	LP_GPIO_FUNC6_OUT_SEL_CFG_REG_GPIO_FUNC6_OUT_SEL_Msk = 0x1f8

	// FUNC7_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC7_OE_INV_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC7_OE_INV_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC7_OE_INV_SEL.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC7_OE_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC7_OE_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC7_OE_SEL.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC7_OUT_INV_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC7_OUT_INV_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC7_OUT_INV_SEL.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC7_OUT_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC7_OUT_SEL field.
	LP_GPIO_FUNC7_OUT_SEL_CFG_REG_GPIO_FUNC7_OUT_SEL_Msk = 0x1f8

	// FUNC8_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC8_OE_INV_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC8_OE_INV_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC8_OE_INV_SEL.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC8_OE_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC8_OE_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC8_OE_SEL.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC8_OUT_INV_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC8_OUT_INV_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC8_OUT_INV_SEL.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC8_OUT_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC8_OUT_SEL field.
	LP_GPIO_FUNC8_OUT_SEL_CFG_REG_GPIO_FUNC8_OUT_SEL_Msk = 0x1f8

	// FUNC9_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC9_OE_INV_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC9_OE_INV_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC9_OE_INV_SEL.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC9_OE_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC9_OE_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC9_OE_SEL.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC9_OUT_INV_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC9_OUT_INV_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC9_OUT_INV_SEL.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC9_OUT_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC9_OUT_SEL field.
	LP_GPIO_FUNC9_OUT_SEL_CFG_REG_GPIO_FUNC9_OUT_SEL_Msk = 0x1f8

	// FUNC10_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC10_OE_INV_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC10_OE_INV_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC10_OE_INV_SEL.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC10_OE_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC10_OE_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC10_OE_SEL.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC10_OUT_INV_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC10_OUT_INV_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC10_OUT_INV_SEL.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC10_OUT_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC10_OUT_SEL field.
	LP_GPIO_FUNC10_OUT_SEL_CFG_REG_GPIO_FUNC10_OUT_SEL_Msk = 0x1f8

	// FUNC11_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC11_OE_INV_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC11_OE_INV_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC11_OE_INV_SEL.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC11_OE_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC11_OE_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC11_OE_SEL.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC11_OUT_INV_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC11_OUT_INV_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC11_OUT_INV_SEL.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC11_OUT_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC11_OUT_SEL field.
	LP_GPIO_FUNC11_OUT_SEL_CFG_REG_GPIO_FUNC11_OUT_SEL_Msk = 0x1f8

	// FUNC12_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC12_OE_INV_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC12_OE_INV_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC12_OE_INV_SEL.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC12_OE_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC12_OE_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC12_OE_SEL.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC12_OUT_INV_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC12_OUT_INV_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC12_OUT_INV_SEL.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC12_OUT_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC12_OUT_SEL field.
	LP_GPIO_FUNC12_OUT_SEL_CFG_REG_GPIO_FUNC12_OUT_SEL_Msk = 0x1f8

	// FUNC13_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC13_OE_INV_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC13_OE_INV_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC13_OE_INV_SEL.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC13_OE_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC13_OE_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC13_OE_SEL.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC13_OUT_INV_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC13_OUT_INV_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC13_OUT_INV_SEL.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC13_OUT_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC13_OUT_SEL field.
	LP_GPIO_FUNC13_OUT_SEL_CFG_REG_GPIO_FUNC13_OUT_SEL_Msk = 0x1f8

	// FUNC14_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC14_OE_INV_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC14_OE_INV_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC14_OE_INV_SEL.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC14_OE_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC14_OE_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC14_OE_SEL.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC14_OUT_INV_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC14_OUT_INV_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC14_OUT_INV_SEL.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC14_OUT_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC14_OUT_SEL field.
	LP_GPIO_FUNC14_OUT_SEL_CFG_REG_GPIO_FUNC14_OUT_SEL_Msk = 0x1f8

	// FUNC15_OUT_SEL_CFG: Reserved
	// Position of REG_GPIO_FUNC15_OE_INV_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_INV_SEL_Pos = 0x0
	// Bit mask of REG_GPIO_FUNC15_OE_INV_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_INV_SEL_Msk = 0x1
	// Bit REG_GPIO_FUNC15_OE_INV_SEL.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_INV_SEL = 0x1
	// Position of REG_GPIO_FUNC15_OE_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_SEL_Pos = 0x1
	// Bit mask of REG_GPIO_FUNC15_OE_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_SEL_Msk = 0x2
	// Bit REG_GPIO_FUNC15_OE_SEL.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OE_SEL = 0x2
	// Position of REG_GPIO_FUNC15_OUT_INV_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_INV_SEL_Pos = 0x2
	// Bit mask of REG_GPIO_FUNC15_OUT_INV_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_INV_SEL_Msk = 0x4
	// Bit REG_GPIO_FUNC15_OUT_INV_SEL.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_INV_SEL = 0x4
	// Position of REG_GPIO_FUNC15_OUT_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_SEL_Pos = 0x3
	// Bit mask of REG_GPIO_FUNC15_OUT_SEL field.
	LP_GPIO_FUNC15_OUT_SEL_CFG_REG_GPIO_FUNC15_OUT_SEL_Msk = 0x1f8
)

// Constants for LP_I2C0: Low-power I2C (Inter-Integrated Circuit) Controller 0
const (
	// SCL_LOW_PERIOD: Configures the low level width of the SCL Clock
	// Position of SCL_LOW_PERIOD field.
	LP_I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Pos = 0x0
	// Bit mask of SCL_LOW_PERIOD field.
	LP_I2C_SCL_LOW_PERIOD_SCL_LOW_PERIOD_Msk = 0x1ff

	// CTR: Transmission setting
	// Position of SDA_FORCE_OUT field.
	LP_I2C_CTR_SDA_FORCE_OUT_Pos = 0x0
	// Bit mask of SDA_FORCE_OUT field.
	LP_I2C_CTR_SDA_FORCE_OUT_Msk = 0x1
	// Bit SDA_FORCE_OUT.
	LP_I2C_CTR_SDA_FORCE_OUT = 0x1
	// Position of SCL_FORCE_OUT field.
	LP_I2C_CTR_SCL_FORCE_OUT_Pos = 0x1
	// Bit mask of SCL_FORCE_OUT field.
	LP_I2C_CTR_SCL_FORCE_OUT_Msk = 0x2
	// Bit SCL_FORCE_OUT.
	LP_I2C_CTR_SCL_FORCE_OUT = 0x2
	// Position of SAMPLE_SCL_LEVEL field.
	LP_I2C_CTR_SAMPLE_SCL_LEVEL_Pos = 0x2
	// Bit mask of SAMPLE_SCL_LEVEL field.
	LP_I2C_CTR_SAMPLE_SCL_LEVEL_Msk = 0x4
	// Bit SAMPLE_SCL_LEVEL.
	LP_I2C_CTR_SAMPLE_SCL_LEVEL = 0x4
	// Position of RX_FULL_ACK_LEVEL field.
	LP_I2C_CTR_RX_FULL_ACK_LEVEL_Pos = 0x3
	// Bit mask of RX_FULL_ACK_LEVEL field.
	LP_I2C_CTR_RX_FULL_ACK_LEVEL_Msk = 0x8
	// Bit RX_FULL_ACK_LEVEL.
	LP_I2C_CTR_RX_FULL_ACK_LEVEL = 0x8
	// Position of TRANS_START field.
	LP_I2C_CTR_TRANS_START_Pos = 0x5
	// Bit mask of TRANS_START field.
	LP_I2C_CTR_TRANS_START_Msk = 0x20
	// Bit TRANS_START.
	LP_I2C_CTR_TRANS_START = 0x20
	// Position of TX_LSB_FIRST field.
	LP_I2C_CTR_TX_LSB_FIRST_Pos = 0x6
	// Bit mask of TX_LSB_FIRST field.
	LP_I2C_CTR_TX_LSB_FIRST_Msk = 0x40
	// Bit TX_LSB_FIRST.
	LP_I2C_CTR_TX_LSB_FIRST = 0x40
	// Position of RX_LSB_FIRST field.
	LP_I2C_CTR_RX_LSB_FIRST_Pos = 0x7
	// Bit mask of RX_LSB_FIRST field.
	LP_I2C_CTR_RX_LSB_FIRST_Msk = 0x80
	// Bit RX_LSB_FIRST.
	LP_I2C_CTR_RX_LSB_FIRST = 0x80
	// Position of CLK_EN field.
	LP_I2C_CTR_CLK_EN_Pos = 0x8
	// Bit mask of CLK_EN field.
	LP_I2C_CTR_CLK_EN_Msk = 0x100
	// Bit CLK_EN.
	LP_I2C_CTR_CLK_EN = 0x100
	// Position of ARBITRATION_EN field.
	LP_I2C_CTR_ARBITRATION_EN_Pos = 0x9
	// Bit mask of ARBITRATION_EN field.
	LP_I2C_CTR_ARBITRATION_EN_Msk = 0x200
	// Bit ARBITRATION_EN.
	LP_I2C_CTR_ARBITRATION_EN = 0x200
	// Position of FSM_RST field.
	LP_I2C_CTR_FSM_RST_Pos = 0xa
	// Bit mask of FSM_RST field.
	LP_I2C_CTR_FSM_RST_Msk = 0x400
	// Bit FSM_RST.
	LP_I2C_CTR_FSM_RST = 0x400
	// Position of CONF_UPGATE field.
	LP_I2C_CTR_CONF_UPGATE_Pos = 0xb
	// Bit mask of CONF_UPGATE field.
	LP_I2C_CTR_CONF_UPGATE_Msk = 0x800
	// Bit CONF_UPGATE.
	LP_I2C_CTR_CONF_UPGATE = 0x800

	// SR: Describe I2C work status.
	// Position of RESP_REC field.
	LP_I2C_SR_RESP_REC_Pos = 0x0
	// Bit mask of RESP_REC field.
	LP_I2C_SR_RESP_REC_Msk = 0x1
	// Bit RESP_REC.
	LP_I2C_SR_RESP_REC = 0x1
	// Position of ARB_LOST field.
	LP_I2C_SR_ARB_LOST_Pos = 0x3
	// Bit mask of ARB_LOST field.
	LP_I2C_SR_ARB_LOST_Msk = 0x8
	// Bit ARB_LOST.
	LP_I2C_SR_ARB_LOST = 0x8
	// Position of BUS_BUSY field.
	LP_I2C_SR_BUS_BUSY_Pos = 0x4
	// Bit mask of BUS_BUSY field.
	LP_I2C_SR_BUS_BUSY_Msk = 0x10
	// Bit BUS_BUSY.
	LP_I2C_SR_BUS_BUSY = 0x10
	// Position of RXFIFO_CNT field.
	LP_I2C_SR_RXFIFO_CNT_Pos = 0x8
	// Bit mask of RXFIFO_CNT field.
	LP_I2C_SR_RXFIFO_CNT_Msk = 0x1f00
	// Position of TXFIFO_CNT field.
	LP_I2C_SR_TXFIFO_CNT_Pos = 0x12
	// Bit mask of TXFIFO_CNT field.
	LP_I2C_SR_TXFIFO_CNT_Msk = 0x7c0000
	// Position of SCL_MAIN_STATE_LAST field.
	LP_I2C_SR_SCL_MAIN_STATE_LAST_Pos = 0x18
	// Bit mask of SCL_MAIN_STATE_LAST field.
	LP_I2C_SR_SCL_MAIN_STATE_LAST_Msk = 0x7000000
	// Position of SCL_STATE_LAST field.
	LP_I2C_SR_SCL_STATE_LAST_Pos = 0x1c
	// Bit mask of SCL_STATE_LAST field.
	LP_I2C_SR_SCL_STATE_LAST_Msk = 0x70000000

	// TO: Setting time out control for receiving data.
	// Position of TIME_OUT_VALUE field.
	LP_I2C_TO_TIME_OUT_VALUE_Pos = 0x0
	// Bit mask of TIME_OUT_VALUE field.
	LP_I2C_TO_TIME_OUT_VALUE_Msk = 0x1f
	// Position of TIME_OUT_EN field.
	LP_I2C_TO_TIME_OUT_EN_Pos = 0x5
	// Bit mask of TIME_OUT_EN field.
	LP_I2C_TO_TIME_OUT_EN_Msk = 0x20
	// Bit TIME_OUT_EN.
	LP_I2C_TO_TIME_OUT_EN = 0x20

	// FIFO_ST: FIFO status register.
	// Position of RXFIFO_RADDR field.
	LP_I2C_FIFO_ST_RXFIFO_RADDR_Pos = 0x0
	// Bit mask of RXFIFO_RADDR field.
	LP_I2C_FIFO_ST_RXFIFO_RADDR_Msk = 0xf
	// Position of RXFIFO_WADDR field.
	LP_I2C_FIFO_ST_RXFIFO_WADDR_Pos = 0x5
	// Bit mask of RXFIFO_WADDR field.
	LP_I2C_FIFO_ST_RXFIFO_WADDR_Msk = 0x1e0
	// Position of TXFIFO_RADDR field.
	LP_I2C_FIFO_ST_TXFIFO_RADDR_Pos = 0xa
	// Bit mask of TXFIFO_RADDR field.
	LP_I2C_FIFO_ST_TXFIFO_RADDR_Msk = 0x3c00
	// Position of TXFIFO_WADDR field.
	LP_I2C_FIFO_ST_TXFIFO_WADDR_Pos = 0xf
	// Bit mask of TXFIFO_WADDR field.
	LP_I2C_FIFO_ST_TXFIFO_WADDR_Msk = 0x78000

	// FIFO_CONF: FIFO configuration register.
	// Position of RXFIFO_WM_THRHD field.
	LP_I2C_FIFO_CONF_RXFIFO_WM_THRHD_Pos = 0x0
	// Bit mask of RXFIFO_WM_THRHD field.
	LP_I2C_FIFO_CONF_RXFIFO_WM_THRHD_Msk = 0xf
	// Position of TXFIFO_WM_THRHD field.
	LP_I2C_FIFO_CONF_TXFIFO_WM_THRHD_Pos = 0x5
	// Bit mask of TXFIFO_WM_THRHD field.
	LP_I2C_FIFO_CONF_TXFIFO_WM_THRHD_Msk = 0x1e0
	// Position of NONFIFO_EN field.
	LP_I2C_FIFO_CONF_NONFIFO_EN_Pos = 0xa
	// Bit mask of NONFIFO_EN field.
	LP_I2C_FIFO_CONF_NONFIFO_EN_Msk = 0x400
	// Bit NONFIFO_EN.
	LP_I2C_FIFO_CONF_NONFIFO_EN = 0x400
	// Position of RX_FIFO_RST field.
	LP_I2C_FIFO_CONF_RX_FIFO_RST_Pos = 0xc
	// Bit mask of RX_FIFO_RST field.
	LP_I2C_FIFO_CONF_RX_FIFO_RST_Msk = 0x1000
	// Bit RX_FIFO_RST.
	LP_I2C_FIFO_CONF_RX_FIFO_RST = 0x1000
	// Position of TX_FIFO_RST field.
	LP_I2C_FIFO_CONF_TX_FIFO_RST_Pos = 0xd
	// Bit mask of TX_FIFO_RST field.
	LP_I2C_FIFO_CONF_TX_FIFO_RST_Msk = 0x2000
	// Bit TX_FIFO_RST.
	LP_I2C_FIFO_CONF_TX_FIFO_RST = 0x2000
	// Position of FIFO_PRT_EN field.
	LP_I2C_FIFO_CONF_FIFO_PRT_EN_Pos = 0xe
	// Bit mask of FIFO_PRT_EN field.
	LP_I2C_FIFO_CONF_FIFO_PRT_EN_Msk = 0x4000
	// Bit FIFO_PRT_EN.
	LP_I2C_FIFO_CONF_FIFO_PRT_EN = 0x4000

	// DATA: Rx FIFO read data.
	// Position of FIFO_RDATA field.
	LP_I2C_DATA_FIFO_RDATA_Pos = 0x0
	// Bit mask of FIFO_RDATA field.
	LP_I2C_DATA_FIFO_RDATA_Msk = 0xff

	// INT_RAW: Raw interrupt status
	// Position of RXFIFO_WM_INT_RAW field.
	LP_I2C_INT_RAW_RXFIFO_WM_INT_RAW_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_RAW field.
	LP_I2C_INT_RAW_RXFIFO_WM_INT_RAW_Msk = 0x1
	// Bit RXFIFO_WM_INT_RAW.
	LP_I2C_INT_RAW_RXFIFO_WM_INT_RAW = 0x1
	// Position of TXFIFO_WM_INT_RAW field.
	LP_I2C_INT_RAW_TXFIFO_WM_INT_RAW_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_RAW field.
	LP_I2C_INT_RAW_TXFIFO_WM_INT_RAW_Msk = 0x2
	// Bit TXFIFO_WM_INT_RAW.
	LP_I2C_INT_RAW_TXFIFO_WM_INT_RAW = 0x2
	// Position of RXFIFO_OVF_INT_RAW field.
	LP_I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_RAW field.
	LP_I2C_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x4
	// Bit RXFIFO_OVF_INT_RAW.
	LP_I2C_INT_RAW_RXFIFO_OVF_INT_RAW = 0x4
	// Position of END_DETECT_INT_RAW field.
	LP_I2C_INT_RAW_END_DETECT_INT_RAW_Pos = 0x3
	// Bit mask of END_DETECT_INT_RAW field.
	LP_I2C_INT_RAW_END_DETECT_INT_RAW_Msk = 0x8
	// Bit END_DETECT_INT_RAW.
	LP_I2C_INT_RAW_END_DETECT_INT_RAW = 0x8
	// Position of BYTE_TRANS_DONE_INT_RAW field.
	LP_I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_RAW field.
	LP_I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_RAW.
	LP_I2C_INT_RAW_BYTE_TRANS_DONE_INT_RAW = 0x10
	// Position of ARBITRATION_LOST_INT_RAW field.
	LP_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_RAW field.
	LP_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_RAW.
	LP_I2C_INT_RAW_ARBITRATION_LOST_INT_RAW = 0x20
	// Position of MST_TXFIFO_UDF_INT_RAW field.
	LP_I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_RAW field.
	LP_I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_RAW.
	LP_I2C_INT_RAW_MST_TXFIFO_UDF_INT_RAW = 0x40
	// Position of TRANS_COMPLETE_INT_RAW field.
	LP_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_RAW field.
	LP_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_RAW.
	LP_I2C_INT_RAW_TRANS_COMPLETE_INT_RAW = 0x80
	// Position of TIME_OUT_INT_RAW field.
	LP_I2C_INT_RAW_TIME_OUT_INT_RAW_Pos = 0x8
	// Bit mask of TIME_OUT_INT_RAW field.
	LP_I2C_INT_RAW_TIME_OUT_INT_RAW_Msk = 0x100
	// Bit TIME_OUT_INT_RAW.
	LP_I2C_INT_RAW_TIME_OUT_INT_RAW = 0x100
	// Position of TRANS_START_INT_RAW field.
	LP_I2C_INT_RAW_TRANS_START_INT_RAW_Pos = 0x9
	// Bit mask of TRANS_START_INT_RAW field.
	LP_I2C_INT_RAW_TRANS_START_INT_RAW_Msk = 0x200
	// Bit TRANS_START_INT_RAW.
	LP_I2C_INT_RAW_TRANS_START_INT_RAW = 0x200
	// Position of NACK_INT_RAW field.
	LP_I2C_INT_RAW_NACK_INT_RAW_Pos = 0xa
	// Bit mask of NACK_INT_RAW field.
	LP_I2C_INT_RAW_NACK_INT_RAW_Msk = 0x400
	// Bit NACK_INT_RAW.
	LP_I2C_INT_RAW_NACK_INT_RAW = 0x400
	// Position of TXFIFO_OVF_INT_RAW field.
	LP_I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_RAW field.
	LP_I2C_INT_RAW_TXFIFO_OVF_INT_RAW_Msk = 0x800
	// Bit TXFIFO_OVF_INT_RAW.
	LP_I2C_INT_RAW_TXFIFO_OVF_INT_RAW = 0x800
	// Position of RXFIFO_UDF_INT_RAW field.
	LP_I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_RAW field.
	LP_I2C_INT_RAW_RXFIFO_UDF_INT_RAW_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_RAW.
	LP_I2C_INT_RAW_RXFIFO_UDF_INT_RAW = 0x1000
	// Position of SCL_ST_TO_INT_RAW field.
	LP_I2C_INT_RAW_SCL_ST_TO_INT_RAW_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_RAW field.
	LP_I2C_INT_RAW_SCL_ST_TO_INT_RAW_Msk = 0x2000
	// Bit SCL_ST_TO_INT_RAW.
	LP_I2C_INT_RAW_SCL_ST_TO_INT_RAW = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_RAW field.
	LP_I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_RAW field.
	LP_I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_RAW.
	LP_I2C_INT_RAW_SCL_MAIN_ST_TO_INT_RAW = 0x4000
	// Position of DET_START_INT_RAW field.
	LP_I2C_INT_RAW_DET_START_INT_RAW_Pos = 0xf
	// Bit mask of DET_START_INT_RAW field.
	LP_I2C_INT_RAW_DET_START_INT_RAW_Msk = 0x8000
	// Bit DET_START_INT_RAW.
	LP_I2C_INT_RAW_DET_START_INT_RAW = 0x8000

	// INT_CLR: Interrupt clear bits
	// Position of RXFIFO_WM_INT_CLR field.
	LP_I2C_INT_CLR_RXFIFO_WM_INT_CLR_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_CLR field.
	LP_I2C_INT_CLR_RXFIFO_WM_INT_CLR_Msk = 0x1
	// Bit RXFIFO_WM_INT_CLR.
	LP_I2C_INT_CLR_RXFIFO_WM_INT_CLR = 0x1
	// Position of TXFIFO_WM_INT_CLR field.
	LP_I2C_INT_CLR_TXFIFO_WM_INT_CLR_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_CLR field.
	LP_I2C_INT_CLR_TXFIFO_WM_INT_CLR_Msk = 0x2
	// Bit TXFIFO_WM_INT_CLR.
	LP_I2C_INT_CLR_TXFIFO_WM_INT_CLR = 0x2
	// Position of RXFIFO_OVF_INT_CLR field.
	LP_I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_CLR field.
	LP_I2C_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x4
	// Bit RXFIFO_OVF_INT_CLR.
	LP_I2C_INT_CLR_RXFIFO_OVF_INT_CLR = 0x4
	// Position of END_DETECT_INT_CLR field.
	LP_I2C_INT_CLR_END_DETECT_INT_CLR_Pos = 0x3
	// Bit mask of END_DETECT_INT_CLR field.
	LP_I2C_INT_CLR_END_DETECT_INT_CLR_Msk = 0x8
	// Bit END_DETECT_INT_CLR.
	LP_I2C_INT_CLR_END_DETECT_INT_CLR = 0x8
	// Position of BYTE_TRANS_DONE_INT_CLR field.
	LP_I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_CLR field.
	LP_I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_CLR.
	LP_I2C_INT_CLR_BYTE_TRANS_DONE_INT_CLR = 0x10
	// Position of ARBITRATION_LOST_INT_CLR field.
	LP_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_CLR field.
	LP_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_CLR.
	LP_I2C_INT_CLR_ARBITRATION_LOST_INT_CLR = 0x20
	// Position of MST_TXFIFO_UDF_INT_CLR field.
	LP_I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_CLR field.
	LP_I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_CLR.
	LP_I2C_INT_CLR_MST_TXFIFO_UDF_INT_CLR = 0x40
	// Position of TRANS_COMPLETE_INT_CLR field.
	LP_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_CLR field.
	LP_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_CLR.
	LP_I2C_INT_CLR_TRANS_COMPLETE_INT_CLR = 0x80
	// Position of TIME_OUT_INT_CLR field.
	LP_I2C_INT_CLR_TIME_OUT_INT_CLR_Pos = 0x8
	// Bit mask of TIME_OUT_INT_CLR field.
	LP_I2C_INT_CLR_TIME_OUT_INT_CLR_Msk = 0x100
	// Bit TIME_OUT_INT_CLR.
	LP_I2C_INT_CLR_TIME_OUT_INT_CLR = 0x100
	// Position of TRANS_START_INT_CLR field.
	LP_I2C_INT_CLR_TRANS_START_INT_CLR_Pos = 0x9
	// Bit mask of TRANS_START_INT_CLR field.
	LP_I2C_INT_CLR_TRANS_START_INT_CLR_Msk = 0x200
	// Bit TRANS_START_INT_CLR.
	LP_I2C_INT_CLR_TRANS_START_INT_CLR = 0x200
	// Position of NACK_INT_CLR field.
	LP_I2C_INT_CLR_NACK_INT_CLR_Pos = 0xa
	// Bit mask of NACK_INT_CLR field.
	LP_I2C_INT_CLR_NACK_INT_CLR_Msk = 0x400
	// Bit NACK_INT_CLR.
	LP_I2C_INT_CLR_NACK_INT_CLR = 0x400
	// Position of TXFIFO_OVF_INT_CLR field.
	LP_I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_CLR field.
	LP_I2C_INT_CLR_TXFIFO_OVF_INT_CLR_Msk = 0x800
	// Bit TXFIFO_OVF_INT_CLR.
	LP_I2C_INT_CLR_TXFIFO_OVF_INT_CLR = 0x800
	// Position of RXFIFO_UDF_INT_CLR field.
	LP_I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_CLR field.
	LP_I2C_INT_CLR_RXFIFO_UDF_INT_CLR_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_CLR.
	LP_I2C_INT_CLR_RXFIFO_UDF_INT_CLR = 0x1000
	// Position of SCL_ST_TO_INT_CLR field.
	LP_I2C_INT_CLR_SCL_ST_TO_INT_CLR_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_CLR field.
	LP_I2C_INT_CLR_SCL_ST_TO_INT_CLR_Msk = 0x2000
	// Bit SCL_ST_TO_INT_CLR.
	LP_I2C_INT_CLR_SCL_ST_TO_INT_CLR = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_CLR field.
	LP_I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_CLR field.
	LP_I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_CLR.
	LP_I2C_INT_CLR_SCL_MAIN_ST_TO_INT_CLR = 0x4000
	// Position of DET_START_INT_CLR field.
	LP_I2C_INT_CLR_DET_START_INT_CLR_Pos = 0xf
	// Bit mask of DET_START_INT_CLR field.
	LP_I2C_INT_CLR_DET_START_INT_CLR_Msk = 0x8000
	// Bit DET_START_INT_CLR.
	LP_I2C_INT_CLR_DET_START_INT_CLR = 0x8000

	// INT_ENA: Interrupt enable bits
	// Position of RXFIFO_WM_INT_ENA field.
	LP_I2C_INT_ENA_RXFIFO_WM_INT_ENA_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_ENA field.
	LP_I2C_INT_ENA_RXFIFO_WM_INT_ENA_Msk = 0x1
	// Bit RXFIFO_WM_INT_ENA.
	LP_I2C_INT_ENA_RXFIFO_WM_INT_ENA = 0x1
	// Position of TXFIFO_WM_INT_ENA field.
	LP_I2C_INT_ENA_TXFIFO_WM_INT_ENA_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_ENA field.
	LP_I2C_INT_ENA_TXFIFO_WM_INT_ENA_Msk = 0x2
	// Bit TXFIFO_WM_INT_ENA.
	LP_I2C_INT_ENA_TXFIFO_WM_INT_ENA = 0x2
	// Position of RXFIFO_OVF_INT_ENA field.
	LP_I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_ENA field.
	LP_I2C_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x4
	// Bit RXFIFO_OVF_INT_ENA.
	LP_I2C_INT_ENA_RXFIFO_OVF_INT_ENA = 0x4
	// Position of END_DETECT_INT_ENA field.
	LP_I2C_INT_ENA_END_DETECT_INT_ENA_Pos = 0x3
	// Bit mask of END_DETECT_INT_ENA field.
	LP_I2C_INT_ENA_END_DETECT_INT_ENA_Msk = 0x8
	// Bit END_DETECT_INT_ENA.
	LP_I2C_INT_ENA_END_DETECT_INT_ENA = 0x8
	// Position of BYTE_TRANS_DONE_INT_ENA field.
	LP_I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_ENA field.
	LP_I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_ENA.
	LP_I2C_INT_ENA_BYTE_TRANS_DONE_INT_ENA = 0x10
	// Position of ARBITRATION_LOST_INT_ENA field.
	LP_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_ENA field.
	LP_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_ENA.
	LP_I2C_INT_ENA_ARBITRATION_LOST_INT_ENA = 0x20
	// Position of MST_TXFIFO_UDF_INT_ENA field.
	LP_I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_ENA field.
	LP_I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_ENA.
	LP_I2C_INT_ENA_MST_TXFIFO_UDF_INT_ENA = 0x40
	// Position of TRANS_COMPLETE_INT_ENA field.
	LP_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_ENA field.
	LP_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_ENA.
	LP_I2C_INT_ENA_TRANS_COMPLETE_INT_ENA = 0x80
	// Position of TIME_OUT_INT_ENA field.
	LP_I2C_INT_ENA_TIME_OUT_INT_ENA_Pos = 0x8
	// Bit mask of TIME_OUT_INT_ENA field.
	LP_I2C_INT_ENA_TIME_OUT_INT_ENA_Msk = 0x100
	// Bit TIME_OUT_INT_ENA.
	LP_I2C_INT_ENA_TIME_OUT_INT_ENA = 0x100
	// Position of TRANS_START_INT_ENA field.
	LP_I2C_INT_ENA_TRANS_START_INT_ENA_Pos = 0x9
	// Bit mask of TRANS_START_INT_ENA field.
	LP_I2C_INT_ENA_TRANS_START_INT_ENA_Msk = 0x200
	// Bit TRANS_START_INT_ENA.
	LP_I2C_INT_ENA_TRANS_START_INT_ENA = 0x200
	// Position of NACK_INT_ENA field.
	LP_I2C_INT_ENA_NACK_INT_ENA_Pos = 0xa
	// Bit mask of NACK_INT_ENA field.
	LP_I2C_INT_ENA_NACK_INT_ENA_Msk = 0x400
	// Bit NACK_INT_ENA.
	LP_I2C_INT_ENA_NACK_INT_ENA = 0x400
	// Position of TXFIFO_OVF_INT_ENA field.
	LP_I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_ENA field.
	LP_I2C_INT_ENA_TXFIFO_OVF_INT_ENA_Msk = 0x800
	// Bit TXFIFO_OVF_INT_ENA.
	LP_I2C_INT_ENA_TXFIFO_OVF_INT_ENA = 0x800
	// Position of RXFIFO_UDF_INT_ENA field.
	LP_I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_ENA field.
	LP_I2C_INT_ENA_RXFIFO_UDF_INT_ENA_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_ENA.
	LP_I2C_INT_ENA_RXFIFO_UDF_INT_ENA = 0x1000
	// Position of SCL_ST_TO_INT_ENA field.
	LP_I2C_INT_ENA_SCL_ST_TO_INT_ENA_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_ENA field.
	LP_I2C_INT_ENA_SCL_ST_TO_INT_ENA_Msk = 0x2000
	// Bit SCL_ST_TO_INT_ENA.
	LP_I2C_INT_ENA_SCL_ST_TO_INT_ENA = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_ENA field.
	LP_I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_ENA field.
	LP_I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_ENA.
	LP_I2C_INT_ENA_SCL_MAIN_ST_TO_INT_ENA = 0x4000
	// Position of DET_START_INT_ENA field.
	LP_I2C_INT_ENA_DET_START_INT_ENA_Pos = 0xf
	// Bit mask of DET_START_INT_ENA field.
	LP_I2C_INT_ENA_DET_START_INT_ENA_Msk = 0x8000
	// Bit DET_START_INT_ENA.
	LP_I2C_INT_ENA_DET_START_INT_ENA = 0x8000

	// INT_STATUS: Status of captured I2C communication events
	// Position of RXFIFO_WM_INT_ST field.
	LP_I2C_INT_STATUS_RXFIFO_WM_INT_ST_Pos = 0x0
	// Bit mask of RXFIFO_WM_INT_ST field.
	LP_I2C_INT_STATUS_RXFIFO_WM_INT_ST_Msk = 0x1
	// Bit RXFIFO_WM_INT_ST.
	LP_I2C_INT_STATUS_RXFIFO_WM_INT_ST = 0x1
	// Position of TXFIFO_WM_INT_ST field.
	LP_I2C_INT_STATUS_TXFIFO_WM_INT_ST_Pos = 0x1
	// Bit mask of TXFIFO_WM_INT_ST field.
	LP_I2C_INT_STATUS_TXFIFO_WM_INT_ST_Msk = 0x2
	// Bit TXFIFO_WM_INT_ST.
	LP_I2C_INT_STATUS_TXFIFO_WM_INT_ST = 0x2
	// Position of RXFIFO_OVF_INT_ST field.
	LP_I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Pos = 0x2
	// Bit mask of RXFIFO_OVF_INT_ST field.
	LP_I2C_INT_STATUS_RXFIFO_OVF_INT_ST_Msk = 0x4
	// Bit RXFIFO_OVF_INT_ST.
	LP_I2C_INT_STATUS_RXFIFO_OVF_INT_ST = 0x4
	// Position of END_DETECT_INT_ST field.
	LP_I2C_INT_STATUS_END_DETECT_INT_ST_Pos = 0x3
	// Bit mask of END_DETECT_INT_ST field.
	LP_I2C_INT_STATUS_END_DETECT_INT_ST_Msk = 0x8
	// Bit END_DETECT_INT_ST.
	LP_I2C_INT_STATUS_END_DETECT_INT_ST = 0x8
	// Position of BYTE_TRANS_DONE_INT_ST field.
	LP_I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Pos = 0x4
	// Bit mask of BYTE_TRANS_DONE_INT_ST field.
	LP_I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST_Msk = 0x10
	// Bit BYTE_TRANS_DONE_INT_ST.
	LP_I2C_INT_STATUS_BYTE_TRANS_DONE_INT_ST = 0x10
	// Position of ARBITRATION_LOST_INT_ST field.
	LP_I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Pos = 0x5
	// Bit mask of ARBITRATION_LOST_INT_ST field.
	LP_I2C_INT_STATUS_ARBITRATION_LOST_INT_ST_Msk = 0x20
	// Bit ARBITRATION_LOST_INT_ST.
	LP_I2C_INT_STATUS_ARBITRATION_LOST_INT_ST = 0x20
	// Position of MST_TXFIFO_UDF_INT_ST field.
	LP_I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Pos = 0x6
	// Bit mask of MST_TXFIFO_UDF_INT_ST field.
	LP_I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST_Msk = 0x40
	// Bit MST_TXFIFO_UDF_INT_ST.
	LP_I2C_INT_STATUS_MST_TXFIFO_UDF_INT_ST = 0x40
	// Position of TRANS_COMPLETE_INT_ST field.
	LP_I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Pos = 0x7
	// Bit mask of TRANS_COMPLETE_INT_ST field.
	LP_I2C_INT_STATUS_TRANS_COMPLETE_INT_ST_Msk = 0x80
	// Bit TRANS_COMPLETE_INT_ST.
	LP_I2C_INT_STATUS_TRANS_COMPLETE_INT_ST = 0x80
	// Position of TIME_OUT_INT_ST field.
	LP_I2C_INT_STATUS_TIME_OUT_INT_ST_Pos = 0x8
	// Bit mask of TIME_OUT_INT_ST field.
	LP_I2C_INT_STATUS_TIME_OUT_INT_ST_Msk = 0x100
	// Bit TIME_OUT_INT_ST.
	LP_I2C_INT_STATUS_TIME_OUT_INT_ST = 0x100
	// Position of TRANS_START_INT_ST field.
	LP_I2C_INT_STATUS_TRANS_START_INT_ST_Pos = 0x9
	// Bit mask of TRANS_START_INT_ST field.
	LP_I2C_INT_STATUS_TRANS_START_INT_ST_Msk = 0x200
	// Bit TRANS_START_INT_ST.
	LP_I2C_INT_STATUS_TRANS_START_INT_ST = 0x200
	// Position of NACK_INT_ST field.
	LP_I2C_INT_STATUS_NACK_INT_ST_Pos = 0xa
	// Bit mask of NACK_INT_ST field.
	LP_I2C_INT_STATUS_NACK_INT_ST_Msk = 0x400
	// Bit NACK_INT_ST.
	LP_I2C_INT_STATUS_NACK_INT_ST = 0x400
	// Position of TXFIFO_OVF_INT_ST field.
	LP_I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Pos = 0xb
	// Bit mask of TXFIFO_OVF_INT_ST field.
	LP_I2C_INT_STATUS_TXFIFO_OVF_INT_ST_Msk = 0x800
	// Bit TXFIFO_OVF_INT_ST.
	LP_I2C_INT_STATUS_TXFIFO_OVF_INT_ST = 0x800
	// Position of RXFIFO_UDF_INT_ST field.
	LP_I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Pos = 0xc
	// Bit mask of RXFIFO_UDF_INT_ST field.
	LP_I2C_INT_STATUS_RXFIFO_UDF_INT_ST_Msk = 0x1000
	// Bit RXFIFO_UDF_INT_ST.
	LP_I2C_INT_STATUS_RXFIFO_UDF_INT_ST = 0x1000
	// Position of SCL_ST_TO_INT_ST field.
	LP_I2C_INT_STATUS_SCL_ST_TO_INT_ST_Pos = 0xd
	// Bit mask of SCL_ST_TO_INT_ST field.
	LP_I2C_INT_STATUS_SCL_ST_TO_INT_ST_Msk = 0x2000
	// Bit SCL_ST_TO_INT_ST.
	LP_I2C_INT_STATUS_SCL_ST_TO_INT_ST = 0x2000
	// Position of SCL_MAIN_ST_TO_INT_ST field.
	LP_I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Pos = 0xe
	// Bit mask of SCL_MAIN_ST_TO_INT_ST field.
	LP_I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST_Msk = 0x4000
	// Bit SCL_MAIN_ST_TO_INT_ST.
	LP_I2C_INT_STATUS_SCL_MAIN_ST_TO_INT_ST = 0x4000
	// Position of DET_START_INT_ST field.
	LP_I2C_INT_STATUS_DET_START_INT_ST_Pos = 0xf
	// Bit mask of DET_START_INT_ST field.
	LP_I2C_INT_STATUS_DET_START_INT_ST_Msk = 0x8000
	// Bit DET_START_INT_ST.
	LP_I2C_INT_STATUS_DET_START_INT_ST = 0x8000

	// SDA_HOLD: Configures the hold time after a negative SCL edge.
	// Position of TIME field.
	LP_I2C_SDA_HOLD_TIME_Pos = 0x0
	// Bit mask of TIME field.
	LP_I2C_SDA_HOLD_TIME_Msk = 0x1ff

	// SDA_SAMPLE: Configures the sample time after a positive SCL edge.
	// Position of TIME field.
	LP_I2C_SDA_SAMPLE_TIME_Pos = 0x0
	// Bit mask of TIME field.
	LP_I2C_SDA_SAMPLE_TIME_Msk = 0x1ff

	// SCL_HIGH_PERIOD: Configures the high level width of SCL
	// Position of SCL_HIGH_PERIOD field.
	LP_I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Pos = 0x0
	// Bit mask of SCL_HIGH_PERIOD field.
	LP_I2C_SCL_HIGH_PERIOD_SCL_HIGH_PERIOD_Msk = 0x1ff
	// Position of SCL_WAIT_HIGH_PERIOD field.
	LP_I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Pos = 0x9
	// Bit mask of SCL_WAIT_HIGH_PERIOD field.
	LP_I2C_SCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD_Msk = 0xfe00

	// SCL_START_HOLD: Configures the delay between the SDA and SCL negative edge for a start condition
	// Position of TIME field.
	LP_I2C_SCL_START_HOLD_TIME_Pos = 0x0
	// Bit mask of TIME field.
	LP_I2C_SCL_START_HOLD_TIME_Msk = 0x1ff

	// SCL_RSTART_SETUP: Configures the delay between the positive edge of SCL and the negative edge of SDA
	// Position of TIME field.
	LP_I2C_SCL_RSTART_SETUP_TIME_Pos = 0x0
	// Bit mask of TIME field.
	LP_I2C_SCL_RSTART_SETUP_TIME_Msk = 0x1ff

	// SCL_STOP_HOLD: Configures the delay after the SCL clock edge for a stop condition
	// Position of TIME field.
	LP_I2C_SCL_STOP_HOLD_TIME_Pos = 0x0
	// Bit mask of TIME field.
	LP_I2C_SCL_STOP_HOLD_TIME_Msk = 0x1ff

	// SCL_STOP_SETUP: Configures the delay between the SDA and SCL positive edge for a stop condition
	// Position of TIME field.
	LP_I2C_SCL_STOP_SETUP_TIME_Pos = 0x0
	// Bit mask of TIME field.
	LP_I2C_SCL_STOP_SETUP_TIME_Msk = 0x1ff

	// FILTER_CFG: SCL and SDA filter configuration register
	// Position of SCL_FILTER_THRES field.
	LP_I2C_FILTER_CFG_SCL_FILTER_THRES_Pos = 0x0
	// Bit mask of SCL_FILTER_THRES field.
	LP_I2C_FILTER_CFG_SCL_FILTER_THRES_Msk = 0xf
	// Position of SDA_FILTER_THRES field.
	LP_I2C_FILTER_CFG_SDA_FILTER_THRES_Pos = 0x4
	// Bit mask of SDA_FILTER_THRES field.
	LP_I2C_FILTER_CFG_SDA_FILTER_THRES_Msk = 0xf0
	// Position of SCL_FILTER_EN field.
	LP_I2C_FILTER_CFG_SCL_FILTER_EN_Pos = 0x8
	// Bit mask of SCL_FILTER_EN field.
	LP_I2C_FILTER_CFG_SCL_FILTER_EN_Msk = 0x100
	// Bit SCL_FILTER_EN.
	LP_I2C_FILTER_CFG_SCL_FILTER_EN = 0x100
	// Position of SDA_FILTER_EN field.
	LP_I2C_FILTER_CFG_SDA_FILTER_EN_Pos = 0x9
	// Bit mask of SDA_FILTER_EN field.
	LP_I2C_FILTER_CFG_SDA_FILTER_EN_Msk = 0x200
	// Bit SDA_FILTER_EN.
	LP_I2C_FILTER_CFG_SDA_FILTER_EN = 0x200

	// CLK_CONF: I2C CLK configuration register
	// Position of SCLK_DIV_NUM field.
	LP_I2C_CLK_CONF_SCLK_DIV_NUM_Pos = 0x0
	// Bit mask of SCLK_DIV_NUM field.
	LP_I2C_CLK_CONF_SCLK_DIV_NUM_Msk = 0xff
	// Position of SCLK_DIV_A field.
	LP_I2C_CLK_CONF_SCLK_DIV_A_Pos = 0x8
	// Bit mask of SCLK_DIV_A field.
	LP_I2C_CLK_CONF_SCLK_DIV_A_Msk = 0x3f00
	// Position of SCLK_DIV_B field.
	LP_I2C_CLK_CONF_SCLK_DIV_B_Pos = 0xe
	// Bit mask of SCLK_DIV_B field.
	LP_I2C_CLK_CONF_SCLK_DIV_B_Msk = 0xfc000
	// Position of SCLK_SEL field.
	LP_I2C_CLK_CONF_SCLK_SEL_Pos = 0x14
	// Bit mask of SCLK_SEL field.
	LP_I2C_CLK_CONF_SCLK_SEL_Msk = 0x100000
	// Bit SCLK_SEL.
	LP_I2C_CLK_CONF_SCLK_SEL = 0x100000
	// Position of SCLK_ACTIVE field.
	LP_I2C_CLK_CONF_SCLK_ACTIVE_Pos = 0x15
	// Bit mask of SCLK_ACTIVE field.
	LP_I2C_CLK_CONF_SCLK_ACTIVE_Msk = 0x200000
	// Bit SCLK_ACTIVE.
	LP_I2C_CLK_CONF_SCLK_ACTIVE = 0x200000

	// COMD0: I2C command register 0
	// Position of COMMAND0 field.
	LP_I2C_COMD0_COMMAND0_Pos = 0x0
	// Bit mask of COMMAND0 field.
	LP_I2C_COMD0_COMMAND0_Msk = 0x3fff
	// Position of COMMAND0_DONE field.
	LP_I2C_COMD0_COMMAND0_DONE_Pos = 0x1f
	// Bit mask of COMMAND0_DONE field.
	LP_I2C_COMD0_COMMAND0_DONE_Msk = 0x80000000
	// Bit COMMAND0_DONE.
	LP_I2C_COMD0_COMMAND0_DONE = 0x80000000

	// COMD1: I2C command register 1
	// Position of COMMAND1 field.
	LP_I2C_COMD1_COMMAND1_Pos = 0x0
	// Bit mask of COMMAND1 field.
	LP_I2C_COMD1_COMMAND1_Msk = 0x3fff
	// Position of COMMAND1_DONE field.
	LP_I2C_COMD1_COMMAND1_DONE_Pos = 0x1f
	// Bit mask of COMMAND1_DONE field.
	LP_I2C_COMD1_COMMAND1_DONE_Msk = 0x80000000
	// Bit COMMAND1_DONE.
	LP_I2C_COMD1_COMMAND1_DONE = 0x80000000

	// COMD2: I2C command register 2
	// Position of COMMAND2 field.
	LP_I2C_COMD2_COMMAND2_Pos = 0x0
	// Bit mask of COMMAND2 field.
	LP_I2C_COMD2_COMMAND2_Msk = 0x3fff
	// Position of COMMAND2_DONE field.
	LP_I2C_COMD2_COMMAND2_DONE_Pos = 0x1f
	// Bit mask of COMMAND2_DONE field.
	LP_I2C_COMD2_COMMAND2_DONE_Msk = 0x80000000
	// Bit COMMAND2_DONE.
	LP_I2C_COMD2_COMMAND2_DONE = 0x80000000

	// COMD3: I2C command register 3
	// Position of COMMAND3 field.
	LP_I2C_COMD3_COMMAND3_Pos = 0x0
	// Bit mask of COMMAND3 field.
	LP_I2C_COMD3_COMMAND3_Msk = 0x3fff
	// Position of COMMAND3_DONE field.
	LP_I2C_COMD3_COMMAND3_DONE_Pos = 0x1f
	// Bit mask of COMMAND3_DONE field.
	LP_I2C_COMD3_COMMAND3_DONE_Msk = 0x80000000
	// Bit COMMAND3_DONE.
	LP_I2C_COMD3_COMMAND3_DONE = 0x80000000

	// COMD4: I2C command register 4
	// Position of COMMAND4 field.
	LP_I2C_COMD4_COMMAND4_Pos = 0x0
	// Bit mask of COMMAND4 field.
	LP_I2C_COMD4_COMMAND4_Msk = 0x3fff
	// Position of COMMAND4_DONE field.
	LP_I2C_COMD4_COMMAND4_DONE_Pos = 0x1f
	// Bit mask of COMMAND4_DONE field.
	LP_I2C_COMD4_COMMAND4_DONE_Msk = 0x80000000
	// Bit COMMAND4_DONE.
	LP_I2C_COMD4_COMMAND4_DONE = 0x80000000

	// COMD5: I2C command register 5
	// Position of COMMAND5 field.
	LP_I2C_COMD5_COMMAND5_Pos = 0x0
	// Bit mask of COMMAND5 field.
	LP_I2C_COMD5_COMMAND5_Msk = 0x3fff
	// Position of COMMAND5_DONE field.
	LP_I2C_COMD5_COMMAND5_DONE_Pos = 0x1f
	// Bit mask of COMMAND5_DONE field.
	LP_I2C_COMD5_COMMAND5_DONE_Msk = 0x80000000
	// Bit COMMAND5_DONE.
	LP_I2C_COMD5_COMMAND5_DONE = 0x80000000

	// COMD6: I2C command register 6
	// Position of COMMAND6 field.
	LP_I2C_COMD6_COMMAND6_Pos = 0x0
	// Bit mask of COMMAND6 field.
	LP_I2C_COMD6_COMMAND6_Msk = 0x3fff
	// Position of COMMAND6_DONE field.
	LP_I2C_COMD6_COMMAND6_DONE_Pos = 0x1f
	// Bit mask of COMMAND6_DONE field.
	LP_I2C_COMD6_COMMAND6_DONE_Msk = 0x80000000
	// Bit COMMAND6_DONE.
	LP_I2C_COMD6_COMMAND6_DONE = 0x80000000

	// COMD7: I2C command register 7
	// Position of COMMAND7 field.
	LP_I2C_COMD7_COMMAND7_Pos = 0x0
	// Bit mask of COMMAND7 field.
	LP_I2C_COMD7_COMMAND7_Msk = 0x3fff
	// Position of COMMAND7_DONE field.
	LP_I2C_COMD7_COMMAND7_DONE_Pos = 0x1f
	// Bit mask of COMMAND7_DONE field.
	LP_I2C_COMD7_COMMAND7_DONE_Msk = 0x80000000
	// Bit COMMAND7_DONE.
	LP_I2C_COMD7_COMMAND7_DONE = 0x80000000

	// SCL_ST_TIME_OUT: SCL status time out register
	// Position of SCL_ST_TO_I2C field.
	LP_I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Pos = 0x0
	// Bit mask of SCL_ST_TO_I2C field.
	LP_I2C_SCL_ST_TIME_OUT_SCL_ST_TO_I2C_Msk = 0x1f

	// SCL_MAIN_ST_TIME_OUT: SCL main status time out register
	// Position of SCL_MAIN_ST_TO_I2C field.
	LP_I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Pos = 0x0
	// Bit mask of SCL_MAIN_ST_TO_I2C field.
	LP_I2C_SCL_MAIN_ST_TIME_OUT_SCL_MAIN_ST_TO_I2C_Msk = 0x1f

	// SCL_SP_CONF: Power configuration register
	// Position of SCL_RST_SLV_EN field.
	LP_I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Pos = 0x0
	// Bit mask of SCL_RST_SLV_EN field.
	LP_I2C_SCL_SP_CONF_SCL_RST_SLV_EN_Msk = 0x1
	// Bit SCL_RST_SLV_EN.
	LP_I2C_SCL_SP_CONF_SCL_RST_SLV_EN = 0x1
	// Position of SCL_RST_SLV_NUM field.
	LP_I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Pos = 0x1
	// Bit mask of SCL_RST_SLV_NUM field.
	LP_I2C_SCL_SP_CONF_SCL_RST_SLV_NUM_Msk = 0x3e
	// Position of SCL_PD_EN field.
	LP_I2C_SCL_SP_CONF_SCL_PD_EN_Pos = 0x6
	// Bit mask of SCL_PD_EN field.
	LP_I2C_SCL_SP_CONF_SCL_PD_EN_Msk = 0x40
	// Bit SCL_PD_EN.
	LP_I2C_SCL_SP_CONF_SCL_PD_EN = 0x40
	// Position of SDA_PD_EN field.
	LP_I2C_SCL_SP_CONF_SDA_PD_EN_Pos = 0x7
	// Bit mask of SDA_PD_EN field.
	LP_I2C_SCL_SP_CONF_SDA_PD_EN_Msk = 0x80
	// Bit SDA_PD_EN.
	LP_I2C_SCL_SP_CONF_SDA_PD_EN = 0x80

	// DATE: Version register
	// Position of DATE field.
	LP_I2C_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	LP_I2C_DATE_DATE_Msk = 0xffffffff

	// TXFIFO_START_ADDR: I2C TXFIFO base address register
	// Position of TXFIFO_START_ADDR field.
	LP_I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Pos = 0x0
	// Bit mask of TXFIFO_START_ADDR field.
	LP_I2C_TXFIFO_START_ADDR_TXFIFO_START_ADDR_Msk = 0xffffffff

	// RXFIFO_START_ADDR: I2C RXFIFO base address register
	// Position of RXFIFO_START_ADDR field.
	LP_I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Pos = 0x0
	// Bit mask of RXFIFO_START_ADDR field.
	LP_I2C_RXFIFO_START_ADDR_RXFIFO_START_ADDR_Msk = 0xffffffff
)

// Constants for LP_I2S0: Low-power I2S (Inter-IC Sound) Controller 0
const (
	// VAD_CONF: I2S VAD Configure register
	// Position of VAD_EN field.
	LP_I2S_VAD_CONF_VAD_EN_Pos = 0x0
	// Bit mask of VAD_EN field.
	LP_I2S_VAD_CONF_VAD_EN_Msk = 0x1
	// Bit VAD_EN.
	LP_I2S_VAD_CONF_VAD_EN = 0x1
	// Position of VAD_RESET field.
	LP_I2S_VAD_CONF_VAD_RESET_Pos = 0x1
	// Bit mask of VAD_RESET field.
	LP_I2S_VAD_CONF_VAD_RESET_Msk = 0x2
	// Bit VAD_RESET.
	LP_I2S_VAD_CONF_VAD_RESET = 0x2
	// Position of VAD_FORCE_START field.
	LP_I2S_VAD_CONF_VAD_FORCE_START_Pos = 0x2
	// Bit mask of VAD_FORCE_START field.
	LP_I2S_VAD_CONF_VAD_FORCE_START_Msk = 0x4
	// Bit VAD_FORCE_START.
	LP_I2S_VAD_CONF_VAD_FORCE_START = 0x4

	// VAD_RESULT: I2S VAD Result register
	// Position of VAD_FLAG field.
	LP_I2S_VAD_RESULT_VAD_FLAG_Pos = 0x0
	// Bit mask of VAD_FLAG field.
	LP_I2S_VAD_RESULT_VAD_FLAG_Msk = 0x1
	// Bit VAD_FLAG.
	LP_I2S_VAD_RESULT_VAD_FLAG = 0x1
	// Position of ENERGY_ENOUGH field.
	LP_I2S_VAD_RESULT_ENERGY_ENOUGH_Pos = 0x1
	// Bit mask of ENERGY_ENOUGH field.
	LP_I2S_VAD_RESULT_ENERGY_ENOUGH_Msk = 0x2
	// Bit ENERGY_ENOUGH.
	LP_I2S_VAD_RESULT_ENERGY_ENOUGH = 0x2

	// RX_MEM_CONF: I2S VAD Observe register
	// Position of RX_MEM_FIFO_CNT field.
	LP_I2S_RX_MEM_CONF_RX_MEM_FIFO_CNT_Pos = 0x0
	// Bit mask of RX_MEM_FIFO_CNT field.
	LP_I2S_RX_MEM_CONF_RX_MEM_FIFO_CNT_Msk = 0x1ff
	// Position of RX_MEM_THRESHOLD field.
	LP_I2S_RX_MEM_CONF_RX_MEM_THRESHOLD_Pos = 0x9
	// Bit mask of RX_MEM_THRESHOLD field.
	LP_I2S_RX_MEM_CONF_RX_MEM_THRESHOLD_Msk = 0x1fe00

	// INT_RAW: I2S interrupt raw register, valid in level.
	// Position of RX_DONE_INT_RAW field.
	LP_I2S_INT_RAW_RX_DONE_INT_RAW_Pos = 0x0
	// Bit mask of RX_DONE_INT_RAW field.
	LP_I2S_INT_RAW_RX_DONE_INT_RAW_Msk = 0x1
	// Bit RX_DONE_INT_RAW.
	LP_I2S_INT_RAW_RX_DONE_INT_RAW = 0x1
	// Position of RX_HUNG_INT_RAW field.
	LP_I2S_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x1
	// Bit mask of RX_HUNG_INT_RAW field.
	LP_I2S_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x2
	// Bit RX_HUNG_INT_RAW.
	LP_I2S_INT_RAW_RX_HUNG_INT_RAW = 0x2
	// Position of RX_FIFOMEM_UDF_INT_RAW field.
	LP_I2S_INT_RAW_RX_FIFOMEM_UDF_INT_RAW_Pos = 0x2
	// Bit mask of RX_FIFOMEM_UDF_INT_RAW field.
	LP_I2S_INT_RAW_RX_FIFOMEM_UDF_INT_RAW_Msk = 0x4
	// Bit RX_FIFOMEM_UDF_INT_RAW.
	LP_I2S_INT_RAW_RX_FIFOMEM_UDF_INT_RAW = 0x4
	// Position of VAD_DONE_INT_RAW field.
	LP_I2S_INT_RAW_VAD_DONE_INT_RAW_Pos = 0x3
	// Bit mask of VAD_DONE_INT_RAW field.
	LP_I2S_INT_RAW_VAD_DONE_INT_RAW_Msk = 0x8
	// Bit VAD_DONE_INT_RAW.
	LP_I2S_INT_RAW_VAD_DONE_INT_RAW = 0x8
	// Position of VAD_RESET_DONE_INT_RAW field.
	LP_I2S_INT_RAW_VAD_RESET_DONE_INT_RAW_Pos = 0x4
	// Bit mask of VAD_RESET_DONE_INT_RAW field.
	LP_I2S_INT_RAW_VAD_RESET_DONE_INT_RAW_Msk = 0x10
	// Bit VAD_RESET_DONE_INT_RAW.
	LP_I2S_INT_RAW_VAD_RESET_DONE_INT_RAW = 0x10
	// Position of RX_MEM_THRESHOLD_INT_RAW field.
	LP_I2S_INT_RAW_RX_MEM_THRESHOLD_INT_RAW_Pos = 0x5
	// Bit mask of RX_MEM_THRESHOLD_INT_RAW field.
	LP_I2S_INT_RAW_RX_MEM_THRESHOLD_INT_RAW_Msk = 0x20
	// Bit RX_MEM_THRESHOLD_INT_RAW.
	LP_I2S_INT_RAW_RX_MEM_THRESHOLD_INT_RAW = 0x20

	// INT_ST: I2S interrupt status register.
	// Position of RX_DONE_INT_ST field.
	LP_I2S_INT_ST_RX_DONE_INT_ST_Pos = 0x0
	// Bit mask of RX_DONE_INT_ST field.
	LP_I2S_INT_ST_RX_DONE_INT_ST_Msk = 0x1
	// Bit RX_DONE_INT_ST.
	LP_I2S_INT_ST_RX_DONE_INT_ST = 0x1
	// Position of RX_HUNG_INT_ST field.
	LP_I2S_INT_ST_RX_HUNG_INT_ST_Pos = 0x1
	// Bit mask of RX_HUNG_INT_ST field.
	LP_I2S_INT_ST_RX_HUNG_INT_ST_Msk = 0x2
	// Bit RX_HUNG_INT_ST.
	LP_I2S_INT_ST_RX_HUNG_INT_ST = 0x2
	// Position of RX_FIFOMEM_UDF_INT_ST field.
	LP_I2S_INT_ST_RX_FIFOMEM_UDF_INT_ST_Pos = 0x2
	// Bit mask of RX_FIFOMEM_UDF_INT_ST field.
	LP_I2S_INT_ST_RX_FIFOMEM_UDF_INT_ST_Msk = 0x4
	// Bit RX_FIFOMEM_UDF_INT_ST.
	LP_I2S_INT_ST_RX_FIFOMEM_UDF_INT_ST = 0x4
	// Position of LP_VAD_DONE_INT_ST field.
	LP_I2S_INT_ST_LP_VAD_DONE_INT_ST_Pos = 0x3
	// Bit mask of LP_VAD_DONE_INT_ST field.
	LP_I2S_INT_ST_LP_VAD_DONE_INT_ST_Msk = 0x8
	// Bit LP_VAD_DONE_INT_ST.
	LP_I2S_INT_ST_LP_VAD_DONE_INT_ST = 0x8
	// Position of LP_VAD_RESET_DONE_INT_ST field.
	LP_I2S_INT_ST_LP_VAD_RESET_DONE_INT_ST_Pos = 0x4
	// Bit mask of LP_VAD_RESET_DONE_INT_ST field.
	LP_I2S_INT_ST_LP_VAD_RESET_DONE_INT_ST_Msk = 0x10
	// Bit LP_VAD_RESET_DONE_INT_ST.
	LP_I2S_INT_ST_LP_VAD_RESET_DONE_INT_ST = 0x10
	// Position of RX_MEM_THRESHOLD_INT_ST field.
	LP_I2S_INT_ST_RX_MEM_THRESHOLD_INT_ST_Pos = 0x5
	// Bit mask of RX_MEM_THRESHOLD_INT_ST field.
	LP_I2S_INT_ST_RX_MEM_THRESHOLD_INT_ST_Msk = 0x20
	// Bit RX_MEM_THRESHOLD_INT_ST.
	LP_I2S_INT_ST_RX_MEM_THRESHOLD_INT_ST = 0x20

	// INT_ENA: I2S interrupt enable register.
	// Position of RX_DONE_INT_ENA field.
	LP_I2S_INT_ENA_RX_DONE_INT_ENA_Pos = 0x0
	// Bit mask of RX_DONE_INT_ENA field.
	LP_I2S_INT_ENA_RX_DONE_INT_ENA_Msk = 0x1
	// Bit RX_DONE_INT_ENA.
	LP_I2S_INT_ENA_RX_DONE_INT_ENA = 0x1
	// Position of RX_HUNG_INT_ENA field.
	LP_I2S_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x1
	// Bit mask of RX_HUNG_INT_ENA field.
	LP_I2S_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x2
	// Bit RX_HUNG_INT_ENA.
	LP_I2S_INT_ENA_RX_HUNG_INT_ENA = 0x2
	// Position of RX_FIFOMEM_UDF_INT_ENA field.
	LP_I2S_INT_ENA_RX_FIFOMEM_UDF_INT_ENA_Pos = 0x2
	// Bit mask of RX_FIFOMEM_UDF_INT_ENA field.
	LP_I2S_INT_ENA_RX_FIFOMEM_UDF_INT_ENA_Msk = 0x4
	// Bit RX_FIFOMEM_UDF_INT_ENA.
	LP_I2S_INT_ENA_RX_FIFOMEM_UDF_INT_ENA = 0x4
	// Position of LP_VAD_DONE_INT_ENA field.
	LP_I2S_INT_ENA_LP_VAD_DONE_INT_ENA_Pos = 0x3
	// Bit mask of LP_VAD_DONE_INT_ENA field.
	LP_I2S_INT_ENA_LP_VAD_DONE_INT_ENA_Msk = 0x8
	// Bit LP_VAD_DONE_INT_ENA.
	LP_I2S_INT_ENA_LP_VAD_DONE_INT_ENA = 0x8
	// Position of LP_VAD_RESET_DONE_INT_ENA field.
	LP_I2S_INT_ENA_LP_VAD_RESET_DONE_INT_ENA_Pos = 0x4
	// Bit mask of LP_VAD_RESET_DONE_INT_ENA field.
	LP_I2S_INT_ENA_LP_VAD_RESET_DONE_INT_ENA_Msk = 0x10
	// Bit LP_VAD_RESET_DONE_INT_ENA.
	LP_I2S_INT_ENA_LP_VAD_RESET_DONE_INT_ENA = 0x10
	// Position of RX_MEM_THRESHOLD_INT_ENA field.
	LP_I2S_INT_ENA_RX_MEM_THRESHOLD_INT_ENA_Pos = 0x5
	// Bit mask of RX_MEM_THRESHOLD_INT_ENA field.
	LP_I2S_INT_ENA_RX_MEM_THRESHOLD_INT_ENA_Msk = 0x20
	// Bit RX_MEM_THRESHOLD_INT_ENA.
	LP_I2S_INT_ENA_RX_MEM_THRESHOLD_INT_ENA = 0x20

	// INT_CLR: I2S interrupt clear register.
	// Position of RX_DONE_INT_CLR field.
	LP_I2S_INT_CLR_RX_DONE_INT_CLR_Pos = 0x0
	// Bit mask of RX_DONE_INT_CLR field.
	LP_I2S_INT_CLR_RX_DONE_INT_CLR_Msk = 0x1
	// Bit RX_DONE_INT_CLR.
	LP_I2S_INT_CLR_RX_DONE_INT_CLR = 0x1
	// Position of RX_HUNG_INT_CLR field.
	LP_I2S_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x1
	// Bit mask of RX_HUNG_INT_CLR field.
	LP_I2S_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x2
	// Bit RX_HUNG_INT_CLR.
	LP_I2S_INT_CLR_RX_HUNG_INT_CLR = 0x2
	// Position of RX_FIFOMEM_UDF_INT_CLR field.
	LP_I2S_INT_CLR_RX_FIFOMEM_UDF_INT_CLR_Pos = 0x2
	// Bit mask of RX_FIFOMEM_UDF_INT_CLR field.
	LP_I2S_INT_CLR_RX_FIFOMEM_UDF_INT_CLR_Msk = 0x4
	// Bit RX_FIFOMEM_UDF_INT_CLR.
	LP_I2S_INT_CLR_RX_FIFOMEM_UDF_INT_CLR = 0x4
	// Position of LP_VAD_DONE_INT_CLR field.
	LP_I2S_INT_CLR_LP_VAD_DONE_INT_CLR_Pos = 0x3
	// Bit mask of LP_VAD_DONE_INT_CLR field.
	LP_I2S_INT_CLR_LP_VAD_DONE_INT_CLR_Msk = 0x8
	// Bit LP_VAD_DONE_INT_CLR.
	LP_I2S_INT_CLR_LP_VAD_DONE_INT_CLR = 0x8
	// Position of LP_VAD_RESET_DONE_INT_CLR field.
	LP_I2S_INT_CLR_LP_VAD_RESET_DONE_INT_CLR_Pos = 0x4
	// Bit mask of LP_VAD_RESET_DONE_INT_CLR field.
	LP_I2S_INT_CLR_LP_VAD_RESET_DONE_INT_CLR_Msk = 0x10
	// Bit LP_VAD_RESET_DONE_INT_CLR.
	LP_I2S_INT_CLR_LP_VAD_RESET_DONE_INT_CLR = 0x10
	// Position of RX_MEM_THRESHOLD_INT_CLR field.
	LP_I2S_INT_CLR_RX_MEM_THRESHOLD_INT_CLR_Pos = 0x5
	// Bit mask of RX_MEM_THRESHOLD_INT_CLR field.
	LP_I2S_INT_CLR_RX_MEM_THRESHOLD_INT_CLR_Msk = 0x20
	// Bit RX_MEM_THRESHOLD_INT_CLR.
	LP_I2S_INT_CLR_RX_MEM_THRESHOLD_INT_CLR = 0x20

	// RX_CONF: I2S RX configure register
	// Position of RX_RESET field.
	LP_I2S_RX_CONF_RX_RESET_Pos = 0x0
	// Bit mask of RX_RESET field.
	LP_I2S_RX_CONF_RX_RESET_Msk = 0x1
	// Bit RX_RESET.
	LP_I2S_RX_CONF_RX_RESET = 0x1
	// Position of RX_FIFO_RESET field.
	LP_I2S_RX_CONF_RX_FIFO_RESET_Pos = 0x1
	// Bit mask of RX_FIFO_RESET field.
	LP_I2S_RX_CONF_RX_FIFO_RESET_Msk = 0x2
	// Bit RX_FIFO_RESET.
	LP_I2S_RX_CONF_RX_FIFO_RESET = 0x2
	// Position of RX_START field.
	LP_I2S_RX_CONF_RX_START_Pos = 0x2
	// Bit mask of RX_START field.
	LP_I2S_RX_CONF_RX_START_Msk = 0x4
	// Bit RX_START.
	LP_I2S_RX_CONF_RX_START = 0x4
	// Position of RX_SLAVE_MOD field.
	LP_I2S_RX_CONF_RX_SLAVE_MOD_Pos = 0x3
	// Bit mask of RX_SLAVE_MOD field.
	LP_I2S_RX_CONF_RX_SLAVE_MOD_Msk = 0x8
	// Bit RX_SLAVE_MOD.
	LP_I2S_RX_CONF_RX_SLAVE_MOD = 0x8
	// Position of RX_FIFOMEM_RESET field.
	LP_I2S_RX_CONF_RX_FIFOMEM_RESET_Pos = 0x4
	// Bit mask of RX_FIFOMEM_RESET field.
	LP_I2S_RX_CONF_RX_FIFOMEM_RESET_Msk = 0x10
	// Bit RX_FIFOMEM_RESET.
	LP_I2S_RX_CONF_RX_FIFOMEM_RESET = 0x10
	// Position of RX_MONO field.
	LP_I2S_RX_CONF_RX_MONO_Pos = 0x5
	// Bit mask of RX_MONO field.
	LP_I2S_RX_CONF_RX_MONO_Msk = 0x20
	// Bit RX_MONO.
	LP_I2S_RX_CONF_RX_MONO = 0x20
	// Position of RX_BIG_ENDIAN field.
	LP_I2S_RX_CONF_RX_BIG_ENDIAN_Pos = 0x7
	// Bit mask of RX_BIG_ENDIAN field.
	LP_I2S_RX_CONF_RX_BIG_ENDIAN_Msk = 0x80
	// Bit RX_BIG_ENDIAN.
	LP_I2S_RX_CONF_RX_BIG_ENDIAN = 0x80
	// Position of RX_UPDATE field.
	LP_I2S_RX_CONF_RX_UPDATE_Pos = 0x8
	// Bit mask of RX_UPDATE field.
	LP_I2S_RX_CONF_RX_UPDATE_Msk = 0x100
	// Bit RX_UPDATE.
	LP_I2S_RX_CONF_RX_UPDATE = 0x100
	// Position of RX_MONO_FST_VLD field.
	LP_I2S_RX_CONF_RX_MONO_FST_VLD_Pos = 0x9
	// Bit mask of RX_MONO_FST_VLD field.
	LP_I2S_RX_CONF_RX_MONO_FST_VLD_Msk = 0x200
	// Bit RX_MONO_FST_VLD.
	LP_I2S_RX_CONF_RX_MONO_FST_VLD = 0x200
	// Position of RX_PCM_CONF field.
	LP_I2S_RX_CONF_RX_PCM_CONF_Pos = 0xa
	// Bit mask of RX_PCM_CONF field.
	LP_I2S_RX_CONF_RX_PCM_CONF_Msk = 0xc00
	// Position of RX_PCM_BYPASS field.
	LP_I2S_RX_CONF_RX_PCM_BYPASS_Pos = 0xc
	// Bit mask of RX_PCM_BYPASS field.
	LP_I2S_RX_CONF_RX_PCM_BYPASS_Msk = 0x1000
	// Bit RX_PCM_BYPASS.
	LP_I2S_RX_CONF_RX_PCM_BYPASS = 0x1000
	// Position of RX_STOP_MODE field.
	LP_I2S_RX_CONF_RX_STOP_MODE_Pos = 0xd
	// Bit mask of RX_STOP_MODE field.
	LP_I2S_RX_CONF_RX_STOP_MODE_Msk = 0x6000
	// Position of RX_LEFT_ALIGN field.
	LP_I2S_RX_CONF_RX_LEFT_ALIGN_Pos = 0xf
	// Bit mask of RX_LEFT_ALIGN field.
	LP_I2S_RX_CONF_RX_LEFT_ALIGN_Msk = 0x8000
	// Bit RX_LEFT_ALIGN.
	LP_I2S_RX_CONF_RX_LEFT_ALIGN = 0x8000
	// Position of RX_24_FILL_EN field.
	LP_I2S_RX_CONF_RX_24_FILL_EN_Pos = 0x10
	// Bit mask of RX_24_FILL_EN field.
	LP_I2S_RX_CONF_RX_24_FILL_EN_Msk = 0x10000
	// Bit RX_24_FILL_EN.
	LP_I2S_RX_CONF_RX_24_FILL_EN = 0x10000
	// Position of RX_WS_IDLE_POL field.
	LP_I2S_RX_CONF_RX_WS_IDLE_POL_Pos = 0x11
	// Bit mask of RX_WS_IDLE_POL field.
	LP_I2S_RX_CONF_RX_WS_IDLE_POL_Msk = 0x20000
	// Bit RX_WS_IDLE_POL.
	LP_I2S_RX_CONF_RX_WS_IDLE_POL = 0x20000
	// Position of RX_BIT_ORDER field.
	LP_I2S_RX_CONF_RX_BIT_ORDER_Pos = 0x12
	// Bit mask of RX_BIT_ORDER field.
	LP_I2S_RX_CONF_RX_BIT_ORDER_Msk = 0x40000
	// Bit RX_BIT_ORDER.
	LP_I2S_RX_CONF_RX_BIT_ORDER = 0x40000
	// Position of RX_TDM_EN field.
	LP_I2S_RX_CONF_RX_TDM_EN_Pos = 0x13
	// Bit mask of RX_TDM_EN field.
	LP_I2S_RX_CONF_RX_TDM_EN_Msk = 0x80000
	// Bit RX_TDM_EN.
	LP_I2S_RX_CONF_RX_TDM_EN = 0x80000
	// Position of RX_PDM_EN field.
	LP_I2S_RX_CONF_RX_PDM_EN_Pos = 0x14
	// Bit mask of RX_PDM_EN field.
	LP_I2S_RX_CONF_RX_PDM_EN_Msk = 0x100000
	// Bit RX_PDM_EN.
	LP_I2S_RX_CONF_RX_PDM_EN = 0x100000

	// RX_CONF1: I2S RX configure register 1
	// Position of RX_TDM_WS_WIDTH field.
	LP_I2S_RX_CONF1_RX_TDM_WS_WIDTH_Pos = 0x0
	// Bit mask of RX_TDM_WS_WIDTH field.
	LP_I2S_RX_CONF1_RX_TDM_WS_WIDTH_Msk = 0x7f
	// Position of RX_BCK_DIV_NUM field.
	LP_I2S_RX_CONF1_RX_BCK_DIV_NUM_Pos = 0x7
	// Bit mask of RX_BCK_DIV_NUM field.
	LP_I2S_RX_CONF1_RX_BCK_DIV_NUM_Msk = 0x1f80
	// Position of RX_BITS_MOD field.
	LP_I2S_RX_CONF1_RX_BITS_MOD_Pos = 0xd
	// Bit mask of RX_BITS_MOD field.
	LP_I2S_RX_CONF1_RX_BITS_MOD_Msk = 0x3e000
	// Position of RX_HALF_SAMPLE_BITS field.
	LP_I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Pos = 0x12
	// Bit mask of RX_HALF_SAMPLE_BITS field.
	LP_I2S_RX_CONF1_RX_HALF_SAMPLE_BITS_Msk = 0xfc0000
	// Position of RX_TDM_CHAN_BITS field.
	LP_I2S_RX_CONF1_RX_TDM_CHAN_BITS_Pos = 0x18
	// Bit mask of RX_TDM_CHAN_BITS field.
	LP_I2S_RX_CONF1_RX_TDM_CHAN_BITS_Msk = 0x1f000000
	// Position of RX_MSB_SHIFT field.
	LP_I2S_RX_CONF1_RX_MSB_SHIFT_Pos = 0x1d
	// Bit mask of RX_MSB_SHIFT field.
	LP_I2S_RX_CONF1_RX_MSB_SHIFT_Msk = 0x20000000
	// Bit RX_MSB_SHIFT.
	LP_I2S_RX_CONF1_RX_MSB_SHIFT = 0x20000000

	// RX_TDM_CTRL: I2S TX TDM mode control register
	// Position of RX_TDM_PDM_CHAN0_EN field.
	LP_I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Pos = 0x0
	// Bit mask of RX_TDM_PDM_CHAN0_EN field.
	LP_I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN_Msk = 0x1
	// Bit RX_TDM_PDM_CHAN0_EN.
	LP_I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN0_EN = 0x1
	// Position of RX_TDM_PDM_CHAN1_EN field.
	LP_I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Pos = 0x1
	// Bit mask of RX_TDM_PDM_CHAN1_EN field.
	LP_I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN_Msk = 0x2
	// Bit RX_TDM_PDM_CHAN1_EN.
	LP_I2S_RX_TDM_CTRL_RX_TDM_PDM_CHAN1_EN = 0x2
	// Position of RX_TDM_TOT_CHAN_NUM field.
	LP_I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Pos = 0x10
	// Bit mask of RX_TDM_TOT_CHAN_NUM field.
	LP_I2S_RX_TDM_CTRL_RX_TDM_TOT_CHAN_NUM_Msk = 0xf0000

	// RX_TIMING: I2S RX timing control register
	// Position of RX_SD_IN_DM field.
	LP_I2S_RX_TIMING_RX_SD_IN_DM_Pos = 0x0
	// Bit mask of RX_SD_IN_DM field.
	LP_I2S_RX_TIMING_RX_SD_IN_DM_Msk = 0x3
	// Position of RX_WS_OUT_DM field.
	LP_I2S_RX_TIMING_RX_WS_OUT_DM_Pos = 0x10
	// Bit mask of RX_WS_OUT_DM field.
	LP_I2S_RX_TIMING_RX_WS_OUT_DM_Msk = 0x30000
	// Position of RX_BCK_OUT_DM field.
	LP_I2S_RX_TIMING_RX_BCK_OUT_DM_Pos = 0x14
	// Bit mask of RX_BCK_OUT_DM field.
	LP_I2S_RX_TIMING_RX_BCK_OUT_DM_Msk = 0x300000
	// Position of RX_WS_IN_DM field.
	LP_I2S_RX_TIMING_RX_WS_IN_DM_Pos = 0x18
	// Bit mask of RX_WS_IN_DM field.
	LP_I2S_RX_TIMING_RX_WS_IN_DM_Msk = 0x3000000
	// Position of RX_BCK_IN_DM field.
	LP_I2S_RX_TIMING_RX_BCK_IN_DM_Pos = 0x1c
	// Bit mask of RX_BCK_IN_DM field.
	LP_I2S_RX_TIMING_RX_BCK_IN_DM_Msk = 0x30000000

	// LC_HUNG_CONF: I2S HUNG configure register.
	// Position of LC_FIFO_TIMEOUT field.
	LP_I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Pos = 0x0
	// Bit mask of LC_FIFO_TIMEOUT field.
	LP_I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_Msk = 0xff
	// Position of LC_FIFO_TIMEOUT_SHIFT field.
	LP_I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Pos = 0x8
	// Bit mask of LC_FIFO_TIMEOUT_SHIFT field.
	LP_I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_SHIFT_Msk = 0x700
	// Position of LC_FIFO_TIMEOUT_ENA field.
	LP_I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Pos = 0xb
	// Bit mask of LC_FIFO_TIMEOUT_ENA field.
	LP_I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA_Msk = 0x800
	// Bit LC_FIFO_TIMEOUT_ENA.
	LP_I2S_LC_HUNG_CONF_LC_FIFO_TIMEOUT_ENA = 0x800

	// RXEOF_NUM: I2S RX data number control register.
	// Position of RX_EOF_NUM field.
	LP_I2S_RXEOF_NUM_RX_EOF_NUM_Pos = 0x0
	// Bit mask of RX_EOF_NUM field.
	LP_I2S_RXEOF_NUM_RX_EOF_NUM_Msk = 0xfff

	// CONF_SIGLE_DATA: I2S signal data register
	// Position of SINGLE_DATA field.
	LP_I2S_CONF_SIGLE_DATA_SINGLE_DATA_Pos = 0x0
	// Bit mask of SINGLE_DATA field.
	LP_I2S_CONF_SIGLE_DATA_SINGLE_DATA_Msk = 0xffffffff

	// RX_PDM_CONF: I2S RX configure register
	// Position of RX_PDM2PCM_EN field.
	LP_I2S_RX_PDM_CONF_RX_PDM2PCM_EN_Pos = 0x13
	// Bit mask of RX_PDM2PCM_EN field.
	LP_I2S_RX_PDM_CONF_RX_PDM2PCM_EN_Msk = 0x80000
	// Bit RX_PDM2PCM_EN.
	LP_I2S_RX_PDM_CONF_RX_PDM2PCM_EN = 0x80000
	// Position of RX_PDM_SINC_DSR_16_EN field.
	LP_I2S_RX_PDM_CONF_RX_PDM_SINC_DSR_16_EN_Pos = 0x14
	// Bit mask of RX_PDM_SINC_DSR_16_EN field.
	LP_I2S_RX_PDM_CONF_RX_PDM_SINC_DSR_16_EN_Msk = 0x100000
	// Bit RX_PDM_SINC_DSR_16_EN.
	LP_I2S_RX_PDM_CONF_RX_PDM_SINC_DSR_16_EN = 0x100000
	// Position of RX_PDM2PCM_AMPLIFY_NUM field.
	LP_I2S_RX_PDM_CONF_RX_PDM2PCM_AMPLIFY_NUM_Pos = 0x15
	// Bit mask of RX_PDM2PCM_AMPLIFY_NUM field.
	LP_I2S_RX_PDM_CONF_RX_PDM2PCM_AMPLIFY_NUM_Msk = 0x1e00000
	// Position of RX_PDM_HP_BYPASS field.
	LP_I2S_RX_PDM_CONF_RX_PDM_HP_BYPASS_Pos = 0x19
	// Bit mask of RX_PDM_HP_BYPASS field.
	LP_I2S_RX_PDM_CONF_RX_PDM_HP_BYPASS_Msk = 0x2000000
	// Bit RX_PDM_HP_BYPASS.
	LP_I2S_RX_PDM_CONF_RX_PDM_HP_BYPASS = 0x2000000
	// Position of RX_IIR_HP_MULT12_5 field.
	LP_I2S_RX_PDM_CONF_RX_IIR_HP_MULT12_5_Pos = 0x1a
	// Bit mask of RX_IIR_HP_MULT12_5 field.
	LP_I2S_RX_PDM_CONF_RX_IIR_HP_MULT12_5_Msk = 0x1c000000
	// Position of RX_IIR_HP_MULT12_0 field.
	LP_I2S_RX_PDM_CONF_RX_IIR_HP_MULT12_0_Pos = 0x1d
	// Bit mask of RX_IIR_HP_MULT12_0 field.
	LP_I2S_RX_PDM_CONF_RX_IIR_HP_MULT12_0_Msk = 0xe0000000

	// ECO_LOW: I2S ECO register
	// Position of RDN_ECO_LOW field.
	LP_I2S_ECO_LOW_RDN_ECO_LOW_Pos = 0x0
	// Bit mask of RDN_ECO_LOW field.
	LP_I2S_ECO_LOW_RDN_ECO_LOW_Msk = 0xffffffff

	// ECO_HIGH: I2S ECO register
	// Position of RDN_ECO_HIGH field.
	LP_I2S_ECO_HIGH_RDN_ECO_HIGH_Pos = 0x0
	// Bit mask of RDN_ECO_HIGH field.
	LP_I2S_ECO_HIGH_RDN_ECO_HIGH_Msk = 0xffffffff

	// ECO_CONF: I2S ECO register
	// Position of RDN_ENA field.
	LP_I2S_ECO_CONF_RDN_ENA_Pos = 0x0
	// Bit mask of RDN_ENA field.
	LP_I2S_ECO_CONF_RDN_ENA_Msk = 0x1
	// Bit RDN_ENA.
	LP_I2S_ECO_CONF_RDN_ENA = 0x1
	// Position of RDN_RESULT field.
	LP_I2S_ECO_CONF_RDN_RESULT_Pos = 0x1
	// Bit mask of RDN_RESULT field.
	LP_I2S_ECO_CONF_RDN_RESULT_Msk = 0x2
	// Bit RDN_RESULT.
	LP_I2S_ECO_CONF_RDN_RESULT = 0x2

	// VAD_PARAM0: I2S VAD Parameter register
	// Position of PARAM_MIN_ENERGY field.
	LP_I2S_VAD_PARAM0_PARAM_MIN_ENERGY_Pos = 0x0
	// Bit mask of PARAM_MIN_ENERGY field.
	LP_I2S_VAD_PARAM0_PARAM_MIN_ENERGY_Msk = 0xffff
	// Position of PARAM_INIT_FRAME_NUM field.
	LP_I2S_VAD_PARAM0_PARAM_INIT_FRAME_NUM_Pos = 0x10
	// Bit mask of PARAM_INIT_FRAME_NUM field.
	LP_I2S_VAD_PARAM0_PARAM_INIT_FRAME_NUM_Msk = 0x1ff0000

	// VAD_PARAM1: I2S VAD Parameter register
	// Position of PARAM_MIN_SPEECH_COUNT field.
	LP_I2S_VAD_PARAM1_PARAM_MIN_SPEECH_COUNT_Pos = 0x0
	// Bit mask of PARAM_MIN_SPEECH_COUNT field.
	LP_I2S_VAD_PARAM1_PARAM_MIN_SPEECH_COUNT_Msk = 0xf
	// Position of PARAM_MAX_SPEECH_COUNT field.
	LP_I2S_VAD_PARAM1_PARAM_MAX_SPEECH_COUNT_Pos = 0x4
	// Bit mask of PARAM_MAX_SPEECH_COUNT field.
	LP_I2S_VAD_PARAM1_PARAM_MAX_SPEECH_COUNT_Msk = 0x7f0
	// Position of PARAM_HANGOVER_SPEECH field.
	LP_I2S_VAD_PARAM1_PARAM_HANGOVER_SPEECH_Pos = 0xb
	// Bit mask of PARAM_HANGOVER_SPEECH field.
	LP_I2S_VAD_PARAM1_PARAM_HANGOVER_SPEECH_Msk = 0xf800
	// Position of PARAM_HANGOVER_SILENT field.
	LP_I2S_VAD_PARAM1_PARAM_HANGOVER_SILENT_Pos = 0x10
	// Bit mask of PARAM_HANGOVER_SILENT field.
	LP_I2S_VAD_PARAM1_PARAM_HANGOVER_SILENT_Msk = 0xff0000
	// Position of PARAM_MAX_OFFSET field.
	LP_I2S_VAD_PARAM1_PARAM_MAX_OFFSET_Pos = 0x18
	// Bit mask of PARAM_MAX_OFFSET field.
	LP_I2S_VAD_PARAM1_PARAM_MAX_OFFSET_Msk = 0x7f000000
	// Position of PARAM_SKIP_BAND_ENERGY field.
	LP_I2S_VAD_PARAM1_PARAM_SKIP_BAND_ENERGY_Pos = 0x1f
	// Bit mask of PARAM_SKIP_BAND_ENERGY field.
	LP_I2S_VAD_PARAM1_PARAM_SKIP_BAND_ENERGY_Msk = 0x80000000
	// Bit PARAM_SKIP_BAND_ENERGY.
	LP_I2S_VAD_PARAM1_PARAM_SKIP_BAND_ENERGY = 0x80000000

	// VAD_PARAM2: I2S VAD Parameter register
	// Position of PARAM_NOISE_AMP_DOWN field.
	LP_I2S_VAD_PARAM2_PARAM_NOISE_AMP_DOWN_Pos = 0x0
	// Bit mask of PARAM_NOISE_AMP_DOWN field.
	LP_I2S_VAD_PARAM2_PARAM_NOISE_AMP_DOWN_Msk = 0xffff
	// Position of PARAM_NOISE_AMP_UP field.
	LP_I2S_VAD_PARAM2_PARAM_NOISE_AMP_UP_Pos = 0x10
	// Bit mask of PARAM_NOISE_AMP_UP field.
	LP_I2S_VAD_PARAM2_PARAM_NOISE_AMP_UP_Msk = 0xffff0000

	// VAD_PARAM3: I2S VAD Parameter register
	// Position of PARAM_NOISE_SPE_UP0 field.
	LP_I2S_VAD_PARAM3_PARAM_NOISE_SPE_UP0_Pos = 0x0
	// Bit mask of PARAM_NOISE_SPE_UP0 field.
	LP_I2S_VAD_PARAM3_PARAM_NOISE_SPE_UP0_Msk = 0xffff
	// Position of PARAM_NOISE_SPE_UP1 field.
	LP_I2S_VAD_PARAM3_PARAM_NOISE_SPE_UP1_Pos = 0x10
	// Bit mask of PARAM_NOISE_SPE_UP1 field.
	LP_I2S_VAD_PARAM3_PARAM_NOISE_SPE_UP1_Msk = 0xffff0000

	// VAD_PARAM4: I2S VAD Parameter register
	// Position of PARAM_NOISE_SPE_DOWN field.
	LP_I2S_VAD_PARAM4_PARAM_NOISE_SPE_DOWN_Pos = 0x0
	// Bit mask of PARAM_NOISE_SPE_DOWN field.
	LP_I2S_VAD_PARAM4_PARAM_NOISE_SPE_DOWN_Msk = 0xffff
	// Position of PARAM_NOISE_MEAN_DOWN field.
	LP_I2S_VAD_PARAM4_PARAM_NOISE_MEAN_DOWN_Pos = 0x10
	// Bit mask of PARAM_NOISE_MEAN_DOWN field.
	LP_I2S_VAD_PARAM4_PARAM_NOISE_MEAN_DOWN_Msk = 0xffff0000

	// VAD_PARAM5: I2S VAD Parameter register
	// Position of PARAM_NOISE_MEAN_UP0 field.
	LP_I2S_VAD_PARAM5_PARAM_NOISE_MEAN_UP0_Pos = 0x0
	// Bit mask of PARAM_NOISE_MEAN_UP0 field.
	LP_I2S_VAD_PARAM5_PARAM_NOISE_MEAN_UP0_Msk = 0xffff
	// Position of PARAM_NOISE_MEAN_UP1 field.
	LP_I2S_VAD_PARAM5_PARAM_NOISE_MEAN_UP1_Pos = 0x10
	// Bit mask of PARAM_NOISE_MEAN_UP1 field.
	LP_I2S_VAD_PARAM5_PARAM_NOISE_MEAN_UP1_Msk = 0xffff0000

	// VAD_PARAM6: I2S VAD Parameter register
	// Position of PARAM_NOISE_STD_FS_THSL field.
	LP_I2S_VAD_PARAM6_PARAM_NOISE_STD_FS_THSL_Pos = 0x0
	// Bit mask of PARAM_NOISE_STD_FS_THSL field.
	LP_I2S_VAD_PARAM6_PARAM_NOISE_STD_FS_THSL_Msk = 0xffff
	// Position of PARAM_NOISE_STD_FS_THSH field.
	LP_I2S_VAD_PARAM6_PARAM_NOISE_STD_FS_THSH_Pos = 0x10
	// Bit mask of PARAM_NOISE_STD_FS_THSH field.
	LP_I2S_VAD_PARAM6_PARAM_NOISE_STD_FS_THSH_Msk = 0xffff0000

	// VAD_PARAM7: I2S VAD Parameter register
	// Position of PARAM_THRES_UPD_BASE field.
	LP_I2S_VAD_PARAM7_PARAM_THRES_UPD_BASE_Pos = 0x0
	// Bit mask of PARAM_THRES_UPD_BASE field.
	LP_I2S_VAD_PARAM7_PARAM_THRES_UPD_BASE_Msk = 0xffff
	// Position of PARAM_THRES_UPD_VARY field.
	LP_I2S_VAD_PARAM7_PARAM_THRES_UPD_VARY_Pos = 0x10
	// Bit mask of PARAM_THRES_UPD_VARY field.
	LP_I2S_VAD_PARAM7_PARAM_THRES_UPD_VARY_Msk = 0xffff0000

	// VAD_PARAM8: I2S VAD Parameter register
	// Position of PARAM_THRES_UPD_BDL field.
	LP_I2S_VAD_PARAM8_PARAM_THRES_UPD_BDL_Pos = 0x0
	// Bit mask of PARAM_THRES_UPD_BDL field.
	LP_I2S_VAD_PARAM8_PARAM_THRES_UPD_BDL_Msk = 0xff
	// Position of PARAM_THRES_UPD_BDH field.
	LP_I2S_VAD_PARAM8_PARAM_THRES_UPD_BDH_Pos = 0x8
	// Bit mask of PARAM_THRES_UPD_BDH field.
	LP_I2S_VAD_PARAM8_PARAM_THRES_UPD_BDH_Msk = 0xff00
	// Position of PARAM_FEATURE_BURST field.
	LP_I2S_VAD_PARAM8_PARAM_FEATURE_BURST_Pos = 0x10
	// Bit mask of PARAM_FEATURE_BURST field.
	LP_I2S_VAD_PARAM8_PARAM_FEATURE_BURST_Msk = 0xffff0000

	// VAD_OB0: I2S VAD Observe register
	// Position of SPEECH_COUNT_OB field.
	LP_I2S_VAD_OB0_SPEECH_COUNT_OB_Pos = 0x0
	// Bit mask of SPEECH_COUNT_OB field.
	LP_I2S_VAD_OB0_SPEECH_COUNT_OB_Msk = 0xff
	// Position of SILENT_COUNT_OB field.
	LP_I2S_VAD_OB0_SILENT_COUNT_OB_Pos = 0x8
	// Bit mask of SILENT_COUNT_OB field.
	LP_I2S_VAD_OB0_SILENT_COUNT_OB_Msk = 0xff00
	// Position of MAX_SIGNAL0_OB field.
	LP_I2S_VAD_OB0_MAX_SIGNAL0_OB_Pos = 0x10
	// Bit mask of MAX_SIGNAL0_OB field.
	LP_I2S_VAD_OB0_MAX_SIGNAL0_OB_Msk = 0xffff0000

	// VAD_OB1: I2S VAD Observe register
	// Position of MAX_SIGNAL1_OB field.
	LP_I2S_VAD_OB1_MAX_SIGNAL1_OB_Pos = 0x0
	// Bit mask of MAX_SIGNAL1_OB field.
	LP_I2S_VAD_OB1_MAX_SIGNAL1_OB_Msk = 0xffff
	// Position of MAX_SIGNAL2_OB field.
	LP_I2S_VAD_OB1_MAX_SIGNAL2_OB_Pos = 0x10
	// Bit mask of MAX_SIGNAL2_OB field.
	LP_I2S_VAD_OB1_MAX_SIGNAL2_OB_Msk = 0xffff0000

	// VAD_OB2: I2S VAD Observe register
	// Position of NOISE_AMP_OB field.
	LP_I2S_VAD_OB2_NOISE_AMP_OB_Pos = 0x0
	// Bit mask of NOISE_AMP_OB field.
	LP_I2S_VAD_OB2_NOISE_AMP_OB_Msk = 0xffffffff

	// VAD_OB3: I2S VAD Observe register
	// Position of NOISE_MEAN_OB field.
	LP_I2S_VAD_OB3_NOISE_MEAN_OB_Pos = 0x0
	// Bit mask of NOISE_MEAN_OB field.
	LP_I2S_VAD_OB3_NOISE_MEAN_OB_Msk = 0xffffffff

	// VAD_OB4: I2S VAD Observe register
	// Position of NOISE_STD_OB field.
	LP_I2S_VAD_OB4_NOISE_STD_OB_Pos = 0x0
	// Bit mask of NOISE_STD_OB field.
	LP_I2S_VAD_OB4_NOISE_STD_OB_Msk = 0xffffffff

	// VAD_OB5: I2S VAD Observe register
	// Position of OFFSET_OB field.
	LP_I2S_VAD_OB5_OFFSET_OB_Pos = 0x0
	// Bit mask of OFFSET_OB field.
	LP_I2S_VAD_OB5_OFFSET_OB_Msk = 0xffffffff

	// VAD_OB6: I2S VAD Observe register
	// Position of THRESHOLD_OB field.
	LP_I2S_VAD_OB6_THRESHOLD_OB_Pos = 0x0
	// Bit mask of THRESHOLD_OB field.
	LP_I2S_VAD_OB6_THRESHOLD_OB_Msk = 0xffffffff

	// VAD_OB7: I2S VAD Observe register
	// Position of ENERGY_LOW_OB field.
	LP_I2S_VAD_OB7_ENERGY_LOW_OB_Pos = 0x0
	// Bit mask of ENERGY_LOW_OB field.
	LP_I2S_VAD_OB7_ENERGY_LOW_OB_Msk = 0xffffffff

	// VAD_OB8: I2S VAD Observe register
	// Position of ENERGY_HIGH_OB field.
	LP_I2S_VAD_OB8_ENERGY_HIGH_OB_Pos = 0x0
	// Bit mask of ENERGY_HIGH_OB field.
	LP_I2S_VAD_OB8_ENERGY_HIGH_OB_Msk = 0xffffffff

	// CLK_GATE: Clock gate register
	// Position of CLK_EN field.
	LP_I2S_CLK_GATE_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	LP_I2S_CLK_GATE_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	LP_I2S_CLK_GATE_CLK_EN = 0x1
	// Position of VAD_CG_FORCE_ON field.
	LP_I2S_CLK_GATE_VAD_CG_FORCE_ON_Pos = 0x1
	// Bit mask of VAD_CG_FORCE_ON field.
	LP_I2S_CLK_GATE_VAD_CG_FORCE_ON_Msk = 0x2
	// Bit VAD_CG_FORCE_ON.
	LP_I2S_CLK_GATE_VAD_CG_FORCE_ON = 0x2
	// Position of RX_MEM_CG_FORCE_ON field.
	LP_I2S_CLK_GATE_RX_MEM_CG_FORCE_ON_Pos = 0x2
	// Bit mask of RX_MEM_CG_FORCE_ON field.
	LP_I2S_CLK_GATE_RX_MEM_CG_FORCE_ON_Msk = 0x4
	// Bit RX_MEM_CG_FORCE_ON.
	LP_I2S_CLK_GATE_RX_MEM_CG_FORCE_ON = 0x4
	// Position of RX_REG_CG_FORCE_ON field.
	LP_I2S_CLK_GATE_RX_REG_CG_FORCE_ON_Pos = 0x3
	// Bit mask of RX_REG_CG_FORCE_ON field.
	LP_I2S_CLK_GATE_RX_REG_CG_FORCE_ON_Msk = 0x8
	// Bit RX_REG_CG_FORCE_ON.
	LP_I2S_CLK_GATE_RX_REG_CG_FORCE_ON = 0x8

	// DATE: Version control register
	// Position of DATE field.
	LP_I2S_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	LP_I2S_DATE_DATE_Msk = 0xfffffff
)

// Constants for LP_IO_MUX: Low-power Input/Output Multiplexer
const (
	// CLK_EN: Reserved
	// Position of REG_CLK_EN field.
	LP_IOMUX_CLK_EN_REG_CLK_EN_Pos = 0x0
	// Bit mask of REG_CLK_EN field.
	LP_IOMUX_CLK_EN_REG_CLK_EN_Msk = 0x1
	// Bit REG_CLK_EN.
	LP_IOMUX_CLK_EN_REG_CLK_EN = 0x1

	// VER_DATE: Reserved
	// Position of REG_VER_DATE field.
	LP_IOMUX_VER_DATE_REG_VER_DATE_Pos = 0x0
	// Bit mask of REG_VER_DATE field.
	LP_IOMUX_VER_DATE_REG_VER_DATE_Msk = 0xfffffff

	// PAD0: Reserved
	// Position of REG_PAD0_DRV field.
	LP_IOMUX_PAD0_REG_PAD0_DRV_Pos = 0x0
	// Bit mask of REG_PAD0_DRV field.
	LP_IOMUX_PAD0_REG_PAD0_DRV_Msk = 0x3
	// Position of REG_PAD0_RDE field.
	LP_IOMUX_PAD0_REG_PAD0_RDE_Pos = 0x2
	// Bit mask of REG_PAD0_RDE field.
	LP_IOMUX_PAD0_REG_PAD0_RDE_Msk = 0x4
	// Bit REG_PAD0_RDE.
	LP_IOMUX_PAD0_REG_PAD0_RDE = 0x4
	// Position of REG_PAD0_RUE field.
	LP_IOMUX_PAD0_REG_PAD0_RUE_Pos = 0x3
	// Bit mask of REG_PAD0_RUE field.
	LP_IOMUX_PAD0_REG_PAD0_RUE_Msk = 0x8
	// Bit REG_PAD0_RUE.
	LP_IOMUX_PAD0_REG_PAD0_RUE = 0x8
	// Position of REG_PAD0_MUX_SEL field.
	LP_IOMUX_PAD0_REG_PAD0_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD0_MUX_SEL field.
	LP_IOMUX_PAD0_REG_PAD0_MUX_SEL_Msk = 0x10
	// Bit REG_PAD0_MUX_SEL.
	LP_IOMUX_PAD0_REG_PAD0_MUX_SEL = 0x10
	// Position of REG_PAD0_FUN_SEL field.
	LP_IOMUX_PAD0_REG_PAD0_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD0_FUN_SEL field.
	LP_IOMUX_PAD0_REG_PAD0_FUN_SEL_Msk = 0x60
	// Position of REG_PAD0_SLP_SEL field.
	LP_IOMUX_PAD0_REG_PAD0_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD0_SLP_SEL field.
	LP_IOMUX_PAD0_REG_PAD0_SLP_SEL_Msk = 0x80
	// Bit REG_PAD0_SLP_SEL.
	LP_IOMUX_PAD0_REG_PAD0_SLP_SEL = 0x80
	// Position of REG_PAD0_SLP_IE field.
	LP_IOMUX_PAD0_REG_PAD0_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD0_SLP_IE field.
	LP_IOMUX_PAD0_REG_PAD0_SLP_IE_Msk = 0x100
	// Bit REG_PAD0_SLP_IE.
	LP_IOMUX_PAD0_REG_PAD0_SLP_IE = 0x100
	// Position of REG_PAD0_SLP_OE field.
	LP_IOMUX_PAD0_REG_PAD0_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD0_SLP_OE field.
	LP_IOMUX_PAD0_REG_PAD0_SLP_OE_Msk = 0x200
	// Bit REG_PAD0_SLP_OE.
	LP_IOMUX_PAD0_REG_PAD0_SLP_OE = 0x200
	// Position of REG_PAD0_FUN_IE field.
	LP_IOMUX_PAD0_REG_PAD0_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD0_FUN_IE field.
	LP_IOMUX_PAD0_REG_PAD0_FUN_IE_Msk = 0x400
	// Bit REG_PAD0_FUN_IE.
	LP_IOMUX_PAD0_REG_PAD0_FUN_IE = 0x400
	// Position of REG_PAD0_FILTER_EN field.
	LP_IOMUX_PAD0_REG_PAD0_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD0_FILTER_EN field.
	LP_IOMUX_PAD0_REG_PAD0_FILTER_EN_Msk = 0x800
	// Bit REG_PAD0_FILTER_EN.
	LP_IOMUX_PAD0_REG_PAD0_FILTER_EN = 0x800

	// PAD1: Reserved
	// Position of REG_PAD1_DRV field.
	LP_IOMUX_PAD1_REG_PAD1_DRV_Pos = 0x0
	// Bit mask of REG_PAD1_DRV field.
	LP_IOMUX_PAD1_REG_PAD1_DRV_Msk = 0x3
	// Position of REG_PAD1_RDE field.
	LP_IOMUX_PAD1_REG_PAD1_RDE_Pos = 0x2
	// Bit mask of REG_PAD1_RDE field.
	LP_IOMUX_PAD1_REG_PAD1_RDE_Msk = 0x4
	// Bit REG_PAD1_RDE.
	LP_IOMUX_PAD1_REG_PAD1_RDE = 0x4
	// Position of REG_PAD1_RUE field.
	LP_IOMUX_PAD1_REG_PAD1_RUE_Pos = 0x3
	// Bit mask of REG_PAD1_RUE field.
	LP_IOMUX_PAD1_REG_PAD1_RUE_Msk = 0x8
	// Bit REG_PAD1_RUE.
	LP_IOMUX_PAD1_REG_PAD1_RUE = 0x8
	// Position of REG_PAD1_MUX_SEL field.
	LP_IOMUX_PAD1_REG_PAD1_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD1_MUX_SEL field.
	LP_IOMUX_PAD1_REG_PAD1_MUX_SEL_Msk = 0x10
	// Bit REG_PAD1_MUX_SEL.
	LP_IOMUX_PAD1_REG_PAD1_MUX_SEL = 0x10
	// Position of REG_PAD1_FUN_SEL field.
	LP_IOMUX_PAD1_REG_PAD1_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD1_FUN_SEL field.
	LP_IOMUX_PAD1_REG_PAD1_FUN_SEL_Msk = 0x60
	// Position of REG_PAD1_SLP_SEL field.
	LP_IOMUX_PAD1_REG_PAD1_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD1_SLP_SEL field.
	LP_IOMUX_PAD1_REG_PAD1_SLP_SEL_Msk = 0x80
	// Bit REG_PAD1_SLP_SEL.
	LP_IOMUX_PAD1_REG_PAD1_SLP_SEL = 0x80
	// Position of REG_PAD1_SLP_IE field.
	LP_IOMUX_PAD1_REG_PAD1_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD1_SLP_IE field.
	LP_IOMUX_PAD1_REG_PAD1_SLP_IE_Msk = 0x100
	// Bit REG_PAD1_SLP_IE.
	LP_IOMUX_PAD1_REG_PAD1_SLP_IE = 0x100
	// Position of REG_PAD1_SLP_OE field.
	LP_IOMUX_PAD1_REG_PAD1_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD1_SLP_OE field.
	LP_IOMUX_PAD1_REG_PAD1_SLP_OE_Msk = 0x200
	// Bit REG_PAD1_SLP_OE.
	LP_IOMUX_PAD1_REG_PAD1_SLP_OE = 0x200
	// Position of REG_PAD1_FUN_IE field.
	LP_IOMUX_PAD1_REG_PAD1_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD1_FUN_IE field.
	LP_IOMUX_PAD1_REG_PAD1_FUN_IE_Msk = 0x400
	// Bit REG_PAD1_FUN_IE.
	LP_IOMUX_PAD1_REG_PAD1_FUN_IE = 0x400
	// Position of REG_PAD1_FILTER_EN field.
	LP_IOMUX_PAD1_REG_PAD1_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD1_FILTER_EN field.
	LP_IOMUX_PAD1_REG_PAD1_FILTER_EN_Msk = 0x800
	// Bit REG_PAD1_FILTER_EN.
	LP_IOMUX_PAD1_REG_PAD1_FILTER_EN = 0x800

	// PAD2: Reserved
	// Position of REG_PAD2_DRV field.
	LP_IOMUX_PAD2_REG_PAD2_DRV_Pos = 0x0
	// Bit mask of REG_PAD2_DRV field.
	LP_IOMUX_PAD2_REG_PAD2_DRV_Msk = 0x3
	// Position of REG_PAD2_RDE field.
	LP_IOMUX_PAD2_REG_PAD2_RDE_Pos = 0x2
	// Bit mask of REG_PAD2_RDE field.
	LP_IOMUX_PAD2_REG_PAD2_RDE_Msk = 0x4
	// Bit REG_PAD2_RDE.
	LP_IOMUX_PAD2_REG_PAD2_RDE = 0x4
	// Position of REG_PAD2_RUE field.
	LP_IOMUX_PAD2_REG_PAD2_RUE_Pos = 0x3
	// Bit mask of REG_PAD2_RUE field.
	LP_IOMUX_PAD2_REG_PAD2_RUE_Msk = 0x8
	// Bit REG_PAD2_RUE.
	LP_IOMUX_PAD2_REG_PAD2_RUE = 0x8
	// Position of REG_PAD2_MUX_SEL field.
	LP_IOMUX_PAD2_REG_PAD2_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD2_MUX_SEL field.
	LP_IOMUX_PAD2_REG_PAD2_MUX_SEL_Msk = 0x10
	// Bit REG_PAD2_MUX_SEL.
	LP_IOMUX_PAD2_REG_PAD2_MUX_SEL = 0x10
	// Position of REG_PAD2_FUN_SEL field.
	LP_IOMUX_PAD2_REG_PAD2_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD2_FUN_SEL field.
	LP_IOMUX_PAD2_REG_PAD2_FUN_SEL_Msk = 0x60
	// Position of REG_PAD2_SLP_SEL field.
	LP_IOMUX_PAD2_REG_PAD2_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD2_SLP_SEL field.
	LP_IOMUX_PAD2_REG_PAD2_SLP_SEL_Msk = 0x80
	// Bit REG_PAD2_SLP_SEL.
	LP_IOMUX_PAD2_REG_PAD2_SLP_SEL = 0x80
	// Position of REG_PAD2_SLP_IE field.
	LP_IOMUX_PAD2_REG_PAD2_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD2_SLP_IE field.
	LP_IOMUX_PAD2_REG_PAD2_SLP_IE_Msk = 0x100
	// Bit REG_PAD2_SLP_IE.
	LP_IOMUX_PAD2_REG_PAD2_SLP_IE = 0x100
	// Position of REG_PAD2_SLP_OE field.
	LP_IOMUX_PAD2_REG_PAD2_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD2_SLP_OE field.
	LP_IOMUX_PAD2_REG_PAD2_SLP_OE_Msk = 0x200
	// Bit REG_PAD2_SLP_OE.
	LP_IOMUX_PAD2_REG_PAD2_SLP_OE = 0x200
	// Position of REG_PAD2_FUN_IE field.
	LP_IOMUX_PAD2_REG_PAD2_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD2_FUN_IE field.
	LP_IOMUX_PAD2_REG_PAD2_FUN_IE_Msk = 0x400
	// Bit REG_PAD2_FUN_IE.
	LP_IOMUX_PAD2_REG_PAD2_FUN_IE = 0x400
	// Position of REG_PAD2_FILTER_EN field.
	LP_IOMUX_PAD2_REG_PAD2_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD2_FILTER_EN field.
	LP_IOMUX_PAD2_REG_PAD2_FILTER_EN_Msk = 0x800
	// Bit REG_PAD2_FILTER_EN.
	LP_IOMUX_PAD2_REG_PAD2_FILTER_EN = 0x800

	// PAD3: Reserved
	// Position of REG_PAD3_DRV field.
	LP_IOMUX_PAD3_REG_PAD3_DRV_Pos = 0x0
	// Bit mask of REG_PAD3_DRV field.
	LP_IOMUX_PAD3_REG_PAD3_DRV_Msk = 0x3
	// Position of REG_PAD3_RDE field.
	LP_IOMUX_PAD3_REG_PAD3_RDE_Pos = 0x2
	// Bit mask of REG_PAD3_RDE field.
	LP_IOMUX_PAD3_REG_PAD3_RDE_Msk = 0x4
	// Bit REG_PAD3_RDE.
	LP_IOMUX_PAD3_REG_PAD3_RDE = 0x4
	// Position of REG_PAD3_RUE field.
	LP_IOMUX_PAD3_REG_PAD3_RUE_Pos = 0x3
	// Bit mask of REG_PAD3_RUE field.
	LP_IOMUX_PAD3_REG_PAD3_RUE_Msk = 0x8
	// Bit REG_PAD3_RUE.
	LP_IOMUX_PAD3_REG_PAD3_RUE = 0x8
	// Position of REG_PAD3_MUX_SEL field.
	LP_IOMUX_PAD3_REG_PAD3_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD3_MUX_SEL field.
	LP_IOMUX_PAD3_REG_PAD3_MUX_SEL_Msk = 0x10
	// Bit REG_PAD3_MUX_SEL.
	LP_IOMUX_PAD3_REG_PAD3_MUX_SEL = 0x10
	// Position of REG_PAD3_FUN_SEL field.
	LP_IOMUX_PAD3_REG_PAD3_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD3_FUN_SEL field.
	LP_IOMUX_PAD3_REG_PAD3_FUN_SEL_Msk = 0x60
	// Position of REG_PAD3_SLP_SEL field.
	LP_IOMUX_PAD3_REG_PAD3_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD3_SLP_SEL field.
	LP_IOMUX_PAD3_REG_PAD3_SLP_SEL_Msk = 0x80
	// Bit REG_PAD3_SLP_SEL.
	LP_IOMUX_PAD3_REG_PAD3_SLP_SEL = 0x80
	// Position of REG_PAD3_SLP_IE field.
	LP_IOMUX_PAD3_REG_PAD3_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD3_SLP_IE field.
	LP_IOMUX_PAD3_REG_PAD3_SLP_IE_Msk = 0x100
	// Bit REG_PAD3_SLP_IE.
	LP_IOMUX_PAD3_REG_PAD3_SLP_IE = 0x100
	// Position of REG_PAD3_SLP_OE field.
	LP_IOMUX_PAD3_REG_PAD3_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD3_SLP_OE field.
	LP_IOMUX_PAD3_REG_PAD3_SLP_OE_Msk = 0x200
	// Bit REG_PAD3_SLP_OE.
	LP_IOMUX_PAD3_REG_PAD3_SLP_OE = 0x200
	// Position of REG_PAD3_FUN_IE field.
	LP_IOMUX_PAD3_REG_PAD3_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD3_FUN_IE field.
	LP_IOMUX_PAD3_REG_PAD3_FUN_IE_Msk = 0x400
	// Bit REG_PAD3_FUN_IE.
	LP_IOMUX_PAD3_REG_PAD3_FUN_IE = 0x400
	// Position of REG_PAD3_FILTER_EN field.
	LP_IOMUX_PAD3_REG_PAD3_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD3_FILTER_EN field.
	LP_IOMUX_PAD3_REG_PAD3_FILTER_EN_Msk = 0x800
	// Bit REG_PAD3_FILTER_EN.
	LP_IOMUX_PAD3_REG_PAD3_FILTER_EN = 0x800

	// PAD4: Reserved
	// Position of REG_PAD4_DRV field.
	LP_IOMUX_PAD4_REG_PAD4_DRV_Pos = 0x0
	// Bit mask of REG_PAD4_DRV field.
	LP_IOMUX_PAD4_REG_PAD4_DRV_Msk = 0x3
	// Position of REG_PAD4_RDE field.
	LP_IOMUX_PAD4_REG_PAD4_RDE_Pos = 0x2
	// Bit mask of REG_PAD4_RDE field.
	LP_IOMUX_PAD4_REG_PAD4_RDE_Msk = 0x4
	// Bit REG_PAD4_RDE.
	LP_IOMUX_PAD4_REG_PAD4_RDE = 0x4
	// Position of REG_PAD4_RUE field.
	LP_IOMUX_PAD4_REG_PAD4_RUE_Pos = 0x3
	// Bit mask of REG_PAD4_RUE field.
	LP_IOMUX_PAD4_REG_PAD4_RUE_Msk = 0x8
	// Bit REG_PAD4_RUE.
	LP_IOMUX_PAD4_REG_PAD4_RUE = 0x8
	// Position of REG_PAD4_MUX_SEL field.
	LP_IOMUX_PAD4_REG_PAD4_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD4_MUX_SEL field.
	LP_IOMUX_PAD4_REG_PAD4_MUX_SEL_Msk = 0x10
	// Bit REG_PAD4_MUX_SEL.
	LP_IOMUX_PAD4_REG_PAD4_MUX_SEL = 0x10
	// Position of REG_PAD4_FUN_SEL field.
	LP_IOMUX_PAD4_REG_PAD4_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD4_FUN_SEL field.
	LP_IOMUX_PAD4_REG_PAD4_FUN_SEL_Msk = 0x60
	// Position of REG_PAD4_SLP_SEL field.
	LP_IOMUX_PAD4_REG_PAD4_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD4_SLP_SEL field.
	LP_IOMUX_PAD4_REG_PAD4_SLP_SEL_Msk = 0x80
	// Bit REG_PAD4_SLP_SEL.
	LP_IOMUX_PAD4_REG_PAD4_SLP_SEL = 0x80
	// Position of REG_PAD4_SLP_IE field.
	LP_IOMUX_PAD4_REG_PAD4_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD4_SLP_IE field.
	LP_IOMUX_PAD4_REG_PAD4_SLP_IE_Msk = 0x100
	// Bit REG_PAD4_SLP_IE.
	LP_IOMUX_PAD4_REG_PAD4_SLP_IE = 0x100
	// Position of REG_PAD4_SLP_OE field.
	LP_IOMUX_PAD4_REG_PAD4_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD4_SLP_OE field.
	LP_IOMUX_PAD4_REG_PAD4_SLP_OE_Msk = 0x200
	// Bit REG_PAD4_SLP_OE.
	LP_IOMUX_PAD4_REG_PAD4_SLP_OE = 0x200
	// Position of REG_PAD4_FUN_IE field.
	LP_IOMUX_PAD4_REG_PAD4_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD4_FUN_IE field.
	LP_IOMUX_PAD4_REG_PAD4_FUN_IE_Msk = 0x400
	// Bit REG_PAD4_FUN_IE.
	LP_IOMUX_PAD4_REG_PAD4_FUN_IE = 0x400
	// Position of REG_PAD4_FILTER_EN field.
	LP_IOMUX_PAD4_REG_PAD4_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD4_FILTER_EN field.
	LP_IOMUX_PAD4_REG_PAD4_FILTER_EN_Msk = 0x800
	// Bit REG_PAD4_FILTER_EN.
	LP_IOMUX_PAD4_REG_PAD4_FILTER_EN = 0x800

	// PAD5: Reserved
	// Position of REG_PAD5_DRV field.
	LP_IOMUX_PAD5_REG_PAD5_DRV_Pos = 0x0
	// Bit mask of REG_PAD5_DRV field.
	LP_IOMUX_PAD5_REG_PAD5_DRV_Msk = 0x3
	// Position of REG_PAD5_RDE field.
	LP_IOMUX_PAD5_REG_PAD5_RDE_Pos = 0x2
	// Bit mask of REG_PAD5_RDE field.
	LP_IOMUX_PAD5_REG_PAD5_RDE_Msk = 0x4
	// Bit REG_PAD5_RDE.
	LP_IOMUX_PAD5_REG_PAD5_RDE = 0x4
	// Position of REG_PAD5_RUE field.
	LP_IOMUX_PAD5_REG_PAD5_RUE_Pos = 0x3
	// Bit mask of REG_PAD5_RUE field.
	LP_IOMUX_PAD5_REG_PAD5_RUE_Msk = 0x8
	// Bit REG_PAD5_RUE.
	LP_IOMUX_PAD5_REG_PAD5_RUE = 0x8
	// Position of REG_PAD5_MUX_SEL field.
	LP_IOMUX_PAD5_REG_PAD5_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD5_MUX_SEL field.
	LP_IOMUX_PAD5_REG_PAD5_MUX_SEL_Msk = 0x10
	// Bit REG_PAD5_MUX_SEL.
	LP_IOMUX_PAD5_REG_PAD5_MUX_SEL = 0x10
	// Position of REG_PAD5_FUN_SEL field.
	LP_IOMUX_PAD5_REG_PAD5_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD5_FUN_SEL field.
	LP_IOMUX_PAD5_REG_PAD5_FUN_SEL_Msk = 0x60
	// Position of REG_PAD5_SLP_SEL field.
	LP_IOMUX_PAD5_REG_PAD5_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD5_SLP_SEL field.
	LP_IOMUX_PAD5_REG_PAD5_SLP_SEL_Msk = 0x80
	// Bit REG_PAD5_SLP_SEL.
	LP_IOMUX_PAD5_REG_PAD5_SLP_SEL = 0x80
	// Position of REG_PAD5_SLP_IE field.
	LP_IOMUX_PAD5_REG_PAD5_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD5_SLP_IE field.
	LP_IOMUX_PAD5_REG_PAD5_SLP_IE_Msk = 0x100
	// Bit REG_PAD5_SLP_IE.
	LP_IOMUX_PAD5_REG_PAD5_SLP_IE = 0x100
	// Position of REG_PAD5_SLP_OE field.
	LP_IOMUX_PAD5_REG_PAD5_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD5_SLP_OE field.
	LP_IOMUX_PAD5_REG_PAD5_SLP_OE_Msk = 0x200
	// Bit REG_PAD5_SLP_OE.
	LP_IOMUX_PAD5_REG_PAD5_SLP_OE = 0x200
	// Position of REG_PAD5_FUN_IE field.
	LP_IOMUX_PAD5_REG_PAD5_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD5_FUN_IE field.
	LP_IOMUX_PAD5_REG_PAD5_FUN_IE_Msk = 0x400
	// Bit REG_PAD5_FUN_IE.
	LP_IOMUX_PAD5_REG_PAD5_FUN_IE = 0x400
	// Position of REG_PAD5_FILTER_EN field.
	LP_IOMUX_PAD5_REG_PAD5_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD5_FILTER_EN field.
	LP_IOMUX_PAD5_REG_PAD5_FILTER_EN_Msk = 0x800
	// Bit REG_PAD5_FILTER_EN.
	LP_IOMUX_PAD5_REG_PAD5_FILTER_EN = 0x800

	// PAD6: Reserved
	// Position of REG_PAD6_DRV field.
	LP_IOMUX_PAD6_REG_PAD6_DRV_Pos = 0x0
	// Bit mask of REG_PAD6_DRV field.
	LP_IOMUX_PAD6_REG_PAD6_DRV_Msk = 0x3
	// Position of REG_PAD6_RDE field.
	LP_IOMUX_PAD6_REG_PAD6_RDE_Pos = 0x2
	// Bit mask of REG_PAD6_RDE field.
	LP_IOMUX_PAD6_REG_PAD6_RDE_Msk = 0x4
	// Bit REG_PAD6_RDE.
	LP_IOMUX_PAD6_REG_PAD6_RDE = 0x4
	// Position of REG_PAD6_RUE field.
	LP_IOMUX_PAD6_REG_PAD6_RUE_Pos = 0x3
	// Bit mask of REG_PAD6_RUE field.
	LP_IOMUX_PAD6_REG_PAD6_RUE_Msk = 0x8
	// Bit REG_PAD6_RUE.
	LP_IOMUX_PAD6_REG_PAD6_RUE = 0x8
	// Position of REG_PAD6_MUX_SEL field.
	LP_IOMUX_PAD6_REG_PAD6_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD6_MUX_SEL field.
	LP_IOMUX_PAD6_REG_PAD6_MUX_SEL_Msk = 0x10
	// Bit REG_PAD6_MUX_SEL.
	LP_IOMUX_PAD6_REG_PAD6_MUX_SEL = 0x10
	// Position of REG_PAD6_FUN_SEL field.
	LP_IOMUX_PAD6_REG_PAD6_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD6_FUN_SEL field.
	LP_IOMUX_PAD6_REG_PAD6_FUN_SEL_Msk = 0x60
	// Position of REG_PAD6_SLP_SEL field.
	LP_IOMUX_PAD6_REG_PAD6_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD6_SLP_SEL field.
	LP_IOMUX_PAD6_REG_PAD6_SLP_SEL_Msk = 0x80
	// Bit REG_PAD6_SLP_SEL.
	LP_IOMUX_PAD6_REG_PAD6_SLP_SEL = 0x80
	// Position of REG_PAD6_SLP_IE field.
	LP_IOMUX_PAD6_REG_PAD6_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD6_SLP_IE field.
	LP_IOMUX_PAD6_REG_PAD6_SLP_IE_Msk = 0x100
	// Bit REG_PAD6_SLP_IE.
	LP_IOMUX_PAD6_REG_PAD6_SLP_IE = 0x100
	// Position of REG_PAD6_SLP_OE field.
	LP_IOMUX_PAD6_REG_PAD6_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD6_SLP_OE field.
	LP_IOMUX_PAD6_REG_PAD6_SLP_OE_Msk = 0x200
	// Bit REG_PAD6_SLP_OE.
	LP_IOMUX_PAD6_REG_PAD6_SLP_OE = 0x200
	// Position of REG_PAD6_FUN_IE field.
	LP_IOMUX_PAD6_REG_PAD6_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD6_FUN_IE field.
	LP_IOMUX_PAD6_REG_PAD6_FUN_IE_Msk = 0x400
	// Bit REG_PAD6_FUN_IE.
	LP_IOMUX_PAD6_REG_PAD6_FUN_IE = 0x400
	// Position of REG_PAD6_FILTER_EN field.
	LP_IOMUX_PAD6_REG_PAD6_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD6_FILTER_EN field.
	LP_IOMUX_PAD6_REG_PAD6_FILTER_EN_Msk = 0x800
	// Bit REG_PAD6_FILTER_EN.
	LP_IOMUX_PAD6_REG_PAD6_FILTER_EN = 0x800

	// PAD7: Reserved
	// Position of REG_PAD7_DRV field.
	LP_IOMUX_PAD7_REG_PAD7_DRV_Pos = 0x0
	// Bit mask of REG_PAD7_DRV field.
	LP_IOMUX_PAD7_REG_PAD7_DRV_Msk = 0x3
	// Position of REG_PAD7_RDE field.
	LP_IOMUX_PAD7_REG_PAD7_RDE_Pos = 0x2
	// Bit mask of REG_PAD7_RDE field.
	LP_IOMUX_PAD7_REG_PAD7_RDE_Msk = 0x4
	// Bit REG_PAD7_RDE.
	LP_IOMUX_PAD7_REG_PAD7_RDE = 0x4
	// Position of REG_PAD7_RUE field.
	LP_IOMUX_PAD7_REG_PAD7_RUE_Pos = 0x3
	// Bit mask of REG_PAD7_RUE field.
	LP_IOMUX_PAD7_REG_PAD7_RUE_Msk = 0x8
	// Bit REG_PAD7_RUE.
	LP_IOMUX_PAD7_REG_PAD7_RUE = 0x8
	// Position of REG_PAD7_MUX_SEL field.
	LP_IOMUX_PAD7_REG_PAD7_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD7_MUX_SEL field.
	LP_IOMUX_PAD7_REG_PAD7_MUX_SEL_Msk = 0x10
	// Bit REG_PAD7_MUX_SEL.
	LP_IOMUX_PAD7_REG_PAD7_MUX_SEL = 0x10
	// Position of REG_PAD7_FUN_SEL field.
	LP_IOMUX_PAD7_REG_PAD7_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD7_FUN_SEL field.
	LP_IOMUX_PAD7_REG_PAD7_FUN_SEL_Msk = 0x60
	// Position of REG_PAD7_SLP_SEL field.
	LP_IOMUX_PAD7_REG_PAD7_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD7_SLP_SEL field.
	LP_IOMUX_PAD7_REG_PAD7_SLP_SEL_Msk = 0x80
	// Bit REG_PAD7_SLP_SEL.
	LP_IOMUX_PAD7_REG_PAD7_SLP_SEL = 0x80
	// Position of REG_PAD7_SLP_IE field.
	LP_IOMUX_PAD7_REG_PAD7_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD7_SLP_IE field.
	LP_IOMUX_PAD7_REG_PAD7_SLP_IE_Msk = 0x100
	// Bit REG_PAD7_SLP_IE.
	LP_IOMUX_PAD7_REG_PAD7_SLP_IE = 0x100
	// Position of REG_PAD7_SLP_OE field.
	LP_IOMUX_PAD7_REG_PAD7_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD7_SLP_OE field.
	LP_IOMUX_PAD7_REG_PAD7_SLP_OE_Msk = 0x200
	// Bit REG_PAD7_SLP_OE.
	LP_IOMUX_PAD7_REG_PAD7_SLP_OE = 0x200
	// Position of REG_PAD7_FUN_IE field.
	LP_IOMUX_PAD7_REG_PAD7_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD7_FUN_IE field.
	LP_IOMUX_PAD7_REG_PAD7_FUN_IE_Msk = 0x400
	// Bit REG_PAD7_FUN_IE.
	LP_IOMUX_PAD7_REG_PAD7_FUN_IE = 0x400
	// Position of REG_PAD7_FILTER_EN field.
	LP_IOMUX_PAD7_REG_PAD7_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD7_FILTER_EN field.
	LP_IOMUX_PAD7_REG_PAD7_FILTER_EN_Msk = 0x800
	// Bit REG_PAD7_FILTER_EN.
	LP_IOMUX_PAD7_REG_PAD7_FILTER_EN = 0x800

	// PAD8: Reserved
	// Position of REG_PAD8_DRV field.
	LP_IOMUX_PAD8_REG_PAD8_DRV_Pos = 0x0
	// Bit mask of REG_PAD8_DRV field.
	LP_IOMUX_PAD8_REG_PAD8_DRV_Msk = 0x3
	// Position of REG_PAD8_RDE field.
	LP_IOMUX_PAD8_REG_PAD8_RDE_Pos = 0x2
	// Bit mask of REG_PAD8_RDE field.
	LP_IOMUX_PAD8_REG_PAD8_RDE_Msk = 0x4
	// Bit REG_PAD8_RDE.
	LP_IOMUX_PAD8_REG_PAD8_RDE = 0x4
	// Position of REG_PAD8_RUE field.
	LP_IOMUX_PAD8_REG_PAD8_RUE_Pos = 0x3
	// Bit mask of REG_PAD8_RUE field.
	LP_IOMUX_PAD8_REG_PAD8_RUE_Msk = 0x8
	// Bit REG_PAD8_RUE.
	LP_IOMUX_PAD8_REG_PAD8_RUE = 0x8
	// Position of REG_PAD8_MUX_SEL field.
	LP_IOMUX_PAD8_REG_PAD8_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD8_MUX_SEL field.
	LP_IOMUX_PAD8_REG_PAD8_MUX_SEL_Msk = 0x10
	// Bit REG_PAD8_MUX_SEL.
	LP_IOMUX_PAD8_REG_PAD8_MUX_SEL = 0x10
	// Position of REG_PAD8_FUN_SEL field.
	LP_IOMUX_PAD8_REG_PAD8_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD8_FUN_SEL field.
	LP_IOMUX_PAD8_REG_PAD8_FUN_SEL_Msk = 0x60
	// Position of REG_PAD8_SLP_SEL field.
	LP_IOMUX_PAD8_REG_PAD8_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD8_SLP_SEL field.
	LP_IOMUX_PAD8_REG_PAD8_SLP_SEL_Msk = 0x80
	// Bit REG_PAD8_SLP_SEL.
	LP_IOMUX_PAD8_REG_PAD8_SLP_SEL = 0x80
	// Position of REG_PAD8_SLP_IE field.
	LP_IOMUX_PAD8_REG_PAD8_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD8_SLP_IE field.
	LP_IOMUX_PAD8_REG_PAD8_SLP_IE_Msk = 0x100
	// Bit REG_PAD8_SLP_IE.
	LP_IOMUX_PAD8_REG_PAD8_SLP_IE = 0x100
	// Position of REG_PAD8_SLP_OE field.
	LP_IOMUX_PAD8_REG_PAD8_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD8_SLP_OE field.
	LP_IOMUX_PAD8_REG_PAD8_SLP_OE_Msk = 0x200
	// Bit REG_PAD8_SLP_OE.
	LP_IOMUX_PAD8_REG_PAD8_SLP_OE = 0x200
	// Position of REG_PAD8_FUN_IE field.
	LP_IOMUX_PAD8_REG_PAD8_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD8_FUN_IE field.
	LP_IOMUX_PAD8_REG_PAD8_FUN_IE_Msk = 0x400
	// Bit REG_PAD8_FUN_IE.
	LP_IOMUX_PAD8_REG_PAD8_FUN_IE = 0x400
	// Position of REG_PAD8_FILTER_EN field.
	LP_IOMUX_PAD8_REG_PAD8_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD8_FILTER_EN field.
	LP_IOMUX_PAD8_REG_PAD8_FILTER_EN_Msk = 0x800
	// Bit REG_PAD8_FILTER_EN.
	LP_IOMUX_PAD8_REG_PAD8_FILTER_EN = 0x800

	// PAD9: Reserved
	// Position of REG_PAD9_DRV field.
	LP_IOMUX_PAD9_REG_PAD9_DRV_Pos = 0x0
	// Bit mask of REG_PAD9_DRV field.
	LP_IOMUX_PAD9_REG_PAD9_DRV_Msk = 0x3
	// Position of REG_PAD9_RDE field.
	LP_IOMUX_PAD9_REG_PAD9_RDE_Pos = 0x2
	// Bit mask of REG_PAD9_RDE field.
	LP_IOMUX_PAD9_REG_PAD9_RDE_Msk = 0x4
	// Bit REG_PAD9_RDE.
	LP_IOMUX_PAD9_REG_PAD9_RDE = 0x4
	// Position of REG_PAD9_RUE field.
	LP_IOMUX_PAD9_REG_PAD9_RUE_Pos = 0x3
	// Bit mask of REG_PAD9_RUE field.
	LP_IOMUX_PAD9_REG_PAD9_RUE_Msk = 0x8
	// Bit REG_PAD9_RUE.
	LP_IOMUX_PAD9_REG_PAD9_RUE = 0x8
	// Position of REG_PAD9_MUX_SEL field.
	LP_IOMUX_PAD9_REG_PAD9_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD9_MUX_SEL field.
	LP_IOMUX_PAD9_REG_PAD9_MUX_SEL_Msk = 0x10
	// Bit REG_PAD9_MUX_SEL.
	LP_IOMUX_PAD9_REG_PAD9_MUX_SEL = 0x10
	// Position of REG_PAD9_FUN_SEL field.
	LP_IOMUX_PAD9_REG_PAD9_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD9_FUN_SEL field.
	LP_IOMUX_PAD9_REG_PAD9_FUN_SEL_Msk = 0x60
	// Position of REG_PAD9_SLP_SEL field.
	LP_IOMUX_PAD9_REG_PAD9_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD9_SLP_SEL field.
	LP_IOMUX_PAD9_REG_PAD9_SLP_SEL_Msk = 0x80
	// Bit REG_PAD9_SLP_SEL.
	LP_IOMUX_PAD9_REG_PAD9_SLP_SEL = 0x80
	// Position of REG_PAD9_SLP_IE field.
	LP_IOMUX_PAD9_REG_PAD9_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD9_SLP_IE field.
	LP_IOMUX_PAD9_REG_PAD9_SLP_IE_Msk = 0x100
	// Bit REG_PAD9_SLP_IE.
	LP_IOMUX_PAD9_REG_PAD9_SLP_IE = 0x100
	// Position of REG_PAD9_SLP_OE field.
	LP_IOMUX_PAD9_REG_PAD9_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD9_SLP_OE field.
	LP_IOMUX_PAD9_REG_PAD9_SLP_OE_Msk = 0x200
	// Bit REG_PAD9_SLP_OE.
	LP_IOMUX_PAD9_REG_PAD9_SLP_OE = 0x200
	// Position of REG_PAD9_FUN_IE field.
	LP_IOMUX_PAD9_REG_PAD9_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD9_FUN_IE field.
	LP_IOMUX_PAD9_REG_PAD9_FUN_IE_Msk = 0x400
	// Bit REG_PAD9_FUN_IE.
	LP_IOMUX_PAD9_REG_PAD9_FUN_IE = 0x400
	// Position of REG_PAD9_FILTER_EN field.
	LP_IOMUX_PAD9_REG_PAD9_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD9_FILTER_EN field.
	LP_IOMUX_PAD9_REG_PAD9_FILTER_EN_Msk = 0x800
	// Bit REG_PAD9_FILTER_EN.
	LP_IOMUX_PAD9_REG_PAD9_FILTER_EN = 0x800

	// PAD10: Reserved
	// Position of REG_PAD10_DRV field.
	LP_IOMUX_PAD10_REG_PAD10_DRV_Pos = 0x0
	// Bit mask of REG_PAD10_DRV field.
	LP_IOMUX_PAD10_REG_PAD10_DRV_Msk = 0x3
	// Position of REG_PAD10_RDE field.
	LP_IOMUX_PAD10_REG_PAD10_RDE_Pos = 0x2
	// Bit mask of REG_PAD10_RDE field.
	LP_IOMUX_PAD10_REG_PAD10_RDE_Msk = 0x4
	// Bit REG_PAD10_RDE.
	LP_IOMUX_PAD10_REG_PAD10_RDE = 0x4
	// Position of REG_PAD10_RUE field.
	LP_IOMUX_PAD10_REG_PAD10_RUE_Pos = 0x3
	// Bit mask of REG_PAD10_RUE field.
	LP_IOMUX_PAD10_REG_PAD10_RUE_Msk = 0x8
	// Bit REG_PAD10_RUE.
	LP_IOMUX_PAD10_REG_PAD10_RUE = 0x8
	// Position of REG_PAD10_MUX_SEL field.
	LP_IOMUX_PAD10_REG_PAD10_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD10_MUX_SEL field.
	LP_IOMUX_PAD10_REG_PAD10_MUX_SEL_Msk = 0x10
	// Bit REG_PAD10_MUX_SEL.
	LP_IOMUX_PAD10_REG_PAD10_MUX_SEL = 0x10
	// Position of REG_PAD10_FUN_SEL field.
	LP_IOMUX_PAD10_REG_PAD10_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD10_FUN_SEL field.
	LP_IOMUX_PAD10_REG_PAD10_FUN_SEL_Msk = 0x60
	// Position of REG_PAD10_SLP_SEL field.
	LP_IOMUX_PAD10_REG_PAD10_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD10_SLP_SEL field.
	LP_IOMUX_PAD10_REG_PAD10_SLP_SEL_Msk = 0x80
	// Bit REG_PAD10_SLP_SEL.
	LP_IOMUX_PAD10_REG_PAD10_SLP_SEL = 0x80
	// Position of REG_PAD10_SLP_IE field.
	LP_IOMUX_PAD10_REG_PAD10_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD10_SLP_IE field.
	LP_IOMUX_PAD10_REG_PAD10_SLP_IE_Msk = 0x100
	// Bit REG_PAD10_SLP_IE.
	LP_IOMUX_PAD10_REG_PAD10_SLP_IE = 0x100
	// Position of REG_PAD10_SLP_OE field.
	LP_IOMUX_PAD10_REG_PAD10_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD10_SLP_OE field.
	LP_IOMUX_PAD10_REG_PAD10_SLP_OE_Msk = 0x200
	// Bit REG_PAD10_SLP_OE.
	LP_IOMUX_PAD10_REG_PAD10_SLP_OE = 0x200
	// Position of REG_PAD10_FUN_IE field.
	LP_IOMUX_PAD10_REG_PAD10_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD10_FUN_IE field.
	LP_IOMUX_PAD10_REG_PAD10_FUN_IE_Msk = 0x400
	// Bit REG_PAD10_FUN_IE.
	LP_IOMUX_PAD10_REG_PAD10_FUN_IE = 0x400
	// Position of REG_PAD10_FILTER_EN field.
	LP_IOMUX_PAD10_REG_PAD10_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD10_FILTER_EN field.
	LP_IOMUX_PAD10_REG_PAD10_FILTER_EN_Msk = 0x800
	// Bit REG_PAD10_FILTER_EN.
	LP_IOMUX_PAD10_REG_PAD10_FILTER_EN = 0x800

	// PAD11: Reserved
	// Position of REG_PAD11_DRV field.
	LP_IOMUX_PAD11_REG_PAD11_DRV_Pos = 0x0
	// Bit mask of REG_PAD11_DRV field.
	LP_IOMUX_PAD11_REG_PAD11_DRV_Msk = 0x3
	// Position of REG_PAD11_RDE field.
	LP_IOMUX_PAD11_REG_PAD11_RDE_Pos = 0x2
	// Bit mask of REG_PAD11_RDE field.
	LP_IOMUX_PAD11_REG_PAD11_RDE_Msk = 0x4
	// Bit REG_PAD11_RDE.
	LP_IOMUX_PAD11_REG_PAD11_RDE = 0x4
	// Position of REG_PAD11_RUE field.
	LP_IOMUX_PAD11_REG_PAD11_RUE_Pos = 0x3
	// Bit mask of REG_PAD11_RUE field.
	LP_IOMUX_PAD11_REG_PAD11_RUE_Msk = 0x8
	// Bit REG_PAD11_RUE.
	LP_IOMUX_PAD11_REG_PAD11_RUE = 0x8
	// Position of REG_PAD11_MUX_SEL field.
	LP_IOMUX_PAD11_REG_PAD11_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD11_MUX_SEL field.
	LP_IOMUX_PAD11_REG_PAD11_MUX_SEL_Msk = 0x10
	// Bit REG_PAD11_MUX_SEL.
	LP_IOMUX_PAD11_REG_PAD11_MUX_SEL = 0x10
	// Position of REG_PAD11_FUN_SEL field.
	LP_IOMUX_PAD11_REG_PAD11_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD11_FUN_SEL field.
	LP_IOMUX_PAD11_REG_PAD11_FUN_SEL_Msk = 0x60
	// Position of REG_PAD11_SLP_SEL field.
	LP_IOMUX_PAD11_REG_PAD11_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD11_SLP_SEL field.
	LP_IOMUX_PAD11_REG_PAD11_SLP_SEL_Msk = 0x80
	// Bit REG_PAD11_SLP_SEL.
	LP_IOMUX_PAD11_REG_PAD11_SLP_SEL = 0x80
	// Position of REG_PAD11_SLP_IE field.
	LP_IOMUX_PAD11_REG_PAD11_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD11_SLP_IE field.
	LP_IOMUX_PAD11_REG_PAD11_SLP_IE_Msk = 0x100
	// Bit REG_PAD11_SLP_IE.
	LP_IOMUX_PAD11_REG_PAD11_SLP_IE = 0x100
	// Position of REG_PAD11_SLP_OE field.
	LP_IOMUX_PAD11_REG_PAD11_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD11_SLP_OE field.
	LP_IOMUX_PAD11_REG_PAD11_SLP_OE_Msk = 0x200
	// Bit REG_PAD11_SLP_OE.
	LP_IOMUX_PAD11_REG_PAD11_SLP_OE = 0x200
	// Position of REG_PAD11_FUN_IE field.
	LP_IOMUX_PAD11_REG_PAD11_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD11_FUN_IE field.
	LP_IOMUX_PAD11_REG_PAD11_FUN_IE_Msk = 0x400
	// Bit REG_PAD11_FUN_IE.
	LP_IOMUX_PAD11_REG_PAD11_FUN_IE = 0x400
	// Position of REG_PAD11_FILTER_EN field.
	LP_IOMUX_PAD11_REG_PAD11_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD11_FILTER_EN field.
	LP_IOMUX_PAD11_REG_PAD11_FILTER_EN_Msk = 0x800
	// Bit REG_PAD11_FILTER_EN.
	LP_IOMUX_PAD11_REG_PAD11_FILTER_EN = 0x800

	// PAD120: Reserved
	// Position of REG_PAD12_DRV field.
	LP_IOMUX_PAD120_REG_PAD12_DRV_Pos = 0x0
	// Bit mask of REG_PAD12_DRV field.
	LP_IOMUX_PAD120_REG_PAD12_DRV_Msk = 0x3
	// Position of REG_PAD12_RDE field.
	LP_IOMUX_PAD120_REG_PAD12_RDE_Pos = 0x2
	// Bit mask of REG_PAD12_RDE field.
	LP_IOMUX_PAD120_REG_PAD12_RDE_Msk = 0x4
	// Bit REG_PAD12_RDE.
	LP_IOMUX_PAD120_REG_PAD12_RDE = 0x4
	// Position of REG_PAD12_RUE field.
	LP_IOMUX_PAD120_REG_PAD12_RUE_Pos = 0x3
	// Bit mask of REG_PAD12_RUE field.
	LP_IOMUX_PAD120_REG_PAD12_RUE_Msk = 0x8
	// Bit REG_PAD12_RUE.
	LP_IOMUX_PAD120_REG_PAD12_RUE = 0x8
	// Position of REG_PAD12_MUX_SEL field.
	LP_IOMUX_PAD120_REG_PAD12_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD12_MUX_SEL field.
	LP_IOMUX_PAD120_REG_PAD12_MUX_SEL_Msk = 0x10
	// Bit REG_PAD12_MUX_SEL.
	LP_IOMUX_PAD120_REG_PAD12_MUX_SEL = 0x10
	// Position of REG_PAD12_FUN_SEL field.
	LP_IOMUX_PAD120_REG_PAD12_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD12_FUN_SEL field.
	LP_IOMUX_PAD120_REG_PAD12_FUN_SEL_Msk = 0x60
	// Position of REG_PAD12_SLP_SEL field.
	LP_IOMUX_PAD120_REG_PAD12_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD12_SLP_SEL field.
	LP_IOMUX_PAD120_REG_PAD12_SLP_SEL_Msk = 0x80
	// Bit REG_PAD12_SLP_SEL.
	LP_IOMUX_PAD120_REG_PAD12_SLP_SEL = 0x80
	// Position of REG_PAD12_SLP_IE field.
	LP_IOMUX_PAD120_REG_PAD12_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD12_SLP_IE field.
	LP_IOMUX_PAD120_REG_PAD12_SLP_IE_Msk = 0x100
	// Bit REG_PAD12_SLP_IE.
	LP_IOMUX_PAD120_REG_PAD12_SLP_IE = 0x100
	// Position of REG_PAD12_SLP_OE field.
	LP_IOMUX_PAD120_REG_PAD12_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD12_SLP_OE field.
	LP_IOMUX_PAD120_REG_PAD12_SLP_OE_Msk = 0x200
	// Bit REG_PAD12_SLP_OE.
	LP_IOMUX_PAD120_REG_PAD12_SLP_OE = 0x200
	// Position of REG_PAD12_FUN_IE field.
	LP_IOMUX_PAD120_REG_PAD12_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD12_FUN_IE field.
	LP_IOMUX_PAD120_REG_PAD12_FUN_IE_Msk = 0x400
	// Bit REG_PAD12_FUN_IE.
	LP_IOMUX_PAD120_REG_PAD12_FUN_IE = 0x400
	// Position of REG_PAD12_FILTER_EN field.
	LP_IOMUX_PAD120_REG_PAD12_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD12_FILTER_EN field.
	LP_IOMUX_PAD120_REG_PAD12_FILTER_EN_Msk = 0x800
	// Bit REG_PAD12_FILTER_EN.
	LP_IOMUX_PAD120_REG_PAD12_FILTER_EN = 0x800

	// PAD13: Reserved
	// Position of REG_PAD13_DRV field.
	LP_IOMUX_PAD13_REG_PAD13_DRV_Pos = 0x0
	// Bit mask of REG_PAD13_DRV field.
	LP_IOMUX_PAD13_REG_PAD13_DRV_Msk = 0x3
	// Position of REG_PAD13_RDE field.
	LP_IOMUX_PAD13_REG_PAD13_RDE_Pos = 0x2
	// Bit mask of REG_PAD13_RDE field.
	LP_IOMUX_PAD13_REG_PAD13_RDE_Msk = 0x4
	// Bit REG_PAD13_RDE.
	LP_IOMUX_PAD13_REG_PAD13_RDE = 0x4
	// Position of REG_PAD13_RUE field.
	LP_IOMUX_PAD13_REG_PAD13_RUE_Pos = 0x3
	// Bit mask of REG_PAD13_RUE field.
	LP_IOMUX_PAD13_REG_PAD13_RUE_Msk = 0x8
	// Bit REG_PAD13_RUE.
	LP_IOMUX_PAD13_REG_PAD13_RUE = 0x8
	// Position of REG_PAD13_MUX_SEL field.
	LP_IOMUX_PAD13_REG_PAD13_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD13_MUX_SEL field.
	LP_IOMUX_PAD13_REG_PAD13_MUX_SEL_Msk = 0x10
	// Bit REG_PAD13_MUX_SEL.
	LP_IOMUX_PAD13_REG_PAD13_MUX_SEL = 0x10
	// Position of REG_PAD13_FUN_SEL field.
	LP_IOMUX_PAD13_REG_PAD13_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD13_FUN_SEL field.
	LP_IOMUX_PAD13_REG_PAD13_FUN_SEL_Msk = 0x60
	// Position of REG_PAD13_SLP_SEL field.
	LP_IOMUX_PAD13_REG_PAD13_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD13_SLP_SEL field.
	LP_IOMUX_PAD13_REG_PAD13_SLP_SEL_Msk = 0x80
	// Bit REG_PAD13_SLP_SEL.
	LP_IOMUX_PAD13_REG_PAD13_SLP_SEL = 0x80
	// Position of REG_PAD13_SLP_IE field.
	LP_IOMUX_PAD13_REG_PAD13_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD13_SLP_IE field.
	LP_IOMUX_PAD13_REG_PAD13_SLP_IE_Msk = 0x100
	// Bit REG_PAD13_SLP_IE.
	LP_IOMUX_PAD13_REG_PAD13_SLP_IE = 0x100
	// Position of REG_PAD13_SLP_OE field.
	LP_IOMUX_PAD13_REG_PAD13_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD13_SLP_OE field.
	LP_IOMUX_PAD13_REG_PAD13_SLP_OE_Msk = 0x200
	// Bit REG_PAD13_SLP_OE.
	LP_IOMUX_PAD13_REG_PAD13_SLP_OE = 0x200
	// Position of REG_PAD13_FUN_IE field.
	LP_IOMUX_PAD13_REG_PAD13_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD13_FUN_IE field.
	LP_IOMUX_PAD13_REG_PAD13_FUN_IE_Msk = 0x400
	// Bit REG_PAD13_FUN_IE.
	LP_IOMUX_PAD13_REG_PAD13_FUN_IE = 0x400
	// Position of REG_PAD13_FILTER_EN field.
	LP_IOMUX_PAD13_REG_PAD13_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD13_FILTER_EN field.
	LP_IOMUX_PAD13_REG_PAD13_FILTER_EN_Msk = 0x800
	// Bit REG_PAD13_FILTER_EN.
	LP_IOMUX_PAD13_REG_PAD13_FILTER_EN = 0x800

	// PAD14: Reserved
	// Position of REG_PAD14_DRV field.
	LP_IOMUX_PAD14_REG_PAD14_DRV_Pos = 0x0
	// Bit mask of REG_PAD14_DRV field.
	LP_IOMUX_PAD14_REG_PAD14_DRV_Msk = 0x3
	// Position of REG_PAD14_RDE field.
	LP_IOMUX_PAD14_REG_PAD14_RDE_Pos = 0x2
	// Bit mask of REG_PAD14_RDE field.
	LP_IOMUX_PAD14_REG_PAD14_RDE_Msk = 0x4
	// Bit REG_PAD14_RDE.
	LP_IOMUX_PAD14_REG_PAD14_RDE = 0x4
	// Position of REG_PAD14_RUE field.
	LP_IOMUX_PAD14_REG_PAD14_RUE_Pos = 0x3
	// Bit mask of REG_PAD14_RUE field.
	LP_IOMUX_PAD14_REG_PAD14_RUE_Msk = 0x8
	// Bit REG_PAD14_RUE.
	LP_IOMUX_PAD14_REG_PAD14_RUE = 0x8
	// Position of REG_PAD14_MUX_SEL field.
	LP_IOMUX_PAD14_REG_PAD14_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD14_MUX_SEL field.
	LP_IOMUX_PAD14_REG_PAD14_MUX_SEL_Msk = 0x10
	// Bit REG_PAD14_MUX_SEL.
	LP_IOMUX_PAD14_REG_PAD14_MUX_SEL = 0x10
	// Position of REG_PAD14_FUN_SEL field.
	LP_IOMUX_PAD14_REG_PAD14_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD14_FUN_SEL field.
	LP_IOMUX_PAD14_REG_PAD14_FUN_SEL_Msk = 0x60
	// Position of REG_PAD14_SLP_SEL field.
	LP_IOMUX_PAD14_REG_PAD14_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD14_SLP_SEL field.
	LP_IOMUX_PAD14_REG_PAD14_SLP_SEL_Msk = 0x80
	// Bit REG_PAD14_SLP_SEL.
	LP_IOMUX_PAD14_REG_PAD14_SLP_SEL = 0x80
	// Position of REG_PAD14_SLP_IE field.
	LP_IOMUX_PAD14_REG_PAD14_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD14_SLP_IE field.
	LP_IOMUX_PAD14_REG_PAD14_SLP_IE_Msk = 0x100
	// Bit REG_PAD14_SLP_IE.
	LP_IOMUX_PAD14_REG_PAD14_SLP_IE = 0x100
	// Position of REG_PAD14_SLP_OE field.
	LP_IOMUX_PAD14_REG_PAD14_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD14_SLP_OE field.
	LP_IOMUX_PAD14_REG_PAD14_SLP_OE_Msk = 0x200
	// Bit REG_PAD14_SLP_OE.
	LP_IOMUX_PAD14_REG_PAD14_SLP_OE = 0x200
	// Position of REG_PAD14_FUN_IE field.
	LP_IOMUX_PAD14_REG_PAD14_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD14_FUN_IE field.
	LP_IOMUX_PAD14_REG_PAD14_FUN_IE_Msk = 0x400
	// Bit REG_PAD14_FUN_IE.
	LP_IOMUX_PAD14_REG_PAD14_FUN_IE = 0x400
	// Position of REG_PAD14_FILTER_EN field.
	LP_IOMUX_PAD14_REG_PAD14_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD14_FILTER_EN field.
	LP_IOMUX_PAD14_REG_PAD14_FILTER_EN_Msk = 0x800
	// Bit REG_PAD14_FILTER_EN.
	LP_IOMUX_PAD14_REG_PAD14_FILTER_EN = 0x800

	// PAD15: Reserved
	// Position of REG_PAD15_DRV field.
	LP_IOMUX_PAD15_REG_PAD15_DRV_Pos = 0x0
	// Bit mask of REG_PAD15_DRV field.
	LP_IOMUX_PAD15_REG_PAD15_DRV_Msk = 0x3
	// Position of REG_PAD15_RDE field.
	LP_IOMUX_PAD15_REG_PAD15_RDE_Pos = 0x2
	// Bit mask of REG_PAD15_RDE field.
	LP_IOMUX_PAD15_REG_PAD15_RDE_Msk = 0x4
	// Bit REG_PAD15_RDE.
	LP_IOMUX_PAD15_REG_PAD15_RDE = 0x4
	// Position of REG_PAD15_RUE field.
	LP_IOMUX_PAD15_REG_PAD15_RUE_Pos = 0x3
	// Bit mask of REG_PAD15_RUE field.
	LP_IOMUX_PAD15_REG_PAD15_RUE_Msk = 0x8
	// Bit REG_PAD15_RUE.
	LP_IOMUX_PAD15_REG_PAD15_RUE = 0x8
	// Position of REG_PAD15_MUX_SEL field.
	LP_IOMUX_PAD15_REG_PAD15_MUX_SEL_Pos = 0x4
	// Bit mask of REG_PAD15_MUX_SEL field.
	LP_IOMUX_PAD15_REG_PAD15_MUX_SEL_Msk = 0x10
	// Bit REG_PAD15_MUX_SEL.
	LP_IOMUX_PAD15_REG_PAD15_MUX_SEL = 0x10
	// Position of REG_PAD15_FUN_SEL field.
	LP_IOMUX_PAD15_REG_PAD15_FUN_SEL_Pos = 0x5
	// Bit mask of REG_PAD15_FUN_SEL field.
	LP_IOMUX_PAD15_REG_PAD15_FUN_SEL_Msk = 0x60
	// Position of REG_PAD15_SLP_SEL field.
	LP_IOMUX_PAD15_REG_PAD15_SLP_SEL_Pos = 0x7
	// Bit mask of REG_PAD15_SLP_SEL field.
	LP_IOMUX_PAD15_REG_PAD15_SLP_SEL_Msk = 0x80
	// Bit REG_PAD15_SLP_SEL.
	LP_IOMUX_PAD15_REG_PAD15_SLP_SEL = 0x80
	// Position of REG_PAD15_SLP_IE field.
	LP_IOMUX_PAD15_REG_PAD15_SLP_IE_Pos = 0x8
	// Bit mask of REG_PAD15_SLP_IE field.
	LP_IOMUX_PAD15_REG_PAD15_SLP_IE_Msk = 0x100
	// Bit REG_PAD15_SLP_IE.
	LP_IOMUX_PAD15_REG_PAD15_SLP_IE = 0x100
	// Position of REG_PAD15_SLP_OE field.
	LP_IOMUX_PAD15_REG_PAD15_SLP_OE_Pos = 0x9
	// Bit mask of REG_PAD15_SLP_OE field.
	LP_IOMUX_PAD15_REG_PAD15_SLP_OE_Msk = 0x200
	// Bit REG_PAD15_SLP_OE.
	LP_IOMUX_PAD15_REG_PAD15_SLP_OE = 0x200
	// Position of REG_PAD15_FUN_IE field.
	LP_IOMUX_PAD15_REG_PAD15_FUN_IE_Pos = 0xa
	// Bit mask of REG_PAD15_FUN_IE field.
	LP_IOMUX_PAD15_REG_PAD15_FUN_IE_Msk = 0x400
	// Bit REG_PAD15_FUN_IE.
	LP_IOMUX_PAD15_REG_PAD15_FUN_IE = 0x400
	// Position of REG_PAD15_FILTER_EN field.
	LP_IOMUX_PAD15_REG_PAD15_FILTER_EN_Pos = 0xb
	// Bit mask of REG_PAD15_FILTER_EN field.
	LP_IOMUX_PAD15_REG_PAD15_FILTER_EN_Msk = 0x800
	// Bit REG_PAD15_FILTER_EN.
	LP_IOMUX_PAD15_REG_PAD15_FILTER_EN = 0x800

	// EXT_WAKEUP0_SEL: Reserved
	// Position of REG_XTL_EXT_CTR_SEL field.
	LP_IOMUX_EXT_WAKEUP0_SEL_REG_XTL_EXT_CTR_SEL_Pos = 0x0
	// Bit mask of REG_XTL_EXT_CTR_SEL field.
	LP_IOMUX_EXT_WAKEUP0_SEL_REG_XTL_EXT_CTR_SEL_Msk = 0x1f
	// Position of REG_EXT_WAKEUP0_SEL field.
	LP_IOMUX_EXT_WAKEUP0_SEL_REG_EXT_WAKEUP0_SEL_Pos = 0x5
	// Bit mask of REG_EXT_WAKEUP0_SEL field.
	LP_IOMUX_EXT_WAKEUP0_SEL_REG_EXT_WAKEUP0_SEL_Msk = 0x3e0

	// LP_PAD_HOLD: Reserved
	// Position of REG_LP_GPIO_HOLD field.
	LP_IOMUX_LP_PAD_HOLD_REG_LP_GPIO_HOLD_Pos = 0x0
	// Bit mask of REG_LP_GPIO_HOLD field.
	LP_IOMUX_LP_PAD_HOLD_REG_LP_GPIO_HOLD_Msk = 0xffff

	// LP_PAD_HYS: Reserved
	// Position of REG_LP_GPIO_HYS field.
	LP_IOMUX_LP_PAD_HYS_REG_LP_GPIO_HYS_Pos = 0x0
	// Bit mask of REG_LP_GPIO_HYS field.
	LP_IOMUX_LP_PAD_HYS_REG_LP_GPIO_HYS_Msk = 0xffff
)

// Constants for LP_UART: Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller
const (
	// FIFO: FIFO data register
	// Position of RXFIFO_RD_BYTE field.
	LP_UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0
	// Bit mask of RXFIFO_RD_BYTE field.
	LP_UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff

	// INT_RAW: Raw interrupt status
	// Position of RXFIFO_FULL_INT_RAW field.
	LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_RAW field.
	LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1
	// Bit RXFIFO_FULL_INT_RAW.
	LP_UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1
	// Position of TXFIFO_EMPTY_INT_RAW field.
	LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_RAW field.
	LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_RAW.
	LP_UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2
	// Position of PARITY_ERR_INT_RAW field.
	LP_UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_RAW field.
	LP_UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4
	// Bit PARITY_ERR_INT_RAW.
	LP_UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4
	// Position of FRM_ERR_INT_RAW field.
	LP_UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3
	// Bit mask of FRM_ERR_INT_RAW field.
	LP_UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8
	// Bit FRM_ERR_INT_RAW.
	LP_UART_INT_RAW_FRM_ERR_INT_RAW = 0x8
	// Position of RXFIFO_OVF_INT_RAW field.
	LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_RAW field.
	LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10
	// Bit RXFIFO_OVF_INT_RAW.
	LP_UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10
	// Position of DSR_CHG_INT_RAW field.
	LP_UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5
	// Bit mask of DSR_CHG_INT_RAW field.
	LP_UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20
	// Bit DSR_CHG_INT_RAW.
	LP_UART_INT_RAW_DSR_CHG_INT_RAW = 0x20
	// Position of CTS_CHG_INT_RAW field.
	LP_UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6
	// Bit mask of CTS_CHG_INT_RAW field.
	LP_UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40
	// Bit CTS_CHG_INT_RAW.
	LP_UART_INT_RAW_CTS_CHG_INT_RAW = 0x40
	// Position of BRK_DET_INT_RAW field.
	LP_UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7
	// Bit mask of BRK_DET_INT_RAW field.
	LP_UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80
	// Bit BRK_DET_INT_RAW.
	LP_UART_INT_RAW_BRK_DET_INT_RAW = 0x80
	// Position of RXFIFO_TOUT_INT_RAW field.
	LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_RAW field.
	LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_RAW.
	LP_UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100
	// Position of SW_XON_INT_RAW field.
	LP_UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9
	// Bit mask of SW_XON_INT_RAW field.
	LP_UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200
	// Bit SW_XON_INT_RAW.
	LP_UART_INT_RAW_SW_XON_INT_RAW = 0x200
	// Position of SW_XOFF_INT_RAW field.
	LP_UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa
	// Bit mask of SW_XOFF_INT_RAW field.
	LP_UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400
	// Bit SW_XOFF_INT_RAW.
	LP_UART_INT_RAW_SW_XOFF_INT_RAW = 0x400
	// Position of GLITCH_DET_INT_RAW field.
	LP_UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_RAW field.
	LP_UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800
	// Bit GLITCH_DET_INT_RAW.
	LP_UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800
	// Position of TX_BRK_DONE_INT_RAW field.
	LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_RAW field.
	LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_RAW.
	LP_UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_RAW field.
	LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_RAW field.
	LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_RAW.
	LP_UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000
	// Position of TX_DONE_INT_RAW field.
	LP_UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe
	// Bit mask of TX_DONE_INT_RAW field.
	LP_UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000
	// Bit TX_DONE_INT_RAW.
	LP_UART_INT_RAW_TX_DONE_INT_RAW = 0x4000
	// Position of AT_CMD_CHAR_DET_INT_RAW field.
	LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_RAW field.
	LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_RAW.
	LP_UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000
	// Position of WAKEUP_INT_RAW field.
	LP_UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13
	// Bit mask of WAKEUP_INT_RAW field.
	LP_UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000
	// Bit WAKEUP_INT_RAW.
	LP_UART_INT_RAW_WAKEUP_INT_RAW = 0x80000

	// INT_ST: Masked interrupt status
	// Position of RXFIFO_FULL_INT_ST field.
	LP_UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_ST field.
	LP_UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1
	// Bit RXFIFO_FULL_INT_ST.
	LP_UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1
	// Position of TXFIFO_EMPTY_INT_ST field.
	LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_ST field.
	LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_ST.
	LP_UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2
	// Position of PARITY_ERR_INT_ST field.
	LP_UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_ST field.
	LP_UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4
	// Bit PARITY_ERR_INT_ST.
	LP_UART_INT_ST_PARITY_ERR_INT_ST = 0x4
	// Position of FRM_ERR_INT_ST field.
	LP_UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3
	// Bit mask of FRM_ERR_INT_ST field.
	LP_UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8
	// Bit FRM_ERR_INT_ST.
	LP_UART_INT_ST_FRM_ERR_INT_ST = 0x8
	// Position of RXFIFO_OVF_INT_ST field.
	LP_UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_ST field.
	LP_UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10
	// Bit RXFIFO_OVF_INT_ST.
	LP_UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10
	// Position of DSR_CHG_INT_ST field.
	LP_UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5
	// Bit mask of DSR_CHG_INT_ST field.
	LP_UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20
	// Bit DSR_CHG_INT_ST.
	LP_UART_INT_ST_DSR_CHG_INT_ST = 0x20
	// Position of CTS_CHG_INT_ST field.
	LP_UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6
	// Bit mask of CTS_CHG_INT_ST field.
	LP_UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40
	// Bit CTS_CHG_INT_ST.
	LP_UART_INT_ST_CTS_CHG_INT_ST = 0x40
	// Position of BRK_DET_INT_ST field.
	LP_UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7
	// Bit mask of BRK_DET_INT_ST field.
	LP_UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80
	// Bit BRK_DET_INT_ST.
	LP_UART_INT_ST_BRK_DET_INT_ST = 0x80
	// Position of RXFIFO_TOUT_INT_ST field.
	LP_UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_ST field.
	LP_UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_ST.
	LP_UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100
	// Position of SW_XON_INT_ST field.
	LP_UART_INT_ST_SW_XON_INT_ST_Pos = 0x9
	// Bit mask of SW_XON_INT_ST field.
	LP_UART_INT_ST_SW_XON_INT_ST_Msk = 0x200
	// Bit SW_XON_INT_ST.
	LP_UART_INT_ST_SW_XON_INT_ST = 0x200
	// Position of SW_XOFF_INT_ST field.
	LP_UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa
	// Bit mask of SW_XOFF_INT_ST field.
	LP_UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400
	// Bit SW_XOFF_INT_ST.
	LP_UART_INT_ST_SW_XOFF_INT_ST = 0x400
	// Position of GLITCH_DET_INT_ST field.
	LP_UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_ST field.
	LP_UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800
	// Bit GLITCH_DET_INT_ST.
	LP_UART_INT_ST_GLITCH_DET_INT_ST = 0x800
	// Position of TX_BRK_DONE_INT_ST field.
	LP_UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_ST field.
	LP_UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_ST.
	LP_UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_ST field.
	LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_ST field.
	LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_ST.
	LP_UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000
	// Position of TX_DONE_INT_ST field.
	LP_UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe
	// Bit mask of TX_DONE_INT_ST field.
	LP_UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000
	// Bit TX_DONE_INT_ST.
	LP_UART_INT_ST_TX_DONE_INT_ST = 0x4000
	// Position of AT_CMD_CHAR_DET_INT_ST field.
	LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_ST field.
	LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_ST.
	LP_UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000
	// Position of WAKEUP_INT_ST field.
	LP_UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13
	// Bit mask of WAKEUP_INT_ST field.
	LP_UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000
	// Bit WAKEUP_INT_ST.
	LP_UART_INT_ST_WAKEUP_INT_ST = 0x80000

	// INT_ENA: Interrupt enable bits
	// Position of RXFIFO_FULL_INT_ENA field.
	LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_ENA field.
	LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1
	// Bit RXFIFO_FULL_INT_ENA.
	LP_UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1
	// Position of TXFIFO_EMPTY_INT_ENA field.
	LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_ENA field.
	LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_ENA.
	LP_UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2
	// Position of PARITY_ERR_INT_ENA field.
	LP_UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_ENA field.
	LP_UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4
	// Bit PARITY_ERR_INT_ENA.
	LP_UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4
	// Position of FRM_ERR_INT_ENA field.
	LP_UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3
	// Bit mask of FRM_ERR_INT_ENA field.
	LP_UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8
	// Bit FRM_ERR_INT_ENA.
	LP_UART_INT_ENA_FRM_ERR_INT_ENA = 0x8
	// Position of RXFIFO_OVF_INT_ENA field.
	LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_ENA field.
	LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10
	// Bit RXFIFO_OVF_INT_ENA.
	LP_UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10
	// Position of DSR_CHG_INT_ENA field.
	LP_UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5
	// Bit mask of DSR_CHG_INT_ENA field.
	LP_UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20
	// Bit DSR_CHG_INT_ENA.
	LP_UART_INT_ENA_DSR_CHG_INT_ENA = 0x20
	// Position of CTS_CHG_INT_ENA field.
	LP_UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6
	// Bit mask of CTS_CHG_INT_ENA field.
	LP_UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40
	// Bit CTS_CHG_INT_ENA.
	LP_UART_INT_ENA_CTS_CHG_INT_ENA = 0x40
	// Position of BRK_DET_INT_ENA field.
	LP_UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7
	// Bit mask of BRK_DET_INT_ENA field.
	LP_UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80
	// Bit BRK_DET_INT_ENA.
	LP_UART_INT_ENA_BRK_DET_INT_ENA = 0x80
	// Position of RXFIFO_TOUT_INT_ENA field.
	LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_ENA field.
	LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_ENA.
	LP_UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100
	// Position of SW_XON_INT_ENA field.
	LP_UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9
	// Bit mask of SW_XON_INT_ENA field.
	LP_UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200
	// Bit SW_XON_INT_ENA.
	LP_UART_INT_ENA_SW_XON_INT_ENA = 0x200
	// Position of SW_XOFF_INT_ENA field.
	LP_UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa
	// Bit mask of SW_XOFF_INT_ENA field.
	LP_UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400
	// Bit SW_XOFF_INT_ENA.
	LP_UART_INT_ENA_SW_XOFF_INT_ENA = 0x400
	// Position of GLITCH_DET_INT_ENA field.
	LP_UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_ENA field.
	LP_UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800
	// Bit GLITCH_DET_INT_ENA.
	LP_UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800
	// Position of TX_BRK_DONE_INT_ENA field.
	LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_ENA field.
	LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_ENA.
	LP_UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_ENA field.
	LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_ENA field.
	LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_ENA.
	LP_UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000
	// Position of TX_DONE_INT_ENA field.
	LP_UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe
	// Bit mask of TX_DONE_INT_ENA field.
	LP_UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000
	// Bit TX_DONE_INT_ENA.
	LP_UART_INT_ENA_TX_DONE_INT_ENA = 0x4000
	// Position of AT_CMD_CHAR_DET_INT_ENA field.
	LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_ENA field.
	LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_ENA.
	LP_UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000
	// Position of WAKEUP_INT_ENA field.
	LP_UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13
	// Bit mask of WAKEUP_INT_ENA field.
	LP_UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000
	// Bit WAKEUP_INT_ENA.
	LP_UART_INT_ENA_WAKEUP_INT_ENA = 0x80000

	// INT_CLR: Interrupt clear bits
	// Position of RXFIFO_FULL_INT_CLR field.
	LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_CLR field.
	LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1
	// Bit RXFIFO_FULL_INT_CLR.
	LP_UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1
	// Position of TXFIFO_EMPTY_INT_CLR field.
	LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_CLR field.
	LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_CLR.
	LP_UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2
	// Position of PARITY_ERR_INT_CLR field.
	LP_UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_CLR field.
	LP_UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4
	// Bit PARITY_ERR_INT_CLR.
	LP_UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4
	// Position of FRM_ERR_INT_CLR field.
	LP_UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3
	// Bit mask of FRM_ERR_INT_CLR field.
	LP_UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8
	// Bit FRM_ERR_INT_CLR.
	LP_UART_INT_CLR_FRM_ERR_INT_CLR = 0x8
	// Position of RXFIFO_OVF_INT_CLR field.
	LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_CLR field.
	LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10
	// Bit RXFIFO_OVF_INT_CLR.
	LP_UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10
	// Position of DSR_CHG_INT_CLR field.
	LP_UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5
	// Bit mask of DSR_CHG_INT_CLR field.
	LP_UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20
	// Bit DSR_CHG_INT_CLR.
	LP_UART_INT_CLR_DSR_CHG_INT_CLR = 0x20
	// Position of CTS_CHG_INT_CLR field.
	LP_UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6
	// Bit mask of CTS_CHG_INT_CLR field.
	LP_UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40
	// Bit CTS_CHG_INT_CLR.
	LP_UART_INT_CLR_CTS_CHG_INT_CLR = 0x40
	// Position of BRK_DET_INT_CLR field.
	LP_UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7
	// Bit mask of BRK_DET_INT_CLR field.
	LP_UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80
	// Bit BRK_DET_INT_CLR.
	LP_UART_INT_CLR_BRK_DET_INT_CLR = 0x80
	// Position of RXFIFO_TOUT_INT_CLR field.
	LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_CLR field.
	LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_CLR.
	LP_UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100
	// Position of SW_XON_INT_CLR field.
	LP_UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9
	// Bit mask of SW_XON_INT_CLR field.
	LP_UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200
	// Bit SW_XON_INT_CLR.
	LP_UART_INT_CLR_SW_XON_INT_CLR = 0x200
	// Position of SW_XOFF_INT_CLR field.
	LP_UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa
	// Bit mask of SW_XOFF_INT_CLR field.
	LP_UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400
	// Bit SW_XOFF_INT_CLR.
	LP_UART_INT_CLR_SW_XOFF_INT_CLR = 0x400
	// Position of GLITCH_DET_INT_CLR field.
	LP_UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_CLR field.
	LP_UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800
	// Bit GLITCH_DET_INT_CLR.
	LP_UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800
	// Position of TX_BRK_DONE_INT_CLR field.
	LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_CLR field.
	LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_CLR.
	LP_UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_CLR field.
	LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_CLR field.
	LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_CLR.
	LP_UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000
	// Position of TX_DONE_INT_CLR field.
	LP_UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe
	// Bit mask of TX_DONE_INT_CLR field.
	LP_UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000
	// Bit TX_DONE_INT_CLR.
	LP_UART_INT_CLR_TX_DONE_INT_CLR = 0x4000
	// Position of AT_CMD_CHAR_DET_INT_CLR field.
	LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_CLR field.
	LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_CLR.
	LP_UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000
	// Position of WAKEUP_INT_CLR field.
	LP_UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13
	// Bit mask of WAKEUP_INT_CLR field.
	LP_UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000
	// Bit WAKEUP_INT_CLR.
	LP_UART_INT_CLR_WAKEUP_INT_CLR = 0x80000

	// CLKDIV_SYNC: Clock divider configuration
	// Position of CLKDIV field.
	LP_UART_CLKDIV_SYNC_CLKDIV_Pos = 0x0
	// Bit mask of CLKDIV field.
	LP_UART_CLKDIV_SYNC_CLKDIV_Msk = 0xfff
	// Position of CLKDIV_FRAG field.
	LP_UART_CLKDIV_SYNC_CLKDIV_FRAG_Pos = 0x14
	// Bit mask of CLKDIV_FRAG field.
	LP_UART_CLKDIV_SYNC_CLKDIV_FRAG_Msk = 0xf00000

	// RX_FILT: Rx Filter configuration
	// Position of GLITCH_FILT field.
	LP_UART_RX_FILT_GLITCH_FILT_Pos = 0x0
	// Bit mask of GLITCH_FILT field.
	LP_UART_RX_FILT_GLITCH_FILT_Msk = 0xff
	// Position of GLITCH_FILT_EN field.
	LP_UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8
	// Bit mask of GLITCH_FILT_EN field.
	LP_UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100
	// Bit GLITCH_FILT_EN.
	LP_UART_RX_FILT_GLITCH_FILT_EN = 0x100

	// STATUS: UART status register
	// Position of RXFIFO_CNT field.
	LP_UART_STATUS_RXFIFO_CNT_Pos = 0x3
	// Bit mask of RXFIFO_CNT field.
	LP_UART_STATUS_RXFIFO_CNT_Msk = 0xf8
	// Position of DSRN field.
	LP_UART_STATUS_DSRN_Pos = 0xd
	// Bit mask of DSRN field.
	LP_UART_STATUS_DSRN_Msk = 0x2000
	// Bit DSRN.
	LP_UART_STATUS_DSRN = 0x2000
	// Position of CTSN field.
	LP_UART_STATUS_CTSN_Pos = 0xe
	// Bit mask of CTSN field.
	LP_UART_STATUS_CTSN_Msk = 0x4000
	// Bit CTSN.
	LP_UART_STATUS_CTSN = 0x4000
	// Position of RXD field.
	LP_UART_STATUS_RXD_Pos = 0xf
	// Bit mask of RXD field.
	LP_UART_STATUS_RXD_Msk = 0x8000
	// Bit RXD.
	LP_UART_STATUS_RXD = 0x8000
	// Position of TXFIFO_CNT field.
	LP_UART_STATUS_TXFIFO_CNT_Pos = 0x13
	// Bit mask of TXFIFO_CNT field.
	LP_UART_STATUS_TXFIFO_CNT_Msk = 0xf80000
	// Position of DTRN field.
	LP_UART_STATUS_DTRN_Pos = 0x1d
	// Bit mask of DTRN field.
	LP_UART_STATUS_DTRN_Msk = 0x20000000
	// Bit DTRN.
	LP_UART_STATUS_DTRN = 0x20000000
	// Position of RTSN field.
	LP_UART_STATUS_RTSN_Pos = 0x1e
	// Bit mask of RTSN field.
	LP_UART_STATUS_RTSN_Msk = 0x40000000
	// Bit RTSN.
	LP_UART_STATUS_RTSN = 0x40000000
	// Position of TXD field.
	LP_UART_STATUS_TXD_Pos = 0x1f
	// Bit mask of TXD field.
	LP_UART_STATUS_TXD_Msk = 0x80000000
	// Bit TXD.
	LP_UART_STATUS_TXD = 0x80000000

	// CONF0_SYNC: Configuration register 0
	// Position of PARITY field.
	LP_UART_CONF0_SYNC_PARITY_Pos = 0x0
	// Bit mask of PARITY field.
	LP_UART_CONF0_SYNC_PARITY_Msk = 0x1
	// Bit PARITY.
	LP_UART_CONF0_SYNC_PARITY = 0x1
	// Position of PARITY_EN field.
	LP_UART_CONF0_SYNC_PARITY_EN_Pos = 0x1
	// Bit mask of PARITY_EN field.
	LP_UART_CONF0_SYNC_PARITY_EN_Msk = 0x2
	// Bit PARITY_EN.
	LP_UART_CONF0_SYNC_PARITY_EN = 0x2
	// Position of BIT_NUM field.
	LP_UART_CONF0_SYNC_BIT_NUM_Pos = 0x2
	// Bit mask of BIT_NUM field.
	LP_UART_CONF0_SYNC_BIT_NUM_Msk = 0xc
	// Position of STOP_BIT_NUM field.
	LP_UART_CONF0_SYNC_STOP_BIT_NUM_Pos = 0x4
	// Bit mask of STOP_BIT_NUM field.
	LP_UART_CONF0_SYNC_STOP_BIT_NUM_Msk = 0x30
	// Position of TXD_BRK field.
	LP_UART_CONF0_SYNC_TXD_BRK_Pos = 0x6
	// Bit mask of TXD_BRK field.
	LP_UART_CONF0_SYNC_TXD_BRK_Msk = 0x40
	// Bit TXD_BRK.
	LP_UART_CONF0_SYNC_TXD_BRK = 0x40
	// Position of LOOPBACK field.
	LP_UART_CONF0_SYNC_LOOPBACK_Pos = 0xc
	// Bit mask of LOOPBACK field.
	LP_UART_CONF0_SYNC_LOOPBACK_Msk = 0x1000
	// Bit LOOPBACK.
	LP_UART_CONF0_SYNC_LOOPBACK = 0x1000
	// Position of TX_FLOW_EN field.
	LP_UART_CONF0_SYNC_TX_FLOW_EN_Pos = 0xd
	// Bit mask of TX_FLOW_EN field.
	LP_UART_CONF0_SYNC_TX_FLOW_EN_Msk = 0x2000
	// Bit TX_FLOW_EN.
	LP_UART_CONF0_SYNC_TX_FLOW_EN = 0x2000
	// Position of RXD_INV field.
	LP_UART_CONF0_SYNC_RXD_INV_Pos = 0xf
	// Bit mask of RXD_INV field.
	LP_UART_CONF0_SYNC_RXD_INV_Msk = 0x8000
	// Bit RXD_INV.
	LP_UART_CONF0_SYNC_RXD_INV = 0x8000
	// Position of TXD_INV field.
	LP_UART_CONF0_SYNC_TXD_INV_Pos = 0x10
	// Bit mask of TXD_INV field.
	LP_UART_CONF0_SYNC_TXD_INV_Msk = 0x10000
	// Bit TXD_INV.
	LP_UART_CONF0_SYNC_TXD_INV = 0x10000
	// Position of DIS_RX_DAT_OVF field.
	LP_UART_CONF0_SYNC_DIS_RX_DAT_OVF_Pos = 0x11
	// Bit mask of DIS_RX_DAT_OVF field.
	LP_UART_CONF0_SYNC_DIS_RX_DAT_OVF_Msk = 0x20000
	// Bit DIS_RX_DAT_OVF.
	LP_UART_CONF0_SYNC_DIS_RX_DAT_OVF = 0x20000
	// Position of ERR_WR_MASK field.
	LP_UART_CONF0_SYNC_ERR_WR_MASK_Pos = 0x12
	// Bit mask of ERR_WR_MASK field.
	LP_UART_CONF0_SYNC_ERR_WR_MASK_Msk = 0x40000
	// Bit ERR_WR_MASK.
	LP_UART_CONF0_SYNC_ERR_WR_MASK = 0x40000
	// Position of MEM_CLK_EN field.
	LP_UART_CONF0_SYNC_MEM_CLK_EN_Pos = 0x14
	// Bit mask of MEM_CLK_EN field.
	LP_UART_CONF0_SYNC_MEM_CLK_EN_Msk = 0x100000
	// Bit MEM_CLK_EN.
	LP_UART_CONF0_SYNC_MEM_CLK_EN = 0x100000
	// Position of SW_RTS field.
	LP_UART_CONF0_SYNC_SW_RTS_Pos = 0x15
	// Bit mask of SW_RTS field.
	LP_UART_CONF0_SYNC_SW_RTS_Msk = 0x200000
	// Bit SW_RTS.
	LP_UART_CONF0_SYNC_SW_RTS = 0x200000
	// Position of RXFIFO_RST field.
	LP_UART_CONF0_SYNC_RXFIFO_RST_Pos = 0x16
	// Bit mask of RXFIFO_RST field.
	LP_UART_CONF0_SYNC_RXFIFO_RST_Msk = 0x400000
	// Bit RXFIFO_RST.
	LP_UART_CONF0_SYNC_RXFIFO_RST = 0x400000
	// Position of TXFIFO_RST field.
	LP_UART_CONF0_SYNC_TXFIFO_RST_Pos = 0x17
	// Bit mask of TXFIFO_RST field.
	LP_UART_CONF0_SYNC_TXFIFO_RST_Msk = 0x800000
	// Bit TXFIFO_RST.
	LP_UART_CONF0_SYNC_TXFIFO_RST = 0x800000

	// CONF1: Configuration register 1
	// Position of RXFIFO_FULL_THRHD field.
	LP_UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x3
	// Bit mask of RXFIFO_FULL_THRHD field.
	LP_UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0xf8
	// Position of TXFIFO_EMPTY_THRHD field.
	LP_UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0xb
	// Bit mask of TXFIFO_EMPTY_THRHD field.
	LP_UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0xf800
	// Position of CTS_INV field.
	LP_UART_CONF1_CTS_INV_Pos = 0x10
	// Bit mask of CTS_INV field.
	LP_UART_CONF1_CTS_INV_Msk = 0x10000
	// Bit CTS_INV.
	LP_UART_CONF1_CTS_INV = 0x10000
	// Position of DSR_INV field.
	LP_UART_CONF1_DSR_INV_Pos = 0x11
	// Bit mask of DSR_INV field.
	LP_UART_CONF1_DSR_INV_Msk = 0x20000
	// Bit DSR_INV.
	LP_UART_CONF1_DSR_INV = 0x20000
	// Position of RTS_INV field.
	LP_UART_CONF1_RTS_INV_Pos = 0x12
	// Bit mask of RTS_INV field.
	LP_UART_CONF1_RTS_INV_Msk = 0x40000
	// Bit RTS_INV.
	LP_UART_CONF1_RTS_INV = 0x40000
	// Position of DTR_INV field.
	LP_UART_CONF1_DTR_INV_Pos = 0x13
	// Bit mask of DTR_INV field.
	LP_UART_CONF1_DTR_INV_Msk = 0x80000
	// Bit DTR_INV.
	LP_UART_CONF1_DTR_INV = 0x80000
	// Position of SW_DTR field.
	LP_UART_CONF1_SW_DTR_Pos = 0x14
	// Bit mask of SW_DTR field.
	LP_UART_CONF1_SW_DTR_Msk = 0x100000
	// Bit SW_DTR.
	LP_UART_CONF1_SW_DTR = 0x100000
	// Position of CLK_EN field.
	LP_UART_CONF1_CLK_EN_Pos = 0x15
	// Bit mask of CLK_EN field.
	LP_UART_CONF1_CLK_EN_Msk = 0x200000
	// Bit CLK_EN.
	LP_UART_CONF1_CLK_EN = 0x200000

	// HWFC_CONF_SYNC: Hardware flow-control configuration
	// Position of RX_FLOW_THRHD field.
	LP_UART_HWFC_CONF_SYNC_RX_FLOW_THRHD_Pos = 0x3
	// Bit mask of RX_FLOW_THRHD field.
	LP_UART_HWFC_CONF_SYNC_RX_FLOW_THRHD_Msk = 0xf8
	// Position of RX_FLOW_EN field.
	LP_UART_HWFC_CONF_SYNC_RX_FLOW_EN_Pos = 0x8
	// Bit mask of RX_FLOW_EN field.
	LP_UART_HWFC_CONF_SYNC_RX_FLOW_EN_Msk = 0x100
	// Bit RX_FLOW_EN.
	LP_UART_HWFC_CONF_SYNC_RX_FLOW_EN = 0x100

	// SLEEP_CONF0: UART sleep configure register 0
	// Position of WK_CHAR1 field.
	LP_UART_SLEEP_CONF0_WK_CHAR1_Pos = 0x0
	// Bit mask of WK_CHAR1 field.
	LP_UART_SLEEP_CONF0_WK_CHAR1_Msk = 0xff
	// Position of WK_CHAR2 field.
	LP_UART_SLEEP_CONF0_WK_CHAR2_Pos = 0x8
	// Bit mask of WK_CHAR2 field.
	LP_UART_SLEEP_CONF0_WK_CHAR2_Msk = 0xff00
	// Position of WK_CHAR3 field.
	LP_UART_SLEEP_CONF0_WK_CHAR3_Pos = 0x10
	// Bit mask of WK_CHAR3 field.
	LP_UART_SLEEP_CONF0_WK_CHAR3_Msk = 0xff0000
	// Position of WK_CHAR4 field.
	LP_UART_SLEEP_CONF0_WK_CHAR4_Pos = 0x18
	// Bit mask of WK_CHAR4 field.
	LP_UART_SLEEP_CONF0_WK_CHAR4_Msk = 0xff000000

	// SLEEP_CONF1: UART sleep configure register 1
	// Position of WK_CHAR0 field.
	LP_UART_SLEEP_CONF1_WK_CHAR0_Pos = 0x0
	// Bit mask of WK_CHAR0 field.
	LP_UART_SLEEP_CONF1_WK_CHAR0_Msk = 0xff

	// SLEEP_CONF2: UART sleep configure register 2
	// Position of ACTIVE_THRESHOLD field.
	LP_UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Pos = 0x0
	// Bit mask of ACTIVE_THRESHOLD field.
	LP_UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Msk = 0x3ff
	// Position of RX_WAKE_UP_THRHD field.
	LP_UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Pos = 0xd
	// Bit mask of RX_WAKE_UP_THRHD field.
	LP_UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Msk = 0x3e000
	// Position of WK_CHAR_NUM field.
	LP_UART_SLEEP_CONF2_WK_CHAR_NUM_Pos = 0x12
	// Bit mask of WK_CHAR_NUM field.
	LP_UART_SLEEP_CONF2_WK_CHAR_NUM_Msk = 0x1c0000
	// Position of WK_CHAR_MASK field.
	LP_UART_SLEEP_CONF2_WK_CHAR_MASK_Pos = 0x15
	// Bit mask of WK_CHAR_MASK field.
	LP_UART_SLEEP_CONF2_WK_CHAR_MASK_Msk = 0x3e00000
	// Position of WK_MODE_SEL field.
	LP_UART_SLEEP_CONF2_WK_MODE_SEL_Pos = 0x1a
	// Bit mask of WK_MODE_SEL field.
	LP_UART_SLEEP_CONF2_WK_MODE_SEL_Msk = 0xc000000

	// SWFC_CONF0_SYNC: Software flow-control character configuration
	// Position of XON_CHAR field.
	LP_UART_SWFC_CONF0_SYNC_XON_CHAR_Pos = 0x0
	// Bit mask of XON_CHAR field.
	LP_UART_SWFC_CONF0_SYNC_XON_CHAR_Msk = 0xff
	// Position of XOFF_CHAR field.
	LP_UART_SWFC_CONF0_SYNC_XOFF_CHAR_Pos = 0x8
	// Bit mask of XOFF_CHAR field.
	LP_UART_SWFC_CONF0_SYNC_XOFF_CHAR_Msk = 0xff00
	// Position of XON_XOFF_STILL_SEND field.
	LP_UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND_Pos = 0x10
	// Bit mask of XON_XOFF_STILL_SEND field.
	LP_UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND_Msk = 0x10000
	// Bit XON_XOFF_STILL_SEND.
	LP_UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND = 0x10000
	// Position of SW_FLOW_CON_EN field.
	LP_UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN_Pos = 0x11
	// Bit mask of SW_FLOW_CON_EN field.
	LP_UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN_Msk = 0x20000
	// Bit SW_FLOW_CON_EN.
	LP_UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN = 0x20000
	// Position of XONOFF_DEL field.
	LP_UART_SWFC_CONF0_SYNC_XONOFF_DEL_Pos = 0x12
	// Bit mask of XONOFF_DEL field.
	LP_UART_SWFC_CONF0_SYNC_XONOFF_DEL_Msk = 0x40000
	// Bit XONOFF_DEL.
	LP_UART_SWFC_CONF0_SYNC_XONOFF_DEL = 0x40000
	// Position of FORCE_XON field.
	LP_UART_SWFC_CONF0_SYNC_FORCE_XON_Pos = 0x13
	// Bit mask of FORCE_XON field.
	LP_UART_SWFC_CONF0_SYNC_FORCE_XON_Msk = 0x80000
	// Bit FORCE_XON.
	LP_UART_SWFC_CONF0_SYNC_FORCE_XON = 0x80000
	// Position of FORCE_XOFF field.
	LP_UART_SWFC_CONF0_SYNC_FORCE_XOFF_Pos = 0x14
	// Bit mask of FORCE_XOFF field.
	LP_UART_SWFC_CONF0_SYNC_FORCE_XOFF_Msk = 0x100000
	// Bit FORCE_XOFF.
	LP_UART_SWFC_CONF0_SYNC_FORCE_XOFF = 0x100000
	// Position of SEND_XON field.
	LP_UART_SWFC_CONF0_SYNC_SEND_XON_Pos = 0x15
	// Bit mask of SEND_XON field.
	LP_UART_SWFC_CONF0_SYNC_SEND_XON_Msk = 0x200000
	// Bit SEND_XON.
	LP_UART_SWFC_CONF0_SYNC_SEND_XON = 0x200000
	// Position of SEND_XOFF field.
	LP_UART_SWFC_CONF0_SYNC_SEND_XOFF_Pos = 0x16
	// Bit mask of SEND_XOFF field.
	LP_UART_SWFC_CONF0_SYNC_SEND_XOFF_Msk = 0x400000
	// Bit SEND_XOFF.
	LP_UART_SWFC_CONF0_SYNC_SEND_XOFF = 0x400000

	// SWFC_CONF1: Software flow-control character configuration
	// Position of XON_THRESHOLD field.
	LP_UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x3
	// Bit mask of XON_THRESHOLD field.
	LP_UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0xf8
	// Position of XOFF_THRESHOLD field.
	LP_UART_SWFC_CONF1_XOFF_THRESHOLD_Pos = 0xb
	// Bit mask of XOFF_THRESHOLD field.
	LP_UART_SWFC_CONF1_XOFF_THRESHOLD_Msk = 0xf800

	// TXBRK_CONF_SYNC: Tx Break character configuration
	// Position of TX_BRK_NUM field.
	LP_UART_TXBRK_CONF_SYNC_TX_BRK_NUM_Pos = 0x0
	// Bit mask of TX_BRK_NUM field.
	LP_UART_TXBRK_CONF_SYNC_TX_BRK_NUM_Msk = 0xff

	// IDLE_CONF_SYNC: Frame-end idle configuration
	// Position of RX_IDLE_THRHD field.
	LP_UART_IDLE_CONF_SYNC_RX_IDLE_THRHD_Pos = 0x0
	// Bit mask of RX_IDLE_THRHD field.
	LP_UART_IDLE_CONF_SYNC_RX_IDLE_THRHD_Msk = 0x3ff
	// Position of TX_IDLE_NUM field.
	LP_UART_IDLE_CONF_SYNC_TX_IDLE_NUM_Pos = 0xa
	// Bit mask of TX_IDLE_NUM field.
	LP_UART_IDLE_CONF_SYNC_TX_IDLE_NUM_Msk = 0xffc00

	// RS485_CONF_SYNC: RS485 mode configuration
	// Position of DL0_EN field.
	LP_UART_RS485_CONF_SYNC_DL0_EN_Pos = 0x1
	// Bit mask of DL0_EN field.
	LP_UART_RS485_CONF_SYNC_DL0_EN_Msk = 0x2
	// Bit DL0_EN.
	LP_UART_RS485_CONF_SYNC_DL0_EN = 0x2
	// Position of DL1_EN field.
	LP_UART_RS485_CONF_SYNC_DL1_EN_Pos = 0x2
	// Bit mask of DL1_EN field.
	LP_UART_RS485_CONF_SYNC_DL1_EN_Msk = 0x4
	// Bit DL1_EN.
	LP_UART_RS485_CONF_SYNC_DL1_EN = 0x4

	// AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration
	// Position of PRE_IDLE_NUM field.
	LP_UART_AT_CMD_PRECNT_SYNC_PRE_IDLE_NUM_Pos = 0x0
	// Bit mask of PRE_IDLE_NUM field.
	LP_UART_AT_CMD_PRECNT_SYNC_PRE_IDLE_NUM_Msk = 0xffff

	// AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration
	// Position of POST_IDLE_NUM field.
	LP_UART_AT_CMD_POSTCNT_SYNC_POST_IDLE_NUM_Pos = 0x0
	// Bit mask of POST_IDLE_NUM field.
	LP_UART_AT_CMD_POSTCNT_SYNC_POST_IDLE_NUM_Msk = 0xffff

	// AT_CMD_GAPTOUT_SYNC: Timeout configuration
	// Position of RX_GAP_TOUT field.
	LP_UART_AT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT_Pos = 0x0
	// Bit mask of RX_GAP_TOUT field.
	LP_UART_AT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT_Msk = 0xffff

	// AT_CMD_CHAR_SYNC: AT escape sequence detection configuration
	// Position of AT_CMD_CHAR field.
	LP_UART_AT_CMD_CHAR_SYNC_AT_CMD_CHAR_Pos = 0x0
	// Bit mask of AT_CMD_CHAR field.
	LP_UART_AT_CMD_CHAR_SYNC_AT_CMD_CHAR_Msk = 0xff
	// Position of CHAR_NUM field.
	LP_UART_AT_CMD_CHAR_SYNC_CHAR_NUM_Pos = 0x8
	// Bit mask of CHAR_NUM field.
	LP_UART_AT_CMD_CHAR_SYNC_CHAR_NUM_Msk = 0xff00

	// MEM_CONF: UART memory power configuration
	// Position of MEM_FORCE_PD field.
	LP_UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x19
	// Bit mask of MEM_FORCE_PD field.
	LP_UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x2000000
	// Bit MEM_FORCE_PD.
	LP_UART_MEM_CONF_MEM_FORCE_PD = 0x2000000
	// Position of MEM_FORCE_PU field.
	LP_UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1a
	// Bit mask of MEM_FORCE_PU field.
	LP_UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x4000000
	// Bit MEM_FORCE_PU.
	LP_UART_MEM_CONF_MEM_FORCE_PU = 0x4000000

	// TOUT_CONF_SYNC: UART threshold and allocation configuration
	// Position of RX_TOUT_EN field.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_EN_Pos = 0x0
	// Bit mask of RX_TOUT_EN field.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_EN_Msk = 0x1
	// Bit RX_TOUT_EN.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_EN = 0x1
	// Position of RX_TOUT_FLOW_DIS field.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS_Pos = 0x1
	// Bit mask of RX_TOUT_FLOW_DIS field.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS_Msk = 0x2
	// Bit RX_TOUT_FLOW_DIS.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS = 0x2
	// Position of RX_TOUT_THRHD field.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_THRHD_Pos = 0x2
	// Bit mask of RX_TOUT_THRHD field.
	LP_UART_TOUT_CONF_SYNC_RX_TOUT_THRHD_Msk = 0xffc

	// MEM_TX_STATUS: Tx-SRAM write and read offset address.
	// Position of TX_SRAM_WADDR field.
	LP_UART_MEM_TX_STATUS_TX_SRAM_WADDR_Pos = 0x3
	// Bit mask of TX_SRAM_WADDR field.
	LP_UART_MEM_TX_STATUS_TX_SRAM_WADDR_Msk = 0xf8
	// Position of TX_SRAM_RADDR field.
	LP_UART_MEM_TX_STATUS_TX_SRAM_RADDR_Pos = 0xc
	// Bit mask of TX_SRAM_RADDR field.
	LP_UART_MEM_TX_STATUS_TX_SRAM_RADDR_Msk = 0x1f000

	// MEM_RX_STATUS: Rx-SRAM write and read offset address.
	// Position of RX_SRAM_RADDR field.
	LP_UART_MEM_RX_STATUS_RX_SRAM_RADDR_Pos = 0x3
	// Bit mask of RX_SRAM_RADDR field.
	LP_UART_MEM_RX_STATUS_RX_SRAM_RADDR_Msk = 0xf8
	// Position of RX_SRAM_WADDR field.
	LP_UART_MEM_RX_STATUS_RX_SRAM_WADDR_Pos = 0xc
	// Bit mask of RX_SRAM_WADDR field.
	LP_UART_MEM_RX_STATUS_RX_SRAM_WADDR_Msk = 0x1f000

	// FSM_STATUS: UART transmit and receive status.
	// Position of ST_URX_OUT field.
	LP_UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0
	// Bit mask of ST_URX_OUT field.
	LP_UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf
	// Position of ST_UTX_OUT field.
	LP_UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4
	// Bit mask of ST_UTX_OUT field.
	LP_UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0

	// CLK_CONF: UART core clock configuration
	// Position of TX_SCLK_EN field.
	LP_UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18
	// Bit mask of TX_SCLK_EN field.
	LP_UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000
	// Bit TX_SCLK_EN.
	LP_UART_CLK_CONF_TX_SCLK_EN = 0x1000000
	// Position of RX_SCLK_EN field.
	LP_UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19
	// Bit mask of RX_SCLK_EN field.
	LP_UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000
	// Bit RX_SCLK_EN.
	LP_UART_CLK_CONF_RX_SCLK_EN = 0x2000000
	// Position of TX_RST_CORE field.
	LP_UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a
	// Bit mask of TX_RST_CORE field.
	LP_UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000
	// Bit TX_RST_CORE.
	LP_UART_CLK_CONF_TX_RST_CORE = 0x4000000
	// Position of RX_RST_CORE field.
	LP_UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b
	// Bit mask of RX_RST_CORE field.
	LP_UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000
	// Bit RX_RST_CORE.
	LP_UART_CLK_CONF_RX_RST_CORE = 0x8000000

	// DATE: UART Version register
	// Position of DATE field.
	LP_UART_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	LP_UART_DATE_DATE_Msk = 0xffffffff

	// AFIFO_STATUS: UART AFIFO Status
	// Position of TX_AFIFO_FULL field.
	LP_UART_AFIFO_STATUS_TX_AFIFO_FULL_Pos = 0x0
	// Bit mask of TX_AFIFO_FULL field.
	LP_UART_AFIFO_STATUS_TX_AFIFO_FULL_Msk = 0x1
	// Bit TX_AFIFO_FULL.
	LP_UART_AFIFO_STATUS_TX_AFIFO_FULL = 0x1
	// Position of TX_AFIFO_EMPTY field.
	LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Pos = 0x1
	// Bit mask of TX_AFIFO_EMPTY field.
	LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Msk = 0x2
	// Bit TX_AFIFO_EMPTY.
	LP_UART_AFIFO_STATUS_TX_AFIFO_EMPTY = 0x2
	// Position of RX_AFIFO_FULL field.
	LP_UART_AFIFO_STATUS_RX_AFIFO_FULL_Pos = 0x2
	// Bit mask of RX_AFIFO_FULL field.
	LP_UART_AFIFO_STATUS_RX_AFIFO_FULL_Msk = 0x4
	// Bit RX_AFIFO_FULL.
	LP_UART_AFIFO_STATUS_RX_AFIFO_FULL = 0x4
	// Position of RX_AFIFO_EMPTY field.
	LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Pos = 0x3
	// Bit mask of RX_AFIFO_EMPTY field.
	LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Msk = 0x8
	// Bit RX_AFIFO_EMPTY.
	LP_UART_AFIFO_STATUS_RX_AFIFO_EMPTY = 0x8

	// REG_UPDATE: UART Registers Configuration Update register
	// Position of REG_UPDATE field.
	LP_UART_REG_UPDATE_REG_UPDATE_Pos = 0x0
	// Bit mask of REG_UPDATE field.
	LP_UART_REG_UPDATE_REG_UPDATE_Msk = 0x1
	// Bit REG_UPDATE.
	LP_UART_REG_UPDATE_REG_UPDATE = 0x1

	// ID: UART ID register
	// Position of ID field.
	LP_UART_ID_ID_Pos = 0x0
	// Bit mask of ID field.
	LP_UART_ID_ID_Msk = 0xffffffff
)

// Constants for MCPWM0: Motor Control Pulse-Width Modulation 0
const (
	// CLK_CFG: PWM clock prescaler register.
	// Position of CLK_PRESCALE field.
	MCPWM_CLK_CFG_CLK_PRESCALE_Pos = 0x0
	// Bit mask of CLK_PRESCALE field.
	MCPWM_CLK_CFG_CLK_PRESCALE_Msk = 0xff

	// TIMER0_CFG0: PWM timer%s period and update method configuration register.
	// Position of TIMER_PRESCALE field.
	MCPWM_TIMER_CFG0_TIMER_PRESCALE_Pos = 0x0
	// Bit mask of TIMER_PRESCALE field.
	MCPWM_TIMER_CFG0_TIMER_PRESCALE_Msk = 0xff
	// Position of TIMER_PERIOD field.
	MCPWM_TIMER_CFG0_TIMER_PERIOD_Pos = 0x8
	// Bit mask of TIMER_PERIOD field.
	MCPWM_TIMER_CFG0_TIMER_PERIOD_Msk = 0xffff00
	// Position of TIMER_PERIOD_UPMETHOD field.
	MCPWM_TIMER_CFG0_TIMER_PERIOD_UPMETHOD_Pos = 0x18
	// Bit mask of TIMER_PERIOD_UPMETHOD field.
	MCPWM_TIMER_CFG0_TIMER_PERIOD_UPMETHOD_Msk = 0x3000000

	// TIMER0_CFG1: PWM timer%s working mode and start/stop control register.
	// Position of TIMER_START field.
	MCPWM_TIMER_CFG1_TIMER_START_Pos = 0x0
	// Bit mask of TIMER_START field.
	MCPWM_TIMER_CFG1_TIMER_START_Msk = 0x7
	// Position of TIMER_MOD field.
	MCPWM_TIMER_CFG1_TIMER_MOD_Pos = 0x3
	// Bit mask of TIMER_MOD field.
	MCPWM_TIMER_CFG1_TIMER_MOD_Msk = 0x18

	// TIMER0_SYNC: PWM timer%s sync function configuration register.
	// Position of TIMER_SYNCI_EN field.
	MCPWM_TIMER_SYNC_TIMER_SYNCI_EN_Pos = 0x0
	// Bit mask of TIMER_SYNCI_EN field.
	MCPWM_TIMER_SYNC_TIMER_SYNCI_EN_Msk = 0x1
	// Bit TIMER_SYNCI_EN.
	MCPWM_TIMER_SYNC_TIMER_SYNCI_EN = 0x1
	// Position of SW field.
	MCPWM_TIMER_SYNC_SW_Pos = 0x1
	// Bit mask of SW field.
	MCPWM_TIMER_SYNC_SW_Msk = 0x2
	// Bit SW.
	MCPWM_TIMER_SYNC_SW = 0x2
	// Position of TIMER_SYNCO_SEL field.
	MCPWM_TIMER_SYNC_TIMER_SYNCO_SEL_Pos = 0x2
	// Bit mask of TIMER_SYNCO_SEL field.
	MCPWM_TIMER_SYNC_TIMER_SYNCO_SEL_Msk = 0xc
	// Position of TIMER_PHASE field.
	MCPWM_TIMER_SYNC_TIMER_PHASE_Pos = 0x4
	// Bit mask of TIMER_PHASE field.
	MCPWM_TIMER_SYNC_TIMER_PHASE_Msk = 0xffff0
	// Position of TIMER_PHASE_DIRECTION field.
	MCPWM_TIMER_SYNC_TIMER_PHASE_DIRECTION_Pos = 0x14
	// Bit mask of TIMER_PHASE_DIRECTION field.
	MCPWM_TIMER_SYNC_TIMER_PHASE_DIRECTION_Msk = 0x100000
	// Bit TIMER_PHASE_DIRECTION.
	MCPWM_TIMER_SYNC_TIMER_PHASE_DIRECTION = 0x100000

	// TIMER0_STATUS: PWM timer%s status register.
	// Position of TIMER_VALUE field.
	MCPWM_TIMER_STATUS_TIMER_VALUE_Pos = 0x0
	// Bit mask of TIMER_VALUE field.
	MCPWM_TIMER_STATUS_TIMER_VALUE_Msk = 0xffff
	// Position of TIMER_DIRECTION field.
	MCPWM_TIMER_STATUS_TIMER_DIRECTION_Pos = 0x10
	// Bit mask of TIMER_DIRECTION field.
	MCPWM_TIMER_STATUS_TIMER_DIRECTION_Msk = 0x10000
	// Bit TIMER_DIRECTION.
	MCPWM_TIMER_STATUS_TIMER_DIRECTION = 0x10000

	// TIMER_SYNCI_CFG: Synchronization input selection register for PWM timers.
	// Position of TIMER0_SYNCISEL field.
	MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Pos = 0x0
	// Bit mask of TIMER0_SYNCISEL field.
	MCPWM_TIMER_SYNCI_CFG_TIMER0_SYNCISEL_Msk = 0x7
	// Position of TIMER1_SYNCISEL field.
	MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Pos = 0x3
	// Bit mask of TIMER1_SYNCISEL field.
	MCPWM_TIMER_SYNCI_CFG_TIMER1_SYNCISEL_Msk = 0x38
	// Position of TIMER2_SYNCISEL field.
	MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Pos = 0x6
	// Bit mask of TIMER2_SYNCISEL field.
	MCPWM_TIMER_SYNCI_CFG_TIMER2_SYNCISEL_Msk = 0x1c0
	// Position of EXTERNAL_SYNCI0_INVERT field.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Pos = 0x9
	// Bit mask of EXTERNAL_SYNCI0_INVERT field.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT_Msk = 0x200
	// Bit EXTERNAL_SYNCI0_INVERT.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI0_INVERT = 0x200
	// Position of EXTERNAL_SYNCI1_INVERT field.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Pos = 0xa
	// Bit mask of EXTERNAL_SYNCI1_INVERT field.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT_Msk = 0x400
	// Bit EXTERNAL_SYNCI1_INVERT.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI1_INVERT = 0x400
	// Position of EXTERNAL_SYNCI2_INVERT field.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Pos = 0xb
	// Bit mask of EXTERNAL_SYNCI2_INVERT field.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT_Msk = 0x800
	// Bit EXTERNAL_SYNCI2_INVERT.
	MCPWM_TIMER_SYNCI_CFG_EXTERNAL_SYNCI2_INVERT = 0x800

	// OPERATOR_TIMERSEL: PWM operator's timer select register
	// Position of OPERATOR0_TIMERSEL field.
	MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Pos = 0x0
	// Bit mask of OPERATOR0_TIMERSEL field.
	MCPWM_OPERATOR_TIMERSEL_OPERATOR0_TIMERSEL_Msk = 0x3
	// Position of OPERATOR1_TIMERSEL field.
	MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Pos = 0x2
	// Bit mask of OPERATOR1_TIMERSEL field.
	MCPWM_OPERATOR_TIMERSEL_OPERATOR1_TIMERSEL_Msk = 0xc
	// Position of OPERATOR2_TIMERSEL field.
	MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Pos = 0x4
	// Bit mask of OPERATOR2_TIMERSEL field.
	MCPWM_OPERATOR_TIMERSEL_OPERATOR2_TIMERSEL_Msk = 0x30

	// GEN0_STMP_CFG: Generator%s time stamp registers A and B transfer status and update method register
	// Position of CMPR_A_UPMETHOD field.
	MCPWM_GEN_STMP_CFG_CMPR_A_UPMETHOD_Pos = 0x0
	// Bit mask of CMPR_A_UPMETHOD field.
	MCPWM_GEN_STMP_CFG_CMPR_A_UPMETHOD_Msk = 0xf
	// Position of CMPR_B_UPMETHOD field.
	MCPWM_GEN_STMP_CFG_CMPR_B_UPMETHOD_Pos = 0x4
	// Bit mask of CMPR_B_UPMETHOD field.
	MCPWM_GEN_STMP_CFG_CMPR_B_UPMETHOD_Msk = 0xf0
	// Position of CMPR_A_SHDW_FULL field.
	MCPWM_GEN_STMP_CFG_CMPR_A_SHDW_FULL_Pos = 0x8
	// Bit mask of CMPR_A_SHDW_FULL field.
	MCPWM_GEN_STMP_CFG_CMPR_A_SHDW_FULL_Msk = 0x100
	// Bit CMPR_A_SHDW_FULL.
	MCPWM_GEN_STMP_CFG_CMPR_A_SHDW_FULL = 0x100
	// Position of CMPR_B_SHDW_FULL field.
	MCPWM_GEN_STMP_CFG_CMPR_B_SHDW_FULL_Pos = 0x9
	// Bit mask of CMPR_B_SHDW_FULL field.
	MCPWM_GEN_STMP_CFG_CMPR_B_SHDW_FULL_Msk = 0x200
	// Bit CMPR_B_SHDW_FULL.
	MCPWM_GEN_STMP_CFG_CMPR_B_SHDW_FULL = 0x200

	// GEN0_TSTMP_A: Generator%s time stamp A's shadow register
	// Position of CMPR_A field.
	MCPWM_GEN_TSTMP_A_CMPR_A_Pos = 0x0
	// Bit mask of CMPR_A field.
	MCPWM_GEN_TSTMP_A_CMPR_A_Msk = 0xffff

	// GEN0_TSTMP_B: Generator%s time stamp B's shadow register
	// Position of CMPR_B field.
	MCPWM_GEN_TSTMP_B_CMPR_B_Pos = 0x0
	// Bit mask of CMPR_B field.
	MCPWM_GEN_TSTMP_B_CMPR_B_Msk = 0xffff

	// GEN0_CFG0: Generator%s fault event T0 and T1 configuration register
	// Position of GEN_CFG_UPMETHOD field.
	MCPWM_GEN_CFG0_GEN_CFG_UPMETHOD_Pos = 0x0
	// Bit mask of GEN_CFG_UPMETHOD field.
	MCPWM_GEN_CFG0_GEN_CFG_UPMETHOD_Msk = 0xf
	// Position of GEN_T0_SEL field.
	MCPWM_GEN_CFG0_GEN_T0_SEL_Pos = 0x4
	// Bit mask of GEN_T0_SEL field.
	MCPWM_GEN_CFG0_GEN_T0_SEL_Msk = 0x70
	// Position of GEN_T1_SEL field.
	MCPWM_GEN_CFG0_GEN_T1_SEL_Pos = 0x7
	// Bit mask of GEN_T1_SEL field.
	MCPWM_GEN_CFG0_GEN_T1_SEL_Msk = 0x380

	// GEN0_FORCE: Generator%s output signal force mode register.
	// Position of GEN_CNTUFORCE_UPMETHOD field.
	MCPWM_GEN_FORCE_GEN_CNTUFORCE_UPMETHOD_Pos = 0x0
	// Bit mask of GEN_CNTUFORCE_UPMETHOD field.
	MCPWM_GEN_FORCE_GEN_CNTUFORCE_UPMETHOD_Msk = 0x3f
	// Position of GEN_A_CNTUFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_A_CNTUFORCE_MODE_Pos = 0x6
	// Bit mask of GEN_A_CNTUFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_A_CNTUFORCE_MODE_Msk = 0xc0
	// Position of GEN_B_CNTUFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_B_CNTUFORCE_MODE_Pos = 0x8
	// Bit mask of GEN_B_CNTUFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_B_CNTUFORCE_MODE_Msk = 0x300
	// Position of GEN_A_NCIFORCE field.
	MCPWM_GEN_FORCE_GEN_A_NCIFORCE_Pos = 0xa
	// Bit mask of GEN_A_NCIFORCE field.
	MCPWM_GEN_FORCE_GEN_A_NCIFORCE_Msk = 0x400
	// Bit GEN_A_NCIFORCE.
	MCPWM_GEN_FORCE_GEN_A_NCIFORCE = 0x400
	// Position of GEN_A_NCIFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_A_NCIFORCE_MODE_Pos = 0xb
	// Bit mask of GEN_A_NCIFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_A_NCIFORCE_MODE_Msk = 0x1800
	// Position of GEN_B_NCIFORCE field.
	MCPWM_GEN_FORCE_GEN_B_NCIFORCE_Pos = 0xd
	// Bit mask of GEN_B_NCIFORCE field.
	MCPWM_GEN_FORCE_GEN_B_NCIFORCE_Msk = 0x2000
	// Bit GEN_B_NCIFORCE.
	MCPWM_GEN_FORCE_GEN_B_NCIFORCE = 0x2000
	// Position of GEN_B_NCIFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_B_NCIFORCE_MODE_Pos = 0xe
	// Bit mask of GEN_B_NCIFORCE_MODE field.
	MCPWM_GEN_FORCE_GEN_B_NCIFORCE_MODE_Msk = 0xc000

	// GEN0_A: PWM%s output signal A actions configuration register
	// Position of UTEZ field.
	MCPWM_GEN_A_UTEZ_Pos = 0x0
	// Bit mask of UTEZ field.
	MCPWM_GEN_A_UTEZ_Msk = 0x3
	// Position of UTEP field.
	MCPWM_GEN_A_UTEP_Pos = 0x2
	// Bit mask of UTEP field.
	MCPWM_GEN_A_UTEP_Msk = 0xc
	// Position of UTEA field.
	MCPWM_GEN_A_UTEA_Pos = 0x4
	// Bit mask of UTEA field.
	MCPWM_GEN_A_UTEA_Msk = 0x30
	// Position of UTEB field.
	MCPWM_GEN_A_UTEB_Pos = 0x6
	// Bit mask of UTEB field.
	MCPWM_GEN_A_UTEB_Msk = 0xc0
	// Position of UT0 field.
	MCPWM_GEN_A_UT0_Pos = 0x8
	// Bit mask of UT0 field.
	MCPWM_GEN_A_UT0_Msk = 0x300
	// Position of UT1 field.
	MCPWM_GEN_A_UT1_Pos = 0xa
	// Bit mask of UT1 field.
	MCPWM_GEN_A_UT1_Msk = 0xc00
	// Position of DTEZ field.
	MCPWM_GEN_A_DTEZ_Pos = 0xc
	// Bit mask of DTEZ field.
	MCPWM_GEN_A_DTEZ_Msk = 0x3000
	// Position of DTEP field.
	MCPWM_GEN_A_DTEP_Pos = 0xe
	// Bit mask of DTEP field.
	MCPWM_GEN_A_DTEP_Msk = 0xc000
	// Position of DTEA field.
	MCPWM_GEN_A_DTEA_Pos = 0x10
	// Bit mask of DTEA field.
	MCPWM_GEN_A_DTEA_Msk = 0x30000
	// Position of DTEB field.
	MCPWM_GEN_A_DTEB_Pos = 0x12
	// Bit mask of DTEB field.
	MCPWM_GEN_A_DTEB_Msk = 0xc0000
	// Position of DT0 field.
	MCPWM_GEN_A_DT0_Pos = 0x14
	// Bit mask of DT0 field.
	MCPWM_GEN_A_DT0_Msk = 0x300000
	// Position of DT1 field.
	MCPWM_GEN_A_DT1_Pos = 0x16
	// Bit mask of DT1 field.
	MCPWM_GEN_A_DT1_Msk = 0xc00000

	// GEN0_B: PWM%s output signal B actions configuration register
	// Position of UTEZ field.
	MCPWM_GEN_B_UTEZ_Pos = 0x0
	// Bit mask of UTEZ field.
	MCPWM_GEN_B_UTEZ_Msk = 0x3
	// Position of UTEP field.
	MCPWM_GEN_B_UTEP_Pos = 0x2
	// Bit mask of UTEP field.
	MCPWM_GEN_B_UTEP_Msk = 0xc
	// Position of UTEA field.
	MCPWM_GEN_B_UTEA_Pos = 0x4
	// Bit mask of UTEA field.
	MCPWM_GEN_B_UTEA_Msk = 0x30
	// Position of UTEB field.
	MCPWM_GEN_B_UTEB_Pos = 0x6
	// Bit mask of UTEB field.
	MCPWM_GEN_B_UTEB_Msk = 0xc0
	// Position of UT0 field.
	MCPWM_GEN_B_UT0_Pos = 0x8
	// Bit mask of UT0 field.
	MCPWM_GEN_B_UT0_Msk = 0x300
	// Position of UT1 field.
	MCPWM_GEN_B_UT1_Pos = 0xa
	// Bit mask of UT1 field.
	MCPWM_GEN_B_UT1_Msk = 0xc00
	// Position of DTEZ field.
	MCPWM_GEN_B_DTEZ_Pos = 0xc
	// Bit mask of DTEZ field.
	MCPWM_GEN_B_DTEZ_Msk = 0x3000
	// Position of DTEP field.
	MCPWM_GEN_B_DTEP_Pos = 0xe
	// Bit mask of DTEP field.
	MCPWM_GEN_B_DTEP_Msk = 0xc000
	// Position of DTEA field.
	MCPWM_GEN_B_DTEA_Pos = 0x10
	// Bit mask of DTEA field.
	MCPWM_GEN_B_DTEA_Msk = 0x30000
	// Position of DTEB field.
	MCPWM_GEN_B_DTEB_Pos = 0x12
	// Bit mask of DTEB field.
	MCPWM_GEN_B_DTEB_Msk = 0xc0000
	// Position of DT0 field.
	MCPWM_GEN_B_DT0_Pos = 0x14
	// Bit mask of DT0 field.
	MCPWM_GEN_B_DT0_Msk = 0x300000
	// Position of DT1 field.
	MCPWM_GEN_B_DT1_Pos = 0x16
	// Bit mask of DT1 field.
	MCPWM_GEN_B_DT1_Msk = 0xc00000

	// DT0_CFG: Dead time configuration register
	// Position of DB_FED_UPMETHOD field.
	MCPWM_DT_CFG_DB_FED_UPMETHOD_Pos = 0x0
	// Bit mask of DB_FED_UPMETHOD field.
	MCPWM_DT_CFG_DB_FED_UPMETHOD_Msk = 0xf
	// Position of DB_RED_UPMETHOD field.
	MCPWM_DT_CFG_DB_RED_UPMETHOD_Pos = 0x4
	// Bit mask of DB_RED_UPMETHOD field.
	MCPWM_DT_CFG_DB_RED_UPMETHOD_Msk = 0xf0
	// Position of DB_DEB_MODE field.
	MCPWM_DT_CFG_DB_DEB_MODE_Pos = 0x8
	// Bit mask of DB_DEB_MODE field.
	MCPWM_DT_CFG_DB_DEB_MODE_Msk = 0x100
	// Bit DB_DEB_MODE.
	MCPWM_DT_CFG_DB_DEB_MODE = 0x100
	// Position of DB_A_OUTSWAP field.
	MCPWM_DT_CFG_DB_A_OUTSWAP_Pos = 0x9
	// Bit mask of DB_A_OUTSWAP field.
	MCPWM_DT_CFG_DB_A_OUTSWAP_Msk = 0x200
	// Bit DB_A_OUTSWAP.
	MCPWM_DT_CFG_DB_A_OUTSWAP = 0x200
	// Position of DB_B_OUTSWAP field.
	MCPWM_DT_CFG_DB_B_OUTSWAP_Pos = 0xa
	// Bit mask of DB_B_OUTSWAP field.
	MCPWM_DT_CFG_DB_B_OUTSWAP_Msk = 0x400
	// Bit DB_B_OUTSWAP.
	MCPWM_DT_CFG_DB_B_OUTSWAP = 0x400
	// Position of DB_RED_INSEL field.
	MCPWM_DT_CFG_DB_RED_INSEL_Pos = 0xb
	// Bit mask of DB_RED_INSEL field.
	MCPWM_DT_CFG_DB_RED_INSEL_Msk = 0x800
	// Bit DB_RED_INSEL.
	MCPWM_DT_CFG_DB_RED_INSEL = 0x800
	// Position of DB_FED_INSEL field.
	MCPWM_DT_CFG_DB_FED_INSEL_Pos = 0xc
	// Bit mask of DB_FED_INSEL field.
	MCPWM_DT_CFG_DB_FED_INSEL_Msk = 0x1000
	// Bit DB_FED_INSEL.
	MCPWM_DT_CFG_DB_FED_INSEL = 0x1000
	// Position of DB_RED_OUTINVERT field.
	MCPWM_DT_CFG_DB_RED_OUTINVERT_Pos = 0xd
	// Bit mask of DB_RED_OUTINVERT field.
	MCPWM_DT_CFG_DB_RED_OUTINVERT_Msk = 0x2000
	// Bit DB_RED_OUTINVERT.
	MCPWM_DT_CFG_DB_RED_OUTINVERT = 0x2000
	// Position of DB_FED_OUTINVERT field.
	MCPWM_DT_CFG_DB_FED_OUTINVERT_Pos = 0xe
	// Bit mask of DB_FED_OUTINVERT field.
	MCPWM_DT_CFG_DB_FED_OUTINVERT_Msk = 0x4000
	// Bit DB_FED_OUTINVERT.
	MCPWM_DT_CFG_DB_FED_OUTINVERT = 0x4000
	// Position of DB_A_OUTBYPASS field.
	MCPWM_DT_CFG_DB_A_OUTBYPASS_Pos = 0xf
	// Bit mask of DB_A_OUTBYPASS field.
	MCPWM_DT_CFG_DB_A_OUTBYPASS_Msk = 0x8000
	// Bit DB_A_OUTBYPASS.
	MCPWM_DT_CFG_DB_A_OUTBYPASS = 0x8000
	// Position of DB_B_OUTBYPASS field.
	MCPWM_DT_CFG_DB_B_OUTBYPASS_Pos = 0x10
	// Bit mask of DB_B_OUTBYPASS field.
	MCPWM_DT_CFG_DB_B_OUTBYPASS_Msk = 0x10000
	// Bit DB_B_OUTBYPASS.
	MCPWM_DT_CFG_DB_B_OUTBYPASS = 0x10000
	// Position of DB_CLK_SEL field.
	MCPWM_DT_CFG_DB_CLK_SEL_Pos = 0x11
	// Bit mask of DB_CLK_SEL field.
	MCPWM_DT_CFG_DB_CLK_SEL_Msk = 0x20000
	// Bit DB_CLK_SEL.
	MCPWM_DT_CFG_DB_CLK_SEL = 0x20000

	// DT0_FED_CFG: Falling edge delay (FED) shadow register
	// Position of DB_FED field.
	MCPWM_DT_FED_CFG_DB_FED_Pos = 0x0
	// Bit mask of DB_FED field.
	MCPWM_DT_FED_CFG_DB_FED_Msk = 0xffff

	// DT0_RED_CFG: Rising edge delay (RED) shadow register
	// Position of DB_RED field.
	MCPWM_DT_RED_CFG_DB_RED_Pos = 0x0
	// Bit mask of DB_RED field.
	MCPWM_DT_RED_CFG_DB_RED_Msk = 0xffff

	// CARRIER0_CFG: Carrier%s configuration register
	// Position of CHOPPER_EN field.
	MCPWM_CARRIER_CFG_CHOPPER_EN_Pos = 0x0
	// Bit mask of CHOPPER_EN field.
	MCPWM_CARRIER_CFG_CHOPPER_EN_Msk = 0x1
	// Bit CHOPPER_EN.
	MCPWM_CARRIER_CFG_CHOPPER_EN = 0x1
	// Position of CHOPPER_PRESCALE field.
	MCPWM_CARRIER_CFG_CHOPPER_PRESCALE_Pos = 0x1
	// Bit mask of CHOPPER_PRESCALE field.
	MCPWM_CARRIER_CFG_CHOPPER_PRESCALE_Msk = 0x1e
	// Position of CHOPPER_DUTY field.
	MCPWM_CARRIER_CFG_CHOPPER_DUTY_Pos = 0x5
	// Bit mask of CHOPPER_DUTY field.
	MCPWM_CARRIER_CFG_CHOPPER_DUTY_Msk = 0xe0
	// Position of CHOPPER_OSHTWTH field.
	MCPWM_CARRIER_CFG_CHOPPER_OSHTWTH_Pos = 0x8
	// Bit mask of CHOPPER_OSHTWTH field.
	MCPWM_CARRIER_CFG_CHOPPER_OSHTWTH_Msk = 0xf00
	// Position of CHOPPER_OUT_INVERT field.
	MCPWM_CARRIER_CFG_CHOPPER_OUT_INVERT_Pos = 0xc
	// Bit mask of CHOPPER_OUT_INVERT field.
	MCPWM_CARRIER_CFG_CHOPPER_OUT_INVERT_Msk = 0x1000
	// Bit CHOPPER_OUT_INVERT.
	MCPWM_CARRIER_CFG_CHOPPER_OUT_INVERT = 0x1000
	// Position of CHOPPER_IN_INVERT field.
	MCPWM_CARRIER_CFG_CHOPPER_IN_INVERT_Pos = 0xd
	// Bit mask of CHOPPER_IN_INVERT field.
	MCPWM_CARRIER_CFG_CHOPPER_IN_INVERT_Msk = 0x2000
	// Bit CHOPPER_IN_INVERT.
	MCPWM_CARRIER_CFG_CHOPPER_IN_INVERT = 0x2000

	// FH0_CFG0: PWM%s A and PWM%s B trip events actions configuration register
	// Position of TZ_SW_CBC field.
	MCPWM_FH_CFG0_TZ_SW_CBC_Pos = 0x0
	// Bit mask of TZ_SW_CBC field.
	MCPWM_FH_CFG0_TZ_SW_CBC_Msk = 0x1
	// Bit TZ_SW_CBC.
	MCPWM_FH_CFG0_TZ_SW_CBC = 0x1
	// Position of TZ_F2_CBC field.
	MCPWM_FH_CFG0_TZ_F2_CBC_Pos = 0x1
	// Bit mask of TZ_F2_CBC field.
	MCPWM_FH_CFG0_TZ_F2_CBC_Msk = 0x2
	// Bit TZ_F2_CBC.
	MCPWM_FH_CFG0_TZ_F2_CBC = 0x2
	// Position of TZ_F1_CBC field.
	MCPWM_FH_CFG0_TZ_F1_CBC_Pos = 0x2
	// Bit mask of TZ_F1_CBC field.
	MCPWM_FH_CFG0_TZ_F1_CBC_Msk = 0x4
	// Bit TZ_F1_CBC.
	MCPWM_FH_CFG0_TZ_F1_CBC = 0x4
	// Position of TZ_F0_CBC field.
	MCPWM_FH_CFG0_TZ_F0_CBC_Pos = 0x3
	// Bit mask of TZ_F0_CBC field.
	MCPWM_FH_CFG0_TZ_F0_CBC_Msk = 0x8
	// Bit TZ_F0_CBC.
	MCPWM_FH_CFG0_TZ_F0_CBC = 0x8
	// Position of TZ_SW_OST field.
	MCPWM_FH_CFG0_TZ_SW_OST_Pos = 0x4
	// Bit mask of TZ_SW_OST field.
	MCPWM_FH_CFG0_TZ_SW_OST_Msk = 0x10
	// Bit TZ_SW_OST.
	MCPWM_FH_CFG0_TZ_SW_OST = 0x10
	// Position of TZ_F2_OST field.
	MCPWM_FH_CFG0_TZ_F2_OST_Pos = 0x5
	// Bit mask of TZ_F2_OST field.
	MCPWM_FH_CFG0_TZ_F2_OST_Msk = 0x20
	// Bit TZ_F2_OST.
	MCPWM_FH_CFG0_TZ_F2_OST = 0x20
	// Position of TZ_F1_OST field.
	MCPWM_FH_CFG0_TZ_F1_OST_Pos = 0x6
	// Bit mask of TZ_F1_OST field.
	MCPWM_FH_CFG0_TZ_F1_OST_Msk = 0x40
	// Bit TZ_F1_OST.
	MCPWM_FH_CFG0_TZ_F1_OST = 0x40
	// Position of TZ_F0_OST field.
	MCPWM_FH_CFG0_TZ_F0_OST_Pos = 0x7
	// Bit mask of TZ_F0_OST field.
	MCPWM_FH_CFG0_TZ_F0_OST_Msk = 0x80
	// Bit TZ_F0_OST.
	MCPWM_FH_CFG0_TZ_F0_OST = 0x80
	// Position of TZ_A_CBC_D field.
	MCPWM_FH_CFG0_TZ_A_CBC_D_Pos = 0x8
	// Bit mask of TZ_A_CBC_D field.
	MCPWM_FH_CFG0_TZ_A_CBC_D_Msk = 0x300
	// Position of TZ_A_CBC_U field.
	MCPWM_FH_CFG0_TZ_A_CBC_U_Pos = 0xa
	// Bit mask of TZ_A_CBC_U field.
	MCPWM_FH_CFG0_TZ_A_CBC_U_Msk = 0xc00
	// Position of TZ_A_OST_D field.
	MCPWM_FH_CFG0_TZ_A_OST_D_Pos = 0xc
	// Bit mask of TZ_A_OST_D field.
	MCPWM_FH_CFG0_TZ_A_OST_D_Msk = 0x3000
	// Position of TZ_A_OST_U field.
	MCPWM_FH_CFG0_TZ_A_OST_U_Pos = 0xe
	// Bit mask of TZ_A_OST_U field.
	MCPWM_FH_CFG0_TZ_A_OST_U_Msk = 0xc000
	// Position of TZ_B_CBC_D field.
	MCPWM_FH_CFG0_TZ_B_CBC_D_Pos = 0x10
	// Bit mask of TZ_B_CBC_D field.
	MCPWM_FH_CFG0_TZ_B_CBC_D_Msk = 0x30000
	// Position of TZ_B_CBC_U field.
	MCPWM_FH_CFG0_TZ_B_CBC_U_Pos = 0x12
	// Bit mask of TZ_B_CBC_U field.
	MCPWM_FH_CFG0_TZ_B_CBC_U_Msk = 0xc0000
	// Position of TZ_B_OST_D field.
	MCPWM_FH_CFG0_TZ_B_OST_D_Pos = 0x14
	// Bit mask of TZ_B_OST_D field.
	MCPWM_FH_CFG0_TZ_B_OST_D_Msk = 0x300000
	// Position of TZ_B_OST_U field.
	MCPWM_FH_CFG0_TZ_B_OST_U_Pos = 0x16
	// Bit mask of TZ_B_OST_U field.
	MCPWM_FH_CFG0_TZ_B_OST_U_Msk = 0xc00000

	// FH0_CFG1: Software triggers for fault handler actions configuration register
	// Position of TZ_CLR_OST field.
	MCPWM_FH_CFG1_TZ_CLR_OST_Pos = 0x0
	// Bit mask of TZ_CLR_OST field.
	MCPWM_FH_CFG1_TZ_CLR_OST_Msk = 0x1
	// Bit TZ_CLR_OST.
	MCPWM_FH_CFG1_TZ_CLR_OST = 0x1
	// Position of TZ_CBCPULSE field.
	MCPWM_FH_CFG1_TZ_CBCPULSE_Pos = 0x1
	// Bit mask of TZ_CBCPULSE field.
	MCPWM_FH_CFG1_TZ_CBCPULSE_Msk = 0x6
	// Position of TZ_FORCE_CBC field.
	MCPWM_FH_CFG1_TZ_FORCE_CBC_Pos = 0x3
	// Bit mask of TZ_FORCE_CBC field.
	MCPWM_FH_CFG1_TZ_FORCE_CBC_Msk = 0x8
	// Bit TZ_FORCE_CBC.
	MCPWM_FH_CFG1_TZ_FORCE_CBC = 0x8
	// Position of TZ_FORCE_OST field.
	MCPWM_FH_CFG1_TZ_FORCE_OST_Pos = 0x4
	// Bit mask of TZ_FORCE_OST field.
	MCPWM_FH_CFG1_TZ_FORCE_OST_Msk = 0x10
	// Bit TZ_FORCE_OST.
	MCPWM_FH_CFG1_TZ_FORCE_OST = 0x10

	// FH0_STATUS: Fault events status register
	// Position of TZ_CBC_ON field.
	MCPWM_FH_STATUS_TZ_CBC_ON_Pos = 0x0
	// Bit mask of TZ_CBC_ON field.
	MCPWM_FH_STATUS_TZ_CBC_ON_Msk = 0x1
	// Bit TZ_CBC_ON.
	MCPWM_FH_STATUS_TZ_CBC_ON = 0x1
	// Position of TZ_OST_ON field.
	MCPWM_FH_STATUS_TZ_OST_ON_Pos = 0x1
	// Bit mask of TZ_OST_ON field.
	MCPWM_FH_STATUS_TZ_OST_ON_Msk = 0x2
	// Bit TZ_OST_ON.
	MCPWM_FH_STATUS_TZ_OST_ON = 0x2

	// FAULT_DETECT: Fault detection configuration and status register
	// Position of F0_EN field.
	MCPWM_FAULT_DETECT_F0_EN_Pos = 0x0
	// Bit mask of F0_EN field.
	MCPWM_FAULT_DETECT_F0_EN_Msk = 0x1
	// Bit F0_EN.
	MCPWM_FAULT_DETECT_F0_EN = 0x1
	// Position of F1_EN field.
	MCPWM_FAULT_DETECT_F1_EN_Pos = 0x1
	// Bit mask of F1_EN field.
	MCPWM_FAULT_DETECT_F1_EN_Msk = 0x2
	// Bit F1_EN.
	MCPWM_FAULT_DETECT_F1_EN = 0x2
	// Position of F2_EN field.
	MCPWM_FAULT_DETECT_F2_EN_Pos = 0x2
	// Bit mask of F2_EN field.
	MCPWM_FAULT_DETECT_F2_EN_Msk = 0x4
	// Bit F2_EN.
	MCPWM_FAULT_DETECT_F2_EN = 0x4
	// Position of F0_POLE field.
	MCPWM_FAULT_DETECT_F0_POLE_Pos = 0x3
	// Bit mask of F0_POLE field.
	MCPWM_FAULT_DETECT_F0_POLE_Msk = 0x8
	// Bit F0_POLE.
	MCPWM_FAULT_DETECT_F0_POLE = 0x8
	// Position of F1_POLE field.
	MCPWM_FAULT_DETECT_F1_POLE_Pos = 0x4
	// Bit mask of F1_POLE field.
	MCPWM_FAULT_DETECT_F1_POLE_Msk = 0x10
	// Bit F1_POLE.
	MCPWM_FAULT_DETECT_F1_POLE = 0x10
	// Position of F2_POLE field.
	MCPWM_FAULT_DETECT_F2_POLE_Pos = 0x5
	// Bit mask of F2_POLE field.
	MCPWM_FAULT_DETECT_F2_POLE_Msk = 0x20
	// Bit F2_POLE.
	MCPWM_FAULT_DETECT_F2_POLE = 0x20
	// Position of EVENT_F0 field.
	MCPWM_FAULT_DETECT_EVENT_F0_Pos = 0x6
	// Bit mask of EVENT_F0 field.
	MCPWM_FAULT_DETECT_EVENT_F0_Msk = 0x40
	// Bit EVENT_F0.
	MCPWM_FAULT_DETECT_EVENT_F0 = 0x40
	// Position of EVENT_F1 field.
	MCPWM_FAULT_DETECT_EVENT_F1_Pos = 0x7
	// Bit mask of EVENT_F1 field.
	MCPWM_FAULT_DETECT_EVENT_F1_Msk = 0x80
	// Bit EVENT_F1.
	MCPWM_FAULT_DETECT_EVENT_F1 = 0x80
	// Position of EVENT_F2 field.
	MCPWM_FAULT_DETECT_EVENT_F2_Pos = 0x8
	// Bit mask of EVENT_F2 field.
	MCPWM_FAULT_DETECT_EVENT_F2_Msk = 0x100
	// Bit EVENT_F2.
	MCPWM_FAULT_DETECT_EVENT_F2 = 0x100

	// CAP_TIMER_CFG: Capture timer configuration register
	// Position of CAP_TIMER_EN field.
	MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Pos = 0x0
	// Bit mask of CAP_TIMER_EN field.
	MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN_Msk = 0x1
	// Bit CAP_TIMER_EN.
	MCPWM_CAP_TIMER_CFG_CAP_TIMER_EN = 0x1
	// Position of CAP_SYNCI_EN field.
	MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Pos = 0x1
	// Bit mask of CAP_SYNCI_EN field.
	MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN_Msk = 0x2
	// Bit CAP_SYNCI_EN.
	MCPWM_CAP_TIMER_CFG_CAP_SYNCI_EN = 0x2
	// Position of CAP_SYNCI_SEL field.
	MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Pos = 0x2
	// Bit mask of CAP_SYNCI_SEL field.
	MCPWM_CAP_TIMER_CFG_CAP_SYNCI_SEL_Msk = 0x1c
	// Position of CAP_SYNC_SW field.
	MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Pos = 0x5
	// Bit mask of CAP_SYNC_SW field.
	MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW_Msk = 0x20
	// Bit CAP_SYNC_SW.
	MCPWM_CAP_TIMER_CFG_CAP_SYNC_SW = 0x20

	// CAP_TIMER_PHASE: Capture timer sync phase register
	// Position of CAP_PHASE field.
	MCPWM_CAP_TIMER_PHASE_CAP_PHASE_Pos = 0x0
	// Bit mask of CAP_PHASE field.
	MCPWM_CAP_TIMER_PHASE_CAP_PHASE_Msk = 0xffffffff

	// CAP_CH0_CFG: Capture channel %s configuration register
	// Position of CAP_EN field.
	MCPWM_CAP_CH_CFG_CAP_EN_Pos = 0x0
	// Bit mask of CAP_EN field.
	MCPWM_CAP_CH_CFG_CAP_EN_Msk = 0x1
	// Bit CAP_EN.
	MCPWM_CAP_CH_CFG_CAP_EN = 0x1
	// Position of CAP_MODE field.
	MCPWM_CAP_CH_CFG_CAP_MODE_Pos = 0x1
	// Bit mask of CAP_MODE field.
	MCPWM_CAP_CH_CFG_CAP_MODE_Msk = 0x6
	// Position of CAP_PRESCALE field.
	MCPWM_CAP_CH_CFG_CAP_PRESCALE_Pos = 0x3
	// Bit mask of CAP_PRESCALE field.
	MCPWM_CAP_CH_CFG_CAP_PRESCALE_Msk = 0x7f8
	// Position of CAP_IN_INVERT field.
	MCPWM_CAP_CH_CFG_CAP_IN_INVERT_Pos = 0xb
	// Bit mask of CAP_IN_INVERT field.
	MCPWM_CAP_CH_CFG_CAP_IN_INVERT_Msk = 0x800
	// Bit CAP_IN_INVERT.
	MCPWM_CAP_CH_CFG_CAP_IN_INVERT = 0x800
	// Position of CAP_SW field.
	MCPWM_CAP_CH_CFG_CAP_SW_Pos = 0xc
	// Bit mask of CAP_SW field.
	MCPWM_CAP_CH_CFG_CAP_SW_Msk = 0x1000
	// Bit CAP_SW.
	MCPWM_CAP_CH_CFG_CAP_SW = 0x1000

	// CAP_CH0: CAP%s capture value register
	// Position of CAP_VALUE field.
	MCPWM_CAP_CH_CAP_VALUE_Pos = 0x0
	// Bit mask of CAP_VALUE field.
	MCPWM_CAP_CH_CAP_VALUE_Msk = 0xffffffff

	// CAP_STATUS: Last capture trigger edge information register
	// Position of CAP0_EDGE field.
	MCPWM_CAP_STATUS_CAP0_EDGE_Pos = 0x0
	// Bit mask of CAP0_EDGE field.
	MCPWM_CAP_STATUS_CAP0_EDGE_Msk = 0x1
	// Bit CAP0_EDGE.
	MCPWM_CAP_STATUS_CAP0_EDGE = 0x1
	// Position of CAP1_EDGE field.
	MCPWM_CAP_STATUS_CAP1_EDGE_Pos = 0x1
	// Bit mask of CAP1_EDGE field.
	MCPWM_CAP_STATUS_CAP1_EDGE_Msk = 0x2
	// Bit CAP1_EDGE.
	MCPWM_CAP_STATUS_CAP1_EDGE = 0x2
	// Position of CAP2_EDGE field.
	MCPWM_CAP_STATUS_CAP2_EDGE_Pos = 0x2
	// Bit mask of CAP2_EDGE field.
	MCPWM_CAP_STATUS_CAP2_EDGE_Msk = 0x4
	// Bit CAP2_EDGE.
	MCPWM_CAP_STATUS_CAP2_EDGE = 0x4

	// UPDATE_CFG: Generator Update configuration register
	// Position of GLOBAL_UP_EN field.
	MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Pos = 0x0
	// Bit mask of GLOBAL_UP_EN field.
	MCPWM_UPDATE_CFG_GLOBAL_UP_EN_Msk = 0x1
	// Bit GLOBAL_UP_EN.
	MCPWM_UPDATE_CFG_GLOBAL_UP_EN = 0x1
	// Position of GLOBAL_FORCE_UP field.
	MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Pos = 0x1
	// Bit mask of GLOBAL_FORCE_UP field.
	MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP_Msk = 0x2
	// Bit GLOBAL_FORCE_UP.
	MCPWM_UPDATE_CFG_GLOBAL_FORCE_UP = 0x2
	// Position of OP0_UP_EN field.
	MCPWM_UPDATE_CFG_OP0_UP_EN_Pos = 0x2
	// Bit mask of OP0_UP_EN field.
	MCPWM_UPDATE_CFG_OP0_UP_EN_Msk = 0x4
	// Bit OP0_UP_EN.
	MCPWM_UPDATE_CFG_OP0_UP_EN = 0x4
	// Position of OP0_FORCE_UP field.
	MCPWM_UPDATE_CFG_OP0_FORCE_UP_Pos = 0x3
	// Bit mask of OP0_FORCE_UP field.
	MCPWM_UPDATE_CFG_OP0_FORCE_UP_Msk = 0x8
	// Bit OP0_FORCE_UP.
	MCPWM_UPDATE_CFG_OP0_FORCE_UP = 0x8
	// Position of OP1_UP_EN field.
	MCPWM_UPDATE_CFG_OP1_UP_EN_Pos = 0x4
	// Bit mask of OP1_UP_EN field.
	MCPWM_UPDATE_CFG_OP1_UP_EN_Msk = 0x10
	// Bit OP1_UP_EN.
	MCPWM_UPDATE_CFG_OP1_UP_EN = 0x10
	// Position of OP1_FORCE_UP field.
	MCPWM_UPDATE_CFG_OP1_FORCE_UP_Pos = 0x5
	// Bit mask of OP1_FORCE_UP field.
	MCPWM_UPDATE_CFG_OP1_FORCE_UP_Msk = 0x20
	// Bit OP1_FORCE_UP.
	MCPWM_UPDATE_CFG_OP1_FORCE_UP = 0x20
	// Position of OP2_UP_EN field.
	MCPWM_UPDATE_CFG_OP2_UP_EN_Pos = 0x6
	// Bit mask of OP2_UP_EN field.
	MCPWM_UPDATE_CFG_OP2_UP_EN_Msk = 0x40
	// Bit OP2_UP_EN.
	MCPWM_UPDATE_CFG_OP2_UP_EN = 0x40
	// Position of OP2_FORCE_UP field.
	MCPWM_UPDATE_CFG_OP2_FORCE_UP_Pos = 0x7
	// Bit mask of OP2_FORCE_UP field.
	MCPWM_UPDATE_CFG_OP2_FORCE_UP_Msk = 0x80
	// Bit OP2_FORCE_UP.
	MCPWM_UPDATE_CFG_OP2_FORCE_UP = 0x80

	// INT_ENA: Interrupt enable register
	// Position of TIMER0_STOP_INT_ENA field.
	MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Pos = 0x0
	// Bit mask of TIMER0_STOP_INT_ENA field.
	MCPWM_INT_ENA_TIMER0_STOP_INT_ENA_Msk = 0x1
	// Bit TIMER0_STOP_INT_ENA.
	MCPWM_INT_ENA_TIMER0_STOP_INT_ENA = 0x1
	// Position of TIMER1_STOP_INT_ENA field.
	MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Pos = 0x1
	// Bit mask of TIMER1_STOP_INT_ENA field.
	MCPWM_INT_ENA_TIMER1_STOP_INT_ENA_Msk = 0x2
	// Bit TIMER1_STOP_INT_ENA.
	MCPWM_INT_ENA_TIMER1_STOP_INT_ENA = 0x2
	// Position of TIMER2_STOP_INT_ENA field.
	MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Pos = 0x2
	// Bit mask of TIMER2_STOP_INT_ENA field.
	MCPWM_INT_ENA_TIMER2_STOP_INT_ENA_Msk = 0x4
	// Bit TIMER2_STOP_INT_ENA.
	MCPWM_INT_ENA_TIMER2_STOP_INT_ENA = 0x4
	// Position of TIMER0_TEZ_INT_ENA field.
	MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Pos = 0x3
	// Bit mask of TIMER0_TEZ_INT_ENA field.
	MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA_Msk = 0x8
	// Bit TIMER0_TEZ_INT_ENA.
	MCPWM_INT_ENA_TIMER0_TEZ_INT_ENA = 0x8
	// Position of TIMER1_TEZ_INT_ENA field.
	MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Pos = 0x4
	// Bit mask of TIMER1_TEZ_INT_ENA field.
	MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA_Msk = 0x10
	// Bit TIMER1_TEZ_INT_ENA.
	MCPWM_INT_ENA_TIMER1_TEZ_INT_ENA = 0x10
	// Position of TIMER2_TEZ_INT_ENA field.
	MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Pos = 0x5
	// Bit mask of TIMER2_TEZ_INT_ENA field.
	MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA_Msk = 0x20
	// Bit TIMER2_TEZ_INT_ENA.
	MCPWM_INT_ENA_TIMER2_TEZ_INT_ENA = 0x20
	// Position of TIMER0_TEP_INT_ENA field.
	MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Pos = 0x6
	// Bit mask of TIMER0_TEP_INT_ENA field.
	MCPWM_INT_ENA_TIMER0_TEP_INT_ENA_Msk = 0x40
	// Bit TIMER0_TEP_INT_ENA.
	MCPWM_INT_ENA_TIMER0_TEP_INT_ENA = 0x40
	// Position of TIMER1_TEP_INT_ENA field.
	MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Pos = 0x7
	// Bit mask of TIMER1_TEP_INT_ENA field.
	MCPWM_INT_ENA_TIMER1_TEP_INT_ENA_Msk = 0x80
	// Bit TIMER1_TEP_INT_ENA.
	MCPWM_INT_ENA_TIMER1_TEP_INT_ENA = 0x80
	// Position of TIMER2_TEP_INT_ENA field.
	MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Pos = 0x8
	// Bit mask of TIMER2_TEP_INT_ENA field.
	MCPWM_INT_ENA_TIMER2_TEP_INT_ENA_Msk = 0x100
	// Bit TIMER2_TEP_INT_ENA.
	MCPWM_INT_ENA_TIMER2_TEP_INT_ENA = 0x100
	// Position of FAULT0_INT_ENA field.
	MCPWM_INT_ENA_FAULT0_INT_ENA_Pos = 0x9
	// Bit mask of FAULT0_INT_ENA field.
	MCPWM_INT_ENA_FAULT0_INT_ENA_Msk = 0x200
	// Bit FAULT0_INT_ENA.
	MCPWM_INT_ENA_FAULT0_INT_ENA = 0x200
	// Position of FAULT1_INT_ENA field.
	MCPWM_INT_ENA_FAULT1_INT_ENA_Pos = 0xa
	// Bit mask of FAULT1_INT_ENA field.
	MCPWM_INT_ENA_FAULT1_INT_ENA_Msk = 0x400
	// Bit FAULT1_INT_ENA.
	MCPWM_INT_ENA_FAULT1_INT_ENA = 0x400
	// Position of FAULT2_INT_ENA field.
	MCPWM_INT_ENA_FAULT2_INT_ENA_Pos = 0xb
	// Bit mask of FAULT2_INT_ENA field.
	MCPWM_INT_ENA_FAULT2_INT_ENA_Msk = 0x800
	// Bit FAULT2_INT_ENA.
	MCPWM_INT_ENA_FAULT2_INT_ENA = 0x800
	// Position of FAULT0_CLR_INT_ENA field.
	MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Pos = 0xc
	// Bit mask of FAULT0_CLR_INT_ENA field.
	MCPWM_INT_ENA_FAULT0_CLR_INT_ENA_Msk = 0x1000
	// Bit FAULT0_CLR_INT_ENA.
	MCPWM_INT_ENA_FAULT0_CLR_INT_ENA = 0x1000
	// Position of FAULT1_CLR_INT_ENA field.
	MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Pos = 0xd
	// Bit mask of FAULT1_CLR_INT_ENA field.
	MCPWM_INT_ENA_FAULT1_CLR_INT_ENA_Msk = 0x2000
	// Bit FAULT1_CLR_INT_ENA.
	MCPWM_INT_ENA_FAULT1_CLR_INT_ENA = 0x2000
	// Position of FAULT2_CLR_INT_ENA field.
	MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Pos = 0xe
	// Bit mask of FAULT2_CLR_INT_ENA field.
	MCPWM_INT_ENA_FAULT2_CLR_INT_ENA_Msk = 0x4000
	// Bit FAULT2_CLR_INT_ENA.
	MCPWM_INT_ENA_FAULT2_CLR_INT_ENA = 0x4000
	// Position of CMPR0_TEA_INT_ENA field.
	MCPWM_INT_ENA_CMPR0_TEA_INT_ENA_Pos = 0xf
	// Bit mask of CMPR0_TEA_INT_ENA field.
	MCPWM_INT_ENA_CMPR0_TEA_INT_ENA_Msk = 0x8000
	// Bit CMPR0_TEA_INT_ENA.
	MCPWM_INT_ENA_CMPR0_TEA_INT_ENA = 0x8000
	// Position of CMPR1_TEA_INT_ENA field.
	MCPWM_INT_ENA_CMPR1_TEA_INT_ENA_Pos = 0x10
	// Bit mask of CMPR1_TEA_INT_ENA field.
	MCPWM_INT_ENA_CMPR1_TEA_INT_ENA_Msk = 0x10000
	// Bit CMPR1_TEA_INT_ENA.
	MCPWM_INT_ENA_CMPR1_TEA_INT_ENA = 0x10000
	// Position of CMPR2_TEA_INT_ENA field.
	MCPWM_INT_ENA_CMPR2_TEA_INT_ENA_Pos = 0x11
	// Bit mask of CMPR2_TEA_INT_ENA field.
	MCPWM_INT_ENA_CMPR2_TEA_INT_ENA_Msk = 0x20000
	// Bit CMPR2_TEA_INT_ENA.
	MCPWM_INT_ENA_CMPR2_TEA_INT_ENA = 0x20000
	// Position of CMPR0_TEB_INT_ENA field.
	MCPWM_INT_ENA_CMPR0_TEB_INT_ENA_Pos = 0x12
	// Bit mask of CMPR0_TEB_INT_ENA field.
	MCPWM_INT_ENA_CMPR0_TEB_INT_ENA_Msk = 0x40000
	// Bit CMPR0_TEB_INT_ENA.
	MCPWM_INT_ENA_CMPR0_TEB_INT_ENA = 0x40000
	// Position of CMPR1_TEB_INT_ENA field.
	MCPWM_INT_ENA_CMPR1_TEB_INT_ENA_Pos = 0x13
	// Bit mask of CMPR1_TEB_INT_ENA field.
	MCPWM_INT_ENA_CMPR1_TEB_INT_ENA_Msk = 0x80000
	// Bit CMPR1_TEB_INT_ENA.
	MCPWM_INT_ENA_CMPR1_TEB_INT_ENA = 0x80000
	// Position of CMPR2_TEB_INT_ENA field.
	MCPWM_INT_ENA_CMPR2_TEB_INT_ENA_Pos = 0x14
	// Bit mask of CMPR2_TEB_INT_ENA field.
	MCPWM_INT_ENA_CMPR2_TEB_INT_ENA_Msk = 0x100000
	// Bit CMPR2_TEB_INT_ENA.
	MCPWM_INT_ENA_CMPR2_TEB_INT_ENA = 0x100000
	// Position of TZ0_CBC_INT_ENA field.
	MCPWM_INT_ENA_TZ0_CBC_INT_ENA_Pos = 0x15
	// Bit mask of TZ0_CBC_INT_ENA field.
	MCPWM_INT_ENA_TZ0_CBC_INT_ENA_Msk = 0x200000
	// Bit TZ0_CBC_INT_ENA.
	MCPWM_INT_ENA_TZ0_CBC_INT_ENA = 0x200000
	// Position of TZ1_CBC_INT_ENA field.
	MCPWM_INT_ENA_TZ1_CBC_INT_ENA_Pos = 0x16
	// Bit mask of TZ1_CBC_INT_ENA field.
	MCPWM_INT_ENA_TZ1_CBC_INT_ENA_Msk = 0x400000
	// Bit TZ1_CBC_INT_ENA.
	MCPWM_INT_ENA_TZ1_CBC_INT_ENA = 0x400000
	// Position of TZ2_CBC_INT_ENA field.
	MCPWM_INT_ENA_TZ2_CBC_INT_ENA_Pos = 0x17
	// Bit mask of TZ2_CBC_INT_ENA field.
	MCPWM_INT_ENA_TZ2_CBC_INT_ENA_Msk = 0x800000
	// Bit TZ2_CBC_INT_ENA.
	MCPWM_INT_ENA_TZ2_CBC_INT_ENA = 0x800000
	// Position of TZ0_OST_INT_ENA field.
	MCPWM_INT_ENA_TZ0_OST_INT_ENA_Pos = 0x18
	// Bit mask of TZ0_OST_INT_ENA field.
	MCPWM_INT_ENA_TZ0_OST_INT_ENA_Msk = 0x1000000
	// Bit TZ0_OST_INT_ENA.
	MCPWM_INT_ENA_TZ0_OST_INT_ENA = 0x1000000
	// Position of TZ1_OST_INT_ENA field.
	MCPWM_INT_ENA_TZ1_OST_INT_ENA_Pos = 0x19
	// Bit mask of TZ1_OST_INT_ENA field.
	MCPWM_INT_ENA_TZ1_OST_INT_ENA_Msk = 0x2000000
	// Bit TZ1_OST_INT_ENA.
	MCPWM_INT_ENA_TZ1_OST_INT_ENA = 0x2000000
	// Position of TZ2_OST_INT_ENA field.
	MCPWM_INT_ENA_TZ2_OST_INT_ENA_Pos = 0x1a
	// Bit mask of TZ2_OST_INT_ENA field.
	MCPWM_INT_ENA_TZ2_OST_INT_ENA_Msk = 0x4000000
	// Bit TZ2_OST_INT_ENA.
	MCPWM_INT_ENA_TZ2_OST_INT_ENA = 0x4000000
	// Position of CAP0_INT_ENA field.
	MCPWM_INT_ENA_CAP0_INT_ENA_Pos = 0x1b
	// Bit mask of CAP0_INT_ENA field.
	MCPWM_INT_ENA_CAP0_INT_ENA_Msk = 0x8000000
	// Bit CAP0_INT_ENA.
	MCPWM_INT_ENA_CAP0_INT_ENA = 0x8000000
	// Position of CAP1_INT_ENA field.
	MCPWM_INT_ENA_CAP1_INT_ENA_Pos = 0x1c
	// Bit mask of CAP1_INT_ENA field.
	MCPWM_INT_ENA_CAP1_INT_ENA_Msk = 0x10000000
	// Bit CAP1_INT_ENA.
	MCPWM_INT_ENA_CAP1_INT_ENA = 0x10000000
	// Position of CAP2_INT_ENA field.
	MCPWM_INT_ENA_CAP2_INT_ENA_Pos = 0x1d
	// Bit mask of CAP2_INT_ENA field.
	MCPWM_INT_ENA_CAP2_INT_ENA_Msk = 0x20000000
	// Bit CAP2_INT_ENA.
	MCPWM_INT_ENA_CAP2_INT_ENA = 0x20000000

	// INT_RAW: Interrupt raw status register
	// Position of TIMER0_STOP_INT_RAW field.
	MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Pos = 0x0
	// Bit mask of TIMER0_STOP_INT_RAW field.
	MCPWM_INT_RAW_TIMER0_STOP_INT_RAW_Msk = 0x1
	// Bit TIMER0_STOP_INT_RAW.
	MCPWM_INT_RAW_TIMER0_STOP_INT_RAW = 0x1
	// Position of TIMER1_STOP_INT_RAW field.
	MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Pos = 0x1
	// Bit mask of TIMER1_STOP_INT_RAW field.
	MCPWM_INT_RAW_TIMER1_STOP_INT_RAW_Msk = 0x2
	// Bit TIMER1_STOP_INT_RAW.
	MCPWM_INT_RAW_TIMER1_STOP_INT_RAW = 0x2
	// Position of TIMER2_STOP_INT_RAW field.
	MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Pos = 0x2
	// Bit mask of TIMER2_STOP_INT_RAW field.
	MCPWM_INT_RAW_TIMER2_STOP_INT_RAW_Msk = 0x4
	// Bit TIMER2_STOP_INT_RAW.
	MCPWM_INT_RAW_TIMER2_STOP_INT_RAW = 0x4
	// Position of TIMER0_TEZ_INT_RAW field.
	MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Pos = 0x3
	// Bit mask of TIMER0_TEZ_INT_RAW field.
	MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW_Msk = 0x8
	// Bit TIMER0_TEZ_INT_RAW.
	MCPWM_INT_RAW_TIMER0_TEZ_INT_RAW = 0x8
	// Position of TIMER1_TEZ_INT_RAW field.
	MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Pos = 0x4
	// Bit mask of TIMER1_TEZ_INT_RAW field.
	MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW_Msk = 0x10
	// Bit TIMER1_TEZ_INT_RAW.
	MCPWM_INT_RAW_TIMER1_TEZ_INT_RAW = 0x10
	// Position of TIMER2_TEZ_INT_RAW field.
	MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Pos = 0x5
	// Bit mask of TIMER2_TEZ_INT_RAW field.
	MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW_Msk = 0x20
	// Bit TIMER2_TEZ_INT_RAW.
	MCPWM_INT_RAW_TIMER2_TEZ_INT_RAW = 0x20
	// Position of TIMER0_TEP_INT_RAW field.
	MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Pos = 0x6
	// Bit mask of TIMER0_TEP_INT_RAW field.
	MCPWM_INT_RAW_TIMER0_TEP_INT_RAW_Msk = 0x40
	// Bit TIMER0_TEP_INT_RAW.
	MCPWM_INT_RAW_TIMER0_TEP_INT_RAW = 0x40
	// Position of TIMER1_TEP_INT_RAW field.
	MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Pos = 0x7
	// Bit mask of TIMER1_TEP_INT_RAW field.
	MCPWM_INT_RAW_TIMER1_TEP_INT_RAW_Msk = 0x80
	// Bit TIMER1_TEP_INT_RAW.
	MCPWM_INT_RAW_TIMER1_TEP_INT_RAW = 0x80
	// Position of TIMER2_TEP_INT_RAW field.
	MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Pos = 0x8
	// Bit mask of TIMER2_TEP_INT_RAW field.
	MCPWM_INT_RAW_TIMER2_TEP_INT_RAW_Msk = 0x100
	// Bit TIMER2_TEP_INT_RAW.
	MCPWM_INT_RAW_TIMER2_TEP_INT_RAW = 0x100
	// Position of FAULT0_INT_RAW field.
	MCPWM_INT_RAW_FAULT0_INT_RAW_Pos = 0x9
	// Bit mask of FAULT0_INT_RAW field.
	MCPWM_INT_RAW_FAULT0_INT_RAW_Msk = 0x200
	// Bit FAULT0_INT_RAW.
	MCPWM_INT_RAW_FAULT0_INT_RAW = 0x200
	// Position of FAULT1_INT_RAW field.
	MCPWM_INT_RAW_FAULT1_INT_RAW_Pos = 0xa
	// Bit mask of FAULT1_INT_RAW field.
	MCPWM_INT_RAW_FAULT1_INT_RAW_Msk = 0x400
	// Bit FAULT1_INT_RAW.
	MCPWM_INT_RAW_FAULT1_INT_RAW = 0x400
	// Position of FAULT2_INT_RAW field.
	MCPWM_INT_RAW_FAULT2_INT_RAW_Pos = 0xb
	// Bit mask of FAULT2_INT_RAW field.
	MCPWM_INT_RAW_FAULT2_INT_RAW_Msk = 0x800
	// Bit FAULT2_INT_RAW.
	MCPWM_INT_RAW_FAULT2_INT_RAW = 0x800
	// Position of FAULT0_CLR_INT_RAW field.
	MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Pos = 0xc
	// Bit mask of FAULT0_CLR_INT_RAW field.
	MCPWM_INT_RAW_FAULT0_CLR_INT_RAW_Msk = 0x1000
	// Bit FAULT0_CLR_INT_RAW.
	MCPWM_INT_RAW_FAULT0_CLR_INT_RAW = 0x1000
	// Position of FAULT1_CLR_INT_RAW field.
	MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Pos = 0xd
	// Bit mask of FAULT1_CLR_INT_RAW field.
	MCPWM_INT_RAW_FAULT1_CLR_INT_RAW_Msk = 0x2000
	// Bit FAULT1_CLR_INT_RAW.
	MCPWM_INT_RAW_FAULT1_CLR_INT_RAW = 0x2000
	// Position of FAULT2_CLR_INT_RAW field.
	MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Pos = 0xe
	// Bit mask of FAULT2_CLR_INT_RAW field.
	MCPWM_INT_RAW_FAULT2_CLR_INT_RAW_Msk = 0x4000
	// Bit FAULT2_CLR_INT_RAW.
	MCPWM_INT_RAW_FAULT2_CLR_INT_RAW = 0x4000
	// Position of CMPR0_TEA_INT_RAW field.
	MCPWM_INT_RAW_CMPR0_TEA_INT_RAW_Pos = 0xf
	// Bit mask of CMPR0_TEA_INT_RAW field.
	MCPWM_INT_RAW_CMPR0_TEA_INT_RAW_Msk = 0x8000
	// Bit CMPR0_TEA_INT_RAW.
	MCPWM_INT_RAW_CMPR0_TEA_INT_RAW = 0x8000
	// Position of CMPR1_TEA_INT_RAW field.
	MCPWM_INT_RAW_CMPR1_TEA_INT_RAW_Pos = 0x10
	// Bit mask of CMPR1_TEA_INT_RAW field.
	MCPWM_INT_RAW_CMPR1_TEA_INT_RAW_Msk = 0x10000
	// Bit CMPR1_TEA_INT_RAW.
	MCPWM_INT_RAW_CMPR1_TEA_INT_RAW = 0x10000
	// Position of CMPR2_TEA_INT_RAW field.
	MCPWM_INT_RAW_CMPR2_TEA_INT_RAW_Pos = 0x11
	// Bit mask of CMPR2_TEA_INT_RAW field.
	MCPWM_INT_RAW_CMPR2_TEA_INT_RAW_Msk = 0x20000
	// Bit CMPR2_TEA_INT_RAW.
	MCPWM_INT_RAW_CMPR2_TEA_INT_RAW = 0x20000
	// Position of CMPR0_TEB_INT_RAW field.
	MCPWM_INT_RAW_CMPR0_TEB_INT_RAW_Pos = 0x12
	// Bit mask of CMPR0_TEB_INT_RAW field.
	MCPWM_INT_RAW_CMPR0_TEB_INT_RAW_Msk = 0x40000
	// Bit CMPR0_TEB_INT_RAW.
	MCPWM_INT_RAW_CMPR0_TEB_INT_RAW = 0x40000
	// Position of CMPR1_TEB_INT_RAW field.
	MCPWM_INT_RAW_CMPR1_TEB_INT_RAW_Pos = 0x13
	// Bit mask of CMPR1_TEB_INT_RAW field.
	MCPWM_INT_RAW_CMPR1_TEB_INT_RAW_Msk = 0x80000
	// Bit CMPR1_TEB_INT_RAW.
	MCPWM_INT_RAW_CMPR1_TEB_INT_RAW = 0x80000
	// Position of CMPR2_TEB_INT_RAW field.
	MCPWM_INT_RAW_CMPR2_TEB_INT_RAW_Pos = 0x14
	// Bit mask of CMPR2_TEB_INT_RAW field.
	MCPWM_INT_RAW_CMPR2_TEB_INT_RAW_Msk = 0x100000
	// Bit CMPR2_TEB_INT_RAW.
	MCPWM_INT_RAW_CMPR2_TEB_INT_RAW = 0x100000
	// Position of TZ0_CBC_INT_RAW field.
	MCPWM_INT_RAW_TZ0_CBC_INT_RAW_Pos = 0x15
	// Bit mask of TZ0_CBC_INT_RAW field.
	MCPWM_INT_RAW_TZ0_CBC_INT_RAW_Msk = 0x200000
	// Bit TZ0_CBC_INT_RAW.
	MCPWM_INT_RAW_TZ0_CBC_INT_RAW = 0x200000
	// Position of TZ1_CBC_INT_RAW field.
	MCPWM_INT_RAW_TZ1_CBC_INT_RAW_Pos = 0x16
	// Bit mask of TZ1_CBC_INT_RAW field.
	MCPWM_INT_RAW_TZ1_CBC_INT_RAW_Msk = 0x400000
	// Bit TZ1_CBC_INT_RAW.
	MCPWM_INT_RAW_TZ1_CBC_INT_RAW = 0x400000
	// Position of TZ2_CBC_INT_RAW field.
	MCPWM_INT_RAW_TZ2_CBC_INT_RAW_Pos = 0x17
	// Bit mask of TZ2_CBC_INT_RAW field.
	MCPWM_INT_RAW_TZ2_CBC_INT_RAW_Msk = 0x800000
	// Bit TZ2_CBC_INT_RAW.
	MCPWM_INT_RAW_TZ2_CBC_INT_RAW = 0x800000
	// Position of TZ0_OST_INT_RAW field.
	MCPWM_INT_RAW_TZ0_OST_INT_RAW_Pos = 0x18
	// Bit mask of TZ0_OST_INT_RAW field.
	MCPWM_INT_RAW_TZ0_OST_INT_RAW_Msk = 0x1000000
	// Bit TZ0_OST_INT_RAW.
	MCPWM_INT_RAW_TZ0_OST_INT_RAW = 0x1000000
	// Position of TZ1_OST_INT_RAW field.
	MCPWM_INT_RAW_TZ1_OST_INT_RAW_Pos = 0x19
	// Bit mask of TZ1_OST_INT_RAW field.
	MCPWM_INT_RAW_TZ1_OST_INT_RAW_Msk = 0x2000000
	// Bit TZ1_OST_INT_RAW.
	MCPWM_INT_RAW_TZ1_OST_INT_RAW = 0x2000000
	// Position of TZ2_OST_INT_RAW field.
	MCPWM_INT_RAW_TZ2_OST_INT_RAW_Pos = 0x1a
	// Bit mask of TZ2_OST_INT_RAW field.
	MCPWM_INT_RAW_TZ2_OST_INT_RAW_Msk = 0x4000000
	// Bit TZ2_OST_INT_RAW.
	MCPWM_INT_RAW_TZ2_OST_INT_RAW = 0x4000000
	// Position of CAP0_INT_RAW field.
	MCPWM_INT_RAW_CAP0_INT_RAW_Pos = 0x1b
	// Bit mask of CAP0_INT_RAW field.
	MCPWM_INT_RAW_CAP0_INT_RAW_Msk = 0x8000000
	// Bit CAP0_INT_RAW.
	MCPWM_INT_RAW_CAP0_INT_RAW = 0x8000000
	// Position of CAP1_INT_RAW field.
	MCPWM_INT_RAW_CAP1_INT_RAW_Pos = 0x1c
	// Bit mask of CAP1_INT_RAW field.
	MCPWM_INT_RAW_CAP1_INT_RAW_Msk = 0x10000000
	// Bit CAP1_INT_RAW.
	MCPWM_INT_RAW_CAP1_INT_RAW = 0x10000000
	// Position of CAP2_INT_RAW field.
	MCPWM_INT_RAW_CAP2_INT_RAW_Pos = 0x1d
	// Bit mask of CAP2_INT_RAW field.
	MCPWM_INT_RAW_CAP2_INT_RAW_Msk = 0x20000000
	// Bit CAP2_INT_RAW.
	MCPWM_INT_RAW_CAP2_INT_RAW = 0x20000000

	// INT_ST: Interrupt masked status register
	// Position of TIMER0_STOP_INT_ST field.
	MCPWM_INT_ST_TIMER0_STOP_INT_ST_Pos = 0x0
	// Bit mask of TIMER0_STOP_INT_ST field.
	MCPWM_INT_ST_TIMER0_STOP_INT_ST_Msk = 0x1
	// Bit TIMER0_STOP_INT_ST.
	MCPWM_INT_ST_TIMER0_STOP_INT_ST = 0x1
	// Position of TIMER1_STOP_INT_ST field.
	MCPWM_INT_ST_TIMER1_STOP_INT_ST_Pos = 0x1
	// Bit mask of TIMER1_STOP_INT_ST field.
	MCPWM_INT_ST_TIMER1_STOP_INT_ST_Msk = 0x2
	// Bit TIMER1_STOP_INT_ST.
	MCPWM_INT_ST_TIMER1_STOP_INT_ST = 0x2
	// Position of TIMER2_STOP_INT_ST field.
	MCPWM_INT_ST_TIMER2_STOP_INT_ST_Pos = 0x2
	// Bit mask of TIMER2_STOP_INT_ST field.
	MCPWM_INT_ST_TIMER2_STOP_INT_ST_Msk = 0x4
	// Bit TIMER2_STOP_INT_ST.
	MCPWM_INT_ST_TIMER2_STOP_INT_ST = 0x4
	// Position of TIMER0_TEZ_INT_ST field.
	MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Pos = 0x3
	// Bit mask of TIMER0_TEZ_INT_ST field.
	MCPWM_INT_ST_TIMER0_TEZ_INT_ST_Msk = 0x8
	// Bit TIMER0_TEZ_INT_ST.
	MCPWM_INT_ST_TIMER0_TEZ_INT_ST = 0x8
	// Position of TIMER1_TEZ_INT_ST field.
	MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Pos = 0x4
	// Bit mask of TIMER1_TEZ_INT_ST field.
	MCPWM_INT_ST_TIMER1_TEZ_INT_ST_Msk = 0x10
	// Bit TIMER1_TEZ_INT_ST.
	MCPWM_INT_ST_TIMER1_TEZ_INT_ST = 0x10
	// Position of TIMER2_TEZ_INT_ST field.
	MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Pos = 0x5
	// Bit mask of TIMER2_TEZ_INT_ST field.
	MCPWM_INT_ST_TIMER2_TEZ_INT_ST_Msk = 0x20
	// Bit TIMER2_TEZ_INT_ST.
	MCPWM_INT_ST_TIMER2_TEZ_INT_ST = 0x20
	// Position of TIMER0_TEP_INT_ST field.
	MCPWM_INT_ST_TIMER0_TEP_INT_ST_Pos = 0x6
	// Bit mask of TIMER0_TEP_INT_ST field.
	MCPWM_INT_ST_TIMER0_TEP_INT_ST_Msk = 0x40
	// Bit TIMER0_TEP_INT_ST.
	MCPWM_INT_ST_TIMER0_TEP_INT_ST = 0x40
	// Position of TIMER1_TEP_INT_ST field.
	MCPWM_INT_ST_TIMER1_TEP_INT_ST_Pos = 0x7
	// Bit mask of TIMER1_TEP_INT_ST field.
	MCPWM_INT_ST_TIMER1_TEP_INT_ST_Msk = 0x80
	// Bit TIMER1_TEP_INT_ST.
	MCPWM_INT_ST_TIMER1_TEP_INT_ST = 0x80
	// Position of TIMER2_TEP_INT_ST field.
	MCPWM_INT_ST_TIMER2_TEP_INT_ST_Pos = 0x8
	// Bit mask of TIMER2_TEP_INT_ST field.
	MCPWM_INT_ST_TIMER2_TEP_INT_ST_Msk = 0x100
	// Bit TIMER2_TEP_INT_ST.
	MCPWM_INT_ST_TIMER2_TEP_INT_ST = 0x100
	// Position of FAULT0_INT_ST field.
	MCPWM_INT_ST_FAULT0_INT_ST_Pos = 0x9
	// Bit mask of FAULT0_INT_ST field.
	MCPWM_INT_ST_FAULT0_INT_ST_Msk = 0x200
	// Bit FAULT0_INT_ST.
	MCPWM_INT_ST_FAULT0_INT_ST = 0x200
	// Position of FAULT1_INT_ST field.
	MCPWM_INT_ST_FAULT1_INT_ST_Pos = 0xa
	// Bit mask of FAULT1_INT_ST field.
	MCPWM_INT_ST_FAULT1_INT_ST_Msk = 0x400
	// Bit FAULT1_INT_ST.
	MCPWM_INT_ST_FAULT1_INT_ST = 0x400
	// Position of FAULT2_INT_ST field.
	MCPWM_INT_ST_FAULT2_INT_ST_Pos = 0xb
	// Bit mask of FAULT2_INT_ST field.
	MCPWM_INT_ST_FAULT2_INT_ST_Msk = 0x800
	// Bit FAULT2_INT_ST.
	MCPWM_INT_ST_FAULT2_INT_ST = 0x800
	// Position of FAULT0_CLR_INT_ST field.
	MCPWM_INT_ST_FAULT0_CLR_INT_ST_Pos = 0xc
	// Bit mask of FAULT0_CLR_INT_ST field.
	MCPWM_INT_ST_FAULT0_CLR_INT_ST_Msk = 0x1000
	// Bit FAULT0_CLR_INT_ST.
	MCPWM_INT_ST_FAULT0_CLR_INT_ST = 0x1000
	// Position of FAULT1_CLR_INT_ST field.
	MCPWM_INT_ST_FAULT1_CLR_INT_ST_Pos = 0xd
	// Bit mask of FAULT1_CLR_INT_ST field.
	MCPWM_INT_ST_FAULT1_CLR_INT_ST_Msk = 0x2000
	// Bit FAULT1_CLR_INT_ST.
	MCPWM_INT_ST_FAULT1_CLR_INT_ST = 0x2000
	// Position of FAULT2_CLR_INT_ST field.
	MCPWM_INT_ST_FAULT2_CLR_INT_ST_Pos = 0xe
	// Bit mask of FAULT2_CLR_INT_ST field.
	MCPWM_INT_ST_FAULT2_CLR_INT_ST_Msk = 0x4000
	// Bit FAULT2_CLR_INT_ST.
	MCPWM_INT_ST_FAULT2_CLR_INT_ST = 0x4000
	// Position of CMPR0_TEA_INT_ST field.
	MCPWM_INT_ST_CMPR0_TEA_INT_ST_Pos = 0xf
	// Bit mask of CMPR0_TEA_INT_ST field.
	MCPWM_INT_ST_CMPR0_TEA_INT_ST_Msk = 0x8000
	// Bit CMPR0_TEA_INT_ST.
	MCPWM_INT_ST_CMPR0_TEA_INT_ST = 0x8000
	// Position of CMPR1_TEA_INT_ST field.
	MCPWM_INT_ST_CMPR1_TEA_INT_ST_Pos = 0x10
	// Bit mask of CMPR1_TEA_INT_ST field.
	MCPWM_INT_ST_CMPR1_TEA_INT_ST_Msk = 0x10000
	// Bit CMPR1_TEA_INT_ST.
	MCPWM_INT_ST_CMPR1_TEA_INT_ST = 0x10000
	// Position of CMPR2_TEA_INT_ST field.
	MCPWM_INT_ST_CMPR2_TEA_INT_ST_Pos = 0x11
	// Bit mask of CMPR2_TEA_INT_ST field.
	MCPWM_INT_ST_CMPR2_TEA_INT_ST_Msk = 0x20000
	// Bit CMPR2_TEA_INT_ST.
	MCPWM_INT_ST_CMPR2_TEA_INT_ST = 0x20000
	// Position of CMPR0_TEB_INT_ST field.
	MCPWM_INT_ST_CMPR0_TEB_INT_ST_Pos = 0x12
	// Bit mask of CMPR0_TEB_INT_ST field.
	MCPWM_INT_ST_CMPR0_TEB_INT_ST_Msk = 0x40000
	// Bit CMPR0_TEB_INT_ST.
	MCPWM_INT_ST_CMPR0_TEB_INT_ST = 0x40000
	// Position of CMPR1_TEB_INT_ST field.
	MCPWM_INT_ST_CMPR1_TEB_INT_ST_Pos = 0x13
	// Bit mask of CMPR1_TEB_INT_ST field.
	MCPWM_INT_ST_CMPR1_TEB_INT_ST_Msk = 0x80000
	// Bit CMPR1_TEB_INT_ST.
	MCPWM_INT_ST_CMPR1_TEB_INT_ST = 0x80000
	// Position of CMPR2_TEB_INT_ST field.
	MCPWM_INT_ST_CMPR2_TEB_INT_ST_Pos = 0x14
	// Bit mask of CMPR2_TEB_INT_ST field.
	MCPWM_INT_ST_CMPR2_TEB_INT_ST_Msk = 0x100000
	// Bit CMPR2_TEB_INT_ST.
	MCPWM_INT_ST_CMPR2_TEB_INT_ST = 0x100000
	// Position of TZ0_CBC_INT_ST field.
	MCPWM_INT_ST_TZ0_CBC_INT_ST_Pos = 0x15
	// Bit mask of TZ0_CBC_INT_ST field.
	MCPWM_INT_ST_TZ0_CBC_INT_ST_Msk = 0x200000
	// Bit TZ0_CBC_INT_ST.
	MCPWM_INT_ST_TZ0_CBC_INT_ST = 0x200000
	// Position of TZ1_CBC_INT_ST field.
	MCPWM_INT_ST_TZ1_CBC_INT_ST_Pos = 0x16
	// Bit mask of TZ1_CBC_INT_ST field.
	MCPWM_INT_ST_TZ1_CBC_INT_ST_Msk = 0x400000
	// Bit TZ1_CBC_INT_ST.
	MCPWM_INT_ST_TZ1_CBC_INT_ST = 0x400000
	// Position of TZ2_CBC_INT_ST field.
	MCPWM_INT_ST_TZ2_CBC_INT_ST_Pos = 0x17
	// Bit mask of TZ2_CBC_INT_ST field.
	MCPWM_INT_ST_TZ2_CBC_INT_ST_Msk = 0x800000
	// Bit TZ2_CBC_INT_ST.
	MCPWM_INT_ST_TZ2_CBC_INT_ST = 0x800000
	// Position of TZ0_OST_INT_ST field.
	MCPWM_INT_ST_TZ0_OST_INT_ST_Pos = 0x18
	// Bit mask of TZ0_OST_INT_ST field.
	MCPWM_INT_ST_TZ0_OST_INT_ST_Msk = 0x1000000
	// Bit TZ0_OST_INT_ST.
	MCPWM_INT_ST_TZ0_OST_INT_ST = 0x1000000
	// Position of TZ1_OST_INT_ST field.
	MCPWM_INT_ST_TZ1_OST_INT_ST_Pos = 0x19
	// Bit mask of TZ1_OST_INT_ST field.
	MCPWM_INT_ST_TZ1_OST_INT_ST_Msk = 0x2000000
	// Bit TZ1_OST_INT_ST.
	MCPWM_INT_ST_TZ1_OST_INT_ST = 0x2000000
	// Position of TZ2_OST_INT_ST field.
	MCPWM_INT_ST_TZ2_OST_INT_ST_Pos = 0x1a
	// Bit mask of TZ2_OST_INT_ST field.
	MCPWM_INT_ST_TZ2_OST_INT_ST_Msk = 0x4000000
	// Bit TZ2_OST_INT_ST.
	MCPWM_INT_ST_TZ2_OST_INT_ST = 0x4000000
	// Position of CAP0_INT_ST field.
	MCPWM_INT_ST_CAP0_INT_ST_Pos = 0x1b
	// Bit mask of CAP0_INT_ST field.
	MCPWM_INT_ST_CAP0_INT_ST_Msk = 0x8000000
	// Bit CAP0_INT_ST.
	MCPWM_INT_ST_CAP0_INT_ST = 0x8000000
	// Position of CAP1_INT_ST field.
	MCPWM_INT_ST_CAP1_INT_ST_Pos = 0x1c
	// Bit mask of CAP1_INT_ST field.
	MCPWM_INT_ST_CAP1_INT_ST_Msk = 0x10000000
	// Bit CAP1_INT_ST.
	MCPWM_INT_ST_CAP1_INT_ST = 0x10000000
	// Position of CAP2_INT_ST field.
	MCPWM_INT_ST_CAP2_INT_ST_Pos = 0x1d
	// Bit mask of CAP2_INT_ST field.
	MCPWM_INT_ST_CAP2_INT_ST_Msk = 0x20000000
	// Bit CAP2_INT_ST.
	MCPWM_INT_ST_CAP2_INT_ST = 0x20000000

	// INT_CLR: Interrupt clear register
	// Position of TIMER0_STOP_INT_CLR field.
	MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Pos = 0x0
	// Bit mask of TIMER0_STOP_INT_CLR field.
	MCPWM_INT_CLR_TIMER0_STOP_INT_CLR_Msk = 0x1
	// Bit TIMER0_STOP_INT_CLR.
	MCPWM_INT_CLR_TIMER0_STOP_INT_CLR = 0x1
	// Position of TIMER1_STOP_INT_CLR field.
	MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Pos = 0x1
	// Bit mask of TIMER1_STOP_INT_CLR field.
	MCPWM_INT_CLR_TIMER1_STOP_INT_CLR_Msk = 0x2
	// Bit TIMER1_STOP_INT_CLR.
	MCPWM_INT_CLR_TIMER1_STOP_INT_CLR = 0x2
	// Position of TIMER2_STOP_INT_CLR field.
	MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Pos = 0x2
	// Bit mask of TIMER2_STOP_INT_CLR field.
	MCPWM_INT_CLR_TIMER2_STOP_INT_CLR_Msk = 0x4
	// Bit TIMER2_STOP_INT_CLR.
	MCPWM_INT_CLR_TIMER2_STOP_INT_CLR = 0x4
	// Position of TIMER0_TEZ_INT_CLR field.
	MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Pos = 0x3
	// Bit mask of TIMER0_TEZ_INT_CLR field.
	MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR_Msk = 0x8
	// Bit TIMER0_TEZ_INT_CLR.
	MCPWM_INT_CLR_TIMER0_TEZ_INT_CLR = 0x8
	// Position of TIMER1_TEZ_INT_CLR field.
	MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Pos = 0x4
	// Bit mask of TIMER1_TEZ_INT_CLR field.
	MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR_Msk = 0x10
	// Bit TIMER1_TEZ_INT_CLR.
	MCPWM_INT_CLR_TIMER1_TEZ_INT_CLR = 0x10
	// Position of TIMER2_TEZ_INT_CLR field.
	MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Pos = 0x5
	// Bit mask of TIMER2_TEZ_INT_CLR field.
	MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR_Msk = 0x20
	// Bit TIMER2_TEZ_INT_CLR.
	MCPWM_INT_CLR_TIMER2_TEZ_INT_CLR = 0x20
	// Position of TIMER0_TEP_INT_CLR field.
	MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Pos = 0x6
	// Bit mask of TIMER0_TEP_INT_CLR field.
	MCPWM_INT_CLR_TIMER0_TEP_INT_CLR_Msk = 0x40
	// Bit TIMER0_TEP_INT_CLR.
	MCPWM_INT_CLR_TIMER0_TEP_INT_CLR = 0x40
	// Position of TIMER1_TEP_INT_CLR field.
	MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Pos = 0x7
	// Bit mask of TIMER1_TEP_INT_CLR field.
	MCPWM_INT_CLR_TIMER1_TEP_INT_CLR_Msk = 0x80
	// Bit TIMER1_TEP_INT_CLR.
	MCPWM_INT_CLR_TIMER1_TEP_INT_CLR = 0x80
	// Position of TIMER2_TEP_INT_CLR field.
	MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Pos = 0x8
	// Bit mask of TIMER2_TEP_INT_CLR field.
	MCPWM_INT_CLR_TIMER2_TEP_INT_CLR_Msk = 0x100
	// Bit TIMER2_TEP_INT_CLR.
	MCPWM_INT_CLR_TIMER2_TEP_INT_CLR = 0x100
	// Position of FAULT0_INT_CLR field.
	MCPWM_INT_CLR_FAULT0_INT_CLR_Pos = 0x9
	// Bit mask of FAULT0_INT_CLR field.
	MCPWM_INT_CLR_FAULT0_INT_CLR_Msk = 0x200
	// Bit FAULT0_INT_CLR.
	MCPWM_INT_CLR_FAULT0_INT_CLR = 0x200
	// Position of FAULT1_INT_CLR field.
	MCPWM_INT_CLR_FAULT1_INT_CLR_Pos = 0xa
	// Bit mask of FAULT1_INT_CLR field.
	MCPWM_INT_CLR_FAULT1_INT_CLR_Msk = 0x400
	// Bit FAULT1_INT_CLR.
	MCPWM_INT_CLR_FAULT1_INT_CLR = 0x400
	// Position of FAULT2_INT_CLR field.
	MCPWM_INT_CLR_FAULT2_INT_CLR_Pos = 0xb
	// Bit mask of FAULT2_INT_CLR field.
	MCPWM_INT_CLR_FAULT2_INT_CLR_Msk = 0x800
	// Bit FAULT2_INT_CLR.
	MCPWM_INT_CLR_FAULT2_INT_CLR = 0x800
	// Position of FAULT0_CLR_INT_CLR field.
	MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Pos = 0xc
	// Bit mask of FAULT0_CLR_INT_CLR field.
	MCPWM_INT_CLR_FAULT0_CLR_INT_CLR_Msk = 0x1000
	// Bit FAULT0_CLR_INT_CLR.
	MCPWM_INT_CLR_FAULT0_CLR_INT_CLR = 0x1000
	// Position of FAULT1_CLR_INT_CLR field.
	MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Pos = 0xd
	// Bit mask of FAULT1_CLR_INT_CLR field.
	MCPWM_INT_CLR_FAULT1_CLR_INT_CLR_Msk = 0x2000
	// Bit FAULT1_CLR_INT_CLR.
	MCPWM_INT_CLR_FAULT1_CLR_INT_CLR = 0x2000
	// Position of FAULT2_CLR_INT_CLR field.
	MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Pos = 0xe
	// Bit mask of FAULT2_CLR_INT_CLR field.
	MCPWM_INT_CLR_FAULT2_CLR_INT_CLR_Msk = 0x4000
	// Bit FAULT2_CLR_INT_CLR.
	MCPWM_INT_CLR_FAULT2_CLR_INT_CLR = 0x4000
	// Position of CMPR0_TEA_INT_CLR field.
	MCPWM_INT_CLR_CMPR0_TEA_INT_CLR_Pos = 0xf
	// Bit mask of CMPR0_TEA_INT_CLR field.
	MCPWM_INT_CLR_CMPR0_TEA_INT_CLR_Msk = 0x8000
	// Bit CMPR0_TEA_INT_CLR.
	MCPWM_INT_CLR_CMPR0_TEA_INT_CLR = 0x8000
	// Position of CMPR1_TEA_INT_CLR field.
	MCPWM_INT_CLR_CMPR1_TEA_INT_CLR_Pos = 0x10
	// Bit mask of CMPR1_TEA_INT_CLR field.
	MCPWM_INT_CLR_CMPR1_TEA_INT_CLR_Msk = 0x10000
	// Bit CMPR1_TEA_INT_CLR.
	MCPWM_INT_CLR_CMPR1_TEA_INT_CLR = 0x10000
	// Position of CMPR2_TEA_INT_CLR field.
	MCPWM_INT_CLR_CMPR2_TEA_INT_CLR_Pos = 0x11
	// Bit mask of CMPR2_TEA_INT_CLR field.
	MCPWM_INT_CLR_CMPR2_TEA_INT_CLR_Msk = 0x20000
	// Bit CMPR2_TEA_INT_CLR.
	MCPWM_INT_CLR_CMPR2_TEA_INT_CLR = 0x20000
	// Position of CMPR0_TEB_INT_CLR field.
	MCPWM_INT_CLR_CMPR0_TEB_INT_CLR_Pos = 0x12
	// Bit mask of CMPR0_TEB_INT_CLR field.
	MCPWM_INT_CLR_CMPR0_TEB_INT_CLR_Msk = 0x40000
	// Bit CMPR0_TEB_INT_CLR.
	MCPWM_INT_CLR_CMPR0_TEB_INT_CLR = 0x40000
	// Position of CMPR1_TEB_INT_CLR field.
	MCPWM_INT_CLR_CMPR1_TEB_INT_CLR_Pos = 0x13
	// Bit mask of CMPR1_TEB_INT_CLR field.
	MCPWM_INT_CLR_CMPR1_TEB_INT_CLR_Msk = 0x80000
	// Bit CMPR1_TEB_INT_CLR.
	MCPWM_INT_CLR_CMPR1_TEB_INT_CLR = 0x80000
	// Position of CMPR2_TEB_INT_CLR field.
	MCPWM_INT_CLR_CMPR2_TEB_INT_CLR_Pos = 0x14
	// Bit mask of CMPR2_TEB_INT_CLR field.
	MCPWM_INT_CLR_CMPR2_TEB_INT_CLR_Msk = 0x100000
	// Bit CMPR2_TEB_INT_CLR.
	MCPWM_INT_CLR_CMPR2_TEB_INT_CLR = 0x100000
	// Position of TZ0_CBC_INT_CLR field.
	MCPWM_INT_CLR_TZ0_CBC_INT_CLR_Pos = 0x15
	// Bit mask of TZ0_CBC_INT_CLR field.
	MCPWM_INT_CLR_TZ0_CBC_INT_CLR_Msk = 0x200000
	// Bit TZ0_CBC_INT_CLR.
	MCPWM_INT_CLR_TZ0_CBC_INT_CLR = 0x200000
	// Position of TZ1_CBC_INT_CLR field.
	MCPWM_INT_CLR_TZ1_CBC_INT_CLR_Pos = 0x16
	// Bit mask of TZ1_CBC_INT_CLR field.
	MCPWM_INT_CLR_TZ1_CBC_INT_CLR_Msk = 0x400000
	// Bit TZ1_CBC_INT_CLR.
	MCPWM_INT_CLR_TZ1_CBC_INT_CLR = 0x400000
	// Position of TZ2_CBC_INT_CLR field.
	MCPWM_INT_CLR_TZ2_CBC_INT_CLR_Pos = 0x17
	// Bit mask of TZ2_CBC_INT_CLR field.
	MCPWM_INT_CLR_TZ2_CBC_INT_CLR_Msk = 0x800000
	// Bit TZ2_CBC_INT_CLR.
	MCPWM_INT_CLR_TZ2_CBC_INT_CLR = 0x800000
	// Position of TZ0_OST_INT_CLR field.
	MCPWM_INT_CLR_TZ0_OST_INT_CLR_Pos = 0x18
	// Bit mask of TZ0_OST_INT_CLR field.
	MCPWM_INT_CLR_TZ0_OST_INT_CLR_Msk = 0x1000000
	// Bit TZ0_OST_INT_CLR.
	MCPWM_INT_CLR_TZ0_OST_INT_CLR = 0x1000000
	// Position of TZ1_OST_INT_CLR field.
	MCPWM_INT_CLR_TZ1_OST_INT_CLR_Pos = 0x19
	// Bit mask of TZ1_OST_INT_CLR field.
	MCPWM_INT_CLR_TZ1_OST_INT_CLR_Msk = 0x2000000
	// Bit TZ1_OST_INT_CLR.
	MCPWM_INT_CLR_TZ1_OST_INT_CLR = 0x2000000
	// Position of TZ2_OST_INT_CLR field.
	MCPWM_INT_CLR_TZ2_OST_INT_CLR_Pos = 0x1a
	// Bit mask of TZ2_OST_INT_CLR field.
	MCPWM_INT_CLR_TZ2_OST_INT_CLR_Msk = 0x4000000
	// Bit TZ2_OST_INT_CLR.
	MCPWM_INT_CLR_TZ2_OST_INT_CLR = 0x4000000
	// Position of CAP0_INT_CLR field.
	MCPWM_INT_CLR_CAP0_INT_CLR_Pos = 0x1b
	// Bit mask of CAP0_INT_CLR field.
	MCPWM_INT_CLR_CAP0_INT_CLR_Msk = 0x8000000
	// Bit CAP0_INT_CLR.
	MCPWM_INT_CLR_CAP0_INT_CLR = 0x8000000
	// Position of CAP1_INT_CLR field.
	MCPWM_INT_CLR_CAP1_INT_CLR_Pos = 0x1c
	// Bit mask of CAP1_INT_CLR field.
	MCPWM_INT_CLR_CAP1_INT_CLR_Msk = 0x10000000
	// Bit CAP1_INT_CLR.
	MCPWM_INT_CLR_CAP1_INT_CLR = 0x10000000
	// Position of CAP2_INT_CLR field.
	MCPWM_INT_CLR_CAP2_INT_CLR_Pos = 0x1d
	// Bit mask of CAP2_INT_CLR field.
	MCPWM_INT_CLR_CAP2_INT_CLR_Msk = 0x20000000
	// Bit CAP2_INT_CLR.
	MCPWM_INT_CLR_CAP2_INT_CLR = 0x20000000

	// EVT_EN: Event enable register
	// Position of EVT_TIMER0_STOP_EN field.
	MCPWM_EVT_EN_EVT_TIMER0_STOP_EN_Pos = 0x0
	// Bit mask of EVT_TIMER0_STOP_EN field.
	MCPWM_EVT_EN_EVT_TIMER0_STOP_EN_Msk = 0x1
	// Bit EVT_TIMER0_STOP_EN.
	MCPWM_EVT_EN_EVT_TIMER0_STOP_EN = 0x1
	// Position of EVT_TIMER1_STOP_EN field.
	MCPWM_EVT_EN_EVT_TIMER1_STOP_EN_Pos = 0x1
	// Bit mask of EVT_TIMER1_STOP_EN field.
	MCPWM_EVT_EN_EVT_TIMER1_STOP_EN_Msk = 0x2
	// Bit EVT_TIMER1_STOP_EN.
	MCPWM_EVT_EN_EVT_TIMER1_STOP_EN = 0x2
	// Position of EVT_TIMER2_STOP_EN field.
	MCPWM_EVT_EN_EVT_TIMER2_STOP_EN_Pos = 0x2
	// Bit mask of EVT_TIMER2_STOP_EN field.
	MCPWM_EVT_EN_EVT_TIMER2_STOP_EN_Msk = 0x4
	// Bit EVT_TIMER2_STOP_EN.
	MCPWM_EVT_EN_EVT_TIMER2_STOP_EN = 0x4
	// Position of EVT_TIMER0_TEZ_EN field.
	MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN_Pos = 0x3
	// Bit mask of EVT_TIMER0_TEZ_EN field.
	MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN_Msk = 0x8
	// Bit EVT_TIMER0_TEZ_EN.
	MCPWM_EVT_EN_EVT_TIMER0_TEZ_EN = 0x8
	// Position of EVT_TIMER1_TEZ_EN field.
	MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN_Pos = 0x4
	// Bit mask of EVT_TIMER1_TEZ_EN field.
	MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN_Msk = 0x10
	// Bit EVT_TIMER1_TEZ_EN.
	MCPWM_EVT_EN_EVT_TIMER1_TEZ_EN = 0x10
	// Position of EVT_TIMER2_TEZ_EN field.
	MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN_Pos = 0x5
	// Bit mask of EVT_TIMER2_TEZ_EN field.
	MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN_Msk = 0x20
	// Bit EVT_TIMER2_TEZ_EN.
	MCPWM_EVT_EN_EVT_TIMER2_TEZ_EN = 0x20
	// Position of EVT_TIMER0_TEP_EN field.
	MCPWM_EVT_EN_EVT_TIMER0_TEP_EN_Pos = 0x6
	// Bit mask of EVT_TIMER0_TEP_EN field.
	MCPWM_EVT_EN_EVT_TIMER0_TEP_EN_Msk = 0x40
	// Bit EVT_TIMER0_TEP_EN.
	MCPWM_EVT_EN_EVT_TIMER0_TEP_EN = 0x40
	// Position of EVT_TIMER1_TEP_EN field.
	MCPWM_EVT_EN_EVT_TIMER1_TEP_EN_Pos = 0x7
	// Bit mask of EVT_TIMER1_TEP_EN field.
	MCPWM_EVT_EN_EVT_TIMER1_TEP_EN_Msk = 0x80
	// Bit EVT_TIMER1_TEP_EN.
	MCPWM_EVT_EN_EVT_TIMER1_TEP_EN = 0x80
	// Position of EVT_TIMER2_TEP_EN field.
	MCPWM_EVT_EN_EVT_TIMER2_TEP_EN_Pos = 0x8
	// Bit mask of EVT_TIMER2_TEP_EN field.
	MCPWM_EVT_EN_EVT_TIMER2_TEP_EN_Msk = 0x100
	// Bit EVT_TIMER2_TEP_EN.
	MCPWM_EVT_EN_EVT_TIMER2_TEP_EN = 0x100
	// Position of EVT_OP0_TEA_EN field.
	MCPWM_EVT_EN_EVT_OP0_TEA_EN_Pos = 0x9
	// Bit mask of EVT_OP0_TEA_EN field.
	MCPWM_EVT_EN_EVT_OP0_TEA_EN_Msk = 0x200
	// Bit EVT_OP0_TEA_EN.
	MCPWM_EVT_EN_EVT_OP0_TEA_EN = 0x200
	// Position of EVT_OP1_TEA_EN field.
	MCPWM_EVT_EN_EVT_OP1_TEA_EN_Pos = 0xa
	// Bit mask of EVT_OP1_TEA_EN field.
	MCPWM_EVT_EN_EVT_OP1_TEA_EN_Msk = 0x400
	// Bit EVT_OP1_TEA_EN.
	MCPWM_EVT_EN_EVT_OP1_TEA_EN = 0x400
	// Position of EVT_OP2_TEA_EN field.
	MCPWM_EVT_EN_EVT_OP2_TEA_EN_Pos = 0xb
	// Bit mask of EVT_OP2_TEA_EN field.
	MCPWM_EVT_EN_EVT_OP2_TEA_EN_Msk = 0x800
	// Bit EVT_OP2_TEA_EN.
	MCPWM_EVT_EN_EVT_OP2_TEA_EN = 0x800
	// Position of EVT_OP0_TEB_EN field.
	MCPWM_EVT_EN_EVT_OP0_TEB_EN_Pos = 0xc
	// Bit mask of EVT_OP0_TEB_EN field.
	MCPWM_EVT_EN_EVT_OP0_TEB_EN_Msk = 0x1000
	// Bit EVT_OP0_TEB_EN.
	MCPWM_EVT_EN_EVT_OP0_TEB_EN = 0x1000
	// Position of EVT_OP1_TEB_EN field.
	MCPWM_EVT_EN_EVT_OP1_TEB_EN_Pos = 0xd
	// Bit mask of EVT_OP1_TEB_EN field.
	MCPWM_EVT_EN_EVT_OP1_TEB_EN_Msk = 0x2000
	// Bit EVT_OP1_TEB_EN.
	MCPWM_EVT_EN_EVT_OP1_TEB_EN = 0x2000
	// Position of EVT_OP2_TEB_EN field.
	MCPWM_EVT_EN_EVT_OP2_TEB_EN_Pos = 0xe
	// Bit mask of EVT_OP2_TEB_EN field.
	MCPWM_EVT_EN_EVT_OP2_TEB_EN_Msk = 0x4000
	// Bit EVT_OP2_TEB_EN.
	MCPWM_EVT_EN_EVT_OP2_TEB_EN = 0x4000
	// Position of EVT_F0_EN field.
	MCPWM_EVT_EN_EVT_F0_EN_Pos = 0xf
	// Bit mask of EVT_F0_EN field.
	MCPWM_EVT_EN_EVT_F0_EN_Msk = 0x8000
	// Bit EVT_F0_EN.
	MCPWM_EVT_EN_EVT_F0_EN = 0x8000
	// Position of EVT_F1_EN field.
	MCPWM_EVT_EN_EVT_F1_EN_Pos = 0x10
	// Bit mask of EVT_F1_EN field.
	MCPWM_EVT_EN_EVT_F1_EN_Msk = 0x10000
	// Bit EVT_F1_EN.
	MCPWM_EVT_EN_EVT_F1_EN = 0x10000
	// Position of EVT_F2_EN field.
	MCPWM_EVT_EN_EVT_F2_EN_Pos = 0x11
	// Bit mask of EVT_F2_EN field.
	MCPWM_EVT_EN_EVT_F2_EN_Msk = 0x20000
	// Bit EVT_F2_EN.
	MCPWM_EVT_EN_EVT_F2_EN = 0x20000
	// Position of EVT_F0_CLR_EN field.
	MCPWM_EVT_EN_EVT_F0_CLR_EN_Pos = 0x12
	// Bit mask of EVT_F0_CLR_EN field.
	MCPWM_EVT_EN_EVT_F0_CLR_EN_Msk = 0x40000
	// Bit EVT_F0_CLR_EN.
	MCPWM_EVT_EN_EVT_F0_CLR_EN = 0x40000
	// Position of EVT_F1_CLR_EN field.
	MCPWM_EVT_EN_EVT_F1_CLR_EN_Pos = 0x13
	// Bit mask of EVT_F1_CLR_EN field.
	MCPWM_EVT_EN_EVT_F1_CLR_EN_Msk = 0x80000
	// Bit EVT_F1_CLR_EN.
	MCPWM_EVT_EN_EVT_F1_CLR_EN = 0x80000
	// Position of EVT_F2_CLR_EN field.
	MCPWM_EVT_EN_EVT_F2_CLR_EN_Pos = 0x14
	// Bit mask of EVT_F2_CLR_EN field.
	MCPWM_EVT_EN_EVT_F2_CLR_EN_Msk = 0x100000
	// Bit EVT_F2_CLR_EN.
	MCPWM_EVT_EN_EVT_F2_CLR_EN = 0x100000
	// Position of EVT_TZ0_CBC_EN field.
	MCPWM_EVT_EN_EVT_TZ0_CBC_EN_Pos = 0x15
	// Bit mask of EVT_TZ0_CBC_EN field.
	MCPWM_EVT_EN_EVT_TZ0_CBC_EN_Msk = 0x200000
	// Bit EVT_TZ0_CBC_EN.
	MCPWM_EVT_EN_EVT_TZ0_CBC_EN = 0x200000
	// Position of EVT_TZ1_CBC_EN field.
	MCPWM_EVT_EN_EVT_TZ1_CBC_EN_Pos = 0x16
	// Bit mask of EVT_TZ1_CBC_EN field.
	MCPWM_EVT_EN_EVT_TZ1_CBC_EN_Msk = 0x400000
	// Bit EVT_TZ1_CBC_EN.
	MCPWM_EVT_EN_EVT_TZ1_CBC_EN = 0x400000
	// Position of EVT_TZ2_CBC_EN field.
	MCPWM_EVT_EN_EVT_TZ2_CBC_EN_Pos = 0x17
	// Bit mask of EVT_TZ2_CBC_EN field.
	MCPWM_EVT_EN_EVT_TZ2_CBC_EN_Msk = 0x800000
	// Bit EVT_TZ2_CBC_EN.
	MCPWM_EVT_EN_EVT_TZ2_CBC_EN = 0x800000
	// Position of EVT_TZ0_OST_EN field.
	MCPWM_EVT_EN_EVT_TZ0_OST_EN_Pos = 0x18
	// Bit mask of EVT_TZ0_OST_EN field.
	MCPWM_EVT_EN_EVT_TZ0_OST_EN_Msk = 0x1000000
	// Bit EVT_TZ0_OST_EN.
	MCPWM_EVT_EN_EVT_TZ0_OST_EN = 0x1000000
	// Position of EVT_TZ1_OST_EN field.
	MCPWM_EVT_EN_EVT_TZ1_OST_EN_Pos = 0x19
	// Bit mask of EVT_TZ1_OST_EN field.
	MCPWM_EVT_EN_EVT_TZ1_OST_EN_Msk = 0x2000000
	// Bit EVT_TZ1_OST_EN.
	MCPWM_EVT_EN_EVT_TZ1_OST_EN = 0x2000000
	// Position of EVT_TZ2_OST_EN field.
	MCPWM_EVT_EN_EVT_TZ2_OST_EN_Pos = 0x1a
	// Bit mask of EVT_TZ2_OST_EN field.
	MCPWM_EVT_EN_EVT_TZ2_OST_EN_Msk = 0x4000000
	// Bit EVT_TZ2_OST_EN.
	MCPWM_EVT_EN_EVT_TZ2_OST_EN = 0x4000000
	// Position of EVT_CAP0_EN field.
	MCPWM_EVT_EN_EVT_CAP0_EN_Pos = 0x1b
	// Bit mask of EVT_CAP0_EN field.
	MCPWM_EVT_EN_EVT_CAP0_EN_Msk = 0x8000000
	// Bit EVT_CAP0_EN.
	MCPWM_EVT_EN_EVT_CAP0_EN = 0x8000000
	// Position of EVT_CAP1_EN field.
	MCPWM_EVT_EN_EVT_CAP1_EN_Pos = 0x1c
	// Bit mask of EVT_CAP1_EN field.
	MCPWM_EVT_EN_EVT_CAP1_EN_Msk = 0x10000000
	// Bit EVT_CAP1_EN.
	MCPWM_EVT_EN_EVT_CAP1_EN = 0x10000000
	// Position of EVT_CAP2_EN field.
	MCPWM_EVT_EN_EVT_CAP2_EN_Pos = 0x1d
	// Bit mask of EVT_CAP2_EN field.
	MCPWM_EVT_EN_EVT_CAP2_EN_Msk = 0x20000000
	// Bit EVT_CAP2_EN.
	MCPWM_EVT_EN_EVT_CAP2_EN = 0x20000000

	// TASK_EN: Task enable register
	// Position of TASK_CMPR0_A_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN_Pos = 0x0
	// Bit mask of TASK_CMPR0_A_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN_Msk = 0x1
	// Bit TASK_CMPR0_A_UP_EN.
	MCPWM_TASK_EN_TASK_CMPR0_A_UP_EN = 0x1
	// Position of TASK_CMPR1_A_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN_Pos = 0x1
	// Bit mask of TASK_CMPR1_A_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN_Msk = 0x2
	// Bit TASK_CMPR1_A_UP_EN.
	MCPWM_TASK_EN_TASK_CMPR1_A_UP_EN = 0x2
	// Position of TASK_CMPR2_A_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN_Pos = 0x2
	// Bit mask of TASK_CMPR2_A_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN_Msk = 0x4
	// Bit TASK_CMPR2_A_UP_EN.
	MCPWM_TASK_EN_TASK_CMPR2_A_UP_EN = 0x4
	// Position of TASK_CMPR0_B_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN_Pos = 0x3
	// Bit mask of TASK_CMPR0_B_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN_Msk = 0x8
	// Bit TASK_CMPR0_B_UP_EN.
	MCPWM_TASK_EN_TASK_CMPR0_B_UP_EN = 0x8
	// Position of TASK_CMPR1_B_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN_Pos = 0x4
	// Bit mask of TASK_CMPR1_B_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN_Msk = 0x10
	// Bit TASK_CMPR1_B_UP_EN.
	MCPWM_TASK_EN_TASK_CMPR1_B_UP_EN = 0x10
	// Position of TASK_CMPR2_B_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN_Pos = 0x5
	// Bit mask of TASK_CMPR2_B_UP_EN field.
	MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN_Msk = 0x20
	// Bit TASK_CMPR2_B_UP_EN.
	MCPWM_TASK_EN_TASK_CMPR2_B_UP_EN = 0x20
	// Position of TASK_GEN_STOP_EN field.
	MCPWM_TASK_EN_TASK_GEN_STOP_EN_Pos = 0x6
	// Bit mask of TASK_GEN_STOP_EN field.
	MCPWM_TASK_EN_TASK_GEN_STOP_EN_Msk = 0x40
	// Bit TASK_GEN_STOP_EN.
	MCPWM_TASK_EN_TASK_GEN_STOP_EN = 0x40
	// Position of TASK_TIMER0_SYNC_EN field.
	MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN_Pos = 0x7
	// Bit mask of TASK_TIMER0_SYNC_EN field.
	MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN_Msk = 0x80
	// Bit TASK_TIMER0_SYNC_EN.
	MCPWM_TASK_EN_TASK_TIMER0_SYNC_EN = 0x80
	// Position of TASK_TIMER1_SYNC_EN field.
	MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN_Pos = 0x8
	// Bit mask of TASK_TIMER1_SYNC_EN field.
	MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN_Msk = 0x100
	// Bit TASK_TIMER1_SYNC_EN.
	MCPWM_TASK_EN_TASK_TIMER1_SYNC_EN = 0x100
	// Position of TASK_TIMER2_SYNC_EN field.
	MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN_Pos = 0x9
	// Bit mask of TASK_TIMER2_SYNC_EN field.
	MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN_Msk = 0x200
	// Bit TASK_TIMER2_SYNC_EN.
	MCPWM_TASK_EN_TASK_TIMER2_SYNC_EN = 0x200
	// Position of TASK_TIMER0_PERIOD_UP_EN field.
	MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN_Pos = 0xa
	// Bit mask of TASK_TIMER0_PERIOD_UP_EN field.
	MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN_Msk = 0x400
	// Bit TASK_TIMER0_PERIOD_UP_EN.
	MCPWM_TASK_EN_TASK_TIMER0_PERIOD_UP_EN = 0x400
	// Position of TASK_TIMER1_PERIOD_UP_EN field.
	MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN_Pos = 0xb
	// Bit mask of TASK_TIMER1_PERIOD_UP_EN field.
	MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN_Msk = 0x800
	// Bit TASK_TIMER1_PERIOD_UP_EN.
	MCPWM_TASK_EN_TASK_TIMER1_PERIOD_UP_EN = 0x800
	// Position of TASK_TIMER2_PERIOD_UP_EN field.
	MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN_Pos = 0xc
	// Bit mask of TASK_TIMER2_PERIOD_UP_EN field.
	MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN_Msk = 0x1000
	// Bit TASK_TIMER2_PERIOD_UP_EN.
	MCPWM_TASK_EN_TASK_TIMER2_PERIOD_UP_EN = 0x1000
	// Position of TASK_TZ0_OST_EN field.
	MCPWM_TASK_EN_TASK_TZ0_OST_EN_Pos = 0xd
	// Bit mask of TASK_TZ0_OST_EN field.
	MCPWM_TASK_EN_TASK_TZ0_OST_EN_Msk = 0x2000
	// Bit TASK_TZ0_OST_EN.
	MCPWM_TASK_EN_TASK_TZ0_OST_EN = 0x2000
	// Position of TASK_TZ1_OST_EN field.
	MCPWM_TASK_EN_TASK_TZ1_OST_EN_Pos = 0xe
	// Bit mask of TASK_TZ1_OST_EN field.
	MCPWM_TASK_EN_TASK_TZ1_OST_EN_Msk = 0x4000
	// Bit TASK_TZ1_OST_EN.
	MCPWM_TASK_EN_TASK_TZ1_OST_EN = 0x4000
	// Position of TASK_TZ2_OST_EN field.
	MCPWM_TASK_EN_TASK_TZ2_OST_EN_Pos = 0xf
	// Bit mask of TASK_TZ2_OST_EN field.
	MCPWM_TASK_EN_TASK_TZ2_OST_EN_Msk = 0x8000
	// Bit TASK_TZ2_OST_EN.
	MCPWM_TASK_EN_TASK_TZ2_OST_EN = 0x8000
	// Position of TASK_CLR0_OST_EN field.
	MCPWM_TASK_EN_TASK_CLR0_OST_EN_Pos = 0x10
	// Bit mask of TASK_CLR0_OST_EN field.
	MCPWM_TASK_EN_TASK_CLR0_OST_EN_Msk = 0x10000
	// Bit TASK_CLR0_OST_EN.
	MCPWM_TASK_EN_TASK_CLR0_OST_EN = 0x10000
	// Position of TASK_CLR1_OST_EN field.
	MCPWM_TASK_EN_TASK_CLR1_OST_EN_Pos = 0x11
	// Bit mask of TASK_CLR1_OST_EN field.
	MCPWM_TASK_EN_TASK_CLR1_OST_EN_Msk = 0x20000
	// Bit TASK_CLR1_OST_EN.
	MCPWM_TASK_EN_TASK_CLR1_OST_EN = 0x20000
	// Position of TASK_CLR2_OST_EN field.
	MCPWM_TASK_EN_TASK_CLR2_OST_EN_Pos = 0x12
	// Bit mask of TASK_CLR2_OST_EN field.
	MCPWM_TASK_EN_TASK_CLR2_OST_EN_Msk = 0x40000
	// Bit TASK_CLR2_OST_EN.
	MCPWM_TASK_EN_TASK_CLR2_OST_EN = 0x40000
	// Position of TASK_CAP0_EN field.
	MCPWM_TASK_EN_TASK_CAP0_EN_Pos = 0x13
	// Bit mask of TASK_CAP0_EN field.
	MCPWM_TASK_EN_TASK_CAP0_EN_Msk = 0x80000
	// Bit TASK_CAP0_EN.
	MCPWM_TASK_EN_TASK_CAP0_EN = 0x80000
	// Position of TASK_CAP1_EN field.
	MCPWM_TASK_EN_TASK_CAP1_EN_Pos = 0x14
	// Bit mask of TASK_CAP1_EN field.
	MCPWM_TASK_EN_TASK_CAP1_EN_Msk = 0x100000
	// Bit TASK_CAP1_EN.
	MCPWM_TASK_EN_TASK_CAP1_EN = 0x100000
	// Position of TASK_CAP2_EN field.
	MCPWM_TASK_EN_TASK_CAP2_EN_Pos = 0x15
	// Bit mask of TASK_CAP2_EN field.
	MCPWM_TASK_EN_TASK_CAP2_EN_Msk = 0x200000
	// Bit TASK_CAP2_EN.
	MCPWM_TASK_EN_TASK_CAP2_EN = 0x200000

	// EVT_EN2: Event enable register2
	// Position of EVT_OP0_TEE1_EN field.
	MCPWM_EVT_EN2_EVT_OP0_TEE1_EN_Pos = 0x0
	// Bit mask of EVT_OP0_TEE1_EN field.
	MCPWM_EVT_EN2_EVT_OP0_TEE1_EN_Msk = 0x1
	// Bit EVT_OP0_TEE1_EN.
	MCPWM_EVT_EN2_EVT_OP0_TEE1_EN = 0x1
	// Position of EVT_OP1_TEE1_EN field.
	MCPWM_EVT_EN2_EVT_OP1_TEE1_EN_Pos = 0x1
	// Bit mask of EVT_OP1_TEE1_EN field.
	MCPWM_EVT_EN2_EVT_OP1_TEE1_EN_Msk = 0x2
	// Bit EVT_OP1_TEE1_EN.
	MCPWM_EVT_EN2_EVT_OP1_TEE1_EN = 0x2
	// Position of EVT_OP2_TEE1_EN field.
	MCPWM_EVT_EN2_EVT_OP2_TEE1_EN_Pos = 0x2
	// Bit mask of EVT_OP2_TEE1_EN field.
	MCPWM_EVT_EN2_EVT_OP2_TEE1_EN_Msk = 0x4
	// Bit EVT_OP2_TEE1_EN.
	MCPWM_EVT_EN2_EVT_OP2_TEE1_EN = 0x4
	// Position of EVT_OP0_TEE2_EN field.
	MCPWM_EVT_EN2_EVT_OP0_TEE2_EN_Pos = 0x3
	// Bit mask of EVT_OP0_TEE2_EN field.
	MCPWM_EVT_EN2_EVT_OP0_TEE2_EN_Msk = 0x8
	// Bit EVT_OP0_TEE2_EN.
	MCPWM_EVT_EN2_EVT_OP0_TEE2_EN = 0x8
	// Position of EVT_OP1_TEE2_EN field.
	MCPWM_EVT_EN2_EVT_OP1_TEE2_EN_Pos = 0x4
	// Bit mask of EVT_OP1_TEE2_EN field.
	MCPWM_EVT_EN2_EVT_OP1_TEE2_EN_Msk = 0x10
	// Bit EVT_OP1_TEE2_EN.
	MCPWM_EVT_EN2_EVT_OP1_TEE2_EN = 0x10
	// Position of EVT_OP2_TEE2_EN field.
	MCPWM_EVT_EN2_EVT_OP2_TEE2_EN_Pos = 0x5
	// Bit mask of EVT_OP2_TEE2_EN field.
	MCPWM_EVT_EN2_EVT_OP2_TEE2_EN_Msk = 0x20
	// Bit EVT_OP2_TEE2_EN.
	MCPWM_EVT_EN2_EVT_OP2_TEE2_EN = 0x20

	// OP0_TSTMP_E1: Generator%s timer stamp E1 value register
	// Position of OP_TSTMP_E1 field.
	MCPWM_OP_TSTMP_E1_OP_TSTMP_E1_Pos = 0x0
	// Bit mask of OP_TSTMP_E1 field.
	MCPWM_OP_TSTMP_E1_OP_TSTMP_E1_Msk = 0xffff

	// OP0_TSTMP_E2: Generator%s timer stamp E2 value register
	// Position of OP_TSTMP_E2 field.
	MCPWM_OP_TSTMP_E2_OP_TSTMP_E2_Pos = 0x0
	// Bit mask of OP_TSTMP_E2 field.
	MCPWM_OP_TSTMP_E2_OP_TSTMP_E2_Msk = 0xffff

	// CLK: Global configuration register
	// Position of EN field.
	MCPWM_CLK_EN_Pos = 0x0
	// Bit mask of EN field.
	MCPWM_CLK_EN_Msk = 0x1
	// Bit EN.
	MCPWM_CLK_EN = 0x1

	// VERSION: Version register.
	// Position of DATE field.
	MCPWM_VERSION_DATE_Pos = 0x0
	// Bit mask of DATE field.
	MCPWM_VERSION_DATE_Msk = 0xfffffff
)

// Constants for PARL_IO: Parallel IO Controller
const (
	// RX_MODE_CFG: Parallel RX Sampling mode configuration register.
	// Position of RX_EXT_EN_SEL field.
	PARL_IO_RX_MODE_CFG_RX_EXT_EN_SEL_Pos = 0x15
	// Bit mask of RX_EXT_EN_SEL field.
	PARL_IO_RX_MODE_CFG_RX_EXT_EN_SEL_Msk = 0x1e00000
	// Position of RX_SW_EN field.
	PARL_IO_RX_MODE_CFG_RX_SW_EN_Pos = 0x19
	// Bit mask of RX_SW_EN field.
	PARL_IO_RX_MODE_CFG_RX_SW_EN_Msk = 0x2000000
	// Bit RX_SW_EN.
	PARL_IO_RX_MODE_CFG_RX_SW_EN = 0x2000000
	// Position of RX_EXT_EN_INV field.
	PARL_IO_RX_MODE_CFG_RX_EXT_EN_INV_Pos = 0x1a
	// Bit mask of RX_EXT_EN_INV field.
	PARL_IO_RX_MODE_CFG_RX_EXT_EN_INV_Msk = 0x4000000
	// Bit RX_EXT_EN_INV.
	PARL_IO_RX_MODE_CFG_RX_EXT_EN_INV = 0x4000000
	// Position of RX_PULSE_SUBMODE_SEL field.
	PARL_IO_RX_MODE_CFG_RX_PULSE_SUBMODE_SEL_Pos = 0x1b
	// Bit mask of RX_PULSE_SUBMODE_SEL field.
	PARL_IO_RX_MODE_CFG_RX_PULSE_SUBMODE_SEL_Msk = 0x38000000
	// Position of RX_SMP_MODE_SEL field.
	PARL_IO_RX_MODE_CFG_RX_SMP_MODE_SEL_Pos = 0x1e
	// Bit mask of RX_SMP_MODE_SEL field.
	PARL_IO_RX_MODE_CFG_RX_SMP_MODE_SEL_Msk = 0xc0000000

	// RX_DATA_CFG: Parallel RX data configuration register.
	// Position of RX_BITLEN field.
	PARL_IO_RX_DATA_CFG_RX_BITLEN_Pos = 0x9
	// Bit mask of RX_BITLEN field.
	PARL_IO_RX_DATA_CFG_RX_BITLEN_Msk = 0xffffe00
	// Position of RX_DATA_ORDER_INV field.
	PARL_IO_RX_DATA_CFG_RX_DATA_ORDER_INV_Pos = 0x1c
	// Bit mask of RX_DATA_ORDER_INV field.
	PARL_IO_RX_DATA_CFG_RX_DATA_ORDER_INV_Msk = 0x10000000
	// Bit RX_DATA_ORDER_INV.
	PARL_IO_RX_DATA_CFG_RX_DATA_ORDER_INV = 0x10000000
	// Position of RX_BUS_WID_SEL field.
	PARL_IO_RX_DATA_CFG_RX_BUS_WID_SEL_Pos = 0x1d
	// Bit mask of RX_BUS_WID_SEL field.
	PARL_IO_RX_DATA_CFG_RX_BUS_WID_SEL_Msk = 0xe0000000

	// RX_GENRL_CFG: Parallel RX general configuration register.
	// Position of RX_GATING_EN field.
	PARL_IO_RX_GENRL_CFG_RX_GATING_EN_Pos = 0xc
	// Bit mask of RX_GATING_EN field.
	PARL_IO_RX_GENRL_CFG_RX_GATING_EN_Msk = 0x1000
	// Bit RX_GATING_EN.
	PARL_IO_RX_GENRL_CFG_RX_GATING_EN = 0x1000
	// Position of RX_TIMEOUT_THRES field.
	PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_THRES_Pos = 0xd
	// Bit mask of RX_TIMEOUT_THRES field.
	PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_THRES_Msk = 0x1fffe000
	// Position of RX_TIMEOUT_EN field.
	PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_EN_Pos = 0x1d
	// Bit mask of RX_TIMEOUT_EN field.
	PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_EN_Msk = 0x20000000
	// Bit RX_TIMEOUT_EN.
	PARL_IO_RX_GENRL_CFG_RX_TIMEOUT_EN = 0x20000000
	// Position of RX_EOF_GEN_SEL field.
	PARL_IO_RX_GENRL_CFG_RX_EOF_GEN_SEL_Pos = 0x1e
	// Bit mask of RX_EOF_GEN_SEL field.
	PARL_IO_RX_GENRL_CFG_RX_EOF_GEN_SEL_Msk = 0x40000000
	// Bit RX_EOF_GEN_SEL.
	PARL_IO_RX_GENRL_CFG_RX_EOF_GEN_SEL = 0x40000000

	// RX_START_CFG: Parallel RX Start configuration register.
	// Position of RX_START field.
	PARL_IO_RX_START_CFG_RX_START_Pos = 0x1f
	// Bit mask of RX_START field.
	PARL_IO_RX_START_CFG_RX_START_Msk = 0x80000000
	// Bit RX_START.
	PARL_IO_RX_START_CFG_RX_START = 0x80000000

	// TX_DATA_CFG: Parallel TX data configuration register.
	// Position of TX_BITLEN field.
	PARL_IO_TX_DATA_CFG_TX_BITLEN_Pos = 0x9
	// Bit mask of TX_BITLEN field.
	PARL_IO_TX_DATA_CFG_TX_BITLEN_Msk = 0xffffe00
	// Position of TX_DATA_ORDER_INV field.
	PARL_IO_TX_DATA_CFG_TX_DATA_ORDER_INV_Pos = 0x1c
	// Bit mask of TX_DATA_ORDER_INV field.
	PARL_IO_TX_DATA_CFG_TX_DATA_ORDER_INV_Msk = 0x10000000
	// Bit TX_DATA_ORDER_INV.
	PARL_IO_TX_DATA_CFG_TX_DATA_ORDER_INV = 0x10000000
	// Position of TX_BUS_WID_SEL field.
	PARL_IO_TX_DATA_CFG_TX_BUS_WID_SEL_Pos = 0x1d
	// Bit mask of TX_BUS_WID_SEL field.
	PARL_IO_TX_DATA_CFG_TX_BUS_WID_SEL_Msk = 0xe0000000

	// TX_START_CFG: Parallel TX Start configuration register.
	// Position of TX_START field.
	PARL_IO_TX_START_CFG_TX_START_Pos = 0x1f
	// Bit mask of TX_START field.
	PARL_IO_TX_START_CFG_TX_START_Msk = 0x80000000
	// Bit TX_START.
	PARL_IO_TX_START_CFG_TX_START = 0x80000000

	// TX_GENRL_CFG: Parallel TX general configuration register.
	// Position of TX_EOF_GEN_SEL field.
	PARL_IO_TX_GENRL_CFG_TX_EOF_GEN_SEL_Pos = 0xd
	// Bit mask of TX_EOF_GEN_SEL field.
	PARL_IO_TX_GENRL_CFG_TX_EOF_GEN_SEL_Msk = 0x2000
	// Bit TX_EOF_GEN_SEL.
	PARL_IO_TX_GENRL_CFG_TX_EOF_GEN_SEL = 0x2000
	// Position of TX_IDLE_VALUE field.
	PARL_IO_TX_GENRL_CFG_TX_IDLE_VALUE_Pos = 0xe
	// Bit mask of TX_IDLE_VALUE field.
	PARL_IO_TX_GENRL_CFG_TX_IDLE_VALUE_Msk = 0x3fffc000
	// Position of TX_GATING_EN field.
	PARL_IO_TX_GENRL_CFG_TX_GATING_EN_Pos = 0x1e
	// Bit mask of TX_GATING_EN field.
	PARL_IO_TX_GENRL_CFG_TX_GATING_EN_Msk = 0x40000000
	// Bit TX_GATING_EN.
	PARL_IO_TX_GENRL_CFG_TX_GATING_EN = 0x40000000
	// Position of TX_VALID_OUTPUT_EN field.
	PARL_IO_TX_GENRL_CFG_TX_VALID_OUTPUT_EN_Pos = 0x1f
	// Bit mask of TX_VALID_OUTPUT_EN field.
	PARL_IO_TX_GENRL_CFG_TX_VALID_OUTPUT_EN_Msk = 0x80000000
	// Bit TX_VALID_OUTPUT_EN.
	PARL_IO_TX_GENRL_CFG_TX_VALID_OUTPUT_EN = 0x80000000

	// FIFO_CFG: Parallel IO FIFO configuration register.
	// Position of TX_FIFO_SRST field.
	PARL_IO_FIFO_CFG_TX_FIFO_SRST_Pos = 0x1e
	// Bit mask of TX_FIFO_SRST field.
	PARL_IO_FIFO_CFG_TX_FIFO_SRST_Msk = 0x40000000
	// Bit TX_FIFO_SRST.
	PARL_IO_FIFO_CFG_TX_FIFO_SRST = 0x40000000
	// Position of RX_FIFO_SRST field.
	PARL_IO_FIFO_CFG_RX_FIFO_SRST_Pos = 0x1f
	// Bit mask of RX_FIFO_SRST field.
	PARL_IO_FIFO_CFG_RX_FIFO_SRST_Msk = 0x80000000
	// Bit RX_FIFO_SRST.
	PARL_IO_FIFO_CFG_RX_FIFO_SRST = 0x80000000

	// REG_UPDATE: Parallel IO FIFO configuration register.
	// Position of RX_REG_UPDATE field.
	PARL_IO_REG_UPDATE_RX_REG_UPDATE_Pos = 0x1f
	// Bit mask of RX_REG_UPDATE field.
	PARL_IO_REG_UPDATE_RX_REG_UPDATE_Msk = 0x80000000
	// Bit RX_REG_UPDATE.
	PARL_IO_REG_UPDATE_RX_REG_UPDATE = 0x80000000

	// ST: Parallel IO module status register0.
	// Position of TX_READY field.
	PARL_IO_ST_TX_READY_Pos = 0x1f
	// Bit mask of TX_READY field.
	PARL_IO_ST_TX_READY_Msk = 0x80000000
	// Bit TX_READY.
	PARL_IO_ST_TX_READY = 0x80000000

	// INT_ENA: Parallel IO interrupt enable singal configuration register.
	// Position of TX_FIFO_REMPTY_INT_ENA field.
	PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA_Pos = 0x0
	// Bit mask of TX_FIFO_REMPTY_INT_ENA field.
	PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA_Msk = 0x1
	// Bit TX_FIFO_REMPTY_INT_ENA.
	PARL_IO_INT_ENA_TX_FIFO_REMPTY_INT_ENA = 0x1
	// Position of RX_FIFO_WOVF_INT_ENA field.
	PARL_IO_INT_ENA_RX_FIFO_WOVF_INT_ENA_Pos = 0x1
	// Bit mask of RX_FIFO_WOVF_INT_ENA field.
	PARL_IO_INT_ENA_RX_FIFO_WOVF_INT_ENA_Msk = 0x2
	// Bit RX_FIFO_WOVF_INT_ENA.
	PARL_IO_INT_ENA_RX_FIFO_WOVF_INT_ENA = 0x2
	// Position of TX_EOF_INT_ENA field.
	PARL_IO_INT_ENA_TX_EOF_INT_ENA_Pos = 0x2
	// Bit mask of TX_EOF_INT_ENA field.
	PARL_IO_INT_ENA_TX_EOF_INT_ENA_Msk = 0x4
	// Bit TX_EOF_INT_ENA.
	PARL_IO_INT_ENA_TX_EOF_INT_ENA = 0x4

	// INT_RAW: Parallel IO interrupt raw singal status register.
	// Position of TX_FIFO_REMPTY_INT_RAW field.
	PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW_Pos = 0x0
	// Bit mask of TX_FIFO_REMPTY_INT_RAW field.
	PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW_Msk = 0x1
	// Bit TX_FIFO_REMPTY_INT_RAW.
	PARL_IO_INT_RAW_TX_FIFO_REMPTY_INT_RAW = 0x1
	// Position of RX_FIFO_WOVF_INT_RAW field.
	PARL_IO_INT_RAW_RX_FIFO_WOVF_INT_RAW_Pos = 0x1
	// Bit mask of RX_FIFO_WOVF_INT_RAW field.
	PARL_IO_INT_RAW_RX_FIFO_WOVF_INT_RAW_Msk = 0x2
	// Bit RX_FIFO_WOVF_INT_RAW.
	PARL_IO_INT_RAW_RX_FIFO_WOVF_INT_RAW = 0x2
	// Position of TX_EOF_INT_RAW field.
	PARL_IO_INT_RAW_TX_EOF_INT_RAW_Pos = 0x2
	// Bit mask of TX_EOF_INT_RAW field.
	PARL_IO_INT_RAW_TX_EOF_INT_RAW_Msk = 0x4
	// Bit TX_EOF_INT_RAW.
	PARL_IO_INT_RAW_TX_EOF_INT_RAW = 0x4

	// INT_ST: Parallel IO interrupt singal status register.
	// Position of TX_FIFO_REMPTY_INT_ST field.
	PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST_Pos = 0x0
	// Bit mask of TX_FIFO_REMPTY_INT_ST field.
	PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST_Msk = 0x1
	// Bit TX_FIFO_REMPTY_INT_ST.
	PARL_IO_INT_ST_TX_FIFO_REMPTY_INT_ST = 0x1
	// Position of RX_FIFO_WOVF_INT_ST field.
	PARL_IO_INT_ST_RX_FIFO_WOVF_INT_ST_Pos = 0x1
	// Bit mask of RX_FIFO_WOVF_INT_ST field.
	PARL_IO_INT_ST_RX_FIFO_WOVF_INT_ST_Msk = 0x2
	// Bit RX_FIFO_WOVF_INT_ST.
	PARL_IO_INT_ST_RX_FIFO_WOVF_INT_ST = 0x2
	// Position of TX_EOF_INT_ST field.
	PARL_IO_INT_ST_TX_EOF_INT_ST_Pos = 0x2
	// Bit mask of TX_EOF_INT_ST field.
	PARL_IO_INT_ST_TX_EOF_INT_ST_Msk = 0x4
	// Bit TX_EOF_INT_ST.
	PARL_IO_INT_ST_TX_EOF_INT_ST = 0x4

	// INT_CLR: Parallel IO interrupt clear singal configuration register.
	// Position of TX_FIFO_REMPTY_INT_CLR field.
	PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR_Pos = 0x0
	// Bit mask of TX_FIFO_REMPTY_INT_CLR field.
	PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR_Msk = 0x1
	// Bit TX_FIFO_REMPTY_INT_CLR.
	PARL_IO_INT_CLR_TX_FIFO_REMPTY_INT_CLR = 0x1
	// Position of RX_FIFO_WOVF_INT_CLR field.
	PARL_IO_INT_CLR_RX_FIFO_WOVF_INT_CLR_Pos = 0x1
	// Bit mask of RX_FIFO_WOVF_INT_CLR field.
	PARL_IO_INT_CLR_RX_FIFO_WOVF_INT_CLR_Msk = 0x2
	// Bit RX_FIFO_WOVF_INT_CLR.
	PARL_IO_INT_CLR_RX_FIFO_WOVF_INT_CLR = 0x2
	// Position of TX_EOF_INT_CLR field.
	PARL_IO_INT_CLR_TX_EOF_INT_CLR_Pos = 0x2
	// Bit mask of TX_EOF_INT_CLR field.
	PARL_IO_INT_CLR_TX_EOF_INT_CLR_Msk = 0x4
	// Bit TX_EOF_INT_CLR.
	PARL_IO_INT_CLR_TX_EOF_INT_CLR = 0x4

	// RX_ST0: Parallel IO RX status register0
	// Position of RX_CNT field.
	PARL_IO_RX_ST0_RX_CNT_Pos = 0x8
	// Bit mask of RX_CNT field.
	PARL_IO_RX_ST0_RX_CNT_Msk = 0x1f00
	// Position of RX_FIFO_WR_BIT_CNT field.
	PARL_IO_RX_ST0_RX_FIFO_WR_BIT_CNT_Pos = 0xd
	// Bit mask of RX_FIFO_WR_BIT_CNT field.
	PARL_IO_RX_ST0_RX_FIFO_WR_BIT_CNT_Msk = 0xffffe000

	// RX_ST1: Parallel IO RX status register1
	// Position of RX_FIFO_RD_BIT_CNT field.
	PARL_IO_RX_ST1_RX_FIFO_RD_BIT_CNT_Pos = 0xd
	// Bit mask of RX_FIFO_RD_BIT_CNT field.
	PARL_IO_RX_ST1_RX_FIFO_RD_BIT_CNT_Msk = 0xffffe000

	// TX_ST0: Parallel IO TX status register0
	// Position of TX_CNT field.
	PARL_IO_TX_ST0_TX_CNT_Pos = 0x6
	// Bit mask of TX_CNT field.
	PARL_IO_TX_ST0_TX_CNT_Msk = 0x1fc0
	// Position of TX_FIFO_RD_BIT_CNT field.
	PARL_IO_TX_ST0_TX_FIFO_RD_BIT_CNT_Pos = 0xd
	// Bit mask of TX_FIFO_RD_BIT_CNT field.
	PARL_IO_TX_ST0_TX_FIFO_RD_BIT_CNT_Msk = 0xffffe000

	// RX_CLK_CFG: Parallel IO RX clk configuration register
	// Position of RX_CLK_I_INV field.
	PARL_IO_RX_CLK_CFG_RX_CLK_I_INV_Pos = 0x1e
	// Bit mask of RX_CLK_I_INV field.
	PARL_IO_RX_CLK_CFG_RX_CLK_I_INV_Msk = 0x40000000
	// Bit RX_CLK_I_INV.
	PARL_IO_RX_CLK_CFG_RX_CLK_I_INV = 0x40000000
	// Position of RX_CLK_O_INV field.
	PARL_IO_RX_CLK_CFG_RX_CLK_O_INV_Pos = 0x1f
	// Bit mask of RX_CLK_O_INV field.
	PARL_IO_RX_CLK_CFG_RX_CLK_O_INV_Msk = 0x80000000
	// Bit RX_CLK_O_INV.
	PARL_IO_RX_CLK_CFG_RX_CLK_O_INV = 0x80000000

	// TX_CLK_CFG: Parallel IO TX clk configuration register
	// Position of TX_CLK_I_INV field.
	PARL_IO_TX_CLK_CFG_TX_CLK_I_INV_Pos = 0x1e
	// Bit mask of TX_CLK_I_INV field.
	PARL_IO_TX_CLK_CFG_TX_CLK_I_INV_Msk = 0x40000000
	// Bit TX_CLK_I_INV.
	PARL_IO_TX_CLK_CFG_TX_CLK_I_INV = 0x40000000
	// Position of TX_CLK_O_INV field.
	PARL_IO_TX_CLK_CFG_TX_CLK_O_INV_Pos = 0x1f
	// Bit mask of TX_CLK_O_INV field.
	PARL_IO_TX_CLK_CFG_TX_CLK_O_INV_Msk = 0x80000000
	// Bit TX_CLK_O_INV.
	PARL_IO_TX_CLK_CFG_TX_CLK_O_INV = 0x80000000

	// CLK: Parallel IO clk configuration register
	// Position of EN field.
	PARL_IO_CLK_EN_Pos = 0x1f
	// Bit mask of EN field.
	PARL_IO_CLK_EN_Msk = 0x80000000
	// Bit EN.
	PARL_IO_CLK_EN = 0x80000000

	// VERSION: Version register.
	// Position of DATE field.
	PARL_IO_VERSION_DATE_Pos = 0x0
	// Bit mask of DATE field.
	PARL_IO_VERSION_DATE_Msk = 0xfffffff
)

// Constants for PAU: PAU Peripheral
const (
	// REGDMA_CONF: Peri backup control register
	// Position of FLOW_ERR field.
	PAU_REGDMA_CONF_FLOW_ERR_Pos = 0x0
	// Bit mask of FLOW_ERR field.
	PAU_REGDMA_CONF_FLOW_ERR_Msk = 0x7
	// Position of START field.
	PAU_REGDMA_CONF_START_Pos = 0x3
	// Bit mask of START field.
	PAU_REGDMA_CONF_START_Msk = 0x8
	// Bit START.
	PAU_REGDMA_CONF_START = 0x8
	// Position of TO_MEM field.
	PAU_REGDMA_CONF_TO_MEM_Pos = 0x4
	// Bit mask of TO_MEM field.
	PAU_REGDMA_CONF_TO_MEM_Msk = 0x10
	// Bit TO_MEM.
	PAU_REGDMA_CONF_TO_MEM = 0x10
	// Position of LINK_SEL field.
	PAU_REGDMA_CONF_LINK_SEL_Pos = 0x5
	// Bit mask of LINK_SEL field.
	PAU_REGDMA_CONF_LINK_SEL_Msk = 0x60
	// Position of START_MAC field.
	PAU_REGDMA_CONF_START_MAC_Pos = 0x7
	// Bit mask of START_MAC field.
	PAU_REGDMA_CONF_START_MAC_Msk = 0x80
	// Bit START_MAC.
	PAU_REGDMA_CONF_START_MAC = 0x80
	// Position of TO_MEM_MAC field.
	PAU_REGDMA_CONF_TO_MEM_MAC_Pos = 0x8
	// Bit mask of TO_MEM_MAC field.
	PAU_REGDMA_CONF_TO_MEM_MAC_Msk = 0x100
	// Bit TO_MEM_MAC.
	PAU_REGDMA_CONF_TO_MEM_MAC = 0x100
	// Position of SEL_MAC field.
	PAU_REGDMA_CONF_SEL_MAC_Pos = 0x9
	// Bit mask of SEL_MAC field.
	PAU_REGDMA_CONF_SEL_MAC_Msk = 0x200
	// Bit SEL_MAC.
	PAU_REGDMA_CONF_SEL_MAC = 0x200

	// REGDMA_CLK_CONF: Clock control register
	// Position of CLK_EN field.
	PAU_REGDMA_CLK_CONF_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	PAU_REGDMA_CLK_CONF_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	PAU_REGDMA_CLK_CONF_CLK_EN = 0x1

	// REGDMA_ETM_CTRL: ETM start ctrl reg
	// Position of ETM_START_0 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_0_Pos = 0x0
	// Bit mask of ETM_START_0 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_0_Msk = 0x1
	// Bit ETM_START_0.
	PAU_REGDMA_ETM_CTRL_ETM_START_0 = 0x1
	// Position of ETM_START_1 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_1_Pos = 0x1
	// Bit mask of ETM_START_1 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_1_Msk = 0x2
	// Bit ETM_START_1.
	PAU_REGDMA_ETM_CTRL_ETM_START_1 = 0x2
	// Position of ETM_START_2 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_2_Pos = 0x2
	// Bit mask of ETM_START_2 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_2_Msk = 0x4
	// Bit ETM_START_2.
	PAU_REGDMA_ETM_CTRL_ETM_START_2 = 0x4
	// Position of ETM_START_3 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_3_Pos = 0x3
	// Bit mask of ETM_START_3 field.
	PAU_REGDMA_ETM_CTRL_ETM_START_3_Msk = 0x8
	// Bit ETM_START_3.
	PAU_REGDMA_ETM_CTRL_ETM_START_3 = 0x8

	// REGDMA_LINK_0_ADDR: link_0_addr
	// Position of LINK_ADDR_0 field.
	PAU_REGDMA_LINK_0_ADDR_LINK_ADDR_0_Pos = 0x0
	// Bit mask of LINK_ADDR_0 field.
	PAU_REGDMA_LINK_0_ADDR_LINK_ADDR_0_Msk = 0xffffffff

	// REGDMA_LINK_1_ADDR: Link_1_addr
	// Position of LINK_ADDR_1 field.
	PAU_REGDMA_LINK_1_ADDR_LINK_ADDR_1_Pos = 0x0
	// Bit mask of LINK_ADDR_1 field.
	PAU_REGDMA_LINK_1_ADDR_LINK_ADDR_1_Msk = 0xffffffff

	// REGDMA_LINK_2_ADDR: Link_2_addr
	// Position of LINK_ADDR_2 field.
	PAU_REGDMA_LINK_2_ADDR_LINK_ADDR_2_Pos = 0x0
	// Bit mask of LINK_ADDR_2 field.
	PAU_REGDMA_LINK_2_ADDR_LINK_ADDR_2_Msk = 0xffffffff

	// REGDMA_LINK_3_ADDR: Link_3_addr
	// Position of LINK_ADDR_3 field.
	PAU_REGDMA_LINK_3_ADDR_LINK_ADDR_3_Pos = 0x0
	// Bit mask of LINK_ADDR_3 field.
	PAU_REGDMA_LINK_3_ADDR_LINK_ADDR_3_Msk = 0xffffffff

	// REGDMA_LINK_MAC_ADDR: Link_mac_addr
	// Position of LINK_ADDR_MAC field.
	PAU_REGDMA_LINK_MAC_ADDR_LINK_ADDR_MAC_Pos = 0x0
	// Bit mask of LINK_ADDR_MAC field.
	PAU_REGDMA_LINK_MAC_ADDR_LINK_ADDR_MAC_Msk = 0xffffffff

	// REGDMA_CURRENT_LINK_ADDR: current link addr
	// Position of CURRENT_LINK_ADDR field.
	PAU_REGDMA_CURRENT_LINK_ADDR_CURRENT_LINK_ADDR_Pos = 0x0
	// Bit mask of CURRENT_LINK_ADDR field.
	PAU_REGDMA_CURRENT_LINK_ADDR_CURRENT_LINK_ADDR_Msk = 0xffffffff

	// REGDMA_BACKUP_ADDR: Backup addr
	// Position of BACKUP_ADDR field.
	PAU_REGDMA_BACKUP_ADDR_BACKUP_ADDR_Pos = 0x0
	// Bit mask of BACKUP_ADDR field.
	PAU_REGDMA_BACKUP_ADDR_BACKUP_ADDR_Msk = 0xffffffff

	// REGDMA_MEM_ADDR: mem addr
	// Position of MEM_ADDR field.
	PAU_REGDMA_MEM_ADDR_MEM_ADDR_Pos = 0x0
	// Bit mask of MEM_ADDR field.
	PAU_REGDMA_MEM_ADDR_MEM_ADDR_Msk = 0xffffffff

	// REGDMA_BKP_CONF: backup config
	// Position of READ_INTERVAL field.
	PAU_REGDMA_BKP_CONF_READ_INTERVAL_Pos = 0x0
	// Bit mask of READ_INTERVAL field.
	PAU_REGDMA_BKP_CONF_READ_INTERVAL_Msk = 0x7f
	// Position of LINK_TOUT_THRES field.
	PAU_REGDMA_BKP_CONF_LINK_TOUT_THRES_Pos = 0x7
	// Bit mask of LINK_TOUT_THRES field.
	PAU_REGDMA_BKP_CONF_LINK_TOUT_THRES_Msk = 0x1ff80
	// Position of BURST_LIMIT field.
	PAU_REGDMA_BKP_CONF_BURST_LIMIT_Pos = 0x11
	// Bit mask of BURST_LIMIT field.
	PAU_REGDMA_BKP_CONF_BURST_LIMIT_Msk = 0x3e0000
	// Position of BACKUP_TOUT_THRES field.
	PAU_REGDMA_BKP_CONF_BACKUP_TOUT_THRES_Pos = 0x16
	// Bit mask of BACKUP_TOUT_THRES field.
	PAU_REGDMA_BKP_CONF_BACKUP_TOUT_THRES_Msk = 0xffc00000

	// INT_ENA: Read only register for error and done
	// Position of DONE_INT_ENA field.
	PAU_INT_ENA_DONE_INT_ENA_Pos = 0x0
	// Bit mask of DONE_INT_ENA field.
	PAU_INT_ENA_DONE_INT_ENA_Msk = 0x1
	// Bit DONE_INT_ENA.
	PAU_INT_ENA_DONE_INT_ENA = 0x1
	// Position of ERROR_INT_ENA field.
	PAU_INT_ENA_ERROR_INT_ENA_Pos = 0x1
	// Bit mask of ERROR_INT_ENA field.
	PAU_INT_ENA_ERROR_INT_ENA_Msk = 0x2
	// Bit ERROR_INT_ENA.
	PAU_INT_ENA_ERROR_INT_ENA = 0x2

	// INT_RAW: Read only register for error and done
	// Position of DONE_INT_RAW field.
	PAU_INT_RAW_DONE_INT_RAW_Pos = 0x0
	// Bit mask of DONE_INT_RAW field.
	PAU_INT_RAW_DONE_INT_RAW_Msk = 0x1
	// Bit DONE_INT_RAW.
	PAU_INT_RAW_DONE_INT_RAW = 0x1
	// Position of ERROR_INT_RAW field.
	PAU_INT_RAW_ERROR_INT_RAW_Pos = 0x1
	// Bit mask of ERROR_INT_RAW field.
	PAU_INT_RAW_ERROR_INT_RAW_Msk = 0x2
	// Bit ERROR_INT_RAW.
	PAU_INT_RAW_ERROR_INT_RAW = 0x2

	// INT_CLR: Read only register for error and done
	// Position of DONE_INT_CLR field.
	PAU_INT_CLR_DONE_INT_CLR_Pos = 0x0
	// Bit mask of DONE_INT_CLR field.
	PAU_INT_CLR_DONE_INT_CLR_Msk = 0x1
	// Bit DONE_INT_CLR.
	PAU_INT_CLR_DONE_INT_CLR = 0x1
	// Position of ERROR_INT_CLR field.
	PAU_INT_CLR_ERROR_INT_CLR_Pos = 0x1
	// Bit mask of ERROR_INT_CLR field.
	PAU_INT_CLR_ERROR_INT_CLR_Msk = 0x2
	// Bit ERROR_INT_CLR.
	PAU_INT_CLR_ERROR_INT_CLR = 0x2

	// INT_ST: Read only register for error and done
	// Position of DONE_INT_ST field.
	PAU_INT_ST_DONE_INT_ST_Pos = 0x0
	// Bit mask of DONE_INT_ST field.
	PAU_INT_ST_DONE_INT_ST_Msk = 0x1
	// Bit DONE_INT_ST.
	PAU_INT_ST_DONE_INT_ST = 0x1
	// Position of ERROR_INT_ST field.
	PAU_INT_ST_ERROR_INT_ST_Pos = 0x1
	// Bit mask of ERROR_INT_ST field.
	PAU_INT_ST_ERROR_INT_ST_Msk = 0x2
	// Bit ERROR_INT_ST.
	PAU_INT_ST_ERROR_INT_ST = 0x2

	// DATE: Date register.
	// Position of DATE field.
	PAU_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	PAU_DATE_DATE_Msk = 0xfffffff
)

// Constants for PCNT: Pulse Count Controller
const (
	// U0_CONF0: Configuration register 0 for unit %s
	// Position of FILTER_THRES_U field.
	PCNT_U_CONF0_FILTER_THRES_U_Pos = 0x0
	// Bit mask of FILTER_THRES_U field.
	PCNT_U_CONF0_FILTER_THRES_U_Msk = 0x3ff
	// Position of FILTER_EN_U field.
	PCNT_U_CONF0_FILTER_EN_U_Pos = 0xa
	// Bit mask of FILTER_EN_U field.
	PCNT_U_CONF0_FILTER_EN_U_Msk = 0x400
	// Bit FILTER_EN_U.
	PCNT_U_CONF0_FILTER_EN_U = 0x400
	// Position of THR_ZERO_EN_U field.
	PCNT_U_CONF0_THR_ZERO_EN_U_Pos = 0xb
	// Bit mask of THR_ZERO_EN_U field.
	PCNT_U_CONF0_THR_ZERO_EN_U_Msk = 0x800
	// Bit THR_ZERO_EN_U.
	PCNT_U_CONF0_THR_ZERO_EN_U = 0x800
	// Position of THR_H_LIM_EN_U field.
	PCNT_U_CONF0_THR_H_LIM_EN_U_Pos = 0xc
	// Bit mask of THR_H_LIM_EN_U field.
	PCNT_U_CONF0_THR_H_LIM_EN_U_Msk = 0x1000
	// Bit THR_H_LIM_EN_U.
	PCNT_U_CONF0_THR_H_LIM_EN_U = 0x1000
	// Position of THR_L_LIM_EN_U field.
	PCNT_U_CONF0_THR_L_LIM_EN_U_Pos = 0xd
	// Bit mask of THR_L_LIM_EN_U field.
	PCNT_U_CONF0_THR_L_LIM_EN_U_Msk = 0x2000
	// Bit THR_L_LIM_EN_U.
	PCNT_U_CONF0_THR_L_LIM_EN_U = 0x2000
	// Position of THR_THRES0_EN_U field.
	PCNT_U_CONF0_THR_THRES0_EN_U_Pos = 0xe
	// Bit mask of THR_THRES0_EN_U field.
	PCNT_U_CONF0_THR_THRES0_EN_U_Msk = 0x4000
	// Bit THR_THRES0_EN_U.
	PCNT_U_CONF0_THR_THRES0_EN_U = 0x4000
	// Position of THR_THRES1_EN_U field.
	PCNT_U_CONF0_THR_THRES1_EN_U_Pos = 0xf
	// Bit mask of THR_THRES1_EN_U field.
	PCNT_U_CONF0_THR_THRES1_EN_U_Msk = 0x8000
	// Bit THR_THRES1_EN_U.
	PCNT_U_CONF0_THR_THRES1_EN_U = 0x8000
	// Position of CH0_NEG_MODE_U field.
	PCNT_U_CONF0_CH0_NEG_MODE_U_Pos = 0x10
	// Bit mask of CH0_NEG_MODE_U field.
	PCNT_U_CONF0_CH0_NEG_MODE_U_Msk = 0x30000
	// Position of CH0_POS_MODE_U field.
	PCNT_U_CONF0_CH0_POS_MODE_U_Pos = 0x12
	// Bit mask of CH0_POS_MODE_U field.
	PCNT_U_CONF0_CH0_POS_MODE_U_Msk = 0xc0000
	// Position of CH0_HCTRL_MODE_U field.
	PCNT_U_CONF0_CH0_HCTRL_MODE_U_Pos = 0x14
	// Bit mask of CH0_HCTRL_MODE_U field.
	PCNT_U_CONF0_CH0_HCTRL_MODE_U_Msk = 0x300000
	// Position of CH0_LCTRL_MODE_U field.
	PCNT_U_CONF0_CH0_LCTRL_MODE_U_Pos = 0x16
	// Bit mask of CH0_LCTRL_MODE_U field.
	PCNT_U_CONF0_CH0_LCTRL_MODE_U_Msk = 0xc00000
	// Position of CH1_NEG_MODE_U field.
	PCNT_U_CONF0_CH1_NEG_MODE_U_Pos = 0x18
	// Bit mask of CH1_NEG_MODE_U field.
	PCNT_U_CONF0_CH1_NEG_MODE_U_Msk = 0x3000000
	// Position of CH1_POS_MODE_U field.
	PCNT_U_CONF0_CH1_POS_MODE_U_Pos = 0x1a
	// Bit mask of CH1_POS_MODE_U field.
	PCNT_U_CONF0_CH1_POS_MODE_U_Msk = 0xc000000
	// Position of CH1_HCTRL_MODE_U field.
	PCNT_U_CONF0_CH1_HCTRL_MODE_U_Pos = 0x1c
	// Bit mask of CH1_HCTRL_MODE_U field.
	PCNT_U_CONF0_CH1_HCTRL_MODE_U_Msk = 0x30000000
	// Position of CH1_LCTRL_MODE_U field.
	PCNT_U_CONF0_CH1_LCTRL_MODE_U_Pos = 0x1e
	// Bit mask of CH1_LCTRL_MODE_U field.
	PCNT_U_CONF0_CH1_LCTRL_MODE_U_Msk = 0xc0000000

	// U0_CONF1: Configuration register 1 for unit %s
	// Position of CNT_THRES0_U field.
	PCNT_U_CONF1_CNT_THRES0_U_Pos = 0x0
	// Bit mask of CNT_THRES0_U field.
	PCNT_U_CONF1_CNT_THRES0_U_Msk = 0xffff
	// Position of CNT_THRES1_U field.
	PCNT_U_CONF1_CNT_THRES1_U_Pos = 0x10
	// Bit mask of CNT_THRES1_U field.
	PCNT_U_CONF1_CNT_THRES1_U_Msk = 0xffff0000

	// U0_CONF2: Configuration register 2 for unit %s
	// Position of CNT_H_LIM_U field.
	PCNT_U_CONF2_CNT_H_LIM_U_Pos = 0x0
	// Bit mask of CNT_H_LIM_U field.
	PCNT_U_CONF2_CNT_H_LIM_U_Msk = 0xffff
	// Position of CNT_L_LIM_U field.
	PCNT_U_CONF2_CNT_L_LIM_U_Pos = 0x10
	// Bit mask of CNT_L_LIM_U field.
	PCNT_U_CONF2_CNT_L_LIM_U_Msk = 0xffff0000

	// U0_CNT: Counter value for unit %s
	// Position of PULSE_CNT_U field.
	PCNT_U_CNT_PULSE_CNT_U_Pos = 0x0
	// Bit mask of PULSE_CNT_U field.
	PCNT_U_CNT_PULSE_CNT_U_Msk = 0xffff

	// INT_RAW: Interrupt raw status register
	// Position of CNT_THR_EVENT_U0_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U0_INT_RAW_Pos = 0x0
	// Bit mask of CNT_THR_EVENT_U0_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U0_INT_RAW_Msk = 0x1
	// Bit CNT_THR_EVENT_U0_INT_RAW.
	PCNT_INT_RAW_CNT_THR_EVENT_U0_INT_RAW = 0x1
	// Position of CNT_THR_EVENT_U1_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U1_INT_RAW_Pos = 0x1
	// Bit mask of CNT_THR_EVENT_U1_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U1_INT_RAW_Msk = 0x2
	// Bit CNT_THR_EVENT_U1_INT_RAW.
	PCNT_INT_RAW_CNT_THR_EVENT_U1_INT_RAW = 0x2
	// Position of CNT_THR_EVENT_U2_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U2_INT_RAW_Pos = 0x2
	// Bit mask of CNT_THR_EVENT_U2_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U2_INT_RAW_Msk = 0x4
	// Bit CNT_THR_EVENT_U2_INT_RAW.
	PCNT_INT_RAW_CNT_THR_EVENT_U2_INT_RAW = 0x4
	// Position of CNT_THR_EVENT_U3_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U3_INT_RAW_Pos = 0x3
	// Bit mask of CNT_THR_EVENT_U3_INT_RAW field.
	PCNT_INT_RAW_CNT_THR_EVENT_U3_INT_RAW_Msk = 0x8
	// Bit CNT_THR_EVENT_U3_INT_RAW.
	PCNT_INT_RAW_CNT_THR_EVENT_U3_INT_RAW = 0x8

	// INT_ST: Interrupt status register
	// Position of CNT_THR_EVENT_U0_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U0_INT_ST_Pos = 0x0
	// Bit mask of CNT_THR_EVENT_U0_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U0_INT_ST_Msk = 0x1
	// Bit CNT_THR_EVENT_U0_INT_ST.
	PCNT_INT_ST_CNT_THR_EVENT_U0_INT_ST = 0x1
	// Position of CNT_THR_EVENT_U1_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U1_INT_ST_Pos = 0x1
	// Bit mask of CNT_THR_EVENT_U1_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U1_INT_ST_Msk = 0x2
	// Bit CNT_THR_EVENT_U1_INT_ST.
	PCNT_INT_ST_CNT_THR_EVENT_U1_INT_ST = 0x2
	// Position of CNT_THR_EVENT_U2_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U2_INT_ST_Pos = 0x2
	// Bit mask of CNT_THR_EVENT_U2_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U2_INT_ST_Msk = 0x4
	// Bit CNT_THR_EVENT_U2_INT_ST.
	PCNT_INT_ST_CNT_THR_EVENT_U2_INT_ST = 0x4
	// Position of CNT_THR_EVENT_U3_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U3_INT_ST_Pos = 0x3
	// Bit mask of CNT_THR_EVENT_U3_INT_ST field.
	PCNT_INT_ST_CNT_THR_EVENT_U3_INT_ST_Msk = 0x8
	// Bit CNT_THR_EVENT_U3_INT_ST.
	PCNT_INT_ST_CNT_THR_EVENT_U3_INT_ST = 0x8

	// INT_ENA: Interrupt enable register
	// Position of CNT_THR_EVENT_U0_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U0_INT_ENA_Pos = 0x0
	// Bit mask of CNT_THR_EVENT_U0_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U0_INT_ENA_Msk = 0x1
	// Bit CNT_THR_EVENT_U0_INT_ENA.
	PCNT_INT_ENA_CNT_THR_EVENT_U0_INT_ENA = 0x1
	// Position of CNT_THR_EVENT_U1_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U1_INT_ENA_Pos = 0x1
	// Bit mask of CNT_THR_EVENT_U1_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U1_INT_ENA_Msk = 0x2
	// Bit CNT_THR_EVENT_U1_INT_ENA.
	PCNT_INT_ENA_CNT_THR_EVENT_U1_INT_ENA = 0x2
	// Position of CNT_THR_EVENT_U2_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U2_INT_ENA_Pos = 0x2
	// Bit mask of CNT_THR_EVENT_U2_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U2_INT_ENA_Msk = 0x4
	// Bit CNT_THR_EVENT_U2_INT_ENA.
	PCNT_INT_ENA_CNT_THR_EVENT_U2_INT_ENA = 0x4
	// Position of CNT_THR_EVENT_U3_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U3_INT_ENA_Pos = 0x3
	// Bit mask of CNT_THR_EVENT_U3_INT_ENA field.
	PCNT_INT_ENA_CNT_THR_EVENT_U3_INT_ENA_Msk = 0x8
	// Bit CNT_THR_EVENT_U3_INT_ENA.
	PCNT_INT_ENA_CNT_THR_EVENT_U3_INT_ENA = 0x8

	// INT_CLR: Interrupt clear register
	// Position of CNT_THR_EVENT_U0_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U0_INT_CLR_Pos = 0x0
	// Bit mask of CNT_THR_EVENT_U0_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U0_INT_CLR_Msk = 0x1
	// Bit CNT_THR_EVENT_U0_INT_CLR.
	PCNT_INT_CLR_CNT_THR_EVENT_U0_INT_CLR = 0x1
	// Position of CNT_THR_EVENT_U1_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U1_INT_CLR_Pos = 0x1
	// Bit mask of CNT_THR_EVENT_U1_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U1_INT_CLR_Msk = 0x2
	// Bit CNT_THR_EVENT_U1_INT_CLR.
	PCNT_INT_CLR_CNT_THR_EVENT_U1_INT_CLR = 0x2
	// Position of CNT_THR_EVENT_U2_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U2_INT_CLR_Pos = 0x2
	// Bit mask of CNT_THR_EVENT_U2_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U2_INT_CLR_Msk = 0x4
	// Bit CNT_THR_EVENT_U2_INT_CLR.
	PCNT_INT_CLR_CNT_THR_EVENT_U2_INT_CLR = 0x4
	// Position of CNT_THR_EVENT_U3_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U3_INT_CLR_Pos = 0x3
	// Bit mask of CNT_THR_EVENT_U3_INT_CLR field.
	PCNT_INT_CLR_CNT_THR_EVENT_U3_INT_CLR_Msk = 0x8
	// Bit CNT_THR_EVENT_U3_INT_CLR.
	PCNT_INT_CLR_CNT_THR_EVENT_U3_INT_CLR = 0x8

	// U0_STATUS: PNCT UNIT%s status register
	// Position of CNT_THR_ZERO_MODE_U field.
	PCNT_U_STATUS_CNT_THR_ZERO_MODE_U_Pos = 0x0
	// Bit mask of CNT_THR_ZERO_MODE_U field.
	PCNT_U_STATUS_CNT_THR_ZERO_MODE_U_Msk = 0x3
	// Position of CNT_THR_THRES1_LAT_U field.
	PCNT_U_STATUS_CNT_THR_THRES1_LAT_U_Pos = 0x2
	// Bit mask of CNT_THR_THRES1_LAT_U field.
	PCNT_U_STATUS_CNT_THR_THRES1_LAT_U_Msk = 0x4
	// Bit CNT_THR_THRES1_LAT_U.
	PCNT_U_STATUS_CNT_THR_THRES1_LAT_U = 0x4
	// Position of CNT_THR_THRES0_LAT_U field.
	PCNT_U_STATUS_CNT_THR_THRES0_LAT_U_Pos = 0x3
	// Bit mask of CNT_THR_THRES0_LAT_U field.
	PCNT_U_STATUS_CNT_THR_THRES0_LAT_U_Msk = 0x8
	// Bit CNT_THR_THRES0_LAT_U.
	PCNT_U_STATUS_CNT_THR_THRES0_LAT_U = 0x8
	// Position of CNT_THR_L_LIM_LAT_U field.
	PCNT_U_STATUS_CNT_THR_L_LIM_LAT_U_Pos = 0x4
	// Bit mask of CNT_THR_L_LIM_LAT_U field.
	PCNT_U_STATUS_CNT_THR_L_LIM_LAT_U_Msk = 0x10
	// Bit CNT_THR_L_LIM_LAT_U.
	PCNT_U_STATUS_CNT_THR_L_LIM_LAT_U = 0x10
	// Position of CNT_THR_H_LIM_LAT_U field.
	PCNT_U_STATUS_CNT_THR_H_LIM_LAT_U_Pos = 0x5
	// Bit mask of CNT_THR_H_LIM_LAT_U field.
	PCNT_U_STATUS_CNT_THR_H_LIM_LAT_U_Msk = 0x20
	// Bit CNT_THR_H_LIM_LAT_U.
	PCNT_U_STATUS_CNT_THR_H_LIM_LAT_U = 0x20
	// Position of CNT_THR_ZERO_LAT_U field.
	PCNT_U_STATUS_CNT_THR_ZERO_LAT_U_Pos = 0x6
	// Bit mask of CNT_THR_ZERO_LAT_U field.
	PCNT_U_STATUS_CNT_THR_ZERO_LAT_U_Msk = 0x40
	// Bit CNT_THR_ZERO_LAT_U.
	PCNT_U_STATUS_CNT_THR_ZERO_LAT_U = 0x40

	// CTRL: Control register for all counters
	// Position of PULSE_CNT_RST_U0 field.
	PCNT_CTRL_PULSE_CNT_RST_U0_Pos = 0x0
	// Bit mask of PULSE_CNT_RST_U0 field.
	PCNT_CTRL_PULSE_CNT_RST_U0_Msk = 0x1
	// Bit PULSE_CNT_RST_U0.
	PCNT_CTRL_PULSE_CNT_RST_U0 = 0x1
	// Position of CNT_PAUSE_U0 field.
	PCNT_CTRL_CNT_PAUSE_U0_Pos = 0x1
	// Bit mask of CNT_PAUSE_U0 field.
	PCNT_CTRL_CNT_PAUSE_U0_Msk = 0x2
	// Bit CNT_PAUSE_U0.
	PCNT_CTRL_CNT_PAUSE_U0 = 0x2
	// Position of PULSE_CNT_RST_U1 field.
	PCNT_CTRL_PULSE_CNT_RST_U1_Pos = 0x2
	// Bit mask of PULSE_CNT_RST_U1 field.
	PCNT_CTRL_PULSE_CNT_RST_U1_Msk = 0x4
	// Bit PULSE_CNT_RST_U1.
	PCNT_CTRL_PULSE_CNT_RST_U1 = 0x4
	// Position of CNT_PAUSE_U1 field.
	PCNT_CTRL_CNT_PAUSE_U1_Pos = 0x3
	// Bit mask of CNT_PAUSE_U1 field.
	PCNT_CTRL_CNT_PAUSE_U1_Msk = 0x8
	// Bit CNT_PAUSE_U1.
	PCNT_CTRL_CNT_PAUSE_U1 = 0x8
	// Position of PULSE_CNT_RST_U2 field.
	PCNT_CTRL_PULSE_CNT_RST_U2_Pos = 0x4
	// Bit mask of PULSE_CNT_RST_U2 field.
	PCNT_CTRL_PULSE_CNT_RST_U2_Msk = 0x10
	// Bit PULSE_CNT_RST_U2.
	PCNT_CTRL_PULSE_CNT_RST_U2 = 0x10
	// Position of CNT_PAUSE_U2 field.
	PCNT_CTRL_CNT_PAUSE_U2_Pos = 0x5
	// Bit mask of CNT_PAUSE_U2 field.
	PCNT_CTRL_CNT_PAUSE_U2_Msk = 0x20
	// Bit CNT_PAUSE_U2.
	PCNT_CTRL_CNT_PAUSE_U2 = 0x20
	// Position of PULSE_CNT_RST_U3 field.
	PCNT_CTRL_PULSE_CNT_RST_U3_Pos = 0x6
	// Bit mask of PULSE_CNT_RST_U3 field.
	PCNT_CTRL_PULSE_CNT_RST_U3_Msk = 0x40
	// Bit PULSE_CNT_RST_U3.
	PCNT_CTRL_PULSE_CNT_RST_U3 = 0x40
	// Position of CNT_PAUSE_U3 field.
	PCNT_CTRL_CNT_PAUSE_U3_Pos = 0x7
	// Bit mask of CNT_PAUSE_U3 field.
	PCNT_CTRL_CNT_PAUSE_U3_Msk = 0x80
	// Bit CNT_PAUSE_U3.
	PCNT_CTRL_CNT_PAUSE_U3 = 0x80
	// Position of DALTA_CHANGE_EN_U0 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U0_Pos = 0x8
	// Bit mask of DALTA_CHANGE_EN_U0 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U0_Msk = 0x100
	// Bit DALTA_CHANGE_EN_U0.
	PCNT_CTRL_DALTA_CHANGE_EN_U0 = 0x100
	// Position of DALTA_CHANGE_EN_U1 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U1_Pos = 0x9
	// Bit mask of DALTA_CHANGE_EN_U1 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U1_Msk = 0x200
	// Bit DALTA_CHANGE_EN_U1.
	PCNT_CTRL_DALTA_CHANGE_EN_U1 = 0x200
	// Position of DALTA_CHANGE_EN_U2 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U2_Pos = 0xa
	// Bit mask of DALTA_CHANGE_EN_U2 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U2_Msk = 0x400
	// Bit DALTA_CHANGE_EN_U2.
	PCNT_CTRL_DALTA_CHANGE_EN_U2 = 0x400
	// Position of DALTA_CHANGE_EN_U3 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U3_Pos = 0xb
	// Bit mask of DALTA_CHANGE_EN_U3 field.
	PCNT_CTRL_DALTA_CHANGE_EN_U3_Msk = 0x800
	// Bit DALTA_CHANGE_EN_U3.
	PCNT_CTRL_DALTA_CHANGE_EN_U3 = 0x800
	// Position of CLK_EN field.
	PCNT_CTRL_CLK_EN_Pos = 0x10
	// Bit mask of CLK_EN field.
	PCNT_CTRL_CLK_EN_Msk = 0x10000
	// Bit CLK_EN.
	PCNT_CTRL_CLK_EN = 0x10000

	// U3_CHANGE_CONF: Configuration register for unit $n's step value.
	// Position of CNT_STEP_U3 field.
	PCNT_U3_CHANGE_CONF_CNT_STEP_U3_Pos = 0x0
	// Bit mask of CNT_STEP_U3 field.
	PCNT_U3_CHANGE_CONF_CNT_STEP_U3_Msk = 0xffff
	// Position of CNT_STEP_LIM_U3 field.
	PCNT_U3_CHANGE_CONF_CNT_STEP_LIM_U3_Pos = 0x10
	// Bit mask of CNT_STEP_LIM_U3 field.
	PCNT_U3_CHANGE_CONF_CNT_STEP_LIM_U3_Msk = 0xffff0000

	// U2_CHANGE_CONF: Configuration register for unit $n's step value.
	// Position of CNT_STEP_U2 field.
	PCNT_U2_CHANGE_CONF_CNT_STEP_U2_Pos = 0x0
	// Bit mask of CNT_STEP_U2 field.
	PCNT_U2_CHANGE_CONF_CNT_STEP_U2_Msk = 0xffff
	// Position of CNT_STEP_LIM_U2 field.
	PCNT_U2_CHANGE_CONF_CNT_STEP_LIM_U2_Pos = 0x10
	// Bit mask of CNT_STEP_LIM_U2 field.
	PCNT_U2_CHANGE_CONF_CNT_STEP_LIM_U2_Msk = 0xffff0000

	// U1_CHANGE_CONF: Configuration register for unit $n's step value.
	// Position of CNT_STEP_U1 field.
	PCNT_U1_CHANGE_CONF_CNT_STEP_U1_Pos = 0x0
	// Bit mask of CNT_STEP_U1 field.
	PCNT_U1_CHANGE_CONF_CNT_STEP_U1_Msk = 0xffff
	// Position of CNT_STEP_LIM_U1 field.
	PCNT_U1_CHANGE_CONF_CNT_STEP_LIM_U1_Pos = 0x10
	// Bit mask of CNT_STEP_LIM_U1 field.
	PCNT_U1_CHANGE_CONF_CNT_STEP_LIM_U1_Msk = 0xffff0000

	// U0_CHANGE_CONF: Configuration register for unit $n's step value.
	// Position of CNT_STEP_U0 field.
	PCNT_U0_CHANGE_CONF_CNT_STEP_U0_Pos = 0x0
	// Bit mask of CNT_STEP_U0 field.
	PCNT_U0_CHANGE_CONF_CNT_STEP_U0_Msk = 0xffff
	// Position of CNT_STEP_LIM_U0 field.
	PCNT_U0_CHANGE_CONF_CNT_STEP_LIM_U0_Pos = 0x10
	// Bit mask of CNT_STEP_LIM_U0 field.
	PCNT_U0_CHANGE_CONF_CNT_STEP_LIM_U0_Msk = 0xffff0000

	// DATE: PCNT version control register
	// Position of DATE field.
	PCNT_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	PCNT_DATE_DATE_Msk = 0xffffffff
)

// Constants for PMU: PMU Peripheral
const (
	// HP_ACTIVE_DIG_POWER: need_des
	// Position of HP_ACTIVE_DCDC_SWITCH_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_DCDC_SWITCH_PD_EN_Pos = 0x15
	// Bit mask of HP_ACTIVE_DCDC_SWITCH_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_DCDC_SWITCH_PD_EN_Msk = 0x200000
	// Bit HP_ACTIVE_DCDC_SWITCH_PD_EN.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_DCDC_SWITCH_PD_EN = 0x200000
	// Position of HP_ACTIVE_HP_MEM_DSLP field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP_Pos = 0x16
	// Bit mask of HP_ACTIVE_HP_MEM_DSLP field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP_Msk = 0x400000
	// Bit HP_ACTIVE_HP_MEM_DSLP.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_HP_MEM_DSLP = 0x400000
	// Position of HP_ACTIVE_PD_HP_MEM_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN_Pos = 0x17
	// Bit mask of HP_ACTIVE_PD_HP_MEM_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN_Msk = 0x800000
	// Bit HP_ACTIVE_PD_HP_MEM_PD_EN.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_HP_MEM_PD_EN = 0x800000
	// Position of HP_ACTIVE_PD_CNNT_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_CNNT_PD_EN_Pos = 0x1e
	// Bit mask of HP_ACTIVE_PD_CNNT_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_CNNT_PD_EN_Msk = 0x40000000
	// Bit HP_ACTIVE_PD_CNNT_PD_EN.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_CNNT_PD_EN = 0x40000000
	// Position of HP_ACTIVE_PD_TOP_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN_Pos = 0x1f
	// Bit mask of HP_ACTIVE_PD_TOP_PD_EN field.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN_Msk = 0x80000000
	// Bit HP_ACTIVE_PD_TOP_PD_EN.
	PMU_HP_ACTIVE_DIG_POWER_HP_ACTIVE_PD_TOP_PD_EN = 0x80000000

	// HP_ACTIVE_ICG_HP_FUNC: need_des
	// Position of HP_ACTIVE_DIG_ICG_FUNC_EN field.
	PMU_HP_ACTIVE_ICG_HP_FUNC_HP_ACTIVE_DIG_ICG_FUNC_EN_Pos = 0x0
	// Bit mask of HP_ACTIVE_DIG_ICG_FUNC_EN field.
	PMU_HP_ACTIVE_ICG_HP_FUNC_HP_ACTIVE_DIG_ICG_FUNC_EN_Msk = 0xffffffff

	// HP_ACTIVE_ICG_HP_APB: need_des
	// Position of HP_ACTIVE_DIG_ICG_APB_EN field.
	PMU_HP_ACTIVE_ICG_HP_APB_HP_ACTIVE_DIG_ICG_APB_EN_Pos = 0x0
	// Bit mask of HP_ACTIVE_DIG_ICG_APB_EN field.
	PMU_HP_ACTIVE_ICG_HP_APB_HP_ACTIVE_DIG_ICG_APB_EN_Msk = 0xffffffff

	// HP_ACTIVE_ICG_MODEM: need_des
	// Position of HP_ACTIVE_DIG_ICG_MODEM_CODE field.
	PMU_HP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE_Pos = 0x1e
	// Bit mask of HP_ACTIVE_DIG_ICG_MODEM_CODE field.
	PMU_HP_ACTIVE_ICG_MODEM_HP_ACTIVE_DIG_ICG_MODEM_CODE_Msk = 0xc0000000

	// HP_ACTIVE_HP_SYS_CNTL: need_des
	// Position of HP_ACTIVE_HP_POWER_DET_BYPASS field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_POWER_DET_BYPASS_Pos = 0x17
	// Bit mask of HP_ACTIVE_HP_POWER_DET_BYPASS field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_POWER_DET_BYPASS_Msk = 0x800000
	// Bit HP_ACTIVE_HP_POWER_DET_BYPASS.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_POWER_DET_BYPASS = 0x800000
	// Position of HP_ACTIVE_UART_WAKEUP_EN field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN_Pos = 0x18
	// Bit mask of HP_ACTIVE_UART_WAKEUP_EN field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN_Msk = 0x1000000
	// Bit HP_ACTIVE_UART_WAKEUP_EN.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_UART_WAKEUP_EN = 0x1000000
	// Position of HP_ACTIVE_LP_PAD_HOLD_ALL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL_Pos = 0x19
	// Bit mask of HP_ACTIVE_LP_PAD_HOLD_ALL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL_Msk = 0x2000000
	// Bit HP_ACTIVE_LP_PAD_HOLD_ALL.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_LP_PAD_HOLD_ALL = 0x2000000
	// Position of HP_ACTIVE_HP_PAD_HOLD_ALL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL_Pos = 0x1a
	// Bit mask of HP_ACTIVE_HP_PAD_HOLD_ALL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL_Msk = 0x4000000
	// Bit HP_ACTIVE_HP_PAD_HOLD_ALL.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_HP_PAD_HOLD_ALL = 0x4000000
	// Position of HP_ACTIVE_DIG_PAD_SLP_SEL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL_Pos = 0x1b
	// Bit mask of HP_ACTIVE_DIG_PAD_SLP_SEL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL_Msk = 0x8000000
	// Bit HP_ACTIVE_DIG_PAD_SLP_SEL.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAD_SLP_SEL = 0x8000000
	// Position of HP_ACTIVE_DIG_PAUSE_WDT field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT_Pos = 0x1c
	// Bit mask of HP_ACTIVE_DIG_PAUSE_WDT field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT_Msk = 0x10000000
	// Bit HP_ACTIVE_DIG_PAUSE_WDT.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_PAUSE_WDT = 0x10000000
	// Position of HP_ACTIVE_DIG_CPU_STALL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL_Pos = 0x1d
	// Bit mask of HP_ACTIVE_DIG_CPU_STALL field.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL_Msk = 0x20000000
	// Bit HP_ACTIVE_DIG_CPU_STALL.
	PMU_HP_ACTIVE_HP_SYS_CNTL_HP_ACTIVE_DIG_CPU_STALL = 0x20000000

	// HP_ACTIVE_HP_CK_POWER: need_des
	// Position of HP_ACTIVE_I2C_ISO_EN field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN_Pos = 0x15
	// Bit mask of HP_ACTIVE_I2C_ISO_EN field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN_Msk = 0x200000
	// Bit HP_ACTIVE_I2C_ISO_EN.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_ISO_EN = 0x200000
	// Position of HP_ACTIVE_I2C_RETENTION field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION_Pos = 0x16
	// Bit mask of HP_ACTIVE_I2C_RETENTION field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION_Msk = 0x400000
	// Bit HP_ACTIVE_I2C_RETENTION.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_I2C_RETENTION = 0x400000
	// Position of HP_ACTIVE_XPD_PLL_I2C field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_I2C_Pos = 0x17
	// Bit mask of HP_ACTIVE_XPD_PLL_I2C field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_I2C_Msk = 0x7800000
	// Position of HP_ACTIVE_XPD_PLL field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_Pos = 0x1b
	// Bit mask of HP_ACTIVE_XPD_PLL field.
	PMU_HP_ACTIVE_HP_CK_POWER_HP_ACTIVE_XPD_PLL_Msk = 0x78000000

	// HP_ACTIVE_BIAS: need_des
	// Position of HP_ACTIVE_DCM_VSET field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DCM_VSET_Pos = 0x12
	// Bit mask of HP_ACTIVE_DCM_VSET field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DCM_VSET_Msk = 0x7c0000
	// Position of HP_ACTIVE_DCM_MODE field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DCM_MODE_Pos = 0x17
	// Bit mask of HP_ACTIVE_DCM_MODE field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DCM_MODE_Msk = 0x1800000
	// Position of HP_ACTIVE_XPD_BIAS field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS_Pos = 0x19
	// Bit mask of HP_ACTIVE_XPD_BIAS field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS_Msk = 0x2000000
	// Bit HP_ACTIVE_XPD_BIAS.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_XPD_BIAS = 0x2000000
	// Position of HP_ACTIVE_DBG_ATTEN field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN_Pos = 0x1a
	// Bit mask of HP_ACTIVE_DBG_ATTEN field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_DBG_ATTEN_Msk = 0x3c000000
	// Position of HP_ACTIVE_PD_CUR field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR_Pos = 0x1e
	// Bit mask of HP_ACTIVE_PD_CUR field.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR_Msk = 0x40000000
	// Bit HP_ACTIVE_PD_CUR.
	PMU_HP_ACTIVE_BIAS_HP_ACTIVE_PD_CUR = 0x40000000
	// Position of SLEEP field.
	PMU_HP_ACTIVE_BIAS_SLEEP_Pos = 0x1f
	// Bit mask of SLEEP field.
	PMU_HP_ACTIVE_BIAS_SLEEP_Msk = 0x80000000
	// Bit SLEEP.
	PMU_HP_ACTIVE_BIAS_SLEEP = 0x80000000

	// HP_ACTIVE_BACKUP: need_des
	// Position of HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_Pos = 0x4
	// Bit mask of HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_Msk = 0x30
	// Position of HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_Pos = 0x6
	// Bit mask of HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_Msk = 0xc0
	// Position of HP_ACTIVE_RETENTION_MODE field.
	PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE_Pos = 0xa
	// Bit mask of HP_ACTIVE_RETENTION_MODE field.
	PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE_Msk = 0x400
	// Bit HP_ACTIVE_RETENTION_MODE.
	PMU_HP_ACTIVE_BACKUP_HP_ACTIVE_RETENTION_MODE = 0x400
	// Position of HP_SLEEP2ACTIVE_RETENTION_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN_Pos = 0xb
	// Bit mask of HP_SLEEP2ACTIVE_RETENTION_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN_Msk = 0x800
	// Bit HP_SLEEP2ACTIVE_RETENTION_EN.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_RETENTION_EN = 0x800
	// Position of HP_MODEM2ACTIVE_RETENTION_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN_Pos = 0xc
	// Bit mask of HP_MODEM2ACTIVE_RETENTION_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN_Msk = 0x1000
	// Bit HP_MODEM2ACTIVE_RETENTION_EN.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_RETENTION_EN = 0x1000
	// Position of HP_SLEEP2ACTIVE_BACKUP_CLK_SEL field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_Pos = 0xe
	// Bit mask of HP_SLEEP2ACTIVE_BACKUP_CLK_SEL field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_Msk = 0xc000
	// Position of HP_MODEM2ACTIVE_BACKUP_CLK_SEL field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_Pos = 0x10
	// Bit mask of HP_MODEM2ACTIVE_BACKUP_CLK_SEL field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_Msk = 0x30000
	// Position of HP_SLEEP2ACTIVE_BACKUP_MODE field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE_Pos = 0x14
	// Bit mask of HP_SLEEP2ACTIVE_BACKUP_MODE field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_MODE_Msk = 0x700000
	// Position of HP_MODEM2ACTIVE_BACKUP_MODE field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE_Pos = 0x17
	// Bit mask of HP_MODEM2ACTIVE_BACKUP_MODE field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_MODE_Msk = 0x3800000
	// Position of HP_SLEEP2ACTIVE_BACKUP_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN_Pos = 0x1d
	// Bit mask of HP_SLEEP2ACTIVE_BACKUP_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN_Msk = 0x20000000
	// Bit HP_SLEEP2ACTIVE_BACKUP_EN.
	PMU_HP_ACTIVE_BACKUP_HP_SLEEP2ACTIVE_BACKUP_EN = 0x20000000
	// Position of HP_MODEM2ACTIVE_BACKUP_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN_Pos = 0x1e
	// Bit mask of HP_MODEM2ACTIVE_BACKUP_EN field.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN_Msk = 0x40000000
	// Bit HP_MODEM2ACTIVE_BACKUP_EN.
	PMU_HP_ACTIVE_BACKUP_HP_MODEM2ACTIVE_BACKUP_EN = 0x40000000

	// HP_ACTIVE_BACKUP_CLK: need_des
	// Position of HP_ACTIVE_BACKUP_ICG_FUNC_EN field.
	PMU_HP_ACTIVE_BACKUP_CLK_HP_ACTIVE_BACKUP_ICG_FUNC_EN_Pos = 0x0
	// Bit mask of HP_ACTIVE_BACKUP_ICG_FUNC_EN field.
	PMU_HP_ACTIVE_BACKUP_CLK_HP_ACTIVE_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff

	// HP_ACTIVE_SYSCLK: need_des
	// Position of HP_ACTIVE_DIG_SYS_CLK_NO_DIV field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_Pos = 0x1a
	// Bit mask of HP_ACTIVE_DIG_SYS_CLK_NO_DIV field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000
	// Bit HP_ACTIVE_DIG_SYS_CLK_NO_DIV.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_NO_DIV = 0x4000000
	// Position of HP_ACTIVE_ICG_SYS_CLOCK_EN field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN_Pos = 0x1b
	// Bit mask of HP_ACTIVE_ICG_SYS_CLOCK_EN field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN_Msk = 0x8000000
	// Bit HP_ACTIVE_ICG_SYS_CLOCK_EN.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SYS_CLOCK_EN = 0x8000000
	// Position of HP_ACTIVE_SYS_CLK_SLP_SEL field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL_Pos = 0x1c
	// Bit mask of HP_ACTIVE_SYS_CLK_SLP_SEL field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL_Msk = 0x10000000
	// Bit HP_ACTIVE_SYS_CLK_SLP_SEL.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_SYS_CLK_SLP_SEL = 0x10000000
	// Position of HP_ACTIVE_ICG_SLP_SEL field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL_Pos = 0x1d
	// Bit mask of HP_ACTIVE_ICG_SLP_SEL field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL_Msk = 0x20000000
	// Bit HP_ACTIVE_ICG_SLP_SEL.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_ICG_SLP_SEL = 0x20000000
	// Position of HP_ACTIVE_DIG_SYS_CLK_SEL field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL_Pos = 0x1e
	// Bit mask of HP_ACTIVE_DIG_SYS_CLK_SEL field.
	PMU_HP_ACTIVE_SYSCLK_HP_ACTIVE_DIG_SYS_CLK_SEL_Msk = 0xc0000000

	// HP_ACTIVE_HP_REGULATOR0: need_des
	// Position of LP_DBIAS_VOL field.
	PMU_HP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL_Pos = 0x4
	// Bit mask of LP_DBIAS_VOL field.
	PMU_HP_ACTIVE_HP_REGULATOR0_LP_DBIAS_VOL_Msk = 0x1f0
	// Position of HP_DBIAS_VOL field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL_Pos = 0x9
	// Bit mask of HP_DBIAS_VOL field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_DBIAS_VOL_Msk = 0x3e00
	// Position of DIG_REGULATOR0_DBIAS_SEL field.
	PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL_Pos = 0xe
	// Bit mask of DIG_REGULATOR0_DBIAS_SEL field.
	PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL_Msk = 0x4000
	// Bit DIG_REGULATOR0_DBIAS_SEL.
	PMU_HP_ACTIVE_HP_REGULATOR0_DIG_REGULATOR0_DBIAS_SEL = 0x4000
	// Position of DIG_DBIAS_INIT field.
	PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT_Pos = 0xf
	// Bit mask of DIG_DBIAS_INIT field.
	PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT_Msk = 0x8000
	// Bit DIG_DBIAS_INIT.
	PMU_HP_ACTIVE_HP_REGULATOR0_DIG_DBIAS_INIT = 0x8000
	// Position of HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10
	// Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000
	// Bit HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD = 0x10000
	// Position of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11
	// Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000
	// Bit HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000
	// Position of HP_ACTIVE_HP_REGULATOR_XPD field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD_Pos = 0x12
	// Bit mask of HP_ACTIVE_HP_REGULATOR_XPD field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD_Msk = 0x40000
	// Bit HP_ACTIVE_HP_REGULATOR_XPD.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_XPD = 0x40000
	// Position of HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13
	// Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000
	// Position of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17
	// Bit mask of HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000
	// Position of HP_ACTIVE_HP_REGULATOR_DBIAS field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS_Pos = 0x1b
	// Bit mask of HP_ACTIVE_HP_REGULATOR_DBIAS field.
	PMU_HP_ACTIVE_HP_REGULATOR0_HP_ACTIVE_HP_REGULATOR_DBIAS_Msk = 0xf8000000

	// HP_ACTIVE_HP_REGULATOR1: need_des
	// Position of HP_ACTIVE_HP_REGULATOR_DRV_B field.
	PMU_HP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B_Pos = 0x1a
	// Bit mask of HP_ACTIVE_HP_REGULATOR_DRV_B field.
	PMU_HP_ACTIVE_HP_REGULATOR1_HP_ACTIVE_HP_REGULATOR_DRV_B_Msk = 0xfc000000

	// HP_ACTIVE_XTAL: need_des
	// Position of HP_ACTIVE_XPD_XTAL field.
	PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL_Pos = 0x1f
	// Bit mask of HP_ACTIVE_XPD_XTAL field.
	PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL_Msk = 0x80000000
	// Bit HP_ACTIVE_XPD_XTAL.
	PMU_HP_ACTIVE_XTAL_HP_ACTIVE_XPD_XTAL = 0x80000000

	// HP_MODEM_DIG_POWER: need_des
	// Position of HP_MODEM_DCDC_SWITCH_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_DCDC_SWITCH_PD_EN_Pos = 0x15
	// Bit mask of HP_MODEM_DCDC_SWITCH_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_DCDC_SWITCH_PD_EN_Msk = 0x200000
	// Bit HP_MODEM_DCDC_SWITCH_PD_EN.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_DCDC_SWITCH_PD_EN = 0x200000
	// Position of HP_MODEM_HP_MEM_DSLP field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP_Pos = 0x16
	// Bit mask of HP_MODEM_HP_MEM_DSLP field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP_Msk = 0x400000
	// Bit HP_MODEM_HP_MEM_DSLP.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_HP_MEM_DSLP = 0x400000
	// Position of HP_MODEM_PD_HP_MEM_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN_Pos = 0x17
	// Bit mask of HP_MODEM_PD_HP_MEM_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_MEM_PD_EN_Msk = 0x7800000
	// Position of HP_MODEM_PD_HP_WIFI_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN_Pos = 0x1b
	// Bit mask of HP_MODEM_PD_HP_WIFI_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN_Msk = 0x8000000
	// Bit HP_MODEM_PD_HP_WIFI_PD_EN.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_WIFI_PD_EN = 0x8000000
	// Position of HP_MODEM_PD_HP_CPU_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN_Pos = 0x1d
	// Bit mask of HP_MODEM_PD_HP_CPU_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN_Msk = 0x20000000
	// Bit HP_MODEM_PD_HP_CPU_PD_EN.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_HP_CPU_PD_EN = 0x20000000
	// Position of HP_MODEM_PD_CNNT_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_CNNT_PD_EN_Pos = 0x1e
	// Bit mask of HP_MODEM_PD_CNNT_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_CNNT_PD_EN_Msk = 0x40000000
	// Bit HP_MODEM_PD_CNNT_PD_EN.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_CNNT_PD_EN = 0x40000000
	// Position of HP_MODEM_PD_TOP_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN_Pos = 0x1f
	// Bit mask of HP_MODEM_PD_TOP_PD_EN field.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN_Msk = 0x80000000
	// Bit HP_MODEM_PD_TOP_PD_EN.
	PMU_HP_MODEM_DIG_POWER_HP_MODEM_PD_TOP_PD_EN = 0x80000000

	// HP_MODEM_ICG_HP_FUNC: need_des
	// Position of HP_MODEM_DIG_ICG_FUNC_EN field.
	PMU_HP_MODEM_ICG_HP_FUNC_HP_MODEM_DIG_ICG_FUNC_EN_Pos = 0x0
	// Bit mask of HP_MODEM_DIG_ICG_FUNC_EN field.
	PMU_HP_MODEM_ICG_HP_FUNC_HP_MODEM_DIG_ICG_FUNC_EN_Msk = 0xffffffff

	// HP_MODEM_ICG_HP_APB: need_des
	// Position of HP_MODEM_DIG_ICG_APB_EN field.
	PMU_HP_MODEM_ICG_HP_APB_HP_MODEM_DIG_ICG_APB_EN_Pos = 0x0
	// Bit mask of HP_MODEM_DIG_ICG_APB_EN field.
	PMU_HP_MODEM_ICG_HP_APB_HP_MODEM_DIG_ICG_APB_EN_Msk = 0xffffffff

	// HP_MODEM_ICG_MODEM: need_des
	// Position of HP_MODEM_DIG_ICG_MODEM_CODE field.
	PMU_HP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE_Pos = 0x1e
	// Bit mask of HP_MODEM_DIG_ICG_MODEM_CODE field.
	PMU_HP_MODEM_ICG_MODEM_HP_MODEM_DIG_ICG_MODEM_CODE_Msk = 0xc0000000

	// HP_MODEM_HP_SYS_CNTL: need_des
	// Position of HP_MODEM_HP_POWER_DET_BYPASS field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_POWER_DET_BYPASS_Pos = 0x17
	// Bit mask of HP_MODEM_HP_POWER_DET_BYPASS field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_POWER_DET_BYPASS_Msk = 0x800000
	// Bit HP_MODEM_HP_POWER_DET_BYPASS.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_POWER_DET_BYPASS = 0x800000
	// Position of HP_MODEM_UART_WAKEUP_EN field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN_Pos = 0x18
	// Bit mask of HP_MODEM_UART_WAKEUP_EN field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN_Msk = 0x1000000
	// Bit HP_MODEM_UART_WAKEUP_EN.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_UART_WAKEUP_EN = 0x1000000
	// Position of HP_MODEM_LP_PAD_HOLD_ALL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL_Pos = 0x19
	// Bit mask of HP_MODEM_LP_PAD_HOLD_ALL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL_Msk = 0x2000000
	// Bit HP_MODEM_LP_PAD_HOLD_ALL.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_LP_PAD_HOLD_ALL = 0x2000000
	// Position of HP_MODEM_HP_PAD_HOLD_ALL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL_Pos = 0x1a
	// Bit mask of HP_MODEM_HP_PAD_HOLD_ALL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL_Msk = 0x4000000
	// Bit HP_MODEM_HP_PAD_HOLD_ALL.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_HP_PAD_HOLD_ALL = 0x4000000
	// Position of HP_MODEM_DIG_PAD_SLP_SEL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL_Pos = 0x1b
	// Bit mask of HP_MODEM_DIG_PAD_SLP_SEL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL_Msk = 0x8000000
	// Bit HP_MODEM_DIG_PAD_SLP_SEL.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAD_SLP_SEL = 0x8000000
	// Position of HP_MODEM_DIG_PAUSE_WDT field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT_Pos = 0x1c
	// Bit mask of HP_MODEM_DIG_PAUSE_WDT field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT_Msk = 0x10000000
	// Bit HP_MODEM_DIG_PAUSE_WDT.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_PAUSE_WDT = 0x10000000
	// Position of HP_MODEM_DIG_CPU_STALL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL_Pos = 0x1d
	// Bit mask of HP_MODEM_DIG_CPU_STALL field.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL_Msk = 0x20000000
	// Bit HP_MODEM_DIG_CPU_STALL.
	PMU_HP_MODEM_HP_SYS_CNTL_HP_MODEM_DIG_CPU_STALL = 0x20000000

	// HP_MODEM_HP_CK_POWER: need_des
	// Position of HP_MODEM_I2C_ISO_EN field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN_Pos = 0x15
	// Bit mask of HP_MODEM_I2C_ISO_EN field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN_Msk = 0x200000
	// Bit HP_MODEM_I2C_ISO_EN.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_ISO_EN = 0x200000
	// Position of HP_MODEM_I2C_RETENTION field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION_Pos = 0x16
	// Bit mask of HP_MODEM_I2C_RETENTION field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION_Msk = 0x400000
	// Bit HP_MODEM_I2C_RETENTION.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_I2C_RETENTION = 0x400000
	// Position of HP_MODEM_XPD_PLL_I2C field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_I2C_Pos = 0x17
	// Bit mask of HP_MODEM_XPD_PLL_I2C field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_I2C_Msk = 0x7800000
	// Position of HP_MODEM_XPD_PLL field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_Pos = 0x1b
	// Bit mask of HP_MODEM_XPD_PLL field.
	PMU_HP_MODEM_HP_CK_POWER_HP_MODEM_XPD_PLL_Msk = 0x78000000

	// HP_MODEM_BIAS: need_des
	// Position of HP_MODEM_DCM_VSET field.
	PMU_HP_MODEM_BIAS_HP_MODEM_DCM_VSET_Pos = 0x12
	// Bit mask of HP_MODEM_DCM_VSET field.
	PMU_HP_MODEM_BIAS_HP_MODEM_DCM_VSET_Msk = 0x7c0000
	// Position of HP_MODEM_DCM_MODE field.
	PMU_HP_MODEM_BIAS_HP_MODEM_DCM_MODE_Pos = 0x17
	// Bit mask of HP_MODEM_DCM_MODE field.
	PMU_HP_MODEM_BIAS_HP_MODEM_DCM_MODE_Msk = 0x1800000
	// Position of HP_MODEM_XPD_BIAS field.
	PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS_Pos = 0x19
	// Bit mask of HP_MODEM_XPD_BIAS field.
	PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS_Msk = 0x2000000
	// Bit HP_MODEM_XPD_BIAS.
	PMU_HP_MODEM_BIAS_HP_MODEM_XPD_BIAS = 0x2000000
	// Position of HP_MODEM_DBG_ATTEN field.
	PMU_HP_MODEM_BIAS_HP_MODEM_DBG_ATTEN_Pos = 0x1a
	// Bit mask of HP_MODEM_DBG_ATTEN field.
	PMU_HP_MODEM_BIAS_HP_MODEM_DBG_ATTEN_Msk = 0x3c000000
	// Position of HP_MODEM_PD_CUR field.
	PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR_Pos = 0x1e
	// Bit mask of HP_MODEM_PD_CUR field.
	PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR_Msk = 0x40000000
	// Bit HP_MODEM_PD_CUR.
	PMU_HP_MODEM_BIAS_HP_MODEM_PD_CUR = 0x40000000
	// Position of SLEEP field.
	PMU_HP_MODEM_BIAS_SLEEP_Pos = 0x1f
	// Bit mask of SLEEP field.
	PMU_HP_MODEM_BIAS_SLEEP_Msk = 0x80000000
	// Bit SLEEP.
	PMU_HP_MODEM_BIAS_SLEEP = 0x80000000

	// HP_MODEM_BACKUP: need_des
	// Position of HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_Pos = 0x4
	// Bit mask of HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_Msk = 0x30
	// Position of HP_MODEM_RETENTION_MODE field.
	PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE_Pos = 0xa
	// Bit mask of HP_MODEM_RETENTION_MODE field.
	PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE_Msk = 0x400
	// Bit HP_MODEM_RETENTION_MODE.
	PMU_HP_MODEM_BACKUP_HP_MODEM_RETENTION_MODE = 0x400
	// Position of HP_SLEEP2MODEM_RETENTION_EN field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN_Pos = 0xb
	// Bit mask of HP_SLEEP2MODEM_RETENTION_EN field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN_Msk = 0x800
	// Bit HP_SLEEP2MODEM_RETENTION_EN.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_RETENTION_EN = 0x800
	// Position of HP_SLEEP2MODEM_BACKUP_CLK_SEL field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL_Pos = 0xe
	// Bit mask of HP_SLEEP2MODEM_BACKUP_CLK_SEL field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_CLK_SEL_Msk = 0xc000
	// Position of HP_SLEEP2MODEM_BACKUP_MODE field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE_Pos = 0x14
	// Bit mask of HP_SLEEP2MODEM_BACKUP_MODE field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_MODE_Msk = 0x700000
	// Position of HP_SLEEP2MODEM_BACKUP_EN field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN_Pos = 0x1d
	// Bit mask of HP_SLEEP2MODEM_BACKUP_EN field.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN_Msk = 0x20000000
	// Bit HP_SLEEP2MODEM_BACKUP_EN.
	PMU_HP_MODEM_BACKUP_HP_SLEEP2MODEM_BACKUP_EN = 0x20000000

	// HP_MODEM_BACKUP_CLK: need_des
	// Position of HP_MODEM_BACKUP_ICG_FUNC_EN field.
	PMU_HP_MODEM_BACKUP_CLK_HP_MODEM_BACKUP_ICG_FUNC_EN_Pos = 0x0
	// Bit mask of HP_MODEM_BACKUP_ICG_FUNC_EN field.
	PMU_HP_MODEM_BACKUP_CLK_HP_MODEM_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff

	// HP_MODEM_SYSCLK: need_des
	// Position of HP_MODEM_DIG_SYS_CLK_NO_DIV field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV_Pos = 0x1a
	// Bit mask of HP_MODEM_DIG_SYS_CLK_NO_DIV field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000
	// Bit HP_MODEM_DIG_SYS_CLK_NO_DIV.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_NO_DIV = 0x4000000
	// Position of HP_MODEM_ICG_SYS_CLOCK_EN field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN_Pos = 0x1b
	// Bit mask of HP_MODEM_ICG_SYS_CLOCK_EN field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN_Msk = 0x8000000
	// Bit HP_MODEM_ICG_SYS_CLOCK_EN.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SYS_CLOCK_EN = 0x8000000
	// Position of HP_MODEM_SYS_CLK_SLP_SEL field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL_Pos = 0x1c
	// Bit mask of HP_MODEM_SYS_CLK_SLP_SEL field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL_Msk = 0x10000000
	// Bit HP_MODEM_SYS_CLK_SLP_SEL.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_SYS_CLK_SLP_SEL = 0x10000000
	// Position of HP_MODEM_ICG_SLP_SEL field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL_Pos = 0x1d
	// Bit mask of HP_MODEM_ICG_SLP_SEL field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL_Msk = 0x20000000
	// Bit HP_MODEM_ICG_SLP_SEL.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_ICG_SLP_SEL = 0x20000000
	// Position of HP_MODEM_DIG_SYS_CLK_SEL field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL_Pos = 0x1e
	// Bit mask of HP_MODEM_DIG_SYS_CLK_SEL field.
	PMU_HP_MODEM_SYSCLK_HP_MODEM_DIG_SYS_CLK_SEL_Msk = 0xc0000000

	// HP_MODEM_HP_REGULATOR0: need_des
	// Position of HP_MODEM_HP_REGULATOR_SLP_MEM_XPD field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10
	// Bit mask of HP_MODEM_HP_REGULATOR_SLP_MEM_XPD field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000
	// Bit HP_MODEM_HP_REGULATOR_SLP_MEM_XPD.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD = 0x10000
	// Position of HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11
	// Bit mask of HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000
	// Bit HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000
	// Position of HP_MODEM_HP_REGULATOR_XPD field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD_Pos = 0x12
	// Bit mask of HP_MODEM_HP_REGULATOR_XPD field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD_Msk = 0x40000
	// Bit HP_MODEM_HP_REGULATOR_XPD.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_XPD = 0x40000
	// Position of HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13
	// Bit mask of HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000
	// Position of HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17
	// Bit mask of HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000
	// Position of HP_MODEM_HP_REGULATOR_DBIAS field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS_Pos = 0x1b
	// Bit mask of HP_MODEM_HP_REGULATOR_DBIAS field.
	PMU_HP_MODEM_HP_REGULATOR0_HP_MODEM_HP_REGULATOR_DBIAS_Msk = 0xf8000000

	// HP_MODEM_HP_REGULATOR1: need_des
	// Position of HP_MODEM_HP_REGULATOR_DRV_B field.
	PMU_HP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B_Pos = 0x8
	// Bit mask of HP_MODEM_HP_REGULATOR_DRV_B field.
	PMU_HP_MODEM_HP_REGULATOR1_HP_MODEM_HP_REGULATOR_DRV_B_Msk = 0xffffff00

	// HP_MODEM_XTAL: need_des
	// Position of HP_MODEM_XPD_XTAL field.
	PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL_Pos = 0x1f
	// Bit mask of HP_MODEM_XPD_XTAL field.
	PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL_Msk = 0x80000000
	// Bit HP_MODEM_XPD_XTAL.
	PMU_HP_MODEM_XTAL_HP_MODEM_XPD_XTAL = 0x80000000

	// HP_SLEEP_DIG_POWER: need_des
	// Position of HP_SLEEP_DCDC_SWITCH_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_DCDC_SWITCH_PD_EN_Pos = 0x15
	// Bit mask of HP_SLEEP_DCDC_SWITCH_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_DCDC_SWITCH_PD_EN_Msk = 0x200000
	// Bit HP_SLEEP_DCDC_SWITCH_PD_EN.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_DCDC_SWITCH_PD_EN = 0x200000
	// Position of HP_SLEEP_HP_MEM_DSLP field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP_Pos = 0x16
	// Bit mask of HP_SLEEP_HP_MEM_DSLP field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP_Msk = 0x400000
	// Bit HP_SLEEP_HP_MEM_DSLP.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_HP_MEM_DSLP = 0x400000
	// Position of HP_SLEEP_PD_HP_MEM_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN_Pos = 0x17
	// Bit mask of HP_SLEEP_PD_HP_MEM_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN_Msk = 0x800000
	// Bit HP_SLEEP_PD_HP_MEM_PD_EN.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_HP_MEM_PD_EN = 0x800000
	// Position of HP_SLEEP_PD_CNNT_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_CNNT_PD_EN_Pos = 0x1e
	// Bit mask of HP_SLEEP_PD_CNNT_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_CNNT_PD_EN_Msk = 0x40000000
	// Bit HP_SLEEP_PD_CNNT_PD_EN.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_CNNT_PD_EN = 0x40000000
	// Position of HP_SLEEP_PD_TOP_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN_Pos = 0x1f
	// Bit mask of HP_SLEEP_PD_TOP_PD_EN field.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN_Msk = 0x80000000
	// Bit HP_SLEEP_PD_TOP_PD_EN.
	PMU_HP_SLEEP_DIG_POWER_HP_SLEEP_PD_TOP_PD_EN = 0x80000000

	// HP_SLEEP_ICG_HP_FUNC: need_des
	// Position of HP_SLEEP_DIG_ICG_FUNC_EN field.
	PMU_HP_SLEEP_ICG_HP_FUNC_HP_SLEEP_DIG_ICG_FUNC_EN_Pos = 0x0
	// Bit mask of HP_SLEEP_DIG_ICG_FUNC_EN field.
	PMU_HP_SLEEP_ICG_HP_FUNC_HP_SLEEP_DIG_ICG_FUNC_EN_Msk = 0xffffffff

	// HP_SLEEP_ICG_HP_APB: need_des
	// Position of HP_SLEEP_DIG_ICG_APB_EN field.
	PMU_HP_SLEEP_ICG_HP_APB_HP_SLEEP_DIG_ICG_APB_EN_Pos = 0x0
	// Bit mask of HP_SLEEP_DIG_ICG_APB_EN field.
	PMU_HP_SLEEP_ICG_HP_APB_HP_SLEEP_DIG_ICG_APB_EN_Msk = 0xffffffff

	// HP_SLEEP_ICG_MODEM: need_des
	// Position of HP_SLEEP_DIG_ICG_MODEM_CODE field.
	PMU_HP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE_Pos = 0x1e
	// Bit mask of HP_SLEEP_DIG_ICG_MODEM_CODE field.
	PMU_HP_SLEEP_ICG_MODEM_HP_SLEEP_DIG_ICG_MODEM_CODE_Msk = 0xc0000000

	// HP_SLEEP_HP_SYS_CNTL: need_des
	// Position of HP_SLEEP_HP_POWER_DET_BYPASS field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_POWER_DET_BYPASS_Pos = 0x17
	// Bit mask of HP_SLEEP_HP_POWER_DET_BYPASS field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_POWER_DET_BYPASS_Msk = 0x800000
	// Bit HP_SLEEP_HP_POWER_DET_BYPASS.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_POWER_DET_BYPASS = 0x800000
	// Position of HP_SLEEP_UART_WAKEUP_EN field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN_Pos = 0x18
	// Bit mask of HP_SLEEP_UART_WAKEUP_EN field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN_Msk = 0x1000000
	// Bit HP_SLEEP_UART_WAKEUP_EN.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_UART_WAKEUP_EN = 0x1000000
	// Position of HP_SLEEP_LP_PAD_HOLD_ALL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL_Pos = 0x19
	// Bit mask of HP_SLEEP_LP_PAD_HOLD_ALL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL_Msk = 0x2000000
	// Bit HP_SLEEP_LP_PAD_HOLD_ALL.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_LP_PAD_HOLD_ALL = 0x2000000
	// Position of HP_SLEEP_HP_PAD_HOLD_ALL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL_Pos = 0x1a
	// Bit mask of HP_SLEEP_HP_PAD_HOLD_ALL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL_Msk = 0x4000000
	// Bit HP_SLEEP_HP_PAD_HOLD_ALL.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_HP_PAD_HOLD_ALL = 0x4000000
	// Position of HP_SLEEP_DIG_PAD_SLP_SEL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL_Pos = 0x1b
	// Bit mask of HP_SLEEP_DIG_PAD_SLP_SEL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL_Msk = 0x8000000
	// Bit HP_SLEEP_DIG_PAD_SLP_SEL.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAD_SLP_SEL = 0x8000000
	// Position of HP_SLEEP_DIG_PAUSE_WDT field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT_Pos = 0x1c
	// Bit mask of HP_SLEEP_DIG_PAUSE_WDT field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT_Msk = 0x10000000
	// Bit HP_SLEEP_DIG_PAUSE_WDT.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_PAUSE_WDT = 0x10000000
	// Position of HP_SLEEP_DIG_CPU_STALL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL_Pos = 0x1d
	// Bit mask of HP_SLEEP_DIG_CPU_STALL field.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL_Msk = 0x20000000
	// Bit HP_SLEEP_DIG_CPU_STALL.
	PMU_HP_SLEEP_HP_SYS_CNTL_HP_SLEEP_DIG_CPU_STALL = 0x20000000

	// HP_SLEEP_HP_CK_POWER: need_des
	// Position of HP_SLEEP_I2C_ISO_EN field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN_Pos = 0x15
	// Bit mask of HP_SLEEP_I2C_ISO_EN field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN_Msk = 0x200000
	// Bit HP_SLEEP_I2C_ISO_EN.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_ISO_EN = 0x200000
	// Position of HP_SLEEP_I2C_RETENTION field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION_Pos = 0x16
	// Bit mask of HP_SLEEP_I2C_RETENTION field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION_Msk = 0x400000
	// Bit HP_SLEEP_I2C_RETENTION.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_I2C_RETENTION = 0x400000
	// Position of HP_SLEEP_XPD_PLL_I2C field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_I2C_Pos = 0x17
	// Bit mask of HP_SLEEP_XPD_PLL_I2C field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_I2C_Msk = 0x7800000
	// Position of HP_SLEEP_XPD_PLL field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_Pos = 0x1b
	// Bit mask of HP_SLEEP_XPD_PLL field.
	PMU_HP_SLEEP_HP_CK_POWER_HP_SLEEP_XPD_PLL_Msk = 0x78000000

	// HP_SLEEP_BIAS: need_des
	// Position of HP_SLEEP_DCM_VSET field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_DCM_VSET_Pos = 0x12
	// Bit mask of HP_SLEEP_DCM_VSET field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_DCM_VSET_Msk = 0x7c0000
	// Position of HP_SLEEP_DCM_MODE field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_DCM_MODE_Pos = 0x17
	// Bit mask of HP_SLEEP_DCM_MODE field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_DCM_MODE_Msk = 0x1800000
	// Position of HP_SLEEP_XPD_BIAS field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS_Pos = 0x19
	// Bit mask of HP_SLEEP_XPD_BIAS field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS_Msk = 0x2000000
	// Bit HP_SLEEP_XPD_BIAS.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_XPD_BIAS = 0x2000000
	// Position of HP_SLEEP_DBG_ATTEN field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN_Pos = 0x1a
	// Bit mask of HP_SLEEP_DBG_ATTEN field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_DBG_ATTEN_Msk = 0x3c000000
	// Position of HP_SLEEP_PD_CUR field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR_Pos = 0x1e
	// Bit mask of HP_SLEEP_PD_CUR field.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR_Msk = 0x40000000
	// Bit HP_SLEEP_PD_CUR.
	PMU_HP_SLEEP_BIAS_HP_SLEEP_PD_CUR = 0x40000000
	// Position of SLEEP field.
	PMU_HP_SLEEP_BIAS_SLEEP_Pos = 0x1f
	// Bit mask of SLEEP field.
	PMU_HP_SLEEP_BIAS_SLEEP_Msk = 0x80000000
	// Bit SLEEP.
	PMU_HP_SLEEP_BIAS_SLEEP = 0x80000000

	// HP_SLEEP_BACKUP: need_des
	// Position of HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_Pos = 0x6
	// Bit mask of HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_Msk = 0xc0
	// Position of HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_Pos = 0x8
	// Bit mask of HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_Msk = 0x300
	// Position of HP_SLEEP_RETENTION_MODE field.
	PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE_Pos = 0xa
	// Bit mask of HP_SLEEP_RETENTION_MODE field.
	PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE_Msk = 0x400
	// Bit HP_SLEEP_RETENTION_MODE.
	PMU_HP_SLEEP_BACKUP_HP_SLEEP_RETENTION_MODE = 0x400
	// Position of HP_MODEM2SLEEP_RETENTION_EN field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN_Pos = 0xc
	// Bit mask of HP_MODEM2SLEEP_RETENTION_EN field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN_Msk = 0x1000
	// Bit HP_MODEM2SLEEP_RETENTION_EN.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_RETENTION_EN = 0x1000
	// Position of HP_ACTIVE2SLEEP_RETENTION_EN field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN_Pos = 0xd
	// Bit mask of HP_ACTIVE2SLEEP_RETENTION_EN field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN_Msk = 0x2000
	// Bit HP_ACTIVE2SLEEP_RETENTION_EN.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_RETENTION_EN = 0x2000
	// Position of HP_MODEM2SLEEP_BACKUP_CLK_SEL field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL_Pos = 0x10
	// Bit mask of HP_MODEM2SLEEP_BACKUP_CLK_SEL field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_CLK_SEL_Msk = 0x30000
	// Position of HP_ACTIVE2SLEEP_BACKUP_CLK_SEL field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_Pos = 0x12
	// Bit mask of HP_ACTIVE2SLEEP_BACKUP_CLK_SEL field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_Msk = 0xc0000
	// Position of HP_MODEM2SLEEP_BACKUP_MODE field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE_Pos = 0x17
	// Bit mask of HP_MODEM2SLEEP_BACKUP_MODE field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_MODE_Msk = 0x3800000
	// Position of HP_ACTIVE2SLEEP_BACKUP_MODE field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE_Pos = 0x1a
	// Bit mask of HP_ACTIVE2SLEEP_BACKUP_MODE field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_MODE_Msk = 0x1c000000
	// Position of HP_MODEM2SLEEP_BACKUP_EN field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN_Pos = 0x1e
	// Bit mask of HP_MODEM2SLEEP_BACKUP_EN field.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN_Msk = 0x40000000
	// Bit HP_MODEM2SLEEP_BACKUP_EN.
	PMU_HP_SLEEP_BACKUP_HP_MODEM2SLEEP_BACKUP_EN = 0x40000000
	// Position of HP_ACTIVE2SLEEP_BACKUP_EN field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN_Pos = 0x1f
	// Bit mask of HP_ACTIVE2SLEEP_BACKUP_EN field.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN_Msk = 0x80000000
	// Bit HP_ACTIVE2SLEEP_BACKUP_EN.
	PMU_HP_SLEEP_BACKUP_HP_ACTIVE2SLEEP_BACKUP_EN = 0x80000000

	// HP_SLEEP_BACKUP_CLK: need_des
	// Position of HP_SLEEP_BACKUP_ICG_FUNC_EN field.
	PMU_HP_SLEEP_BACKUP_CLK_HP_SLEEP_BACKUP_ICG_FUNC_EN_Pos = 0x0
	// Bit mask of HP_SLEEP_BACKUP_ICG_FUNC_EN field.
	PMU_HP_SLEEP_BACKUP_CLK_HP_SLEEP_BACKUP_ICG_FUNC_EN_Msk = 0xffffffff

	// HP_SLEEP_SYSCLK: need_des
	// Position of HP_SLEEP_DIG_SYS_CLK_NO_DIV field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV_Pos = 0x1a
	// Bit mask of HP_SLEEP_DIG_SYS_CLK_NO_DIV field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV_Msk = 0x4000000
	// Bit HP_SLEEP_DIG_SYS_CLK_NO_DIV.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_NO_DIV = 0x4000000
	// Position of HP_SLEEP_ICG_SYS_CLOCK_EN field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN_Pos = 0x1b
	// Bit mask of HP_SLEEP_ICG_SYS_CLOCK_EN field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN_Msk = 0x8000000
	// Bit HP_SLEEP_ICG_SYS_CLOCK_EN.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SYS_CLOCK_EN = 0x8000000
	// Position of HP_SLEEP_SYS_CLK_SLP_SEL field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL_Pos = 0x1c
	// Bit mask of HP_SLEEP_SYS_CLK_SLP_SEL field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL_Msk = 0x10000000
	// Bit HP_SLEEP_SYS_CLK_SLP_SEL.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_SYS_CLK_SLP_SEL = 0x10000000
	// Position of HP_SLEEP_ICG_SLP_SEL field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL_Pos = 0x1d
	// Bit mask of HP_SLEEP_ICG_SLP_SEL field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL_Msk = 0x20000000
	// Bit HP_SLEEP_ICG_SLP_SEL.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_ICG_SLP_SEL = 0x20000000
	// Position of HP_SLEEP_DIG_SYS_CLK_SEL field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL_Pos = 0x1e
	// Bit mask of HP_SLEEP_DIG_SYS_CLK_SEL field.
	PMU_HP_SLEEP_SYSCLK_HP_SLEEP_DIG_SYS_CLK_SEL_Msk = 0xc0000000

	// HP_SLEEP_HP_REGULATOR0: need_des
	// Position of HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_Pos = 0x10
	// Bit mask of HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_Msk = 0x10000
	// Bit HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD = 0x10000
	// Position of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_Pos = 0x11
	// Bit mask of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_Msk = 0x20000
	// Bit HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD = 0x20000
	// Position of HP_SLEEP_HP_REGULATOR_XPD field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD_Pos = 0x12
	// Bit mask of HP_SLEEP_HP_REGULATOR_XPD field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD_Msk = 0x40000
	// Bit HP_SLEEP_HP_REGULATOR_XPD.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_XPD = 0x40000
	// Position of HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_Pos = 0x13
	// Bit mask of HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_Msk = 0x780000
	// Position of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_Pos = 0x17
	// Bit mask of HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_Msk = 0x7800000
	// Position of HP_SLEEP_HP_REGULATOR_DBIAS field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS_Pos = 0x1b
	// Bit mask of HP_SLEEP_HP_REGULATOR_DBIAS field.
	PMU_HP_SLEEP_HP_REGULATOR0_HP_SLEEP_HP_REGULATOR_DBIAS_Msk = 0xf8000000

	// HP_SLEEP_HP_REGULATOR1: need_des
	// Position of HP_SLEEP_HP_REGULATOR_DRV_B field.
	PMU_HP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B_Pos = 0x1a
	// Bit mask of HP_SLEEP_HP_REGULATOR_DRV_B field.
	PMU_HP_SLEEP_HP_REGULATOR1_HP_SLEEP_HP_REGULATOR_DRV_B_Msk = 0xfc000000

	// HP_SLEEP_XTAL: need_des
	// Position of HP_SLEEP_XPD_XTAL field.
	PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL_Pos = 0x1f
	// Bit mask of HP_SLEEP_XPD_XTAL field.
	PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL_Msk = 0x80000000
	// Bit HP_SLEEP_XPD_XTAL.
	PMU_HP_SLEEP_XTAL_HP_SLEEP_XPD_XTAL = 0x80000000

	// HP_SLEEP_LP_REGULATOR0: need_des
	// Position of HP_SLEEP_LP_REGULATOR_SLP_XPD field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD_Pos = 0x15
	// Bit mask of HP_SLEEP_LP_REGULATOR_SLP_XPD field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD_Msk = 0x200000
	// Bit HP_SLEEP_LP_REGULATOR_SLP_XPD.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_XPD = 0x200000
	// Position of HP_SLEEP_LP_REGULATOR_XPD field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD_Pos = 0x16
	// Bit mask of HP_SLEEP_LP_REGULATOR_XPD field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD_Msk = 0x400000
	// Bit HP_SLEEP_LP_REGULATOR_XPD.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_XPD = 0x400000
	// Position of HP_SLEEP_LP_REGULATOR_SLP_DBIAS field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_Pos = 0x17
	// Bit mask of HP_SLEEP_LP_REGULATOR_SLP_DBIAS field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_Msk = 0x7800000
	// Position of HP_SLEEP_LP_REGULATOR_DBIAS field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS_Pos = 0x1b
	// Bit mask of HP_SLEEP_LP_REGULATOR_DBIAS field.
	PMU_HP_SLEEP_LP_REGULATOR0_HP_SLEEP_LP_REGULATOR_DBIAS_Msk = 0xf8000000

	// HP_SLEEP_LP_REGULATOR1: need_des
	// Position of HP_SLEEP_LP_REGULATOR_DRV_B field.
	PMU_HP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B_Pos = 0x1a
	// Bit mask of HP_SLEEP_LP_REGULATOR_DRV_B field.
	PMU_HP_SLEEP_LP_REGULATOR1_HP_SLEEP_LP_REGULATOR_DRV_B_Msk = 0xfc000000

	// HP_SLEEP_LP_DCDC_RESERVE: need_des
	// Position of PMU_HP_SLEEP_LP_DCDC_RESERVE field.
	PMU_HP_SLEEP_LP_DCDC_RESERVE_PMU_HP_SLEEP_LP_DCDC_RESERVE_Pos = 0x0
	// Bit mask of PMU_HP_SLEEP_LP_DCDC_RESERVE field.
	PMU_HP_SLEEP_LP_DCDC_RESERVE_PMU_HP_SLEEP_LP_DCDC_RESERVE_Msk = 0xffffffff

	// HP_SLEEP_LP_DIG_POWER: need_des
	// Position of HP_SLEEP_LP_PAD_SLP_SEL field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_PAD_SLP_SEL_Pos = 0x1a
	// Bit mask of HP_SLEEP_LP_PAD_SLP_SEL field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_PAD_SLP_SEL_Msk = 0x4000000
	// Bit HP_SLEEP_LP_PAD_SLP_SEL.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_PAD_SLP_SEL = 0x4000000
	// Position of HP_SLEEP_BOD_SOURCE_SEL field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL_Pos = 0x1b
	// Bit mask of HP_SLEEP_BOD_SOURCE_SEL field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL_Msk = 0x8000000
	// Bit HP_SLEEP_BOD_SOURCE_SEL.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_BOD_SOURCE_SEL = 0x8000000
	// Position of HP_SLEEP_VDDBAT_MODE field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE_Pos = 0x1c
	// Bit mask of HP_SLEEP_VDDBAT_MODE field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_VDDBAT_MODE_Msk = 0x30000000
	// Position of HP_SLEEP_LP_MEM_DSLP field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP_Pos = 0x1e
	// Bit mask of HP_SLEEP_LP_MEM_DSLP field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP_Msk = 0x40000000
	// Bit HP_SLEEP_LP_MEM_DSLP.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_LP_MEM_DSLP = 0x40000000
	// Position of HP_SLEEP_PD_LP_PERI_PD_EN field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN_Pos = 0x1f
	// Bit mask of HP_SLEEP_PD_LP_PERI_PD_EN field.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN_Msk = 0x80000000
	// Bit HP_SLEEP_PD_LP_PERI_PD_EN.
	PMU_HP_SLEEP_LP_DIG_POWER_HP_SLEEP_PD_LP_PERI_PD_EN = 0x80000000

	// HP_SLEEP_LP_CK_POWER: need_des
	// Position of HP_SLEEP_XPD_LPPLL field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL_Pos = 0x1b
	// Bit mask of HP_SLEEP_XPD_LPPLL field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL_Msk = 0x8000000
	// Bit HP_SLEEP_XPD_LPPLL.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_LPPLL = 0x8000000
	// Position of HP_SLEEP_XPD_XTAL32K field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K_Pos = 0x1c
	// Bit mask of HP_SLEEP_XPD_XTAL32K field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K_Msk = 0x10000000
	// Bit HP_SLEEP_XPD_XTAL32K.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_XTAL32K = 0x10000000
	// Position of HP_SLEEP_XPD_RC32K field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K_Pos = 0x1d
	// Bit mask of HP_SLEEP_XPD_RC32K field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K_Msk = 0x20000000
	// Bit HP_SLEEP_XPD_RC32K.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_RC32K = 0x20000000
	// Position of HP_SLEEP_XPD_FOSC_CLK field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK_Pos = 0x1e
	// Bit mask of HP_SLEEP_XPD_FOSC_CLK field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK_Msk = 0x40000000
	// Bit HP_SLEEP_XPD_FOSC_CLK.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_XPD_FOSC_CLK = 0x40000000
	// Position of HP_SLEEP_PD_OSC_CLK field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK_Pos = 0x1f
	// Bit mask of HP_SLEEP_PD_OSC_CLK field.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK_Msk = 0x80000000
	// Bit HP_SLEEP_PD_OSC_CLK.
	PMU_HP_SLEEP_LP_CK_POWER_HP_SLEEP_PD_OSC_CLK = 0x80000000

	// LP_SLEEP_LP_BIAS_RESERVE: need_des
	// Position of PMU_LP_SLEEP_LP_BIAS_RESERVE field.
	PMU_LP_SLEEP_LP_BIAS_RESERVE_PMU_LP_SLEEP_LP_BIAS_RESERVE_Pos = 0x0
	// Bit mask of PMU_LP_SLEEP_LP_BIAS_RESERVE field.
	PMU_LP_SLEEP_LP_BIAS_RESERVE_PMU_LP_SLEEP_LP_BIAS_RESERVE_Msk = 0xffffffff

	// LP_SLEEP_LP_REGULATOR0: need_des
	// Position of LP_SLEEP_LP_REGULATOR_SLP_XPD field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD_Pos = 0x15
	// Bit mask of LP_SLEEP_LP_REGULATOR_SLP_XPD field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD_Msk = 0x200000
	// Bit LP_SLEEP_LP_REGULATOR_SLP_XPD.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_XPD = 0x200000
	// Position of LP_SLEEP_LP_REGULATOR_XPD field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD_Pos = 0x16
	// Bit mask of LP_SLEEP_LP_REGULATOR_XPD field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD_Msk = 0x400000
	// Bit LP_SLEEP_LP_REGULATOR_XPD.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_XPD = 0x400000
	// Position of LP_SLEEP_LP_REGULATOR_SLP_DBIAS field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_Pos = 0x17
	// Bit mask of LP_SLEEP_LP_REGULATOR_SLP_DBIAS field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_Msk = 0x7800000
	// Position of LP_SLEEP_LP_REGULATOR_DBIAS field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS_Pos = 0x1b
	// Bit mask of LP_SLEEP_LP_REGULATOR_DBIAS field.
	PMU_LP_SLEEP_LP_REGULATOR0_LP_SLEEP_LP_REGULATOR_DBIAS_Msk = 0xf8000000

	// LP_SLEEP_LP_REGULATOR1: need_des
	// Position of LP_SLEEP_LP_REGULATOR_DRV_B field.
	PMU_LP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B_Pos = 0x1a
	// Bit mask of LP_SLEEP_LP_REGULATOR_DRV_B field.
	PMU_LP_SLEEP_LP_REGULATOR1_LP_SLEEP_LP_REGULATOR_DRV_B_Msk = 0xfc000000

	// LP_SLEEP_XTAL: need_des
	// Position of LP_SLEEP_XPD_XTAL field.
	PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL_Pos = 0x1f
	// Bit mask of LP_SLEEP_XPD_XTAL field.
	PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL_Msk = 0x80000000
	// Bit LP_SLEEP_XPD_XTAL.
	PMU_LP_SLEEP_XTAL_LP_SLEEP_XPD_XTAL = 0x80000000

	// LP_SLEEP_LP_DIG_POWER: need_des
	// Position of LP_SLEEP_LP_PAD_SLP_SEL field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_PAD_SLP_SEL_Pos = 0x1a
	// Bit mask of LP_SLEEP_LP_PAD_SLP_SEL field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_PAD_SLP_SEL_Msk = 0x4000000
	// Bit LP_SLEEP_LP_PAD_SLP_SEL.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_PAD_SLP_SEL = 0x4000000
	// Position of LP_SLEEP_BOD_SOURCE_SEL field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL_Pos = 0x1b
	// Bit mask of LP_SLEEP_BOD_SOURCE_SEL field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL_Msk = 0x8000000
	// Bit LP_SLEEP_BOD_SOURCE_SEL.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_BOD_SOURCE_SEL = 0x8000000
	// Position of LP_SLEEP_VDDBAT_MODE field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE_Pos = 0x1c
	// Bit mask of LP_SLEEP_VDDBAT_MODE field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_VDDBAT_MODE_Msk = 0x30000000
	// Position of LP_SLEEP_LP_MEM_DSLP field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP_Pos = 0x1e
	// Bit mask of LP_SLEEP_LP_MEM_DSLP field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP_Msk = 0x40000000
	// Bit LP_SLEEP_LP_MEM_DSLP.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_LP_MEM_DSLP = 0x40000000
	// Position of LP_SLEEP_PD_LP_PERI_PD_EN field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN_Pos = 0x1f
	// Bit mask of LP_SLEEP_PD_LP_PERI_PD_EN field.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN_Msk = 0x80000000
	// Bit LP_SLEEP_PD_LP_PERI_PD_EN.
	PMU_LP_SLEEP_LP_DIG_POWER_LP_SLEEP_PD_LP_PERI_PD_EN = 0x80000000

	// LP_SLEEP_LP_CK_POWER: need_des
	// Position of LP_SLEEP_XPD_LPPLL field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL_Pos = 0x1b
	// Bit mask of LP_SLEEP_XPD_LPPLL field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL_Msk = 0x8000000
	// Bit LP_SLEEP_XPD_LPPLL.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_LPPLL = 0x8000000
	// Position of LP_SLEEP_XPD_XTAL32K field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K_Pos = 0x1c
	// Bit mask of LP_SLEEP_XPD_XTAL32K field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K_Msk = 0x10000000
	// Bit LP_SLEEP_XPD_XTAL32K.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_XTAL32K = 0x10000000
	// Position of LP_SLEEP_XPD_RC32K field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K_Pos = 0x1d
	// Bit mask of LP_SLEEP_XPD_RC32K field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K_Msk = 0x20000000
	// Bit LP_SLEEP_XPD_RC32K.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_RC32K = 0x20000000
	// Position of LP_SLEEP_XPD_FOSC_CLK field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK_Pos = 0x1e
	// Bit mask of LP_SLEEP_XPD_FOSC_CLK field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK_Msk = 0x40000000
	// Bit LP_SLEEP_XPD_FOSC_CLK.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_XPD_FOSC_CLK = 0x40000000
	// Position of LP_SLEEP_PD_OSC_CLK field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK_Pos = 0x1f
	// Bit mask of LP_SLEEP_PD_OSC_CLK field.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK_Msk = 0x80000000
	// Bit LP_SLEEP_PD_OSC_CLK.
	PMU_LP_SLEEP_LP_CK_POWER_LP_SLEEP_PD_OSC_CLK = 0x80000000

	// LP_SLEEP_BIAS: need_des
	// Position of LP_SLEEP_XPD_BIAS field.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS_Pos = 0x19
	// Bit mask of LP_SLEEP_XPD_BIAS field.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS_Msk = 0x2000000
	// Bit LP_SLEEP_XPD_BIAS.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_XPD_BIAS = 0x2000000
	// Position of LP_SLEEP_DBG_ATTEN field.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN_Pos = 0x1a
	// Bit mask of LP_SLEEP_DBG_ATTEN field.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_DBG_ATTEN_Msk = 0x3c000000
	// Position of LP_SLEEP_PD_CUR field.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR_Pos = 0x1e
	// Bit mask of LP_SLEEP_PD_CUR field.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR_Msk = 0x40000000
	// Bit LP_SLEEP_PD_CUR.
	PMU_LP_SLEEP_BIAS_LP_SLEEP_PD_CUR = 0x40000000
	// Position of SLEEP field.
	PMU_LP_SLEEP_BIAS_SLEEP_Pos = 0x1f
	// Bit mask of SLEEP field.
	PMU_LP_SLEEP_BIAS_SLEEP_Msk = 0x80000000
	// Bit SLEEP.
	PMU_LP_SLEEP_BIAS_SLEEP = 0x80000000

	// IMM_HP_CK_POWER: need_des
	// Position of TIE_LOW_CALI_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_CALI_XTAL_ICG_Pos = 0x0
	// Bit mask of TIE_LOW_CALI_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_CALI_XTAL_ICG_Msk = 0x1
	// Bit TIE_LOW_CALI_XTAL_ICG.
	PMU_IMM_HP_CK_POWER_TIE_LOW_CALI_XTAL_ICG = 0x1
	// Position of TIE_LOW_GLOBAL_PLL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_PLL_ICG_Pos = 0x1
	// Bit mask of TIE_LOW_GLOBAL_PLL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_PLL_ICG_Msk = 0x1e
	// Position of TIE_LOW_GLOBAL_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG_Pos = 0x5
	// Bit mask of TIE_LOW_GLOBAL_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG_Msk = 0x20
	// Bit TIE_LOW_GLOBAL_XTAL_ICG.
	PMU_IMM_HP_CK_POWER_TIE_LOW_GLOBAL_XTAL_ICG = 0x20
	// Position of TIE_LOW_I2C_RETENTION field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION_Pos = 0x6
	// Bit mask of TIE_LOW_I2C_RETENTION field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION_Msk = 0x40
	// Bit TIE_LOW_I2C_RETENTION.
	PMU_IMM_HP_CK_POWER_TIE_LOW_I2C_RETENTION = 0x40
	// Position of TIE_LOW_XPD_PLL_I2C field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_PLL_I2C_Pos = 0x7
	// Bit mask of TIE_LOW_XPD_PLL_I2C field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_PLL_I2C_Msk = 0x780
	// Position of TIE_LOW_XPD_PLL field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_PLL_Pos = 0xb
	// Bit mask of TIE_LOW_XPD_PLL field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_PLL_Msk = 0x7800
	// Position of TIE_LOW_XPD_XTAL field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL_Pos = 0xf
	// Bit mask of TIE_LOW_XPD_XTAL field.
	PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL_Msk = 0x8000
	// Bit TIE_LOW_XPD_XTAL.
	PMU_IMM_HP_CK_POWER_TIE_LOW_XPD_XTAL = 0x8000
	// Position of TIE_HIGH_CALI_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_CALI_XTAL_ICG_Pos = 0x10
	// Bit mask of TIE_HIGH_CALI_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_CALI_XTAL_ICG_Msk = 0x10000
	// Bit TIE_HIGH_CALI_XTAL_ICG.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_CALI_XTAL_ICG = 0x10000
	// Position of TIE_HIGH_GLOBAL_PLL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_PLL_ICG_Pos = 0x11
	// Bit mask of TIE_HIGH_GLOBAL_PLL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_PLL_ICG_Msk = 0x1e0000
	// Position of TIE_HIGH_GLOBAL_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG_Pos = 0x15
	// Bit mask of TIE_HIGH_GLOBAL_XTAL_ICG field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG_Msk = 0x200000
	// Bit TIE_HIGH_GLOBAL_XTAL_ICG.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_GLOBAL_XTAL_ICG = 0x200000
	// Position of TIE_HIGH_I2C_RETENTION field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION_Pos = 0x16
	// Bit mask of TIE_HIGH_I2C_RETENTION field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION_Msk = 0x400000
	// Bit TIE_HIGH_I2C_RETENTION.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_I2C_RETENTION = 0x400000
	// Position of TIE_HIGH_XPD_PLL_I2C field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_I2C_Pos = 0x17
	// Bit mask of TIE_HIGH_XPD_PLL_I2C field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_I2C_Msk = 0x7800000
	// Position of TIE_HIGH_XPD_PLL field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_Pos = 0x1b
	// Bit mask of TIE_HIGH_XPD_PLL field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_PLL_Msk = 0x78000000
	// Position of TIE_HIGH_XPD_XTAL field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL_Pos = 0x1f
	// Bit mask of TIE_HIGH_XPD_XTAL field.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL_Msk = 0x80000000
	// Bit TIE_HIGH_XPD_XTAL.
	PMU_IMM_HP_CK_POWER_TIE_HIGH_XPD_XTAL = 0x80000000

	// IMM_SLEEP_SYSCLK: need_des
	// Position of UPDATE_DIG_ICG_SWITCH field.
	PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH_Pos = 0x1c
	// Bit mask of UPDATE_DIG_ICG_SWITCH field.
	PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH_Msk = 0x10000000
	// Bit UPDATE_DIG_ICG_SWITCH.
	PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_ICG_SWITCH = 0x10000000
	// Position of TIE_LOW_ICG_SLP_SEL field.
	PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL_Pos = 0x1d
	// Bit mask of TIE_LOW_ICG_SLP_SEL field.
	PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL_Msk = 0x20000000
	// Bit TIE_LOW_ICG_SLP_SEL.
	PMU_IMM_SLEEP_SYSCLK_TIE_LOW_ICG_SLP_SEL = 0x20000000
	// Position of TIE_HIGH_ICG_SLP_SEL field.
	PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL_Pos = 0x1e
	// Bit mask of TIE_HIGH_ICG_SLP_SEL field.
	PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL_Msk = 0x40000000
	// Bit TIE_HIGH_ICG_SLP_SEL.
	PMU_IMM_SLEEP_SYSCLK_TIE_HIGH_ICG_SLP_SEL = 0x40000000
	// Position of UPDATE_DIG_SYS_CLK_SEL field.
	PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL_Pos = 0x1f
	// Bit mask of UPDATE_DIG_SYS_CLK_SEL field.
	PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL_Msk = 0x80000000
	// Bit UPDATE_DIG_SYS_CLK_SEL.
	PMU_IMM_SLEEP_SYSCLK_UPDATE_DIG_SYS_CLK_SEL = 0x80000000

	// IMM_HP_FUNC_ICG: need_des
	// Position of UPDATE_DIG_ICG_FUNC_EN field.
	PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN_Pos = 0x1f
	// Bit mask of UPDATE_DIG_ICG_FUNC_EN field.
	PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN_Msk = 0x80000000
	// Bit UPDATE_DIG_ICG_FUNC_EN.
	PMU_IMM_HP_FUNC_ICG_UPDATE_DIG_ICG_FUNC_EN = 0x80000000

	// IMM_HP_APB_ICG: need_des
	// Position of UPDATE_DIG_ICG_APB_EN field.
	PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN_Pos = 0x1f
	// Bit mask of UPDATE_DIG_ICG_APB_EN field.
	PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN_Msk = 0x80000000
	// Bit UPDATE_DIG_ICG_APB_EN.
	PMU_IMM_HP_APB_ICG_UPDATE_DIG_ICG_APB_EN = 0x80000000

	// IMM_MODEM_ICG: need_des
	// Position of UPDATE_DIG_ICG_MODEM_EN field.
	PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN_Pos = 0x1f
	// Bit mask of UPDATE_DIG_ICG_MODEM_EN field.
	PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN_Msk = 0x80000000
	// Bit UPDATE_DIG_ICG_MODEM_EN.
	PMU_IMM_MODEM_ICG_UPDATE_DIG_ICG_MODEM_EN = 0x80000000

	// IMM_LP_ICG: need_des
	// Position of TIE_LOW_LP_ROOTCLK_SEL field.
	PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL_Pos = 0x1e
	// Bit mask of TIE_LOW_LP_ROOTCLK_SEL field.
	PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL_Msk = 0x40000000
	// Bit TIE_LOW_LP_ROOTCLK_SEL.
	PMU_IMM_LP_ICG_TIE_LOW_LP_ROOTCLK_SEL = 0x40000000
	// Position of TIE_HIGH_LP_ROOTCLK_SEL field.
	PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL_Pos = 0x1f
	// Bit mask of TIE_HIGH_LP_ROOTCLK_SEL field.
	PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL_Msk = 0x80000000
	// Bit TIE_HIGH_LP_ROOTCLK_SEL.
	PMU_IMM_LP_ICG_TIE_HIGH_LP_ROOTCLK_SEL = 0x80000000

	// IMM_PAD_HOLD_ALL: need_des
	// Position of PAD_SLP_SEL field.
	PMU_IMM_PAD_HOLD_ALL_PAD_SLP_SEL_Pos = 0x0
	// Bit mask of PAD_SLP_SEL field.
	PMU_IMM_PAD_HOLD_ALL_PAD_SLP_SEL_Msk = 0x1
	// Bit PAD_SLP_SEL.
	PMU_IMM_PAD_HOLD_ALL_PAD_SLP_SEL = 0x1
	// Position of LP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_LP_PAD_HOLD_ALL_Pos = 0x1
	// Bit mask of LP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_LP_PAD_HOLD_ALL_Msk = 0x2
	// Bit LP_PAD_HOLD_ALL.
	PMU_IMM_PAD_HOLD_ALL_LP_PAD_HOLD_ALL = 0x2
	// Position of HP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_HP_PAD_HOLD_ALL_Pos = 0x2
	// Bit mask of HP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_HP_PAD_HOLD_ALL_Msk = 0x4
	// Bit HP_PAD_HOLD_ALL.
	PMU_IMM_PAD_HOLD_ALL_HP_PAD_HOLD_ALL = 0x4
	// Position of TIE_HIGH_PAD_SLP_SEL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_PAD_SLP_SEL_Pos = 0x1a
	// Bit mask of TIE_HIGH_PAD_SLP_SEL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_PAD_SLP_SEL_Msk = 0x4000000
	// Bit TIE_HIGH_PAD_SLP_SEL.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_PAD_SLP_SEL = 0x4000000
	// Position of TIE_LOW_PAD_SLP_SEL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_PAD_SLP_SEL_Pos = 0x1b
	// Bit mask of TIE_LOW_PAD_SLP_SEL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_PAD_SLP_SEL_Msk = 0x8000000
	// Bit TIE_LOW_PAD_SLP_SEL.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_PAD_SLP_SEL = 0x8000000
	// Position of TIE_HIGH_LP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL_Pos = 0x1c
	// Bit mask of TIE_HIGH_LP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL_Msk = 0x10000000
	// Bit TIE_HIGH_LP_PAD_HOLD_ALL.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_LP_PAD_HOLD_ALL = 0x10000000
	// Position of TIE_LOW_LP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL_Pos = 0x1d
	// Bit mask of TIE_LOW_LP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL_Msk = 0x20000000
	// Bit TIE_LOW_LP_PAD_HOLD_ALL.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_LP_PAD_HOLD_ALL = 0x20000000
	// Position of TIE_HIGH_HP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL_Pos = 0x1e
	// Bit mask of TIE_HIGH_HP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL_Msk = 0x40000000
	// Bit TIE_HIGH_HP_PAD_HOLD_ALL.
	PMU_IMM_PAD_HOLD_ALL_TIE_HIGH_HP_PAD_HOLD_ALL = 0x40000000
	// Position of TIE_LOW_HP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL_Pos = 0x1f
	// Bit mask of TIE_LOW_HP_PAD_HOLD_ALL field.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL_Msk = 0x80000000
	// Bit TIE_LOW_HP_PAD_HOLD_ALL.
	PMU_IMM_PAD_HOLD_ALL_TIE_LOW_HP_PAD_HOLD_ALL = 0x80000000

	// IMM_I2C_ISO: need_des
	// Position of TIE_HIGH_I2C_ISO_EN field.
	PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN_Pos = 0x1e
	// Bit mask of TIE_HIGH_I2C_ISO_EN field.
	PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN_Msk = 0x40000000
	// Bit TIE_HIGH_I2C_ISO_EN.
	PMU_IMM_I2C_ISO_TIE_HIGH_I2C_ISO_EN = 0x40000000
	// Position of TIE_LOW_I2C_ISO_EN field.
	PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN_Pos = 0x1f
	// Bit mask of TIE_LOW_I2C_ISO_EN field.
	PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN_Msk = 0x80000000
	// Bit TIE_LOW_I2C_ISO_EN.
	PMU_IMM_I2C_ISO_TIE_LOW_I2C_ISO_EN = 0x80000000

	// POWER_WAIT_TIMER0: need_des
	// Position of DG_HP_POWERDOWN_TIMER field.
	PMU_POWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER_Pos = 0x5
	// Bit mask of DG_HP_POWERDOWN_TIMER field.
	PMU_POWER_WAIT_TIMER0_DG_HP_POWERDOWN_TIMER_Msk = 0x3fe0
	// Position of DG_HP_POWERUP_TIMER field.
	PMU_POWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER_Pos = 0xe
	// Bit mask of DG_HP_POWERUP_TIMER field.
	PMU_POWER_WAIT_TIMER0_DG_HP_POWERUP_TIMER_Msk = 0x7fc000
	// Position of DG_HP_WAIT_TIMER field.
	PMU_POWER_WAIT_TIMER0_DG_HP_WAIT_TIMER_Pos = 0x17
	// Bit mask of DG_HP_WAIT_TIMER field.
	PMU_POWER_WAIT_TIMER0_DG_HP_WAIT_TIMER_Msk = 0xff800000

	// POWER_WAIT_TIMER1: need_des
	// Position of DG_LP_POWERDOWN_TIMER field.
	PMU_POWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER_Pos = 0x5
	// Bit mask of DG_LP_POWERDOWN_TIMER field.
	PMU_POWER_WAIT_TIMER1_DG_LP_POWERDOWN_TIMER_Msk = 0x3fe0
	// Position of DG_LP_POWERUP_TIMER field.
	PMU_POWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER_Pos = 0xe
	// Bit mask of DG_LP_POWERUP_TIMER field.
	PMU_POWER_WAIT_TIMER1_DG_LP_POWERUP_TIMER_Msk = 0x7fc000
	// Position of DG_LP_WAIT_TIMER field.
	PMU_POWER_WAIT_TIMER1_DG_LP_WAIT_TIMER_Pos = 0x17
	// Bit mask of DG_LP_WAIT_TIMER field.
	PMU_POWER_WAIT_TIMER1_DG_LP_WAIT_TIMER_Msk = 0xff800000

	// POWER_PD_TOP_CNTL: need_des
	// Position of FORCE_TOP_RESET field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET_Pos = 0x0
	// Bit mask of FORCE_TOP_RESET field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET_Msk = 0x1
	// Bit FORCE_TOP_RESET.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_RESET = 0x1
	// Position of FORCE_TOP_ISO field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO_Pos = 0x1
	// Bit mask of FORCE_TOP_ISO field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO_Msk = 0x2
	// Bit FORCE_TOP_ISO.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_ISO = 0x2
	// Position of FORCE_TOP_PU field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU_Pos = 0x2
	// Bit mask of FORCE_TOP_PU field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU_Msk = 0x4
	// Bit FORCE_TOP_PU.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PU = 0x4
	// Position of FORCE_TOP_NO_RESET field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET_Pos = 0x3
	// Bit mask of FORCE_TOP_NO_RESET field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET_Msk = 0x8
	// Bit FORCE_TOP_NO_RESET.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_RESET = 0x8
	// Position of FORCE_TOP_NO_ISO field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO_Pos = 0x4
	// Bit mask of FORCE_TOP_NO_ISO field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO_Msk = 0x10
	// Bit FORCE_TOP_NO_ISO.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_NO_ISO = 0x10
	// Position of FORCE_TOP_PD field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD_Pos = 0x5
	// Bit mask of FORCE_TOP_PD field.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD_Msk = 0x20
	// Bit FORCE_TOP_PD.
	PMU_POWER_PD_TOP_CNTL_FORCE_TOP_PD = 0x20

	// POWER_PD_CNNT_CNTL: need_des
	// Position of FORCE_CNNT_RESET field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_RESET_Pos = 0x0
	// Bit mask of FORCE_CNNT_RESET field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_RESET_Msk = 0x1
	// Bit FORCE_CNNT_RESET.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_RESET = 0x1
	// Position of FORCE_CNNT_ISO field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_ISO_Pos = 0x1
	// Bit mask of FORCE_CNNT_ISO field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_ISO_Msk = 0x2
	// Bit FORCE_CNNT_ISO.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_ISO = 0x2
	// Position of FORCE_CNNT_PU field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_PU_Pos = 0x2
	// Bit mask of FORCE_CNNT_PU field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_PU_Msk = 0x4
	// Bit FORCE_CNNT_PU.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_PU = 0x4
	// Position of FORCE_CNNT_NO_RESET field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_NO_RESET_Pos = 0x3
	// Bit mask of FORCE_CNNT_NO_RESET field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_NO_RESET_Msk = 0x8
	// Bit FORCE_CNNT_NO_RESET.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_NO_RESET = 0x8
	// Position of FORCE_CNNT_NO_ISO field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_NO_ISO_Pos = 0x4
	// Bit mask of FORCE_CNNT_NO_ISO field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_NO_ISO_Msk = 0x10
	// Bit FORCE_CNNT_NO_ISO.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_NO_ISO = 0x10
	// Position of FORCE_CNNT_PD field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_PD_Pos = 0x5
	// Bit mask of FORCE_CNNT_PD field.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_PD_Msk = 0x20
	// Bit FORCE_CNNT_PD.
	PMU_POWER_PD_CNNT_CNTL_FORCE_CNNT_PD = 0x20

	// POWER_PD_HPMEM_CNTL: need_des
	// Position of FORCE_HP_MEM_RESET field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_RESET_Pos = 0x0
	// Bit mask of FORCE_HP_MEM_RESET field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_RESET_Msk = 0x1
	// Bit FORCE_HP_MEM_RESET.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_RESET = 0x1
	// Position of FORCE_HP_MEM_ISO field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_ISO_Pos = 0x1
	// Bit mask of FORCE_HP_MEM_ISO field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_ISO_Msk = 0x2
	// Bit FORCE_HP_MEM_ISO.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_ISO = 0x2
	// Position of FORCE_HP_MEM_PU field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PU_Pos = 0x2
	// Bit mask of FORCE_HP_MEM_PU field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PU_Msk = 0x4
	// Bit FORCE_HP_MEM_PU.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PU = 0x4
	// Position of FORCE_HP_MEM_NO_RESET field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_RESET_Pos = 0x3
	// Bit mask of FORCE_HP_MEM_NO_RESET field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_RESET_Msk = 0x8
	// Bit FORCE_HP_MEM_NO_RESET.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_RESET = 0x8
	// Position of FORCE_HP_MEM_NO_ISO field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_ISO_Pos = 0x4
	// Bit mask of FORCE_HP_MEM_NO_ISO field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_ISO_Msk = 0x10
	// Bit FORCE_HP_MEM_NO_ISO.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_NO_ISO = 0x10
	// Position of FORCE_HP_MEM_PD field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PD_Pos = 0x5
	// Bit mask of FORCE_HP_MEM_PD field.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PD_Msk = 0x20
	// Bit FORCE_HP_MEM_PD.
	PMU_POWER_PD_HPMEM_CNTL_FORCE_HP_MEM_PD = 0x20

	// POWER_PD_TOP_MASK: need_des
	// Position of XPD_TOP_MASK field.
	PMU_POWER_PD_TOP_MASK_XPD_TOP_MASK_Pos = 0x0
	// Bit mask of XPD_TOP_MASK field.
	PMU_POWER_PD_TOP_MASK_XPD_TOP_MASK_Msk = 0x1f
	// Position of PD_TOP_MASK field.
	PMU_POWER_PD_TOP_MASK_PD_TOP_MASK_Pos = 0x1b
	// Bit mask of PD_TOP_MASK field.
	PMU_POWER_PD_TOP_MASK_PD_TOP_MASK_Msk = 0xf8000000

	// POWER_PD_CNNT_MASK: need_des
	// Position of XPD_CNNT_MASK field.
	PMU_POWER_PD_CNNT_MASK_XPD_CNNT_MASK_Pos = 0x0
	// Bit mask of XPD_CNNT_MASK field.
	PMU_POWER_PD_CNNT_MASK_XPD_CNNT_MASK_Msk = 0x1f
	// Position of PD_CNNT_MASK field.
	PMU_POWER_PD_CNNT_MASK_PD_CNNT_MASK_Pos = 0x1b
	// Bit mask of PD_CNNT_MASK field.
	PMU_POWER_PD_CNNT_MASK_PD_CNNT_MASK_Msk = 0xf8000000

	// POWER_PD_HPMEM_MASK: need_des
	// Position of XPD_HP_MEM_MASK field.
	PMU_POWER_PD_HPMEM_MASK_XPD_HP_MEM_MASK_Pos = 0x0
	// Bit mask of XPD_HP_MEM_MASK field.
	PMU_POWER_PD_HPMEM_MASK_XPD_HP_MEM_MASK_Msk = 0x3f
	// Position of PD_HP_MEM_MASK field.
	PMU_POWER_PD_HPMEM_MASK_PD_HP_MEM_MASK_Pos = 0x1a
	// Bit mask of PD_HP_MEM_MASK field.
	PMU_POWER_PD_HPMEM_MASK_PD_HP_MEM_MASK_Msk = 0xfc000000

	// POWER_DCDC_SWITCH: need_des
	// Position of FORCE_DCDC_SWITCH_PU field.
	PMU_POWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PU_Pos = 0x0
	// Bit mask of FORCE_DCDC_SWITCH_PU field.
	PMU_POWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PU_Msk = 0x1
	// Bit FORCE_DCDC_SWITCH_PU.
	PMU_POWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PU = 0x1
	// Position of FORCE_DCDC_SWITCH_PD field.
	PMU_POWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PD_Pos = 0x1
	// Bit mask of FORCE_DCDC_SWITCH_PD field.
	PMU_POWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PD_Msk = 0x2
	// Bit FORCE_DCDC_SWITCH_PD.
	PMU_POWER_DCDC_SWITCH_FORCE_DCDC_SWITCH_PD = 0x2

	// POWER_PD_LPPERI_CNTL: need_des
	// Position of FORCE_LP_PERI_RESET field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET_Pos = 0x0
	// Bit mask of FORCE_LP_PERI_RESET field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET_Msk = 0x1
	// Bit FORCE_LP_PERI_RESET.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_RESET = 0x1
	// Position of FORCE_LP_PERI_ISO field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO_Pos = 0x1
	// Bit mask of FORCE_LP_PERI_ISO field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO_Msk = 0x2
	// Bit FORCE_LP_PERI_ISO.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_ISO = 0x2
	// Position of FORCE_LP_PERI_PU field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU_Pos = 0x2
	// Bit mask of FORCE_LP_PERI_PU field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU_Msk = 0x4
	// Bit FORCE_LP_PERI_PU.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PU = 0x4
	// Position of FORCE_LP_PERI_NO_RESET field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET_Pos = 0x3
	// Bit mask of FORCE_LP_PERI_NO_RESET field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET_Msk = 0x8
	// Bit FORCE_LP_PERI_NO_RESET.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_RESET = 0x8
	// Position of FORCE_LP_PERI_NO_ISO field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO_Pos = 0x4
	// Bit mask of FORCE_LP_PERI_NO_ISO field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO_Msk = 0x10
	// Bit FORCE_LP_PERI_NO_ISO.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_NO_ISO = 0x10
	// Position of FORCE_LP_PERI_PD field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD_Pos = 0x5
	// Bit mask of FORCE_LP_PERI_PD field.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD_Msk = 0x20
	// Bit FORCE_LP_PERI_PD.
	PMU_POWER_PD_LPPERI_CNTL_FORCE_LP_PERI_PD = 0x20

	// POWER_PD_LPPERI_MASK: need_des
	// Position of XPD_LP_PERI_MASK field.
	PMU_POWER_PD_LPPERI_MASK_XPD_LP_PERI_MASK_Pos = 0x0
	// Bit mask of XPD_LP_PERI_MASK field.
	PMU_POWER_PD_LPPERI_MASK_XPD_LP_PERI_MASK_Msk = 0x1f
	// Position of PD_LP_PERI_MASK field.
	PMU_POWER_PD_LPPERI_MASK_PD_LP_PERI_MASK_Pos = 0x1b
	// Bit mask of PD_LP_PERI_MASK field.
	PMU_POWER_PD_LPPERI_MASK_PD_LP_PERI_MASK_Msk = 0xf8000000

	// POWER_HP_PAD: need_des
	// Position of FORCE_HP_PAD_NO_ISO_ALL field.
	PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL_Pos = 0x0
	// Bit mask of FORCE_HP_PAD_NO_ISO_ALL field.
	PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL_Msk = 0x1
	// Bit FORCE_HP_PAD_NO_ISO_ALL.
	PMU_POWER_HP_PAD_FORCE_HP_PAD_NO_ISO_ALL = 0x1
	// Position of FORCE_HP_PAD_ISO_ALL field.
	PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL_Pos = 0x1
	// Bit mask of FORCE_HP_PAD_ISO_ALL field.
	PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL_Msk = 0x2
	// Bit FORCE_HP_PAD_ISO_ALL.
	PMU_POWER_HP_PAD_FORCE_HP_PAD_ISO_ALL = 0x2

	// POWER_CK_WAIT_CNTL: need_des
	// Position of PMU_WAIT_XTL_STABLE field.
	PMU_POWER_CK_WAIT_CNTL_PMU_WAIT_XTL_STABLE_Pos = 0x0
	// Bit mask of PMU_WAIT_XTL_STABLE field.
	PMU_POWER_CK_WAIT_CNTL_PMU_WAIT_XTL_STABLE_Msk = 0xffff
	// Position of PMU_WAIT_PLL_STABLE field.
	PMU_POWER_CK_WAIT_CNTL_PMU_WAIT_PLL_STABLE_Pos = 0x10
	// Bit mask of PMU_WAIT_PLL_STABLE field.
	PMU_POWER_CK_WAIT_CNTL_PMU_WAIT_PLL_STABLE_Msk = 0xffff0000

	// SLP_WAKEUP_CNTL0: need_des
	// Position of SLEEP_REQ field.
	PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ_Pos = 0x1f
	// Bit mask of SLEEP_REQ field.
	PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ_Msk = 0x80000000
	// Bit SLEEP_REQ.
	PMU_SLP_WAKEUP_CNTL0_SLEEP_REQ = 0x80000000

	// SLP_WAKEUP_CNTL1: need_des
	// Position of SLEEP_REJECT_ENA field.
	PMU_SLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA_Pos = 0x0
	// Bit mask of SLEEP_REJECT_ENA field.
	PMU_SLP_WAKEUP_CNTL1_SLEEP_REJECT_ENA_Msk = 0x7fffffff
	// Position of SLP_REJECT_EN field.
	PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN_Pos = 0x1f
	// Bit mask of SLP_REJECT_EN field.
	PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN_Msk = 0x80000000
	// Bit SLP_REJECT_EN.
	PMU_SLP_WAKEUP_CNTL1_SLP_REJECT_EN = 0x80000000

	// SLP_WAKEUP_CNTL2: need_des
	// Position of WAKEUP_ENA field.
	PMU_SLP_WAKEUP_CNTL2_WAKEUP_ENA_Pos = 0x0
	// Bit mask of WAKEUP_ENA field.
	PMU_SLP_WAKEUP_CNTL2_WAKEUP_ENA_Msk = 0x7fffffff

	// SLP_WAKEUP_CNTL3: need_des
	// Position of LP_MIN_SLP_VAL field.
	PMU_SLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL_Pos = 0x0
	// Bit mask of LP_MIN_SLP_VAL field.
	PMU_SLP_WAKEUP_CNTL3_LP_MIN_SLP_VAL_Msk = 0xff
	// Position of HP_MIN_SLP_VAL field.
	PMU_SLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL_Pos = 0x8
	// Bit mask of HP_MIN_SLP_VAL field.
	PMU_SLP_WAKEUP_CNTL3_HP_MIN_SLP_VAL_Msk = 0xff00
	// Position of SLEEP_PRT_SEL field.
	PMU_SLP_WAKEUP_CNTL3_SLEEP_PRT_SEL_Pos = 0x10
	// Bit mask of SLEEP_PRT_SEL field.
	PMU_SLP_WAKEUP_CNTL3_SLEEP_PRT_SEL_Msk = 0x30000

	// SLP_WAKEUP_CNTL4: need_des
	// Position of SLP_REJECT_CAUSE_CLR field.
	PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR_Pos = 0x1f
	// Bit mask of SLP_REJECT_CAUSE_CLR field.
	PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR_Msk = 0x80000000
	// Bit SLP_REJECT_CAUSE_CLR.
	PMU_SLP_WAKEUP_CNTL4_SLP_REJECT_CAUSE_CLR = 0x80000000

	// SLP_WAKEUP_CNTL5: need_des
	// Position of MODEM_WAIT_TARGET field.
	PMU_SLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET_Pos = 0x0
	// Bit mask of MODEM_WAIT_TARGET field.
	PMU_SLP_WAKEUP_CNTL5_MODEM_WAIT_TARGET_Msk = 0xfffff
	// Position of LP_ANA_WAIT_TARGET field.
	PMU_SLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET_Pos = 0x18
	// Bit mask of LP_ANA_WAIT_TARGET field.
	PMU_SLP_WAKEUP_CNTL5_LP_ANA_WAIT_TARGET_Msk = 0xff000000

	// SLP_WAKEUP_CNTL6: need_des
	// Position of SOC_WAKEUP_WAIT field.
	PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_Pos = 0x0
	// Bit mask of SOC_WAKEUP_WAIT field.
	PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_Msk = 0xfffff
	// Position of SOC_WAKEUP_WAIT_CFG field.
	PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG_Pos = 0x1e
	// Bit mask of SOC_WAKEUP_WAIT_CFG field.
	PMU_SLP_WAKEUP_CNTL6_SOC_WAKEUP_WAIT_CFG_Msk = 0xc0000000

	// SLP_WAKEUP_CNTL7: need_des
	// Position of ANA_WAIT_TARGET field.
	PMU_SLP_WAKEUP_CNTL7_ANA_WAIT_TARGET_Pos = 0x10
	// Bit mask of ANA_WAIT_TARGET field.
	PMU_SLP_WAKEUP_CNTL7_ANA_WAIT_TARGET_Msk = 0xffff0000

	// SLP_WAKEUP_CNTL8: need_des
	// Position of LP_LITE_WAKEUP_ENA field.
	PMU_SLP_WAKEUP_CNTL8_LP_LITE_WAKEUP_ENA_Pos = 0x1f
	// Bit mask of LP_LITE_WAKEUP_ENA field.
	PMU_SLP_WAKEUP_CNTL8_LP_LITE_WAKEUP_ENA_Msk = 0x80000000
	// Bit LP_LITE_WAKEUP_ENA.
	PMU_SLP_WAKEUP_CNTL8_LP_LITE_WAKEUP_ENA = 0x80000000

	// SLP_WAKEUP_STATUS0: need_des
	// Position of WAKEUP_CAUSE field.
	PMU_SLP_WAKEUP_STATUS0_WAKEUP_CAUSE_Pos = 0x0
	// Bit mask of WAKEUP_CAUSE field.
	PMU_SLP_WAKEUP_STATUS0_WAKEUP_CAUSE_Msk = 0x7fffffff

	// SLP_WAKEUP_STATUS1: need_des
	// Position of REJECT_CAUSE field.
	PMU_SLP_WAKEUP_STATUS1_REJECT_CAUSE_Pos = 0x0
	// Bit mask of REJECT_CAUSE field.
	PMU_SLP_WAKEUP_STATUS1_REJECT_CAUSE_Msk = 0x7fffffff

	// SLP_WAKEUP_STATUS2: need_des
	// Position of LP_LITE_WAKEUP_CAUSE field.
	PMU_SLP_WAKEUP_STATUS2_LP_LITE_WAKEUP_CAUSE_Pos = 0x1f
	// Bit mask of LP_LITE_WAKEUP_CAUSE field.
	PMU_SLP_WAKEUP_STATUS2_LP_LITE_WAKEUP_CAUSE_Msk = 0x80000000
	// Bit LP_LITE_WAKEUP_CAUSE.
	PMU_SLP_WAKEUP_STATUS2_LP_LITE_WAKEUP_CAUSE = 0x80000000

	// HP_CK_POWERON: need_des
	// Position of I2C_POR_WAIT_TARGET field.
	PMU_HP_CK_POWERON_I2C_POR_WAIT_TARGET_Pos = 0x0
	// Bit mask of I2C_POR_WAIT_TARGET field.
	PMU_HP_CK_POWERON_I2C_POR_WAIT_TARGET_Msk = 0xff

	// HP_CK_CNTL: need_des
	// Position of MODIFY_ICG_CNTL_WAIT field.
	PMU_HP_CK_CNTL_MODIFY_ICG_CNTL_WAIT_Pos = 0x0
	// Bit mask of MODIFY_ICG_CNTL_WAIT field.
	PMU_HP_CK_CNTL_MODIFY_ICG_CNTL_WAIT_Msk = 0xff
	// Position of SWITCH_ICG_CNTL_WAIT field.
	PMU_HP_CK_CNTL_SWITCH_ICG_CNTL_WAIT_Pos = 0x8
	// Bit mask of SWITCH_ICG_CNTL_WAIT field.
	PMU_HP_CK_CNTL_SWITCH_ICG_CNTL_WAIT_Msk = 0xff00

	// POR_STATUS: need_des
	// Position of POR_DONE field.
	PMU_POR_STATUS_POR_DONE_Pos = 0x1f
	// Bit mask of POR_DONE field.
	PMU_POR_STATUS_POR_DONE_Msk = 0x80000000
	// Bit POR_DONE.
	PMU_POR_STATUS_POR_DONE = 0x80000000

	// RF_PWC: need_des
	// Position of MSPI_PHY_XPD field.
	PMU_RF_PWC_MSPI_PHY_XPD_Pos = 0x18
	// Bit mask of MSPI_PHY_XPD field.
	PMU_RF_PWC_MSPI_PHY_XPD_Msk = 0x1000000
	// Bit MSPI_PHY_XPD.
	PMU_RF_PWC_MSPI_PHY_XPD = 0x1000000
	// Position of SDIO_PLL_XPD field.
	PMU_RF_PWC_SDIO_PLL_XPD_Pos = 0x19
	// Bit mask of SDIO_PLL_XPD field.
	PMU_RF_PWC_SDIO_PLL_XPD_Msk = 0x2000000
	// Bit SDIO_PLL_XPD.
	PMU_RF_PWC_SDIO_PLL_XPD = 0x2000000
	// Position of PERIF_I2C_RSTB field.
	PMU_RF_PWC_PERIF_I2C_RSTB_Pos = 0x1a
	// Bit mask of PERIF_I2C_RSTB field.
	PMU_RF_PWC_PERIF_I2C_RSTB_Msk = 0x4000000
	// Bit PERIF_I2C_RSTB.
	PMU_RF_PWC_PERIF_I2C_RSTB = 0x4000000
	// Position of XPD_PERIF_I2C field.
	PMU_RF_PWC_XPD_PERIF_I2C_Pos = 0x1b
	// Bit mask of XPD_PERIF_I2C field.
	PMU_RF_PWC_XPD_PERIF_I2C_Msk = 0x8000000
	// Bit XPD_PERIF_I2C.
	PMU_RF_PWC_XPD_PERIF_I2C = 0x8000000
	// Position of XPD_TXRF_I2C field.
	PMU_RF_PWC_XPD_TXRF_I2C_Pos = 0x1c
	// Bit mask of XPD_TXRF_I2C field.
	PMU_RF_PWC_XPD_TXRF_I2C_Msk = 0x10000000
	// Bit XPD_TXRF_I2C.
	PMU_RF_PWC_XPD_TXRF_I2C = 0x10000000
	// Position of XPD_RFRX_PBUS field.
	PMU_RF_PWC_XPD_RFRX_PBUS_Pos = 0x1d
	// Bit mask of XPD_RFRX_PBUS field.
	PMU_RF_PWC_XPD_RFRX_PBUS_Msk = 0x20000000
	// Bit XPD_RFRX_PBUS.
	PMU_RF_PWC_XPD_RFRX_PBUS = 0x20000000
	// Position of XPD_CKGEN_I2C field.
	PMU_RF_PWC_XPD_CKGEN_I2C_Pos = 0x1e
	// Bit mask of XPD_CKGEN_I2C field.
	PMU_RF_PWC_XPD_CKGEN_I2C_Msk = 0x40000000
	// Bit XPD_CKGEN_I2C.
	PMU_RF_PWC_XPD_CKGEN_I2C = 0x40000000

	// BACKUP_CFG: need_des
	// Position of BACKUP_SYS_CLK_NO_DIV field.
	PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV_Pos = 0x1f
	// Bit mask of BACKUP_SYS_CLK_NO_DIV field.
	PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV_Msk = 0x80000000
	// Bit BACKUP_SYS_CLK_NO_DIV.
	PMU_BACKUP_CFG_BACKUP_SYS_CLK_NO_DIV = 0x80000000

	// INT_RAW: need_des
	// Position of _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW.
	PMU_INT_RAW__0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW.
	PMU_INT_RAW__0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW.
	PMU_INT_RAW__0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW.
	PMU_INT_RAW__0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW.
	PMU_INT_RAW__0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW.
	PMU_INT_RAW__0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW.
	PMU_INT_RAW__0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW.
	PMU_INT_RAW__0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW.
	PMU_INT_RAW__0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW.
	PMU_INT_RAW__0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW.
	PMU_INT_RAW__0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW field.
	PMU_INT_RAW__0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW.
	PMU_INT_RAW__0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW = 0x2000000
	// Position of LP_CPU_EXC_INT_RAW field.
	PMU_INT_RAW_LP_CPU_EXC_INT_RAW_Pos = 0x1b
	// Bit mask of LP_CPU_EXC_INT_RAW field.
	PMU_INT_RAW_LP_CPU_EXC_INT_RAW_Msk = 0x8000000
	// Bit LP_CPU_EXC_INT_RAW.
	PMU_INT_RAW_LP_CPU_EXC_INT_RAW = 0x8000000
	// Position of SDIO_IDLE_INT_RAW field.
	PMU_INT_RAW_SDIO_IDLE_INT_RAW_Pos = 0x1c
	// Bit mask of SDIO_IDLE_INT_RAW field.
	PMU_INT_RAW_SDIO_IDLE_INT_RAW_Msk = 0x10000000
	// Bit SDIO_IDLE_INT_RAW.
	PMU_INT_RAW_SDIO_IDLE_INT_RAW = 0x10000000
	// Position of SW_INT_RAW field.
	PMU_INT_RAW_SW_INT_RAW_Pos = 0x1d
	// Bit mask of SW_INT_RAW field.
	PMU_INT_RAW_SW_INT_RAW_Msk = 0x20000000
	// Bit SW_INT_RAW.
	PMU_INT_RAW_SW_INT_RAW = 0x20000000
	// Position of SOC_SLEEP_REJECT_INT_RAW field.
	PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW_Pos = 0x1e
	// Bit mask of SOC_SLEEP_REJECT_INT_RAW field.
	PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW_Msk = 0x40000000
	// Bit SOC_SLEEP_REJECT_INT_RAW.
	PMU_INT_RAW_SOC_SLEEP_REJECT_INT_RAW = 0x40000000
	// Position of SOC_WAKEUP_INT_RAW field.
	PMU_INT_RAW_SOC_WAKEUP_INT_RAW_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_RAW field.
	PMU_INT_RAW_SOC_WAKEUP_INT_RAW_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_RAW.
	PMU_INT_RAW_SOC_WAKEUP_INT_RAW = 0x80000000

	// HP_INT_ST: need_des
	// Position of _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST.
	PMU_HP_INT_ST__0P1A_CNT_TARGET0_REACH_0_HP_INT_ST = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST.
	PMU_HP_INT_ST__0P1A_CNT_TARGET1_REACH_0_HP_INT_ST = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST.
	PMU_HP_INT_ST__0P1A_CNT_TARGET0_REACH_1_HP_INT_ST = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST.
	PMU_HP_INT_ST__0P1A_CNT_TARGET1_REACH_1_HP_INT_ST = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST.
	PMU_HP_INT_ST__0P2A_CNT_TARGET0_REACH_0_HP_INT_ST = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST.
	PMU_HP_INT_ST__0P2A_CNT_TARGET1_REACH_0_HP_INT_ST = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST.
	PMU_HP_INT_ST__0P2A_CNT_TARGET0_REACH_1_HP_INT_ST = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST.
	PMU_HP_INT_ST__0P2A_CNT_TARGET1_REACH_1_HP_INT_ST = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST.
	PMU_HP_INT_ST__0P3A_CNT_TARGET0_REACH_0_HP_INT_ST = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST.
	PMU_HP_INT_ST__0P3A_CNT_TARGET1_REACH_0_HP_INT_ST = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST.
	PMU_HP_INT_ST__0P3A_CNT_TARGET0_REACH_1_HP_INT_ST = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST field.
	PMU_HP_INT_ST__0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST.
	PMU_HP_INT_ST__0P3A_CNT_TARGET1_REACH_1_HP_INT_ST = 0x2000000
	// Position of LP_CPU_EXC_INT_ST field.
	PMU_HP_INT_ST_LP_CPU_EXC_INT_ST_Pos = 0x1b
	// Bit mask of LP_CPU_EXC_INT_ST field.
	PMU_HP_INT_ST_LP_CPU_EXC_INT_ST_Msk = 0x8000000
	// Bit LP_CPU_EXC_INT_ST.
	PMU_HP_INT_ST_LP_CPU_EXC_INT_ST = 0x8000000
	// Position of SDIO_IDLE_INT_ST field.
	PMU_HP_INT_ST_SDIO_IDLE_INT_ST_Pos = 0x1c
	// Bit mask of SDIO_IDLE_INT_ST field.
	PMU_HP_INT_ST_SDIO_IDLE_INT_ST_Msk = 0x10000000
	// Bit SDIO_IDLE_INT_ST.
	PMU_HP_INT_ST_SDIO_IDLE_INT_ST = 0x10000000
	// Position of SW_INT_ST field.
	PMU_HP_INT_ST_SW_INT_ST_Pos = 0x1d
	// Bit mask of SW_INT_ST field.
	PMU_HP_INT_ST_SW_INT_ST_Msk = 0x20000000
	// Bit SW_INT_ST.
	PMU_HP_INT_ST_SW_INT_ST = 0x20000000
	// Position of SOC_SLEEP_REJECT_INT_ST field.
	PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST_Pos = 0x1e
	// Bit mask of SOC_SLEEP_REJECT_INT_ST field.
	PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST_Msk = 0x40000000
	// Bit SOC_SLEEP_REJECT_INT_ST.
	PMU_HP_INT_ST_SOC_SLEEP_REJECT_INT_ST = 0x40000000
	// Position of SOC_WAKEUP_INT_ST field.
	PMU_HP_INT_ST_SOC_WAKEUP_INT_ST_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_ST field.
	PMU_HP_INT_ST_SOC_WAKEUP_INT_ST_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_ST.
	PMU_HP_INT_ST_SOC_WAKEUP_INT_ST = 0x80000000

	// HP_INT_ENA: need_des
	// Position of _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA.
	PMU_HP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA.
	PMU_HP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA field.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA.
	PMU_HP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA = 0x2000000
	// Position of LP_CPU_EXC_INT_ENA field.
	PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA_Pos = 0x1b
	// Bit mask of LP_CPU_EXC_INT_ENA field.
	PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA_Msk = 0x8000000
	// Bit LP_CPU_EXC_INT_ENA.
	PMU_HP_INT_ENA_LP_CPU_EXC_INT_ENA = 0x8000000
	// Position of SDIO_IDLE_INT_ENA field.
	PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA_Pos = 0x1c
	// Bit mask of SDIO_IDLE_INT_ENA field.
	PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA_Msk = 0x10000000
	// Bit SDIO_IDLE_INT_ENA.
	PMU_HP_INT_ENA_SDIO_IDLE_INT_ENA = 0x10000000
	// Position of SW_INT_ENA field.
	PMU_HP_INT_ENA_SW_INT_ENA_Pos = 0x1d
	// Bit mask of SW_INT_ENA field.
	PMU_HP_INT_ENA_SW_INT_ENA_Msk = 0x20000000
	// Bit SW_INT_ENA.
	PMU_HP_INT_ENA_SW_INT_ENA = 0x20000000
	// Position of SOC_SLEEP_REJECT_INT_ENA field.
	PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA_Pos = 0x1e
	// Bit mask of SOC_SLEEP_REJECT_INT_ENA field.
	PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA_Msk = 0x40000000
	// Bit SOC_SLEEP_REJECT_INT_ENA.
	PMU_HP_INT_ENA_SOC_SLEEP_REJECT_INT_ENA = 0x40000000
	// Position of SOC_WAKEUP_INT_ENA field.
	PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_ENA field.
	PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_ENA.
	PMU_HP_INT_ENA_SOC_WAKEUP_INT_ENA = 0x80000000

	// HP_INT_CLR: need_des
	// Position of _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR.
	PMU_HP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR.
	PMU_HP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR field.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR.
	PMU_HP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR = 0x2000000
	// Position of LP_CPU_EXC_INT_CLR field.
	PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR_Pos = 0x1b
	// Bit mask of LP_CPU_EXC_INT_CLR field.
	PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR_Msk = 0x8000000
	// Bit LP_CPU_EXC_INT_CLR.
	PMU_HP_INT_CLR_LP_CPU_EXC_INT_CLR = 0x8000000
	// Position of SDIO_IDLE_INT_CLR field.
	PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR_Pos = 0x1c
	// Bit mask of SDIO_IDLE_INT_CLR field.
	PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR_Msk = 0x10000000
	// Bit SDIO_IDLE_INT_CLR.
	PMU_HP_INT_CLR_SDIO_IDLE_INT_CLR = 0x10000000
	// Position of SW_INT_CLR field.
	PMU_HP_INT_CLR_SW_INT_CLR_Pos = 0x1d
	// Bit mask of SW_INT_CLR field.
	PMU_HP_INT_CLR_SW_INT_CLR_Msk = 0x20000000
	// Bit SW_INT_CLR.
	PMU_HP_INT_CLR_SW_INT_CLR = 0x20000000
	// Position of SOC_SLEEP_REJECT_INT_CLR field.
	PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR_Pos = 0x1e
	// Bit mask of SOC_SLEEP_REJECT_INT_CLR field.
	PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR_Msk = 0x40000000
	// Bit SOC_SLEEP_REJECT_INT_CLR.
	PMU_HP_INT_CLR_SOC_SLEEP_REJECT_INT_CLR = 0x40000000
	// Position of SOC_WAKEUP_INT_CLR field.
	PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_CLR field.
	PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_CLR.
	PMU_HP_INT_CLR_SOC_WAKEUP_INT_CLR = 0x80000000

	// LP_INT_RAW: need_des
	// Position of LP_CPU_SLEEP_REJECT_INT_RAW field.
	PMU_LP_INT_RAW_LP_CPU_SLEEP_REJECT_INT_RAW_Pos = 0xd
	// Bit mask of LP_CPU_SLEEP_REJECT_INT_RAW field.
	PMU_LP_INT_RAW_LP_CPU_SLEEP_REJECT_INT_RAW_Msk = 0x2000
	// Bit LP_CPU_SLEEP_REJECT_INT_RAW.
	PMU_LP_INT_RAW_LP_CPU_SLEEP_REJECT_INT_RAW = 0x2000
	// Position of _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW.
	PMU_LP_INT_RAW__0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW.
	PMU_LP_INT_RAW__0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW field.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW.
	PMU_LP_INT_RAW__0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW = 0x2000000
	// Position of LP_CPU_WAKEUP_INT_RAW field.
	PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW_Pos = 0x1a
	// Bit mask of LP_CPU_WAKEUP_INT_RAW field.
	PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW_Msk = 0x4000000
	// Bit LP_CPU_WAKEUP_INT_RAW.
	PMU_LP_INT_RAW_LP_CPU_WAKEUP_INT_RAW = 0x4000000
	// Position of SLEEP_SWITCH_ACTIVE_END_INT_RAW field.
	PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW_Pos = 0x1b
	// Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_RAW field.
	PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW_Msk = 0x8000000
	// Bit SLEEP_SWITCH_ACTIVE_END_INT_RAW.
	PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_END_INT_RAW = 0x8000000
	// Position of ACTIVE_SWITCH_SLEEP_END_INT_RAW field.
	PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW_Pos = 0x1c
	// Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_RAW field.
	PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW_Msk = 0x10000000
	// Bit ACTIVE_SWITCH_SLEEP_END_INT_RAW.
	PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_END_INT_RAW = 0x10000000
	// Position of SLEEP_SWITCH_ACTIVE_START_INT_RAW field.
	PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW_Pos = 0x1d
	// Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_RAW field.
	PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW_Msk = 0x20000000
	// Bit SLEEP_SWITCH_ACTIVE_START_INT_RAW.
	PMU_LP_INT_RAW_SLEEP_SWITCH_ACTIVE_START_INT_RAW = 0x20000000
	// Position of ACTIVE_SWITCH_SLEEP_START_INT_RAW field.
	PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW_Pos = 0x1e
	// Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_RAW field.
	PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW_Msk = 0x40000000
	// Bit ACTIVE_SWITCH_SLEEP_START_INT_RAW.
	PMU_LP_INT_RAW_ACTIVE_SWITCH_SLEEP_START_INT_RAW = 0x40000000
	// Position of HP_SW_TRIGGER_INT_RAW field.
	PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW_Pos = 0x1f
	// Bit mask of HP_SW_TRIGGER_INT_RAW field.
	PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW_Msk = 0x80000000
	// Bit HP_SW_TRIGGER_INT_RAW.
	PMU_LP_INT_RAW_HP_SW_TRIGGER_INT_RAW = 0x80000000

	// LP_INT_ST: need_des
	// Position of LP_CPU_SLEEP_REJECT_INT_ST field.
	PMU_LP_INT_ST_LP_CPU_SLEEP_REJECT_INT_ST_Pos = 0xd
	// Bit mask of LP_CPU_SLEEP_REJECT_INT_ST field.
	PMU_LP_INT_ST_LP_CPU_SLEEP_REJECT_INT_ST_Msk = 0x2000
	// Bit LP_CPU_SLEEP_REJECT_INT_ST.
	PMU_LP_INT_ST_LP_CPU_SLEEP_REJECT_INT_ST = 0x2000
	// Position of _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST.
	PMU_LP_INT_ST__0P1A_CNT_TARGET0_REACH_0_LP_INT_ST = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST.
	PMU_LP_INT_ST__0P1A_CNT_TARGET1_REACH_0_LP_INT_ST = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST.
	PMU_LP_INT_ST__0P1A_CNT_TARGET0_REACH_1_LP_INT_ST = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST.
	PMU_LP_INT_ST__0P1A_CNT_TARGET1_REACH_1_LP_INT_ST = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST.
	PMU_LP_INT_ST__0P2A_CNT_TARGET0_REACH_0_LP_INT_ST = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST.
	PMU_LP_INT_ST__0P2A_CNT_TARGET1_REACH_0_LP_INT_ST = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST.
	PMU_LP_INT_ST__0P2A_CNT_TARGET0_REACH_1_LP_INT_ST = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST.
	PMU_LP_INT_ST__0P2A_CNT_TARGET1_REACH_1_LP_INT_ST = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST.
	PMU_LP_INT_ST__0P3A_CNT_TARGET0_REACH_0_LP_INT_ST = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST.
	PMU_LP_INT_ST__0P3A_CNT_TARGET1_REACH_0_LP_INT_ST = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST.
	PMU_LP_INT_ST__0P3A_CNT_TARGET0_REACH_1_LP_INT_ST = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST field.
	PMU_LP_INT_ST__0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST.
	PMU_LP_INT_ST__0P3A_CNT_TARGET1_REACH_1_LP_INT_ST = 0x2000000
	// Position of LP_CPU_WAKEUP_INT_ST field.
	PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST_Pos = 0x1a
	// Bit mask of LP_CPU_WAKEUP_INT_ST field.
	PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST_Msk = 0x4000000
	// Bit LP_CPU_WAKEUP_INT_ST.
	PMU_LP_INT_ST_LP_CPU_WAKEUP_INT_ST = 0x4000000
	// Position of SLEEP_SWITCH_ACTIVE_END_INT_ST field.
	PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST_Pos = 0x1b
	// Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_ST field.
	PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST_Msk = 0x8000000
	// Bit SLEEP_SWITCH_ACTIVE_END_INT_ST.
	PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_END_INT_ST = 0x8000000
	// Position of ACTIVE_SWITCH_SLEEP_END_INT_ST field.
	PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST_Pos = 0x1c
	// Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_ST field.
	PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST_Msk = 0x10000000
	// Bit ACTIVE_SWITCH_SLEEP_END_INT_ST.
	PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_END_INT_ST = 0x10000000
	// Position of SLEEP_SWITCH_ACTIVE_START_INT_ST field.
	PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST_Pos = 0x1d
	// Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_ST field.
	PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST_Msk = 0x20000000
	// Bit SLEEP_SWITCH_ACTIVE_START_INT_ST.
	PMU_LP_INT_ST_SLEEP_SWITCH_ACTIVE_START_INT_ST = 0x20000000
	// Position of ACTIVE_SWITCH_SLEEP_START_INT_ST field.
	PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST_Pos = 0x1e
	// Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_ST field.
	PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST_Msk = 0x40000000
	// Bit ACTIVE_SWITCH_SLEEP_START_INT_ST.
	PMU_LP_INT_ST_ACTIVE_SWITCH_SLEEP_START_INT_ST = 0x40000000
	// Position of HP_SW_TRIGGER_INT_ST field.
	PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST_Pos = 0x1f
	// Bit mask of HP_SW_TRIGGER_INT_ST field.
	PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST_Msk = 0x80000000
	// Bit HP_SW_TRIGGER_INT_ST.
	PMU_LP_INT_ST_HP_SW_TRIGGER_INT_ST = 0x80000000

	// LP_INT_ENA: need_des
	// Position of LP_CPU_SLEEP_REJECT_INT_ENA field.
	PMU_LP_INT_ENA_LP_CPU_SLEEP_REJECT_INT_ENA_Pos = 0xd
	// Bit mask of LP_CPU_SLEEP_REJECT_INT_ENA field.
	PMU_LP_INT_ENA_LP_CPU_SLEEP_REJECT_INT_ENA_Msk = 0x2000
	// Bit LP_CPU_SLEEP_REJECT_INT_ENA.
	PMU_LP_INT_ENA_LP_CPU_SLEEP_REJECT_INT_ENA = 0x2000
	// Position of _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA.
	PMU_LP_INT_ENA__0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA.
	PMU_LP_INT_ENA__0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA field.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA.
	PMU_LP_INT_ENA__0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA = 0x2000000
	// Position of LP_CPU_WAKEUP_INT_ENA field.
	PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA_Pos = 0x1a
	// Bit mask of LP_CPU_WAKEUP_INT_ENA field.
	PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA_Msk = 0x4000000
	// Bit LP_CPU_WAKEUP_INT_ENA.
	PMU_LP_INT_ENA_LP_CPU_WAKEUP_INT_ENA = 0x4000000
	// Position of SLEEP_SWITCH_ACTIVE_END_INT_ENA field.
	PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA_Pos = 0x1b
	// Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_ENA field.
	PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA_Msk = 0x8000000
	// Bit SLEEP_SWITCH_ACTIVE_END_INT_ENA.
	PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_END_INT_ENA = 0x8000000
	// Position of ACTIVE_SWITCH_SLEEP_END_INT_ENA field.
	PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA_Pos = 0x1c
	// Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_ENA field.
	PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA_Msk = 0x10000000
	// Bit ACTIVE_SWITCH_SLEEP_END_INT_ENA.
	PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_END_INT_ENA = 0x10000000
	// Position of SLEEP_SWITCH_ACTIVE_START_INT_ENA field.
	PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA_Pos = 0x1d
	// Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_ENA field.
	PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA_Msk = 0x20000000
	// Bit SLEEP_SWITCH_ACTIVE_START_INT_ENA.
	PMU_LP_INT_ENA_SLEEP_SWITCH_ACTIVE_START_INT_ENA = 0x20000000
	// Position of ACTIVE_SWITCH_SLEEP_START_INT_ENA field.
	PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA_Pos = 0x1e
	// Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_ENA field.
	PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA_Msk = 0x40000000
	// Bit ACTIVE_SWITCH_SLEEP_START_INT_ENA.
	PMU_LP_INT_ENA_ACTIVE_SWITCH_SLEEP_START_INT_ENA = 0x40000000
	// Position of HP_SW_TRIGGER_INT_ENA field.
	PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA_Pos = 0x1f
	// Bit mask of HP_SW_TRIGGER_INT_ENA field.
	PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA_Msk = 0x80000000
	// Bit HP_SW_TRIGGER_INT_ENA.
	PMU_LP_INT_ENA_HP_SW_TRIGGER_INT_ENA = 0x80000000

	// LP_INT_CLR: need_des
	// Position of LP_CPU_SLEEP_REJECT_LP_INT_CLR field.
	PMU_LP_INT_CLR_LP_CPU_SLEEP_REJECT_LP_INT_CLR_Pos = 0xd
	// Bit mask of LP_CPU_SLEEP_REJECT_LP_INT_CLR field.
	PMU_LP_INT_CLR_LP_CPU_SLEEP_REJECT_LP_INT_CLR_Msk = 0x2000
	// Bit LP_CPU_SLEEP_REJECT_LP_INT_CLR.
	PMU_LP_INT_CLR_LP_CPU_SLEEP_REJECT_LP_INT_CLR = 0x2000
	// Position of _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_Pos = 0xe
	// Bit mask of _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_Msk = 0x4000
	// Bit _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR = 0x4000
	// Position of _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_Pos = 0xf
	// Bit mask of _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_Msk = 0x8000
	// Bit _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR = 0x8000
	// Position of _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_Pos = 0x10
	// Bit mask of _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_Msk = 0x10000
	// Bit _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR = 0x10000
	// Position of _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_Pos = 0x11
	// Bit mask of _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_Msk = 0x20000
	// Bit _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR.
	PMU_LP_INT_CLR__0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR = 0x20000
	// Position of _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_Pos = 0x12
	// Bit mask of _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_Msk = 0x40000
	// Bit _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR = 0x40000
	// Position of _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_Pos = 0x13
	// Bit mask of _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_Msk = 0x80000
	// Bit _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR = 0x80000
	// Position of _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_Pos = 0x14
	// Bit mask of _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_Msk = 0x100000
	// Bit _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR = 0x100000
	// Position of _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_Pos = 0x15
	// Bit mask of _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_Msk = 0x200000
	// Bit _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR.
	PMU_LP_INT_CLR__0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR = 0x200000
	// Position of _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_Pos = 0x16
	// Bit mask of _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_Msk = 0x400000
	// Bit _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR = 0x400000
	// Position of _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_Pos = 0x17
	// Bit mask of _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_Msk = 0x800000
	// Bit _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR = 0x800000
	// Position of _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_Pos = 0x18
	// Bit mask of _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_Msk = 0x1000000
	// Bit _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR = 0x1000000
	// Position of _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_Pos = 0x19
	// Bit mask of _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR field.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_Msk = 0x2000000
	// Bit _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR.
	PMU_LP_INT_CLR__0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR = 0x2000000
	// Position of LP_CPU_WAKEUP_INT_CLR field.
	PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR_Pos = 0x1a
	// Bit mask of LP_CPU_WAKEUP_INT_CLR field.
	PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR_Msk = 0x4000000
	// Bit LP_CPU_WAKEUP_INT_CLR.
	PMU_LP_INT_CLR_LP_CPU_WAKEUP_INT_CLR = 0x4000000
	// Position of SLEEP_SWITCH_ACTIVE_END_INT_CLR field.
	PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR_Pos = 0x1b
	// Bit mask of SLEEP_SWITCH_ACTIVE_END_INT_CLR field.
	PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR_Msk = 0x8000000
	// Bit SLEEP_SWITCH_ACTIVE_END_INT_CLR.
	PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_END_INT_CLR = 0x8000000
	// Position of ACTIVE_SWITCH_SLEEP_END_INT_CLR field.
	PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR_Pos = 0x1c
	// Bit mask of ACTIVE_SWITCH_SLEEP_END_INT_CLR field.
	PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR_Msk = 0x10000000
	// Bit ACTIVE_SWITCH_SLEEP_END_INT_CLR.
	PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_END_INT_CLR = 0x10000000
	// Position of SLEEP_SWITCH_ACTIVE_START_INT_CLR field.
	PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR_Pos = 0x1d
	// Bit mask of SLEEP_SWITCH_ACTIVE_START_INT_CLR field.
	PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR_Msk = 0x20000000
	// Bit SLEEP_SWITCH_ACTIVE_START_INT_CLR.
	PMU_LP_INT_CLR_SLEEP_SWITCH_ACTIVE_START_INT_CLR = 0x20000000
	// Position of ACTIVE_SWITCH_SLEEP_START_INT_CLR field.
	PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR_Pos = 0x1e
	// Bit mask of ACTIVE_SWITCH_SLEEP_START_INT_CLR field.
	PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR_Msk = 0x40000000
	// Bit ACTIVE_SWITCH_SLEEP_START_INT_CLR.
	PMU_LP_INT_CLR_ACTIVE_SWITCH_SLEEP_START_INT_CLR = 0x40000000
	// Position of HP_SW_TRIGGER_INT_CLR field.
	PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR_Pos = 0x1f
	// Bit mask of HP_SW_TRIGGER_INT_CLR field.
	PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR_Msk = 0x80000000
	// Bit HP_SW_TRIGGER_INT_CLR.
	PMU_LP_INT_CLR_HP_SW_TRIGGER_INT_CLR = 0x80000000

	// LP_CPU_PWR0: need_des
	// Position of LP_CPU_WAITI_RDY field.
	PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY_Pos = 0x0
	// Bit mask of LP_CPU_WAITI_RDY field.
	PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY_Msk = 0x1
	// Bit LP_CPU_WAITI_RDY.
	PMU_LP_CPU_PWR0_LP_CPU_WAITI_RDY = 0x1
	// Position of LP_CPU_STALL_RDY field.
	PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY_Pos = 0x1
	// Bit mask of LP_CPU_STALL_RDY field.
	PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY_Msk = 0x2
	// Bit LP_CPU_STALL_RDY.
	PMU_LP_CPU_PWR0_LP_CPU_STALL_RDY = 0x2
	// Position of LP_CPU_FORCE_STALL field.
	PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL_Pos = 0x12
	// Bit mask of LP_CPU_FORCE_STALL field.
	PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL_Msk = 0x40000
	// Bit LP_CPU_FORCE_STALL.
	PMU_LP_CPU_PWR0_LP_CPU_FORCE_STALL = 0x40000
	// Position of LP_CPU_SLP_WAITI_FLAG_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN_Pos = 0x13
	// Bit mask of LP_CPU_SLP_WAITI_FLAG_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN_Msk = 0x80000
	// Bit LP_CPU_SLP_WAITI_FLAG_EN.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_WAITI_FLAG_EN = 0x80000
	// Position of LP_CPU_SLP_STALL_FLAG_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN_Pos = 0x14
	// Bit mask of LP_CPU_SLP_STALL_FLAG_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN_Msk = 0x100000
	// Bit LP_CPU_SLP_STALL_FLAG_EN.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_FLAG_EN = 0x100000
	// Position of LP_CPU_SLP_STALL_WAIT field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT_Pos = 0x15
	// Bit mask of LP_CPU_SLP_STALL_WAIT field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_WAIT_Msk = 0x1fe00000
	// Position of LP_CPU_SLP_STALL_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN_Pos = 0x1d
	// Bit mask of LP_CPU_SLP_STALL_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN_Msk = 0x20000000
	// Bit LP_CPU_SLP_STALL_EN.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_STALL_EN = 0x20000000
	// Position of LP_CPU_SLP_RESET_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN_Pos = 0x1e
	// Bit mask of LP_CPU_SLP_RESET_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN_Msk = 0x40000000
	// Bit LP_CPU_SLP_RESET_EN.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_RESET_EN = 0x40000000
	// Position of LP_CPU_SLP_BYPASS_INTR_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN_Pos = 0x1f
	// Bit mask of LP_CPU_SLP_BYPASS_INTR_EN field.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN_Msk = 0x80000000
	// Bit LP_CPU_SLP_BYPASS_INTR_EN.
	PMU_LP_CPU_PWR0_LP_CPU_SLP_BYPASS_INTR_EN = 0x80000000

	// LP_CPU_PWR1: need_des
	// Position of LP_CPU_SLEEP_REQ field.
	PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ_Pos = 0x1f
	// Bit mask of LP_CPU_SLEEP_REQ field.
	PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ_Msk = 0x80000000
	// Bit LP_CPU_SLEEP_REQ.
	PMU_LP_CPU_PWR1_LP_CPU_SLEEP_REQ = 0x80000000

	// LP_CPU_PWR2: need_des
	// Position of LP_CPU_WAKEUP_EN field.
	PMU_LP_CPU_PWR2_LP_CPU_WAKEUP_EN_Pos = 0x0
	// Bit mask of LP_CPU_WAKEUP_EN field.
	PMU_LP_CPU_PWR2_LP_CPU_WAKEUP_EN_Msk = 0x7fffffff

	// LP_CPU_PWR3: need_des
	// Position of LP_CPU_WAKEUP_CAUSE field.
	PMU_LP_CPU_PWR3_LP_CPU_WAKEUP_CAUSE_Pos = 0x0
	// Bit mask of LP_CPU_WAKEUP_CAUSE field.
	PMU_LP_CPU_PWR3_LP_CPU_WAKEUP_CAUSE_Msk = 0x7fffffff

	// LP_CPU_PWR4: need_des
	// Position of LP_CPU_REJECT_EN field.
	PMU_LP_CPU_PWR4_LP_CPU_REJECT_EN_Pos = 0x0
	// Bit mask of LP_CPU_REJECT_EN field.
	PMU_LP_CPU_PWR4_LP_CPU_REJECT_EN_Msk = 0x7fffffff

	// LP_CPU_PWR5: need_des
	// Position of LP_CPU_REJECT_CAUSE field.
	PMU_LP_CPU_PWR5_LP_CPU_REJECT_CAUSE_Pos = 0x0
	// Bit mask of LP_CPU_REJECT_CAUSE field.
	PMU_LP_CPU_PWR5_LP_CPU_REJECT_CAUSE_Msk = 0x7fffffff

	// HP_LP_CPU_COMM: need_des
	// Position of LP_TRIGGER_HP field.
	PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP_Pos = 0x1e
	// Bit mask of LP_TRIGGER_HP field.
	PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP_Msk = 0x40000000
	// Bit LP_TRIGGER_HP.
	PMU_HP_LP_CPU_COMM_LP_TRIGGER_HP = 0x40000000
	// Position of HP_TRIGGER_LP field.
	PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP_Pos = 0x1f
	// Bit mask of HP_TRIGGER_LP field.
	PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP_Msk = 0x80000000
	// Bit HP_TRIGGER_LP.
	PMU_HP_LP_CPU_COMM_HP_TRIGGER_LP = 0x80000000

	// HP_REGULATOR_CFG: need_des
	// Position of DIG_REGULATOR_EN_CAL field.
	PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL_Pos = 0x1f
	// Bit mask of DIG_REGULATOR_EN_CAL field.
	PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL_Msk = 0x80000000
	// Bit DIG_REGULATOR_EN_CAL.
	PMU_HP_REGULATOR_CFG_DIG_REGULATOR_EN_CAL = 0x80000000

	// MAIN_STATE: need_des
	// Position of ENABLE_CALI_PMU_CNTL field.
	PMU_MAIN_STATE_ENABLE_CALI_PMU_CNTL_Pos = 0x0
	// Bit mask of ENABLE_CALI_PMU_CNTL field.
	PMU_MAIN_STATE_ENABLE_CALI_PMU_CNTL_Msk = 0x1
	// Bit ENABLE_CALI_PMU_CNTL.
	PMU_MAIN_STATE_ENABLE_CALI_PMU_CNTL = 0x1
	// Position of PMU_MAIN_LAST_ST_STATE field.
	PMU_MAIN_STATE_PMU_MAIN_LAST_ST_STATE_Pos = 0xb
	// Bit mask of PMU_MAIN_LAST_ST_STATE field.
	PMU_MAIN_STATE_PMU_MAIN_LAST_ST_STATE_Msk = 0x3f800
	// Position of PMU_MAIN_TAR_ST_STATE field.
	PMU_MAIN_STATE_PMU_MAIN_TAR_ST_STATE_Pos = 0x12
	// Bit mask of PMU_MAIN_TAR_ST_STATE field.
	PMU_MAIN_STATE_PMU_MAIN_TAR_ST_STATE_Msk = 0x1fc0000
	// Position of PMU_MAIN_CUR_ST_STATE field.
	PMU_MAIN_STATE_PMU_MAIN_CUR_ST_STATE_Pos = 0x19
	// Bit mask of PMU_MAIN_CUR_ST_STATE field.
	PMU_MAIN_STATE_PMU_MAIN_CUR_ST_STATE_Msk = 0xfe000000

	// PWR_STATE: need_des
	// Position of PMU_BACKUP_ST_STATE field.
	PMU_PWR_STATE_PMU_BACKUP_ST_STATE_Pos = 0xd
	// Bit mask of PMU_BACKUP_ST_STATE field.
	PMU_PWR_STATE_PMU_BACKUP_ST_STATE_Msk = 0x3e000
	// Position of PMU_LP_PWR_ST_STATE field.
	PMU_PWR_STATE_PMU_LP_PWR_ST_STATE_Pos = 0x12
	// Bit mask of PMU_LP_PWR_ST_STATE field.
	PMU_PWR_STATE_PMU_LP_PWR_ST_STATE_Msk = 0x7c0000
	// Position of PMU_HP_PWR_ST_STATE field.
	PMU_PWR_STATE_PMU_HP_PWR_ST_STATE_Pos = 0x17
	// Bit mask of PMU_HP_PWR_ST_STATE field.
	PMU_PWR_STATE_PMU_HP_PWR_ST_STATE_Msk = 0xff800000

	// CLK_STATE0: need_des
	// Position of STABLE_XPD_PLL_STATE field.
	PMU_CLK_STATE0_STABLE_XPD_PLL_STATE_Pos = 0x0
	// Bit mask of STABLE_XPD_PLL_STATE field.
	PMU_CLK_STATE0_STABLE_XPD_PLL_STATE_Msk = 0x7
	// Position of STABLE_XPD_XTAL_STATE field.
	PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE_Pos = 0x3
	// Bit mask of STABLE_XPD_XTAL_STATE field.
	PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE_Msk = 0x8
	// Bit STABLE_XPD_XTAL_STATE.
	PMU_CLK_STATE0_STABLE_XPD_XTAL_STATE = 0x8
	// Position of PMU_ANA_XPD_PLL_I2C_STATE field.
	PMU_CLK_STATE0_PMU_ANA_XPD_PLL_I2C_STATE_Pos = 0x4
	// Bit mask of PMU_ANA_XPD_PLL_I2C_STATE field.
	PMU_CLK_STATE0_PMU_ANA_XPD_PLL_I2C_STATE_Msk = 0x70
	// Position of PMU_SYS_CLK_SLP_SEL_STATE field.
	PMU_CLK_STATE0_PMU_SYS_CLK_SLP_SEL_STATE_Pos = 0xa
	// Bit mask of PMU_SYS_CLK_SLP_SEL_STATE field.
	PMU_CLK_STATE0_PMU_SYS_CLK_SLP_SEL_STATE_Msk = 0x400
	// Bit PMU_SYS_CLK_SLP_SEL_STATE.
	PMU_CLK_STATE0_PMU_SYS_CLK_SLP_SEL_STATE = 0x400
	// Position of PMU_SYS_CLK_SEL_STATE field.
	PMU_CLK_STATE0_PMU_SYS_CLK_SEL_STATE_Pos = 0xb
	// Bit mask of PMU_SYS_CLK_SEL_STATE field.
	PMU_CLK_STATE0_PMU_SYS_CLK_SEL_STATE_Msk = 0x1800
	// Position of PMU_SYS_CLK_NO_DIV_STATE field.
	PMU_CLK_STATE0_PMU_SYS_CLK_NO_DIV_STATE_Pos = 0xd
	// Bit mask of PMU_SYS_CLK_NO_DIV_STATE field.
	PMU_CLK_STATE0_PMU_SYS_CLK_NO_DIV_STATE_Msk = 0x2000
	// Bit PMU_SYS_CLK_NO_DIV_STATE.
	PMU_CLK_STATE0_PMU_SYS_CLK_NO_DIV_STATE = 0x2000
	// Position of PMU_ICG_SYS_CLK_EN_STATE field.
	PMU_CLK_STATE0_PMU_ICG_SYS_CLK_EN_STATE_Pos = 0xe
	// Bit mask of PMU_ICG_SYS_CLK_EN_STATE field.
	PMU_CLK_STATE0_PMU_ICG_SYS_CLK_EN_STATE_Msk = 0x4000
	// Bit PMU_ICG_SYS_CLK_EN_STATE.
	PMU_CLK_STATE0_PMU_ICG_SYS_CLK_EN_STATE = 0x4000
	// Position of PMU_ICG_MODEM_SWITCH_STATE field.
	PMU_CLK_STATE0_PMU_ICG_MODEM_SWITCH_STATE_Pos = 0xf
	// Bit mask of PMU_ICG_MODEM_SWITCH_STATE field.
	PMU_CLK_STATE0_PMU_ICG_MODEM_SWITCH_STATE_Msk = 0x8000
	// Bit PMU_ICG_MODEM_SWITCH_STATE.
	PMU_CLK_STATE0_PMU_ICG_MODEM_SWITCH_STATE = 0x8000
	// Position of PMU_ICG_MODEM_CODE_STATE field.
	PMU_CLK_STATE0_PMU_ICG_MODEM_CODE_STATE_Pos = 0x10
	// Bit mask of PMU_ICG_MODEM_CODE_STATE field.
	PMU_CLK_STATE0_PMU_ICG_MODEM_CODE_STATE_Msk = 0x30000
	// Position of PMU_ICG_SLP_SEL_STATE field.
	PMU_CLK_STATE0_PMU_ICG_SLP_SEL_STATE_Pos = 0x12
	// Bit mask of PMU_ICG_SLP_SEL_STATE field.
	PMU_CLK_STATE0_PMU_ICG_SLP_SEL_STATE_Msk = 0x40000
	// Bit PMU_ICG_SLP_SEL_STATE.
	PMU_CLK_STATE0_PMU_ICG_SLP_SEL_STATE = 0x40000
	// Position of PMU_ICG_GLOBAL_XTAL_STATE field.
	PMU_CLK_STATE0_PMU_ICG_GLOBAL_XTAL_STATE_Pos = 0x13
	// Bit mask of PMU_ICG_GLOBAL_XTAL_STATE field.
	PMU_CLK_STATE0_PMU_ICG_GLOBAL_XTAL_STATE_Msk = 0x80000
	// Bit PMU_ICG_GLOBAL_XTAL_STATE.
	PMU_CLK_STATE0_PMU_ICG_GLOBAL_XTAL_STATE = 0x80000
	// Position of PMU_ICG_GLOBAL_PLL_STATE field.
	PMU_CLK_STATE0_PMU_ICG_GLOBAL_PLL_STATE_Pos = 0x14
	// Bit mask of PMU_ICG_GLOBAL_PLL_STATE field.
	PMU_CLK_STATE0_PMU_ICG_GLOBAL_PLL_STATE_Msk = 0xf00000
	// Position of PMU_ANA_I2C_ISO_EN_STATE field.
	PMU_CLK_STATE0_PMU_ANA_I2C_ISO_EN_STATE_Pos = 0x18
	// Bit mask of PMU_ANA_I2C_ISO_EN_STATE field.
	PMU_CLK_STATE0_PMU_ANA_I2C_ISO_EN_STATE_Msk = 0x1000000
	// Bit PMU_ANA_I2C_ISO_EN_STATE.
	PMU_CLK_STATE0_PMU_ANA_I2C_ISO_EN_STATE = 0x1000000
	// Position of PMU_ANA_I2C_RETENTION_STATE field.
	PMU_CLK_STATE0_PMU_ANA_I2C_RETENTION_STATE_Pos = 0x19
	// Bit mask of PMU_ANA_I2C_RETENTION_STATE field.
	PMU_CLK_STATE0_PMU_ANA_I2C_RETENTION_STATE_Msk = 0x2000000
	// Bit PMU_ANA_I2C_RETENTION_STATE.
	PMU_CLK_STATE0_PMU_ANA_I2C_RETENTION_STATE = 0x2000000
	// Position of PMU_ANA_XPD_PLL_STATE field.
	PMU_CLK_STATE0_PMU_ANA_XPD_PLL_STATE_Pos = 0x1b
	// Bit mask of PMU_ANA_XPD_PLL_STATE field.
	PMU_CLK_STATE0_PMU_ANA_XPD_PLL_STATE_Msk = 0x78000000
	// Position of PMU_ANA_XPD_XTAL_STATE field.
	PMU_CLK_STATE0_PMU_ANA_XPD_XTAL_STATE_Pos = 0x1f
	// Bit mask of PMU_ANA_XPD_XTAL_STATE field.
	PMU_CLK_STATE0_PMU_ANA_XPD_XTAL_STATE_Msk = 0x80000000
	// Bit PMU_ANA_XPD_XTAL_STATE.
	PMU_CLK_STATE0_PMU_ANA_XPD_XTAL_STATE = 0x80000000

	// CLK_STATE1: need_des
	// Position of PMU_ICG_FUNC_EN_STATE field.
	PMU_CLK_STATE1_PMU_ICG_FUNC_EN_STATE_Pos = 0x0
	// Bit mask of PMU_ICG_FUNC_EN_STATE field.
	PMU_CLK_STATE1_PMU_ICG_FUNC_EN_STATE_Msk = 0xffffffff

	// CLK_STATE2: need_des
	// Position of PMU_ICG_APB_EN_STATE field.
	PMU_CLK_STATE2_PMU_ICG_APB_EN_STATE_Pos = 0x0
	// Bit mask of PMU_ICG_APB_EN_STATE field.
	PMU_CLK_STATE2_PMU_ICG_APB_EN_STATE_Msk = 0xffffffff

	// EXT_LDO_P0_0P1A: need_des
	// Position of _0P1A_FORCE_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_FORCE_TIEH_SEL_0_Pos = 0x7
	// Bit mask of _0P1A_FORCE_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_FORCE_TIEH_SEL_0_Msk = 0x80
	// Bit _0P1A_FORCE_TIEH_SEL_0.
	PMU_EXT_LDO_P0_0P1A__0P1A_FORCE_TIEH_SEL_0 = 0x80
	// Position of _0P1A_XPD_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_XPD_0_Pos = 0x8
	// Bit mask of _0P1A_XPD_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_XPD_0_Msk = 0x100
	// Bit _0P1A_XPD_0.
	PMU_EXT_LDO_P0_0P1A__0P1A_XPD_0 = 0x100
	// Position of _0P1A_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_SEL_0_Pos = 0x9
	// Bit mask of _0P1A_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_SEL_0_Msk = 0xe00
	// Position of _0P1A_TIEH_POS_EN_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_POS_EN_0_Pos = 0xc
	// Bit mask of _0P1A_TIEH_POS_EN_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_POS_EN_0_Msk = 0x1000
	// Bit _0P1A_TIEH_POS_EN_0.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_POS_EN_0 = 0x1000
	// Position of _0P1A_TIEH_NEG_EN_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_NEG_EN_0_Pos = 0xd
	// Bit mask of _0P1A_TIEH_NEG_EN_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_NEG_EN_0_Msk = 0x2000
	// Bit _0P1A_TIEH_NEG_EN_0.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_NEG_EN_0 = 0x2000
	// Position of _0P1A_TIEH_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_0_Pos = 0xe
	// Bit mask of _0P1A_TIEH_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_0_Msk = 0x4000
	// Bit _0P1A_TIEH_0.
	PMU_EXT_LDO_P0_0P1A__0P1A_TIEH_0 = 0x4000
	// Position of _0P1A_TARGET1_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TARGET1_0_Pos = 0xf
	// Bit mask of _0P1A_TARGET1_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TARGET1_0_Msk = 0x7f8000
	// Position of _0P1A_TARGET0_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TARGET0_0_Pos = 0x17
	// Bit mask of _0P1A_TARGET0_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_TARGET0_0_Msk = 0x7f800000
	// Position of _0P1A_LDO_CNT_PRESCALER_SEL_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_0_Pos = 0x1f
	// Bit mask of _0P1A_LDO_CNT_PRESCALER_SEL_0 field.
	PMU_EXT_LDO_P0_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_0_Msk = 0x80000000
	// Bit _0P1A_LDO_CNT_PRESCALER_SEL_0.
	PMU_EXT_LDO_P0_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_0 = 0x80000000

	// EXT_LDO_P0_0P1A_ANA: need_des
	// Position of ANA_0P1A_MUL_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_MUL_0_Pos = 0x17
	// Bit mask of ANA_0P1A_MUL_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_MUL_0_Msk = 0x3800000
	// Position of ANA_0P1A_EN_VDET_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_VDET_0_Pos = 0x1a
	// Bit mask of ANA_0P1A_EN_VDET_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_VDET_0_Msk = 0x4000000
	// Bit ANA_0P1A_EN_VDET_0.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_VDET_0 = 0x4000000
	// Position of ANA_0P1A_EN_CUR_LIM_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_0_Pos = 0x1b
	// Bit mask of ANA_0P1A_EN_CUR_LIM_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_0_Msk = 0x8000000
	// Bit ANA_0P1A_EN_CUR_LIM_0.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_0 = 0x8000000
	// Position of ANA_0P1A_DREF_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_DREF_0_Pos = 0x1c
	// Bit mask of ANA_0P1A_DREF_0 field.
	PMU_EXT_LDO_P0_0P1A_ANA_ANA_0P1A_DREF_0_Msk = 0xf0000000

	// EXT_LDO_P0_0P2A: need_des
	// Position of _0P2A_FORCE_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_FORCE_TIEH_SEL_0_Pos = 0x7
	// Bit mask of _0P2A_FORCE_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_FORCE_TIEH_SEL_0_Msk = 0x80
	// Bit _0P2A_FORCE_TIEH_SEL_0.
	PMU_EXT_LDO_P0_0P2A__0P2A_FORCE_TIEH_SEL_0 = 0x80
	// Position of _0P2A_XPD_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_XPD_0_Pos = 0x8
	// Bit mask of _0P2A_XPD_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_XPD_0_Msk = 0x100
	// Bit _0P2A_XPD_0.
	PMU_EXT_LDO_P0_0P2A__0P2A_XPD_0 = 0x100
	// Position of _0P2A_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_SEL_0_Pos = 0x9
	// Bit mask of _0P2A_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_SEL_0_Msk = 0xe00
	// Position of _0P2A_TIEH_POS_EN_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_POS_EN_0_Pos = 0xc
	// Bit mask of _0P2A_TIEH_POS_EN_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_POS_EN_0_Msk = 0x1000
	// Bit _0P2A_TIEH_POS_EN_0.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_POS_EN_0 = 0x1000
	// Position of _0P2A_TIEH_NEG_EN_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_NEG_EN_0_Pos = 0xd
	// Bit mask of _0P2A_TIEH_NEG_EN_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_NEG_EN_0_Msk = 0x2000
	// Bit _0P2A_TIEH_NEG_EN_0.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_NEG_EN_0 = 0x2000
	// Position of _0P2A_TIEH_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_0_Pos = 0xe
	// Bit mask of _0P2A_TIEH_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_0_Msk = 0x4000
	// Bit _0P2A_TIEH_0.
	PMU_EXT_LDO_P0_0P2A__0P2A_TIEH_0 = 0x4000
	// Position of _0P2A_TARGET1_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TARGET1_0_Pos = 0xf
	// Bit mask of _0P2A_TARGET1_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TARGET1_0_Msk = 0x7f8000
	// Position of _0P2A_TARGET0_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TARGET0_0_Pos = 0x17
	// Bit mask of _0P2A_TARGET0_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_TARGET0_0_Msk = 0x7f800000
	// Position of _0P2A_LDO_CNT_PRESCALER_SEL_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_0_Pos = 0x1f
	// Bit mask of _0P2A_LDO_CNT_PRESCALER_SEL_0 field.
	PMU_EXT_LDO_P0_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_0_Msk = 0x80000000
	// Bit _0P2A_LDO_CNT_PRESCALER_SEL_0.
	PMU_EXT_LDO_P0_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_0 = 0x80000000

	// EXT_LDO_P0_0P2A_ANA: need_des
	// Position of ANA_0P2A_MUL_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_MUL_0_Pos = 0x17
	// Bit mask of ANA_0P2A_MUL_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_MUL_0_Msk = 0x3800000
	// Position of ANA_0P2A_EN_VDET_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_VDET_0_Pos = 0x1a
	// Bit mask of ANA_0P2A_EN_VDET_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_VDET_0_Msk = 0x4000000
	// Bit ANA_0P2A_EN_VDET_0.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_VDET_0 = 0x4000000
	// Position of ANA_0P2A_EN_CUR_LIM_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_0_Pos = 0x1b
	// Bit mask of ANA_0P2A_EN_CUR_LIM_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_0_Msk = 0x8000000
	// Bit ANA_0P2A_EN_CUR_LIM_0.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_0 = 0x8000000
	// Position of ANA_0P2A_DREF_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_DREF_0_Pos = 0x1c
	// Bit mask of ANA_0P2A_DREF_0 field.
	PMU_EXT_LDO_P0_0P2A_ANA_ANA_0P2A_DREF_0_Msk = 0xf0000000

	// EXT_LDO_P0_0P3A: need_des
	// Position of _0P3A_FORCE_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_FORCE_TIEH_SEL_0_Pos = 0x7
	// Bit mask of _0P3A_FORCE_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_FORCE_TIEH_SEL_0_Msk = 0x80
	// Bit _0P3A_FORCE_TIEH_SEL_0.
	PMU_EXT_LDO_P0_0P3A__0P3A_FORCE_TIEH_SEL_0 = 0x80
	// Position of _0P3A_XPD_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_XPD_0_Pos = 0x8
	// Bit mask of _0P3A_XPD_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_XPD_0_Msk = 0x100
	// Bit _0P3A_XPD_0.
	PMU_EXT_LDO_P0_0P3A__0P3A_XPD_0 = 0x100
	// Position of _0P3A_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_SEL_0_Pos = 0x9
	// Bit mask of _0P3A_TIEH_SEL_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_SEL_0_Msk = 0xe00
	// Position of _0P3A_TIEH_POS_EN_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_POS_EN_0_Pos = 0xc
	// Bit mask of _0P3A_TIEH_POS_EN_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_POS_EN_0_Msk = 0x1000
	// Bit _0P3A_TIEH_POS_EN_0.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_POS_EN_0 = 0x1000
	// Position of _0P3A_TIEH_NEG_EN_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_NEG_EN_0_Pos = 0xd
	// Bit mask of _0P3A_TIEH_NEG_EN_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_NEG_EN_0_Msk = 0x2000
	// Bit _0P3A_TIEH_NEG_EN_0.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_NEG_EN_0 = 0x2000
	// Position of _0P3A_TIEH_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_0_Pos = 0xe
	// Bit mask of _0P3A_TIEH_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_0_Msk = 0x4000
	// Bit _0P3A_TIEH_0.
	PMU_EXT_LDO_P0_0P3A__0P3A_TIEH_0 = 0x4000
	// Position of _0P3A_TARGET1_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TARGET1_0_Pos = 0xf
	// Bit mask of _0P3A_TARGET1_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TARGET1_0_Msk = 0x7f8000
	// Position of _0P3A_TARGET0_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TARGET0_0_Pos = 0x17
	// Bit mask of _0P3A_TARGET0_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_TARGET0_0_Msk = 0x7f800000
	// Position of _0P3A_LDO_CNT_PRESCALER_SEL_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_0_Pos = 0x1f
	// Bit mask of _0P3A_LDO_CNT_PRESCALER_SEL_0 field.
	PMU_EXT_LDO_P0_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_0_Msk = 0x80000000
	// Bit _0P3A_LDO_CNT_PRESCALER_SEL_0.
	PMU_EXT_LDO_P0_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_0 = 0x80000000

	// EXT_LDO_P0_0P3A_ANA: need_des
	// Position of ANA_0P3A_MUL_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_MUL_0_Pos = 0x17
	// Bit mask of ANA_0P3A_MUL_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_MUL_0_Msk = 0x3800000
	// Position of ANA_0P3A_EN_VDET_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_VDET_0_Pos = 0x1a
	// Bit mask of ANA_0P3A_EN_VDET_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_VDET_0_Msk = 0x4000000
	// Bit ANA_0P3A_EN_VDET_0.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_VDET_0 = 0x4000000
	// Position of ANA_0P3A_EN_CUR_LIM_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_0_Pos = 0x1b
	// Bit mask of ANA_0P3A_EN_CUR_LIM_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_0_Msk = 0x8000000
	// Bit ANA_0P3A_EN_CUR_LIM_0.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_0 = 0x8000000
	// Position of ANA_0P3A_DREF_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_DREF_0_Pos = 0x1c
	// Bit mask of ANA_0P3A_DREF_0 field.
	PMU_EXT_LDO_P0_0P3A_ANA_ANA_0P3A_DREF_0_Msk = 0xf0000000

	// EXT_LDO_P1_0P1A: need_des
	// Position of _0P1A_FORCE_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_FORCE_TIEH_SEL_1_Pos = 0x7
	// Bit mask of _0P1A_FORCE_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_FORCE_TIEH_SEL_1_Msk = 0x80
	// Bit _0P1A_FORCE_TIEH_SEL_1.
	PMU_EXT_LDO_P1_0P1A__0P1A_FORCE_TIEH_SEL_1 = 0x80
	// Position of _0P1A_XPD_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_XPD_1_Pos = 0x8
	// Bit mask of _0P1A_XPD_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_XPD_1_Msk = 0x100
	// Bit _0P1A_XPD_1.
	PMU_EXT_LDO_P1_0P1A__0P1A_XPD_1 = 0x100
	// Position of _0P1A_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_SEL_1_Pos = 0x9
	// Bit mask of _0P1A_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_SEL_1_Msk = 0xe00
	// Position of _0P1A_TIEH_POS_EN_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_POS_EN_1_Pos = 0xc
	// Bit mask of _0P1A_TIEH_POS_EN_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_POS_EN_1_Msk = 0x1000
	// Bit _0P1A_TIEH_POS_EN_1.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_POS_EN_1 = 0x1000
	// Position of _0P1A_TIEH_NEG_EN_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_NEG_EN_1_Pos = 0xd
	// Bit mask of _0P1A_TIEH_NEG_EN_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_NEG_EN_1_Msk = 0x2000
	// Bit _0P1A_TIEH_NEG_EN_1.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_NEG_EN_1 = 0x2000
	// Position of _0P1A_TIEH_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_1_Pos = 0xe
	// Bit mask of _0P1A_TIEH_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_1_Msk = 0x4000
	// Bit _0P1A_TIEH_1.
	PMU_EXT_LDO_P1_0P1A__0P1A_TIEH_1 = 0x4000
	// Position of _0P1A_TARGET1_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TARGET1_1_Pos = 0xf
	// Bit mask of _0P1A_TARGET1_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TARGET1_1_Msk = 0x7f8000
	// Position of _0P1A_TARGET0_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TARGET0_1_Pos = 0x17
	// Bit mask of _0P1A_TARGET0_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_TARGET0_1_Msk = 0x7f800000
	// Position of _0P1A_LDO_CNT_PRESCALER_SEL_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_1_Pos = 0x1f
	// Bit mask of _0P1A_LDO_CNT_PRESCALER_SEL_1 field.
	PMU_EXT_LDO_P1_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_1_Msk = 0x80000000
	// Bit _0P1A_LDO_CNT_PRESCALER_SEL_1.
	PMU_EXT_LDO_P1_0P1A__0P1A_LDO_CNT_PRESCALER_SEL_1 = 0x80000000

	// EXT_LDO_P1_0P1A_ANA: need_des
	// Position of ANA_0P1A_MUL_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_MUL_1_Pos = 0x17
	// Bit mask of ANA_0P1A_MUL_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_MUL_1_Msk = 0x3800000
	// Position of ANA_0P1A_EN_VDET_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_VDET_1_Pos = 0x1a
	// Bit mask of ANA_0P1A_EN_VDET_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_VDET_1_Msk = 0x4000000
	// Bit ANA_0P1A_EN_VDET_1.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_VDET_1 = 0x4000000
	// Position of ANA_0P1A_EN_CUR_LIM_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_1_Pos = 0x1b
	// Bit mask of ANA_0P1A_EN_CUR_LIM_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_1_Msk = 0x8000000
	// Bit ANA_0P1A_EN_CUR_LIM_1.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_EN_CUR_LIM_1 = 0x8000000
	// Position of ANA_0P1A_DREF_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_DREF_1_Pos = 0x1c
	// Bit mask of ANA_0P1A_DREF_1 field.
	PMU_EXT_LDO_P1_0P1A_ANA_ANA_0P1A_DREF_1_Msk = 0xf0000000

	// EXT_LDO_P1_0P2A: need_des
	// Position of _0P2A_FORCE_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_FORCE_TIEH_SEL_1_Pos = 0x7
	// Bit mask of _0P2A_FORCE_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_FORCE_TIEH_SEL_1_Msk = 0x80
	// Bit _0P2A_FORCE_TIEH_SEL_1.
	PMU_EXT_LDO_P1_0P2A__0P2A_FORCE_TIEH_SEL_1 = 0x80
	// Position of _0P2A_XPD_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_XPD_1_Pos = 0x8
	// Bit mask of _0P2A_XPD_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_XPD_1_Msk = 0x100
	// Bit _0P2A_XPD_1.
	PMU_EXT_LDO_P1_0P2A__0P2A_XPD_1 = 0x100
	// Position of _0P2A_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_SEL_1_Pos = 0x9
	// Bit mask of _0P2A_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_SEL_1_Msk = 0xe00
	// Position of _0P2A_TIEH_POS_EN_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_POS_EN_1_Pos = 0xc
	// Bit mask of _0P2A_TIEH_POS_EN_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_POS_EN_1_Msk = 0x1000
	// Bit _0P2A_TIEH_POS_EN_1.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_POS_EN_1 = 0x1000
	// Position of _0P2A_TIEH_NEG_EN_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_NEG_EN_1_Pos = 0xd
	// Bit mask of _0P2A_TIEH_NEG_EN_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_NEG_EN_1_Msk = 0x2000
	// Bit _0P2A_TIEH_NEG_EN_1.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_NEG_EN_1 = 0x2000
	// Position of _0P2A_TIEH_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_1_Pos = 0xe
	// Bit mask of _0P2A_TIEH_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_1_Msk = 0x4000
	// Bit _0P2A_TIEH_1.
	PMU_EXT_LDO_P1_0P2A__0P2A_TIEH_1 = 0x4000
	// Position of _0P2A_TARGET1_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TARGET1_1_Pos = 0xf
	// Bit mask of _0P2A_TARGET1_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TARGET1_1_Msk = 0x7f8000
	// Position of _0P2A_TARGET0_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TARGET0_1_Pos = 0x17
	// Bit mask of _0P2A_TARGET0_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_TARGET0_1_Msk = 0x7f800000
	// Position of _0P2A_LDO_CNT_PRESCALER_SEL_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_1_Pos = 0x1f
	// Bit mask of _0P2A_LDO_CNT_PRESCALER_SEL_1 field.
	PMU_EXT_LDO_P1_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_1_Msk = 0x80000000
	// Bit _0P2A_LDO_CNT_PRESCALER_SEL_1.
	PMU_EXT_LDO_P1_0P2A__0P2A_LDO_CNT_PRESCALER_SEL_1 = 0x80000000

	// EXT_LDO_P1_0P2A_ANA: need_des
	// Position of ANA_0P2A_MUL_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_MUL_1_Pos = 0x17
	// Bit mask of ANA_0P2A_MUL_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_MUL_1_Msk = 0x3800000
	// Position of ANA_0P2A_EN_VDET_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_VDET_1_Pos = 0x1a
	// Bit mask of ANA_0P2A_EN_VDET_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_VDET_1_Msk = 0x4000000
	// Bit ANA_0P2A_EN_VDET_1.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_VDET_1 = 0x4000000
	// Position of ANA_0P2A_EN_CUR_LIM_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_1_Pos = 0x1b
	// Bit mask of ANA_0P2A_EN_CUR_LIM_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_1_Msk = 0x8000000
	// Bit ANA_0P2A_EN_CUR_LIM_1.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_EN_CUR_LIM_1 = 0x8000000
	// Position of ANA_0P2A_DREF_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_DREF_1_Pos = 0x1c
	// Bit mask of ANA_0P2A_DREF_1 field.
	PMU_EXT_LDO_P1_0P2A_ANA_ANA_0P2A_DREF_1_Msk = 0xf0000000

	// EXT_LDO_P1_0P3A: need_des
	// Position of _0P3A_FORCE_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_FORCE_TIEH_SEL_1_Pos = 0x7
	// Bit mask of _0P3A_FORCE_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_FORCE_TIEH_SEL_1_Msk = 0x80
	// Bit _0P3A_FORCE_TIEH_SEL_1.
	PMU_EXT_LDO_P1_0P3A__0P3A_FORCE_TIEH_SEL_1 = 0x80
	// Position of _0P3A_XPD_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_XPD_1_Pos = 0x8
	// Bit mask of _0P3A_XPD_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_XPD_1_Msk = 0x100
	// Bit _0P3A_XPD_1.
	PMU_EXT_LDO_P1_0P3A__0P3A_XPD_1 = 0x100
	// Position of _0P3A_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_SEL_1_Pos = 0x9
	// Bit mask of _0P3A_TIEH_SEL_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_SEL_1_Msk = 0xe00
	// Position of _0P3A_TIEH_POS_EN_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_POS_EN_1_Pos = 0xc
	// Bit mask of _0P3A_TIEH_POS_EN_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_POS_EN_1_Msk = 0x1000
	// Bit _0P3A_TIEH_POS_EN_1.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_POS_EN_1 = 0x1000
	// Position of _0P3A_TIEH_NEG_EN_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_NEG_EN_1_Pos = 0xd
	// Bit mask of _0P3A_TIEH_NEG_EN_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_NEG_EN_1_Msk = 0x2000
	// Bit _0P3A_TIEH_NEG_EN_1.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_NEG_EN_1 = 0x2000
	// Position of _0P3A_TIEH_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_1_Pos = 0xe
	// Bit mask of _0P3A_TIEH_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_1_Msk = 0x4000
	// Bit _0P3A_TIEH_1.
	PMU_EXT_LDO_P1_0P3A__0P3A_TIEH_1 = 0x4000
	// Position of _0P3A_TARGET1_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TARGET1_1_Pos = 0xf
	// Bit mask of _0P3A_TARGET1_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TARGET1_1_Msk = 0x7f8000
	// Position of _0P3A_TARGET0_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TARGET0_1_Pos = 0x17
	// Bit mask of _0P3A_TARGET0_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_TARGET0_1_Msk = 0x7f800000
	// Position of _0P3A_LDO_CNT_PRESCALER_SEL_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_1_Pos = 0x1f
	// Bit mask of _0P3A_LDO_CNT_PRESCALER_SEL_1 field.
	PMU_EXT_LDO_P1_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_1_Msk = 0x80000000
	// Bit _0P3A_LDO_CNT_PRESCALER_SEL_1.
	PMU_EXT_LDO_P1_0P3A__0P3A_LDO_CNT_PRESCALER_SEL_1 = 0x80000000

	// EXT_LDO_P1_0P3A_ANA: need_des
	// Position of ANA_0P3A_MUL_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_MUL_1_Pos = 0x17
	// Bit mask of ANA_0P3A_MUL_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_MUL_1_Msk = 0x3800000
	// Position of ANA_0P3A_EN_VDET_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_VDET_1_Pos = 0x1a
	// Bit mask of ANA_0P3A_EN_VDET_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_VDET_1_Msk = 0x4000000
	// Bit ANA_0P3A_EN_VDET_1.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_VDET_1 = 0x4000000
	// Position of ANA_0P3A_EN_CUR_LIM_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_1_Pos = 0x1b
	// Bit mask of ANA_0P3A_EN_CUR_LIM_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_1_Msk = 0x8000000
	// Bit ANA_0P3A_EN_CUR_LIM_1.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_EN_CUR_LIM_1 = 0x8000000
	// Position of ANA_0P3A_DREF_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_DREF_1_Pos = 0x1c
	// Bit mask of ANA_0P3A_DREF_1 field.
	PMU_EXT_LDO_P1_0P3A_ANA_ANA_0P3A_DREF_1_Msk = 0xf0000000

	// EXT_WAKEUP_LV: need_des
	// Position of EXT_WAKEUP_LV field.
	PMU_EXT_WAKEUP_LV_EXT_WAKEUP_LV_Pos = 0x0
	// Bit mask of EXT_WAKEUP_LV field.
	PMU_EXT_WAKEUP_LV_EXT_WAKEUP_LV_Msk = 0xffffffff

	// EXT_WAKEUP_SEL: need_des
	// Position of EXT_WAKEUP_SEL field.
	PMU_EXT_WAKEUP_SEL_EXT_WAKEUP_SEL_Pos = 0x0
	// Bit mask of EXT_WAKEUP_SEL field.
	PMU_EXT_WAKEUP_SEL_EXT_WAKEUP_SEL_Msk = 0xffffffff

	// EXT_WAKEUP_ST: need_des
	// Position of EXT_WAKEUP_STATUS field.
	PMU_EXT_WAKEUP_ST_EXT_WAKEUP_STATUS_Pos = 0x0
	// Bit mask of EXT_WAKEUP_STATUS field.
	PMU_EXT_WAKEUP_ST_EXT_WAKEUP_STATUS_Msk = 0xffffffff

	// EXT_WAKEUP_CNTL: need_des
	// Position of EXT_WAKEUP_STATUS_CLR field.
	PMU_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Pos = 0x1e
	// Bit mask of EXT_WAKEUP_STATUS_CLR field.
	PMU_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR_Msk = 0x40000000
	// Bit EXT_WAKEUP_STATUS_CLR.
	PMU_EXT_WAKEUP_CNTL_EXT_WAKEUP_STATUS_CLR = 0x40000000
	// Position of EXT_WAKEUP_FILTER field.
	PMU_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Pos = 0x1f
	// Bit mask of EXT_WAKEUP_FILTER field.
	PMU_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER_Msk = 0x80000000
	// Bit EXT_WAKEUP_FILTER.
	PMU_EXT_WAKEUP_CNTL_EXT_WAKEUP_FILTER = 0x80000000

	// SDIO_WAKEUP_CNTL: need_des
	// Position of SDIO_ACT_DNUM field.
	PMU_SDIO_WAKEUP_CNTL_SDIO_ACT_DNUM_Pos = 0x0
	// Bit mask of SDIO_ACT_DNUM field.
	PMU_SDIO_WAKEUP_CNTL_SDIO_ACT_DNUM_Msk = 0x3ff

	// XTAL_SLP: need_des
	// Position of CNT_TARGET field.
	PMU_XTAL_SLP_CNT_TARGET_Pos = 0x10
	// Bit mask of CNT_TARGET field.
	PMU_XTAL_SLP_CNT_TARGET_Msk = 0xffff0000

	// CPU_SW_STALL: need_des
	// Position of HPCORE1_SW_STALL_CODE field.
	PMU_CPU_SW_STALL_HPCORE1_SW_STALL_CODE_Pos = 0x10
	// Bit mask of HPCORE1_SW_STALL_CODE field.
	PMU_CPU_SW_STALL_HPCORE1_SW_STALL_CODE_Msk = 0xff0000
	// Position of HPCORE0_SW_STALL_CODE field.
	PMU_CPU_SW_STALL_HPCORE0_SW_STALL_CODE_Pos = 0x18
	// Bit mask of HPCORE0_SW_STALL_CODE field.
	PMU_CPU_SW_STALL_HPCORE0_SW_STALL_CODE_Msk = 0xff000000

	// DCM_CTRL: need_des
	// Position of DCDC_ON_REQ field.
	PMU_DCM_CTRL_DCDC_ON_REQ_Pos = 0x0
	// Bit mask of DCDC_ON_REQ field.
	PMU_DCM_CTRL_DCDC_ON_REQ_Msk = 0x1
	// Bit DCDC_ON_REQ.
	PMU_DCM_CTRL_DCDC_ON_REQ = 0x1
	// Position of DCDC_OFF_REQ field.
	PMU_DCM_CTRL_DCDC_OFF_REQ_Pos = 0x1
	// Bit mask of DCDC_OFF_REQ field.
	PMU_DCM_CTRL_DCDC_OFF_REQ_Msk = 0x2
	// Bit DCDC_OFF_REQ.
	PMU_DCM_CTRL_DCDC_OFF_REQ = 0x2
	// Position of DCDC_LIGHTSLP_REQ field.
	PMU_DCM_CTRL_DCDC_LIGHTSLP_REQ_Pos = 0x2
	// Bit mask of DCDC_LIGHTSLP_REQ field.
	PMU_DCM_CTRL_DCDC_LIGHTSLP_REQ_Msk = 0x4
	// Bit DCDC_LIGHTSLP_REQ.
	PMU_DCM_CTRL_DCDC_LIGHTSLP_REQ = 0x4
	// Position of DCDC_DEEPSLP_REQ field.
	PMU_DCM_CTRL_DCDC_DEEPSLP_REQ_Pos = 0x3
	// Bit mask of DCDC_DEEPSLP_REQ field.
	PMU_DCM_CTRL_DCDC_DEEPSLP_REQ_Msk = 0x8
	// Bit DCDC_DEEPSLP_REQ.
	PMU_DCM_CTRL_DCDC_DEEPSLP_REQ = 0x8
	// Position of DCDC_DONE_FORCE field.
	PMU_DCM_CTRL_DCDC_DONE_FORCE_Pos = 0x7
	// Bit mask of DCDC_DONE_FORCE field.
	PMU_DCM_CTRL_DCDC_DONE_FORCE_Msk = 0x80
	// Bit DCDC_DONE_FORCE.
	PMU_DCM_CTRL_DCDC_DONE_FORCE = 0x80
	// Position of DCDC_ON_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_ON_FORCE_PU_Pos = 0x8
	// Bit mask of DCDC_ON_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_ON_FORCE_PU_Msk = 0x100
	// Bit DCDC_ON_FORCE_PU.
	PMU_DCM_CTRL_DCDC_ON_FORCE_PU = 0x100
	// Position of DCDC_ON_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_ON_FORCE_PD_Pos = 0x9
	// Bit mask of DCDC_ON_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_ON_FORCE_PD_Msk = 0x200
	// Bit DCDC_ON_FORCE_PD.
	PMU_DCM_CTRL_DCDC_ON_FORCE_PD = 0x200
	// Position of DCDC_FB_RES_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_FB_RES_FORCE_PU_Pos = 0xa
	// Bit mask of DCDC_FB_RES_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_FB_RES_FORCE_PU_Msk = 0x400
	// Bit DCDC_FB_RES_FORCE_PU.
	PMU_DCM_CTRL_DCDC_FB_RES_FORCE_PU = 0x400
	// Position of DCDC_FB_RES_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_FB_RES_FORCE_PD_Pos = 0xb
	// Bit mask of DCDC_FB_RES_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_FB_RES_FORCE_PD_Msk = 0x800
	// Bit DCDC_FB_RES_FORCE_PD.
	PMU_DCM_CTRL_DCDC_FB_RES_FORCE_PD = 0x800
	// Position of DCDC_LS_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_LS_FORCE_PU_Pos = 0xc
	// Bit mask of DCDC_LS_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_LS_FORCE_PU_Msk = 0x1000
	// Bit DCDC_LS_FORCE_PU.
	PMU_DCM_CTRL_DCDC_LS_FORCE_PU = 0x1000
	// Position of DCDC_LS_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_LS_FORCE_PD_Pos = 0xd
	// Bit mask of DCDC_LS_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_LS_FORCE_PD_Msk = 0x2000
	// Bit DCDC_LS_FORCE_PD.
	PMU_DCM_CTRL_DCDC_LS_FORCE_PD = 0x2000
	// Position of DCDC_DS_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_DS_FORCE_PU_Pos = 0xe
	// Bit mask of DCDC_DS_FORCE_PU field.
	PMU_DCM_CTRL_DCDC_DS_FORCE_PU_Msk = 0x4000
	// Bit DCDC_DS_FORCE_PU.
	PMU_DCM_CTRL_DCDC_DS_FORCE_PU = 0x4000
	// Position of DCDC_DS_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_DS_FORCE_PD_Pos = 0xf
	// Bit mask of DCDC_DS_FORCE_PD field.
	PMU_DCM_CTRL_DCDC_DS_FORCE_PD_Msk = 0x8000
	// Bit DCDC_DS_FORCE_PD.
	PMU_DCM_CTRL_DCDC_DS_FORCE_PD = 0x8000
	// Position of DCM_CUR_ST field.
	PMU_DCM_CTRL_DCM_CUR_ST_Pos = 0x10
	// Bit mask of DCM_CUR_ST field.
	PMU_DCM_CTRL_DCM_CUR_ST_Msk = 0xff0000
	// Position of DCDC_EN_AMUX_TEST field.
	PMU_DCM_CTRL_DCDC_EN_AMUX_TEST_Pos = 0x1d
	// Bit mask of DCDC_EN_AMUX_TEST field.
	PMU_DCM_CTRL_DCDC_EN_AMUX_TEST_Msk = 0x20000000
	// Bit DCDC_EN_AMUX_TEST.
	PMU_DCM_CTRL_DCDC_EN_AMUX_TEST = 0x20000000

	// DCM_WAIT_DELAY: need_des
	// Position of DCDC_PRE_DELAY field.
	PMU_DCM_WAIT_DELAY_DCDC_PRE_DELAY_Pos = 0x0
	// Bit mask of DCDC_PRE_DELAY field.
	PMU_DCM_WAIT_DELAY_DCDC_PRE_DELAY_Msk = 0xff
	// Position of DCDC_RES_OFF_DELAY field.
	PMU_DCM_WAIT_DELAY_DCDC_RES_OFF_DELAY_Pos = 0x8
	// Bit mask of DCDC_RES_OFF_DELAY field.
	PMU_DCM_WAIT_DELAY_DCDC_RES_OFF_DELAY_Msk = 0xff00
	// Position of DCDC_STABLE_DELAY field.
	PMU_DCM_WAIT_DELAY_DCDC_STABLE_DELAY_Pos = 0x10
	// Bit mask of DCDC_STABLE_DELAY field.
	PMU_DCM_WAIT_DELAY_DCDC_STABLE_DELAY_Msk = 0x3ff0000

	// VDDBAT_CFG: need_des
	// Position of ANA_VDDBAT_MODE field.
	PMU_VDDBAT_CFG_ANA_VDDBAT_MODE_Pos = 0x0
	// Bit mask of ANA_VDDBAT_MODE field.
	PMU_VDDBAT_CFG_ANA_VDDBAT_MODE_Msk = 0x3
	// Position of VDDBAT_SW_UPDATE field.
	PMU_VDDBAT_CFG_VDDBAT_SW_UPDATE_Pos = 0x1f
	// Bit mask of VDDBAT_SW_UPDATE field.
	PMU_VDDBAT_CFG_VDDBAT_SW_UPDATE_Msk = 0x80000000
	// Bit VDDBAT_SW_UPDATE.
	PMU_VDDBAT_CFG_VDDBAT_SW_UPDATE = 0x80000000

	// TOUCH_PWR_CNTL: need_des
	// Position of TOUCH_WAIT_CYCLES field.
	PMU_TOUCH_PWR_CNTL_TOUCH_WAIT_CYCLES_Pos = 0x5
	// Bit mask of TOUCH_WAIT_CYCLES field.
	PMU_TOUCH_PWR_CNTL_TOUCH_WAIT_CYCLES_Msk = 0x3fe0
	// Position of TOUCH_SLEEP_CYCLES field.
	PMU_TOUCH_PWR_CNTL_TOUCH_SLEEP_CYCLES_Pos = 0xe
	// Bit mask of TOUCH_SLEEP_CYCLES field.
	PMU_TOUCH_PWR_CNTL_TOUCH_SLEEP_CYCLES_Msk = 0x3fffc000
	// Position of TOUCH_FORCE_DONE field.
	PMU_TOUCH_PWR_CNTL_TOUCH_FORCE_DONE_Pos = 0x1e
	// Bit mask of TOUCH_FORCE_DONE field.
	PMU_TOUCH_PWR_CNTL_TOUCH_FORCE_DONE_Msk = 0x40000000
	// Bit TOUCH_FORCE_DONE.
	PMU_TOUCH_PWR_CNTL_TOUCH_FORCE_DONE = 0x40000000
	// Position of TOUCH_SLEEP_TIMER_EN field.
	PMU_TOUCH_PWR_CNTL_TOUCH_SLEEP_TIMER_EN_Pos = 0x1f
	// Bit mask of TOUCH_SLEEP_TIMER_EN field.
	PMU_TOUCH_PWR_CNTL_TOUCH_SLEEP_TIMER_EN_Msk = 0x80000000
	// Bit TOUCH_SLEEP_TIMER_EN.
	PMU_TOUCH_PWR_CNTL_TOUCH_SLEEP_TIMER_EN = 0x80000000

	// RDN_ECO: need_des
	// Position of PMU_RDN_ECO_RESULT field.
	PMU_RDN_ECO_PMU_RDN_ECO_RESULT_Pos = 0x0
	// Bit mask of PMU_RDN_ECO_RESULT field.
	PMU_RDN_ECO_PMU_RDN_ECO_RESULT_Msk = 0x1
	// Bit PMU_RDN_ECO_RESULT.
	PMU_RDN_ECO_PMU_RDN_ECO_RESULT = 0x1
	// Position of PMU_RDN_ECO_EN field.
	PMU_RDN_ECO_PMU_RDN_ECO_EN_Pos = 0x1f
	// Bit mask of PMU_RDN_ECO_EN field.
	PMU_RDN_ECO_PMU_RDN_ECO_EN_Msk = 0x80000000
	// Bit PMU_RDN_ECO_EN.
	PMU_RDN_ECO_PMU_RDN_ECO_EN = 0x80000000

	// DATE: need_des
	// Position of PMU_DATE field.
	PMU_DATE_PMU_DATE_Pos = 0x0
	// Bit mask of PMU_DATE field.
	PMU_DATE_PMU_DATE_Msk = 0x7fffffff
	// Position of CLK_EN field.
	PMU_DATE_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	PMU_DATE_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	PMU_DATE_CLK_EN = 0x80000000
)

// Constants for PPA: PPA Peripheral
const (
	// BLEND0_CLUT_DATA: CLUT sram data read/write register in background plane of blender
	// Position of RDWR_WORD_BLEND0_CLUT field.
	PPA_BLEND0_CLUT_DATA_RDWR_WORD_BLEND0_CLUT_Pos = 0x0
	// Bit mask of RDWR_WORD_BLEND0_CLUT field.
	PPA_BLEND0_CLUT_DATA_RDWR_WORD_BLEND0_CLUT_Msk = 0xffffffff

	// BLEND1_CLUT_DATA: CLUT sram data read/write register in foreground plane of blender
	// Position of RDWR_WORD_BLEND1_CLUT field.
	PPA_BLEND1_CLUT_DATA_RDWR_WORD_BLEND1_CLUT_Pos = 0x0
	// Bit mask of RDWR_WORD_BLEND1_CLUT field.
	PPA_BLEND1_CLUT_DATA_RDWR_WORD_BLEND1_CLUT_Msk = 0xffffffff

	// CLUT_CONF: CLUT configure register
	// Position of APB_FIFO_MASK field.
	PPA_CLUT_CONF_APB_FIFO_MASK_Pos = 0x0
	// Bit mask of APB_FIFO_MASK field.
	PPA_CLUT_CONF_APB_FIFO_MASK_Msk = 0x1
	// Bit APB_FIFO_MASK.
	PPA_CLUT_CONF_APB_FIFO_MASK = 0x1
	// Position of BLEND0_CLUT_MEM_RST field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_RST_Pos = 0x1
	// Bit mask of BLEND0_CLUT_MEM_RST field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_RST_Msk = 0x2
	// Bit BLEND0_CLUT_MEM_RST.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_RST = 0x2
	// Position of BLEND1_CLUT_MEM_RST field.
	PPA_CLUT_CONF_BLEND1_CLUT_MEM_RST_Pos = 0x2
	// Bit mask of BLEND1_CLUT_MEM_RST field.
	PPA_CLUT_CONF_BLEND1_CLUT_MEM_RST_Msk = 0x4
	// Bit BLEND1_CLUT_MEM_RST.
	PPA_CLUT_CONF_BLEND1_CLUT_MEM_RST = 0x4
	// Position of BLEND0_CLUT_MEM_RDADDR_RST field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_RDADDR_RST_Pos = 0x3
	// Bit mask of BLEND0_CLUT_MEM_RDADDR_RST field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_RDADDR_RST_Msk = 0x8
	// Bit BLEND0_CLUT_MEM_RDADDR_RST.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_RDADDR_RST = 0x8
	// Position of BLEND1_CLUT_MEM_RDADDR_RST field.
	PPA_CLUT_CONF_BLEND1_CLUT_MEM_RDADDR_RST_Pos = 0x4
	// Bit mask of BLEND1_CLUT_MEM_RDADDR_RST field.
	PPA_CLUT_CONF_BLEND1_CLUT_MEM_RDADDR_RST_Msk = 0x10
	// Bit BLEND1_CLUT_MEM_RDADDR_RST.
	PPA_CLUT_CONF_BLEND1_CLUT_MEM_RDADDR_RST = 0x10
	// Position of BLEND0_CLUT_MEM_FORCE_PD field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_FORCE_PD_Pos = 0x5
	// Bit mask of BLEND0_CLUT_MEM_FORCE_PD field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_FORCE_PD_Msk = 0x20
	// Bit BLEND0_CLUT_MEM_FORCE_PD.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_FORCE_PD = 0x20
	// Position of BLEND0_CLUT_MEM_FORCE_PU field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_FORCE_PU_Pos = 0x6
	// Bit mask of BLEND0_CLUT_MEM_FORCE_PU field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_FORCE_PU_Msk = 0x40
	// Bit BLEND0_CLUT_MEM_FORCE_PU.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_FORCE_PU = 0x40
	// Position of BLEND0_CLUT_MEM_CLK_ENA field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_CLK_ENA_Pos = 0x7
	// Bit mask of BLEND0_CLUT_MEM_CLK_ENA field.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_CLK_ENA_Msk = 0x80
	// Bit BLEND0_CLUT_MEM_CLK_ENA.
	PPA_CLUT_CONF_BLEND0_CLUT_MEM_CLK_ENA = 0x80

	// INT_RAW: Raw status interrupt
	// Position of SR_EOF_INT_RAW field.
	PPA_INT_RAW_SR_EOF_INT_RAW_Pos = 0x0
	// Bit mask of SR_EOF_INT_RAW field.
	PPA_INT_RAW_SR_EOF_INT_RAW_Msk = 0x1
	// Bit SR_EOF_INT_RAW.
	PPA_INT_RAW_SR_EOF_INT_RAW = 0x1
	// Position of BLEND_EOF_INT_RAW field.
	PPA_INT_RAW_BLEND_EOF_INT_RAW_Pos = 0x1
	// Bit mask of BLEND_EOF_INT_RAW field.
	PPA_INT_RAW_BLEND_EOF_INT_RAW_Msk = 0x2
	// Bit BLEND_EOF_INT_RAW.
	PPA_INT_RAW_BLEND_EOF_INT_RAW = 0x2
	// Position of SR_PARAM_CFG_ERR_INT_RAW field.
	PPA_INT_RAW_SR_PARAM_CFG_ERR_INT_RAW_Pos = 0x2
	// Bit mask of SR_PARAM_CFG_ERR_INT_RAW field.
	PPA_INT_RAW_SR_PARAM_CFG_ERR_INT_RAW_Msk = 0x4
	// Bit SR_PARAM_CFG_ERR_INT_RAW.
	PPA_INT_RAW_SR_PARAM_CFG_ERR_INT_RAW = 0x4

	// INT_ST: Masked interrupt
	// Position of SR_EOF_INT_ST field.
	PPA_INT_ST_SR_EOF_INT_ST_Pos = 0x0
	// Bit mask of SR_EOF_INT_ST field.
	PPA_INT_ST_SR_EOF_INT_ST_Msk = 0x1
	// Bit SR_EOF_INT_ST.
	PPA_INT_ST_SR_EOF_INT_ST = 0x1
	// Position of BLEND_EOF_INT_ST field.
	PPA_INT_ST_BLEND_EOF_INT_ST_Pos = 0x1
	// Bit mask of BLEND_EOF_INT_ST field.
	PPA_INT_ST_BLEND_EOF_INT_ST_Msk = 0x2
	// Bit BLEND_EOF_INT_ST.
	PPA_INT_ST_BLEND_EOF_INT_ST = 0x2
	// Position of SR_PARAM_CFG_ERR_INT_ST field.
	PPA_INT_ST_SR_PARAM_CFG_ERR_INT_ST_Pos = 0x2
	// Bit mask of SR_PARAM_CFG_ERR_INT_ST field.
	PPA_INT_ST_SR_PARAM_CFG_ERR_INT_ST_Msk = 0x4
	// Bit SR_PARAM_CFG_ERR_INT_ST.
	PPA_INT_ST_SR_PARAM_CFG_ERR_INT_ST = 0x4

	// INT_ENA: Interrupt enable bits
	// Position of SR_EOF_INT_ENA field.
	PPA_INT_ENA_SR_EOF_INT_ENA_Pos = 0x0
	// Bit mask of SR_EOF_INT_ENA field.
	PPA_INT_ENA_SR_EOF_INT_ENA_Msk = 0x1
	// Bit SR_EOF_INT_ENA.
	PPA_INT_ENA_SR_EOF_INT_ENA = 0x1
	// Position of BLEND_EOF_INT_ENA field.
	PPA_INT_ENA_BLEND_EOF_INT_ENA_Pos = 0x1
	// Bit mask of BLEND_EOF_INT_ENA field.
	PPA_INT_ENA_BLEND_EOF_INT_ENA_Msk = 0x2
	// Bit BLEND_EOF_INT_ENA.
	PPA_INT_ENA_BLEND_EOF_INT_ENA = 0x2
	// Position of SR_PARAM_CFG_ERR_INT_ENA field.
	PPA_INT_ENA_SR_PARAM_CFG_ERR_INT_ENA_Pos = 0x2
	// Bit mask of SR_PARAM_CFG_ERR_INT_ENA field.
	PPA_INT_ENA_SR_PARAM_CFG_ERR_INT_ENA_Msk = 0x4
	// Bit SR_PARAM_CFG_ERR_INT_ENA.
	PPA_INT_ENA_SR_PARAM_CFG_ERR_INT_ENA = 0x4

	// INT_CLR: Interrupt clear bits
	// Position of SR_EOF_INT_CLR field.
	PPA_INT_CLR_SR_EOF_INT_CLR_Pos = 0x0
	// Bit mask of SR_EOF_INT_CLR field.
	PPA_INT_CLR_SR_EOF_INT_CLR_Msk = 0x1
	// Bit SR_EOF_INT_CLR.
	PPA_INT_CLR_SR_EOF_INT_CLR = 0x1
	// Position of BLEND_EOF_INT_CLR field.
	PPA_INT_CLR_BLEND_EOF_INT_CLR_Pos = 0x1
	// Bit mask of BLEND_EOF_INT_CLR field.
	PPA_INT_CLR_BLEND_EOF_INT_CLR_Msk = 0x2
	// Bit BLEND_EOF_INT_CLR.
	PPA_INT_CLR_BLEND_EOF_INT_CLR = 0x2
	// Position of SR_PARAM_CFG_ERR_INT_CLR field.
	PPA_INT_CLR_SR_PARAM_CFG_ERR_INT_CLR_Pos = 0x2
	// Bit mask of SR_PARAM_CFG_ERR_INT_CLR field.
	PPA_INT_CLR_SR_PARAM_CFG_ERR_INT_CLR_Msk = 0x4
	// Bit SR_PARAM_CFG_ERR_INT_CLR.
	PPA_INT_CLR_SR_PARAM_CFG_ERR_INT_CLR = 0x4

	// SR_COLOR_MODE: Scaling and rotating engine color mode register
	// Position of SR_RX_CM field.
	PPA_SR_COLOR_MODE_SR_RX_CM_Pos = 0x0
	// Bit mask of SR_RX_CM field.
	PPA_SR_COLOR_MODE_SR_RX_CM_Msk = 0xf
	// Position of SR_TX_CM field.
	PPA_SR_COLOR_MODE_SR_TX_CM_Pos = 0x4
	// Bit mask of SR_TX_CM field.
	PPA_SR_COLOR_MODE_SR_TX_CM_Msk = 0xf0
	// Position of YUV_RX_RANGE field.
	PPA_SR_COLOR_MODE_YUV_RX_RANGE_Pos = 0x8
	// Bit mask of YUV_RX_RANGE field.
	PPA_SR_COLOR_MODE_YUV_RX_RANGE_Msk = 0x100
	// Bit YUV_RX_RANGE.
	PPA_SR_COLOR_MODE_YUV_RX_RANGE = 0x100
	// Position of YUV_TX_RANGE field.
	PPA_SR_COLOR_MODE_YUV_TX_RANGE_Pos = 0x9
	// Bit mask of YUV_TX_RANGE field.
	PPA_SR_COLOR_MODE_YUV_TX_RANGE_Msk = 0x200
	// Bit YUV_TX_RANGE.
	PPA_SR_COLOR_MODE_YUV_TX_RANGE = 0x200
	// Position of YUV2RGB_PROTOCAL field.
	PPA_SR_COLOR_MODE_YUV2RGB_PROTOCAL_Pos = 0xa
	// Bit mask of YUV2RGB_PROTOCAL field.
	PPA_SR_COLOR_MODE_YUV2RGB_PROTOCAL_Msk = 0x400
	// Bit YUV2RGB_PROTOCAL.
	PPA_SR_COLOR_MODE_YUV2RGB_PROTOCAL = 0x400
	// Position of RGB2YUV_PROTOCAL field.
	PPA_SR_COLOR_MODE_RGB2YUV_PROTOCAL_Pos = 0xb
	// Bit mask of RGB2YUV_PROTOCAL field.
	PPA_SR_COLOR_MODE_RGB2YUV_PROTOCAL_Msk = 0x800
	// Bit RGB2YUV_PROTOCAL.
	PPA_SR_COLOR_MODE_RGB2YUV_PROTOCAL = 0x800

	// BLEND_COLOR_MODE: blending engine color mode register
	// Position of BLEND0_RX_CM field.
	PPA_BLEND_COLOR_MODE_BLEND0_RX_CM_Pos = 0x0
	// Bit mask of BLEND0_RX_CM field.
	PPA_BLEND_COLOR_MODE_BLEND0_RX_CM_Msk = 0xf
	// Position of BLEND1_RX_CM field.
	PPA_BLEND_COLOR_MODE_BLEND1_RX_CM_Pos = 0x4
	// Bit mask of BLEND1_RX_CM field.
	PPA_BLEND_COLOR_MODE_BLEND1_RX_CM_Msk = 0xf0
	// Position of BLEND_TX_CM field.
	PPA_BLEND_COLOR_MODE_BLEND_TX_CM_Pos = 0x8
	// Bit mask of BLEND_TX_CM field.
	PPA_BLEND_COLOR_MODE_BLEND_TX_CM_Msk = 0xf00

	// SR_BYTE_ORDER: Scaling and rotating engine byte order register
	// Position of SR_RX_BYTE_SWAP_EN field.
	PPA_SR_BYTE_ORDER_SR_RX_BYTE_SWAP_EN_Pos = 0x0
	// Bit mask of SR_RX_BYTE_SWAP_EN field.
	PPA_SR_BYTE_ORDER_SR_RX_BYTE_SWAP_EN_Msk = 0x1
	// Bit SR_RX_BYTE_SWAP_EN.
	PPA_SR_BYTE_ORDER_SR_RX_BYTE_SWAP_EN = 0x1
	// Position of SR_RX_RGB_SWAP_EN field.
	PPA_SR_BYTE_ORDER_SR_RX_RGB_SWAP_EN_Pos = 0x1
	// Bit mask of SR_RX_RGB_SWAP_EN field.
	PPA_SR_BYTE_ORDER_SR_RX_RGB_SWAP_EN_Msk = 0x2
	// Bit SR_RX_RGB_SWAP_EN.
	PPA_SR_BYTE_ORDER_SR_RX_RGB_SWAP_EN = 0x2
	// Position of SR_MACRO_BK_RO_BYPASS field.
	PPA_SR_BYTE_ORDER_SR_MACRO_BK_RO_BYPASS_Pos = 0x2
	// Bit mask of SR_MACRO_BK_RO_BYPASS field.
	PPA_SR_BYTE_ORDER_SR_MACRO_BK_RO_BYPASS_Msk = 0x4
	// Bit SR_MACRO_BK_RO_BYPASS.
	PPA_SR_BYTE_ORDER_SR_MACRO_BK_RO_BYPASS = 0x4

	// BLEND_BYTE_ORDER: Blending engine byte order register
	// Position of BLEND0_RX_BYTE_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND0_RX_BYTE_SWAP_EN_Pos = 0x0
	// Bit mask of BLEND0_RX_BYTE_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND0_RX_BYTE_SWAP_EN_Msk = 0x1
	// Bit BLEND0_RX_BYTE_SWAP_EN.
	PPA_BLEND_BYTE_ORDER_BLEND0_RX_BYTE_SWAP_EN = 0x1
	// Position of BLEND1_RX_BYTE_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND1_RX_BYTE_SWAP_EN_Pos = 0x1
	// Bit mask of BLEND1_RX_BYTE_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND1_RX_BYTE_SWAP_EN_Msk = 0x2
	// Bit BLEND1_RX_BYTE_SWAP_EN.
	PPA_BLEND_BYTE_ORDER_BLEND1_RX_BYTE_SWAP_EN = 0x2
	// Position of BLEND0_RX_RGB_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND0_RX_RGB_SWAP_EN_Pos = 0x2
	// Bit mask of BLEND0_RX_RGB_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND0_RX_RGB_SWAP_EN_Msk = 0x4
	// Bit BLEND0_RX_RGB_SWAP_EN.
	PPA_BLEND_BYTE_ORDER_BLEND0_RX_RGB_SWAP_EN = 0x4
	// Position of BLEND1_RX_RGB_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND1_RX_RGB_SWAP_EN_Pos = 0x3
	// Bit mask of BLEND1_RX_RGB_SWAP_EN field.
	PPA_BLEND_BYTE_ORDER_BLEND1_RX_RGB_SWAP_EN_Msk = 0x8
	// Bit BLEND1_RX_RGB_SWAP_EN.
	PPA_BLEND_BYTE_ORDER_BLEND1_RX_RGB_SWAP_EN = 0x8

	// BLEND_TRANS_MODE: Blending engine mode configure register
	// Position of BLEND_EN field.
	PPA_BLEND_TRANS_MODE_BLEND_EN_Pos = 0x0
	// Bit mask of BLEND_EN field.
	PPA_BLEND_TRANS_MODE_BLEND_EN_Msk = 0x1
	// Bit BLEND_EN.
	PPA_BLEND_TRANS_MODE_BLEND_EN = 0x1
	// Position of BLEND_BYPASS field.
	PPA_BLEND_TRANS_MODE_BLEND_BYPASS_Pos = 0x1
	// Bit mask of BLEND_BYPASS field.
	PPA_BLEND_TRANS_MODE_BLEND_BYPASS_Msk = 0x2
	// Bit BLEND_BYPASS.
	PPA_BLEND_TRANS_MODE_BLEND_BYPASS = 0x2
	// Position of BLEND_FIX_PIXEL_FILL_EN field.
	PPA_BLEND_TRANS_MODE_BLEND_FIX_PIXEL_FILL_EN_Pos = 0x2
	// Bit mask of BLEND_FIX_PIXEL_FILL_EN field.
	PPA_BLEND_TRANS_MODE_BLEND_FIX_PIXEL_FILL_EN_Msk = 0x4
	// Bit BLEND_FIX_PIXEL_FILL_EN.
	PPA_BLEND_TRANS_MODE_BLEND_FIX_PIXEL_FILL_EN = 0x4
	// Position of UPDATE field.
	PPA_BLEND_TRANS_MODE_UPDATE_Pos = 0x3
	// Bit mask of UPDATE field.
	PPA_BLEND_TRANS_MODE_UPDATE_Msk = 0x8
	// Bit UPDATE.
	PPA_BLEND_TRANS_MODE_UPDATE = 0x8
	// Position of BLEND_RST field.
	PPA_BLEND_TRANS_MODE_BLEND_RST_Pos = 0x4
	// Bit mask of BLEND_RST field.
	PPA_BLEND_TRANS_MODE_BLEND_RST_Msk = 0x10
	// Bit BLEND_RST.
	PPA_BLEND_TRANS_MODE_BLEND_RST = 0x10

	// SR_FIX_ALPHA: Scaling and rotating engine alpha override register
	// Position of SR_RX_FIX_ALPHA field.
	PPA_SR_FIX_ALPHA_SR_RX_FIX_ALPHA_Pos = 0x0
	// Bit mask of SR_RX_FIX_ALPHA field.
	PPA_SR_FIX_ALPHA_SR_RX_FIX_ALPHA_Msk = 0xff
	// Position of SR_RX_ALPHA_MOD field.
	PPA_SR_FIX_ALPHA_SR_RX_ALPHA_MOD_Pos = 0x8
	// Bit mask of SR_RX_ALPHA_MOD field.
	PPA_SR_FIX_ALPHA_SR_RX_ALPHA_MOD_Msk = 0x300
	// Position of SR_RX_ALPHA_INV field.
	PPA_SR_FIX_ALPHA_SR_RX_ALPHA_INV_Pos = 0xa
	// Bit mask of SR_RX_ALPHA_INV field.
	PPA_SR_FIX_ALPHA_SR_RX_ALPHA_INV_Msk = 0x400
	// Bit SR_RX_ALPHA_INV.
	PPA_SR_FIX_ALPHA_SR_RX_ALPHA_INV = 0x400

	// BLEND_TX_SIZE: Fix pixel filling mode image size register
	// Position of BLEND_HB field.
	PPA_BLEND_TX_SIZE_BLEND_HB_Pos = 0x0
	// Bit mask of BLEND_HB field.
	PPA_BLEND_TX_SIZE_BLEND_HB_Msk = 0x3fff
	// Position of BLEND_VB field.
	PPA_BLEND_TX_SIZE_BLEND_VB_Pos = 0xe
	// Bit mask of BLEND_VB field.
	PPA_BLEND_TX_SIZE_BLEND_VB_Msk = 0xfffc000

	// BLEND_FIX_ALPHA: Blending engine alpha override register
	// Position of BLEND0_RX_FIX_ALPHA field.
	PPA_BLEND_FIX_ALPHA_BLEND0_RX_FIX_ALPHA_Pos = 0x0
	// Bit mask of BLEND0_RX_FIX_ALPHA field.
	PPA_BLEND_FIX_ALPHA_BLEND0_RX_FIX_ALPHA_Msk = 0xff
	// Position of BLEND1_RX_FIX_ALPHA field.
	PPA_BLEND_FIX_ALPHA_BLEND1_RX_FIX_ALPHA_Pos = 0x8
	// Bit mask of BLEND1_RX_FIX_ALPHA field.
	PPA_BLEND_FIX_ALPHA_BLEND1_RX_FIX_ALPHA_Msk = 0xff00
	// Position of BLEND0_RX_ALPHA_MOD field.
	PPA_BLEND_FIX_ALPHA_BLEND0_RX_ALPHA_MOD_Pos = 0x10
	// Bit mask of BLEND0_RX_ALPHA_MOD field.
	PPA_BLEND_FIX_ALPHA_BLEND0_RX_ALPHA_MOD_Msk = 0x30000
	// Position of BLEND1_RX_ALPHA_MOD field.
	PPA_BLEND_FIX_ALPHA_BLEND1_RX_ALPHA_MOD_Pos = 0x12
	// Bit mask of BLEND1_RX_ALPHA_MOD field.
	PPA_BLEND_FIX_ALPHA_BLEND1_RX_ALPHA_MOD_Msk = 0xc0000
	// Position of BLEND0_RX_ALPHA_INV field.
	PPA_BLEND_FIX_ALPHA_BLEND0_RX_ALPHA_INV_Pos = 0x14
	// Bit mask of BLEND0_RX_ALPHA_INV field.
	PPA_BLEND_FIX_ALPHA_BLEND0_RX_ALPHA_INV_Msk = 0x100000
	// Bit BLEND0_RX_ALPHA_INV.
	PPA_BLEND_FIX_ALPHA_BLEND0_RX_ALPHA_INV = 0x100000
	// Position of BLEND1_RX_ALPHA_INV field.
	PPA_BLEND_FIX_ALPHA_BLEND1_RX_ALPHA_INV_Pos = 0x15
	// Bit mask of BLEND1_RX_ALPHA_INV field.
	PPA_BLEND_FIX_ALPHA_BLEND1_RX_ALPHA_INV_Msk = 0x200000
	// Bit BLEND1_RX_ALPHA_INV.
	PPA_BLEND_FIX_ALPHA_BLEND1_RX_ALPHA_INV = 0x200000

	// BLEND_RGB: RGB color register
	// Position of BLEND1_RX_B field.
	PPA_BLEND_RGB_BLEND1_RX_B_Pos = 0x0
	// Bit mask of BLEND1_RX_B field.
	PPA_BLEND_RGB_BLEND1_RX_B_Msk = 0xff
	// Position of BLEND1_RX_G field.
	PPA_BLEND_RGB_BLEND1_RX_G_Pos = 0x8
	// Bit mask of BLEND1_RX_G field.
	PPA_BLEND_RGB_BLEND1_RX_G_Msk = 0xff00
	// Position of BLEND1_RX_R field.
	PPA_BLEND_RGB_BLEND1_RX_R_Pos = 0x10
	// Bit mask of BLEND1_RX_R field.
	PPA_BLEND_RGB_BLEND1_RX_R_Msk = 0xff0000

	// BLEND_FIX_PIXEL: Blending engine fix pixel register
	// Position of BLEND_TX_FIX_PIXEL field.
	PPA_BLEND_FIX_PIXEL_BLEND_TX_FIX_PIXEL_Pos = 0x0
	// Bit mask of BLEND_TX_FIX_PIXEL field.
	PPA_BLEND_FIX_PIXEL_BLEND_TX_FIX_PIXEL_Msk = 0xffffffff

	// CK_FG_LOW: foreground color key lower threshold
	// Position of COLORKEY_FG_B_LOW field.
	PPA_CK_FG_LOW_COLORKEY_FG_B_LOW_Pos = 0x0
	// Bit mask of COLORKEY_FG_B_LOW field.
	PPA_CK_FG_LOW_COLORKEY_FG_B_LOW_Msk = 0xff
	// Position of COLORKEY_FG_G_LOW field.
	PPA_CK_FG_LOW_COLORKEY_FG_G_LOW_Pos = 0x8
	// Bit mask of COLORKEY_FG_G_LOW field.
	PPA_CK_FG_LOW_COLORKEY_FG_G_LOW_Msk = 0xff00
	// Position of COLORKEY_FG_R_LOW field.
	PPA_CK_FG_LOW_COLORKEY_FG_R_LOW_Pos = 0x10
	// Bit mask of COLORKEY_FG_R_LOW field.
	PPA_CK_FG_LOW_COLORKEY_FG_R_LOW_Msk = 0xff0000

	// CK_FG_HIGH: foreground color key higher threshold
	// Position of COLORKEY_FG_B_HIGH field.
	PPA_CK_FG_HIGH_COLORKEY_FG_B_HIGH_Pos = 0x0
	// Bit mask of COLORKEY_FG_B_HIGH field.
	PPA_CK_FG_HIGH_COLORKEY_FG_B_HIGH_Msk = 0xff
	// Position of COLORKEY_FG_G_HIGH field.
	PPA_CK_FG_HIGH_COLORKEY_FG_G_HIGH_Pos = 0x8
	// Bit mask of COLORKEY_FG_G_HIGH field.
	PPA_CK_FG_HIGH_COLORKEY_FG_G_HIGH_Msk = 0xff00
	// Position of COLORKEY_FG_R_HIGH field.
	PPA_CK_FG_HIGH_COLORKEY_FG_R_HIGH_Pos = 0x10
	// Bit mask of COLORKEY_FG_R_HIGH field.
	PPA_CK_FG_HIGH_COLORKEY_FG_R_HIGH_Msk = 0xff0000

	// CK_BG_LOW: background color key lower threshold
	// Position of COLORKEY_BG_B_LOW field.
	PPA_CK_BG_LOW_COLORKEY_BG_B_LOW_Pos = 0x0
	// Bit mask of COLORKEY_BG_B_LOW field.
	PPA_CK_BG_LOW_COLORKEY_BG_B_LOW_Msk = 0xff
	// Position of COLORKEY_BG_G_LOW field.
	PPA_CK_BG_LOW_COLORKEY_BG_G_LOW_Pos = 0x8
	// Bit mask of COLORKEY_BG_G_LOW field.
	PPA_CK_BG_LOW_COLORKEY_BG_G_LOW_Msk = 0xff00
	// Position of COLORKEY_BG_R_LOW field.
	PPA_CK_BG_LOW_COLORKEY_BG_R_LOW_Pos = 0x10
	// Bit mask of COLORKEY_BG_R_LOW field.
	PPA_CK_BG_LOW_COLORKEY_BG_R_LOW_Msk = 0xff0000

	// CK_BG_HIGH: background color key higher threshold
	// Position of COLORKEY_BG_B_HIGH field.
	PPA_CK_BG_HIGH_COLORKEY_BG_B_HIGH_Pos = 0x0
	// Bit mask of COLORKEY_BG_B_HIGH field.
	PPA_CK_BG_HIGH_COLORKEY_BG_B_HIGH_Msk = 0xff
	// Position of COLORKEY_BG_G_HIGH field.
	PPA_CK_BG_HIGH_COLORKEY_BG_G_HIGH_Pos = 0x8
	// Bit mask of COLORKEY_BG_G_HIGH field.
	PPA_CK_BG_HIGH_COLORKEY_BG_G_HIGH_Msk = 0xff00
	// Position of COLORKEY_BG_R_HIGH field.
	PPA_CK_BG_HIGH_COLORKEY_BG_R_HIGH_Pos = 0x10
	// Bit mask of COLORKEY_BG_R_HIGH field.
	PPA_CK_BG_HIGH_COLORKEY_BG_R_HIGH_Msk = 0xff0000

	// CK_DEFAULT: default value when foreground and background both in color key range
	// Position of COLORKEY_DEFAULT_B field.
	PPA_CK_DEFAULT_COLORKEY_DEFAULT_B_Pos = 0x0
	// Bit mask of COLORKEY_DEFAULT_B field.
	PPA_CK_DEFAULT_COLORKEY_DEFAULT_B_Msk = 0xff
	// Position of COLORKEY_DEFAULT_G field.
	PPA_CK_DEFAULT_COLORKEY_DEFAULT_G_Pos = 0x8
	// Bit mask of COLORKEY_DEFAULT_G field.
	PPA_CK_DEFAULT_COLORKEY_DEFAULT_G_Msk = 0xff00
	// Position of COLORKEY_DEFAULT_R field.
	PPA_CK_DEFAULT_COLORKEY_DEFAULT_R_Pos = 0x10
	// Bit mask of COLORKEY_DEFAULT_R field.
	PPA_CK_DEFAULT_COLORKEY_DEFAULT_R_Msk = 0xff0000
	// Position of COLORKEY_FG_BG_REVERSE field.
	PPA_CK_DEFAULT_COLORKEY_FG_BG_REVERSE_Pos = 0x18
	// Bit mask of COLORKEY_FG_BG_REVERSE field.
	PPA_CK_DEFAULT_COLORKEY_FG_BG_REVERSE_Msk = 0x1000000
	// Bit COLORKEY_FG_BG_REVERSE.
	PPA_CK_DEFAULT_COLORKEY_FG_BG_REVERSE = 0x1000000

	// SR_SCAL_ROTATE: Scaling and rotating coefficient register
	// Position of SR_SCAL_X_INT field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_X_INT_Pos = 0x0
	// Bit mask of SR_SCAL_X_INT field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_X_INT_Msk = 0xff
	// Position of SR_SCAL_X_FRAG field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_X_FRAG_Pos = 0x8
	// Bit mask of SR_SCAL_X_FRAG field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_X_FRAG_Msk = 0xf00
	// Position of SR_SCAL_Y_INT field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_Y_INT_Pos = 0xc
	// Bit mask of SR_SCAL_Y_INT field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_Y_INT_Msk = 0xff000
	// Position of SR_SCAL_Y_FRAG field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_Y_FRAG_Pos = 0x14
	// Bit mask of SR_SCAL_Y_FRAG field.
	PPA_SR_SCAL_ROTATE_SR_SCAL_Y_FRAG_Msk = 0xf00000
	// Position of SR_ROTATE_ANGLE field.
	PPA_SR_SCAL_ROTATE_SR_ROTATE_ANGLE_Pos = 0x18
	// Bit mask of SR_ROTATE_ANGLE field.
	PPA_SR_SCAL_ROTATE_SR_ROTATE_ANGLE_Msk = 0x3000000
	// Position of SCAL_ROTATE_RST field.
	PPA_SR_SCAL_ROTATE_SCAL_ROTATE_RST_Pos = 0x1a
	// Bit mask of SCAL_ROTATE_RST field.
	PPA_SR_SCAL_ROTATE_SCAL_ROTATE_RST_Msk = 0x4000000
	// Bit SCAL_ROTATE_RST.
	PPA_SR_SCAL_ROTATE_SCAL_ROTATE_RST = 0x4000000
	// Position of SCAL_ROTATE_START field.
	PPA_SR_SCAL_ROTATE_SCAL_ROTATE_START_Pos = 0x1b
	// Bit mask of SCAL_ROTATE_START field.
	PPA_SR_SCAL_ROTATE_SCAL_ROTATE_START_Msk = 0x8000000
	// Bit SCAL_ROTATE_START.
	PPA_SR_SCAL_ROTATE_SCAL_ROTATE_START = 0x8000000
	// Position of SR_MIRROR_X field.
	PPA_SR_SCAL_ROTATE_SR_MIRROR_X_Pos = 0x1c
	// Bit mask of SR_MIRROR_X field.
	PPA_SR_SCAL_ROTATE_SR_MIRROR_X_Msk = 0x10000000
	// Bit SR_MIRROR_X.
	PPA_SR_SCAL_ROTATE_SR_MIRROR_X = 0x10000000
	// Position of SR_MIRROR_Y field.
	PPA_SR_SCAL_ROTATE_SR_MIRROR_Y_Pos = 0x1d
	// Bit mask of SR_MIRROR_Y field.
	PPA_SR_SCAL_ROTATE_SR_MIRROR_Y_Msk = 0x20000000
	// Bit SR_MIRROR_Y.
	PPA_SR_SCAL_ROTATE_SR_MIRROR_Y = 0x20000000

	// SR_MEM_PD: SR memory power done register
	// Position of SR_MEM_CLK_ENA field.
	PPA_SR_MEM_PD_SR_MEM_CLK_ENA_Pos = 0x0
	// Bit mask of SR_MEM_CLK_ENA field.
	PPA_SR_MEM_PD_SR_MEM_CLK_ENA_Msk = 0x1
	// Bit SR_MEM_CLK_ENA.
	PPA_SR_MEM_PD_SR_MEM_CLK_ENA = 0x1
	// Position of SR_MEM_FORCE_PD field.
	PPA_SR_MEM_PD_SR_MEM_FORCE_PD_Pos = 0x1
	// Bit mask of SR_MEM_FORCE_PD field.
	PPA_SR_MEM_PD_SR_MEM_FORCE_PD_Msk = 0x2
	// Bit SR_MEM_FORCE_PD.
	PPA_SR_MEM_PD_SR_MEM_FORCE_PD = 0x2
	// Position of SR_MEM_FORCE_PU field.
	PPA_SR_MEM_PD_SR_MEM_FORCE_PU_Pos = 0x2
	// Bit mask of SR_MEM_FORCE_PU field.
	PPA_SR_MEM_PD_SR_MEM_FORCE_PU_Msk = 0x4
	// Bit SR_MEM_FORCE_PU.
	PPA_SR_MEM_PD_SR_MEM_FORCE_PU = 0x4

	// REG_CONF: Register clock enable register
	// Position of CLK_EN field.
	PPA_REG_CONF_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	PPA_REG_CONF_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	PPA_REG_CONF_CLK_EN = 0x1

	// CLUT_CNT: BLEND CLUT write counter register
	// Position of BLEND0_CLUT_CNT field.
	PPA_CLUT_CNT_BLEND0_CLUT_CNT_Pos = 0x0
	// Bit mask of BLEND0_CLUT_CNT field.
	PPA_CLUT_CNT_BLEND0_CLUT_CNT_Msk = 0x1ff
	// Position of BLEND1_CLUT_CNT field.
	PPA_CLUT_CNT_BLEND1_CLUT_CNT_Pos = 0x9
	// Bit mask of BLEND1_CLUT_CNT field.
	PPA_CLUT_CNT_BLEND1_CLUT_CNT_Msk = 0x3fe00

	// BLEND_ST: Blending engine status register
	// Position of BLEND_SIZE_DIFF_ST field.
	PPA_BLEND_ST_BLEND_SIZE_DIFF_ST_Pos = 0x0
	// Bit mask of BLEND_SIZE_DIFF_ST field.
	PPA_BLEND_ST_BLEND_SIZE_DIFF_ST_Msk = 0x1
	// Bit BLEND_SIZE_DIFF_ST.
	PPA_BLEND_ST_BLEND_SIZE_DIFF_ST = 0x1

	// SR_PARAM_ERR_ST: Scaling and rotating coefficient error register
	// Position of TX_DSCR_VB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_TX_DSCR_VB_ERR_ST_Pos = 0x0
	// Bit mask of TX_DSCR_VB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_TX_DSCR_VB_ERR_ST_Msk = 0x1
	// Bit TX_DSCR_VB_ERR_ST.
	PPA_SR_PARAM_ERR_ST_TX_DSCR_VB_ERR_ST = 0x1
	// Position of TX_DSCR_HB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_TX_DSCR_HB_ERR_ST_Pos = 0x1
	// Bit mask of TX_DSCR_HB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_TX_DSCR_HB_ERR_ST_Msk = 0x2
	// Bit TX_DSCR_HB_ERR_ST.
	PPA_SR_PARAM_ERR_ST_TX_DSCR_HB_ERR_ST = 0x2
	// Position of Y_RX_SCAL_EQUAL_0_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_Y_RX_SCAL_EQUAL_0_ERR_ST_Pos = 0x2
	// Bit mask of Y_RX_SCAL_EQUAL_0_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_Y_RX_SCAL_EQUAL_0_ERR_ST_Msk = 0x4
	// Bit Y_RX_SCAL_EQUAL_0_ERR_ST.
	PPA_SR_PARAM_ERR_ST_Y_RX_SCAL_EQUAL_0_ERR_ST = 0x4
	// Position of RX_DSCR_VB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_RX_DSCR_VB_ERR_ST_Pos = 0x3
	// Bit mask of RX_DSCR_VB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_RX_DSCR_VB_ERR_ST_Msk = 0x8
	// Bit RX_DSCR_VB_ERR_ST.
	PPA_SR_PARAM_ERR_ST_RX_DSCR_VB_ERR_ST = 0x8
	// Position of YDST_LEN_TOO_SAMLL_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_YDST_LEN_TOO_SAMLL_ERR_ST_Pos = 0x4
	// Bit mask of YDST_LEN_TOO_SAMLL_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_YDST_LEN_TOO_SAMLL_ERR_ST_Msk = 0x10
	// Bit YDST_LEN_TOO_SAMLL_ERR_ST.
	PPA_SR_PARAM_ERR_ST_YDST_LEN_TOO_SAMLL_ERR_ST = 0x10
	// Position of YDST_LEN_TOO_LARGE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_YDST_LEN_TOO_LARGE_ERR_ST_Pos = 0x5
	// Bit mask of YDST_LEN_TOO_LARGE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_YDST_LEN_TOO_LARGE_ERR_ST_Msk = 0x20
	// Bit YDST_LEN_TOO_LARGE_ERR_ST.
	PPA_SR_PARAM_ERR_ST_YDST_LEN_TOO_LARGE_ERR_ST = 0x20
	// Position of X_RX_SCAL_EQUAL_0_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_X_RX_SCAL_EQUAL_0_ERR_ST_Pos = 0x6
	// Bit mask of X_RX_SCAL_EQUAL_0_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_X_RX_SCAL_EQUAL_0_ERR_ST_Msk = 0x40
	// Bit X_RX_SCAL_EQUAL_0_ERR_ST.
	PPA_SR_PARAM_ERR_ST_X_RX_SCAL_EQUAL_0_ERR_ST = 0x40
	// Position of RX_DSCR_HB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_RX_DSCR_HB_ERR_ST_Pos = 0x7
	// Bit mask of RX_DSCR_HB_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_RX_DSCR_HB_ERR_ST_Msk = 0x80
	// Bit RX_DSCR_HB_ERR_ST.
	PPA_SR_PARAM_ERR_ST_RX_DSCR_HB_ERR_ST = 0x80
	// Position of XDST_LEN_TOO_SAMLL_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_XDST_LEN_TOO_SAMLL_ERR_ST_Pos = 0x8
	// Bit mask of XDST_LEN_TOO_SAMLL_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_XDST_LEN_TOO_SAMLL_ERR_ST_Msk = 0x100
	// Bit XDST_LEN_TOO_SAMLL_ERR_ST.
	PPA_SR_PARAM_ERR_ST_XDST_LEN_TOO_SAMLL_ERR_ST = 0x100
	// Position of XDST_LEN_TOO_LARGE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_XDST_LEN_TOO_LARGE_ERR_ST_Pos = 0x9
	// Bit mask of XDST_LEN_TOO_LARGE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_XDST_LEN_TOO_LARGE_ERR_ST_Msk = 0x200
	// Bit XDST_LEN_TOO_LARGE_ERR_ST.
	PPA_SR_PARAM_ERR_ST_XDST_LEN_TOO_LARGE_ERR_ST = 0x200
	// Position of X_YUV420_RX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_X_YUV420_RX_SCALE_ERR_ST_Pos = 0xa
	// Bit mask of X_YUV420_RX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_X_YUV420_RX_SCALE_ERR_ST_Msk = 0x400
	// Bit X_YUV420_RX_SCALE_ERR_ST.
	PPA_SR_PARAM_ERR_ST_X_YUV420_RX_SCALE_ERR_ST = 0x400
	// Position of Y_YUV420_RX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_Y_YUV420_RX_SCALE_ERR_ST_Pos = 0xb
	// Bit mask of Y_YUV420_RX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_Y_YUV420_RX_SCALE_ERR_ST_Msk = 0x800
	// Bit Y_YUV420_RX_SCALE_ERR_ST.
	PPA_SR_PARAM_ERR_ST_Y_YUV420_RX_SCALE_ERR_ST = 0x800
	// Position of X_YUV420_TX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_X_YUV420_TX_SCALE_ERR_ST_Pos = 0xc
	// Bit mask of X_YUV420_TX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_X_YUV420_TX_SCALE_ERR_ST_Msk = 0x1000
	// Bit X_YUV420_TX_SCALE_ERR_ST.
	PPA_SR_PARAM_ERR_ST_X_YUV420_TX_SCALE_ERR_ST = 0x1000
	// Position of Y_YUV420_TX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_Y_YUV420_TX_SCALE_ERR_ST_Pos = 0xd
	// Bit mask of Y_YUV420_TX_SCALE_ERR_ST field.
	PPA_SR_PARAM_ERR_ST_Y_YUV420_TX_SCALE_ERR_ST_Msk = 0x2000
	// Bit Y_YUV420_TX_SCALE_ERR_ST.
	PPA_SR_PARAM_ERR_ST_Y_YUV420_TX_SCALE_ERR_ST = 0x2000

	// SR_STATUS: SR FSM register
	// Position of SR_RX_DSCR_SAMPLE_STATE field.
	PPA_SR_STATUS_SR_RX_DSCR_SAMPLE_STATE_Pos = 0x0
	// Bit mask of SR_RX_DSCR_SAMPLE_STATE field.
	PPA_SR_STATUS_SR_RX_DSCR_SAMPLE_STATE_Msk = 0x3
	// Position of SR_RX_SCAN_STATE field.
	PPA_SR_STATUS_SR_RX_SCAN_STATE_Pos = 0x2
	// Bit mask of SR_RX_SCAN_STATE field.
	PPA_SR_STATUS_SR_RX_SCAN_STATE_Msk = 0xc
	// Position of SR_TX_DSCR_SAMPLE_STATE field.
	PPA_SR_STATUS_SR_TX_DSCR_SAMPLE_STATE_Pos = 0x4
	// Bit mask of SR_TX_DSCR_SAMPLE_STATE field.
	PPA_SR_STATUS_SR_TX_DSCR_SAMPLE_STATE_Msk = 0x30
	// Position of SR_TX_SCAN_STATE field.
	PPA_SR_STATUS_SR_TX_SCAN_STATE_Pos = 0x6
	// Bit mask of SR_TX_SCAN_STATE field.
	PPA_SR_STATUS_SR_TX_SCAN_STATE_Msk = 0x1c0

	// ECO_LOW: Reserved.
	// Position of RND_ECO_LOW field.
	PPA_ECO_LOW_RND_ECO_LOW_Pos = 0x0
	// Bit mask of RND_ECO_LOW field.
	PPA_ECO_LOW_RND_ECO_LOW_Msk = 0xffffffff

	// ECO_HIGH: Reserved.
	// Position of RND_ECO_HIGH field.
	PPA_ECO_HIGH_RND_ECO_HIGH_Pos = 0x0
	// Bit mask of RND_ECO_HIGH field.
	PPA_ECO_HIGH_RND_ECO_HIGH_Msk = 0xffffffff

	// ECO_CELL_CTRL: Reserved.
	// Position of RDN_RESULT field.
	PPA_ECO_CELL_CTRL_RDN_RESULT_Pos = 0x0
	// Bit mask of RDN_RESULT field.
	PPA_ECO_CELL_CTRL_RDN_RESULT_Msk = 0x1
	// Bit RDN_RESULT.
	PPA_ECO_CELL_CTRL_RDN_RESULT = 0x1
	// Position of RDN_ENA field.
	PPA_ECO_CELL_CTRL_RDN_ENA_Pos = 0x1
	// Bit mask of RDN_ENA field.
	PPA_ECO_CELL_CTRL_RDN_ENA_Msk = 0x2
	// Bit RDN_ENA.
	PPA_ECO_CELL_CTRL_RDN_ENA = 0x2

	// SRAM_CTRL: PPA SRAM Control Register
	// Position of MEM_AUX_CTRL field.
	PPA_SRAM_CTRL_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of MEM_AUX_CTRL field.
	PPA_SRAM_CTRL_MEM_AUX_CTRL_Msk = 0x3fff

	// DATE: PPA Version register
	// Position of DATE field.
	PPA_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	PPA_DATE_DATE_Msk = 0xffffffff
)

// Constants for PVT: PVT Peripheral
const (
	// PMUP_BITMAP_HIGH0: select valid pvt channel
	// Position of PUMP_BITMAP_HIGH0 field.
	PVT_PMUP_BITMAP_HIGH0_PUMP_BITMAP_HIGH0_Pos = 0x0
	// Bit mask of PUMP_BITMAP_HIGH0 field.
	PVT_PMUP_BITMAP_HIGH0_PUMP_BITMAP_HIGH0_Msk = 0xffffffff

	// PMUP_BITMAP_HIGH1: select valid pvt channel
	// Position of PUMP_BITMAP_HIGH1 field.
	PVT_PMUP_BITMAP_HIGH1_PUMP_BITMAP_HIGH1_Pos = 0x0
	// Bit mask of PUMP_BITMAP_HIGH1 field.
	PVT_PMUP_BITMAP_HIGH1_PUMP_BITMAP_HIGH1_Msk = 0xffffffff

	// PMUP_BITMAP_HIGH2: select valid pvt channel
	// Position of PUMP_BITMAP_HIGH2 field.
	PVT_PMUP_BITMAP_HIGH2_PUMP_BITMAP_HIGH2_Pos = 0x0
	// Bit mask of PUMP_BITMAP_HIGH2 field.
	PVT_PMUP_BITMAP_HIGH2_PUMP_BITMAP_HIGH2_Msk = 0xffffffff

	// PMUP_BITMAP_HIGH3: select valid pvt channel
	// Position of PUMP_BITMAP_HIGH3 field.
	PVT_PMUP_BITMAP_HIGH3_PUMP_BITMAP_HIGH3_Pos = 0x0
	// Bit mask of PUMP_BITMAP_HIGH3 field.
	PVT_PMUP_BITMAP_HIGH3_PUMP_BITMAP_HIGH3_Msk = 0xffffffff

	// PMUP_BITMAP_HIGH4: select valid pvt channel
	// Position of PUMP_BITMAP_HIGH4 field.
	PVT_PMUP_BITMAP_HIGH4_PUMP_BITMAP_HIGH4_Pos = 0x0
	// Bit mask of PUMP_BITMAP_HIGH4 field.
	PVT_PMUP_BITMAP_HIGH4_PUMP_BITMAP_HIGH4_Msk = 0xffffffff

	// PMUP_BITMAP_LOW0: select valid pvt channel
	// Position of PUMP_BITMAP_LOW0 field.
	PVT_PMUP_BITMAP_LOW0_PUMP_BITMAP_LOW0_Pos = 0x0
	// Bit mask of PUMP_BITMAP_LOW0 field.
	PVT_PMUP_BITMAP_LOW0_PUMP_BITMAP_LOW0_Msk = 0xffffffff

	// PMUP_BITMAP_LOW1: select valid pvt channel
	// Position of PUMP_BITMAP_LOW1 field.
	PVT_PMUP_BITMAP_LOW1_PUMP_BITMAP_LOW1_Pos = 0x0
	// Bit mask of PUMP_BITMAP_LOW1 field.
	PVT_PMUP_BITMAP_LOW1_PUMP_BITMAP_LOW1_Msk = 0xffffffff

	// PMUP_BITMAP_LOW2: select valid pvt channel
	// Position of PUMP_BITMAP_LOW2 field.
	PVT_PMUP_BITMAP_LOW2_PUMP_BITMAP_LOW2_Pos = 0x0
	// Bit mask of PUMP_BITMAP_LOW2 field.
	PVT_PMUP_BITMAP_LOW2_PUMP_BITMAP_LOW2_Msk = 0xffffffff

	// PMUP_BITMAP_LOW3: select valid pvt channel
	// Position of PUMP_BITMAP_LOW3 field.
	PVT_PMUP_BITMAP_LOW3_PUMP_BITMAP_LOW3_Pos = 0x0
	// Bit mask of PUMP_BITMAP_LOW3 field.
	PVT_PMUP_BITMAP_LOW3_PUMP_BITMAP_LOW3_Msk = 0xffffffff

	// PMUP_BITMAP_LOW4: select valid pvt channel
	// Position of PUMP_BITMAP_LOW4 field.
	PVT_PMUP_BITMAP_LOW4_PUMP_BITMAP_LOW4_Pos = 0x0
	// Bit mask of PUMP_BITMAP_LOW4 field.
	PVT_PMUP_BITMAP_LOW4_PUMP_BITMAP_LOW4_Msk = 0xffffffff

	// PMUP_DRV_CFG: configure pump drv
	// Position of PUMP_EN field.
	PVT_PMUP_DRV_CFG_PUMP_EN_Pos = 0x9
	// Bit mask of PUMP_EN field.
	PVT_PMUP_DRV_CFG_PUMP_EN_Msk = 0x200
	// Bit PUMP_EN.
	PVT_PMUP_DRV_CFG_PUMP_EN = 0x200
	// Position of CLK_EN field.
	PVT_PMUP_DRV_CFG_CLK_EN_Pos = 0xa
	// Bit mask of CLK_EN field.
	PVT_PMUP_DRV_CFG_CLK_EN_Msk = 0x400
	// Bit CLK_EN.
	PVT_PMUP_DRV_CFG_CLK_EN = 0x400
	// Position of PUMP_DRV4 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV4_Pos = 0xb
	// Bit mask of PUMP_DRV4 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV4_Msk = 0x7800
	// Position of PUMP_DRV3 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV3_Pos = 0xf
	// Bit mask of PUMP_DRV3 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV3_Msk = 0x78000
	// Position of PUMP_DRV2 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV2_Pos = 0x13
	// Bit mask of PUMP_DRV2 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV2_Msk = 0x780000
	// Position of PUMP_DRV1 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV1_Pos = 0x17
	// Bit mask of PUMP_DRV1 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV1_Msk = 0x7800000
	// Position of PUMP_DRV0 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV0_Pos = 0x1b
	// Bit mask of PUMP_DRV0 field.
	PVT_PMUP_DRV_CFG_PUMP_DRV0_Msk = 0x78000000

	// PMUP_CHANNEL_CFG: configure the code of valid pump channel code
	// Position of PUMP_CHANNEL_CODE4 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE4_Pos = 0x7
	// Bit mask of PUMP_CHANNEL_CODE4 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE4_Msk = 0xf80
	// Position of PUMP_CHANNEL_CODE3 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE3_Pos = 0xc
	// Bit mask of PUMP_CHANNEL_CODE3 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE3_Msk = 0x1f000
	// Position of PUMP_CHANNEL_CODE2 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE2_Pos = 0x11
	// Bit mask of PUMP_CHANNEL_CODE2 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE2_Msk = 0x3e0000
	// Position of PUMP_CHANNEL_CODE1 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE1_Pos = 0x16
	// Bit mask of PUMP_CHANNEL_CODE1 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE1_Msk = 0x7c00000
	// Position of PUMP_CHANNEL_CODE0 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE0_Pos = 0x1b
	// Bit mask of PUMP_CHANNEL_CODE0 field.
	PVT_PMUP_CHANNEL_CFG_PUMP_CHANNEL_CODE0_Msk = 0xf8000000

	// CLK_CFG: configure pvt clk
	// Position of PUMP_CLK_DIV_NUM field.
	PVT_CLK_CFG_PUMP_CLK_DIV_NUM_Pos = 0x0
	// Bit mask of PUMP_CLK_DIV_NUM field.
	PVT_CLK_CFG_PUMP_CLK_DIV_NUM_Msk = 0xff
	// Position of MONITOR_CLK_PVT_EN field.
	PVT_CLK_CFG_MONITOR_CLK_PVT_EN_Pos = 0x8
	// Bit mask of MONITOR_CLK_PVT_EN field.
	PVT_CLK_CFG_MONITOR_CLK_PVT_EN_Msk = 0x100
	// Bit MONITOR_CLK_PVT_EN.
	PVT_CLK_CFG_MONITOR_CLK_PVT_EN = 0x100
	// Position of CLK_SEL field.
	PVT_CLK_CFG_CLK_SEL_Pos = 0x1f
	// Bit mask of CLK_SEL field.
	PVT_CLK_CFG_CLK_SEL_Msk = 0x80000000
	// Bit CLK_SEL.
	PVT_CLK_CFG_CLK_SEL = 0x80000000

	// DBIAS_CHANNEL_SEL0: needs desc
	// Position of DBIAS_CHANNEL3_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL3_SEL_Pos = 0x4
	// Bit mask of DBIAS_CHANNEL3_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL3_SEL_Msk = 0x7f0
	// Position of DBIAS_CHANNEL2_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL2_SEL_Pos = 0xb
	// Bit mask of DBIAS_CHANNEL2_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL2_SEL_Msk = 0x3f800
	// Position of DBIAS_CHANNEL1_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL1_SEL_Pos = 0x12
	// Bit mask of DBIAS_CHANNEL1_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL1_SEL_Msk = 0x1fc0000
	// Position of DBIAS_CHANNEL0_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL0_SEL_Pos = 0x19
	// Bit mask of DBIAS_CHANNEL0_SEL field.
	PVT_DBIAS_CHANNEL_SEL0_DBIAS_CHANNEL0_SEL_Msk = 0xfe000000

	// DBIAS_CHANNEL_SEL1: needs desc
	// Position of DBIAS_CHANNEL4_SEL field.
	PVT_DBIAS_CHANNEL_SEL1_DBIAS_CHANNEL4_SEL_Pos = 0x19
	// Bit mask of DBIAS_CHANNEL4_SEL field.
	PVT_DBIAS_CHANNEL_SEL1_DBIAS_CHANNEL4_SEL_Msk = 0xfe000000

	// DBIAS_CHANNEL0_SEL: needs desc
	// Position of DBIAS_CHANNEL0_CFG field.
	PVT_DBIAS_CHANNEL0_SEL_DBIAS_CHANNEL0_CFG_Pos = 0x0
	// Bit mask of DBIAS_CHANNEL0_CFG field.
	PVT_DBIAS_CHANNEL0_SEL_DBIAS_CHANNEL0_CFG_Msk = 0x1ffff

	// DBIAS_CHANNEL1_SEL: needs desc
	// Position of DBIAS_CHANNEL1_CFG field.
	PVT_DBIAS_CHANNEL1_SEL_DBIAS_CHANNEL1_CFG_Pos = 0x0
	// Bit mask of DBIAS_CHANNEL1_CFG field.
	PVT_DBIAS_CHANNEL1_SEL_DBIAS_CHANNEL1_CFG_Msk = 0x1ffff

	// DBIAS_CHANNEL2_SEL: needs desc
	// Position of DBIAS_CHANNEL2_CFG field.
	PVT_DBIAS_CHANNEL2_SEL_DBIAS_CHANNEL2_CFG_Pos = 0x0
	// Bit mask of DBIAS_CHANNEL2_CFG field.
	PVT_DBIAS_CHANNEL2_SEL_DBIAS_CHANNEL2_CFG_Msk = 0x1ffff

	// DBIAS_CHANNEL3_SEL: needs desc
	// Position of DBIAS_CHANNEL3_CFG field.
	PVT_DBIAS_CHANNEL3_SEL_DBIAS_CHANNEL3_CFG_Pos = 0x0
	// Bit mask of DBIAS_CHANNEL3_CFG field.
	PVT_DBIAS_CHANNEL3_SEL_DBIAS_CHANNEL3_CFG_Msk = 0x1ffff

	// DBIAS_CHANNEL4_SEL: needs desc
	// Position of DBIAS_CHANNEL4_CFG field.
	PVT_DBIAS_CHANNEL4_SEL_DBIAS_CHANNEL4_CFG_Pos = 0x0
	// Bit mask of DBIAS_CHANNEL4_CFG field.
	PVT_DBIAS_CHANNEL4_SEL_DBIAS_CHANNEL4_CFG_Msk = 0x1ffff

	// DBIAS_CMD0: needs desc
	// Position of DBIAS_CMD0 field.
	PVT_DBIAS_CMD0_DBIAS_CMD0_Pos = 0x0
	// Bit mask of DBIAS_CMD0 field.
	PVT_DBIAS_CMD0_DBIAS_CMD0_Msk = 0x1ffff

	// DBIAS_CMD1: needs desc
	// Position of DBIAS_CMD1 field.
	PVT_DBIAS_CMD1_DBIAS_CMD1_Pos = 0x0
	// Bit mask of DBIAS_CMD1 field.
	PVT_DBIAS_CMD1_DBIAS_CMD1_Msk = 0x1ffff

	// DBIAS_CMD2: needs desc
	// Position of DBIAS_CMD2 field.
	PVT_DBIAS_CMD2_DBIAS_CMD2_Pos = 0x0
	// Bit mask of DBIAS_CMD2 field.
	PVT_DBIAS_CMD2_DBIAS_CMD2_Msk = 0x1ffff

	// DBIAS_CMD3: needs desc
	// Position of DBIAS_CMD3 field.
	PVT_DBIAS_CMD3_DBIAS_CMD3_Pos = 0x0
	// Bit mask of DBIAS_CMD3 field.
	PVT_DBIAS_CMD3_DBIAS_CMD3_Msk = 0x1ffff

	// DBIAS_CMD4: needs desc
	// Position of DBIAS_CMD4 field.
	PVT_DBIAS_CMD4_DBIAS_CMD4_Pos = 0x0
	// Bit mask of DBIAS_CMD4 field.
	PVT_DBIAS_CMD4_DBIAS_CMD4_Msk = 0x1ffff

	// DBIAS_TIMER: needs desc
	// Position of TIMER_TARGET field.
	PVT_DBIAS_TIMER_TIMER_TARGET_Pos = 0xf
	// Bit mask of TIMER_TARGET field.
	PVT_DBIAS_TIMER_TIMER_TARGET_Msk = 0x7fff8000
	// Position of TIMER_EN field.
	PVT_DBIAS_TIMER_TIMER_EN_Pos = 0x1f
	// Bit mask of TIMER_EN field.
	PVT_DBIAS_TIMER_TIMER_EN_Msk = 0x80000000
	// Bit TIMER_EN.
	PVT_DBIAS_TIMER_TIMER_EN = 0x80000000

	// COMB_PD_SITE0_UNIT0_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT0 = 0x80000000

	// COMB_PD_SITE0_UNIT1_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT1 = 0x80000000

	// COMB_PD_SITE0_UNIT2_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT2 = 0x80000000

	// COMB_PD_SITE0_UNIT3_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE0_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE0_UNIT3 = 0x80000000

	// COMB_PD_SITE0_UNIT0_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT0 = 0x80000000

	// COMB_PD_SITE0_UNIT1_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT1 = 0x80000000

	// COMB_PD_SITE0_UNIT2_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT2 = 0x80000000

	// COMB_PD_SITE0_UNIT3_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE0_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE0_UNIT3 = 0x80000000

	// COMB_PD_SITE0_UNIT0_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT0 = 0x80000000

	// COMB_PD_SITE0_UNIT1_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT1 = 0x80000000

	// COMB_PD_SITE0_UNIT2_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT2 = 0x80000000

	// COMB_PD_SITE0_UNIT3_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE0_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE0_UNIT3 = 0x80000000

	// COMB_PD_SITE1_UNIT0_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT0 = 0x80000000

	// COMB_PD_SITE1_UNIT1_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT1 = 0x80000000

	// COMB_PD_SITE1_UNIT2_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT2 = 0x80000000

	// COMB_PD_SITE1_UNIT3_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE1_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE1_UNIT3 = 0x80000000

	// COMB_PD_SITE1_UNIT0_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT0 = 0x80000000

	// COMB_PD_SITE1_UNIT1_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT1 = 0x80000000

	// COMB_PD_SITE1_UNIT2_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT2 = 0x80000000

	// COMB_PD_SITE1_UNIT3_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE1_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE1_UNIT3 = 0x80000000

	// COMB_PD_SITE1_UNIT0_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT0 = 0x80000000

	// COMB_PD_SITE1_UNIT1_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT1 = 0x80000000

	// COMB_PD_SITE1_UNIT2_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT2 = 0x80000000

	// COMB_PD_SITE1_UNIT3_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE1_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE1_UNIT3 = 0x80000000

	// COMB_PD_SITE2_UNIT0_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT0 = 0x80000000

	// COMB_PD_SITE2_UNIT1_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT1 = 0x80000000

	// COMB_PD_SITE2_UNIT2_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT2 = 0x80000000

	// COMB_PD_SITE2_UNIT3_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE2_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE2_UNIT3 = 0x80000000

	// COMB_PD_SITE2_UNIT0_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT0 = 0x80000000

	// COMB_PD_SITE2_UNIT1_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT1 = 0x80000000

	// COMB_PD_SITE2_UNIT2_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT2 = 0x80000000

	// COMB_PD_SITE2_UNIT3_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE2_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE2_UNIT3 = 0x80000000

	// COMB_PD_SITE2_UNIT0_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT0 = 0x80000000

	// COMB_PD_SITE2_UNIT1_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT1 = 0x80000000

	// COMB_PD_SITE2_UNIT2_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT2 = 0x80000000

	// COMB_PD_SITE2_UNIT3_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE2_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE2_UNIT3 = 0x80000000

	// COMB_PD_SITE3_UNIT0_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT0 = 0x80000000

	// COMB_PD_SITE3_UNIT1_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT1 = 0x80000000

	// COMB_PD_SITE3_UNIT2_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT2 = 0x80000000

	// COMB_PD_SITE3_UNIT3_VT0_CONF1: needs desc
	// Position of MONITOR_EN_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT0_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_MONITOR_EN_VT0_PD_SITE3_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT0_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_TIMING_ERR_VT0_PD_SITE3_UNIT3 = 0x80000000

	// COMB_PD_SITE3_UNIT0_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT0 = 0x80000000

	// COMB_PD_SITE3_UNIT1_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT1 = 0x80000000

	// COMB_PD_SITE3_UNIT2_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT2 = 0x80000000

	// COMB_PD_SITE3_UNIT3_VT1_CONF1: needs desc
	// Position of MONITOR_EN_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT1_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_MONITOR_EN_VT1_PD_SITE3_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT1_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_TIMING_ERR_VT1_PD_SITE3_UNIT3 = 0x80000000

	// COMB_PD_SITE3_UNIT0_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT0_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT0 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT0_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT0_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT0 = 0x80000000

	// COMB_PD_SITE3_UNIT1_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT1_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT1 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT1_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT1_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT1 = 0x80000000

	// COMB_PD_SITE3_UNIT2_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT2_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT2 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT2_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT2_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT2 = 0x80000000

	// COMB_PD_SITE3_UNIT3_VT2_CONF1: needs desc
	// Position of MONITOR_EN_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EN_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT3_Msk = 0x1
	// Bit MONITOR_EN_VT2_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_MONITOR_EN_VT2_PD_SITE3_UNIT3 = 0x1
	// Position of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_Pos = 0x1
	// Bit mask of TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_Msk = 0x2
	// Bit TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 = 0x2
	// Position of DELAY_LIMIT_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_Pos = 0x2
	// Bit mask of DELAY_LIMIT_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_Msk = 0x3fc
	// Position of DELAY_NUM_O_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_Pos = 0x17
	// Bit mask of DELAY_NUM_O_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_Msk = 0x7f800000
	// Position of TIMING_ERR_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT3_Pos = 0x1f
	// Bit mask of TIMING_ERR_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT3_Msk = 0x80000000
	// Bit TIMING_ERR_VT2_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_TIMING_ERR_VT2_PD_SITE3_UNIT3 = 0x80000000

	// COMB_PD_SITE0_UNIT0_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT1_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT2_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT3_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE0_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT0_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT1_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT2_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT3_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE0_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT0_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE0_UNIT0.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 field.
	PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT1_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE0_UNIT1.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 field.
	PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT2_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE0_UNIT2.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 field.
	PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE0_UNIT3_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE0_UNIT3.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE0_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 field.
	PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT0_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT1_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT2_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT3_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE1_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT0_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT1_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT2_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT3_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE1_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT0_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE1_UNIT0.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 field.
	PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT1_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE1_UNIT1.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 field.
	PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT2_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE1_UNIT2.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 field.
	PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE1_UNIT3_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE1_UNIT3.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE1_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 field.
	PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT0_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT1_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT2_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT3_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE2_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT0_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT1_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT2_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT3_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE2_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT0_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE2_UNIT0.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 field.
	PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT1_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE2_UNIT1.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 field.
	PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT2_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE2_UNIT2.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 field.
	PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE2_UNIT3_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE2_UNIT3.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE2_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 field.
	PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT0_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT1_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT2_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT3_VT0_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT0_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_DELAY_OVF_VT0_PD_SITE3_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT0_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT1_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT2_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT3_VT1_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT1_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_DELAY_OVF_VT1_PD_SITE3_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT0_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT0_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT0_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE3_UNIT0.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT0 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 field.
	PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT1_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT1_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT1_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE3_UNIT1.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT1 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 field.
	PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT2_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT2_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT2_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE3_UNIT2.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT2 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 field.
	PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_Msk = 0xffff0000

	// COMB_PD_SITE3_UNIT3_VT2_CONF2: needs desc
	// Position of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_Pos = 0x0
	// Bit mask of MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_Msk = 0x3
	// Position of DELAY_OVF_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT3_Pos = 0xf
	// Bit mask of DELAY_OVF_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT3_Msk = 0x8000
	// Bit DELAY_OVF_VT2_PD_SITE3_UNIT3.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_DELAY_OVF_VT2_PD_SITE3_UNIT3 = 0x8000
	// Position of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_Pos = 0x10
	// Bit mask of TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 field.
	PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_Msk = 0xffff0000

	// VALUE_UPDATE: needs field desc
	// Position of VALUE_UPDATE field.
	PVT_VALUE_UPDATE_VALUE_UPDATE_Pos = 0x0
	// Bit mask of VALUE_UPDATE field.
	PVT_VALUE_UPDATE_VALUE_UPDATE_Msk = 0x1
	// Bit VALUE_UPDATE.
	PVT_VALUE_UPDATE_VALUE_UPDATE = 0x1
	// Position of BYPASS field.
	PVT_VALUE_UPDATE_BYPASS_Pos = 0x1
	// Bit mask of BYPASS field.
	PVT_VALUE_UPDATE_BYPASS_Msk = 0x2
	// Bit BYPASS.
	PVT_VALUE_UPDATE_BYPASS = 0x2

	// DATE: version register
	// Position of DATE field.
	PVT_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	PVT_DATE_DATE_Msk = 0xffffffff
)

// Constants for RMT: Remote Control
const (
	// TX_CH0DATA: The read and write data register for CHANNEL%s by apb fifo access.
	// Position of CHDATA field.
	RMT_TX_CHDATA_CHDATA_Pos = 0x0
	// Bit mask of CHDATA field.
	RMT_TX_CHDATA_CHDATA_Msk = 0xffffffff

	// RX_CH0DATA: The read and write data register for CHANNEL$n by apb fifo access.
	// Position of CHDATA field.
	RMT_RX_CHDATA_CHDATA_Pos = 0x0
	// Bit mask of CHDATA field.
	RMT_RX_CHDATA_CHDATA_Msk = 0xffffffff

	// TX_CH0CONF0: Channel %s configure register 0
	// Position of TX_START_CH0 field.
	RMT_TX_CHCONF0_TX_START_CH0_Pos = 0x0
	// Bit mask of TX_START_CH0 field.
	RMT_TX_CHCONF0_TX_START_CH0_Msk = 0x1
	// Bit TX_START_CH0.
	RMT_TX_CHCONF0_TX_START_CH0 = 0x1
	// Position of MEM_RD_RST_CH0 field.
	RMT_TX_CHCONF0_MEM_RD_RST_CH0_Pos = 0x1
	// Bit mask of MEM_RD_RST_CH0 field.
	RMT_TX_CHCONF0_MEM_RD_RST_CH0_Msk = 0x2
	// Bit MEM_RD_RST_CH0.
	RMT_TX_CHCONF0_MEM_RD_RST_CH0 = 0x2
	// Position of APB_MEM_RST_CH0 field.
	RMT_TX_CHCONF0_APB_MEM_RST_CH0_Pos = 0x2
	// Bit mask of APB_MEM_RST_CH0 field.
	RMT_TX_CHCONF0_APB_MEM_RST_CH0_Msk = 0x4
	// Bit APB_MEM_RST_CH0.
	RMT_TX_CHCONF0_APB_MEM_RST_CH0 = 0x4
	// Position of TX_CONTI_MODE_CH0 field.
	RMT_TX_CHCONF0_TX_CONTI_MODE_CH0_Pos = 0x3
	// Bit mask of TX_CONTI_MODE_CH0 field.
	RMT_TX_CHCONF0_TX_CONTI_MODE_CH0_Msk = 0x8
	// Bit TX_CONTI_MODE_CH0.
	RMT_TX_CHCONF0_TX_CONTI_MODE_CH0 = 0x8
	// Position of MEM_TX_WRAP_EN_CH0 field.
	RMT_TX_CHCONF0_MEM_TX_WRAP_EN_CH0_Pos = 0x4
	// Bit mask of MEM_TX_WRAP_EN_CH0 field.
	RMT_TX_CHCONF0_MEM_TX_WRAP_EN_CH0_Msk = 0x10
	// Bit MEM_TX_WRAP_EN_CH0.
	RMT_TX_CHCONF0_MEM_TX_WRAP_EN_CH0 = 0x10
	// Position of IDLE_OUT_LV_CH0 field.
	RMT_TX_CHCONF0_IDLE_OUT_LV_CH0_Pos = 0x5
	// Bit mask of IDLE_OUT_LV_CH0 field.
	RMT_TX_CHCONF0_IDLE_OUT_LV_CH0_Msk = 0x20
	// Bit IDLE_OUT_LV_CH0.
	RMT_TX_CHCONF0_IDLE_OUT_LV_CH0 = 0x20
	// Position of IDLE_OUT_EN_CH0 field.
	RMT_TX_CHCONF0_IDLE_OUT_EN_CH0_Pos = 0x6
	// Bit mask of IDLE_OUT_EN_CH0 field.
	RMT_TX_CHCONF0_IDLE_OUT_EN_CH0_Msk = 0x40
	// Bit IDLE_OUT_EN_CH0.
	RMT_TX_CHCONF0_IDLE_OUT_EN_CH0 = 0x40
	// Position of TX_STOP_CH0 field.
	RMT_TX_CHCONF0_TX_STOP_CH0_Pos = 0x7
	// Bit mask of TX_STOP_CH0 field.
	RMT_TX_CHCONF0_TX_STOP_CH0_Msk = 0x80
	// Bit TX_STOP_CH0.
	RMT_TX_CHCONF0_TX_STOP_CH0 = 0x80
	// Position of DIV_CNT_CH0 field.
	RMT_TX_CHCONF0_DIV_CNT_CH0_Pos = 0x8
	// Bit mask of DIV_CNT_CH0 field.
	RMT_TX_CHCONF0_DIV_CNT_CH0_Msk = 0xff00
	// Position of MEM_SIZE_CH0 field.
	RMT_TX_CHCONF0_MEM_SIZE_CH0_Pos = 0x10
	// Bit mask of MEM_SIZE_CH0 field.
	RMT_TX_CHCONF0_MEM_SIZE_CH0_Msk = 0xf0000
	// Position of CARRIER_EFF_EN_CH0 field.
	RMT_TX_CHCONF0_CARRIER_EFF_EN_CH0_Pos = 0x14
	// Bit mask of CARRIER_EFF_EN_CH0 field.
	RMT_TX_CHCONF0_CARRIER_EFF_EN_CH0_Msk = 0x100000
	// Bit CARRIER_EFF_EN_CH0.
	RMT_TX_CHCONF0_CARRIER_EFF_EN_CH0 = 0x100000
	// Position of CARRIER_EN_CH0 field.
	RMT_TX_CHCONF0_CARRIER_EN_CH0_Pos = 0x15
	// Bit mask of CARRIER_EN_CH0 field.
	RMT_TX_CHCONF0_CARRIER_EN_CH0_Msk = 0x200000
	// Bit CARRIER_EN_CH0.
	RMT_TX_CHCONF0_CARRIER_EN_CH0 = 0x200000
	// Position of CARRIER_OUT_LV_CH0 field.
	RMT_TX_CHCONF0_CARRIER_OUT_LV_CH0_Pos = 0x16
	// Bit mask of CARRIER_OUT_LV_CH0 field.
	RMT_TX_CHCONF0_CARRIER_OUT_LV_CH0_Msk = 0x400000
	// Bit CARRIER_OUT_LV_CH0.
	RMT_TX_CHCONF0_CARRIER_OUT_LV_CH0 = 0x400000
	// Position of AFIFO_RST_CH0 field.
	RMT_TX_CHCONF0_AFIFO_RST_CH0_Pos = 0x17
	// Bit mask of AFIFO_RST_CH0 field.
	RMT_TX_CHCONF0_AFIFO_RST_CH0_Msk = 0x800000
	// Bit AFIFO_RST_CH0.
	RMT_TX_CHCONF0_AFIFO_RST_CH0 = 0x800000
	// Position of CONF_UPDATE_CH0 field.
	RMT_TX_CHCONF0_CONF_UPDATE_CH0_Pos = 0x18
	// Bit mask of CONF_UPDATE_CH0 field.
	RMT_TX_CHCONF0_CONF_UPDATE_CH0_Msk = 0x1000000
	// Bit CONF_UPDATE_CH0.
	RMT_TX_CHCONF0_CONF_UPDATE_CH0 = 0x1000000

	// RX_CH0CONF0: Channel %s configure register 0
	// Position of DIV_CNT_CH4 field.
	RMT_RX_CHCONF0_DIV_CNT_CH4_Pos = 0x0
	// Bit mask of DIV_CNT_CH4 field.
	RMT_RX_CHCONF0_DIV_CNT_CH4_Msk = 0xff
	// Position of IDLE_THRES_CH4 field.
	RMT_RX_CHCONF0_IDLE_THRES_CH4_Pos = 0x8
	// Bit mask of IDLE_THRES_CH4 field.
	RMT_RX_CHCONF0_IDLE_THRES_CH4_Msk = 0x7fff00
	// Position of MEM_SIZE_CH4 field.
	RMT_RX_CHCONF0_MEM_SIZE_CH4_Pos = 0x18
	// Bit mask of MEM_SIZE_CH4 field.
	RMT_RX_CHCONF0_MEM_SIZE_CH4_Msk = 0xf000000
	// Position of CARRIER_EN_CH4 field.
	RMT_RX_CHCONF0_CARRIER_EN_CH4_Pos = 0x1c
	// Bit mask of CARRIER_EN_CH4 field.
	RMT_RX_CHCONF0_CARRIER_EN_CH4_Msk = 0x10000000
	// Bit CARRIER_EN_CH4.
	RMT_RX_CHCONF0_CARRIER_EN_CH4 = 0x10000000
	// Position of CARRIER_OUT_LV_CH4 field.
	RMT_RX_CHCONF0_CARRIER_OUT_LV_CH4_Pos = 0x1d
	// Bit mask of CARRIER_OUT_LV_CH4 field.
	RMT_RX_CHCONF0_CARRIER_OUT_LV_CH4_Msk = 0x20000000
	// Bit CARRIER_OUT_LV_CH4.
	RMT_RX_CHCONF0_CARRIER_OUT_LV_CH4 = 0x20000000

	// RX_CH0CONF1: Channel %s configure register 1
	// Position of RX_EN_CH4 field.
	RMT_RX_CHCONF1_RX_EN_CH4_Pos = 0x0
	// Bit mask of RX_EN_CH4 field.
	RMT_RX_CHCONF1_RX_EN_CH4_Msk = 0x1
	// Bit RX_EN_CH4.
	RMT_RX_CHCONF1_RX_EN_CH4 = 0x1
	// Position of MEM_WR_RST_CH4 field.
	RMT_RX_CHCONF1_MEM_WR_RST_CH4_Pos = 0x1
	// Bit mask of MEM_WR_RST_CH4 field.
	RMT_RX_CHCONF1_MEM_WR_RST_CH4_Msk = 0x2
	// Bit MEM_WR_RST_CH4.
	RMT_RX_CHCONF1_MEM_WR_RST_CH4 = 0x2
	// Position of APB_MEM_RST_CH4 field.
	RMT_RX_CHCONF1_APB_MEM_RST_CH4_Pos = 0x2
	// Bit mask of APB_MEM_RST_CH4 field.
	RMT_RX_CHCONF1_APB_MEM_RST_CH4_Msk = 0x4
	// Bit APB_MEM_RST_CH4.
	RMT_RX_CHCONF1_APB_MEM_RST_CH4 = 0x4
	// Position of MEM_OWNER_CH4 field.
	RMT_RX_CHCONF1_MEM_OWNER_CH4_Pos = 0x3
	// Bit mask of MEM_OWNER_CH4 field.
	RMT_RX_CHCONF1_MEM_OWNER_CH4_Msk = 0x8
	// Bit MEM_OWNER_CH4.
	RMT_RX_CHCONF1_MEM_OWNER_CH4 = 0x8
	// Position of RX_FILTER_EN_CH4 field.
	RMT_RX_CHCONF1_RX_FILTER_EN_CH4_Pos = 0x4
	// Bit mask of RX_FILTER_EN_CH4 field.
	RMT_RX_CHCONF1_RX_FILTER_EN_CH4_Msk = 0x10
	// Bit RX_FILTER_EN_CH4.
	RMT_RX_CHCONF1_RX_FILTER_EN_CH4 = 0x10
	// Position of RX_FILTER_THRES_CH4 field.
	RMT_RX_CHCONF1_RX_FILTER_THRES_CH4_Pos = 0x5
	// Bit mask of RX_FILTER_THRES_CH4 field.
	RMT_RX_CHCONF1_RX_FILTER_THRES_CH4_Msk = 0x1fe0
	// Position of MEM_RX_WRAP_EN_CH4 field.
	RMT_RX_CHCONF1_MEM_RX_WRAP_EN_CH4_Pos = 0xd
	// Bit mask of MEM_RX_WRAP_EN_CH4 field.
	RMT_RX_CHCONF1_MEM_RX_WRAP_EN_CH4_Msk = 0x2000
	// Bit MEM_RX_WRAP_EN_CH4.
	RMT_RX_CHCONF1_MEM_RX_WRAP_EN_CH4 = 0x2000
	// Position of AFIFO_RST_CH4 field.
	RMT_RX_CHCONF1_AFIFO_RST_CH4_Pos = 0xe
	// Bit mask of AFIFO_RST_CH4 field.
	RMT_RX_CHCONF1_AFIFO_RST_CH4_Msk = 0x4000
	// Bit AFIFO_RST_CH4.
	RMT_RX_CHCONF1_AFIFO_RST_CH4 = 0x4000
	// Position of CONF_UPDATE_CH4 field.
	RMT_RX_CHCONF1_CONF_UPDATE_CH4_Pos = 0xf
	// Bit mask of CONF_UPDATE_CH4 field.
	RMT_RX_CHCONF1_CONF_UPDATE_CH4_Msk = 0x8000
	// Bit CONF_UPDATE_CH4.
	RMT_RX_CHCONF1_CONF_UPDATE_CH4 = 0x8000

	// TX_CH0STATUS: Channel %s status register
	// Position of MEM_RADDR_EX_CH0 field.
	RMT_TX_CHSTATUS_MEM_RADDR_EX_CH0_Pos = 0x0
	// Bit mask of MEM_RADDR_EX_CH0 field.
	RMT_TX_CHSTATUS_MEM_RADDR_EX_CH0_Msk = 0x3ff
	// Position of APB_MEM_WADDR_CH0 field.
	RMT_TX_CHSTATUS_APB_MEM_WADDR_CH0_Pos = 0xb
	// Bit mask of APB_MEM_WADDR_CH0 field.
	RMT_TX_CHSTATUS_APB_MEM_WADDR_CH0_Msk = 0x1ff800
	// Position of STATE_CH0 field.
	RMT_TX_CHSTATUS_STATE_CH0_Pos = 0x16
	// Bit mask of STATE_CH0 field.
	RMT_TX_CHSTATUS_STATE_CH0_Msk = 0x1c00000
	// Position of MEM_EMPTY_CH0 field.
	RMT_TX_CHSTATUS_MEM_EMPTY_CH0_Pos = 0x19
	// Bit mask of MEM_EMPTY_CH0 field.
	RMT_TX_CHSTATUS_MEM_EMPTY_CH0_Msk = 0x2000000
	// Bit MEM_EMPTY_CH0.
	RMT_TX_CHSTATUS_MEM_EMPTY_CH0 = 0x2000000
	// Position of APB_MEM_WR_ERR_CH0 field.
	RMT_TX_CHSTATUS_APB_MEM_WR_ERR_CH0_Pos = 0x1a
	// Bit mask of APB_MEM_WR_ERR_CH0 field.
	RMT_TX_CHSTATUS_APB_MEM_WR_ERR_CH0_Msk = 0x4000000
	// Bit APB_MEM_WR_ERR_CH0.
	RMT_TX_CHSTATUS_APB_MEM_WR_ERR_CH0 = 0x4000000

	// RX_CH0STATUS: Channel %s status register
	// Position of MEM_WADDR_EX_CH4 field.
	RMT_RX_CHSTATUS_MEM_WADDR_EX_CH4_Pos = 0x0
	// Bit mask of MEM_WADDR_EX_CH4 field.
	RMT_RX_CHSTATUS_MEM_WADDR_EX_CH4_Msk = 0x3ff
	// Position of APB_MEM_RADDR_CH4 field.
	RMT_RX_CHSTATUS_APB_MEM_RADDR_CH4_Pos = 0xb
	// Bit mask of APB_MEM_RADDR_CH4 field.
	RMT_RX_CHSTATUS_APB_MEM_RADDR_CH4_Msk = 0x1ff800
	// Position of STATE_CH4 field.
	RMT_RX_CHSTATUS_STATE_CH4_Pos = 0x16
	// Bit mask of STATE_CH4 field.
	RMT_RX_CHSTATUS_STATE_CH4_Msk = 0x1c00000
	// Position of MEM_OWNER_ERR_CH4 field.
	RMT_RX_CHSTATUS_MEM_OWNER_ERR_CH4_Pos = 0x19
	// Bit mask of MEM_OWNER_ERR_CH4 field.
	RMT_RX_CHSTATUS_MEM_OWNER_ERR_CH4_Msk = 0x2000000
	// Bit MEM_OWNER_ERR_CH4.
	RMT_RX_CHSTATUS_MEM_OWNER_ERR_CH4 = 0x2000000
	// Position of MEM_FULL_CH4 field.
	RMT_RX_CHSTATUS_MEM_FULL_CH4_Pos = 0x1a
	// Bit mask of MEM_FULL_CH4 field.
	RMT_RX_CHSTATUS_MEM_FULL_CH4_Msk = 0x4000000
	// Bit MEM_FULL_CH4.
	RMT_RX_CHSTATUS_MEM_FULL_CH4 = 0x4000000
	// Position of APB_MEM_RD_ERR_CH4 field.
	RMT_RX_CHSTATUS_APB_MEM_RD_ERR_CH4_Pos = 0x1b
	// Bit mask of APB_MEM_RD_ERR_CH4 field.
	RMT_RX_CHSTATUS_APB_MEM_RD_ERR_CH4_Msk = 0x8000000
	// Bit APB_MEM_RD_ERR_CH4.
	RMT_RX_CHSTATUS_APB_MEM_RD_ERR_CH4 = 0x8000000

	// INT_RAW: Raw interrupt status
	// Position of CH0_TX_END_INT_RAW field.
	RMT_INT_RAW_CH0_TX_END_INT_RAW_Pos = 0x0
	// Bit mask of CH0_TX_END_INT_RAW field.
	RMT_INT_RAW_CH0_TX_END_INT_RAW_Msk = 0x1
	// Bit CH0_TX_END_INT_RAW.
	RMT_INT_RAW_CH0_TX_END_INT_RAW = 0x1
	// Position of CH1_TX_END_INT_RAW field.
	RMT_INT_RAW_CH1_TX_END_INT_RAW_Pos = 0x1
	// Bit mask of CH1_TX_END_INT_RAW field.
	RMT_INT_RAW_CH1_TX_END_INT_RAW_Msk = 0x2
	// Bit CH1_TX_END_INT_RAW.
	RMT_INT_RAW_CH1_TX_END_INT_RAW = 0x2
	// Position of CH2_TX_END_INT_RAW field.
	RMT_INT_RAW_CH2_TX_END_INT_RAW_Pos = 0x2
	// Bit mask of CH2_TX_END_INT_RAW field.
	RMT_INT_RAW_CH2_TX_END_INT_RAW_Msk = 0x4
	// Bit CH2_TX_END_INT_RAW.
	RMT_INT_RAW_CH2_TX_END_INT_RAW = 0x4
	// Position of CH3_TX_END_INT_RAW field.
	RMT_INT_RAW_CH3_TX_END_INT_RAW_Pos = 0x3
	// Bit mask of CH3_TX_END_INT_RAW field.
	RMT_INT_RAW_CH3_TX_END_INT_RAW_Msk = 0x8
	// Bit CH3_TX_END_INT_RAW.
	RMT_INT_RAW_CH3_TX_END_INT_RAW = 0x8
	// Position of TX_CH0_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH0_ERR_INT_RAW_Pos = 0x4
	// Bit mask of TX_CH0_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH0_ERR_INT_RAW_Msk = 0x10
	// Bit TX_CH0_ERR_INT_RAW.
	RMT_INT_RAW_TX_CH0_ERR_INT_RAW = 0x10
	// Position of TX_CH1_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH1_ERR_INT_RAW_Pos = 0x5
	// Bit mask of TX_CH1_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH1_ERR_INT_RAW_Msk = 0x20
	// Bit TX_CH1_ERR_INT_RAW.
	RMT_INT_RAW_TX_CH1_ERR_INT_RAW = 0x20
	// Position of TX_CH2_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH2_ERR_INT_RAW_Pos = 0x6
	// Bit mask of TX_CH2_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH2_ERR_INT_RAW_Msk = 0x40
	// Bit TX_CH2_ERR_INT_RAW.
	RMT_INT_RAW_TX_CH2_ERR_INT_RAW = 0x40
	// Position of TX_CH3_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH3_ERR_INT_RAW_Pos = 0x7
	// Bit mask of TX_CH3_ERR_INT_RAW field.
	RMT_INT_RAW_TX_CH3_ERR_INT_RAW_Msk = 0x80
	// Bit TX_CH3_ERR_INT_RAW.
	RMT_INT_RAW_TX_CH3_ERR_INT_RAW = 0x80
	// Position of CH0_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH0_TX_THR_EVENT_INT_RAW_Pos = 0x8
	// Bit mask of CH0_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH0_TX_THR_EVENT_INT_RAW_Msk = 0x100
	// Bit CH0_TX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH0_TX_THR_EVENT_INT_RAW = 0x100
	// Position of CH1_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH1_TX_THR_EVENT_INT_RAW_Pos = 0x9
	// Bit mask of CH1_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH1_TX_THR_EVENT_INT_RAW_Msk = 0x200
	// Bit CH1_TX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH1_TX_THR_EVENT_INT_RAW = 0x200
	// Position of CH2_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH2_TX_THR_EVENT_INT_RAW_Pos = 0xa
	// Bit mask of CH2_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH2_TX_THR_EVENT_INT_RAW_Msk = 0x400
	// Bit CH2_TX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH2_TX_THR_EVENT_INT_RAW = 0x400
	// Position of CH3_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH3_TX_THR_EVENT_INT_RAW_Pos = 0xb
	// Bit mask of CH3_TX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH3_TX_THR_EVENT_INT_RAW_Msk = 0x800
	// Bit CH3_TX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH3_TX_THR_EVENT_INT_RAW = 0x800
	// Position of CH0_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH0_TX_LOOP_INT_RAW_Pos = 0xc
	// Bit mask of CH0_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH0_TX_LOOP_INT_RAW_Msk = 0x1000
	// Bit CH0_TX_LOOP_INT_RAW.
	RMT_INT_RAW_CH0_TX_LOOP_INT_RAW = 0x1000
	// Position of CH1_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH1_TX_LOOP_INT_RAW_Pos = 0xd
	// Bit mask of CH1_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH1_TX_LOOP_INT_RAW_Msk = 0x2000
	// Bit CH1_TX_LOOP_INT_RAW.
	RMT_INT_RAW_CH1_TX_LOOP_INT_RAW = 0x2000
	// Position of CH2_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH2_TX_LOOP_INT_RAW_Pos = 0xe
	// Bit mask of CH2_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH2_TX_LOOP_INT_RAW_Msk = 0x4000
	// Bit CH2_TX_LOOP_INT_RAW.
	RMT_INT_RAW_CH2_TX_LOOP_INT_RAW = 0x4000
	// Position of CH3_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH3_TX_LOOP_INT_RAW_Pos = 0xf
	// Bit mask of CH3_TX_LOOP_INT_RAW field.
	RMT_INT_RAW_CH3_TX_LOOP_INT_RAW_Msk = 0x8000
	// Bit CH3_TX_LOOP_INT_RAW.
	RMT_INT_RAW_CH3_TX_LOOP_INT_RAW = 0x8000
	// Position of CH4_RX_END_INT_RAW field.
	RMT_INT_RAW_CH4_RX_END_INT_RAW_Pos = 0x10
	// Bit mask of CH4_RX_END_INT_RAW field.
	RMT_INT_RAW_CH4_RX_END_INT_RAW_Msk = 0x10000
	// Bit CH4_RX_END_INT_RAW.
	RMT_INT_RAW_CH4_RX_END_INT_RAW = 0x10000
	// Position of CH5_RX_END_INT_RAW field.
	RMT_INT_RAW_CH5_RX_END_INT_RAW_Pos = 0x11
	// Bit mask of CH5_RX_END_INT_RAW field.
	RMT_INT_RAW_CH5_RX_END_INT_RAW_Msk = 0x20000
	// Bit CH5_RX_END_INT_RAW.
	RMT_INT_RAW_CH5_RX_END_INT_RAW = 0x20000
	// Position of CH6_RX_END_INT_RAW field.
	RMT_INT_RAW_CH6_RX_END_INT_RAW_Pos = 0x12
	// Bit mask of CH6_RX_END_INT_RAW field.
	RMT_INT_RAW_CH6_RX_END_INT_RAW_Msk = 0x40000
	// Bit CH6_RX_END_INT_RAW.
	RMT_INT_RAW_CH6_RX_END_INT_RAW = 0x40000
	// Position of CH7_RX_END_INT_RAW field.
	RMT_INT_RAW_CH7_RX_END_INT_RAW_Pos = 0x13
	// Bit mask of CH7_RX_END_INT_RAW field.
	RMT_INT_RAW_CH7_RX_END_INT_RAW_Msk = 0x80000
	// Bit CH7_RX_END_INT_RAW.
	RMT_INT_RAW_CH7_RX_END_INT_RAW = 0x80000
	// Position of RX_CH4_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH4_ERR_INT_RAW_Pos = 0x14
	// Bit mask of RX_CH4_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH4_ERR_INT_RAW_Msk = 0x100000
	// Bit RX_CH4_ERR_INT_RAW.
	RMT_INT_RAW_RX_CH4_ERR_INT_RAW = 0x100000
	// Position of RX_CH5_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH5_ERR_INT_RAW_Pos = 0x15
	// Bit mask of RX_CH5_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH5_ERR_INT_RAW_Msk = 0x200000
	// Bit RX_CH5_ERR_INT_RAW.
	RMT_INT_RAW_RX_CH5_ERR_INT_RAW = 0x200000
	// Position of RX_CH6_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH6_ERR_INT_RAW_Pos = 0x16
	// Bit mask of RX_CH6_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH6_ERR_INT_RAW_Msk = 0x400000
	// Bit RX_CH6_ERR_INT_RAW.
	RMT_INT_RAW_RX_CH6_ERR_INT_RAW = 0x400000
	// Position of RX_CH7_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH7_ERR_INT_RAW_Pos = 0x17
	// Bit mask of RX_CH7_ERR_INT_RAW field.
	RMT_INT_RAW_RX_CH7_ERR_INT_RAW_Msk = 0x800000
	// Bit RX_CH7_ERR_INT_RAW.
	RMT_INT_RAW_RX_CH7_ERR_INT_RAW = 0x800000
	// Position of CH4_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH4_RX_THR_EVENT_INT_RAW_Pos = 0x18
	// Bit mask of CH4_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH4_RX_THR_EVENT_INT_RAW_Msk = 0x1000000
	// Bit CH4_RX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH4_RX_THR_EVENT_INT_RAW = 0x1000000
	// Position of CH5_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH5_RX_THR_EVENT_INT_RAW_Pos = 0x19
	// Bit mask of CH5_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH5_RX_THR_EVENT_INT_RAW_Msk = 0x2000000
	// Bit CH5_RX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH5_RX_THR_EVENT_INT_RAW = 0x2000000
	// Position of CH6_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH6_RX_THR_EVENT_INT_RAW_Pos = 0x1a
	// Bit mask of CH6_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH6_RX_THR_EVENT_INT_RAW_Msk = 0x4000000
	// Bit CH6_RX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH6_RX_THR_EVENT_INT_RAW = 0x4000000
	// Position of CH7_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH7_RX_THR_EVENT_INT_RAW_Pos = 0x1b
	// Bit mask of CH7_RX_THR_EVENT_INT_RAW field.
	RMT_INT_RAW_CH7_RX_THR_EVENT_INT_RAW_Msk = 0x8000000
	// Bit CH7_RX_THR_EVENT_INT_RAW.
	RMT_INT_RAW_CH7_RX_THR_EVENT_INT_RAW = 0x8000000
	// Position of TX_CH3_DMA_ACCESS_FAIL_INT_RAW field.
	RMT_INT_RAW_TX_CH3_DMA_ACCESS_FAIL_INT_RAW_Pos = 0x1c
	// Bit mask of TX_CH3_DMA_ACCESS_FAIL_INT_RAW field.
	RMT_INT_RAW_TX_CH3_DMA_ACCESS_FAIL_INT_RAW_Msk = 0x10000000
	// Bit TX_CH3_DMA_ACCESS_FAIL_INT_RAW.
	RMT_INT_RAW_TX_CH3_DMA_ACCESS_FAIL_INT_RAW = 0x10000000
	// Position of RX_CH7_DMA_ACCESS_FAIL_INT_RAW field.
	RMT_INT_RAW_RX_CH7_DMA_ACCESS_FAIL_INT_RAW_Pos = 0x1d
	// Bit mask of RX_CH7_DMA_ACCESS_FAIL_INT_RAW field.
	RMT_INT_RAW_RX_CH7_DMA_ACCESS_FAIL_INT_RAW_Msk = 0x20000000
	// Bit RX_CH7_DMA_ACCESS_FAIL_INT_RAW.
	RMT_INT_RAW_RX_CH7_DMA_ACCESS_FAIL_INT_RAW = 0x20000000

	// INT_ST: Masked interrupt status
	// Position of CH0_TX_END_INT_ST field.
	RMT_INT_ST_CH0_TX_END_INT_ST_Pos = 0x0
	// Bit mask of CH0_TX_END_INT_ST field.
	RMT_INT_ST_CH0_TX_END_INT_ST_Msk = 0x1
	// Bit CH0_TX_END_INT_ST.
	RMT_INT_ST_CH0_TX_END_INT_ST = 0x1
	// Position of CH1_TX_END_INT_ST field.
	RMT_INT_ST_CH1_TX_END_INT_ST_Pos = 0x1
	// Bit mask of CH1_TX_END_INT_ST field.
	RMT_INT_ST_CH1_TX_END_INT_ST_Msk = 0x2
	// Bit CH1_TX_END_INT_ST.
	RMT_INT_ST_CH1_TX_END_INT_ST = 0x2
	// Position of CH2_TX_END_INT_ST field.
	RMT_INT_ST_CH2_TX_END_INT_ST_Pos = 0x2
	// Bit mask of CH2_TX_END_INT_ST field.
	RMT_INT_ST_CH2_TX_END_INT_ST_Msk = 0x4
	// Bit CH2_TX_END_INT_ST.
	RMT_INT_ST_CH2_TX_END_INT_ST = 0x4
	// Position of CH3_TX_END_INT_ST field.
	RMT_INT_ST_CH3_TX_END_INT_ST_Pos = 0x3
	// Bit mask of CH3_TX_END_INT_ST field.
	RMT_INT_ST_CH3_TX_END_INT_ST_Msk = 0x8
	// Bit CH3_TX_END_INT_ST.
	RMT_INT_ST_CH3_TX_END_INT_ST = 0x8
	// Position of TX_CH0_ERR_INT_ST field.
	RMT_INT_ST_TX_CH0_ERR_INT_ST_Pos = 0x4
	// Bit mask of TX_CH0_ERR_INT_ST field.
	RMT_INT_ST_TX_CH0_ERR_INT_ST_Msk = 0x10
	// Bit TX_CH0_ERR_INT_ST.
	RMT_INT_ST_TX_CH0_ERR_INT_ST = 0x10
	// Position of TX_CH1_ERR_INT_ST field.
	RMT_INT_ST_TX_CH1_ERR_INT_ST_Pos = 0x5
	// Bit mask of TX_CH1_ERR_INT_ST field.
	RMT_INT_ST_TX_CH1_ERR_INT_ST_Msk = 0x20
	// Bit TX_CH1_ERR_INT_ST.
	RMT_INT_ST_TX_CH1_ERR_INT_ST = 0x20
	// Position of TX_CH2_ERR_INT_ST field.
	RMT_INT_ST_TX_CH2_ERR_INT_ST_Pos = 0x6
	// Bit mask of TX_CH2_ERR_INT_ST field.
	RMT_INT_ST_TX_CH2_ERR_INT_ST_Msk = 0x40
	// Bit TX_CH2_ERR_INT_ST.
	RMT_INT_ST_TX_CH2_ERR_INT_ST = 0x40
	// Position of TX_CH3_ERR_INT_ST field.
	RMT_INT_ST_TX_CH3_ERR_INT_ST_Pos = 0x7
	// Bit mask of TX_CH3_ERR_INT_ST field.
	RMT_INT_ST_TX_CH3_ERR_INT_ST_Msk = 0x80
	// Bit TX_CH3_ERR_INT_ST.
	RMT_INT_ST_TX_CH3_ERR_INT_ST = 0x80
	// Position of CH0_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH0_TX_THR_EVENT_INT_ST_Pos = 0x8
	// Bit mask of CH0_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH0_TX_THR_EVENT_INT_ST_Msk = 0x100
	// Bit CH0_TX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH0_TX_THR_EVENT_INT_ST = 0x100
	// Position of CH1_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH1_TX_THR_EVENT_INT_ST_Pos = 0x9
	// Bit mask of CH1_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH1_TX_THR_EVENT_INT_ST_Msk = 0x200
	// Bit CH1_TX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH1_TX_THR_EVENT_INT_ST = 0x200
	// Position of CH2_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH2_TX_THR_EVENT_INT_ST_Pos = 0xa
	// Bit mask of CH2_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH2_TX_THR_EVENT_INT_ST_Msk = 0x400
	// Bit CH2_TX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH2_TX_THR_EVENT_INT_ST = 0x400
	// Position of CH3_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH3_TX_THR_EVENT_INT_ST_Pos = 0xb
	// Bit mask of CH3_TX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH3_TX_THR_EVENT_INT_ST_Msk = 0x800
	// Bit CH3_TX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH3_TX_THR_EVENT_INT_ST = 0x800
	// Position of CH0_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH0_TX_LOOP_INT_ST_Pos = 0xc
	// Bit mask of CH0_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH0_TX_LOOP_INT_ST_Msk = 0x1000
	// Bit CH0_TX_LOOP_INT_ST.
	RMT_INT_ST_CH0_TX_LOOP_INT_ST = 0x1000
	// Position of CH1_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH1_TX_LOOP_INT_ST_Pos = 0xd
	// Bit mask of CH1_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH1_TX_LOOP_INT_ST_Msk = 0x2000
	// Bit CH1_TX_LOOP_INT_ST.
	RMT_INT_ST_CH1_TX_LOOP_INT_ST = 0x2000
	// Position of CH2_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH2_TX_LOOP_INT_ST_Pos = 0xe
	// Bit mask of CH2_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH2_TX_LOOP_INT_ST_Msk = 0x4000
	// Bit CH2_TX_LOOP_INT_ST.
	RMT_INT_ST_CH2_TX_LOOP_INT_ST = 0x4000
	// Position of CH3_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH3_TX_LOOP_INT_ST_Pos = 0xf
	// Bit mask of CH3_TX_LOOP_INT_ST field.
	RMT_INT_ST_CH3_TX_LOOP_INT_ST_Msk = 0x8000
	// Bit CH3_TX_LOOP_INT_ST.
	RMT_INT_ST_CH3_TX_LOOP_INT_ST = 0x8000
	// Position of CH4_RX_END_INT_ST field.
	RMT_INT_ST_CH4_RX_END_INT_ST_Pos = 0x10
	// Bit mask of CH4_RX_END_INT_ST field.
	RMT_INT_ST_CH4_RX_END_INT_ST_Msk = 0x10000
	// Bit CH4_RX_END_INT_ST.
	RMT_INT_ST_CH4_RX_END_INT_ST = 0x10000
	// Position of CH5_RX_END_INT_ST field.
	RMT_INT_ST_CH5_RX_END_INT_ST_Pos = 0x11
	// Bit mask of CH5_RX_END_INT_ST field.
	RMT_INT_ST_CH5_RX_END_INT_ST_Msk = 0x20000
	// Bit CH5_RX_END_INT_ST.
	RMT_INT_ST_CH5_RX_END_INT_ST = 0x20000
	// Position of CH6_RX_END_INT_ST field.
	RMT_INT_ST_CH6_RX_END_INT_ST_Pos = 0x12
	// Bit mask of CH6_RX_END_INT_ST field.
	RMT_INT_ST_CH6_RX_END_INT_ST_Msk = 0x40000
	// Bit CH6_RX_END_INT_ST.
	RMT_INT_ST_CH6_RX_END_INT_ST = 0x40000
	// Position of CH7_RX_END_INT_ST field.
	RMT_INT_ST_CH7_RX_END_INT_ST_Pos = 0x13
	// Bit mask of CH7_RX_END_INT_ST field.
	RMT_INT_ST_CH7_RX_END_INT_ST_Msk = 0x80000
	// Bit CH7_RX_END_INT_ST.
	RMT_INT_ST_CH7_RX_END_INT_ST = 0x80000
	// Position of RX_CH4_ERR_INT_ST field.
	RMT_INT_ST_RX_CH4_ERR_INT_ST_Pos = 0x14
	// Bit mask of RX_CH4_ERR_INT_ST field.
	RMT_INT_ST_RX_CH4_ERR_INT_ST_Msk = 0x100000
	// Bit RX_CH4_ERR_INT_ST.
	RMT_INT_ST_RX_CH4_ERR_INT_ST = 0x100000
	// Position of RX_CH5_ERR_INT_ST field.
	RMT_INT_ST_RX_CH5_ERR_INT_ST_Pos = 0x15
	// Bit mask of RX_CH5_ERR_INT_ST field.
	RMT_INT_ST_RX_CH5_ERR_INT_ST_Msk = 0x200000
	// Bit RX_CH5_ERR_INT_ST.
	RMT_INT_ST_RX_CH5_ERR_INT_ST = 0x200000
	// Position of RX_CH6_ERR_INT_ST field.
	RMT_INT_ST_RX_CH6_ERR_INT_ST_Pos = 0x16
	// Bit mask of RX_CH6_ERR_INT_ST field.
	RMT_INT_ST_RX_CH6_ERR_INT_ST_Msk = 0x400000
	// Bit RX_CH6_ERR_INT_ST.
	RMT_INT_ST_RX_CH6_ERR_INT_ST = 0x400000
	// Position of RX_CH7_ERR_INT_ST field.
	RMT_INT_ST_RX_CH7_ERR_INT_ST_Pos = 0x17
	// Bit mask of RX_CH7_ERR_INT_ST field.
	RMT_INT_ST_RX_CH7_ERR_INT_ST_Msk = 0x800000
	// Bit RX_CH7_ERR_INT_ST.
	RMT_INT_ST_RX_CH7_ERR_INT_ST = 0x800000
	// Position of CH4_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH4_RX_THR_EVENT_INT_ST_Pos = 0x18
	// Bit mask of CH4_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH4_RX_THR_EVENT_INT_ST_Msk = 0x1000000
	// Bit CH4_RX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH4_RX_THR_EVENT_INT_ST = 0x1000000
	// Position of CH5_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH5_RX_THR_EVENT_INT_ST_Pos = 0x19
	// Bit mask of CH5_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH5_RX_THR_EVENT_INT_ST_Msk = 0x2000000
	// Bit CH5_RX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH5_RX_THR_EVENT_INT_ST = 0x2000000
	// Position of CH6_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH6_RX_THR_EVENT_INT_ST_Pos = 0x1a
	// Bit mask of CH6_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH6_RX_THR_EVENT_INT_ST_Msk = 0x4000000
	// Bit CH6_RX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH6_RX_THR_EVENT_INT_ST = 0x4000000
	// Position of CH7_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH7_RX_THR_EVENT_INT_ST_Pos = 0x1b
	// Bit mask of CH7_RX_THR_EVENT_INT_ST field.
	RMT_INT_ST_CH7_RX_THR_EVENT_INT_ST_Msk = 0x8000000
	// Bit CH7_RX_THR_EVENT_INT_ST.
	RMT_INT_ST_CH7_RX_THR_EVENT_INT_ST = 0x8000000
	// Position of TX_CH3_DMA_ACCESS_FAIL_INT_ST field.
	RMT_INT_ST_TX_CH3_DMA_ACCESS_FAIL_INT_ST_Pos = 0x1c
	// Bit mask of TX_CH3_DMA_ACCESS_FAIL_INT_ST field.
	RMT_INT_ST_TX_CH3_DMA_ACCESS_FAIL_INT_ST_Msk = 0x10000000
	// Bit TX_CH3_DMA_ACCESS_FAIL_INT_ST.
	RMT_INT_ST_TX_CH3_DMA_ACCESS_FAIL_INT_ST = 0x10000000
	// Position of RX_CH7_DMA_ACCESS_FAIL_INT_ST field.
	RMT_INT_ST_RX_CH7_DMA_ACCESS_FAIL_INT_ST_Pos = 0x1d
	// Bit mask of RX_CH7_DMA_ACCESS_FAIL_INT_ST field.
	RMT_INT_ST_RX_CH7_DMA_ACCESS_FAIL_INT_ST_Msk = 0x20000000
	// Bit RX_CH7_DMA_ACCESS_FAIL_INT_ST.
	RMT_INT_ST_RX_CH7_DMA_ACCESS_FAIL_INT_ST = 0x20000000

	// INT_ENA: Interrupt enable bits
	// Position of CH0_TX_END_INT_ENA field.
	RMT_INT_ENA_CH0_TX_END_INT_ENA_Pos = 0x0
	// Bit mask of CH0_TX_END_INT_ENA field.
	RMT_INT_ENA_CH0_TX_END_INT_ENA_Msk = 0x1
	// Bit CH0_TX_END_INT_ENA.
	RMT_INT_ENA_CH0_TX_END_INT_ENA = 0x1
	// Position of CH1_TX_END_INT_ENA field.
	RMT_INT_ENA_CH1_TX_END_INT_ENA_Pos = 0x1
	// Bit mask of CH1_TX_END_INT_ENA field.
	RMT_INT_ENA_CH1_TX_END_INT_ENA_Msk = 0x2
	// Bit CH1_TX_END_INT_ENA.
	RMT_INT_ENA_CH1_TX_END_INT_ENA = 0x2
	// Position of CH2_TX_END_INT_ENA field.
	RMT_INT_ENA_CH2_TX_END_INT_ENA_Pos = 0x2
	// Bit mask of CH2_TX_END_INT_ENA field.
	RMT_INT_ENA_CH2_TX_END_INT_ENA_Msk = 0x4
	// Bit CH2_TX_END_INT_ENA.
	RMT_INT_ENA_CH2_TX_END_INT_ENA = 0x4
	// Position of CH3_TX_END_INT_ENA field.
	RMT_INT_ENA_CH3_TX_END_INT_ENA_Pos = 0x3
	// Bit mask of CH3_TX_END_INT_ENA field.
	RMT_INT_ENA_CH3_TX_END_INT_ENA_Msk = 0x8
	// Bit CH3_TX_END_INT_ENA.
	RMT_INT_ENA_CH3_TX_END_INT_ENA = 0x8
	// Position of TX_CH0_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH0_ERR_INT_ENA_Pos = 0x4
	// Bit mask of TX_CH0_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH0_ERR_INT_ENA_Msk = 0x10
	// Bit TX_CH0_ERR_INT_ENA.
	RMT_INT_ENA_TX_CH0_ERR_INT_ENA = 0x10
	// Position of TX_CH1_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH1_ERR_INT_ENA_Pos = 0x5
	// Bit mask of TX_CH1_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH1_ERR_INT_ENA_Msk = 0x20
	// Bit TX_CH1_ERR_INT_ENA.
	RMT_INT_ENA_TX_CH1_ERR_INT_ENA = 0x20
	// Position of TX_CH2_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH2_ERR_INT_ENA_Pos = 0x6
	// Bit mask of TX_CH2_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH2_ERR_INT_ENA_Msk = 0x40
	// Bit TX_CH2_ERR_INT_ENA.
	RMT_INT_ENA_TX_CH2_ERR_INT_ENA = 0x40
	// Position of TX_CH3_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH3_ERR_INT_ENA_Pos = 0x7
	// Bit mask of TX_CH3_ERR_INT_ENA field.
	RMT_INT_ENA_TX_CH3_ERR_INT_ENA_Msk = 0x80
	// Bit TX_CH3_ERR_INT_ENA.
	RMT_INT_ENA_TX_CH3_ERR_INT_ENA = 0x80
	// Position of CH0_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH0_TX_THR_EVENT_INT_ENA_Pos = 0x8
	// Bit mask of CH0_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH0_TX_THR_EVENT_INT_ENA_Msk = 0x100
	// Bit CH0_TX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH0_TX_THR_EVENT_INT_ENA = 0x100
	// Position of CH1_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH1_TX_THR_EVENT_INT_ENA_Pos = 0x9
	// Bit mask of CH1_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH1_TX_THR_EVENT_INT_ENA_Msk = 0x200
	// Bit CH1_TX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH1_TX_THR_EVENT_INT_ENA = 0x200
	// Position of CH2_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH2_TX_THR_EVENT_INT_ENA_Pos = 0xa
	// Bit mask of CH2_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH2_TX_THR_EVENT_INT_ENA_Msk = 0x400
	// Bit CH2_TX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH2_TX_THR_EVENT_INT_ENA = 0x400
	// Position of CH3_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH3_TX_THR_EVENT_INT_ENA_Pos = 0xb
	// Bit mask of CH3_TX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH3_TX_THR_EVENT_INT_ENA_Msk = 0x800
	// Bit CH3_TX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH3_TX_THR_EVENT_INT_ENA = 0x800
	// Position of CH0_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH0_TX_LOOP_INT_ENA_Pos = 0xc
	// Bit mask of CH0_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH0_TX_LOOP_INT_ENA_Msk = 0x1000
	// Bit CH0_TX_LOOP_INT_ENA.
	RMT_INT_ENA_CH0_TX_LOOP_INT_ENA = 0x1000
	// Position of CH1_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH1_TX_LOOP_INT_ENA_Pos = 0xd
	// Bit mask of CH1_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH1_TX_LOOP_INT_ENA_Msk = 0x2000
	// Bit CH1_TX_LOOP_INT_ENA.
	RMT_INT_ENA_CH1_TX_LOOP_INT_ENA = 0x2000
	// Position of CH2_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH2_TX_LOOP_INT_ENA_Pos = 0xe
	// Bit mask of CH2_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH2_TX_LOOP_INT_ENA_Msk = 0x4000
	// Bit CH2_TX_LOOP_INT_ENA.
	RMT_INT_ENA_CH2_TX_LOOP_INT_ENA = 0x4000
	// Position of CH3_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH3_TX_LOOP_INT_ENA_Pos = 0xf
	// Bit mask of CH3_TX_LOOP_INT_ENA field.
	RMT_INT_ENA_CH3_TX_LOOP_INT_ENA_Msk = 0x8000
	// Bit CH3_TX_LOOP_INT_ENA.
	RMT_INT_ENA_CH3_TX_LOOP_INT_ENA = 0x8000
	// Position of CH4_RX_END_INT_ENA field.
	RMT_INT_ENA_CH4_RX_END_INT_ENA_Pos = 0x10
	// Bit mask of CH4_RX_END_INT_ENA field.
	RMT_INT_ENA_CH4_RX_END_INT_ENA_Msk = 0x10000
	// Bit CH4_RX_END_INT_ENA.
	RMT_INT_ENA_CH4_RX_END_INT_ENA = 0x10000
	// Position of CH5_RX_END_INT_ENA field.
	RMT_INT_ENA_CH5_RX_END_INT_ENA_Pos = 0x11
	// Bit mask of CH5_RX_END_INT_ENA field.
	RMT_INT_ENA_CH5_RX_END_INT_ENA_Msk = 0x20000
	// Bit CH5_RX_END_INT_ENA.
	RMT_INT_ENA_CH5_RX_END_INT_ENA = 0x20000
	// Position of CH6_RX_END_INT_ENA field.
	RMT_INT_ENA_CH6_RX_END_INT_ENA_Pos = 0x12
	// Bit mask of CH6_RX_END_INT_ENA field.
	RMT_INT_ENA_CH6_RX_END_INT_ENA_Msk = 0x40000
	// Bit CH6_RX_END_INT_ENA.
	RMT_INT_ENA_CH6_RX_END_INT_ENA = 0x40000
	// Position of CH7_RX_END_INT_ENA field.
	RMT_INT_ENA_CH7_RX_END_INT_ENA_Pos = 0x13
	// Bit mask of CH7_RX_END_INT_ENA field.
	RMT_INT_ENA_CH7_RX_END_INT_ENA_Msk = 0x80000
	// Bit CH7_RX_END_INT_ENA.
	RMT_INT_ENA_CH7_RX_END_INT_ENA = 0x80000
	// Position of CH4_ERR_INT_ENA field.
	RMT_INT_ENA_CH4_ERR_INT_ENA_Pos = 0x14
	// Bit mask of CH4_ERR_INT_ENA field.
	RMT_INT_ENA_CH4_ERR_INT_ENA_Msk = 0x100000
	// Bit CH4_ERR_INT_ENA.
	RMT_INT_ENA_CH4_ERR_INT_ENA = 0x100000
	// Position of CH5_ERR_INT_ENA field.
	RMT_INT_ENA_CH5_ERR_INT_ENA_Pos = 0x15
	// Bit mask of CH5_ERR_INT_ENA field.
	RMT_INT_ENA_CH5_ERR_INT_ENA_Msk = 0x200000
	// Bit CH5_ERR_INT_ENA.
	RMT_INT_ENA_CH5_ERR_INT_ENA = 0x200000
	// Position of CH6_ERR_INT_ENA field.
	RMT_INT_ENA_CH6_ERR_INT_ENA_Pos = 0x16
	// Bit mask of CH6_ERR_INT_ENA field.
	RMT_INT_ENA_CH6_ERR_INT_ENA_Msk = 0x400000
	// Bit CH6_ERR_INT_ENA.
	RMT_INT_ENA_CH6_ERR_INT_ENA = 0x400000
	// Position of CH7_ERR_INT_ENA field.
	RMT_INT_ENA_CH7_ERR_INT_ENA_Pos = 0x17
	// Bit mask of CH7_ERR_INT_ENA field.
	RMT_INT_ENA_CH7_ERR_INT_ENA_Msk = 0x800000
	// Bit CH7_ERR_INT_ENA.
	RMT_INT_ENA_CH7_ERR_INT_ENA = 0x800000
	// Position of CH4_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH4_RX_THR_EVENT_INT_ENA_Pos = 0x18
	// Bit mask of CH4_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH4_RX_THR_EVENT_INT_ENA_Msk = 0x1000000
	// Bit CH4_RX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH4_RX_THR_EVENT_INT_ENA = 0x1000000
	// Position of CH5_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH5_RX_THR_EVENT_INT_ENA_Pos = 0x19
	// Bit mask of CH5_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH5_RX_THR_EVENT_INT_ENA_Msk = 0x2000000
	// Bit CH5_RX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH5_RX_THR_EVENT_INT_ENA = 0x2000000
	// Position of CH6_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH6_RX_THR_EVENT_INT_ENA_Pos = 0x1a
	// Bit mask of CH6_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH6_RX_THR_EVENT_INT_ENA_Msk = 0x4000000
	// Bit CH6_RX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH6_RX_THR_EVENT_INT_ENA = 0x4000000
	// Position of CH7_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH7_RX_THR_EVENT_INT_ENA_Pos = 0x1b
	// Bit mask of CH7_RX_THR_EVENT_INT_ENA field.
	RMT_INT_ENA_CH7_RX_THR_EVENT_INT_ENA_Msk = 0x8000000
	// Bit CH7_RX_THR_EVENT_INT_ENA.
	RMT_INT_ENA_CH7_RX_THR_EVENT_INT_ENA = 0x8000000
	// Position of TX_CH3_DMA_ACCESS_FAIL_INT_ENA field.
	RMT_INT_ENA_TX_CH3_DMA_ACCESS_FAIL_INT_ENA_Pos = 0x1c
	// Bit mask of TX_CH3_DMA_ACCESS_FAIL_INT_ENA field.
	RMT_INT_ENA_TX_CH3_DMA_ACCESS_FAIL_INT_ENA_Msk = 0x10000000
	// Bit TX_CH3_DMA_ACCESS_FAIL_INT_ENA.
	RMT_INT_ENA_TX_CH3_DMA_ACCESS_FAIL_INT_ENA = 0x10000000
	// Position of RX_CH7_DMA_ACCESS_FAIL_INT_ENA field.
	RMT_INT_ENA_RX_CH7_DMA_ACCESS_FAIL_INT_ENA_Pos = 0x1d
	// Bit mask of RX_CH7_DMA_ACCESS_FAIL_INT_ENA field.
	RMT_INT_ENA_RX_CH7_DMA_ACCESS_FAIL_INT_ENA_Msk = 0x20000000
	// Bit RX_CH7_DMA_ACCESS_FAIL_INT_ENA.
	RMT_INT_ENA_RX_CH7_DMA_ACCESS_FAIL_INT_ENA = 0x20000000

	// INT_CLR: Interrupt clear bits
	// Position of CH0_TX_END_INT_CLR field.
	RMT_INT_CLR_CH0_TX_END_INT_CLR_Pos = 0x0
	// Bit mask of CH0_TX_END_INT_CLR field.
	RMT_INT_CLR_CH0_TX_END_INT_CLR_Msk = 0x1
	// Bit CH0_TX_END_INT_CLR.
	RMT_INT_CLR_CH0_TX_END_INT_CLR = 0x1
	// Position of CH1_TX_END_INT_CLR field.
	RMT_INT_CLR_CH1_TX_END_INT_CLR_Pos = 0x1
	// Bit mask of CH1_TX_END_INT_CLR field.
	RMT_INT_CLR_CH1_TX_END_INT_CLR_Msk = 0x2
	// Bit CH1_TX_END_INT_CLR.
	RMT_INT_CLR_CH1_TX_END_INT_CLR = 0x2
	// Position of CH2_TX_END_INT_CLR field.
	RMT_INT_CLR_CH2_TX_END_INT_CLR_Pos = 0x2
	// Bit mask of CH2_TX_END_INT_CLR field.
	RMT_INT_CLR_CH2_TX_END_INT_CLR_Msk = 0x4
	// Bit CH2_TX_END_INT_CLR.
	RMT_INT_CLR_CH2_TX_END_INT_CLR = 0x4
	// Position of CH3_TX_END_INT_CLR field.
	RMT_INT_CLR_CH3_TX_END_INT_CLR_Pos = 0x3
	// Bit mask of CH3_TX_END_INT_CLR field.
	RMT_INT_CLR_CH3_TX_END_INT_CLR_Msk = 0x8
	// Bit CH3_TX_END_INT_CLR.
	RMT_INT_CLR_CH3_TX_END_INT_CLR = 0x8
	// Position of TX_CH0_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH0_ERR_INT_CLR_Pos = 0x4
	// Bit mask of TX_CH0_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH0_ERR_INT_CLR_Msk = 0x10
	// Bit TX_CH0_ERR_INT_CLR.
	RMT_INT_CLR_TX_CH0_ERR_INT_CLR = 0x10
	// Position of TX_CH1_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH1_ERR_INT_CLR_Pos = 0x5
	// Bit mask of TX_CH1_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH1_ERR_INT_CLR_Msk = 0x20
	// Bit TX_CH1_ERR_INT_CLR.
	RMT_INT_CLR_TX_CH1_ERR_INT_CLR = 0x20
	// Position of TX_CH2_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH2_ERR_INT_CLR_Pos = 0x6
	// Bit mask of TX_CH2_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH2_ERR_INT_CLR_Msk = 0x40
	// Bit TX_CH2_ERR_INT_CLR.
	RMT_INT_CLR_TX_CH2_ERR_INT_CLR = 0x40
	// Position of TX_CH3_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH3_ERR_INT_CLR_Pos = 0x7
	// Bit mask of TX_CH3_ERR_INT_CLR field.
	RMT_INT_CLR_TX_CH3_ERR_INT_CLR_Msk = 0x80
	// Bit TX_CH3_ERR_INT_CLR.
	RMT_INT_CLR_TX_CH3_ERR_INT_CLR = 0x80
	// Position of CH0_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH0_TX_THR_EVENT_INT_CLR_Pos = 0x8
	// Bit mask of CH0_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH0_TX_THR_EVENT_INT_CLR_Msk = 0x100
	// Bit CH0_TX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH0_TX_THR_EVENT_INT_CLR = 0x100
	// Position of CH1_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH1_TX_THR_EVENT_INT_CLR_Pos = 0x9
	// Bit mask of CH1_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH1_TX_THR_EVENT_INT_CLR_Msk = 0x200
	// Bit CH1_TX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH1_TX_THR_EVENT_INT_CLR = 0x200
	// Position of CH2_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH2_TX_THR_EVENT_INT_CLR_Pos = 0xa
	// Bit mask of CH2_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH2_TX_THR_EVENT_INT_CLR_Msk = 0x400
	// Bit CH2_TX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH2_TX_THR_EVENT_INT_CLR = 0x400
	// Position of CH3_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH3_TX_THR_EVENT_INT_CLR_Pos = 0xb
	// Bit mask of CH3_TX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH3_TX_THR_EVENT_INT_CLR_Msk = 0x800
	// Bit CH3_TX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH3_TX_THR_EVENT_INT_CLR = 0x800
	// Position of CH0_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH0_TX_LOOP_INT_CLR_Pos = 0xc
	// Bit mask of CH0_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH0_TX_LOOP_INT_CLR_Msk = 0x1000
	// Bit CH0_TX_LOOP_INT_CLR.
	RMT_INT_CLR_CH0_TX_LOOP_INT_CLR = 0x1000
	// Position of CH1_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH1_TX_LOOP_INT_CLR_Pos = 0xd
	// Bit mask of CH1_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH1_TX_LOOP_INT_CLR_Msk = 0x2000
	// Bit CH1_TX_LOOP_INT_CLR.
	RMT_INT_CLR_CH1_TX_LOOP_INT_CLR = 0x2000
	// Position of CH2_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH2_TX_LOOP_INT_CLR_Pos = 0xe
	// Bit mask of CH2_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH2_TX_LOOP_INT_CLR_Msk = 0x4000
	// Bit CH2_TX_LOOP_INT_CLR.
	RMT_INT_CLR_CH2_TX_LOOP_INT_CLR = 0x4000
	// Position of CH3_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH3_TX_LOOP_INT_CLR_Pos = 0xf
	// Bit mask of CH3_TX_LOOP_INT_CLR field.
	RMT_INT_CLR_CH3_TX_LOOP_INT_CLR_Msk = 0x8000
	// Bit CH3_TX_LOOP_INT_CLR.
	RMT_INT_CLR_CH3_TX_LOOP_INT_CLR = 0x8000
	// Position of CH4_RX_END_INT_CLR field.
	RMT_INT_CLR_CH4_RX_END_INT_CLR_Pos = 0x10
	// Bit mask of CH4_RX_END_INT_CLR field.
	RMT_INT_CLR_CH4_RX_END_INT_CLR_Msk = 0x10000
	// Bit CH4_RX_END_INT_CLR.
	RMT_INT_CLR_CH4_RX_END_INT_CLR = 0x10000
	// Position of CH5_RX_END_INT_CLR field.
	RMT_INT_CLR_CH5_RX_END_INT_CLR_Pos = 0x11
	// Bit mask of CH5_RX_END_INT_CLR field.
	RMT_INT_CLR_CH5_RX_END_INT_CLR_Msk = 0x20000
	// Bit CH5_RX_END_INT_CLR.
	RMT_INT_CLR_CH5_RX_END_INT_CLR = 0x20000
	// Position of CH6_RX_END_INT_CLR field.
	RMT_INT_CLR_CH6_RX_END_INT_CLR_Pos = 0x12
	// Bit mask of CH6_RX_END_INT_CLR field.
	RMT_INT_CLR_CH6_RX_END_INT_CLR_Msk = 0x40000
	// Bit CH6_RX_END_INT_CLR.
	RMT_INT_CLR_CH6_RX_END_INT_CLR = 0x40000
	// Position of CH7_RX_END_INT_CLR field.
	RMT_INT_CLR_CH7_RX_END_INT_CLR_Pos = 0x13
	// Bit mask of CH7_RX_END_INT_CLR field.
	RMT_INT_CLR_CH7_RX_END_INT_CLR_Msk = 0x80000
	// Bit CH7_RX_END_INT_CLR.
	RMT_INT_CLR_CH7_RX_END_INT_CLR = 0x80000
	// Position of RX_CH4_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH4_ERR_INT_CLR_Pos = 0x14
	// Bit mask of RX_CH4_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH4_ERR_INT_CLR_Msk = 0x100000
	// Bit RX_CH4_ERR_INT_CLR.
	RMT_INT_CLR_RX_CH4_ERR_INT_CLR = 0x100000
	// Position of RX_CH5_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH5_ERR_INT_CLR_Pos = 0x15
	// Bit mask of RX_CH5_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH5_ERR_INT_CLR_Msk = 0x200000
	// Bit RX_CH5_ERR_INT_CLR.
	RMT_INT_CLR_RX_CH5_ERR_INT_CLR = 0x200000
	// Position of RX_CH6_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH6_ERR_INT_CLR_Pos = 0x16
	// Bit mask of RX_CH6_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH6_ERR_INT_CLR_Msk = 0x400000
	// Bit RX_CH6_ERR_INT_CLR.
	RMT_INT_CLR_RX_CH6_ERR_INT_CLR = 0x400000
	// Position of RX_CH7_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH7_ERR_INT_CLR_Pos = 0x17
	// Bit mask of RX_CH7_ERR_INT_CLR field.
	RMT_INT_CLR_RX_CH7_ERR_INT_CLR_Msk = 0x800000
	// Bit RX_CH7_ERR_INT_CLR.
	RMT_INT_CLR_RX_CH7_ERR_INT_CLR = 0x800000
	// Position of CH4_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH4_RX_THR_EVENT_INT_CLR_Pos = 0x18
	// Bit mask of CH4_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH4_RX_THR_EVENT_INT_CLR_Msk = 0x1000000
	// Bit CH4_RX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH4_RX_THR_EVENT_INT_CLR = 0x1000000
	// Position of CH5_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH5_RX_THR_EVENT_INT_CLR_Pos = 0x19
	// Bit mask of CH5_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH5_RX_THR_EVENT_INT_CLR_Msk = 0x2000000
	// Bit CH5_RX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH5_RX_THR_EVENT_INT_CLR = 0x2000000
	// Position of CH6_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH6_RX_THR_EVENT_INT_CLR_Pos = 0x1a
	// Bit mask of CH6_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH6_RX_THR_EVENT_INT_CLR_Msk = 0x4000000
	// Bit CH6_RX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH6_RX_THR_EVENT_INT_CLR = 0x4000000
	// Position of CH7_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH7_RX_THR_EVENT_INT_CLR_Pos = 0x1b
	// Bit mask of CH7_RX_THR_EVENT_INT_CLR field.
	RMT_INT_CLR_CH7_RX_THR_EVENT_INT_CLR_Msk = 0x8000000
	// Bit CH7_RX_THR_EVENT_INT_CLR.
	RMT_INT_CLR_CH7_RX_THR_EVENT_INT_CLR = 0x8000000
	// Position of TX_CH3_DMA_ACCESS_FAIL_INT_CLR field.
	RMT_INT_CLR_TX_CH3_DMA_ACCESS_FAIL_INT_CLR_Pos = 0x1c
	// Bit mask of TX_CH3_DMA_ACCESS_FAIL_INT_CLR field.
	RMT_INT_CLR_TX_CH3_DMA_ACCESS_FAIL_INT_CLR_Msk = 0x10000000
	// Bit TX_CH3_DMA_ACCESS_FAIL_INT_CLR.
	RMT_INT_CLR_TX_CH3_DMA_ACCESS_FAIL_INT_CLR = 0x10000000
	// Position of RX_CH7_DMA_ACCESS_FAIL_INT_CLR field.
	RMT_INT_CLR_RX_CH7_DMA_ACCESS_FAIL_INT_CLR_Pos = 0x1d
	// Bit mask of RX_CH7_DMA_ACCESS_FAIL_INT_CLR field.
	RMT_INT_CLR_RX_CH7_DMA_ACCESS_FAIL_INT_CLR_Msk = 0x20000000
	// Bit RX_CH7_DMA_ACCESS_FAIL_INT_CLR.
	RMT_INT_CLR_RX_CH7_DMA_ACCESS_FAIL_INT_CLR = 0x20000000

	// CH0CARRIER_DUTY: Channel %s duty cycle configuration register
	// Position of CARRIER_LOW_CH field.
	RMT_CHCARRIER_DUTY_CARRIER_LOW_CH_Pos = 0x0
	// Bit mask of CARRIER_LOW_CH field.
	RMT_CHCARRIER_DUTY_CARRIER_LOW_CH_Msk = 0xffff
	// Position of CARRIER_HIGH_CH field.
	RMT_CHCARRIER_DUTY_CARRIER_HIGH_CH_Pos = 0x10
	// Bit mask of CARRIER_HIGH_CH field.
	RMT_CHCARRIER_DUTY_CARRIER_HIGH_CH_Msk = 0xffff0000

	// CH0_RX_CARRIER_RM: Channel %s carrier remove register
	// Position of CARRIER_LOW_THRES_CH field.
	RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_CH_Pos = 0x0
	// Bit mask of CARRIER_LOW_THRES_CH field.
	RMT_CH_RX_CARRIER_RM_CARRIER_LOW_THRES_CH_Msk = 0xffff
	// Position of CARRIER_HIGH_THRES_CH field.
	RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH_Pos = 0x10
	// Bit mask of CARRIER_HIGH_THRES_CH field.
	RMT_CH_RX_CARRIER_RM_CARRIER_HIGH_THRES_CH_Msk = 0xffff0000

	// CH0_TX_LIM: Channel %s Tx event configuration register
	// Position of TX_LIM_CH field.
	RMT_CH_TX_LIM_TX_LIM_CH_Pos = 0x0
	// Bit mask of TX_LIM_CH field.
	RMT_CH_TX_LIM_TX_LIM_CH_Msk = 0x1ff
	// Position of TX_LOOP_NUM_CH field.
	RMT_CH_TX_LIM_TX_LOOP_NUM_CH_Pos = 0x9
	// Bit mask of TX_LOOP_NUM_CH field.
	RMT_CH_TX_LIM_TX_LOOP_NUM_CH_Msk = 0x7fe00
	// Position of TX_LOOP_CNT_EN_CH field.
	RMT_CH_TX_LIM_TX_LOOP_CNT_EN_CH_Pos = 0x13
	// Bit mask of TX_LOOP_CNT_EN_CH field.
	RMT_CH_TX_LIM_TX_LOOP_CNT_EN_CH_Msk = 0x80000
	// Bit TX_LOOP_CNT_EN_CH.
	RMT_CH_TX_LIM_TX_LOOP_CNT_EN_CH = 0x80000
	// Position of LOOP_COUNT_RESET_CH field.
	RMT_CH_TX_LIM_LOOP_COUNT_RESET_CH_Pos = 0x14
	// Bit mask of LOOP_COUNT_RESET_CH field.
	RMT_CH_TX_LIM_LOOP_COUNT_RESET_CH_Msk = 0x100000
	// Bit LOOP_COUNT_RESET_CH.
	RMT_CH_TX_LIM_LOOP_COUNT_RESET_CH = 0x100000
	// Position of LOOP_STOP_EN_CH field.
	RMT_CH_TX_LIM_LOOP_STOP_EN_CH_Pos = 0x15
	// Bit mask of LOOP_STOP_EN_CH field.
	RMT_CH_TX_LIM_LOOP_STOP_EN_CH_Msk = 0x200000
	// Bit LOOP_STOP_EN_CH.
	RMT_CH_TX_LIM_LOOP_STOP_EN_CH = 0x200000

	// CH0_RX_LIM: Channel %s Rx event configuration register
	// Position of RX_LIM_CH4 field.
	RMT_CH_RX_LIM_RX_LIM_CH4_Pos = 0x0
	// Bit mask of RX_LIM_CH4 field.
	RMT_CH_RX_LIM_RX_LIM_CH4_Msk = 0x1ff

	// SYS_CONF: RMT apb configuration register
	// Position of APB_FIFO_MASK field.
	RMT_SYS_CONF_APB_FIFO_MASK_Pos = 0x0
	// Bit mask of APB_FIFO_MASK field.
	RMT_SYS_CONF_APB_FIFO_MASK_Msk = 0x1
	// Bit APB_FIFO_MASK.
	RMT_SYS_CONF_APB_FIFO_MASK = 0x1
	// Position of MEM_CLK_FORCE_ON field.
	RMT_SYS_CONF_MEM_CLK_FORCE_ON_Pos = 0x1
	// Bit mask of MEM_CLK_FORCE_ON field.
	RMT_SYS_CONF_MEM_CLK_FORCE_ON_Msk = 0x2
	// Bit MEM_CLK_FORCE_ON.
	RMT_SYS_CONF_MEM_CLK_FORCE_ON = 0x2
	// Position of MEM_FORCE_PD field.
	RMT_SYS_CONF_MEM_FORCE_PD_Pos = 0x2
	// Bit mask of MEM_FORCE_PD field.
	RMT_SYS_CONF_MEM_FORCE_PD_Msk = 0x4
	// Bit MEM_FORCE_PD.
	RMT_SYS_CONF_MEM_FORCE_PD = 0x4
	// Position of MEM_FORCE_PU field.
	RMT_SYS_CONF_MEM_FORCE_PU_Pos = 0x3
	// Bit mask of MEM_FORCE_PU field.
	RMT_SYS_CONF_MEM_FORCE_PU_Msk = 0x8
	// Bit MEM_FORCE_PU.
	RMT_SYS_CONF_MEM_FORCE_PU = 0x8
	// Position of SCLK_DIV_NUM field.
	RMT_SYS_CONF_SCLK_DIV_NUM_Pos = 0x4
	// Bit mask of SCLK_DIV_NUM field.
	RMT_SYS_CONF_SCLK_DIV_NUM_Msk = 0xff0
	// Position of SCLK_DIV_A field.
	RMT_SYS_CONF_SCLK_DIV_A_Pos = 0xc
	// Bit mask of SCLK_DIV_A field.
	RMT_SYS_CONF_SCLK_DIV_A_Msk = 0x3f000
	// Position of SCLK_DIV_B field.
	RMT_SYS_CONF_SCLK_DIV_B_Pos = 0x12
	// Bit mask of SCLK_DIV_B field.
	RMT_SYS_CONF_SCLK_DIV_B_Msk = 0xfc0000
	// Position of SCLK_SEL field.
	RMT_SYS_CONF_SCLK_SEL_Pos = 0x18
	// Bit mask of SCLK_SEL field.
	RMT_SYS_CONF_SCLK_SEL_Msk = 0x3000000
	// Position of SCLK_ACTIVE field.
	RMT_SYS_CONF_SCLK_ACTIVE_Pos = 0x1a
	// Bit mask of SCLK_ACTIVE field.
	RMT_SYS_CONF_SCLK_ACTIVE_Msk = 0x4000000
	// Bit SCLK_ACTIVE.
	RMT_SYS_CONF_SCLK_ACTIVE = 0x4000000
	// Position of CLK_EN field.
	RMT_SYS_CONF_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	RMT_SYS_CONF_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	RMT_SYS_CONF_CLK_EN = 0x80000000

	// TX_SIM: RMT TX synchronous register
	// Position of CH0 field.
	RMT_TX_SIM_CH0_Pos = 0x0
	// Bit mask of CH0 field.
	RMT_TX_SIM_CH0_Msk = 0x1
	// Bit CH0.
	RMT_TX_SIM_CH0 = 0x1
	// Position of CH1 field.
	RMT_TX_SIM_CH1_Pos = 0x1
	// Bit mask of CH1 field.
	RMT_TX_SIM_CH1_Msk = 0x2
	// Bit CH1.
	RMT_TX_SIM_CH1 = 0x2
	// Position of CH2 field.
	RMT_TX_SIM_CH2_Pos = 0x2
	// Bit mask of CH2 field.
	RMT_TX_SIM_CH2_Msk = 0x4
	// Bit CH2.
	RMT_TX_SIM_CH2 = 0x4
	// Position of CH3 field.
	RMT_TX_SIM_CH3_Pos = 0x3
	// Bit mask of CH3 field.
	RMT_TX_SIM_CH3_Msk = 0x8
	// Bit CH3.
	RMT_TX_SIM_CH3 = 0x8
	// Position of EN field.
	RMT_TX_SIM_EN_Pos = 0x4
	// Bit mask of EN field.
	RMT_TX_SIM_EN_Msk = 0x10
	// Bit EN.
	RMT_TX_SIM_EN = 0x10

	// REF_CNT_RST: RMT clock divider reset register
	// Position of TX_REF_CNT_RST_CH0 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH0_Pos = 0x0
	// Bit mask of TX_REF_CNT_RST_CH0 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH0_Msk = 0x1
	// Bit TX_REF_CNT_RST_CH0.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH0 = 0x1
	// Position of TX_REF_CNT_RST_CH1 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1_Pos = 0x1
	// Bit mask of TX_REF_CNT_RST_CH1 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1_Msk = 0x2
	// Bit TX_REF_CNT_RST_CH1.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH1 = 0x2
	// Position of TX_REF_CNT_RST_CH2 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH2_Pos = 0x2
	// Bit mask of TX_REF_CNT_RST_CH2 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH2_Msk = 0x4
	// Bit TX_REF_CNT_RST_CH2.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH2 = 0x4
	// Position of TX_REF_CNT_RST_CH3 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH3_Pos = 0x3
	// Bit mask of TX_REF_CNT_RST_CH3 field.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH3_Msk = 0x8
	// Bit TX_REF_CNT_RST_CH3.
	RMT_REF_CNT_RST_TX_REF_CNT_RST_CH3 = 0x8
	// Position of RX_REF_CNT_RST_CH4 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH4_Pos = 0x4
	// Bit mask of RX_REF_CNT_RST_CH4 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH4_Msk = 0x10
	// Bit RX_REF_CNT_RST_CH4.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH4 = 0x10
	// Position of RX_REF_CNT_RST_CH5 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH5_Pos = 0x5
	// Bit mask of RX_REF_CNT_RST_CH5 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH5_Msk = 0x20
	// Bit RX_REF_CNT_RST_CH5.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH5 = 0x20
	// Position of RX_REF_CNT_RST_CH6 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH6_Pos = 0x6
	// Bit mask of RX_REF_CNT_RST_CH6 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH6_Msk = 0x40
	// Bit RX_REF_CNT_RST_CH6.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH6 = 0x40
	// Position of RX_REF_CNT_RST_CH7 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH7_Pos = 0x7
	// Bit mask of RX_REF_CNT_RST_CH7 field.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH7_Msk = 0x80
	// Bit RX_REF_CNT_RST_CH7.
	RMT_REF_CNT_RST_RX_REF_CNT_RST_CH7 = 0x80

	// DATE: RMT version register
	// Position of DATE field.
	RMT_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	RMT_DATE_DATE_Msk = 0xfffffff
)

// Constants for RSA: RSA (Rivest Shamir Adleman) Accelerator
const (
	// M_PRIME: Represents M’
	// Position of M_PRIME field.
	RSA_M_PRIME_M_PRIME_Pos = 0x0
	// Bit mask of M_PRIME field.
	RSA_M_PRIME_M_PRIME_Msk = 0xffffffff

	// MODE: Configures RSA length
	// Position of MODE field.
	RSA_MODE_MODE_Pos = 0x0
	// Bit mask of MODE field.
	RSA_MODE_MODE_Msk = 0x7f

	// QUERY_CLEAN: RSA clean register
	// Position of QUERY_CLEAN field.
	RSA_QUERY_CLEAN_QUERY_CLEAN_Pos = 0x0
	// Bit mask of QUERY_CLEAN field.
	RSA_QUERY_CLEAN_QUERY_CLEAN_Msk = 0x1
	// Bit QUERY_CLEAN.
	RSA_QUERY_CLEAN_QUERY_CLEAN = 0x1

	// SET_START_MODEXP: Starts modular exponentiation
	// Position of SET_START_MODEXP field.
	RSA_SET_START_MODEXP_SET_START_MODEXP_Pos = 0x0
	// Bit mask of SET_START_MODEXP field.
	RSA_SET_START_MODEXP_SET_START_MODEXP_Msk = 0x1
	// Bit SET_START_MODEXP.
	RSA_SET_START_MODEXP_SET_START_MODEXP = 0x1

	// SET_START_MODMULT: Starts modular multiplication
	// Position of SET_START_MODMULT field.
	RSA_SET_START_MODMULT_SET_START_MODMULT_Pos = 0x0
	// Bit mask of SET_START_MODMULT field.
	RSA_SET_START_MODMULT_SET_START_MODMULT_Msk = 0x1
	// Bit SET_START_MODMULT.
	RSA_SET_START_MODMULT_SET_START_MODMULT = 0x1

	// SET_START_MULT: Starts multiplication
	// Position of SET_START_MULT field.
	RSA_SET_START_MULT_SET_START_MULT_Pos = 0x0
	// Bit mask of SET_START_MULT field.
	RSA_SET_START_MULT_SET_START_MULT_Msk = 0x1
	// Bit SET_START_MULT.
	RSA_SET_START_MULT_SET_START_MULT = 0x1

	// QUERY_IDLE: Represents the RSA status
	// Position of QUERY_IDLE field.
	RSA_QUERY_IDLE_QUERY_IDLE_Pos = 0x0
	// Bit mask of QUERY_IDLE field.
	RSA_QUERY_IDLE_QUERY_IDLE_Msk = 0x1
	// Bit QUERY_IDLE.
	RSA_QUERY_IDLE_QUERY_IDLE = 0x1

	// INT_CLR: Clears RSA interrupt
	// Position of CLEAR_INTERRUPT field.
	RSA_INT_CLR_CLEAR_INTERRUPT_Pos = 0x0
	// Bit mask of CLEAR_INTERRUPT field.
	RSA_INT_CLR_CLEAR_INTERRUPT_Msk = 0x1
	// Bit CLEAR_INTERRUPT.
	RSA_INT_CLR_CLEAR_INTERRUPT = 0x1

	// CONSTANT_TIME: Configures the constant_time option
	// Position of CONSTANT_TIME field.
	RSA_CONSTANT_TIME_CONSTANT_TIME_Pos = 0x0
	// Bit mask of CONSTANT_TIME field.
	RSA_CONSTANT_TIME_CONSTANT_TIME_Msk = 0x1
	// Bit CONSTANT_TIME.
	RSA_CONSTANT_TIME_CONSTANT_TIME = 0x1

	// SEARCH_ENABLE: Configures the search option
	// Position of SEARCH_ENABLE field.
	RSA_SEARCH_ENABLE_SEARCH_ENABLE_Pos = 0x0
	// Bit mask of SEARCH_ENABLE field.
	RSA_SEARCH_ENABLE_SEARCH_ENABLE_Msk = 0x1
	// Bit SEARCH_ENABLE.
	RSA_SEARCH_ENABLE_SEARCH_ENABLE = 0x1

	// SEARCH_POS: Configures the search position
	// Position of SEARCH_POS field.
	RSA_SEARCH_POS_SEARCH_POS_Pos = 0x0
	// Bit mask of SEARCH_POS field.
	RSA_SEARCH_POS_SEARCH_POS_Msk = 0xfff

	// INT_ENA: Enables the RSA interrupt
	// Position of INT_ENA field.
	RSA_INT_ENA_INT_ENA_Pos = 0x0
	// Bit mask of INT_ENA field.
	RSA_INT_ENA_INT_ENA_Msk = 0x1
	// Bit INT_ENA.
	RSA_INT_ENA_INT_ENA = 0x1

	// DATE: Version control register
	// Position of DATE field.
	RSA_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	RSA_DATE_DATE_Msk = 0x3fffffff
)

// Constants for LP_ADC: Low-power Analog to Digital Converter
const (
	// READER1_CTRL: Control the read operation of ADC1.
	// Position of SAR1_CLK_DIV field.
	RTCADC_READER1_CTRL_SAR1_CLK_DIV_Pos = 0x0
	// Bit mask of SAR1_CLK_DIV field.
	RTCADC_READER1_CTRL_SAR1_CLK_DIV_Msk = 0xff
	// Position of SAR1_CLK_GATED field.
	RTCADC_READER1_CTRL_SAR1_CLK_GATED_Pos = 0x12
	// Bit mask of SAR1_CLK_GATED field.
	RTCADC_READER1_CTRL_SAR1_CLK_GATED_Msk = 0x40000
	// Bit SAR1_CLK_GATED.
	RTCADC_READER1_CTRL_SAR1_CLK_GATED = 0x40000
	// Position of SAR1_SAMPLE_NUM field.
	RTCADC_READER1_CTRL_SAR1_SAMPLE_NUM_Pos = 0x13
	// Bit mask of SAR1_SAMPLE_NUM field.
	RTCADC_READER1_CTRL_SAR1_SAMPLE_NUM_Msk = 0x7f80000
	// Position of SAR1_DATA_INV field.
	RTCADC_READER1_CTRL_SAR1_DATA_INV_Pos = 0x1c
	// Bit mask of SAR1_DATA_INV field.
	RTCADC_READER1_CTRL_SAR1_DATA_INV_Msk = 0x10000000
	// Bit SAR1_DATA_INV.
	RTCADC_READER1_CTRL_SAR1_DATA_INV = 0x10000000
	// Position of SAR1_INT_EN field.
	RTCADC_READER1_CTRL_SAR1_INT_EN_Pos = 0x1d
	// Bit mask of SAR1_INT_EN field.
	RTCADC_READER1_CTRL_SAR1_INT_EN_Msk = 0x20000000
	// Bit SAR1_INT_EN.
	RTCADC_READER1_CTRL_SAR1_INT_EN = 0x20000000
	// Position of SAR1_EN_PAD_FORCE_ENABLE field.
	RTCADC_READER1_CTRL_SAR1_EN_PAD_FORCE_ENABLE_Pos = 0x1e
	// Bit mask of SAR1_EN_PAD_FORCE_ENABLE field.
	RTCADC_READER1_CTRL_SAR1_EN_PAD_FORCE_ENABLE_Msk = 0xc0000000

	// READER1_STATUS: N/A
	// Position of SAR1_READER_STATUS field.
	RTCADC_READER1_STATUS_SAR1_READER_STATUS_Pos = 0x0
	// Bit mask of SAR1_READER_STATUS field.
	RTCADC_READER1_STATUS_SAR1_READER_STATUS_Msk = 0xffffffff

	// MEAS1_CTRL1: N/A
	// Position of FORCE_XPD_AMP field.
	RTCADC_MEAS1_CTRL1_FORCE_XPD_AMP_Pos = 0x18
	// Bit mask of FORCE_XPD_AMP field.
	RTCADC_MEAS1_CTRL1_FORCE_XPD_AMP_Msk = 0x3000000
	// Position of AMP_RST_FB_FORCE field.
	RTCADC_MEAS1_CTRL1_AMP_RST_FB_FORCE_Pos = 0x1a
	// Bit mask of AMP_RST_FB_FORCE field.
	RTCADC_MEAS1_CTRL1_AMP_RST_FB_FORCE_Msk = 0xc000000
	// Position of AMP_SHORT_REF_FORCE field.
	RTCADC_MEAS1_CTRL1_AMP_SHORT_REF_FORCE_Pos = 0x1c
	// Bit mask of AMP_SHORT_REF_FORCE field.
	RTCADC_MEAS1_CTRL1_AMP_SHORT_REF_FORCE_Msk = 0x30000000
	// Position of AMP_SHORT_REF_GND_FORCE field.
	RTCADC_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE_Pos = 0x1e
	// Bit mask of AMP_SHORT_REF_GND_FORCE field.
	RTCADC_MEAS1_CTRL1_AMP_SHORT_REF_GND_FORCE_Msk = 0xc0000000

	// MEAS1_CTRL2: ADC1 configuration registers.
	// Position of MEAS1_DATA_SAR field.
	RTCADC_MEAS1_CTRL2_MEAS1_DATA_SAR_Pos = 0x0
	// Bit mask of MEAS1_DATA_SAR field.
	RTCADC_MEAS1_CTRL2_MEAS1_DATA_SAR_Msk = 0xffff
	// Position of MEAS1_DONE_SAR field.
	RTCADC_MEAS1_CTRL2_MEAS1_DONE_SAR_Pos = 0x10
	// Bit mask of MEAS1_DONE_SAR field.
	RTCADC_MEAS1_CTRL2_MEAS1_DONE_SAR_Msk = 0x10000
	// Bit MEAS1_DONE_SAR.
	RTCADC_MEAS1_CTRL2_MEAS1_DONE_SAR = 0x10000
	// Position of MEAS1_START_SAR field.
	RTCADC_MEAS1_CTRL2_MEAS1_START_SAR_Pos = 0x11
	// Bit mask of MEAS1_START_SAR field.
	RTCADC_MEAS1_CTRL2_MEAS1_START_SAR_Msk = 0x20000
	// Bit MEAS1_START_SAR.
	RTCADC_MEAS1_CTRL2_MEAS1_START_SAR = 0x20000
	// Position of MEAS1_START_FORCE field.
	RTCADC_MEAS1_CTRL2_MEAS1_START_FORCE_Pos = 0x12
	// Bit mask of MEAS1_START_FORCE field.
	RTCADC_MEAS1_CTRL2_MEAS1_START_FORCE_Msk = 0x40000
	// Bit MEAS1_START_FORCE.
	RTCADC_MEAS1_CTRL2_MEAS1_START_FORCE = 0x40000
	// Position of SAR1_EN_PAD field.
	RTCADC_MEAS1_CTRL2_SAR1_EN_PAD_Pos = 0x13
	// Bit mask of SAR1_EN_PAD field.
	RTCADC_MEAS1_CTRL2_SAR1_EN_PAD_Msk = 0x7ff80000
	// Position of SAR1_EN_PAD_FORCE field.
	RTCADC_MEAS1_CTRL2_SAR1_EN_PAD_FORCE_Pos = 0x1f
	// Bit mask of SAR1_EN_PAD_FORCE field.
	RTCADC_MEAS1_CTRL2_SAR1_EN_PAD_FORCE_Msk = 0x80000000
	// Bit SAR1_EN_PAD_FORCE.
	RTCADC_MEAS1_CTRL2_SAR1_EN_PAD_FORCE = 0x80000000

	// MEAS1_MUX: SAR ADC1 MUX register.
	// Position of SAR1_DIG_FORCE field.
	RTCADC_MEAS1_MUX_SAR1_DIG_FORCE_Pos = 0x1f
	// Bit mask of SAR1_DIG_FORCE field.
	RTCADC_MEAS1_MUX_SAR1_DIG_FORCE_Msk = 0x80000000
	// Bit SAR1_DIG_FORCE.
	RTCADC_MEAS1_MUX_SAR1_DIG_FORCE = 0x80000000

	// ATTEN1: ADC1 attenuation registers.
	// Position of SAR1_ATTEN field.
	RTCADC_ATTEN1_SAR1_ATTEN_Pos = 0x0
	// Bit mask of SAR1_ATTEN field.
	RTCADC_ATTEN1_SAR1_ATTEN_Msk = 0xffffffff

	// AMP_CTRL1: N/A
	// Position of SAR_AMP_WAIT1 field.
	RTCADC_AMP_CTRL1_SAR_AMP_WAIT1_Pos = 0x0
	// Bit mask of SAR_AMP_WAIT1 field.
	RTCADC_AMP_CTRL1_SAR_AMP_WAIT1_Msk = 0xffff
	// Position of SAR_AMP_WAIT2 field.
	RTCADC_AMP_CTRL1_SAR_AMP_WAIT2_Pos = 0x10
	// Bit mask of SAR_AMP_WAIT2 field.
	RTCADC_AMP_CTRL1_SAR_AMP_WAIT2_Msk = 0xffff0000

	// AMP_CTRL2: N/A
	// Position of SAR1_DAC_XPD_FSM_IDLE field.
	RTCADC_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE_Pos = 0x0
	// Bit mask of SAR1_DAC_XPD_FSM_IDLE field.
	RTCADC_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE_Msk = 0x1
	// Bit SAR1_DAC_XPD_FSM_IDLE.
	RTCADC_AMP_CTRL2_SAR1_DAC_XPD_FSM_IDLE = 0x1
	// Position of XPD_SAR_AMP_FSM_IDLE field.
	RTCADC_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE_Pos = 0x1
	// Bit mask of XPD_SAR_AMP_FSM_IDLE field.
	RTCADC_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE_Msk = 0x2
	// Bit XPD_SAR_AMP_FSM_IDLE.
	RTCADC_AMP_CTRL2_XPD_SAR_AMP_FSM_IDLE = 0x2
	// Position of AMP_RST_FB_FSM_IDLE field.
	RTCADC_AMP_CTRL2_AMP_RST_FB_FSM_IDLE_Pos = 0x2
	// Bit mask of AMP_RST_FB_FSM_IDLE field.
	RTCADC_AMP_CTRL2_AMP_RST_FB_FSM_IDLE_Msk = 0x4
	// Bit AMP_RST_FB_FSM_IDLE.
	RTCADC_AMP_CTRL2_AMP_RST_FB_FSM_IDLE = 0x4
	// Position of AMP_SHORT_REF_FSM_IDLE field.
	RTCADC_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE_Pos = 0x3
	// Bit mask of AMP_SHORT_REF_FSM_IDLE field.
	RTCADC_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE_Msk = 0x8
	// Bit AMP_SHORT_REF_FSM_IDLE.
	RTCADC_AMP_CTRL2_AMP_SHORT_REF_FSM_IDLE = 0x8
	// Position of AMP_SHORT_REF_GND_FSM_IDLE field.
	RTCADC_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE_Pos = 0x4
	// Bit mask of AMP_SHORT_REF_GND_FSM_IDLE field.
	RTCADC_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE_Msk = 0x10
	// Bit AMP_SHORT_REF_GND_FSM_IDLE.
	RTCADC_AMP_CTRL2_AMP_SHORT_REF_GND_FSM_IDLE = 0x10
	// Position of XPD_SAR_FSM_IDLE field.
	RTCADC_AMP_CTRL2_XPD_SAR_FSM_IDLE_Pos = 0x5
	// Bit mask of XPD_SAR_FSM_IDLE field.
	RTCADC_AMP_CTRL2_XPD_SAR_FSM_IDLE_Msk = 0x20
	// Bit XPD_SAR_FSM_IDLE.
	RTCADC_AMP_CTRL2_XPD_SAR_FSM_IDLE = 0x20
	// Position of SAR_RSTB_FSM_IDLE field.
	RTCADC_AMP_CTRL2_SAR_RSTB_FSM_IDLE_Pos = 0x6
	// Bit mask of SAR_RSTB_FSM_IDLE field.
	RTCADC_AMP_CTRL2_SAR_RSTB_FSM_IDLE_Msk = 0x40
	// Bit SAR_RSTB_FSM_IDLE.
	RTCADC_AMP_CTRL2_SAR_RSTB_FSM_IDLE = 0x40
	// Position of SAR_AMP_WAIT3 field.
	RTCADC_AMP_CTRL2_SAR_AMP_WAIT3_Pos = 0x10
	// Bit mask of SAR_AMP_WAIT3 field.
	RTCADC_AMP_CTRL2_SAR_AMP_WAIT3_Msk = 0xffff0000

	// AMP_CTRL3: N/A
	// Position of SAR1_DAC_XPD_FSM field.
	RTCADC_AMP_CTRL3_SAR1_DAC_XPD_FSM_Pos = 0x0
	// Bit mask of SAR1_DAC_XPD_FSM field.
	RTCADC_AMP_CTRL3_SAR1_DAC_XPD_FSM_Msk = 0xf
	// Position of XPD_SAR_AMP_FSM field.
	RTCADC_AMP_CTRL3_XPD_SAR_AMP_FSM_Pos = 0x4
	// Bit mask of XPD_SAR_AMP_FSM field.
	RTCADC_AMP_CTRL3_XPD_SAR_AMP_FSM_Msk = 0xf0
	// Position of AMP_RST_FB_FSM field.
	RTCADC_AMP_CTRL3_AMP_RST_FB_FSM_Pos = 0x8
	// Bit mask of AMP_RST_FB_FSM field.
	RTCADC_AMP_CTRL3_AMP_RST_FB_FSM_Msk = 0xf00
	// Position of AMP_SHORT_REF_FSM field.
	RTCADC_AMP_CTRL3_AMP_SHORT_REF_FSM_Pos = 0xc
	// Bit mask of AMP_SHORT_REF_FSM field.
	RTCADC_AMP_CTRL3_AMP_SHORT_REF_FSM_Msk = 0xf000
	// Position of AMP_SHORT_REF_GND_FSM field.
	RTCADC_AMP_CTRL3_AMP_SHORT_REF_GND_FSM_Pos = 0x10
	// Bit mask of AMP_SHORT_REF_GND_FSM field.
	RTCADC_AMP_CTRL3_AMP_SHORT_REF_GND_FSM_Msk = 0xf0000
	// Position of XPD_SAR_FSM field.
	RTCADC_AMP_CTRL3_XPD_SAR_FSM_Pos = 0x14
	// Bit mask of XPD_SAR_FSM field.
	RTCADC_AMP_CTRL3_XPD_SAR_FSM_Msk = 0xf00000
	// Position of SAR_RSTB_FSM field.
	RTCADC_AMP_CTRL3_SAR_RSTB_FSM_Pos = 0x18
	// Bit mask of SAR_RSTB_FSM field.
	RTCADC_AMP_CTRL3_SAR_RSTB_FSM_Msk = 0xf000000

	// READER2_CTRL: Control the read operation of ADC2.
	// Position of SAR2_CLK_DIV field.
	RTCADC_READER2_CTRL_SAR2_CLK_DIV_Pos = 0x0
	// Bit mask of SAR2_CLK_DIV field.
	RTCADC_READER2_CTRL_SAR2_CLK_DIV_Msk = 0xff
	// Position of SAR2_WAIT_ARB_CYCLE field.
	RTCADC_READER2_CTRL_SAR2_WAIT_ARB_CYCLE_Pos = 0x10
	// Bit mask of SAR2_WAIT_ARB_CYCLE field.
	RTCADC_READER2_CTRL_SAR2_WAIT_ARB_CYCLE_Msk = 0x30000
	// Position of SAR2_CLK_GATED field.
	RTCADC_READER2_CTRL_SAR2_CLK_GATED_Pos = 0x12
	// Bit mask of SAR2_CLK_GATED field.
	RTCADC_READER2_CTRL_SAR2_CLK_GATED_Msk = 0x40000
	// Bit SAR2_CLK_GATED.
	RTCADC_READER2_CTRL_SAR2_CLK_GATED = 0x40000
	// Position of SAR2_SAMPLE_NUM field.
	RTCADC_READER2_CTRL_SAR2_SAMPLE_NUM_Pos = 0x13
	// Bit mask of SAR2_SAMPLE_NUM field.
	RTCADC_READER2_CTRL_SAR2_SAMPLE_NUM_Msk = 0x7f80000
	// Position of SAR2_EN_PAD_FORCE_ENABLE field.
	RTCADC_READER2_CTRL_SAR2_EN_PAD_FORCE_ENABLE_Pos = 0x1b
	// Bit mask of SAR2_EN_PAD_FORCE_ENABLE field.
	RTCADC_READER2_CTRL_SAR2_EN_PAD_FORCE_ENABLE_Msk = 0x18000000
	// Position of SAR2_DATA_INV field.
	RTCADC_READER2_CTRL_SAR2_DATA_INV_Pos = 0x1d
	// Bit mask of SAR2_DATA_INV field.
	RTCADC_READER2_CTRL_SAR2_DATA_INV_Msk = 0x20000000
	// Bit SAR2_DATA_INV.
	RTCADC_READER2_CTRL_SAR2_DATA_INV = 0x20000000
	// Position of SAR2_INT_EN field.
	RTCADC_READER2_CTRL_SAR2_INT_EN_Pos = 0x1e
	// Bit mask of SAR2_INT_EN field.
	RTCADC_READER2_CTRL_SAR2_INT_EN_Msk = 0x40000000
	// Bit SAR2_INT_EN.
	RTCADC_READER2_CTRL_SAR2_INT_EN = 0x40000000

	// READER2_STATUS: N/A
	// Position of SAR2_READER_STATUS field.
	RTCADC_READER2_STATUS_SAR2_READER_STATUS_Pos = 0x0
	// Bit mask of SAR2_READER_STATUS field.
	RTCADC_READER2_STATUS_SAR2_READER_STATUS_Msk = 0xffffffff

	// MEAS2_CTRL1: ADC2 configuration registers.
	// Position of SAR2_CNTL_STATE field.
	RTCADC_MEAS2_CTRL1_SAR2_CNTL_STATE_Pos = 0x0
	// Bit mask of SAR2_CNTL_STATE field.
	RTCADC_MEAS2_CTRL1_SAR2_CNTL_STATE_Msk = 0x7
	// Position of SAR2_PWDET_CAL_EN field.
	RTCADC_MEAS2_CTRL1_SAR2_PWDET_CAL_EN_Pos = 0x3
	// Bit mask of SAR2_PWDET_CAL_EN field.
	RTCADC_MEAS2_CTRL1_SAR2_PWDET_CAL_EN_Msk = 0x8
	// Bit SAR2_PWDET_CAL_EN.
	RTCADC_MEAS2_CTRL1_SAR2_PWDET_CAL_EN = 0x8
	// Position of SAR2_PKDET_CAL_EN field.
	RTCADC_MEAS2_CTRL1_SAR2_PKDET_CAL_EN_Pos = 0x4
	// Bit mask of SAR2_PKDET_CAL_EN field.
	RTCADC_MEAS2_CTRL1_SAR2_PKDET_CAL_EN_Msk = 0x10
	// Bit SAR2_PKDET_CAL_EN.
	RTCADC_MEAS2_CTRL1_SAR2_PKDET_CAL_EN = 0x10
	// Position of SAR2_EN_TEST field.
	RTCADC_MEAS2_CTRL1_SAR2_EN_TEST_Pos = 0x5
	// Bit mask of SAR2_EN_TEST field.
	RTCADC_MEAS2_CTRL1_SAR2_EN_TEST_Msk = 0x20
	// Bit SAR2_EN_TEST.
	RTCADC_MEAS2_CTRL1_SAR2_EN_TEST = 0x20
	// Position of SAR2_RSTB_FORCE field.
	RTCADC_MEAS2_CTRL1_SAR2_RSTB_FORCE_Pos = 0x6
	// Bit mask of SAR2_RSTB_FORCE field.
	RTCADC_MEAS2_CTRL1_SAR2_RSTB_FORCE_Msk = 0xc0
	// Position of SAR2_STANDBY_WAIT field.
	RTCADC_MEAS2_CTRL1_SAR2_STANDBY_WAIT_Pos = 0x8
	// Bit mask of SAR2_STANDBY_WAIT field.
	RTCADC_MEAS2_CTRL1_SAR2_STANDBY_WAIT_Msk = 0xff00
	// Position of SAR2_RSTB_WAIT field.
	RTCADC_MEAS2_CTRL1_SAR2_RSTB_WAIT_Pos = 0x10
	// Bit mask of SAR2_RSTB_WAIT field.
	RTCADC_MEAS2_CTRL1_SAR2_RSTB_WAIT_Msk = 0xff0000
	// Position of SAR2_XPD_WAIT field.
	RTCADC_MEAS2_CTRL1_SAR2_XPD_WAIT_Pos = 0x18
	// Bit mask of SAR2_XPD_WAIT field.
	RTCADC_MEAS2_CTRL1_SAR2_XPD_WAIT_Msk = 0xff000000

	// MEAS2_CTRL2: ADC2 configuration registers.
	// Position of MEAS2_DATA_SAR field.
	RTCADC_MEAS2_CTRL2_MEAS2_DATA_SAR_Pos = 0x0
	// Bit mask of MEAS2_DATA_SAR field.
	RTCADC_MEAS2_CTRL2_MEAS2_DATA_SAR_Msk = 0xffff
	// Position of MEAS2_DONE_SAR field.
	RTCADC_MEAS2_CTRL2_MEAS2_DONE_SAR_Pos = 0x10
	// Bit mask of MEAS2_DONE_SAR field.
	RTCADC_MEAS2_CTRL2_MEAS2_DONE_SAR_Msk = 0x10000
	// Bit MEAS2_DONE_SAR.
	RTCADC_MEAS2_CTRL2_MEAS2_DONE_SAR = 0x10000
	// Position of MEAS2_START_SAR field.
	RTCADC_MEAS2_CTRL2_MEAS2_START_SAR_Pos = 0x11
	// Bit mask of MEAS2_START_SAR field.
	RTCADC_MEAS2_CTRL2_MEAS2_START_SAR_Msk = 0x20000
	// Bit MEAS2_START_SAR.
	RTCADC_MEAS2_CTRL2_MEAS2_START_SAR = 0x20000
	// Position of MEAS2_START_FORCE field.
	RTCADC_MEAS2_CTRL2_MEAS2_START_FORCE_Pos = 0x12
	// Bit mask of MEAS2_START_FORCE field.
	RTCADC_MEAS2_CTRL2_MEAS2_START_FORCE_Msk = 0x40000
	// Bit MEAS2_START_FORCE.
	RTCADC_MEAS2_CTRL2_MEAS2_START_FORCE = 0x40000
	// Position of SAR2_EN_PAD field.
	RTCADC_MEAS2_CTRL2_SAR2_EN_PAD_Pos = 0x13
	// Bit mask of SAR2_EN_PAD field.
	RTCADC_MEAS2_CTRL2_SAR2_EN_PAD_Msk = 0x7ff80000
	// Position of SAR2_EN_PAD_FORCE field.
	RTCADC_MEAS2_CTRL2_SAR2_EN_PAD_FORCE_Pos = 0x1f
	// Bit mask of SAR2_EN_PAD_FORCE field.
	RTCADC_MEAS2_CTRL2_SAR2_EN_PAD_FORCE_Msk = 0x80000000
	// Bit SAR2_EN_PAD_FORCE.
	RTCADC_MEAS2_CTRL2_SAR2_EN_PAD_FORCE = 0x80000000

	// MEAS2_MUX: SAR ADC2 MUX register.
	// Position of SAR2_PWDET_CCT field.
	RTCADC_MEAS2_MUX_SAR2_PWDET_CCT_Pos = 0x1c
	// Bit mask of SAR2_PWDET_CCT field.
	RTCADC_MEAS2_MUX_SAR2_PWDET_CCT_Msk = 0x70000000
	// Position of SAR2_RTC_FORCE field.
	RTCADC_MEAS2_MUX_SAR2_RTC_FORCE_Pos = 0x1f
	// Bit mask of SAR2_RTC_FORCE field.
	RTCADC_MEAS2_MUX_SAR2_RTC_FORCE_Msk = 0x80000000
	// Bit SAR2_RTC_FORCE.
	RTCADC_MEAS2_MUX_SAR2_RTC_FORCE = 0x80000000

	// ATTEN2: ADC1 attenuation registers.
	// Position of SAR2_ATTEN field.
	RTCADC_ATTEN2_SAR2_ATTEN_Pos = 0x0
	// Bit mask of SAR2_ATTEN field.
	RTCADC_ATTEN2_SAR2_ATTEN_Msk = 0xffffffff

	// FORCE_WPD_SAR: In sleep, force to use rtc to control ADC
	// Position of FORCE_XPD_SAR1 field.
	RTCADC_FORCE_WPD_SAR_FORCE_XPD_SAR1_Pos = 0x0
	// Bit mask of FORCE_XPD_SAR1 field.
	RTCADC_FORCE_WPD_SAR_FORCE_XPD_SAR1_Msk = 0x3
	// Position of FORCE_XPD_SAR2 field.
	RTCADC_FORCE_WPD_SAR_FORCE_XPD_SAR2_Pos = 0x2
	// Bit mask of FORCE_XPD_SAR2 field.
	RTCADC_FORCE_WPD_SAR_FORCE_XPD_SAR2_Msk = 0xc

	// MEAS_STATUS: N/A
	// Position of SARADC_MEAS_STATUS field.
	RTCADC_MEAS_STATUS_SARADC_MEAS_STATUS_Pos = 0x0
	// Bit mask of SARADC_MEAS_STATUS field.
	RTCADC_MEAS_STATUS_SARADC_MEAS_STATUS_Msk = 0xff

	// REG_CLKEN: N/A
	// Position of CLK_EN field.
	RTCADC_REG_CLKEN_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	RTCADC_REG_CLKEN_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	RTCADC_REG_CLKEN_CLK_EN = 0x1

	// COCPU_INT_RAW: Interrupt raw registers.
	// Position of COCPU_SARADC1_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW_Pos = 0x0
	// Bit mask of COCPU_SARADC1_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW_Msk = 0x1
	// Bit COCPU_SARADC1_INT_RAW.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_INT_RAW = 0x1
	// Position of COCPU_SARADC2_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW_Pos = 0x1
	// Bit mask of COCPU_SARADC2_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW_Msk = 0x2
	// Bit COCPU_SARADC2_INT_RAW.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_INT_RAW = 0x2
	// Position of COCPU_SARADC1_ERROR_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_ERROR_INT_RAW_Pos = 0x2
	// Bit mask of COCPU_SARADC1_ERROR_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_ERROR_INT_RAW_Msk = 0x4
	// Bit COCPU_SARADC1_ERROR_INT_RAW.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_ERROR_INT_RAW = 0x4
	// Position of COCPU_SARADC2_ERROR_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_ERROR_INT_RAW_Pos = 0x3
	// Bit mask of COCPU_SARADC2_ERROR_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_ERROR_INT_RAW_Msk = 0x8
	// Bit COCPU_SARADC2_ERROR_INT_RAW.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_ERROR_INT_RAW = 0x8
	// Position of COCPU_SARADC1_WAKE_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_WAKE_INT_RAW_Pos = 0x4
	// Bit mask of COCPU_SARADC1_WAKE_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_WAKE_INT_RAW_Msk = 0x10
	// Bit COCPU_SARADC1_WAKE_INT_RAW.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC1_WAKE_INT_RAW = 0x10
	// Position of COCPU_SARADC2_WAKE_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_WAKE_INT_RAW_Pos = 0x5
	// Bit mask of COCPU_SARADC2_WAKE_INT_RAW field.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_WAKE_INT_RAW_Msk = 0x20
	// Bit COCPU_SARADC2_WAKE_INT_RAW.
	RTCADC_COCPU_INT_RAW_COCPU_SARADC2_WAKE_INT_RAW = 0x20

	// INT_ENA: Interrupt enable registers.
	// Position of COCPU_SARADC1_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC1_INT_ENA_Pos = 0x0
	// Bit mask of COCPU_SARADC1_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC1_INT_ENA_Msk = 0x1
	// Bit COCPU_SARADC1_INT_ENA.
	RTCADC_INT_ENA_COCPU_SARADC1_INT_ENA = 0x1
	// Position of COCPU_SARADC2_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC2_INT_ENA_Pos = 0x1
	// Bit mask of COCPU_SARADC2_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC2_INT_ENA_Msk = 0x2
	// Bit COCPU_SARADC2_INT_ENA.
	RTCADC_INT_ENA_COCPU_SARADC2_INT_ENA = 0x2
	// Position of COCPU_SARADC1_ERROR_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC1_ERROR_INT_ENA_Pos = 0x2
	// Bit mask of COCPU_SARADC1_ERROR_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC1_ERROR_INT_ENA_Msk = 0x4
	// Bit COCPU_SARADC1_ERROR_INT_ENA.
	RTCADC_INT_ENA_COCPU_SARADC1_ERROR_INT_ENA = 0x4
	// Position of COCPU_SARADC2_ERROR_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC2_ERROR_INT_ENA_Pos = 0x3
	// Bit mask of COCPU_SARADC2_ERROR_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC2_ERROR_INT_ENA_Msk = 0x8
	// Bit COCPU_SARADC2_ERROR_INT_ENA.
	RTCADC_INT_ENA_COCPU_SARADC2_ERROR_INT_ENA = 0x8
	// Position of COCPU_SARADC1_WAKE_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC1_WAKE_INT_ENA_Pos = 0x4
	// Bit mask of COCPU_SARADC1_WAKE_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC1_WAKE_INT_ENA_Msk = 0x10
	// Bit COCPU_SARADC1_WAKE_INT_ENA.
	RTCADC_INT_ENA_COCPU_SARADC1_WAKE_INT_ENA = 0x10
	// Position of COCPU_SARADC2_WAKE_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC2_WAKE_INT_ENA_Pos = 0x5
	// Bit mask of COCPU_SARADC2_WAKE_INT_ENA field.
	RTCADC_INT_ENA_COCPU_SARADC2_WAKE_INT_ENA_Msk = 0x20
	// Bit COCPU_SARADC2_WAKE_INT_ENA.
	RTCADC_INT_ENA_COCPU_SARADC2_WAKE_INT_ENA = 0x20

	// INT_ST: Interrupt status registers.
	// Position of COCPU_SARADC1_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC1_INT_ST_Pos = 0x0
	// Bit mask of COCPU_SARADC1_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC1_INT_ST_Msk = 0x1
	// Bit COCPU_SARADC1_INT_ST.
	RTCADC_INT_ST_COCPU_SARADC1_INT_ST = 0x1
	// Position of COCPU_SARADC2_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC2_INT_ST_Pos = 0x1
	// Bit mask of COCPU_SARADC2_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC2_INT_ST_Msk = 0x2
	// Bit COCPU_SARADC2_INT_ST.
	RTCADC_INT_ST_COCPU_SARADC2_INT_ST = 0x2
	// Position of COCPU_SARADC1_ERROR_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC1_ERROR_INT_ST_Pos = 0x2
	// Bit mask of COCPU_SARADC1_ERROR_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC1_ERROR_INT_ST_Msk = 0x4
	// Bit COCPU_SARADC1_ERROR_INT_ST.
	RTCADC_INT_ST_COCPU_SARADC1_ERROR_INT_ST = 0x4
	// Position of COCPU_SARADC2_ERROR_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC2_ERROR_INT_ST_Pos = 0x3
	// Bit mask of COCPU_SARADC2_ERROR_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC2_ERROR_INT_ST_Msk = 0x8
	// Bit COCPU_SARADC2_ERROR_INT_ST.
	RTCADC_INT_ST_COCPU_SARADC2_ERROR_INT_ST = 0x8
	// Position of COCPU_SARADC1_WAKE_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC1_WAKE_INT_ST_Pos = 0x4
	// Bit mask of COCPU_SARADC1_WAKE_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC1_WAKE_INT_ST_Msk = 0x10
	// Bit COCPU_SARADC1_WAKE_INT_ST.
	RTCADC_INT_ST_COCPU_SARADC1_WAKE_INT_ST = 0x10
	// Position of COCPU_SARADC2_WAKE_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC2_WAKE_INT_ST_Pos = 0x5
	// Bit mask of COCPU_SARADC2_WAKE_INT_ST field.
	RTCADC_INT_ST_COCPU_SARADC2_WAKE_INT_ST_Msk = 0x20
	// Bit COCPU_SARADC2_WAKE_INT_ST.
	RTCADC_INT_ST_COCPU_SARADC2_WAKE_INT_ST = 0x20

	// INT_CLR: Interrupt clear registers.
	// Position of COCPU_SARADC1_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC1_INT_CLR_Pos = 0x0
	// Bit mask of COCPU_SARADC1_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC1_INT_CLR_Msk = 0x1
	// Bit COCPU_SARADC1_INT_CLR.
	RTCADC_INT_CLR_COCPU_SARADC1_INT_CLR = 0x1
	// Position of COCPU_SARADC2_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC2_INT_CLR_Pos = 0x1
	// Bit mask of COCPU_SARADC2_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC2_INT_CLR_Msk = 0x2
	// Bit COCPU_SARADC2_INT_CLR.
	RTCADC_INT_CLR_COCPU_SARADC2_INT_CLR = 0x2
	// Position of COCPU_SARADC1_ERROR_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC1_ERROR_INT_CLR_Pos = 0x2
	// Bit mask of COCPU_SARADC1_ERROR_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC1_ERROR_INT_CLR_Msk = 0x4
	// Bit COCPU_SARADC1_ERROR_INT_CLR.
	RTCADC_INT_CLR_COCPU_SARADC1_ERROR_INT_CLR = 0x4
	// Position of COCPU_SARADC2_ERROR_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC2_ERROR_INT_CLR_Pos = 0x3
	// Bit mask of COCPU_SARADC2_ERROR_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC2_ERROR_INT_CLR_Msk = 0x8
	// Bit COCPU_SARADC2_ERROR_INT_CLR.
	RTCADC_INT_CLR_COCPU_SARADC2_ERROR_INT_CLR = 0x8
	// Position of COCPU_SARADC1_WAKE_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC1_WAKE_INT_CLR_Pos = 0x4
	// Bit mask of COCPU_SARADC1_WAKE_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC1_WAKE_INT_CLR_Msk = 0x10
	// Bit COCPU_SARADC1_WAKE_INT_CLR.
	RTCADC_INT_CLR_COCPU_SARADC1_WAKE_INT_CLR = 0x10
	// Position of COCPU_SARADC2_WAKE_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC2_WAKE_INT_CLR_Pos = 0x5
	// Bit mask of COCPU_SARADC2_WAKE_INT_CLR field.
	RTCADC_INT_CLR_COCPU_SARADC2_WAKE_INT_CLR_Msk = 0x20
	// Bit COCPU_SARADC2_WAKE_INT_CLR.
	RTCADC_INT_CLR_COCPU_SARADC2_WAKE_INT_CLR = 0x20

	// INT_ENA_W1TS: Interrupt enable assert registers.
	// Position of COCPU_SARADC1_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_INT_ENA_W1TS_Pos = 0x0
	// Bit mask of COCPU_SARADC1_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_INT_ENA_W1TS_Msk = 0x1
	// Bit COCPU_SARADC1_INT_ENA_W1TS.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_INT_ENA_W1TS = 0x1
	// Position of COCPU_SARADC2_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_INT_ENA_W1TS_Pos = 0x1
	// Bit mask of COCPU_SARADC2_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_INT_ENA_W1TS_Msk = 0x2
	// Bit COCPU_SARADC2_INT_ENA_W1TS.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_INT_ENA_W1TS = 0x2
	// Position of COCPU_SARADC1_ERROR_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_ERROR_INT_ENA_W1TS_Pos = 0x2
	// Bit mask of COCPU_SARADC1_ERROR_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_ERROR_INT_ENA_W1TS_Msk = 0x4
	// Bit COCPU_SARADC1_ERROR_INT_ENA_W1TS.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_ERROR_INT_ENA_W1TS = 0x4
	// Position of COCPU_SARADC2_ERROR_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_ERROR_INT_ENA_W1TS_Pos = 0x3
	// Bit mask of COCPU_SARADC2_ERROR_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_ERROR_INT_ENA_W1TS_Msk = 0x8
	// Bit COCPU_SARADC2_ERROR_INT_ENA_W1TS.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_ERROR_INT_ENA_W1TS = 0x8
	// Position of COCPU_SARADC1_WAKE_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_WAKE_INT_ENA_W1TS_Pos = 0x4
	// Bit mask of COCPU_SARADC1_WAKE_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_WAKE_INT_ENA_W1TS_Msk = 0x10
	// Bit COCPU_SARADC1_WAKE_INT_ENA_W1TS.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC1_WAKE_INT_ENA_W1TS = 0x10
	// Position of COCPU_SARADC2_WAKE_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_WAKE_INT_ENA_W1TS_Pos = 0x5
	// Bit mask of COCPU_SARADC2_WAKE_INT_ENA_W1TS field.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_WAKE_INT_ENA_W1TS_Msk = 0x20
	// Bit COCPU_SARADC2_WAKE_INT_ENA_W1TS.
	RTCADC_INT_ENA_W1TS_COCPU_SARADC2_WAKE_INT_ENA_W1TS = 0x20

	// INT_ENA_W1TC: Interrupt enable deassert registers.
	// Position of COCPU_SARADC1_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_INT_ENA_W1TC_Pos = 0x0
	// Bit mask of COCPU_SARADC1_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_INT_ENA_W1TC_Msk = 0x1
	// Bit COCPU_SARADC1_INT_ENA_W1TC.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_INT_ENA_W1TC = 0x1
	// Position of COCPU_SARADC2_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_INT_ENA_W1TC_Pos = 0x1
	// Bit mask of COCPU_SARADC2_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_INT_ENA_W1TC_Msk = 0x2
	// Bit COCPU_SARADC2_INT_ENA_W1TC.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_INT_ENA_W1TC = 0x2
	// Position of COCPU_SARADC1_ERROR_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_Pos = 0x2
	// Bit mask of COCPU_SARADC1_ERROR_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_Msk = 0x4
	// Bit COCPU_SARADC1_ERROR_INT_ENA_W1TC.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_ERROR_INT_ENA_W1TC = 0x4
	// Position of COCPU_SARADC2_ERROR_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_Pos = 0x3
	// Bit mask of COCPU_SARADC2_ERROR_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_Msk = 0x8
	// Bit COCPU_SARADC2_ERROR_INT_ENA_W1TC.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_ERROR_INT_ENA_W1TC = 0x8
	// Position of COCPU_SARADC1_WAKE_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_Pos = 0x4
	// Bit mask of COCPU_SARADC1_WAKE_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_WAKE_INT_ENA_W1TC_Msk = 0x10
	// Bit COCPU_SARADC1_WAKE_INT_ENA_W1TC.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC1_WAKE_INT_ENA_W1TC = 0x10
	// Position of COCPU_SARADC2_WAKE_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_Pos = 0x5
	// Bit mask of COCPU_SARADC2_WAKE_INT_ENA_W1TC field.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_WAKE_INT_ENA_W1TC_Msk = 0x20
	// Bit COCPU_SARADC2_WAKE_INT_ENA_W1TC.
	RTCADC_INT_ENA_W1TC_COCPU_SARADC2_WAKE_INT_ENA_W1TC = 0x20

	// WAKEUP1: ADC1 wakeup configuration registers.
	// Position of SAR1_WAKEUP_TH_LOW field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_TH_LOW_Pos = 0x0
	// Bit mask of SAR1_WAKEUP_TH_LOW field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_TH_LOW_Msk = 0xfff
	// Position of SAR1_WAKEUP_TH_HIGH field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_TH_HIGH_Pos = 0xe
	// Bit mask of SAR1_WAKEUP_TH_HIGH field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_TH_HIGH_Msk = 0x3ffc000
	// Position of SAR1_WAKEUP_OVER_UPPER_TH field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_OVER_UPPER_TH_Pos = 0x1d
	// Bit mask of SAR1_WAKEUP_OVER_UPPER_TH field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_OVER_UPPER_TH_Msk = 0x20000000
	// Bit SAR1_WAKEUP_OVER_UPPER_TH.
	RTCADC_WAKEUP1_SAR1_WAKEUP_OVER_UPPER_TH = 0x20000000
	// Position of SAR1_WAKEUP_EN field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_EN_Pos = 0x1e
	// Bit mask of SAR1_WAKEUP_EN field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_EN_Msk = 0x40000000
	// Bit SAR1_WAKEUP_EN.
	RTCADC_WAKEUP1_SAR1_WAKEUP_EN = 0x40000000
	// Position of SAR1_WAKEUP_MODE field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_MODE_Pos = 0x1f
	// Bit mask of SAR1_WAKEUP_MODE field.
	RTCADC_WAKEUP1_SAR1_WAKEUP_MODE_Msk = 0x80000000
	// Bit SAR1_WAKEUP_MODE.
	RTCADC_WAKEUP1_SAR1_WAKEUP_MODE = 0x80000000

	// WAKEUP2: ADC2 wakeup configuration registers.
	// Position of SAR2_WAKEUP_TH_LOW field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_TH_LOW_Pos = 0x0
	// Bit mask of SAR2_WAKEUP_TH_LOW field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_TH_LOW_Msk = 0xfff
	// Position of SAR2_WAKEUP_TH_HIGH field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_TH_HIGH_Pos = 0xe
	// Bit mask of SAR2_WAKEUP_TH_HIGH field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_TH_HIGH_Msk = 0x3ffc000
	// Position of SAR2_WAKEUP_OVER_UPPER_TH field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_OVER_UPPER_TH_Pos = 0x1d
	// Bit mask of SAR2_WAKEUP_OVER_UPPER_TH field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_OVER_UPPER_TH_Msk = 0x20000000
	// Bit SAR2_WAKEUP_OVER_UPPER_TH.
	RTCADC_WAKEUP2_SAR2_WAKEUP_OVER_UPPER_TH = 0x20000000
	// Position of SAR2_WAKEUP_EN field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_EN_Pos = 0x1e
	// Bit mask of SAR2_WAKEUP_EN field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_EN_Msk = 0x40000000
	// Bit SAR2_WAKEUP_EN.
	RTCADC_WAKEUP2_SAR2_WAKEUP_EN = 0x40000000
	// Position of SAR2_WAKEUP_MODE field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_MODE_Pos = 0x1f
	// Bit mask of SAR2_WAKEUP_MODE field.
	RTCADC_WAKEUP2_SAR2_WAKEUP_MODE_Msk = 0x80000000
	// Bit SAR2_WAKEUP_MODE.
	RTCADC_WAKEUP2_SAR2_WAKEUP_MODE = 0x80000000

	// WAKEUP_SEL: Wakeup source select register.
	// Position of SAR_WAKEUP_SEL field.
	RTCADC_WAKEUP_SEL_SAR_WAKEUP_SEL_Pos = 0x0
	// Bit mask of SAR_WAKEUP_SEL field.
	RTCADC_WAKEUP_SEL_SAR_WAKEUP_SEL_Msk = 0x1
	// Bit SAR_WAKEUP_SEL.
	RTCADC_WAKEUP_SEL_SAR_WAKEUP_SEL = 0x1

	// SAR1_HW_WAKEUP: Hardware automatic sampling registers for wakeup function.
	// Position of ADC1_HW_READ_EN_I field.
	RTCADC_SAR1_HW_WAKEUP_ADC1_HW_READ_EN_I_Pos = 0x0
	// Bit mask of ADC1_HW_READ_EN_I field.
	RTCADC_SAR1_HW_WAKEUP_ADC1_HW_READ_EN_I_Msk = 0x1
	// Bit ADC1_HW_READ_EN_I.
	RTCADC_SAR1_HW_WAKEUP_ADC1_HW_READ_EN_I = 0x1
	// Position of ADC1_HW_READ_RATE_I field.
	RTCADC_SAR1_HW_WAKEUP_ADC1_HW_READ_RATE_I_Pos = 0x1
	// Bit mask of ADC1_HW_READ_RATE_I field.
	RTCADC_SAR1_HW_WAKEUP_ADC1_HW_READ_RATE_I_Msk = 0x1fffe

	// SAR2_HW_WAKEUP: Hardware automatic sampling registers for wakeup function.
	// Position of ADC2_HW_READ_EN_I field.
	RTCADC_SAR2_HW_WAKEUP_ADC2_HW_READ_EN_I_Pos = 0x0
	// Bit mask of ADC2_HW_READ_EN_I field.
	RTCADC_SAR2_HW_WAKEUP_ADC2_HW_READ_EN_I_Msk = 0x1
	// Bit ADC2_HW_READ_EN_I.
	RTCADC_SAR2_HW_WAKEUP_ADC2_HW_READ_EN_I = 0x1
	// Position of ADC2_HW_READ_RATE_I field.
	RTCADC_SAR2_HW_WAKEUP_ADC2_HW_READ_RATE_I_Pos = 0x1
	// Bit mask of ADC2_HW_READ_RATE_I field.
	RTCADC_SAR2_HW_WAKEUP_ADC2_HW_READ_RATE_I_Msk = 0x1fffe

	// RND_ECO_LOW: N/A
	// Position of RND_ECO_LOW field.
	RTCADC_RND_ECO_LOW_RND_ECO_LOW_Pos = 0x0
	// Bit mask of RND_ECO_LOW field.
	RTCADC_RND_ECO_LOW_RND_ECO_LOW_Msk = 0xffffffff

	// RND_ECO_HIGH: N/A
	// Position of RND_ECO_HIGH field.
	RTCADC_RND_ECO_HIGH_RND_ECO_HIGH_Pos = 0x0
	// Bit mask of RND_ECO_HIGH field.
	RTCADC_RND_ECO_HIGH_RND_ECO_HIGH_Msk = 0xffffffff

	// RND_ECO_CS: N/A
	// Position of RND_ECO_EN field.
	RTCADC_RND_ECO_CS_RND_ECO_EN_Pos = 0x0
	// Bit mask of RND_ECO_EN field.
	RTCADC_RND_ECO_CS_RND_ECO_EN_Msk = 0x1
	// Bit RND_ECO_EN.
	RTCADC_RND_ECO_CS_RND_ECO_EN = 0x1
	// Position of RND_ECO_RESULT field.
	RTCADC_RND_ECO_CS_RND_ECO_RESULT_Pos = 0x1
	// Bit mask of RND_ECO_RESULT field.
	RTCADC_RND_ECO_CS_RND_ECO_RESULT_Msk = 0x2
	// Bit RND_ECO_RESULT.
	RTCADC_RND_ECO_CS_RND_ECO_RESULT = 0x2
)

// Constants for LP_TIMER: Low-power Timer
const (
	// TAR0_LOW: need_des
	// Position of MAIN_TIMER_TAR_LOW0 field.
	RTC_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Pos = 0x0
	// Bit mask of MAIN_TIMER_TAR_LOW0 field.
	RTC_TIMER_TAR0_LOW_MAIN_TIMER_TAR_LOW0_Msk = 0xffffffff

	// TAR0_HIGH: need_des
	// Position of MAIN_TIMER_TAR_HIGH0 field.
	RTC_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Pos = 0x0
	// Bit mask of MAIN_TIMER_TAR_HIGH0 field.
	RTC_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_HIGH0_Msk = 0xffff
	// Position of MAIN_TIMER_TAR_EN0 field.
	RTC_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Pos = 0x1f
	// Bit mask of MAIN_TIMER_TAR_EN0 field.
	RTC_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0_Msk = 0x80000000
	// Bit MAIN_TIMER_TAR_EN0.
	RTC_TIMER_TAR0_HIGH_MAIN_TIMER_TAR_EN0 = 0x80000000

	// TAR1_LOW: need_des
	// Position of MAIN_TIMER_TAR_LOW1 field.
	RTC_TIMER_TAR1_LOW_MAIN_TIMER_TAR_LOW1_Pos = 0x0
	// Bit mask of MAIN_TIMER_TAR_LOW1 field.
	RTC_TIMER_TAR1_LOW_MAIN_TIMER_TAR_LOW1_Msk = 0xffffffff

	// TAR1_HIGH: need_des
	// Position of MAIN_TIMER_TAR_HIGH1 field.
	RTC_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_HIGH1_Pos = 0x0
	// Bit mask of MAIN_TIMER_TAR_HIGH1 field.
	RTC_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_HIGH1_Msk = 0xffff
	// Position of MAIN_TIMER_TAR_EN1 field.
	RTC_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1_Pos = 0x1f
	// Bit mask of MAIN_TIMER_TAR_EN1 field.
	RTC_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1_Msk = 0x80000000
	// Bit MAIN_TIMER_TAR_EN1.
	RTC_TIMER_TAR1_HIGH_MAIN_TIMER_TAR_EN1 = 0x80000000

	// UPDATE: need_des
	// Position of MAIN_TIMER_UPDATE field.
	RTC_TIMER_UPDATE_MAIN_TIMER_UPDATE_Pos = 0x1c
	// Bit mask of MAIN_TIMER_UPDATE field.
	RTC_TIMER_UPDATE_MAIN_TIMER_UPDATE_Msk = 0x10000000
	// Bit MAIN_TIMER_UPDATE.
	RTC_TIMER_UPDATE_MAIN_TIMER_UPDATE = 0x10000000
	// Position of MAIN_TIMER_XTAL_OFF field.
	RTC_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Pos = 0x1d
	// Bit mask of MAIN_TIMER_XTAL_OFF field.
	RTC_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF_Msk = 0x20000000
	// Bit MAIN_TIMER_XTAL_OFF.
	RTC_TIMER_UPDATE_MAIN_TIMER_XTAL_OFF = 0x20000000
	// Position of MAIN_TIMER_SYS_STALL field.
	RTC_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Pos = 0x1e
	// Bit mask of MAIN_TIMER_SYS_STALL field.
	RTC_TIMER_UPDATE_MAIN_TIMER_SYS_STALL_Msk = 0x40000000
	// Bit MAIN_TIMER_SYS_STALL.
	RTC_TIMER_UPDATE_MAIN_TIMER_SYS_STALL = 0x40000000
	// Position of MAIN_TIMER_SYS_RST field.
	RTC_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Pos = 0x1f
	// Bit mask of MAIN_TIMER_SYS_RST field.
	RTC_TIMER_UPDATE_MAIN_TIMER_SYS_RST_Msk = 0x80000000
	// Bit MAIN_TIMER_SYS_RST.
	RTC_TIMER_UPDATE_MAIN_TIMER_SYS_RST = 0x80000000

	// MAIN_BUF0_LOW: need_des
	// Position of MAIN_TIMER_BUF0_LOW field.
	RTC_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Pos = 0x0
	// Bit mask of MAIN_TIMER_BUF0_LOW field.
	RTC_TIMER_MAIN_BUF0_LOW_MAIN_TIMER_BUF0_LOW_Msk = 0xffffffff

	// MAIN_BUF0_HIGH: need_des
	// Position of MAIN_TIMER_BUF0_HIGH field.
	RTC_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Pos = 0x0
	// Bit mask of MAIN_TIMER_BUF0_HIGH field.
	RTC_TIMER_MAIN_BUF0_HIGH_MAIN_TIMER_BUF0_HIGH_Msk = 0xffff

	// MAIN_BUF1_LOW: need_des
	// Position of MAIN_TIMER_BUF1_LOW field.
	RTC_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Pos = 0x0
	// Bit mask of MAIN_TIMER_BUF1_LOW field.
	RTC_TIMER_MAIN_BUF1_LOW_MAIN_TIMER_BUF1_LOW_Msk = 0xffffffff

	// MAIN_BUF1_HIGH: need_des
	// Position of MAIN_TIMER_BUF1_HIGH field.
	RTC_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Pos = 0x0
	// Bit mask of MAIN_TIMER_BUF1_HIGH field.
	RTC_TIMER_MAIN_BUF1_HIGH_MAIN_TIMER_BUF1_HIGH_Msk = 0xffff

	// MAIN_OVERFLOW: need_des
	// Position of MAIN_TIMER_ALARM_LOAD field.
	RTC_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Pos = 0x1f
	// Bit mask of MAIN_TIMER_ALARM_LOAD field.
	RTC_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD_Msk = 0x80000000
	// Bit MAIN_TIMER_ALARM_LOAD.
	RTC_TIMER_MAIN_OVERFLOW_MAIN_TIMER_ALARM_LOAD = 0x80000000

	// INT_RAW: need_des
	// Position of OVERFLOW_RAW field.
	RTC_TIMER_INT_RAW_OVERFLOW_RAW_Pos = 0x1e
	// Bit mask of OVERFLOW_RAW field.
	RTC_TIMER_INT_RAW_OVERFLOW_RAW_Msk = 0x40000000
	// Bit OVERFLOW_RAW.
	RTC_TIMER_INT_RAW_OVERFLOW_RAW = 0x40000000
	// Position of SOC_WAKEUP_INT_RAW field.
	RTC_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_RAW field.
	RTC_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_RAW.
	RTC_TIMER_INT_RAW_SOC_WAKEUP_INT_RAW = 0x80000000

	// INT_ST: need_des
	// Position of OVERFLOW_ST field.
	RTC_TIMER_INT_ST_OVERFLOW_ST_Pos = 0x1e
	// Bit mask of OVERFLOW_ST field.
	RTC_TIMER_INT_ST_OVERFLOW_ST_Msk = 0x40000000
	// Bit OVERFLOW_ST.
	RTC_TIMER_INT_ST_OVERFLOW_ST = 0x40000000
	// Position of SOC_WAKEUP_INT_ST field.
	RTC_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_ST field.
	RTC_TIMER_INT_ST_SOC_WAKEUP_INT_ST_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_ST.
	RTC_TIMER_INT_ST_SOC_WAKEUP_INT_ST = 0x80000000

	// INT_ENA: need_des
	// Position of OVERFLOW_ENA field.
	RTC_TIMER_INT_ENA_OVERFLOW_ENA_Pos = 0x1e
	// Bit mask of OVERFLOW_ENA field.
	RTC_TIMER_INT_ENA_OVERFLOW_ENA_Msk = 0x40000000
	// Bit OVERFLOW_ENA.
	RTC_TIMER_INT_ENA_OVERFLOW_ENA = 0x40000000
	// Position of SOC_WAKEUP_INT_ENA field.
	RTC_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_ENA field.
	RTC_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_ENA.
	RTC_TIMER_INT_ENA_SOC_WAKEUP_INT_ENA = 0x80000000

	// INT_CLR: need_des
	// Position of OVERFLOW_CLR field.
	RTC_TIMER_INT_CLR_OVERFLOW_CLR_Pos = 0x1e
	// Bit mask of OVERFLOW_CLR field.
	RTC_TIMER_INT_CLR_OVERFLOW_CLR_Msk = 0x40000000
	// Bit OVERFLOW_CLR.
	RTC_TIMER_INT_CLR_OVERFLOW_CLR = 0x40000000
	// Position of SOC_WAKEUP_INT_CLR field.
	RTC_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Pos = 0x1f
	// Bit mask of SOC_WAKEUP_INT_CLR field.
	RTC_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR_Msk = 0x80000000
	// Bit SOC_WAKEUP_INT_CLR.
	RTC_TIMER_INT_CLR_SOC_WAKEUP_INT_CLR = 0x80000000

	// LP_INT_RAW: need_des
	// Position of MAIN_TIMER_OVERFLOW_LP_INT_RAW field.
	RTC_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW_Pos = 0x1e
	// Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_RAW field.
	RTC_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW_Msk = 0x40000000
	// Bit MAIN_TIMER_OVERFLOW_LP_INT_RAW.
	RTC_TIMER_LP_INT_RAW_MAIN_TIMER_OVERFLOW_LP_INT_RAW = 0x40000000
	// Position of MAIN_TIMER_LP_INT_RAW field.
	RTC_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW_Pos = 0x1f
	// Bit mask of MAIN_TIMER_LP_INT_RAW field.
	RTC_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW_Msk = 0x80000000
	// Bit MAIN_TIMER_LP_INT_RAW.
	RTC_TIMER_LP_INT_RAW_MAIN_TIMER_LP_INT_RAW = 0x80000000

	// LP_INT_ST: need_des
	// Position of MAIN_TIMER_OVERFLOW_LP_INT_ST field.
	RTC_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST_Pos = 0x1e
	// Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_ST field.
	RTC_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST_Msk = 0x40000000
	// Bit MAIN_TIMER_OVERFLOW_LP_INT_ST.
	RTC_TIMER_LP_INT_ST_MAIN_TIMER_OVERFLOW_LP_INT_ST = 0x40000000
	// Position of MAIN_TIMER_LP_INT_ST field.
	RTC_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST_Pos = 0x1f
	// Bit mask of MAIN_TIMER_LP_INT_ST field.
	RTC_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST_Msk = 0x80000000
	// Bit MAIN_TIMER_LP_INT_ST.
	RTC_TIMER_LP_INT_ST_MAIN_TIMER_LP_INT_ST = 0x80000000

	// LP_INT_ENA: need_des
	// Position of MAIN_TIMER_OVERFLOW_LP_INT_ENA field.
	RTC_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA_Pos = 0x1e
	// Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_ENA field.
	RTC_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA_Msk = 0x40000000
	// Bit MAIN_TIMER_OVERFLOW_LP_INT_ENA.
	RTC_TIMER_LP_INT_ENA_MAIN_TIMER_OVERFLOW_LP_INT_ENA = 0x40000000
	// Position of MAIN_TIMER_LP_INT_ENA field.
	RTC_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA_Pos = 0x1f
	// Bit mask of MAIN_TIMER_LP_INT_ENA field.
	RTC_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA_Msk = 0x80000000
	// Bit MAIN_TIMER_LP_INT_ENA.
	RTC_TIMER_LP_INT_ENA_MAIN_TIMER_LP_INT_ENA = 0x80000000

	// LP_INT_CLR: need_des
	// Position of MAIN_TIMER_OVERFLOW_LP_INT_CLR field.
	RTC_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR_Pos = 0x1e
	// Bit mask of MAIN_TIMER_OVERFLOW_LP_INT_CLR field.
	RTC_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR_Msk = 0x40000000
	// Bit MAIN_TIMER_OVERFLOW_LP_INT_CLR.
	RTC_TIMER_LP_INT_CLR_MAIN_TIMER_OVERFLOW_LP_INT_CLR = 0x40000000
	// Position of MAIN_TIMER_LP_INT_CLR field.
	RTC_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR_Pos = 0x1f
	// Bit mask of MAIN_TIMER_LP_INT_CLR field.
	RTC_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR_Msk = 0x80000000
	// Bit MAIN_TIMER_LP_INT_CLR.
	RTC_TIMER_LP_INT_CLR_MAIN_TIMER_LP_INT_CLR = 0x80000000

	// DATE: need_des
	// Position of DATE field.
	RTC_TIMER_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	RTC_TIMER_DATE_DATE_Msk = 0x7fffffff
	// Position of CLK_EN field.
	RTC_TIMER_DATE_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	RTC_TIMER_DATE_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	RTC_TIMER_DATE_CLK_EN = 0x80000000
)

// Constants for LP_TOUCH: LP_TOUCH Peripheral
const (
	// INT_RAW: need_des
	// Position of SCAN_DONE_INT_RAW field.
	RTC_TOUCH_INT_RAW_SCAN_DONE_INT_RAW_Pos = 0x0
	// Bit mask of SCAN_DONE_INT_RAW field.
	RTC_TOUCH_INT_RAW_SCAN_DONE_INT_RAW_Msk = 0x1
	// Bit SCAN_DONE_INT_RAW.
	RTC_TOUCH_INT_RAW_SCAN_DONE_INT_RAW = 0x1
	// Position of DONE_INT_RAW field.
	RTC_TOUCH_INT_RAW_DONE_INT_RAW_Pos = 0x1
	// Bit mask of DONE_INT_RAW field.
	RTC_TOUCH_INT_RAW_DONE_INT_RAW_Msk = 0x2
	// Bit DONE_INT_RAW.
	RTC_TOUCH_INT_RAW_DONE_INT_RAW = 0x2
	// Position of ACTIVE_INT_RAW field.
	RTC_TOUCH_INT_RAW_ACTIVE_INT_RAW_Pos = 0x2
	// Bit mask of ACTIVE_INT_RAW field.
	RTC_TOUCH_INT_RAW_ACTIVE_INT_RAW_Msk = 0x4
	// Bit ACTIVE_INT_RAW.
	RTC_TOUCH_INT_RAW_ACTIVE_INT_RAW = 0x4
	// Position of INACTIVE_INT_RAW field.
	RTC_TOUCH_INT_RAW_INACTIVE_INT_RAW_Pos = 0x3
	// Bit mask of INACTIVE_INT_RAW field.
	RTC_TOUCH_INT_RAW_INACTIVE_INT_RAW_Msk = 0x8
	// Bit INACTIVE_INT_RAW.
	RTC_TOUCH_INT_RAW_INACTIVE_INT_RAW = 0x8
	// Position of TIMEOUT_INT_RAW field.
	RTC_TOUCH_INT_RAW_TIMEOUT_INT_RAW_Pos = 0x4
	// Bit mask of TIMEOUT_INT_RAW field.
	RTC_TOUCH_INT_RAW_TIMEOUT_INT_RAW_Msk = 0x10
	// Bit TIMEOUT_INT_RAW.
	RTC_TOUCH_INT_RAW_TIMEOUT_INT_RAW = 0x10
	// Position of APPROACH_LOOP_DONE_INT_RAW field.
	RTC_TOUCH_INT_RAW_APPROACH_LOOP_DONE_INT_RAW_Pos = 0x5
	// Bit mask of APPROACH_LOOP_DONE_INT_RAW field.
	RTC_TOUCH_INT_RAW_APPROACH_LOOP_DONE_INT_RAW_Msk = 0x20
	// Bit APPROACH_LOOP_DONE_INT_RAW.
	RTC_TOUCH_INT_RAW_APPROACH_LOOP_DONE_INT_RAW = 0x20

	// INT_ST: need_des
	// Position of SCAN_DONE_INT_ST field.
	RTC_TOUCH_INT_ST_SCAN_DONE_INT_ST_Pos = 0x0
	// Bit mask of SCAN_DONE_INT_ST field.
	RTC_TOUCH_INT_ST_SCAN_DONE_INT_ST_Msk = 0x1
	// Bit SCAN_DONE_INT_ST.
	RTC_TOUCH_INT_ST_SCAN_DONE_INT_ST = 0x1
	// Position of DONE_INT_ST field.
	RTC_TOUCH_INT_ST_DONE_INT_ST_Pos = 0x1
	// Bit mask of DONE_INT_ST field.
	RTC_TOUCH_INT_ST_DONE_INT_ST_Msk = 0x2
	// Bit DONE_INT_ST.
	RTC_TOUCH_INT_ST_DONE_INT_ST = 0x2
	// Position of ACTIVE_INT_ST field.
	RTC_TOUCH_INT_ST_ACTIVE_INT_ST_Pos = 0x2
	// Bit mask of ACTIVE_INT_ST field.
	RTC_TOUCH_INT_ST_ACTIVE_INT_ST_Msk = 0x4
	// Bit ACTIVE_INT_ST.
	RTC_TOUCH_INT_ST_ACTIVE_INT_ST = 0x4
	// Position of INACTIVE_INT_ST field.
	RTC_TOUCH_INT_ST_INACTIVE_INT_ST_Pos = 0x3
	// Bit mask of INACTIVE_INT_ST field.
	RTC_TOUCH_INT_ST_INACTIVE_INT_ST_Msk = 0x8
	// Bit INACTIVE_INT_ST.
	RTC_TOUCH_INT_ST_INACTIVE_INT_ST = 0x8
	// Position of TIMEOUT_INT_ST field.
	RTC_TOUCH_INT_ST_TIMEOUT_INT_ST_Pos = 0x4
	// Bit mask of TIMEOUT_INT_ST field.
	RTC_TOUCH_INT_ST_TIMEOUT_INT_ST_Msk = 0x10
	// Bit TIMEOUT_INT_ST.
	RTC_TOUCH_INT_ST_TIMEOUT_INT_ST = 0x10
	// Position of APPROACH_LOOP_DONE_INT_ST field.
	RTC_TOUCH_INT_ST_APPROACH_LOOP_DONE_INT_ST_Pos = 0x5
	// Bit mask of APPROACH_LOOP_DONE_INT_ST field.
	RTC_TOUCH_INT_ST_APPROACH_LOOP_DONE_INT_ST_Msk = 0x20
	// Bit APPROACH_LOOP_DONE_INT_ST.
	RTC_TOUCH_INT_ST_APPROACH_LOOP_DONE_INT_ST = 0x20

	// INT_ENA: need_des
	// Position of SCAN_DONE_INT_ENA field.
	RTC_TOUCH_INT_ENA_SCAN_DONE_INT_ENA_Pos = 0x0
	// Bit mask of SCAN_DONE_INT_ENA field.
	RTC_TOUCH_INT_ENA_SCAN_DONE_INT_ENA_Msk = 0x1
	// Bit SCAN_DONE_INT_ENA.
	RTC_TOUCH_INT_ENA_SCAN_DONE_INT_ENA = 0x1
	// Position of DONE_INT_ENA field.
	RTC_TOUCH_INT_ENA_DONE_INT_ENA_Pos = 0x1
	// Bit mask of DONE_INT_ENA field.
	RTC_TOUCH_INT_ENA_DONE_INT_ENA_Msk = 0x2
	// Bit DONE_INT_ENA.
	RTC_TOUCH_INT_ENA_DONE_INT_ENA = 0x2
	// Position of ACTIVE_INT_ENA field.
	RTC_TOUCH_INT_ENA_ACTIVE_INT_ENA_Pos = 0x2
	// Bit mask of ACTIVE_INT_ENA field.
	RTC_TOUCH_INT_ENA_ACTIVE_INT_ENA_Msk = 0x4
	// Bit ACTIVE_INT_ENA.
	RTC_TOUCH_INT_ENA_ACTIVE_INT_ENA = 0x4
	// Position of INACTIVE_INT_ENA field.
	RTC_TOUCH_INT_ENA_INACTIVE_INT_ENA_Pos = 0x3
	// Bit mask of INACTIVE_INT_ENA field.
	RTC_TOUCH_INT_ENA_INACTIVE_INT_ENA_Msk = 0x8
	// Bit INACTIVE_INT_ENA.
	RTC_TOUCH_INT_ENA_INACTIVE_INT_ENA = 0x8
	// Position of TIMEOUT_INT_ENA field.
	RTC_TOUCH_INT_ENA_TIMEOUT_INT_ENA_Pos = 0x4
	// Bit mask of TIMEOUT_INT_ENA field.
	RTC_TOUCH_INT_ENA_TIMEOUT_INT_ENA_Msk = 0x10
	// Bit TIMEOUT_INT_ENA.
	RTC_TOUCH_INT_ENA_TIMEOUT_INT_ENA = 0x10
	// Position of APPROACH_LOOP_DONE_INT_ENA field.
	RTC_TOUCH_INT_ENA_APPROACH_LOOP_DONE_INT_ENA_Pos = 0x5
	// Bit mask of APPROACH_LOOP_DONE_INT_ENA field.
	RTC_TOUCH_INT_ENA_APPROACH_LOOP_DONE_INT_ENA_Msk = 0x20
	// Bit APPROACH_LOOP_DONE_INT_ENA.
	RTC_TOUCH_INT_ENA_APPROACH_LOOP_DONE_INT_ENA = 0x20

	// INT_CLR: need_des
	// Position of SCAN_DONE_INT_CLR field.
	RTC_TOUCH_INT_CLR_SCAN_DONE_INT_CLR_Pos = 0x0
	// Bit mask of SCAN_DONE_INT_CLR field.
	RTC_TOUCH_INT_CLR_SCAN_DONE_INT_CLR_Msk = 0x1
	// Bit SCAN_DONE_INT_CLR.
	RTC_TOUCH_INT_CLR_SCAN_DONE_INT_CLR = 0x1
	// Position of DONE_INT_CLR field.
	RTC_TOUCH_INT_CLR_DONE_INT_CLR_Pos = 0x1
	// Bit mask of DONE_INT_CLR field.
	RTC_TOUCH_INT_CLR_DONE_INT_CLR_Msk = 0x2
	// Bit DONE_INT_CLR.
	RTC_TOUCH_INT_CLR_DONE_INT_CLR = 0x2
	// Position of ACTIVE_INT_CLR field.
	RTC_TOUCH_INT_CLR_ACTIVE_INT_CLR_Pos = 0x2
	// Bit mask of ACTIVE_INT_CLR field.
	RTC_TOUCH_INT_CLR_ACTIVE_INT_CLR_Msk = 0x4
	// Bit ACTIVE_INT_CLR.
	RTC_TOUCH_INT_CLR_ACTIVE_INT_CLR = 0x4
	// Position of INACTIVE_INT_CLR field.
	RTC_TOUCH_INT_CLR_INACTIVE_INT_CLR_Pos = 0x3
	// Bit mask of INACTIVE_INT_CLR field.
	RTC_TOUCH_INT_CLR_INACTIVE_INT_CLR_Msk = 0x8
	// Bit INACTIVE_INT_CLR.
	RTC_TOUCH_INT_CLR_INACTIVE_INT_CLR = 0x8
	// Position of TIMEOUT_INT_CLR field.
	RTC_TOUCH_INT_CLR_TIMEOUT_INT_CLR_Pos = 0x4
	// Bit mask of TIMEOUT_INT_CLR field.
	RTC_TOUCH_INT_CLR_TIMEOUT_INT_CLR_Msk = 0x10
	// Bit TIMEOUT_INT_CLR.
	RTC_TOUCH_INT_CLR_TIMEOUT_INT_CLR = 0x10
	// Position of APPROACH_LOOP_DONE_INT_CLR field.
	RTC_TOUCH_INT_CLR_APPROACH_LOOP_DONE_INT_CLR_Pos = 0x5
	// Bit mask of APPROACH_LOOP_DONE_INT_CLR field.
	RTC_TOUCH_INT_CLR_APPROACH_LOOP_DONE_INT_CLR_Msk = 0x20
	// Bit APPROACH_LOOP_DONE_INT_CLR.
	RTC_TOUCH_INT_CLR_APPROACH_LOOP_DONE_INT_CLR = 0x20

	// CHN_STATUS: need_des
	// Position of PAD_ACTIVE field.
	RTC_TOUCH_CHN_STATUS_PAD_ACTIVE_Pos = 0x0
	// Bit mask of PAD_ACTIVE field.
	RTC_TOUCH_CHN_STATUS_PAD_ACTIVE_Msk = 0x7fff
	// Position of MEAS_DONE field.
	RTC_TOUCH_CHN_STATUS_MEAS_DONE_Pos = 0xf
	// Bit mask of MEAS_DONE field.
	RTC_TOUCH_CHN_STATUS_MEAS_DONE_Msk = 0x8000
	// Bit MEAS_DONE.
	RTC_TOUCH_CHN_STATUS_MEAS_DONE = 0x8000
	// Position of SCAN_CURR field.
	RTC_TOUCH_CHN_STATUS_SCAN_CURR_Pos = 0x10
	// Bit mask of SCAN_CURR field.
	RTC_TOUCH_CHN_STATUS_SCAN_CURR_Msk = 0xf0000

	// STATUS_0: need_des
	// Position of PAD0_DATA field.
	RTC_TOUCH_STATUS_0_PAD0_DATA_Pos = 0x0
	// Bit mask of PAD0_DATA field.
	RTC_TOUCH_STATUS_0_PAD0_DATA_Msk = 0xffff
	// Position of PAD0_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_0_PAD0_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD0_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_0_PAD0_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD0_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_0_PAD0_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD0_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_0_PAD0_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_1: need_des
	// Position of PAD1_DATA field.
	RTC_TOUCH_STATUS_1_PAD1_DATA_Pos = 0x0
	// Bit mask of PAD1_DATA field.
	RTC_TOUCH_STATUS_1_PAD1_DATA_Msk = 0xffff
	// Position of PAD1_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_1_PAD1_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD1_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_1_PAD1_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD1_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_1_PAD1_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD1_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_1_PAD1_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_2: need_des
	// Position of PAD2_DATA field.
	RTC_TOUCH_STATUS_2_PAD2_DATA_Pos = 0x0
	// Bit mask of PAD2_DATA field.
	RTC_TOUCH_STATUS_2_PAD2_DATA_Msk = 0xffff
	// Position of PAD2_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_2_PAD2_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD2_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_2_PAD2_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD2_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_2_PAD2_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD2_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_2_PAD2_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_3: need_des
	// Position of PAD3_DATA field.
	RTC_TOUCH_STATUS_3_PAD3_DATA_Pos = 0x0
	// Bit mask of PAD3_DATA field.
	RTC_TOUCH_STATUS_3_PAD3_DATA_Msk = 0xffff
	// Position of PAD3_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_3_PAD3_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD3_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_3_PAD3_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD3_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_3_PAD3_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD3_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_3_PAD3_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_4: need_des
	// Position of PAD4_DATA field.
	RTC_TOUCH_STATUS_4_PAD4_DATA_Pos = 0x0
	// Bit mask of PAD4_DATA field.
	RTC_TOUCH_STATUS_4_PAD4_DATA_Msk = 0xffff
	// Position of PAD4_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_4_PAD4_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD4_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_4_PAD4_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD4_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_4_PAD4_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD4_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_4_PAD4_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_5: need_des
	// Position of PAD5_DATA field.
	RTC_TOUCH_STATUS_5_PAD5_DATA_Pos = 0x0
	// Bit mask of PAD5_DATA field.
	RTC_TOUCH_STATUS_5_PAD5_DATA_Msk = 0xffff
	// Position of PAD5_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_5_PAD5_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD5_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_5_PAD5_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD5_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_5_PAD5_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD5_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_5_PAD5_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_6: need_des
	// Position of PAD6_DATA field.
	RTC_TOUCH_STATUS_6_PAD6_DATA_Pos = 0x0
	// Bit mask of PAD6_DATA field.
	RTC_TOUCH_STATUS_6_PAD6_DATA_Msk = 0xffff
	// Position of PAD6_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_6_PAD6_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD6_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_6_PAD6_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD6_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_6_PAD6_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD6_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_6_PAD6_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_7: need_des
	// Position of PAD7_DATA field.
	RTC_TOUCH_STATUS_7_PAD7_DATA_Pos = 0x0
	// Bit mask of PAD7_DATA field.
	RTC_TOUCH_STATUS_7_PAD7_DATA_Msk = 0xffff
	// Position of PAD7_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_7_PAD7_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD7_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_7_PAD7_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD7_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_7_PAD7_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD7_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_7_PAD7_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_8: need_des
	// Position of PAD8_DATA field.
	RTC_TOUCH_STATUS_8_PAD8_DATA_Pos = 0x0
	// Bit mask of PAD8_DATA field.
	RTC_TOUCH_STATUS_8_PAD8_DATA_Msk = 0xffff
	// Position of PAD8_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_8_PAD8_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD8_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_8_PAD8_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD8_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_8_PAD8_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD8_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_8_PAD8_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_9: need_des
	// Position of PAD9_DATA field.
	RTC_TOUCH_STATUS_9_PAD9_DATA_Pos = 0x0
	// Bit mask of PAD9_DATA field.
	RTC_TOUCH_STATUS_9_PAD9_DATA_Msk = 0xffff
	// Position of PAD9_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_9_PAD9_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD9_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_9_PAD9_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD9_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_9_PAD9_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD9_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_9_PAD9_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_10: need_des
	// Position of PAD10_DATA field.
	RTC_TOUCH_STATUS_10_PAD10_DATA_Pos = 0x0
	// Bit mask of PAD10_DATA field.
	RTC_TOUCH_STATUS_10_PAD10_DATA_Msk = 0xffff
	// Position of PAD10_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_10_PAD10_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD10_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_10_PAD10_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD10_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_10_PAD10_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD10_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_10_PAD10_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_11: need_des
	// Position of PAD11_DATA field.
	RTC_TOUCH_STATUS_11_PAD11_DATA_Pos = 0x0
	// Bit mask of PAD11_DATA field.
	RTC_TOUCH_STATUS_11_PAD11_DATA_Msk = 0xffff
	// Position of PAD11_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_11_PAD11_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD11_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_11_PAD11_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD11_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_11_PAD11_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD11_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_11_PAD11_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_12: need_des
	// Position of PAD12_DATA field.
	RTC_TOUCH_STATUS_12_PAD12_DATA_Pos = 0x0
	// Bit mask of PAD12_DATA field.
	RTC_TOUCH_STATUS_12_PAD12_DATA_Msk = 0xffff
	// Position of PAD12_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_12_PAD12_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD12_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_12_PAD12_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD12_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_12_PAD12_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD12_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_12_PAD12_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_13: need_des
	// Position of PAD13_DATA field.
	RTC_TOUCH_STATUS_13_PAD13_DATA_Pos = 0x0
	// Bit mask of PAD13_DATA field.
	RTC_TOUCH_STATUS_13_PAD13_DATA_Msk = 0xffff
	// Position of PAD13_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_13_PAD13_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD13_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_13_PAD13_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD13_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_13_PAD13_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD13_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_13_PAD13_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_14: need_des
	// Position of PAD14_DATA field.
	RTC_TOUCH_STATUS_14_PAD14_DATA_Pos = 0x0
	// Bit mask of PAD14_DATA field.
	RTC_TOUCH_STATUS_14_PAD14_DATA_Msk = 0xffff
	// Position of PAD14_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_14_PAD14_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of PAD14_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_14_PAD14_DEBOUNCE_CNT_Msk = 0x70000
	// Position of PAD14_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_14_PAD14_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of PAD14_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_14_PAD14_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_15: need_des
	// Position of SLP_DATA field.
	RTC_TOUCH_STATUS_15_SLP_DATA_Pos = 0x0
	// Bit mask of SLP_DATA field.
	RTC_TOUCH_STATUS_15_SLP_DATA_Msk = 0xffff
	// Position of SLP_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_15_SLP_DEBOUNCE_CNT_Pos = 0x10
	// Bit mask of SLP_DEBOUNCE_CNT field.
	RTC_TOUCH_STATUS_15_SLP_DEBOUNCE_CNT_Msk = 0x70000
	// Position of SLP_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_15_SLP_NEG_NOISE_CNT_Pos = 0x13
	// Bit mask of SLP_NEG_NOISE_CNT field.
	RTC_TOUCH_STATUS_15_SLP_NEG_NOISE_CNT_Msk = 0x780000

	// STATUS_16: need_des
	// Position of APPROACH_PAD2_CNT field.
	RTC_TOUCH_STATUS_16_APPROACH_PAD2_CNT_Pos = 0x0
	// Bit mask of APPROACH_PAD2_CNT field.
	RTC_TOUCH_STATUS_16_APPROACH_PAD2_CNT_Msk = 0xff
	// Position of APPROACH_PAD1_CNT field.
	RTC_TOUCH_STATUS_16_APPROACH_PAD1_CNT_Pos = 0x8
	// Bit mask of APPROACH_PAD1_CNT field.
	RTC_TOUCH_STATUS_16_APPROACH_PAD1_CNT_Msk = 0xff00
	// Position of APPROACH_PAD0_CNT field.
	RTC_TOUCH_STATUS_16_APPROACH_PAD0_CNT_Pos = 0x10
	// Bit mask of APPROACH_PAD0_CNT field.
	RTC_TOUCH_STATUS_16_APPROACH_PAD0_CNT_Msk = 0xff0000
	// Position of SLP_APPROACH_CNT field.
	RTC_TOUCH_STATUS_16_SLP_APPROACH_CNT_Pos = 0x18
	// Bit mask of SLP_APPROACH_CNT field.
	RTC_TOUCH_STATUS_16_SLP_APPROACH_CNT_Msk = 0xff000000

	// STATUS_17: need_des
	// Position of DCAP_LPF field.
	RTC_TOUCH_STATUS_17_DCAP_LPF_Pos = 0x0
	// Bit mask of DCAP_LPF field.
	RTC_TOUCH_STATUS_17_DCAP_LPF_Msk = 0x7f
	// Position of DRES_LPF field.
	RTC_TOUCH_STATUS_17_DRES_LPF_Pos = 0x7
	// Bit mask of DRES_LPF field.
	RTC_TOUCH_STATUS_17_DRES_LPF_Msk = 0x180
	// Position of DRV_LS field.
	RTC_TOUCH_STATUS_17_DRV_LS_Pos = 0x9
	// Bit mask of DRV_LS field.
	RTC_TOUCH_STATUS_17_DRV_LS_Msk = 0x1e00
	// Position of DRV_HS field.
	RTC_TOUCH_STATUS_17_DRV_HS_Pos = 0xd
	// Bit mask of DRV_HS field.
	RTC_TOUCH_STATUS_17_DRV_HS_Msk = 0x3e000
	// Position of DBIAS field.
	RTC_TOUCH_STATUS_17_DBIAS_Pos = 0x12
	// Bit mask of DBIAS field.
	RTC_TOUCH_STATUS_17_DBIAS_Msk = 0x7c0000
	// Position of RTC_FREQ_SCAN_CNT field.
	RTC_TOUCH_STATUS_17_RTC_FREQ_SCAN_CNT_Pos = 0x17
	// Bit mask of RTC_FREQ_SCAN_CNT field.
	RTC_TOUCH_STATUS_17_RTC_FREQ_SCAN_CNT_Msk = 0x1800000

	// CHN_TMP_STATUS: need_des
	// Position of PAD_INACTIVE_STATUS field.
	RTC_TOUCH_CHN_TMP_STATUS_PAD_INACTIVE_STATUS_Pos = 0x0
	// Bit mask of PAD_INACTIVE_STATUS field.
	RTC_TOUCH_CHN_TMP_STATUS_PAD_INACTIVE_STATUS_Msk = 0x7fff
	// Position of PAD_ACTIVE_STATUS field.
	RTC_TOUCH_CHN_TMP_STATUS_PAD_ACTIVE_STATUS_Pos = 0xf
	// Bit mask of PAD_ACTIVE_STATUS field.
	RTC_TOUCH_CHN_TMP_STATUS_PAD_ACTIVE_STATUS_Msk = 0x3fff8000

	// DATE: need_des
	// Position of RTC_DATE field.
	RTC_TOUCH_DATE_RTC_DATE_Pos = 0x0
	// Bit mask of RTC_DATE field.
	RTC_TOUCH_DATE_RTC_DATE_Msk = 0xfffffff
	// Position of RTC_CLK_EN field.
	RTC_TOUCH_DATE_RTC_CLK_EN_Pos = 0x1f
	// Bit mask of RTC_CLK_EN field.
	RTC_TOUCH_DATE_RTC_CLK_EN_Msk = 0x80000000
	// Bit RTC_CLK_EN.
	RTC_TOUCH_DATE_RTC_CLK_EN = 0x80000000
)

// Constants for LP_WDT: Low-power Watchdog Timer
const (
	// CONFIG0: need_des
	// Position of WDT_CHIP_RESET_WIDTH field.
	RTC_WDT_CONFIG0_WDT_CHIP_RESET_WIDTH_Pos = 0x0
	// Bit mask of WDT_CHIP_RESET_WIDTH field.
	RTC_WDT_CONFIG0_WDT_CHIP_RESET_WIDTH_Msk = 0xff
	// Position of WDT_CHIP_RESET_EN field.
	RTC_WDT_CONFIG0_WDT_CHIP_RESET_EN_Pos = 0x8
	// Bit mask of WDT_CHIP_RESET_EN field.
	RTC_WDT_CONFIG0_WDT_CHIP_RESET_EN_Msk = 0x100
	// Bit WDT_CHIP_RESET_EN.
	RTC_WDT_CONFIG0_WDT_CHIP_RESET_EN = 0x100
	// Position of WDT_PAUSE_IN_SLP field.
	RTC_WDT_CONFIG0_WDT_PAUSE_IN_SLP_Pos = 0x9
	// Bit mask of WDT_PAUSE_IN_SLP field.
	RTC_WDT_CONFIG0_WDT_PAUSE_IN_SLP_Msk = 0x200
	// Bit WDT_PAUSE_IN_SLP.
	RTC_WDT_CONFIG0_WDT_PAUSE_IN_SLP = 0x200
	// Position of WDT_APPCPU_RESET_EN field.
	RTC_WDT_CONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xa
	// Bit mask of WDT_APPCPU_RESET_EN field.
	RTC_WDT_CONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x400
	// Bit WDT_APPCPU_RESET_EN.
	RTC_WDT_CONFIG0_WDT_APPCPU_RESET_EN = 0x400
	// Position of WDT_PROCPU_RESET_EN field.
	RTC_WDT_CONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xb
	// Bit mask of WDT_PROCPU_RESET_EN field.
	RTC_WDT_CONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x800
	// Bit WDT_PROCPU_RESET_EN.
	RTC_WDT_CONFIG0_WDT_PROCPU_RESET_EN = 0x800
	// Position of WDT_FLASHBOOT_MOD_EN field.
	RTC_WDT_CONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xc
	// Bit mask of WDT_FLASHBOOT_MOD_EN field.
	RTC_WDT_CONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x1000
	// Bit WDT_FLASHBOOT_MOD_EN.
	RTC_WDT_CONFIG0_WDT_FLASHBOOT_MOD_EN = 0x1000
	// Position of WDT_SYS_RESET_LENGTH field.
	RTC_WDT_CONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xd
	// Bit mask of WDT_SYS_RESET_LENGTH field.
	RTC_WDT_CONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0xe000
	// Position of WDT_CPU_RESET_LENGTH field.
	RTC_WDT_CONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x10
	// Bit mask of WDT_CPU_RESET_LENGTH field.
	RTC_WDT_CONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x70000
	// Position of WDT_STG3 field.
	RTC_WDT_CONFIG0_WDT_STG3_Pos = 0x13
	// Bit mask of WDT_STG3 field.
	RTC_WDT_CONFIG0_WDT_STG3_Msk = 0x380000
	// Position of WDT_STG2 field.
	RTC_WDT_CONFIG0_WDT_STG2_Pos = 0x16
	// Bit mask of WDT_STG2 field.
	RTC_WDT_CONFIG0_WDT_STG2_Msk = 0x1c00000
	// Position of WDT_STG1 field.
	RTC_WDT_CONFIG0_WDT_STG1_Pos = 0x19
	// Bit mask of WDT_STG1 field.
	RTC_WDT_CONFIG0_WDT_STG1_Msk = 0xe000000
	// Position of WDT_STG0 field.
	RTC_WDT_CONFIG0_WDT_STG0_Pos = 0x1c
	// Bit mask of WDT_STG0 field.
	RTC_WDT_CONFIG0_WDT_STG0_Msk = 0x70000000
	// Position of WDT_EN field.
	RTC_WDT_CONFIG0_WDT_EN_Pos = 0x1f
	// Bit mask of WDT_EN field.
	RTC_WDT_CONFIG0_WDT_EN_Msk = 0x80000000
	// Bit WDT_EN.
	RTC_WDT_CONFIG0_WDT_EN = 0x80000000

	// CONFIG1: need_des
	// Position of WDT_STG0_HOLD field.
	RTC_WDT_CONFIG1_WDT_STG0_HOLD_Pos = 0x0
	// Bit mask of WDT_STG0_HOLD field.
	RTC_WDT_CONFIG1_WDT_STG0_HOLD_Msk = 0xffffffff

	// CONFIG2: need_des
	// Position of WDT_STG1_HOLD field.
	RTC_WDT_CONFIG2_WDT_STG1_HOLD_Pos = 0x0
	// Bit mask of WDT_STG1_HOLD field.
	RTC_WDT_CONFIG2_WDT_STG1_HOLD_Msk = 0xffffffff

	// CONFIG3: need_des
	// Position of WDT_STG2_HOLD field.
	RTC_WDT_CONFIG3_WDT_STG2_HOLD_Pos = 0x0
	// Bit mask of WDT_STG2_HOLD field.
	RTC_WDT_CONFIG3_WDT_STG2_HOLD_Msk = 0xffffffff

	// CONFIG4: need_des
	// Position of WDT_STG3_HOLD field.
	RTC_WDT_CONFIG4_WDT_STG3_HOLD_Pos = 0x0
	// Bit mask of WDT_STG3_HOLD field.
	RTC_WDT_CONFIG4_WDT_STG3_HOLD_Msk = 0xffffffff

	// FEED: need_des
	// Position of FEED field.
	RTC_WDT_FEED_FEED_Pos = 0x1f
	// Bit mask of FEED field.
	RTC_WDT_FEED_FEED_Msk = 0x80000000
	// Bit FEED.
	RTC_WDT_FEED_FEED = 0x80000000

	// WPROTECT: need_des
	// Position of WDT_WKEY field.
	RTC_WDT_WPROTECT_WDT_WKEY_Pos = 0x0
	// Bit mask of WDT_WKEY field.
	RTC_WDT_WPROTECT_WDT_WKEY_Msk = 0xffffffff

	// SWD_CONFIG: need_des
	// Position of SWD_RESET_FLAG field.
	RTC_WDT_SWD_CONFIG_SWD_RESET_FLAG_Pos = 0x0
	// Bit mask of SWD_RESET_FLAG field.
	RTC_WDT_SWD_CONFIG_SWD_RESET_FLAG_Msk = 0x1
	// Bit SWD_RESET_FLAG.
	RTC_WDT_SWD_CONFIG_SWD_RESET_FLAG = 0x1
	// Position of SWD_AUTO_FEED_EN field.
	RTC_WDT_SWD_CONFIG_SWD_AUTO_FEED_EN_Pos = 0x12
	// Bit mask of SWD_AUTO_FEED_EN field.
	RTC_WDT_SWD_CONFIG_SWD_AUTO_FEED_EN_Msk = 0x40000
	// Bit SWD_AUTO_FEED_EN.
	RTC_WDT_SWD_CONFIG_SWD_AUTO_FEED_EN = 0x40000
	// Position of SWD_RST_FLAG_CLR field.
	RTC_WDT_SWD_CONFIG_SWD_RST_FLAG_CLR_Pos = 0x13
	// Bit mask of SWD_RST_FLAG_CLR field.
	RTC_WDT_SWD_CONFIG_SWD_RST_FLAG_CLR_Msk = 0x80000
	// Bit SWD_RST_FLAG_CLR.
	RTC_WDT_SWD_CONFIG_SWD_RST_FLAG_CLR = 0x80000
	// Position of SWD_SIGNAL_WIDTH field.
	RTC_WDT_SWD_CONFIG_SWD_SIGNAL_WIDTH_Pos = 0x14
	// Bit mask of SWD_SIGNAL_WIDTH field.
	RTC_WDT_SWD_CONFIG_SWD_SIGNAL_WIDTH_Msk = 0x3ff00000
	// Position of SWD_DISABLE field.
	RTC_WDT_SWD_CONFIG_SWD_DISABLE_Pos = 0x1e
	// Bit mask of SWD_DISABLE field.
	RTC_WDT_SWD_CONFIG_SWD_DISABLE_Msk = 0x40000000
	// Bit SWD_DISABLE.
	RTC_WDT_SWD_CONFIG_SWD_DISABLE = 0x40000000
	// Position of SWD_FEED field.
	RTC_WDT_SWD_CONFIG_SWD_FEED_Pos = 0x1f
	// Bit mask of SWD_FEED field.
	RTC_WDT_SWD_CONFIG_SWD_FEED_Msk = 0x80000000
	// Bit SWD_FEED.
	RTC_WDT_SWD_CONFIG_SWD_FEED = 0x80000000

	// SWD_WPROTECT: need_des
	// Position of SWD_WKEY field.
	RTC_WDT_SWD_WPROTECT_SWD_WKEY_Pos = 0x0
	// Bit mask of SWD_WKEY field.
	RTC_WDT_SWD_WPROTECT_SWD_WKEY_Msk = 0xffffffff

	// INT_RAW: need_des
	// Position of SUPER_WDT_INT_RAW field.
	RTC_WDT_INT_RAW_SUPER_WDT_INT_RAW_Pos = 0x1e
	// Bit mask of SUPER_WDT_INT_RAW field.
	RTC_WDT_INT_RAW_SUPER_WDT_INT_RAW_Msk = 0x40000000
	// Bit SUPER_WDT_INT_RAW.
	RTC_WDT_INT_RAW_SUPER_WDT_INT_RAW = 0x40000000
	// Position of LP_WDT_INT_RAW field.
	RTC_WDT_INT_RAW_LP_WDT_INT_RAW_Pos = 0x1f
	// Bit mask of LP_WDT_INT_RAW field.
	RTC_WDT_INT_RAW_LP_WDT_INT_RAW_Msk = 0x80000000
	// Bit LP_WDT_INT_RAW.
	RTC_WDT_INT_RAW_LP_WDT_INT_RAW = 0x80000000

	// INT_ST: need_des
	// Position of SUPER_WDT_INT_ST field.
	RTC_WDT_INT_ST_SUPER_WDT_INT_ST_Pos = 0x1e
	// Bit mask of SUPER_WDT_INT_ST field.
	RTC_WDT_INT_ST_SUPER_WDT_INT_ST_Msk = 0x40000000
	// Bit SUPER_WDT_INT_ST.
	RTC_WDT_INT_ST_SUPER_WDT_INT_ST = 0x40000000
	// Position of LP_WDT_INT_ST field.
	RTC_WDT_INT_ST_LP_WDT_INT_ST_Pos = 0x1f
	// Bit mask of LP_WDT_INT_ST field.
	RTC_WDT_INT_ST_LP_WDT_INT_ST_Msk = 0x80000000
	// Bit LP_WDT_INT_ST.
	RTC_WDT_INT_ST_LP_WDT_INT_ST = 0x80000000

	// INT_ENA: need_des
	// Position of SUPER_WDT_INT_ENA field.
	RTC_WDT_INT_ENA_SUPER_WDT_INT_ENA_Pos = 0x1e
	// Bit mask of SUPER_WDT_INT_ENA field.
	RTC_WDT_INT_ENA_SUPER_WDT_INT_ENA_Msk = 0x40000000
	// Bit SUPER_WDT_INT_ENA.
	RTC_WDT_INT_ENA_SUPER_WDT_INT_ENA = 0x40000000
	// Position of LP_WDT_INT_ENA field.
	RTC_WDT_INT_ENA_LP_WDT_INT_ENA_Pos = 0x1f
	// Bit mask of LP_WDT_INT_ENA field.
	RTC_WDT_INT_ENA_LP_WDT_INT_ENA_Msk = 0x80000000
	// Bit LP_WDT_INT_ENA.
	RTC_WDT_INT_ENA_LP_WDT_INT_ENA = 0x80000000

	// INT_CLR: need_des
	// Position of SUPER_WDT_INT_CLR field.
	RTC_WDT_INT_CLR_SUPER_WDT_INT_CLR_Pos = 0x1e
	// Bit mask of SUPER_WDT_INT_CLR field.
	RTC_WDT_INT_CLR_SUPER_WDT_INT_CLR_Msk = 0x40000000
	// Bit SUPER_WDT_INT_CLR.
	RTC_WDT_INT_CLR_SUPER_WDT_INT_CLR = 0x40000000
	// Position of LP_WDT_INT_CLR field.
	RTC_WDT_INT_CLR_LP_WDT_INT_CLR_Pos = 0x1f
	// Bit mask of LP_WDT_INT_CLR field.
	RTC_WDT_INT_CLR_LP_WDT_INT_CLR_Msk = 0x80000000
	// Bit LP_WDT_INT_CLR.
	RTC_WDT_INT_CLR_LP_WDT_INT_CLR = 0x80000000

	// DATE: need_des
	// Position of LP_WDT_DATE field.
	RTC_WDT_DATE_LP_WDT_DATE_Pos = 0x0
	// Bit mask of LP_WDT_DATE field.
	RTC_WDT_DATE_LP_WDT_DATE_Msk = 0x7fffffff
	// Position of CLK_EN field.
	RTC_WDT_DATE_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	RTC_WDT_DATE_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	RTC_WDT_DATE_CLK_EN = 0x80000000
)

// Constants for SDHOST: SD/MMC Host Controller
const (
	// CTRL: Control register
	// Position of CONTROLLER_RESET field.
	SDHOST_CTRL_CONTROLLER_RESET_Pos = 0x0
	// Bit mask of CONTROLLER_RESET field.
	SDHOST_CTRL_CONTROLLER_RESET_Msk = 0x1
	// Bit CONTROLLER_RESET.
	SDHOST_CTRL_CONTROLLER_RESET = 0x1
	// Position of FIFO_RESET field.
	SDHOST_CTRL_FIFO_RESET_Pos = 0x1
	// Bit mask of FIFO_RESET field.
	SDHOST_CTRL_FIFO_RESET_Msk = 0x2
	// Bit FIFO_RESET.
	SDHOST_CTRL_FIFO_RESET = 0x2
	// Position of DMA_RESET field.
	SDHOST_CTRL_DMA_RESET_Pos = 0x2
	// Bit mask of DMA_RESET field.
	SDHOST_CTRL_DMA_RESET_Msk = 0x4
	// Bit DMA_RESET.
	SDHOST_CTRL_DMA_RESET = 0x4
	// Position of INT_ENABLE field.
	SDHOST_CTRL_INT_ENABLE_Pos = 0x4
	// Bit mask of INT_ENABLE field.
	SDHOST_CTRL_INT_ENABLE_Msk = 0x10
	// Bit INT_ENABLE.
	SDHOST_CTRL_INT_ENABLE = 0x10
	// Position of READ_WAIT field.
	SDHOST_CTRL_READ_WAIT_Pos = 0x6
	// Bit mask of READ_WAIT field.
	SDHOST_CTRL_READ_WAIT_Msk = 0x40
	// Bit READ_WAIT.
	SDHOST_CTRL_READ_WAIT = 0x40
	// Position of SEND_IRQ_RESPONSE field.
	SDHOST_CTRL_SEND_IRQ_RESPONSE_Pos = 0x7
	// Bit mask of SEND_IRQ_RESPONSE field.
	SDHOST_CTRL_SEND_IRQ_RESPONSE_Msk = 0x80
	// Bit SEND_IRQ_RESPONSE.
	SDHOST_CTRL_SEND_IRQ_RESPONSE = 0x80
	// Position of ABORT_READ_DATA field.
	SDHOST_CTRL_ABORT_READ_DATA_Pos = 0x8
	// Bit mask of ABORT_READ_DATA field.
	SDHOST_CTRL_ABORT_READ_DATA_Msk = 0x100
	// Bit ABORT_READ_DATA.
	SDHOST_CTRL_ABORT_READ_DATA = 0x100
	// Position of SEND_CCSD field.
	SDHOST_CTRL_SEND_CCSD_Pos = 0x9
	// Bit mask of SEND_CCSD field.
	SDHOST_CTRL_SEND_CCSD_Msk = 0x200
	// Bit SEND_CCSD.
	SDHOST_CTRL_SEND_CCSD = 0x200
	// Position of SEND_AUTO_STOP_CCSD field.
	SDHOST_CTRL_SEND_AUTO_STOP_CCSD_Pos = 0xa
	// Bit mask of SEND_AUTO_STOP_CCSD field.
	SDHOST_CTRL_SEND_AUTO_STOP_CCSD_Msk = 0x400
	// Bit SEND_AUTO_STOP_CCSD.
	SDHOST_CTRL_SEND_AUTO_STOP_CCSD = 0x400
	// Position of CEATA_DEVICE_INTERRUPT_STATUS field.
	SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos = 0xb
	// Bit mask of CEATA_DEVICE_INTERRUPT_STATUS field.
	SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk = 0x800
	// Bit CEATA_DEVICE_INTERRUPT_STATUS.
	SDHOST_CTRL_CEATA_DEVICE_INTERRUPT_STATUS = 0x800

	// CLKDIV: Clock divider configuration register
	// Position of CLK_DIVIDER0 field.
	SDHOST_CLKDIV_CLK_DIVIDER0_Pos = 0x0
	// Bit mask of CLK_DIVIDER0 field.
	SDHOST_CLKDIV_CLK_DIVIDER0_Msk = 0xff
	// Position of CLK_DIVIDER1 field.
	SDHOST_CLKDIV_CLK_DIVIDER1_Pos = 0x8
	// Bit mask of CLK_DIVIDER1 field.
	SDHOST_CLKDIV_CLK_DIVIDER1_Msk = 0xff00
	// Position of CLK_DIVIDER2 field.
	SDHOST_CLKDIV_CLK_DIVIDER2_Pos = 0x10
	// Bit mask of CLK_DIVIDER2 field.
	SDHOST_CLKDIV_CLK_DIVIDER2_Msk = 0xff0000
	// Position of CLK_DIVIDER3 field.
	SDHOST_CLKDIV_CLK_DIVIDER3_Pos = 0x18
	// Bit mask of CLK_DIVIDER3 field.
	SDHOST_CLKDIV_CLK_DIVIDER3_Msk = 0xff000000

	// CLKSRC: Clock source selection register
	// Position of CLKSRC field.
	SDHOST_CLKSRC_CLKSRC_Pos = 0x0
	// Bit mask of CLKSRC field.
	SDHOST_CLKSRC_CLKSRC_Msk = 0xf

	// CLKENA: Clock enable register
	// Position of CCLK_ENABLE field.
	SDHOST_CLKENA_CCLK_ENABLE_Pos = 0x0
	// Bit mask of CCLK_ENABLE field.
	SDHOST_CLKENA_CCLK_ENABLE_Msk = 0x3
	// Position of LP_ENABLE field.
	SDHOST_CLKENA_LP_ENABLE_Pos = 0x10
	// Bit mask of LP_ENABLE field.
	SDHOST_CLKENA_LP_ENABLE_Msk = 0x30000

	// TMOUT: Data and response timeout configuration register
	// Position of RESPONSE_TIMEOUT field.
	SDHOST_TMOUT_RESPONSE_TIMEOUT_Pos = 0x0
	// Bit mask of RESPONSE_TIMEOUT field.
	SDHOST_TMOUT_RESPONSE_TIMEOUT_Msk = 0xff
	// Position of DATA_TIMEOUT field.
	SDHOST_TMOUT_DATA_TIMEOUT_Pos = 0x8
	// Bit mask of DATA_TIMEOUT field.
	SDHOST_TMOUT_DATA_TIMEOUT_Msk = 0xffffff00

	// CTYPE: Card bus width configuration register
	// Position of CARD_WIDTH4 field.
	SDHOST_CTYPE_CARD_WIDTH4_Pos = 0x0
	// Bit mask of CARD_WIDTH4 field.
	SDHOST_CTYPE_CARD_WIDTH4_Msk = 0x3
	// Position of CARD_WIDTH8 field.
	SDHOST_CTYPE_CARD_WIDTH8_Pos = 0x10
	// Bit mask of CARD_WIDTH8 field.
	SDHOST_CTYPE_CARD_WIDTH8_Msk = 0x30000

	// BLKSIZ: Card data block size configuration register
	// Position of BLOCK_SIZE field.
	SDHOST_BLKSIZ_BLOCK_SIZE_Pos = 0x0
	// Bit mask of BLOCK_SIZE field.
	SDHOST_BLKSIZ_BLOCK_SIZE_Msk = 0xffff

	// BYTCNT: Data transfer length configuration register
	// Position of BYTE_COUNT field.
	SDHOST_BYTCNT_BYTE_COUNT_Pos = 0x0
	// Bit mask of BYTE_COUNT field.
	SDHOST_BYTCNT_BYTE_COUNT_Msk = 0xffffffff

	// INTMASK: SDIO interrupt mask register
	// Position of INT_MASK field.
	SDHOST_INTMASK_INT_MASK_Pos = 0x0
	// Bit mask of INT_MASK field.
	SDHOST_INTMASK_INT_MASK_Msk = 0xffff
	// Position of SDIO_INT_MASK field.
	SDHOST_INTMASK_SDIO_INT_MASK_Pos = 0x10
	// Bit mask of SDIO_INT_MASK field.
	SDHOST_INTMASK_SDIO_INT_MASK_Msk = 0x30000

	// CMDARG: Command argument data register
	// Position of CMDARG field.
	SDHOST_CMDARG_CMDARG_Pos = 0x0
	// Bit mask of CMDARG field.
	SDHOST_CMDARG_CMDARG_Msk = 0xffffffff

	// CMD: Command and boot configuration register
	// Position of INDEX field.
	SDHOST_CMD_INDEX_Pos = 0x0
	// Bit mask of INDEX field.
	SDHOST_CMD_INDEX_Msk = 0x3f
	// Position of RESPONSE_EXPECT field.
	SDHOST_CMD_RESPONSE_EXPECT_Pos = 0x6
	// Bit mask of RESPONSE_EXPECT field.
	SDHOST_CMD_RESPONSE_EXPECT_Msk = 0x40
	// Bit RESPONSE_EXPECT.
	SDHOST_CMD_RESPONSE_EXPECT = 0x40
	// Position of RESPONSE_LENGTH field.
	SDHOST_CMD_RESPONSE_LENGTH_Pos = 0x7
	// Bit mask of RESPONSE_LENGTH field.
	SDHOST_CMD_RESPONSE_LENGTH_Msk = 0x80
	// Bit RESPONSE_LENGTH.
	SDHOST_CMD_RESPONSE_LENGTH = 0x80
	// Position of CHECK_RESPONSE_CRC field.
	SDHOST_CMD_CHECK_RESPONSE_CRC_Pos = 0x8
	// Bit mask of CHECK_RESPONSE_CRC field.
	SDHOST_CMD_CHECK_RESPONSE_CRC_Msk = 0x100
	// Bit CHECK_RESPONSE_CRC.
	SDHOST_CMD_CHECK_RESPONSE_CRC = 0x100
	// Position of DATA_EXPECTED field.
	SDHOST_CMD_DATA_EXPECTED_Pos = 0x9
	// Bit mask of DATA_EXPECTED field.
	SDHOST_CMD_DATA_EXPECTED_Msk = 0x200
	// Bit DATA_EXPECTED.
	SDHOST_CMD_DATA_EXPECTED = 0x200
	// Position of READ_WRITE field.
	SDHOST_CMD_READ_WRITE_Pos = 0xa
	// Bit mask of READ_WRITE field.
	SDHOST_CMD_READ_WRITE_Msk = 0x400
	// Bit READ_WRITE.
	SDHOST_CMD_READ_WRITE = 0x400
	// Position of TRANSFER_MODE field.
	SDHOST_CMD_TRANSFER_MODE_Pos = 0xb
	// Bit mask of TRANSFER_MODE field.
	SDHOST_CMD_TRANSFER_MODE_Msk = 0x800
	// Bit TRANSFER_MODE.
	SDHOST_CMD_TRANSFER_MODE = 0x800
	// Position of SEND_AUTO_STOP field.
	SDHOST_CMD_SEND_AUTO_STOP_Pos = 0xc
	// Bit mask of SEND_AUTO_STOP field.
	SDHOST_CMD_SEND_AUTO_STOP_Msk = 0x1000
	// Bit SEND_AUTO_STOP.
	SDHOST_CMD_SEND_AUTO_STOP = 0x1000
	// Position of WAIT_PRVDATA_COMPLETE field.
	SDHOST_CMD_WAIT_PRVDATA_COMPLETE_Pos = 0xd
	// Bit mask of WAIT_PRVDATA_COMPLETE field.
	SDHOST_CMD_WAIT_PRVDATA_COMPLETE_Msk = 0x2000
	// Bit WAIT_PRVDATA_COMPLETE.
	SDHOST_CMD_WAIT_PRVDATA_COMPLETE = 0x2000
	// Position of STOP_ABORT_CMD field.
	SDHOST_CMD_STOP_ABORT_CMD_Pos = 0xe
	// Bit mask of STOP_ABORT_CMD field.
	SDHOST_CMD_STOP_ABORT_CMD_Msk = 0x4000
	// Bit STOP_ABORT_CMD.
	SDHOST_CMD_STOP_ABORT_CMD = 0x4000
	// Position of SEND_INITIALIZATION field.
	SDHOST_CMD_SEND_INITIALIZATION_Pos = 0xf
	// Bit mask of SEND_INITIALIZATION field.
	SDHOST_CMD_SEND_INITIALIZATION_Msk = 0x8000
	// Bit SEND_INITIALIZATION.
	SDHOST_CMD_SEND_INITIALIZATION = 0x8000
	// Position of CARD_NUMBER field.
	SDHOST_CMD_CARD_NUMBER_Pos = 0x10
	// Bit mask of CARD_NUMBER field.
	SDHOST_CMD_CARD_NUMBER_Msk = 0x1f0000
	// Position of UPDATE_CLOCK_REGISTERS_ONLY field.
	SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos = 0x15
	// Bit mask of UPDATE_CLOCK_REGISTERS_ONLY field.
	SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk = 0x200000
	// Bit UPDATE_CLOCK_REGISTERS_ONLY.
	SDHOST_CMD_UPDATE_CLOCK_REGISTERS_ONLY = 0x200000
	// Position of READ_CEATA_DEVICE field.
	SDHOST_CMD_READ_CEATA_DEVICE_Pos = 0x16
	// Bit mask of READ_CEATA_DEVICE field.
	SDHOST_CMD_READ_CEATA_DEVICE_Msk = 0x400000
	// Bit READ_CEATA_DEVICE.
	SDHOST_CMD_READ_CEATA_DEVICE = 0x400000
	// Position of CCS_EXPECTED field.
	SDHOST_CMD_CCS_EXPECTED_Pos = 0x17
	// Bit mask of CCS_EXPECTED field.
	SDHOST_CMD_CCS_EXPECTED_Msk = 0x800000
	// Bit CCS_EXPECTED.
	SDHOST_CMD_CCS_EXPECTED = 0x800000
	// Position of USE_HOLE field.
	SDHOST_CMD_USE_HOLE_Pos = 0x1d
	// Bit mask of USE_HOLE field.
	SDHOST_CMD_USE_HOLE_Msk = 0x20000000
	// Bit USE_HOLE.
	SDHOST_CMD_USE_HOLE = 0x20000000
	// Position of START_CMD field.
	SDHOST_CMD_START_CMD_Pos = 0x1f
	// Bit mask of START_CMD field.
	SDHOST_CMD_START_CMD_Msk = 0x80000000
	// Bit START_CMD.
	SDHOST_CMD_START_CMD = 0x80000000

	// RESP0: Response data register
	// Position of RESPONSE0 field.
	SDHOST_RESP0_RESPONSE0_Pos = 0x0
	// Bit mask of RESPONSE0 field.
	SDHOST_RESP0_RESPONSE0_Msk = 0xffffffff

	// RESP1: Long response data register
	// Position of RESPONSE1 field.
	SDHOST_RESP1_RESPONSE1_Pos = 0x0
	// Bit mask of RESPONSE1 field.
	SDHOST_RESP1_RESPONSE1_Msk = 0xffffffff

	// RESP2: Long response data register
	// Position of RESPONSE2 field.
	SDHOST_RESP2_RESPONSE2_Pos = 0x0
	// Bit mask of RESPONSE2 field.
	SDHOST_RESP2_RESPONSE2_Msk = 0xffffffff

	// RESP3: Long response data register
	// Position of RESPONSE3 field.
	SDHOST_RESP3_RESPONSE3_Pos = 0x0
	// Bit mask of RESPONSE3 field.
	SDHOST_RESP3_RESPONSE3_Msk = 0xffffffff

	// MINTSTS: Masked interrupt status register
	// Position of INT_STATUS_MSK field.
	SDHOST_MINTSTS_INT_STATUS_MSK_Pos = 0x0
	// Bit mask of INT_STATUS_MSK field.
	SDHOST_MINTSTS_INT_STATUS_MSK_Msk = 0xffff
	// Position of SDIO_INTERRUPT_MSK field.
	SDHOST_MINTSTS_SDIO_INTERRUPT_MSK_Pos = 0x10
	// Bit mask of SDIO_INTERRUPT_MSK field.
	SDHOST_MINTSTS_SDIO_INTERRUPT_MSK_Msk = 0x30000

	// RINTSTS: Raw interrupt status register
	// Position of INT_STATUS_RAW field.
	SDHOST_RINTSTS_INT_STATUS_RAW_Pos = 0x0
	// Bit mask of INT_STATUS_RAW field.
	SDHOST_RINTSTS_INT_STATUS_RAW_Msk = 0xffff
	// Position of SDIO_INTERRUPT_RAW field.
	SDHOST_RINTSTS_SDIO_INTERRUPT_RAW_Pos = 0x10
	// Bit mask of SDIO_INTERRUPT_RAW field.
	SDHOST_RINTSTS_SDIO_INTERRUPT_RAW_Msk = 0x30000

	// STATUS: SD/MMC status register
	// Position of FIFO_RX_WATERMARK field.
	SDHOST_STATUS_FIFO_RX_WATERMARK_Pos = 0x0
	// Bit mask of FIFO_RX_WATERMARK field.
	SDHOST_STATUS_FIFO_RX_WATERMARK_Msk = 0x1
	// Bit FIFO_RX_WATERMARK.
	SDHOST_STATUS_FIFO_RX_WATERMARK = 0x1
	// Position of FIFO_TX_WATERMARK field.
	SDHOST_STATUS_FIFO_TX_WATERMARK_Pos = 0x1
	// Bit mask of FIFO_TX_WATERMARK field.
	SDHOST_STATUS_FIFO_TX_WATERMARK_Msk = 0x2
	// Bit FIFO_TX_WATERMARK.
	SDHOST_STATUS_FIFO_TX_WATERMARK = 0x2
	// Position of FIFO_EMPTY field.
	SDHOST_STATUS_FIFO_EMPTY_Pos = 0x2
	// Bit mask of FIFO_EMPTY field.
	SDHOST_STATUS_FIFO_EMPTY_Msk = 0x4
	// Bit FIFO_EMPTY.
	SDHOST_STATUS_FIFO_EMPTY = 0x4
	// Position of FIFO_FULL field.
	SDHOST_STATUS_FIFO_FULL_Pos = 0x3
	// Bit mask of FIFO_FULL field.
	SDHOST_STATUS_FIFO_FULL_Msk = 0x8
	// Bit FIFO_FULL.
	SDHOST_STATUS_FIFO_FULL = 0x8
	// Position of COMMAND_FSM_STATES field.
	SDHOST_STATUS_COMMAND_FSM_STATES_Pos = 0x4
	// Bit mask of COMMAND_FSM_STATES field.
	SDHOST_STATUS_COMMAND_FSM_STATES_Msk = 0xf0
	// Position of DATA_3_STATUS field.
	SDHOST_STATUS_DATA_3_STATUS_Pos = 0x8
	// Bit mask of DATA_3_STATUS field.
	SDHOST_STATUS_DATA_3_STATUS_Msk = 0x100
	// Bit DATA_3_STATUS.
	SDHOST_STATUS_DATA_3_STATUS = 0x100
	// Position of DATA_BUSY field.
	SDHOST_STATUS_DATA_BUSY_Pos = 0x9
	// Bit mask of DATA_BUSY field.
	SDHOST_STATUS_DATA_BUSY_Msk = 0x200
	// Bit DATA_BUSY.
	SDHOST_STATUS_DATA_BUSY = 0x200
	// Position of DATA_STATE_MC_BUSY field.
	SDHOST_STATUS_DATA_STATE_MC_BUSY_Pos = 0xa
	// Bit mask of DATA_STATE_MC_BUSY field.
	SDHOST_STATUS_DATA_STATE_MC_BUSY_Msk = 0x400
	// Bit DATA_STATE_MC_BUSY.
	SDHOST_STATUS_DATA_STATE_MC_BUSY = 0x400
	// Position of RESPONSE_INDEX field.
	SDHOST_STATUS_RESPONSE_INDEX_Pos = 0xb
	// Bit mask of RESPONSE_INDEX field.
	SDHOST_STATUS_RESPONSE_INDEX_Msk = 0x1f800
	// Position of FIFO_COUNT field.
	SDHOST_STATUS_FIFO_COUNT_Pos = 0x11
	// Bit mask of FIFO_COUNT field.
	SDHOST_STATUS_FIFO_COUNT_Msk = 0x3ffe0000

	// FIFOTH: FIFO configuration register
	// Position of TX_WMARK field.
	SDHOST_FIFOTH_TX_WMARK_Pos = 0x0
	// Bit mask of TX_WMARK field.
	SDHOST_FIFOTH_TX_WMARK_Msk = 0xfff
	// Position of RX_WMARK field.
	SDHOST_FIFOTH_RX_WMARK_Pos = 0x10
	// Bit mask of RX_WMARK field.
	SDHOST_FIFOTH_RX_WMARK_Msk = 0x7ff0000
	// Position of DMA_MULTIPLE_TRANSACTION_SIZE field.
	SDHOST_FIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE_Pos = 0x1c
	// Bit mask of DMA_MULTIPLE_TRANSACTION_SIZE field.
	SDHOST_FIFOTH_DMA_MULTIPLE_TRANSACTION_SIZE_Msk = 0x70000000

	// CDETECT: Card detect register
	// Position of CARD_DETECT_N field.
	SDHOST_CDETECT_CARD_DETECT_N_Pos = 0x0
	// Bit mask of CARD_DETECT_N field.
	SDHOST_CDETECT_CARD_DETECT_N_Msk = 0x3

	// WRTPRT: Card write protection (WP) status register
	// Position of WRITE_PROTECT field.
	SDHOST_WRTPRT_WRITE_PROTECT_Pos = 0x0
	// Bit mask of WRITE_PROTECT field.
	SDHOST_WRTPRT_WRITE_PROTECT_Msk = 0x3

	// TCBCNT: Transferred byte count register
	// Position of TCBCNT field.
	SDHOST_TCBCNT_TCBCNT_Pos = 0x0
	// Bit mask of TCBCNT field.
	SDHOST_TCBCNT_TCBCNT_Msk = 0xffffffff

	// TBBCNT: Transferred byte count register
	// Position of TBBCNT field.
	SDHOST_TBBCNT_TBBCNT_Pos = 0x0
	// Bit mask of TBBCNT field.
	SDHOST_TBBCNT_TBBCNT_Msk = 0xffffffff

	// DEBNCE: Debounce filter time configuration register
	// Position of DEBOUNCE_COUNT field.
	SDHOST_DEBNCE_DEBOUNCE_COUNT_Pos = 0x0
	// Bit mask of DEBOUNCE_COUNT field.
	SDHOST_DEBNCE_DEBOUNCE_COUNT_Msk = 0xffffff

	// USRID: User ID (scratchpad) register
	// Position of USRID field.
	SDHOST_USRID_USRID_Pos = 0x0
	// Bit mask of USRID field.
	SDHOST_USRID_USRID_Msk = 0xffffffff

	// VERID: Version ID (scratchpad) register
	// Position of VERSIONID field.
	SDHOST_VERID_VERSIONID_Pos = 0x0
	// Bit mask of VERSIONID field.
	SDHOST_VERID_VERSIONID_Msk = 0xffffffff

	// HCON: Hardware feature register
	// Position of CARD_TYPE field.
	SDHOST_HCON_CARD_TYPE_Pos = 0x0
	// Bit mask of CARD_TYPE field.
	SDHOST_HCON_CARD_TYPE_Msk = 0x1
	// Bit CARD_TYPE.
	SDHOST_HCON_CARD_TYPE = 0x1
	// Position of CARD_NUM field.
	SDHOST_HCON_CARD_NUM_Pos = 0x1
	// Bit mask of CARD_NUM field.
	SDHOST_HCON_CARD_NUM_Msk = 0x3e
	// Position of BUS_TYPE field.
	SDHOST_HCON_BUS_TYPE_Pos = 0x6
	// Bit mask of BUS_TYPE field.
	SDHOST_HCON_BUS_TYPE_Msk = 0x40
	// Bit BUS_TYPE.
	SDHOST_HCON_BUS_TYPE = 0x40
	// Position of DATA_WIDTH field.
	SDHOST_HCON_DATA_WIDTH_Pos = 0x7
	// Bit mask of DATA_WIDTH field.
	SDHOST_HCON_DATA_WIDTH_Msk = 0x380
	// Position of ADDR_WIDTH field.
	SDHOST_HCON_ADDR_WIDTH_Pos = 0xa
	// Bit mask of ADDR_WIDTH field.
	SDHOST_HCON_ADDR_WIDTH_Msk = 0xfc00
	// Position of DMA_WIDTH field.
	SDHOST_HCON_DMA_WIDTH_Pos = 0x12
	// Bit mask of DMA_WIDTH field.
	SDHOST_HCON_DMA_WIDTH_Msk = 0x1c0000
	// Position of RAM_INDISE field.
	SDHOST_HCON_RAM_INDISE_Pos = 0x15
	// Bit mask of RAM_INDISE field.
	SDHOST_HCON_RAM_INDISE_Msk = 0x200000
	// Bit RAM_INDISE.
	SDHOST_HCON_RAM_INDISE = 0x200000
	// Position of HOLD field.
	SDHOST_HCON_HOLD_Pos = 0x16
	// Bit mask of HOLD field.
	SDHOST_HCON_HOLD_Msk = 0x400000
	// Bit HOLD.
	SDHOST_HCON_HOLD = 0x400000
	// Position of NUM_CLK_DIV field.
	SDHOST_HCON_NUM_CLK_DIV_Pos = 0x18
	// Bit mask of NUM_CLK_DIV field.
	SDHOST_HCON_NUM_CLK_DIV_Msk = 0x3000000

	// UHS: UHS-1 register
	// Position of DDR field.
	SDHOST_UHS_DDR_Pos = 0x10
	// Bit mask of DDR field.
	SDHOST_UHS_DDR_Msk = 0x30000

	// RST_N: Card reset register
	// Position of CARD_RESET field.
	SDHOST_RST_N_CARD_RESET_Pos = 0x0
	// Bit mask of CARD_RESET field.
	SDHOST_RST_N_CARD_RESET_Msk = 0x3

	// BMOD: Burst mode transfer configuration register
	// Position of SWR field.
	SDHOST_BMOD_SWR_Pos = 0x0
	// Bit mask of SWR field.
	SDHOST_BMOD_SWR_Msk = 0x1
	// Bit SWR.
	SDHOST_BMOD_SWR = 0x1
	// Position of FB field.
	SDHOST_BMOD_FB_Pos = 0x1
	// Bit mask of FB field.
	SDHOST_BMOD_FB_Msk = 0x2
	// Bit FB.
	SDHOST_BMOD_FB = 0x2
	// Position of DE field.
	SDHOST_BMOD_DE_Pos = 0x7
	// Bit mask of DE field.
	SDHOST_BMOD_DE_Msk = 0x80
	// Bit DE.
	SDHOST_BMOD_DE = 0x80
	// Position of PBL field.
	SDHOST_BMOD_PBL_Pos = 0x8
	// Bit mask of PBL field.
	SDHOST_BMOD_PBL_Msk = 0x700

	// PLDMND: Poll demand configuration register
	// Position of PD field.
	SDHOST_PLDMND_PD_Pos = 0x0
	// Bit mask of PD field.
	SDHOST_PLDMND_PD_Msk = 0xffffffff

	// DBADDR: Descriptor base address register
	// Position of DBADDR field.
	SDHOST_DBADDR_DBADDR_Pos = 0x0
	// Bit mask of DBADDR field.
	SDHOST_DBADDR_DBADDR_Msk = 0xffffffff

	// IDSTS: IDMAC status register
	// Position of TI field.
	SDHOST_IDSTS_TI_Pos = 0x0
	// Bit mask of TI field.
	SDHOST_IDSTS_TI_Msk = 0x1
	// Bit TI.
	SDHOST_IDSTS_TI = 0x1
	// Position of RI field.
	SDHOST_IDSTS_RI_Pos = 0x1
	// Bit mask of RI field.
	SDHOST_IDSTS_RI_Msk = 0x2
	// Bit RI.
	SDHOST_IDSTS_RI = 0x2
	// Position of FBE field.
	SDHOST_IDSTS_FBE_Pos = 0x2
	// Bit mask of FBE field.
	SDHOST_IDSTS_FBE_Msk = 0x4
	// Bit FBE.
	SDHOST_IDSTS_FBE = 0x4
	// Position of DU field.
	SDHOST_IDSTS_DU_Pos = 0x4
	// Bit mask of DU field.
	SDHOST_IDSTS_DU_Msk = 0x10
	// Bit DU.
	SDHOST_IDSTS_DU = 0x10
	// Position of CES field.
	SDHOST_IDSTS_CES_Pos = 0x5
	// Bit mask of CES field.
	SDHOST_IDSTS_CES_Msk = 0x20
	// Bit CES.
	SDHOST_IDSTS_CES = 0x20
	// Position of NIS field.
	SDHOST_IDSTS_NIS_Pos = 0x8
	// Bit mask of NIS field.
	SDHOST_IDSTS_NIS_Msk = 0x100
	// Bit NIS.
	SDHOST_IDSTS_NIS = 0x100
	// Position of AIS field.
	SDHOST_IDSTS_AIS_Pos = 0x9
	// Bit mask of AIS field.
	SDHOST_IDSTS_AIS_Msk = 0x200
	// Bit AIS.
	SDHOST_IDSTS_AIS = 0x200
	// Position of FBE_CODE field.
	SDHOST_IDSTS_FBE_CODE_Pos = 0xa
	// Bit mask of FBE_CODE field.
	SDHOST_IDSTS_FBE_CODE_Msk = 0x1c00
	// Position of FSM field.
	SDHOST_IDSTS_FSM_Pos = 0xd
	// Bit mask of FSM field.
	SDHOST_IDSTS_FSM_Msk = 0x1e000

	// IDINTEN: IDMAC interrupt enable register
	// Position of TI field.
	SDHOST_IDINTEN_TI_Pos = 0x0
	// Bit mask of TI field.
	SDHOST_IDINTEN_TI_Msk = 0x1
	// Bit TI.
	SDHOST_IDINTEN_TI = 0x1
	// Position of RI field.
	SDHOST_IDINTEN_RI_Pos = 0x1
	// Bit mask of RI field.
	SDHOST_IDINTEN_RI_Msk = 0x2
	// Bit RI.
	SDHOST_IDINTEN_RI = 0x2
	// Position of FBE field.
	SDHOST_IDINTEN_FBE_Pos = 0x2
	// Bit mask of FBE field.
	SDHOST_IDINTEN_FBE_Msk = 0x4
	// Bit FBE.
	SDHOST_IDINTEN_FBE = 0x4
	// Position of DU field.
	SDHOST_IDINTEN_DU_Pos = 0x4
	// Bit mask of DU field.
	SDHOST_IDINTEN_DU_Msk = 0x10
	// Bit DU.
	SDHOST_IDINTEN_DU = 0x10
	// Position of CES field.
	SDHOST_IDINTEN_CES_Pos = 0x5
	// Bit mask of CES field.
	SDHOST_IDINTEN_CES_Msk = 0x20
	// Bit CES.
	SDHOST_IDINTEN_CES = 0x20
	// Position of NI field.
	SDHOST_IDINTEN_NI_Pos = 0x8
	// Bit mask of NI field.
	SDHOST_IDINTEN_NI_Msk = 0x100
	// Bit NI.
	SDHOST_IDINTEN_NI = 0x100
	// Position of AI field.
	SDHOST_IDINTEN_AI_Pos = 0x9
	// Bit mask of AI field.
	SDHOST_IDINTEN_AI_Msk = 0x200
	// Bit AI.
	SDHOST_IDINTEN_AI = 0x200

	// DSCADDR: Host descriptor address pointer
	// Position of DSCADDR field.
	SDHOST_DSCADDR_DSCADDR_Pos = 0x0
	// Bit mask of DSCADDR field.
	SDHOST_DSCADDR_DSCADDR_Msk = 0xffffffff

	// BUFADDR: Host buffer address pointer register
	// Position of BUFADDR field.
	SDHOST_BUFADDR_BUFADDR_Pos = 0x0
	// Bit mask of BUFADDR field.
	SDHOST_BUFADDR_BUFADDR_Msk = 0xffffffff

	// CARDTHRCTL: Card Threshold Control register
	// Position of CARDRDTHREN field.
	SDHOST_CARDTHRCTL_CARDRDTHREN_Pos = 0x0
	// Bit mask of CARDRDTHREN field.
	SDHOST_CARDTHRCTL_CARDRDTHREN_Msk = 0x1
	// Bit CARDRDTHREN.
	SDHOST_CARDTHRCTL_CARDRDTHREN = 0x1
	// Position of CARDCLRINTEN field.
	SDHOST_CARDTHRCTL_CARDCLRINTEN_Pos = 0x1
	// Bit mask of CARDCLRINTEN field.
	SDHOST_CARDTHRCTL_CARDCLRINTEN_Msk = 0x2
	// Bit CARDCLRINTEN.
	SDHOST_CARDTHRCTL_CARDCLRINTEN = 0x2
	// Position of CARDWRTHREN field.
	SDHOST_CARDTHRCTL_CARDWRTHREN_Pos = 0x2
	// Bit mask of CARDWRTHREN field.
	SDHOST_CARDTHRCTL_CARDWRTHREN_Msk = 0x4
	// Bit CARDWRTHREN.
	SDHOST_CARDTHRCTL_CARDWRTHREN = 0x4
	// Position of CARDTHRESHOLD field.
	SDHOST_CARDTHRCTL_CARDTHRESHOLD_Pos = 0x10
	// Bit mask of CARDTHRESHOLD field.
	SDHOST_CARDTHRCTL_CARDTHRESHOLD_Msk = 0xffff0000

	// EMMCDDR: eMMC DDR register
	// Position of HALFSTARTBIT field.
	SDHOST_EMMCDDR_HALFSTARTBIT_Pos = 0x0
	// Bit mask of HALFSTARTBIT field.
	SDHOST_EMMCDDR_HALFSTARTBIT_Msk = 0x3
	// Position of HS400_MODE field.
	SDHOST_EMMCDDR_HS400_MODE_Pos = 0x1f
	// Bit mask of HS400_MODE field.
	SDHOST_EMMCDDR_HS400_MODE_Msk = 0x80000000
	// Bit HS400_MODE.
	SDHOST_EMMCDDR_HS400_MODE = 0x80000000

	// ENSHIFT: Enable Phase Shift register
	// Position of ENABLE_SHIFT field.
	SDHOST_ENSHIFT_ENABLE_SHIFT_Pos = 0x0
	// Bit mask of ENABLE_SHIFT field.
	SDHOST_ENSHIFT_ENABLE_SHIFT_Msk = 0xf

	// BUFFIFO: CPU write and read transmit data by FIFO
	// Position of BUFFIFO field.
	SDHOST_BUFFIFO_BUFFIFO_Pos = 0x0
	// Bit mask of BUFFIFO field.
	SDHOST_BUFFIFO_BUFFIFO_Msk = 0xffffffff

	// CLK_EDGE_SEL: SDIO control register.
	// Position of CCLKIN_EDGE_DRV_SEL field.
	SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL_Pos = 0x0
	// Bit mask of CCLKIN_EDGE_DRV_SEL field.
	SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_DRV_SEL_Msk = 0x7
	// Position of CCLKIN_EDGE_SAM_SEL field.
	SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL_Pos = 0x3
	// Bit mask of CCLKIN_EDGE_SAM_SEL field.
	SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SAM_SEL_Msk = 0x38
	// Position of CCLKIN_EDGE_SLF_SEL field.
	SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL_Pos = 0x6
	// Bit mask of CCLKIN_EDGE_SLF_SEL field.
	SDHOST_CLK_EDGE_SEL_CCLKIN_EDGE_SLF_SEL_Msk = 0x1c0
	// Position of CCLLKIN_EDGE_H field.
	SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_H_Pos = 0x9
	// Bit mask of CCLLKIN_EDGE_H field.
	SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_H_Msk = 0x1e00
	// Position of CCLLKIN_EDGE_L field.
	SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_L_Pos = 0xd
	// Bit mask of CCLLKIN_EDGE_L field.
	SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_L_Msk = 0x1e000
	// Position of CCLLKIN_EDGE_N field.
	SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_N_Pos = 0x11
	// Bit mask of CCLLKIN_EDGE_N field.
	SDHOST_CLK_EDGE_SEL_CCLLKIN_EDGE_N_Msk = 0x1e0000
	// Position of ESDIO_MODE field.
	SDHOST_CLK_EDGE_SEL_ESDIO_MODE_Pos = 0x15
	// Bit mask of ESDIO_MODE field.
	SDHOST_CLK_EDGE_SEL_ESDIO_MODE_Msk = 0x200000
	// Bit ESDIO_MODE.
	SDHOST_CLK_EDGE_SEL_ESDIO_MODE = 0x200000
	// Position of ESD_MODE field.
	SDHOST_CLK_EDGE_SEL_ESD_MODE_Pos = 0x16
	// Bit mask of ESD_MODE field.
	SDHOST_CLK_EDGE_SEL_ESD_MODE_Msk = 0x400000
	// Bit ESD_MODE.
	SDHOST_CLK_EDGE_SEL_ESD_MODE = 0x400000
	// Position of CCLK_EN field.
	SDHOST_CLK_EDGE_SEL_CCLK_EN_Pos = 0x17
	// Bit mask of CCLK_EN field.
	SDHOST_CLK_EDGE_SEL_CCLK_EN_Msk = 0x800000
	// Bit CCLK_EN.
	SDHOST_CLK_EDGE_SEL_CCLK_EN = 0x800000
	// Position of ULTRA_HIGH_SPEED_MODE field.
	SDHOST_CLK_EDGE_SEL_ULTRA_HIGH_SPEED_MODE_Pos = 0x18
	// Bit mask of ULTRA_HIGH_SPEED_MODE field.
	SDHOST_CLK_EDGE_SEL_ULTRA_HIGH_SPEED_MODE_Msk = 0x1000000
	// Bit ULTRA_HIGH_SPEED_MODE.
	SDHOST_CLK_EDGE_SEL_ULTRA_HIGH_SPEED_MODE = 0x1000000

	// RAW_INTS: SDIO raw ints register.
	// Position of RAW_INTS field.
	SDHOST_RAW_INTS_RAW_INTS_Pos = 0x0
	// Bit mask of RAW_INTS field.
	SDHOST_RAW_INTS_RAW_INTS_Msk = 0xffffffff

	// DLL_CLK_CONF: SDIO DLL clock control register.
	// Position of DLL_CCLK_IN_SLF_EN field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SLF_EN_Pos = 0x0
	// Bit mask of DLL_CCLK_IN_SLF_EN field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SLF_EN_Msk = 0x1
	// Bit DLL_CCLK_IN_SLF_EN.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SLF_EN = 0x1
	// Position of DLL_CCLK_IN_DRV_EN field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_DRV_EN_Pos = 0x1
	// Bit mask of DLL_CCLK_IN_DRV_EN field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_DRV_EN_Msk = 0x2
	// Bit DLL_CCLK_IN_DRV_EN.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_DRV_EN = 0x2
	// Position of DLL_CCLK_IN_SAM_EN field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SAM_EN_Pos = 0x2
	// Bit mask of DLL_CCLK_IN_SAM_EN field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SAM_EN_Msk = 0x4
	// Bit DLL_CCLK_IN_SAM_EN.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SAM_EN = 0x4
	// Position of DLL_CCLK_IN_SLF_PHASE field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SLF_PHASE_Pos = 0x3
	// Bit mask of DLL_CCLK_IN_SLF_PHASE field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SLF_PHASE_Msk = 0x1f8
	// Position of DLL_CCLK_IN_DRV_PHASE field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_DRV_PHASE_Pos = 0x9
	// Bit mask of DLL_CCLK_IN_DRV_PHASE field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_DRV_PHASE_Msk = 0x7e00
	// Position of DLL_CCLK_IN_SAM_PHASE field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SAM_PHASE_Pos = 0xf
	// Bit mask of DLL_CCLK_IN_SAM_PHASE field.
	SDHOST_DLL_CLK_CONF_DLL_CCLK_IN_SAM_PHASE_Msk = 0x1f8000

	// DLL_CONF: SDIO DLL configuration register.
	// Position of DLL_CAL_STOP field.
	SDHOST_DLL_CONF_DLL_CAL_STOP_Pos = 0x0
	// Bit mask of DLL_CAL_STOP field.
	SDHOST_DLL_CONF_DLL_CAL_STOP_Msk = 0x1
	// Bit DLL_CAL_STOP.
	SDHOST_DLL_CONF_DLL_CAL_STOP = 0x1
	// Position of DLL_CAL_END field.
	SDHOST_DLL_CONF_DLL_CAL_END_Pos = 0x1
	// Bit mask of DLL_CAL_END field.
	SDHOST_DLL_CONF_DLL_CAL_END_Msk = 0x2
	// Bit DLL_CAL_END.
	SDHOST_DLL_CONF_DLL_CAL_END = 0x2
)

// Constants for SHA: SHA (Secure Hash Algorithm) Accelerator
const (
	// MODE: Initial configuration register.
	// Position of MODE field.
	SHA_MODE_MODE_Pos = 0x0
	// Bit mask of MODE field.
	SHA_MODE_MODE_Msk = 0x7

	// T_STRING: SHA 512/t configuration register 0.
	// Position of T_STRING field.
	SHA_T_STRING_T_STRING_Pos = 0x0
	// Bit mask of T_STRING field.
	SHA_T_STRING_T_STRING_Msk = 0xffffffff

	// T_LENGTH: SHA 512/t configuration register 1.
	// Position of T_LENGTH field.
	SHA_T_LENGTH_T_LENGTH_Pos = 0x0
	// Bit mask of T_LENGTH field.
	SHA_T_LENGTH_T_LENGTH_Msk = 0x3f

	// DMA_BLOCK_NUM: DMA configuration register 0.
	// Position of DMA_BLOCK_NUM field.
	SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Pos = 0x0
	// Bit mask of DMA_BLOCK_NUM field.
	SHA_DMA_BLOCK_NUM_DMA_BLOCK_NUM_Msk = 0x3f

	// START: Typical SHA configuration register 0.
	// Position of START field.
	SHA_START_START_Pos = 0x1
	// Bit mask of START field.
	SHA_START_START_Msk = 0xfffffffe

	// CONTINUE: Typical SHA configuration register 1.
	// Position of CONTINUE field.
	SHA_CONTINUE_CONTINUE_Pos = 0x1
	// Bit mask of CONTINUE field.
	SHA_CONTINUE_CONTINUE_Msk = 0xfffffffe

	// BUSY: Busy register.
	// Position of STATE field.
	SHA_BUSY_STATE_Pos = 0x0
	// Bit mask of STATE field.
	SHA_BUSY_STATE_Msk = 0x1
	// Bit STATE.
	SHA_BUSY_STATE = 0x1

	// DMA_START: DMA configuration register 1.
	// Position of DMA_START field.
	SHA_DMA_START_DMA_START_Pos = 0x0
	// Bit mask of DMA_START field.
	SHA_DMA_START_DMA_START_Msk = 0x1
	// Bit DMA_START.
	SHA_DMA_START_DMA_START = 0x1

	// DMA_CONTINUE: DMA configuration register 2.
	// Position of DMA_CONTINUE field.
	SHA_DMA_CONTINUE_DMA_CONTINUE_Pos = 0x0
	// Bit mask of DMA_CONTINUE field.
	SHA_DMA_CONTINUE_DMA_CONTINUE_Msk = 0x1
	// Bit DMA_CONTINUE.
	SHA_DMA_CONTINUE_DMA_CONTINUE = 0x1

	// CLEAR_IRQ: Interrupt clear register.
	// Position of CLEAR_INTERRUPT field.
	SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Pos = 0x0
	// Bit mask of CLEAR_INTERRUPT field.
	SHA_CLEAR_IRQ_CLEAR_INTERRUPT_Msk = 0x1
	// Bit CLEAR_INTERRUPT.
	SHA_CLEAR_IRQ_CLEAR_INTERRUPT = 0x1

	// IRQ_ENA: Interrupt enable register.
	// Position of INTERRUPT_ENA field.
	SHA_IRQ_ENA_INTERRUPT_ENA_Pos = 0x0
	// Bit mask of INTERRUPT_ENA field.
	SHA_IRQ_ENA_INTERRUPT_ENA_Msk = 0x1
	// Bit INTERRUPT_ENA.
	SHA_IRQ_ENA_INTERRUPT_ENA = 0x1

	// DATE: Date register.
	// Position of DATE field.
	SHA_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	SHA_DATE_DATE_Msk = 0x3fffffff
)

// Constants for SOC_ETM: Event Task Matrix
const (
	// CH_ENA_AD0: Channel enable status register
	// Position of CH_ENA0 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA0_Pos = 0x0
	// Bit mask of CH_ENA0 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA0_Msk = 0x1
	// Bit CH_ENA0.
	SOC_ETM_CH_ENA_AD0_CH_ENA0 = 0x1
	// Position of CH_ENA1 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA1_Pos = 0x1
	// Bit mask of CH_ENA1 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA1_Msk = 0x2
	// Bit CH_ENA1.
	SOC_ETM_CH_ENA_AD0_CH_ENA1 = 0x2
	// Position of CH_ENA2 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA2_Pos = 0x2
	// Bit mask of CH_ENA2 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA2_Msk = 0x4
	// Bit CH_ENA2.
	SOC_ETM_CH_ENA_AD0_CH_ENA2 = 0x4
	// Position of CH_ENA3 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA3_Pos = 0x3
	// Bit mask of CH_ENA3 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA3_Msk = 0x8
	// Bit CH_ENA3.
	SOC_ETM_CH_ENA_AD0_CH_ENA3 = 0x8
	// Position of CH_ENA4 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA4_Pos = 0x4
	// Bit mask of CH_ENA4 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA4_Msk = 0x10
	// Bit CH_ENA4.
	SOC_ETM_CH_ENA_AD0_CH_ENA4 = 0x10
	// Position of CH_ENA5 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA5_Pos = 0x5
	// Bit mask of CH_ENA5 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA5_Msk = 0x20
	// Bit CH_ENA5.
	SOC_ETM_CH_ENA_AD0_CH_ENA5 = 0x20
	// Position of CH_ENA6 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA6_Pos = 0x6
	// Bit mask of CH_ENA6 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA6_Msk = 0x40
	// Bit CH_ENA6.
	SOC_ETM_CH_ENA_AD0_CH_ENA6 = 0x40
	// Position of CH_ENA7 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA7_Pos = 0x7
	// Bit mask of CH_ENA7 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA7_Msk = 0x80
	// Bit CH_ENA7.
	SOC_ETM_CH_ENA_AD0_CH_ENA7 = 0x80
	// Position of CH_ENA8 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA8_Pos = 0x8
	// Bit mask of CH_ENA8 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA8_Msk = 0x100
	// Bit CH_ENA8.
	SOC_ETM_CH_ENA_AD0_CH_ENA8 = 0x100
	// Position of CH_ENA9 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA9_Pos = 0x9
	// Bit mask of CH_ENA9 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA9_Msk = 0x200
	// Bit CH_ENA9.
	SOC_ETM_CH_ENA_AD0_CH_ENA9 = 0x200
	// Position of CH_ENA10 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA10_Pos = 0xa
	// Bit mask of CH_ENA10 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA10_Msk = 0x400
	// Bit CH_ENA10.
	SOC_ETM_CH_ENA_AD0_CH_ENA10 = 0x400
	// Position of CH_ENA11 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA11_Pos = 0xb
	// Bit mask of CH_ENA11 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA11_Msk = 0x800
	// Bit CH_ENA11.
	SOC_ETM_CH_ENA_AD0_CH_ENA11 = 0x800
	// Position of CH_ENA12 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA12_Pos = 0xc
	// Bit mask of CH_ENA12 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA12_Msk = 0x1000
	// Bit CH_ENA12.
	SOC_ETM_CH_ENA_AD0_CH_ENA12 = 0x1000
	// Position of CH_ENA13 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA13_Pos = 0xd
	// Bit mask of CH_ENA13 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA13_Msk = 0x2000
	// Bit CH_ENA13.
	SOC_ETM_CH_ENA_AD0_CH_ENA13 = 0x2000
	// Position of CH_ENA14 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA14_Pos = 0xe
	// Bit mask of CH_ENA14 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA14_Msk = 0x4000
	// Bit CH_ENA14.
	SOC_ETM_CH_ENA_AD0_CH_ENA14 = 0x4000
	// Position of CH_ENA15 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA15_Pos = 0xf
	// Bit mask of CH_ENA15 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA15_Msk = 0x8000
	// Bit CH_ENA15.
	SOC_ETM_CH_ENA_AD0_CH_ENA15 = 0x8000
	// Position of CH_ENA16 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA16_Pos = 0x10
	// Bit mask of CH_ENA16 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA16_Msk = 0x10000
	// Bit CH_ENA16.
	SOC_ETM_CH_ENA_AD0_CH_ENA16 = 0x10000
	// Position of CH_ENA17 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA17_Pos = 0x11
	// Bit mask of CH_ENA17 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA17_Msk = 0x20000
	// Bit CH_ENA17.
	SOC_ETM_CH_ENA_AD0_CH_ENA17 = 0x20000
	// Position of CH_ENA18 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA18_Pos = 0x12
	// Bit mask of CH_ENA18 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA18_Msk = 0x40000
	// Bit CH_ENA18.
	SOC_ETM_CH_ENA_AD0_CH_ENA18 = 0x40000
	// Position of CH_ENA19 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA19_Pos = 0x13
	// Bit mask of CH_ENA19 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA19_Msk = 0x80000
	// Bit CH_ENA19.
	SOC_ETM_CH_ENA_AD0_CH_ENA19 = 0x80000
	// Position of CH_ENA20 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA20_Pos = 0x14
	// Bit mask of CH_ENA20 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA20_Msk = 0x100000
	// Bit CH_ENA20.
	SOC_ETM_CH_ENA_AD0_CH_ENA20 = 0x100000
	// Position of CH_ENA21 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA21_Pos = 0x15
	// Bit mask of CH_ENA21 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA21_Msk = 0x200000
	// Bit CH_ENA21.
	SOC_ETM_CH_ENA_AD0_CH_ENA21 = 0x200000
	// Position of CH_ENA22 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA22_Pos = 0x16
	// Bit mask of CH_ENA22 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA22_Msk = 0x400000
	// Bit CH_ENA22.
	SOC_ETM_CH_ENA_AD0_CH_ENA22 = 0x400000
	// Position of CH_ENA23 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA23_Pos = 0x17
	// Bit mask of CH_ENA23 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA23_Msk = 0x800000
	// Bit CH_ENA23.
	SOC_ETM_CH_ENA_AD0_CH_ENA23 = 0x800000
	// Position of CH_ENA24 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA24_Pos = 0x18
	// Bit mask of CH_ENA24 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA24_Msk = 0x1000000
	// Bit CH_ENA24.
	SOC_ETM_CH_ENA_AD0_CH_ENA24 = 0x1000000
	// Position of CH_ENA25 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA25_Pos = 0x19
	// Bit mask of CH_ENA25 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA25_Msk = 0x2000000
	// Bit CH_ENA25.
	SOC_ETM_CH_ENA_AD0_CH_ENA25 = 0x2000000
	// Position of CH_ENA26 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA26_Pos = 0x1a
	// Bit mask of CH_ENA26 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA26_Msk = 0x4000000
	// Bit CH_ENA26.
	SOC_ETM_CH_ENA_AD0_CH_ENA26 = 0x4000000
	// Position of CH_ENA27 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA27_Pos = 0x1b
	// Bit mask of CH_ENA27 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA27_Msk = 0x8000000
	// Bit CH_ENA27.
	SOC_ETM_CH_ENA_AD0_CH_ENA27 = 0x8000000
	// Position of CH_ENA28 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA28_Pos = 0x1c
	// Bit mask of CH_ENA28 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA28_Msk = 0x10000000
	// Bit CH_ENA28.
	SOC_ETM_CH_ENA_AD0_CH_ENA28 = 0x10000000
	// Position of CH_ENA29 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA29_Pos = 0x1d
	// Bit mask of CH_ENA29 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA29_Msk = 0x20000000
	// Bit CH_ENA29.
	SOC_ETM_CH_ENA_AD0_CH_ENA29 = 0x20000000
	// Position of CH_ENA30 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA30_Pos = 0x1e
	// Bit mask of CH_ENA30 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA30_Msk = 0x40000000
	// Bit CH_ENA30.
	SOC_ETM_CH_ENA_AD0_CH_ENA30 = 0x40000000
	// Position of CH_ENA31 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA31_Pos = 0x1f
	// Bit mask of CH_ENA31 field.
	SOC_ETM_CH_ENA_AD0_CH_ENA31_Msk = 0x80000000
	// Bit CH_ENA31.
	SOC_ETM_CH_ENA_AD0_CH_ENA31 = 0x80000000

	// CH_ENA_AD0_SET: Channel enable set register
	// Position of CH_SET0 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET0_Pos = 0x0
	// Bit mask of CH_SET0 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET0_Msk = 0x1
	// Bit CH_SET0.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET0 = 0x1
	// Position of CH_SET1 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET1_Pos = 0x1
	// Bit mask of CH_SET1 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET1_Msk = 0x2
	// Bit CH_SET1.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET1 = 0x2
	// Position of CH_SET2 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET2_Pos = 0x2
	// Bit mask of CH_SET2 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET2_Msk = 0x4
	// Bit CH_SET2.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET2 = 0x4
	// Position of CH_SET3 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET3_Pos = 0x3
	// Bit mask of CH_SET3 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET3_Msk = 0x8
	// Bit CH_SET3.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET3 = 0x8
	// Position of CH_SET4 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET4_Pos = 0x4
	// Bit mask of CH_SET4 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET4_Msk = 0x10
	// Bit CH_SET4.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET4 = 0x10
	// Position of CH_SET5 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET5_Pos = 0x5
	// Bit mask of CH_SET5 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET5_Msk = 0x20
	// Bit CH_SET5.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET5 = 0x20
	// Position of CH_SET6 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET6_Pos = 0x6
	// Bit mask of CH_SET6 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET6_Msk = 0x40
	// Bit CH_SET6.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET6 = 0x40
	// Position of CH_SET7 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET7_Pos = 0x7
	// Bit mask of CH_SET7 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET7_Msk = 0x80
	// Bit CH_SET7.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET7 = 0x80
	// Position of CH_SET8 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET8_Pos = 0x8
	// Bit mask of CH_SET8 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET8_Msk = 0x100
	// Bit CH_SET8.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET8 = 0x100
	// Position of CH_SET9 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET9_Pos = 0x9
	// Bit mask of CH_SET9 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET9_Msk = 0x200
	// Bit CH_SET9.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET9 = 0x200
	// Position of CH_SET10 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET10_Pos = 0xa
	// Bit mask of CH_SET10 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET10_Msk = 0x400
	// Bit CH_SET10.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET10 = 0x400
	// Position of CH_SET11 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET11_Pos = 0xb
	// Bit mask of CH_SET11 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET11_Msk = 0x800
	// Bit CH_SET11.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET11 = 0x800
	// Position of CH_SET12 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET12_Pos = 0xc
	// Bit mask of CH_SET12 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET12_Msk = 0x1000
	// Bit CH_SET12.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET12 = 0x1000
	// Position of CH_SET13 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET13_Pos = 0xd
	// Bit mask of CH_SET13 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET13_Msk = 0x2000
	// Bit CH_SET13.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET13 = 0x2000
	// Position of CH_SET14 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET14_Pos = 0xe
	// Bit mask of CH_SET14 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET14_Msk = 0x4000
	// Bit CH_SET14.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET14 = 0x4000
	// Position of CH_SET15 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET15_Pos = 0xf
	// Bit mask of CH_SET15 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET15_Msk = 0x8000
	// Bit CH_SET15.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET15 = 0x8000
	// Position of CH_SET16 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET16_Pos = 0x10
	// Bit mask of CH_SET16 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET16_Msk = 0x10000
	// Bit CH_SET16.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET16 = 0x10000
	// Position of CH_SET17 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET17_Pos = 0x11
	// Bit mask of CH_SET17 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET17_Msk = 0x20000
	// Bit CH_SET17.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET17 = 0x20000
	// Position of CH_SET18 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET18_Pos = 0x12
	// Bit mask of CH_SET18 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET18_Msk = 0x40000
	// Bit CH_SET18.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET18 = 0x40000
	// Position of CH_SET19 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET19_Pos = 0x13
	// Bit mask of CH_SET19 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET19_Msk = 0x80000
	// Bit CH_SET19.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET19 = 0x80000
	// Position of CH_SET20 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET20_Pos = 0x14
	// Bit mask of CH_SET20 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET20_Msk = 0x100000
	// Bit CH_SET20.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET20 = 0x100000
	// Position of CH_SET21 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET21_Pos = 0x15
	// Bit mask of CH_SET21 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET21_Msk = 0x200000
	// Bit CH_SET21.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET21 = 0x200000
	// Position of CH_SET22 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET22_Pos = 0x16
	// Bit mask of CH_SET22 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET22_Msk = 0x400000
	// Bit CH_SET22.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET22 = 0x400000
	// Position of CH_SET23 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET23_Pos = 0x17
	// Bit mask of CH_SET23 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET23_Msk = 0x800000
	// Bit CH_SET23.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET23 = 0x800000
	// Position of CH_SET24 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET24_Pos = 0x18
	// Bit mask of CH_SET24 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET24_Msk = 0x1000000
	// Bit CH_SET24.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET24 = 0x1000000
	// Position of CH_SET25 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET25_Pos = 0x19
	// Bit mask of CH_SET25 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET25_Msk = 0x2000000
	// Bit CH_SET25.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET25 = 0x2000000
	// Position of CH_SET26 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET26_Pos = 0x1a
	// Bit mask of CH_SET26 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET26_Msk = 0x4000000
	// Bit CH_SET26.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET26 = 0x4000000
	// Position of CH_SET27 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET27_Pos = 0x1b
	// Bit mask of CH_SET27 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET27_Msk = 0x8000000
	// Bit CH_SET27.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET27 = 0x8000000
	// Position of CH_SET28 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET28_Pos = 0x1c
	// Bit mask of CH_SET28 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET28_Msk = 0x10000000
	// Bit CH_SET28.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET28 = 0x10000000
	// Position of CH_SET29 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET29_Pos = 0x1d
	// Bit mask of CH_SET29 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET29_Msk = 0x20000000
	// Bit CH_SET29.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET29 = 0x20000000
	// Position of CH_SET30 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET30_Pos = 0x1e
	// Bit mask of CH_SET30 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET30_Msk = 0x40000000
	// Bit CH_SET30.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET30 = 0x40000000
	// Position of CH_SET31 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET31_Pos = 0x1f
	// Bit mask of CH_SET31 field.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET31_Msk = 0x80000000
	// Bit CH_SET31.
	SOC_ETM_CH_ENA_AD0_SET_CH_SET31 = 0x80000000

	// CH_ENA_AD0_CLR: Channel enable clear register
	// Position of CH_CLR0 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0_Pos = 0x0
	// Bit mask of CH_CLR0 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0_Msk = 0x1
	// Bit CH_CLR0.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR0 = 0x1
	// Position of CH_CLR1 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1_Pos = 0x1
	// Bit mask of CH_CLR1 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1_Msk = 0x2
	// Bit CH_CLR1.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR1 = 0x2
	// Position of CH_CLR2 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2_Pos = 0x2
	// Bit mask of CH_CLR2 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2_Msk = 0x4
	// Bit CH_CLR2.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR2 = 0x4
	// Position of CH_CLR3 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3_Pos = 0x3
	// Bit mask of CH_CLR3 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3_Msk = 0x8
	// Bit CH_CLR3.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR3 = 0x8
	// Position of CH_CLR4 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4_Pos = 0x4
	// Bit mask of CH_CLR4 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4_Msk = 0x10
	// Bit CH_CLR4.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR4 = 0x10
	// Position of CH_CLR5 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5_Pos = 0x5
	// Bit mask of CH_CLR5 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5_Msk = 0x20
	// Bit CH_CLR5.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR5 = 0x20
	// Position of CH_CLR6 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6_Pos = 0x6
	// Bit mask of CH_CLR6 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6_Msk = 0x40
	// Bit CH_CLR6.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR6 = 0x40
	// Position of CH_CLR7 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7_Pos = 0x7
	// Bit mask of CH_CLR7 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7_Msk = 0x80
	// Bit CH_CLR7.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR7 = 0x80
	// Position of CH_CLR8 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8_Pos = 0x8
	// Bit mask of CH_CLR8 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8_Msk = 0x100
	// Bit CH_CLR8.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR8 = 0x100
	// Position of CH_CLR9 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9_Pos = 0x9
	// Bit mask of CH_CLR9 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9_Msk = 0x200
	// Bit CH_CLR9.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR9 = 0x200
	// Position of CH_CLR10 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10_Pos = 0xa
	// Bit mask of CH_CLR10 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10_Msk = 0x400
	// Bit CH_CLR10.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR10 = 0x400
	// Position of CH_CLR11 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11_Pos = 0xb
	// Bit mask of CH_CLR11 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11_Msk = 0x800
	// Bit CH_CLR11.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR11 = 0x800
	// Position of CH_CLR12 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12_Pos = 0xc
	// Bit mask of CH_CLR12 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12_Msk = 0x1000
	// Bit CH_CLR12.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR12 = 0x1000
	// Position of CH_CLR13 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13_Pos = 0xd
	// Bit mask of CH_CLR13 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13_Msk = 0x2000
	// Bit CH_CLR13.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR13 = 0x2000
	// Position of CH_CLR14 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14_Pos = 0xe
	// Bit mask of CH_CLR14 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14_Msk = 0x4000
	// Bit CH_CLR14.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR14 = 0x4000
	// Position of CH_CLR15 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15_Pos = 0xf
	// Bit mask of CH_CLR15 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15_Msk = 0x8000
	// Bit CH_CLR15.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR15 = 0x8000
	// Position of CH_CLR16 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16_Pos = 0x10
	// Bit mask of CH_CLR16 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16_Msk = 0x10000
	// Bit CH_CLR16.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR16 = 0x10000
	// Position of CH_CLR17 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17_Pos = 0x11
	// Bit mask of CH_CLR17 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17_Msk = 0x20000
	// Bit CH_CLR17.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR17 = 0x20000
	// Position of CH_CLR18 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18_Pos = 0x12
	// Bit mask of CH_CLR18 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18_Msk = 0x40000
	// Bit CH_CLR18.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR18 = 0x40000
	// Position of CH_CLR19 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19_Pos = 0x13
	// Bit mask of CH_CLR19 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19_Msk = 0x80000
	// Bit CH_CLR19.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR19 = 0x80000
	// Position of CH_CLR20 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20_Pos = 0x14
	// Bit mask of CH_CLR20 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20_Msk = 0x100000
	// Bit CH_CLR20.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR20 = 0x100000
	// Position of CH_CLR21 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21_Pos = 0x15
	// Bit mask of CH_CLR21 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21_Msk = 0x200000
	// Bit CH_CLR21.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR21 = 0x200000
	// Position of CH_CLR22 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22_Pos = 0x16
	// Bit mask of CH_CLR22 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22_Msk = 0x400000
	// Bit CH_CLR22.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR22 = 0x400000
	// Position of CH_CLR23 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23_Pos = 0x17
	// Bit mask of CH_CLR23 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23_Msk = 0x800000
	// Bit CH_CLR23.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR23 = 0x800000
	// Position of CH_CLR24 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24_Pos = 0x18
	// Bit mask of CH_CLR24 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24_Msk = 0x1000000
	// Bit CH_CLR24.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR24 = 0x1000000
	// Position of CH_CLR25 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25_Pos = 0x19
	// Bit mask of CH_CLR25 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25_Msk = 0x2000000
	// Bit CH_CLR25.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR25 = 0x2000000
	// Position of CH_CLR26 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26_Pos = 0x1a
	// Bit mask of CH_CLR26 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26_Msk = 0x4000000
	// Bit CH_CLR26.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR26 = 0x4000000
	// Position of CH_CLR27 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27_Pos = 0x1b
	// Bit mask of CH_CLR27 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27_Msk = 0x8000000
	// Bit CH_CLR27.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR27 = 0x8000000
	// Position of CH_CLR28 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28_Pos = 0x1c
	// Bit mask of CH_CLR28 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28_Msk = 0x10000000
	// Bit CH_CLR28.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR28 = 0x10000000
	// Position of CH_CLR29 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29_Pos = 0x1d
	// Bit mask of CH_CLR29 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29_Msk = 0x20000000
	// Bit CH_CLR29.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR29 = 0x20000000
	// Position of CH_CLR30 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30_Pos = 0x1e
	// Bit mask of CH_CLR30 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30_Msk = 0x40000000
	// Bit CH_CLR30.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR30 = 0x40000000
	// Position of CH_CLR31 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31_Pos = 0x1f
	// Bit mask of CH_CLR31 field.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31_Msk = 0x80000000
	// Bit CH_CLR31.
	SOC_ETM_CH_ENA_AD0_CLR_CH_CLR31 = 0x80000000

	// CH_ENA_AD1: Channel enable status register
	// Position of CH_ENA32 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA32_Pos = 0x0
	// Bit mask of CH_ENA32 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA32_Msk = 0x1
	// Bit CH_ENA32.
	SOC_ETM_CH_ENA_AD1_CH_ENA32 = 0x1
	// Position of CH_ENA33 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA33_Pos = 0x1
	// Bit mask of CH_ENA33 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA33_Msk = 0x2
	// Bit CH_ENA33.
	SOC_ETM_CH_ENA_AD1_CH_ENA33 = 0x2
	// Position of CH_ENA34 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA34_Pos = 0x2
	// Bit mask of CH_ENA34 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA34_Msk = 0x4
	// Bit CH_ENA34.
	SOC_ETM_CH_ENA_AD1_CH_ENA34 = 0x4
	// Position of CH_ENA35 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA35_Pos = 0x3
	// Bit mask of CH_ENA35 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA35_Msk = 0x8
	// Bit CH_ENA35.
	SOC_ETM_CH_ENA_AD1_CH_ENA35 = 0x8
	// Position of CH_ENA36 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA36_Pos = 0x4
	// Bit mask of CH_ENA36 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA36_Msk = 0x10
	// Bit CH_ENA36.
	SOC_ETM_CH_ENA_AD1_CH_ENA36 = 0x10
	// Position of CH_ENA37 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA37_Pos = 0x5
	// Bit mask of CH_ENA37 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA37_Msk = 0x20
	// Bit CH_ENA37.
	SOC_ETM_CH_ENA_AD1_CH_ENA37 = 0x20
	// Position of CH_ENA38 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA38_Pos = 0x6
	// Bit mask of CH_ENA38 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA38_Msk = 0x40
	// Bit CH_ENA38.
	SOC_ETM_CH_ENA_AD1_CH_ENA38 = 0x40
	// Position of CH_ENA39 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA39_Pos = 0x7
	// Bit mask of CH_ENA39 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA39_Msk = 0x80
	// Bit CH_ENA39.
	SOC_ETM_CH_ENA_AD1_CH_ENA39 = 0x80
	// Position of CH_ENA40 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA40_Pos = 0x8
	// Bit mask of CH_ENA40 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA40_Msk = 0x100
	// Bit CH_ENA40.
	SOC_ETM_CH_ENA_AD1_CH_ENA40 = 0x100
	// Position of CH_ENA41 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA41_Pos = 0x9
	// Bit mask of CH_ENA41 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA41_Msk = 0x200
	// Bit CH_ENA41.
	SOC_ETM_CH_ENA_AD1_CH_ENA41 = 0x200
	// Position of CH_ENA42 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA42_Pos = 0xa
	// Bit mask of CH_ENA42 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA42_Msk = 0x400
	// Bit CH_ENA42.
	SOC_ETM_CH_ENA_AD1_CH_ENA42 = 0x400
	// Position of CH_ENA43 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA43_Pos = 0xb
	// Bit mask of CH_ENA43 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA43_Msk = 0x800
	// Bit CH_ENA43.
	SOC_ETM_CH_ENA_AD1_CH_ENA43 = 0x800
	// Position of CH_ENA44 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA44_Pos = 0xc
	// Bit mask of CH_ENA44 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA44_Msk = 0x1000
	// Bit CH_ENA44.
	SOC_ETM_CH_ENA_AD1_CH_ENA44 = 0x1000
	// Position of CH_ENA45 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA45_Pos = 0xd
	// Bit mask of CH_ENA45 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA45_Msk = 0x2000
	// Bit CH_ENA45.
	SOC_ETM_CH_ENA_AD1_CH_ENA45 = 0x2000
	// Position of CH_ENA46 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA46_Pos = 0xe
	// Bit mask of CH_ENA46 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA46_Msk = 0x4000
	// Bit CH_ENA46.
	SOC_ETM_CH_ENA_AD1_CH_ENA46 = 0x4000
	// Position of CH_ENA47 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA47_Pos = 0xf
	// Bit mask of CH_ENA47 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA47_Msk = 0x8000
	// Bit CH_ENA47.
	SOC_ETM_CH_ENA_AD1_CH_ENA47 = 0x8000
	// Position of CH_ENA48 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA48_Pos = 0x10
	// Bit mask of CH_ENA48 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA48_Msk = 0x10000
	// Bit CH_ENA48.
	SOC_ETM_CH_ENA_AD1_CH_ENA48 = 0x10000
	// Position of CH_ENA49 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA49_Pos = 0x11
	// Bit mask of CH_ENA49 field.
	SOC_ETM_CH_ENA_AD1_CH_ENA49_Msk = 0x20000
	// Bit CH_ENA49.
	SOC_ETM_CH_ENA_AD1_CH_ENA49 = 0x20000

	// CH_ENA_AD1_SET: Channel enable set register
	// Position of CH_SET32 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET32_Pos = 0x0
	// Bit mask of CH_SET32 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET32_Msk = 0x1
	// Bit CH_SET32.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET32 = 0x1
	// Position of CH_SET33 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET33_Pos = 0x1
	// Bit mask of CH_SET33 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET33_Msk = 0x2
	// Bit CH_SET33.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET33 = 0x2
	// Position of CH_SET34 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET34_Pos = 0x2
	// Bit mask of CH_SET34 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET34_Msk = 0x4
	// Bit CH_SET34.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET34 = 0x4
	// Position of CH_SET35 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET35_Pos = 0x3
	// Bit mask of CH_SET35 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET35_Msk = 0x8
	// Bit CH_SET35.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET35 = 0x8
	// Position of CH_SET36 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET36_Pos = 0x4
	// Bit mask of CH_SET36 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET36_Msk = 0x10
	// Bit CH_SET36.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET36 = 0x10
	// Position of CH_SET37 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET37_Pos = 0x5
	// Bit mask of CH_SET37 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET37_Msk = 0x20
	// Bit CH_SET37.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET37 = 0x20
	// Position of CH_SET38 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET38_Pos = 0x6
	// Bit mask of CH_SET38 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET38_Msk = 0x40
	// Bit CH_SET38.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET38 = 0x40
	// Position of CH_SET39 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET39_Pos = 0x7
	// Bit mask of CH_SET39 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET39_Msk = 0x80
	// Bit CH_SET39.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET39 = 0x80
	// Position of CH_SET40 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET40_Pos = 0x8
	// Bit mask of CH_SET40 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET40_Msk = 0x100
	// Bit CH_SET40.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET40 = 0x100
	// Position of CH_SET41 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET41_Pos = 0x9
	// Bit mask of CH_SET41 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET41_Msk = 0x200
	// Bit CH_SET41.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET41 = 0x200
	// Position of CH_SET42 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET42_Pos = 0xa
	// Bit mask of CH_SET42 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET42_Msk = 0x400
	// Bit CH_SET42.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET42 = 0x400
	// Position of CH_SET43 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET43_Pos = 0xb
	// Bit mask of CH_SET43 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET43_Msk = 0x800
	// Bit CH_SET43.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET43 = 0x800
	// Position of CH_SET44 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET44_Pos = 0xc
	// Bit mask of CH_SET44 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET44_Msk = 0x1000
	// Bit CH_SET44.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET44 = 0x1000
	// Position of CH_SET45 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET45_Pos = 0xd
	// Bit mask of CH_SET45 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET45_Msk = 0x2000
	// Bit CH_SET45.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET45 = 0x2000
	// Position of CH_SET46 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET46_Pos = 0xe
	// Bit mask of CH_SET46 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET46_Msk = 0x4000
	// Bit CH_SET46.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET46 = 0x4000
	// Position of CH_SET47 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET47_Pos = 0xf
	// Bit mask of CH_SET47 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET47_Msk = 0x8000
	// Bit CH_SET47.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET47 = 0x8000
	// Position of CH_SET48 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET48_Pos = 0x10
	// Bit mask of CH_SET48 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET48_Msk = 0x10000
	// Bit CH_SET48.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET48 = 0x10000
	// Position of CH_SET49 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET49_Pos = 0x11
	// Bit mask of CH_SET49 field.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET49_Msk = 0x20000
	// Bit CH_SET49.
	SOC_ETM_CH_ENA_AD1_SET_CH_SET49 = 0x20000

	// CH_ENA_AD1_CLR: Channel enable clear register
	// Position of CH_CLR32 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32_Pos = 0x0
	// Bit mask of CH_CLR32 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32_Msk = 0x1
	// Bit CH_CLR32.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR32 = 0x1
	// Position of CH_CLR33 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33_Pos = 0x1
	// Bit mask of CH_CLR33 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33_Msk = 0x2
	// Bit CH_CLR33.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR33 = 0x2
	// Position of CH_CLR34 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34_Pos = 0x2
	// Bit mask of CH_CLR34 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34_Msk = 0x4
	// Bit CH_CLR34.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR34 = 0x4
	// Position of CH_CLR35 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35_Pos = 0x3
	// Bit mask of CH_CLR35 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35_Msk = 0x8
	// Bit CH_CLR35.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR35 = 0x8
	// Position of CH_CLR36 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36_Pos = 0x4
	// Bit mask of CH_CLR36 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36_Msk = 0x10
	// Bit CH_CLR36.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR36 = 0x10
	// Position of CH_CLR37 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37_Pos = 0x5
	// Bit mask of CH_CLR37 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37_Msk = 0x20
	// Bit CH_CLR37.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR37 = 0x20
	// Position of CH_CLR38 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38_Pos = 0x6
	// Bit mask of CH_CLR38 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38_Msk = 0x40
	// Bit CH_CLR38.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR38 = 0x40
	// Position of CH_CLR39 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39_Pos = 0x7
	// Bit mask of CH_CLR39 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39_Msk = 0x80
	// Bit CH_CLR39.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR39 = 0x80
	// Position of CH_CLR40 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40_Pos = 0x8
	// Bit mask of CH_CLR40 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40_Msk = 0x100
	// Bit CH_CLR40.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR40 = 0x100
	// Position of CH_CLR41 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41_Pos = 0x9
	// Bit mask of CH_CLR41 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41_Msk = 0x200
	// Bit CH_CLR41.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR41 = 0x200
	// Position of CH_CLR42 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42_Pos = 0xa
	// Bit mask of CH_CLR42 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42_Msk = 0x400
	// Bit CH_CLR42.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR42 = 0x400
	// Position of CH_CLR43 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43_Pos = 0xb
	// Bit mask of CH_CLR43 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43_Msk = 0x800
	// Bit CH_CLR43.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR43 = 0x800
	// Position of CH_CLR44 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44_Pos = 0xc
	// Bit mask of CH_CLR44 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44_Msk = 0x1000
	// Bit CH_CLR44.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR44 = 0x1000
	// Position of CH_CLR45 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45_Pos = 0xd
	// Bit mask of CH_CLR45 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45_Msk = 0x2000
	// Bit CH_CLR45.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR45 = 0x2000
	// Position of CH_CLR46 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46_Pos = 0xe
	// Bit mask of CH_CLR46 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46_Msk = 0x4000
	// Bit CH_CLR46.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR46 = 0x4000
	// Position of CH_CLR47 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47_Pos = 0xf
	// Bit mask of CH_CLR47 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47_Msk = 0x8000
	// Bit CH_CLR47.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR47 = 0x8000
	// Position of CH_CLR48 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48_Pos = 0x10
	// Bit mask of CH_CLR48 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48_Msk = 0x10000
	// Bit CH_CLR48.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR48 = 0x10000
	// Position of CH_CLR49 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49_Pos = 0x11
	// Bit mask of CH_CLR49 field.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49_Msk = 0x20000
	// Bit CH_CLR49.
	SOC_ETM_CH_ENA_AD1_CLR_CH_CLR49 = 0x20000

	// CH0_EVT_ID: Channel0 event id register
	// Position of CH0_EVT_ID field.
	SOC_ETM_CH0_EVT_ID_CH0_EVT_ID_Pos = 0x0
	// Bit mask of CH0_EVT_ID field.
	SOC_ETM_CH0_EVT_ID_CH0_EVT_ID_Msk = 0xff

	// CH0_TASK_ID: Channel0 task id register
	// Position of CH0_TASK_ID field.
	SOC_ETM_CH0_TASK_ID_CH0_TASK_ID_Pos = 0x0
	// Bit mask of CH0_TASK_ID field.
	SOC_ETM_CH0_TASK_ID_CH0_TASK_ID_Msk = 0xff

	// CH1_EVT_ID: Channel1 event id register
	// Position of CH1_EVT_ID field.
	SOC_ETM_CH1_EVT_ID_CH1_EVT_ID_Pos = 0x0
	// Bit mask of CH1_EVT_ID field.
	SOC_ETM_CH1_EVT_ID_CH1_EVT_ID_Msk = 0xff

	// CH1_TASK_ID: Channel1 task id register
	// Position of CH1_TASK_ID field.
	SOC_ETM_CH1_TASK_ID_CH1_TASK_ID_Pos = 0x0
	// Bit mask of CH1_TASK_ID field.
	SOC_ETM_CH1_TASK_ID_CH1_TASK_ID_Msk = 0xff

	// CH2_EVT_ID: Channel2 event id register
	// Position of CH2_EVT_ID field.
	SOC_ETM_CH2_EVT_ID_CH2_EVT_ID_Pos = 0x0
	// Bit mask of CH2_EVT_ID field.
	SOC_ETM_CH2_EVT_ID_CH2_EVT_ID_Msk = 0xff

	// CH2_TASK_ID: Channel2 task id register
	// Position of CH2_TASK_ID field.
	SOC_ETM_CH2_TASK_ID_CH2_TASK_ID_Pos = 0x0
	// Bit mask of CH2_TASK_ID field.
	SOC_ETM_CH2_TASK_ID_CH2_TASK_ID_Msk = 0xff

	// CH3_EVT_ID: Channel3 event id register
	// Position of CH3_EVT_ID field.
	SOC_ETM_CH3_EVT_ID_CH3_EVT_ID_Pos = 0x0
	// Bit mask of CH3_EVT_ID field.
	SOC_ETM_CH3_EVT_ID_CH3_EVT_ID_Msk = 0xff

	// CH3_TASK_ID: Channel3 task id register
	// Position of CH3_TASK_ID field.
	SOC_ETM_CH3_TASK_ID_CH3_TASK_ID_Pos = 0x0
	// Bit mask of CH3_TASK_ID field.
	SOC_ETM_CH3_TASK_ID_CH3_TASK_ID_Msk = 0xff

	// CH4_EVT_ID: Channel4 event id register
	// Position of CH4_EVT_ID field.
	SOC_ETM_CH4_EVT_ID_CH4_EVT_ID_Pos = 0x0
	// Bit mask of CH4_EVT_ID field.
	SOC_ETM_CH4_EVT_ID_CH4_EVT_ID_Msk = 0xff

	// CH4_TASK_ID: Channel4 task id register
	// Position of CH4_TASK_ID field.
	SOC_ETM_CH4_TASK_ID_CH4_TASK_ID_Pos = 0x0
	// Bit mask of CH4_TASK_ID field.
	SOC_ETM_CH4_TASK_ID_CH4_TASK_ID_Msk = 0xff

	// CH5_EVT_ID: Channel5 event id register
	// Position of CH5_EVT_ID field.
	SOC_ETM_CH5_EVT_ID_CH5_EVT_ID_Pos = 0x0
	// Bit mask of CH5_EVT_ID field.
	SOC_ETM_CH5_EVT_ID_CH5_EVT_ID_Msk = 0xff

	// CH5_TASK_ID: Channel5 task id register
	// Position of CH5_TASK_ID field.
	SOC_ETM_CH5_TASK_ID_CH5_TASK_ID_Pos = 0x0
	// Bit mask of CH5_TASK_ID field.
	SOC_ETM_CH5_TASK_ID_CH5_TASK_ID_Msk = 0xff

	// CH6_EVT_ID: Channel6 event id register
	// Position of CH6_EVT_ID field.
	SOC_ETM_CH6_EVT_ID_CH6_EVT_ID_Pos = 0x0
	// Bit mask of CH6_EVT_ID field.
	SOC_ETM_CH6_EVT_ID_CH6_EVT_ID_Msk = 0xff

	// CH6_TASK_ID: Channel6 task id register
	// Position of CH6_TASK_ID field.
	SOC_ETM_CH6_TASK_ID_CH6_TASK_ID_Pos = 0x0
	// Bit mask of CH6_TASK_ID field.
	SOC_ETM_CH6_TASK_ID_CH6_TASK_ID_Msk = 0xff

	// CH7_EVT_ID: Channel7 event id register
	// Position of CH7_EVT_ID field.
	SOC_ETM_CH7_EVT_ID_CH7_EVT_ID_Pos = 0x0
	// Bit mask of CH7_EVT_ID field.
	SOC_ETM_CH7_EVT_ID_CH7_EVT_ID_Msk = 0xff

	// CH7_TASK_ID: Channel7 task id register
	// Position of CH7_TASK_ID field.
	SOC_ETM_CH7_TASK_ID_CH7_TASK_ID_Pos = 0x0
	// Bit mask of CH7_TASK_ID field.
	SOC_ETM_CH7_TASK_ID_CH7_TASK_ID_Msk = 0xff

	// CH8_EVT_ID: Channel8 event id register
	// Position of CH8_EVT_ID field.
	SOC_ETM_CH8_EVT_ID_CH8_EVT_ID_Pos = 0x0
	// Bit mask of CH8_EVT_ID field.
	SOC_ETM_CH8_EVT_ID_CH8_EVT_ID_Msk = 0xff

	// CH8_TASK_ID: Channel8 task id register
	// Position of CH8_TASK_ID field.
	SOC_ETM_CH8_TASK_ID_CH8_TASK_ID_Pos = 0x0
	// Bit mask of CH8_TASK_ID field.
	SOC_ETM_CH8_TASK_ID_CH8_TASK_ID_Msk = 0xff

	// CH9_EVT_ID: Channel9 event id register
	// Position of CH9_EVT_ID field.
	SOC_ETM_CH9_EVT_ID_CH9_EVT_ID_Pos = 0x0
	// Bit mask of CH9_EVT_ID field.
	SOC_ETM_CH9_EVT_ID_CH9_EVT_ID_Msk = 0xff

	// CH9_TASK_ID: Channel9 task id register
	// Position of CH9_TASK_ID field.
	SOC_ETM_CH9_TASK_ID_CH9_TASK_ID_Pos = 0x0
	// Bit mask of CH9_TASK_ID field.
	SOC_ETM_CH9_TASK_ID_CH9_TASK_ID_Msk = 0xff

	// CH10_EVT_ID: Channel10 event id register
	// Position of CH10_EVT_ID field.
	SOC_ETM_CH10_EVT_ID_CH10_EVT_ID_Pos = 0x0
	// Bit mask of CH10_EVT_ID field.
	SOC_ETM_CH10_EVT_ID_CH10_EVT_ID_Msk = 0xff

	// CH10_TASK_ID: Channel10 task id register
	// Position of CH10_TASK_ID field.
	SOC_ETM_CH10_TASK_ID_CH10_TASK_ID_Pos = 0x0
	// Bit mask of CH10_TASK_ID field.
	SOC_ETM_CH10_TASK_ID_CH10_TASK_ID_Msk = 0xff

	// CH11_EVT_ID: Channel11 event id register
	// Position of CH11_EVT_ID field.
	SOC_ETM_CH11_EVT_ID_CH11_EVT_ID_Pos = 0x0
	// Bit mask of CH11_EVT_ID field.
	SOC_ETM_CH11_EVT_ID_CH11_EVT_ID_Msk = 0xff

	// CH11_TASK_ID: Channel11 task id register
	// Position of CH11_TASK_ID field.
	SOC_ETM_CH11_TASK_ID_CH11_TASK_ID_Pos = 0x0
	// Bit mask of CH11_TASK_ID field.
	SOC_ETM_CH11_TASK_ID_CH11_TASK_ID_Msk = 0xff

	// CH12_EVT_ID: Channel12 event id register
	// Position of CH12_EVT_ID field.
	SOC_ETM_CH12_EVT_ID_CH12_EVT_ID_Pos = 0x0
	// Bit mask of CH12_EVT_ID field.
	SOC_ETM_CH12_EVT_ID_CH12_EVT_ID_Msk = 0xff

	// CH12_TASK_ID: Channel12 task id register
	// Position of CH12_TASK_ID field.
	SOC_ETM_CH12_TASK_ID_CH12_TASK_ID_Pos = 0x0
	// Bit mask of CH12_TASK_ID field.
	SOC_ETM_CH12_TASK_ID_CH12_TASK_ID_Msk = 0xff

	// CH13_EVT_ID: Channel13 event id register
	// Position of CH13_EVT_ID field.
	SOC_ETM_CH13_EVT_ID_CH13_EVT_ID_Pos = 0x0
	// Bit mask of CH13_EVT_ID field.
	SOC_ETM_CH13_EVT_ID_CH13_EVT_ID_Msk = 0xff

	// CH13_TASK_ID: Channel13 task id register
	// Position of CH13_TASK_ID field.
	SOC_ETM_CH13_TASK_ID_CH13_TASK_ID_Pos = 0x0
	// Bit mask of CH13_TASK_ID field.
	SOC_ETM_CH13_TASK_ID_CH13_TASK_ID_Msk = 0xff

	// CH14_EVT_ID: Channel14 event id register
	// Position of CH14_EVT_ID field.
	SOC_ETM_CH14_EVT_ID_CH14_EVT_ID_Pos = 0x0
	// Bit mask of CH14_EVT_ID field.
	SOC_ETM_CH14_EVT_ID_CH14_EVT_ID_Msk = 0xff

	// CH14_TASK_ID: Channel14 task id register
	// Position of CH14_TASK_ID field.
	SOC_ETM_CH14_TASK_ID_CH14_TASK_ID_Pos = 0x0
	// Bit mask of CH14_TASK_ID field.
	SOC_ETM_CH14_TASK_ID_CH14_TASK_ID_Msk = 0xff

	// CH15_EVT_ID: Channel15 event id register
	// Position of CH15_EVT_ID field.
	SOC_ETM_CH15_EVT_ID_CH15_EVT_ID_Pos = 0x0
	// Bit mask of CH15_EVT_ID field.
	SOC_ETM_CH15_EVT_ID_CH15_EVT_ID_Msk = 0xff

	// CH15_TASK_ID: Channel15 task id register
	// Position of CH15_TASK_ID field.
	SOC_ETM_CH15_TASK_ID_CH15_TASK_ID_Pos = 0x0
	// Bit mask of CH15_TASK_ID field.
	SOC_ETM_CH15_TASK_ID_CH15_TASK_ID_Msk = 0xff

	// CH16_EVT_ID: Channel16 event id register
	// Position of CH16_EVT_ID field.
	SOC_ETM_CH16_EVT_ID_CH16_EVT_ID_Pos = 0x0
	// Bit mask of CH16_EVT_ID field.
	SOC_ETM_CH16_EVT_ID_CH16_EVT_ID_Msk = 0xff

	// CH16_TASK_ID: Channel16 task id register
	// Position of CH16_TASK_ID field.
	SOC_ETM_CH16_TASK_ID_CH16_TASK_ID_Pos = 0x0
	// Bit mask of CH16_TASK_ID field.
	SOC_ETM_CH16_TASK_ID_CH16_TASK_ID_Msk = 0xff

	// CH17_EVT_ID: Channel17 event id register
	// Position of CH17_EVT_ID field.
	SOC_ETM_CH17_EVT_ID_CH17_EVT_ID_Pos = 0x0
	// Bit mask of CH17_EVT_ID field.
	SOC_ETM_CH17_EVT_ID_CH17_EVT_ID_Msk = 0xff

	// CH17_TASK_ID: Channel17 task id register
	// Position of CH17_TASK_ID field.
	SOC_ETM_CH17_TASK_ID_CH17_TASK_ID_Pos = 0x0
	// Bit mask of CH17_TASK_ID field.
	SOC_ETM_CH17_TASK_ID_CH17_TASK_ID_Msk = 0xff

	// CH18_EVT_ID: Channel18 event id register
	// Position of CH18_EVT_ID field.
	SOC_ETM_CH18_EVT_ID_CH18_EVT_ID_Pos = 0x0
	// Bit mask of CH18_EVT_ID field.
	SOC_ETM_CH18_EVT_ID_CH18_EVT_ID_Msk = 0xff

	// CH18_TASK_ID: Channel18 task id register
	// Position of CH18_TASK_ID field.
	SOC_ETM_CH18_TASK_ID_CH18_TASK_ID_Pos = 0x0
	// Bit mask of CH18_TASK_ID field.
	SOC_ETM_CH18_TASK_ID_CH18_TASK_ID_Msk = 0xff

	// CH19_EVT_ID: Channel19 event id register
	// Position of CH19_EVT_ID field.
	SOC_ETM_CH19_EVT_ID_CH19_EVT_ID_Pos = 0x0
	// Bit mask of CH19_EVT_ID field.
	SOC_ETM_CH19_EVT_ID_CH19_EVT_ID_Msk = 0xff

	// CH19_TASK_ID: Channel19 task id register
	// Position of CH19_TASK_ID field.
	SOC_ETM_CH19_TASK_ID_CH19_TASK_ID_Pos = 0x0
	// Bit mask of CH19_TASK_ID field.
	SOC_ETM_CH19_TASK_ID_CH19_TASK_ID_Msk = 0xff

	// CH20_EVT_ID: Channel20 event id register
	// Position of CH20_EVT_ID field.
	SOC_ETM_CH20_EVT_ID_CH20_EVT_ID_Pos = 0x0
	// Bit mask of CH20_EVT_ID field.
	SOC_ETM_CH20_EVT_ID_CH20_EVT_ID_Msk = 0xff

	// CH20_TASK_ID: Channel20 task id register
	// Position of CH20_TASK_ID field.
	SOC_ETM_CH20_TASK_ID_CH20_TASK_ID_Pos = 0x0
	// Bit mask of CH20_TASK_ID field.
	SOC_ETM_CH20_TASK_ID_CH20_TASK_ID_Msk = 0xff

	// CH21_EVT_ID: Channel21 event id register
	// Position of CH21_EVT_ID field.
	SOC_ETM_CH21_EVT_ID_CH21_EVT_ID_Pos = 0x0
	// Bit mask of CH21_EVT_ID field.
	SOC_ETM_CH21_EVT_ID_CH21_EVT_ID_Msk = 0xff

	// CH21_TASK_ID: Channel21 task id register
	// Position of CH21_TASK_ID field.
	SOC_ETM_CH21_TASK_ID_CH21_TASK_ID_Pos = 0x0
	// Bit mask of CH21_TASK_ID field.
	SOC_ETM_CH21_TASK_ID_CH21_TASK_ID_Msk = 0xff

	// CH22_EVT_ID: Channel22 event id register
	// Position of CH22_EVT_ID field.
	SOC_ETM_CH22_EVT_ID_CH22_EVT_ID_Pos = 0x0
	// Bit mask of CH22_EVT_ID field.
	SOC_ETM_CH22_EVT_ID_CH22_EVT_ID_Msk = 0xff

	// CH22_TASK_ID: Channel22 task id register
	// Position of CH22_TASK_ID field.
	SOC_ETM_CH22_TASK_ID_CH22_TASK_ID_Pos = 0x0
	// Bit mask of CH22_TASK_ID field.
	SOC_ETM_CH22_TASK_ID_CH22_TASK_ID_Msk = 0xff

	// CH23_EVT_ID: Channel23 event id register
	// Position of CH23_EVT_ID field.
	SOC_ETM_CH23_EVT_ID_CH23_EVT_ID_Pos = 0x0
	// Bit mask of CH23_EVT_ID field.
	SOC_ETM_CH23_EVT_ID_CH23_EVT_ID_Msk = 0xff

	// CH23_TASK_ID: Channel23 task id register
	// Position of CH23_TASK_ID field.
	SOC_ETM_CH23_TASK_ID_CH23_TASK_ID_Pos = 0x0
	// Bit mask of CH23_TASK_ID field.
	SOC_ETM_CH23_TASK_ID_CH23_TASK_ID_Msk = 0xff

	// CH24_EVT_ID: Channel24 event id register
	// Position of CH24_EVT_ID field.
	SOC_ETM_CH24_EVT_ID_CH24_EVT_ID_Pos = 0x0
	// Bit mask of CH24_EVT_ID field.
	SOC_ETM_CH24_EVT_ID_CH24_EVT_ID_Msk = 0xff

	// CH24_TASK_ID: Channel24 task id register
	// Position of CH24_TASK_ID field.
	SOC_ETM_CH24_TASK_ID_CH24_TASK_ID_Pos = 0x0
	// Bit mask of CH24_TASK_ID field.
	SOC_ETM_CH24_TASK_ID_CH24_TASK_ID_Msk = 0xff

	// CH25_EVT_ID: Channel25 event id register
	// Position of CH25_EVT_ID field.
	SOC_ETM_CH25_EVT_ID_CH25_EVT_ID_Pos = 0x0
	// Bit mask of CH25_EVT_ID field.
	SOC_ETM_CH25_EVT_ID_CH25_EVT_ID_Msk = 0xff

	// CH25_TASK_ID: Channel25 task id register
	// Position of CH25_TASK_ID field.
	SOC_ETM_CH25_TASK_ID_CH25_TASK_ID_Pos = 0x0
	// Bit mask of CH25_TASK_ID field.
	SOC_ETM_CH25_TASK_ID_CH25_TASK_ID_Msk = 0xff

	// CH26_EVT_ID: Channel26 event id register
	// Position of CH26_EVT_ID field.
	SOC_ETM_CH26_EVT_ID_CH26_EVT_ID_Pos = 0x0
	// Bit mask of CH26_EVT_ID field.
	SOC_ETM_CH26_EVT_ID_CH26_EVT_ID_Msk = 0xff

	// CH26_TASK_ID: Channel26 task id register
	// Position of CH26_TASK_ID field.
	SOC_ETM_CH26_TASK_ID_CH26_TASK_ID_Pos = 0x0
	// Bit mask of CH26_TASK_ID field.
	SOC_ETM_CH26_TASK_ID_CH26_TASK_ID_Msk = 0xff

	// CH27_EVT_ID: Channel27 event id register
	// Position of CH27_EVT_ID field.
	SOC_ETM_CH27_EVT_ID_CH27_EVT_ID_Pos = 0x0
	// Bit mask of CH27_EVT_ID field.
	SOC_ETM_CH27_EVT_ID_CH27_EVT_ID_Msk = 0xff

	// CH27_TASK_ID: Channel27 task id register
	// Position of CH27_TASK_ID field.
	SOC_ETM_CH27_TASK_ID_CH27_TASK_ID_Pos = 0x0
	// Bit mask of CH27_TASK_ID field.
	SOC_ETM_CH27_TASK_ID_CH27_TASK_ID_Msk = 0xff

	// CH28_EVT_ID: Channel28 event id register
	// Position of CH28_EVT_ID field.
	SOC_ETM_CH28_EVT_ID_CH28_EVT_ID_Pos = 0x0
	// Bit mask of CH28_EVT_ID field.
	SOC_ETM_CH28_EVT_ID_CH28_EVT_ID_Msk = 0xff

	// CH28_TASK_ID: Channel28 task id register
	// Position of CH28_TASK_ID field.
	SOC_ETM_CH28_TASK_ID_CH28_TASK_ID_Pos = 0x0
	// Bit mask of CH28_TASK_ID field.
	SOC_ETM_CH28_TASK_ID_CH28_TASK_ID_Msk = 0xff

	// CH29_EVT_ID: Channel29 event id register
	// Position of CH29_EVT_ID field.
	SOC_ETM_CH29_EVT_ID_CH29_EVT_ID_Pos = 0x0
	// Bit mask of CH29_EVT_ID field.
	SOC_ETM_CH29_EVT_ID_CH29_EVT_ID_Msk = 0xff

	// CH29_TASK_ID: Channel29 task id register
	// Position of CH29_TASK_ID field.
	SOC_ETM_CH29_TASK_ID_CH29_TASK_ID_Pos = 0x0
	// Bit mask of CH29_TASK_ID field.
	SOC_ETM_CH29_TASK_ID_CH29_TASK_ID_Msk = 0xff

	// CH30_EVT_ID: Channel30 event id register
	// Position of CH30_EVT_ID field.
	SOC_ETM_CH30_EVT_ID_CH30_EVT_ID_Pos = 0x0
	// Bit mask of CH30_EVT_ID field.
	SOC_ETM_CH30_EVT_ID_CH30_EVT_ID_Msk = 0xff

	// CH30_TASK_ID: Channel30 task id register
	// Position of CH30_TASK_ID field.
	SOC_ETM_CH30_TASK_ID_CH30_TASK_ID_Pos = 0x0
	// Bit mask of CH30_TASK_ID field.
	SOC_ETM_CH30_TASK_ID_CH30_TASK_ID_Msk = 0xff

	// CH31_EVT_ID: Channel31 event id register
	// Position of CH31_EVT_ID field.
	SOC_ETM_CH31_EVT_ID_CH31_EVT_ID_Pos = 0x0
	// Bit mask of CH31_EVT_ID field.
	SOC_ETM_CH31_EVT_ID_CH31_EVT_ID_Msk = 0xff

	// CH31_TASK_ID: Channel31 task id register
	// Position of CH31_TASK_ID field.
	SOC_ETM_CH31_TASK_ID_CH31_TASK_ID_Pos = 0x0
	// Bit mask of CH31_TASK_ID field.
	SOC_ETM_CH31_TASK_ID_CH31_TASK_ID_Msk = 0xff

	// CH32_EVT_ID: Channel32 event id register
	// Position of CH32_EVT_ID field.
	SOC_ETM_CH32_EVT_ID_CH32_EVT_ID_Pos = 0x0
	// Bit mask of CH32_EVT_ID field.
	SOC_ETM_CH32_EVT_ID_CH32_EVT_ID_Msk = 0xff

	// CH32_TASK_ID: Channel32 task id register
	// Position of CH32_TASK_ID field.
	SOC_ETM_CH32_TASK_ID_CH32_TASK_ID_Pos = 0x0
	// Bit mask of CH32_TASK_ID field.
	SOC_ETM_CH32_TASK_ID_CH32_TASK_ID_Msk = 0xff

	// CH33_EVT_ID: Channel33 event id register
	// Position of CH33_EVT_ID field.
	SOC_ETM_CH33_EVT_ID_CH33_EVT_ID_Pos = 0x0
	// Bit mask of CH33_EVT_ID field.
	SOC_ETM_CH33_EVT_ID_CH33_EVT_ID_Msk = 0xff

	// CH33_TASK_ID: Channel33 task id register
	// Position of CH33_TASK_ID field.
	SOC_ETM_CH33_TASK_ID_CH33_TASK_ID_Pos = 0x0
	// Bit mask of CH33_TASK_ID field.
	SOC_ETM_CH33_TASK_ID_CH33_TASK_ID_Msk = 0xff

	// CH34_EVT_ID: Channel34 event id register
	// Position of CH34_EVT_ID field.
	SOC_ETM_CH34_EVT_ID_CH34_EVT_ID_Pos = 0x0
	// Bit mask of CH34_EVT_ID field.
	SOC_ETM_CH34_EVT_ID_CH34_EVT_ID_Msk = 0xff

	// CH34_TASK_ID: Channel34 task id register
	// Position of CH34_TASK_ID field.
	SOC_ETM_CH34_TASK_ID_CH34_TASK_ID_Pos = 0x0
	// Bit mask of CH34_TASK_ID field.
	SOC_ETM_CH34_TASK_ID_CH34_TASK_ID_Msk = 0xff

	// CH35_EVT_ID: Channel35 event id register
	// Position of CH35_EVT_ID field.
	SOC_ETM_CH35_EVT_ID_CH35_EVT_ID_Pos = 0x0
	// Bit mask of CH35_EVT_ID field.
	SOC_ETM_CH35_EVT_ID_CH35_EVT_ID_Msk = 0xff

	// CH35_TASK_ID: Channel35 task id register
	// Position of CH35_TASK_ID field.
	SOC_ETM_CH35_TASK_ID_CH35_TASK_ID_Pos = 0x0
	// Bit mask of CH35_TASK_ID field.
	SOC_ETM_CH35_TASK_ID_CH35_TASK_ID_Msk = 0xff

	// CH36_EVT_ID: Channel36 event id register
	// Position of CH36_EVT_ID field.
	SOC_ETM_CH36_EVT_ID_CH36_EVT_ID_Pos = 0x0
	// Bit mask of CH36_EVT_ID field.
	SOC_ETM_CH36_EVT_ID_CH36_EVT_ID_Msk = 0xff

	// CH36_TASK_ID: Channel36 task id register
	// Position of CH36_TASK_ID field.
	SOC_ETM_CH36_TASK_ID_CH36_TASK_ID_Pos = 0x0
	// Bit mask of CH36_TASK_ID field.
	SOC_ETM_CH36_TASK_ID_CH36_TASK_ID_Msk = 0xff

	// CH37_EVT_ID: Channel37 event id register
	// Position of CH37_EVT_ID field.
	SOC_ETM_CH37_EVT_ID_CH37_EVT_ID_Pos = 0x0
	// Bit mask of CH37_EVT_ID field.
	SOC_ETM_CH37_EVT_ID_CH37_EVT_ID_Msk = 0xff

	// CH37_TASK_ID: Channel37 task id register
	// Position of CH37_TASK_ID field.
	SOC_ETM_CH37_TASK_ID_CH37_TASK_ID_Pos = 0x0
	// Bit mask of CH37_TASK_ID field.
	SOC_ETM_CH37_TASK_ID_CH37_TASK_ID_Msk = 0xff

	// CH38_EVT_ID: Channel38 event id register
	// Position of CH38_EVT_ID field.
	SOC_ETM_CH38_EVT_ID_CH38_EVT_ID_Pos = 0x0
	// Bit mask of CH38_EVT_ID field.
	SOC_ETM_CH38_EVT_ID_CH38_EVT_ID_Msk = 0xff

	// CH38_TASK_ID: Channel38 task id register
	// Position of CH38_TASK_ID field.
	SOC_ETM_CH38_TASK_ID_CH38_TASK_ID_Pos = 0x0
	// Bit mask of CH38_TASK_ID field.
	SOC_ETM_CH38_TASK_ID_CH38_TASK_ID_Msk = 0xff

	// CH39_EVT_ID: Channel39 event id register
	// Position of CH39_EVT_ID field.
	SOC_ETM_CH39_EVT_ID_CH39_EVT_ID_Pos = 0x0
	// Bit mask of CH39_EVT_ID field.
	SOC_ETM_CH39_EVT_ID_CH39_EVT_ID_Msk = 0xff

	// CH39_TASK_ID: Channel39 task id register
	// Position of CH39_TASK_ID field.
	SOC_ETM_CH39_TASK_ID_CH39_TASK_ID_Pos = 0x0
	// Bit mask of CH39_TASK_ID field.
	SOC_ETM_CH39_TASK_ID_CH39_TASK_ID_Msk = 0xff

	// CH40_EVT_ID: Channel40 event id register
	// Position of CH40_EVT_ID field.
	SOC_ETM_CH40_EVT_ID_CH40_EVT_ID_Pos = 0x0
	// Bit mask of CH40_EVT_ID field.
	SOC_ETM_CH40_EVT_ID_CH40_EVT_ID_Msk = 0xff

	// CH40_TASK_ID: Channel40 task id register
	// Position of CH40_TASK_ID field.
	SOC_ETM_CH40_TASK_ID_CH40_TASK_ID_Pos = 0x0
	// Bit mask of CH40_TASK_ID field.
	SOC_ETM_CH40_TASK_ID_CH40_TASK_ID_Msk = 0xff

	// CH41_EVT_ID: Channel41 event id register
	// Position of CH41_EVT_ID field.
	SOC_ETM_CH41_EVT_ID_CH41_EVT_ID_Pos = 0x0
	// Bit mask of CH41_EVT_ID field.
	SOC_ETM_CH41_EVT_ID_CH41_EVT_ID_Msk = 0xff

	// CH41_TASK_ID: Channel41 task id register
	// Position of CH41_TASK_ID field.
	SOC_ETM_CH41_TASK_ID_CH41_TASK_ID_Pos = 0x0
	// Bit mask of CH41_TASK_ID field.
	SOC_ETM_CH41_TASK_ID_CH41_TASK_ID_Msk = 0xff

	// CH42_EVT_ID: Channel42 event id register
	// Position of CH42_EVT_ID field.
	SOC_ETM_CH42_EVT_ID_CH42_EVT_ID_Pos = 0x0
	// Bit mask of CH42_EVT_ID field.
	SOC_ETM_CH42_EVT_ID_CH42_EVT_ID_Msk = 0xff

	// CH42_TASK_ID: Channel42 task id register
	// Position of CH42_TASK_ID field.
	SOC_ETM_CH42_TASK_ID_CH42_TASK_ID_Pos = 0x0
	// Bit mask of CH42_TASK_ID field.
	SOC_ETM_CH42_TASK_ID_CH42_TASK_ID_Msk = 0xff

	// CH43_EVT_ID: Channel43 event id register
	// Position of CH43_EVT_ID field.
	SOC_ETM_CH43_EVT_ID_CH43_EVT_ID_Pos = 0x0
	// Bit mask of CH43_EVT_ID field.
	SOC_ETM_CH43_EVT_ID_CH43_EVT_ID_Msk = 0xff

	// CH43_TASK_ID: Channel43 task id register
	// Position of CH43_TASK_ID field.
	SOC_ETM_CH43_TASK_ID_CH43_TASK_ID_Pos = 0x0
	// Bit mask of CH43_TASK_ID field.
	SOC_ETM_CH43_TASK_ID_CH43_TASK_ID_Msk = 0xff

	// CH44_EVT_ID: Channel44 event id register
	// Position of CH44_EVT_ID field.
	SOC_ETM_CH44_EVT_ID_CH44_EVT_ID_Pos = 0x0
	// Bit mask of CH44_EVT_ID field.
	SOC_ETM_CH44_EVT_ID_CH44_EVT_ID_Msk = 0xff

	// CH44_TASK_ID: Channel44 task id register
	// Position of CH44_TASK_ID field.
	SOC_ETM_CH44_TASK_ID_CH44_TASK_ID_Pos = 0x0
	// Bit mask of CH44_TASK_ID field.
	SOC_ETM_CH44_TASK_ID_CH44_TASK_ID_Msk = 0xff

	// CH45_EVT_ID: Channel45 event id register
	// Position of CH45_EVT_ID field.
	SOC_ETM_CH45_EVT_ID_CH45_EVT_ID_Pos = 0x0
	// Bit mask of CH45_EVT_ID field.
	SOC_ETM_CH45_EVT_ID_CH45_EVT_ID_Msk = 0xff

	// CH45_TASK_ID: Channel45 task id register
	// Position of CH45_TASK_ID field.
	SOC_ETM_CH45_TASK_ID_CH45_TASK_ID_Pos = 0x0
	// Bit mask of CH45_TASK_ID field.
	SOC_ETM_CH45_TASK_ID_CH45_TASK_ID_Msk = 0xff

	// CH46_EVT_ID: Channel46 event id register
	// Position of CH46_EVT_ID field.
	SOC_ETM_CH46_EVT_ID_CH46_EVT_ID_Pos = 0x0
	// Bit mask of CH46_EVT_ID field.
	SOC_ETM_CH46_EVT_ID_CH46_EVT_ID_Msk = 0xff

	// CH46_TASK_ID: Channel46 task id register
	// Position of CH46_TASK_ID field.
	SOC_ETM_CH46_TASK_ID_CH46_TASK_ID_Pos = 0x0
	// Bit mask of CH46_TASK_ID field.
	SOC_ETM_CH46_TASK_ID_CH46_TASK_ID_Msk = 0xff

	// CH47_EVT_ID: Channel47 event id register
	// Position of CH47_EVT_ID field.
	SOC_ETM_CH47_EVT_ID_CH47_EVT_ID_Pos = 0x0
	// Bit mask of CH47_EVT_ID field.
	SOC_ETM_CH47_EVT_ID_CH47_EVT_ID_Msk = 0xff

	// CH47_TASK_ID: Channel47 task id register
	// Position of CH47_TASK_ID field.
	SOC_ETM_CH47_TASK_ID_CH47_TASK_ID_Pos = 0x0
	// Bit mask of CH47_TASK_ID field.
	SOC_ETM_CH47_TASK_ID_CH47_TASK_ID_Msk = 0xff

	// CH48_EVT_ID: Channel48 event id register
	// Position of CH48_EVT_ID field.
	SOC_ETM_CH48_EVT_ID_CH48_EVT_ID_Pos = 0x0
	// Bit mask of CH48_EVT_ID field.
	SOC_ETM_CH48_EVT_ID_CH48_EVT_ID_Msk = 0xff

	// CH48_TASK_ID: Channel48 task id register
	// Position of CH48_TASK_ID field.
	SOC_ETM_CH48_TASK_ID_CH48_TASK_ID_Pos = 0x0
	// Bit mask of CH48_TASK_ID field.
	SOC_ETM_CH48_TASK_ID_CH48_TASK_ID_Msk = 0xff

	// CH49_EVT_ID: Channel49 event id register
	// Position of CH49_EVT_ID field.
	SOC_ETM_CH49_EVT_ID_CH49_EVT_ID_Pos = 0x0
	// Bit mask of CH49_EVT_ID field.
	SOC_ETM_CH49_EVT_ID_CH49_EVT_ID_Msk = 0xff

	// CH49_TASK_ID: Channel49 task id register
	// Position of CH49_TASK_ID field.
	SOC_ETM_CH49_TASK_ID_CH49_TASK_ID_Pos = 0x0
	// Bit mask of CH49_TASK_ID field.
	SOC_ETM_CH49_TASK_ID_CH49_TASK_ID_Msk = 0xff

	// EVT_ST0: Events trigger status register
	// Position of GPIO_EVT_CH0_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_RISE_EDGE_ST_Pos = 0x0
	// Bit mask of GPIO_EVT_CH0_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_RISE_EDGE_ST_Msk = 0x1
	// Bit GPIO_EVT_CH0_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_RISE_EDGE_ST = 0x1
	// Position of GPIO_EVT_CH1_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_RISE_EDGE_ST_Pos = 0x1
	// Bit mask of GPIO_EVT_CH1_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_RISE_EDGE_ST_Msk = 0x2
	// Bit GPIO_EVT_CH1_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_RISE_EDGE_ST = 0x2
	// Position of GPIO_EVT_CH2_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_RISE_EDGE_ST_Pos = 0x2
	// Bit mask of GPIO_EVT_CH2_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_RISE_EDGE_ST_Msk = 0x4
	// Bit GPIO_EVT_CH2_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_RISE_EDGE_ST = 0x4
	// Position of GPIO_EVT_CH3_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_RISE_EDGE_ST_Pos = 0x3
	// Bit mask of GPIO_EVT_CH3_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_RISE_EDGE_ST_Msk = 0x8
	// Bit GPIO_EVT_CH3_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_RISE_EDGE_ST = 0x8
	// Position of GPIO_EVT_CH4_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_RISE_EDGE_ST_Pos = 0x4
	// Bit mask of GPIO_EVT_CH4_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_RISE_EDGE_ST_Msk = 0x10
	// Bit GPIO_EVT_CH4_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_RISE_EDGE_ST = 0x10
	// Position of GPIO_EVT_CH5_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_RISE_EDGE_ST_Pos = 0x5
	// Bit mask of GPIO_EVT_CH5_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_RISE_EDGE_ST_Msk = 0x20
	// Bit GPIO_EVT_CH5_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_RISE_EDGE_ST = 0x20
	// Position of GPIO_EVT_CH6_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_RISE_EDGE_ST_Pos = 0x6
	// Bit mask of GPIO_EVT_CH6_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_RISE_EDGE_ST_Msk = 0x40
	// Bit GPIO_EVT_CH6_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_RISE_EDGE_ST = 0x40
	// Position of GPIO_EVT_CH7_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_RISE_EDGE_ST_Pos = 0x7
	// Bit mask of GPIO_EVT_CH7_RISE_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_RISE_EDGE_ST_Msk = 0x80
	// Bit GPIO_EVT_CH7_RISE_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_RISE_EDGE_ST = 0x80
	// Position of GPIO_EVT_CH0_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_FALL_EDGE_ST_Pos = 0x8
	// Bit mask of GPIO_EVT_CH0_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_FALL_EDGE_ST_Msk = 0x100
	// Bit GPIO_EVT_CH0_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_FALL_EDGE_ST = 0x100
	// Position of GPIO_EVT_CH1_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_FALL_EDGE_ST_Pos = 0x9
	// Bit mask of GPIO_EVT_CH1_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_FALL_EDGE_ST_Msk = 0x200
	// Bit GPIO_EVT_CH1_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_FALL_EDGE_ST = 0x200
	// Position of GPIO_EVT_CH2_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_FALL_EDGE_ST_Pos = 0xa
	// Bit mask of GPIO_EVT_CH2_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_FALL_EDGE_ST_Msk = 0x400
	// Bit GPIO_EVT_CH2_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_FALL_EDGE_ST = 0x400
	// Position of GPIO_EVT_CH3_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_FALL_EDGE_ST_Pos = 0xb
	// Bit mask of GPIO_EVT_CH3_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_FALL_EDGE_ST_Msk = 0x800
	// Bit GPIO_EVT_CH3_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_FALL_EDGE_ST = 0x800
	// Position of GPIO_EVT_CH4_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_FALL_EDGE_ST_Pos = 0xc
	// Bit mask of GPIO_EVT_CH4_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_FALL_EDGE_ST_Msk = 0x1000
	// Bit GPIO_EVT_CH4_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_FALL_EDGE_ST = 0x1000
	// Position of GPIO_EVT_CH5_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_FALL_EDGE_ST_Pos = 0xd
	// Bit mask of GPIO_EVT_CH5_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_FALL_EDGE_ST_Msk = 0x2000
	// Bit GPIO_EVT_CH5_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_FALL_EDGE_ST = 0x2000
	// Position of GPIO_EVT_CH6_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_FALL_EDGE_ST_Pos = 0xe
	// Bit mask of GPIO_EVT_CH6_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_FALL_EDGE_ST_Msk = 0x4000
	// Bit GPIO_EVT_CH6_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_FALL_EDGE_ST = 0x4000
	// Position of GPIO_EVT_CH7_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_FALL_EDGE_ST_Pos = 0xf
	// Bit mask of GPIO_EVT_CH7_FALL_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_FALL_EDGE_ST_Msk = 0x8000
	// Bit GPIO_EVT_CH7_FALL_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_FALL_EDGE_ST = 0x8000
	// Position of GPIO_EVT_CH0_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_ANY_EDGE_ST_Pos = 0x10
	// Bit mask of GPIO_EVT_CH0_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_ANY_EDGE_ST_Msk = 0x10000
	// Bit GPIO_EVT_CH0_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH0_ANY_EDGE_ST = 0x10000
	// Position of GPIO_EVT_CH1_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_ANY_EDGE_ST_Pos = 0x11
	// Bit mask of GPIO_EVT_CH1_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_ANY_EDGE_ST_Msk = 0x20000
	// Bit GPIO_EVT_CH1_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH1_ANY_EDGE_ST = 0x20000
	// Position of GPIO_EVT_CH2_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_ANY_EDGE_ST_Pos = 0x12
	// Bit mask of GPIO_EVT_CH2_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_ANY_EDGE_ST_Msk = 0x40000
	// Bit GPIO_EVT_CH2_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH2_ANY_EDGE_ST = 0x40000
	// Position of GPIO_EVT_CH3_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_ANY_EDGE_ST_Pos = 0x13
	// Bit mask of GPIO_EVT_CH3_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_ANY_EDGE_ST_Msk = 0x80000
	// Bit GPIO_EVT_CH3_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH3_ANY_EDGE_ST = 0x80000
	// Position of GPIO_EVT_CH4_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_ANY_EDGE_ST_Pos = 0x14
	// Bit mask of GPIO_EVT_CH4_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_ANY_EDGE_ST_Msk = 0x100000
	// Bit GPIO_EVT_CH4_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH4_ANY_EDGE_ST = 0x100000
	// Position of GPIO_EVT_CH5_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_ANY_EDGE_ST_Pos = 0x15
	// Bit mask of GPIO_EVT_CH5_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_ANY_EDGE_ST_Msk = 0x200000
	// Bit GPIO_EVT_CH5_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH5_ANY_EDGE_ST = 0x200000
	// Position of GPIO_EVT_CH6_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_ANY_EDGE_ST_Pos = 0x16
	// Bit mask of GPIO_EVT_CH6_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_ANY_EDGE_ST_Msk = 0x400000
	// Bit GPIO_EVT_CH6_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH6_ANY_EDGE_ST = 0x400000
	// Position of GPIO_EVT_CH7_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_ANY_EDGE_ST_Pos = 0x17
	// Bit mask of GPIO_EVT_CH7_ANY_EDGE_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_ANY_EDGE_ST_Msk = 0x800000
	// Bit GPIO_EVT_CH7_ANY_EDGE_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_CH7_ANY_EDGE_ST = 0x800000
	// Position of GPIO_EVT_ZERO_DET_POS0_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_POS0_ST_Pos = 0x18
	// Bit mask of GPIO_EVT_ZERO_DET_POS0_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_POS0_ST_Msk = 0x1000000
	// Bit GPIO_EVT_ZERO_DET_POS0_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_POS0_ST = 0x1000000
	// Position of GPIO_EVT_ZERO_DET_NEG0_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_NEG0_ST_Pos = 0x19
	// Bit mask of GPIO_EVT_ZERO_DET_NEG0_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_NEG0_ST_Msk = 0x2000000
	// Bit GPIO_EVT_ZERO_DET_NEG0_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_NEG0_ST = 0x2000000
	// Position of GPIO_EVT_ZERO_DET_POS1_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_POS1_ST_Pos = 0x1a
	// Bit mask of GPIO_EVT_ZERO_DET_POS1_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_POS1_ST_Msk = 0x4000000
	// Bit GPIO_EVT_ZERO_DET_POS1_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_POS1_ST = 0x4000000
	// Position of GPIO_EVT_ZERO_DET_NEG1_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_NEG1_ST_Pos = 0x1b
	// Bit mask of GPIO_EVT_ZERO_DET_NEG1_ST field.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_NEG1_ST_Msk = 0x8000000
	// Bit GPIO_EVT_ZERO_DET_NEG1_ST.
	SOC_ETM_EVT_ST0_GPIO_EVT_ZERO_DET_NEG1_ST = 0x8000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH0_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH0_ST_Pos = 0x1c
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH0_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH0_ST_Msk = 0x10000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH0_ST.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH0_ST = 0x10000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH1_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH1_ST_Pos = 0x1d
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH1_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH1_ST_Msk = 0x20000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH1_ST.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH1_ST = 0x20000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH2_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH2_ST_Pos = 0x1e
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH2_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH2_ST_Msk = 0x40000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH2_ST.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH2_ST = 0x40000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH3_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH3_ST_Pos = 0x1f
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH3_ST field.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH3_ST_Msk = 0x80000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH3_ST.
	SOC_ETM_EVT_ST0_LEDC_EVT_DUTY_CHNG_END_CH3_ST = 0x80000000

	// EVT_ST0_CLR: Events trigger status clear register
	// Position of GPIO_EVT_CH0_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_Pos = 0x0
	// Bit mask of GPIO_EVT_CH0_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_Msk = 0x1
	// Bit GPIO_EVT_CH0_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_RISE_EDGE_ST_CLR = 0x1
	// Position of GPIO_EVT_CH1_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_Pos = 0x1
	// Bit mask of GPIO_EVT_CH1_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_Msk = 0x2
	// Bit GPIO_EVT_CH1_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_RISE_EDGE_ST_CLR = 0x2
	// Position of GPIO_EVT_CH2_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_Pos = 0x2
	// Bit mask of GPIO_EVT_CH2_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_Msk = 0x4
	// Bit GPIO_EVT_CH2_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_RISE_EDGE_ST_CLR = 0x4
	// Position of GPIO_EVT_CH3_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_Pos = 0x3
	// Bit mask of GPIO_EVT_CH3_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_Msk = 0x8
	// Bit GPIO_EVT_CH3_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_RISE_EDGE_ST_CLR = 0x8
	// Position of GPIO_EVT_CH4_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_Pos = 0x4
	// Bit mask of GPIO_EVT_CH4_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_Msk = 0x10
	// Bit GPIO_EVT_CH4_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_RISE_EDGE_ST_CLR = 0x10
	// Position of GPIO_EVT_CH5_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_Pos = 0x5
	// Bit mask of GPIO_EVT_CH5_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_Msk = 0x20
	// Bit GPIO_EVT_CH5_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_RISE_EDGE_ST_CLR = 0x20
	// Position of GPIO_EVT_CH6_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_Pos = 0x6
	// Bit mask of GPIO_EVT_CH6_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_Msk = 0x40
	// Bit GPIO_EVT_CH6_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_RISE_EDGE_ST_CLR = 0x40
	// Position of GPIO_EVT_CH7_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_Pos = 0x7
	// Bit mask of GPIO_EVT_CH7_RISE_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_Msk = 0x80
	// Bit GPIO_EVT_CH7_RISE_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_RISE_EDGE_ST_CLR = 0x80
	// Position of GPIO_EVT_CH0_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_Pos = 0x8
	// Bit mask of GPIO_EVT_CH0_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_Msk = 0x100
	// Bit GPIO_EVT_CH0_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_FALL_EDGE_ST_CLR = 0x100
	// Position of GPIO_EVT_CH1_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_Pos = 0x9
	// Bit mask of GPIO_EVT_CH1_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_Msk = 0x200
	// Bit GPIO_EVT_CH1_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_FALL_EDGE_ST_CLR = 0x200
	// Position of GPIO_EVT_CH2_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_Pos = 0xa
	// Bit mask of GPIO_EVT_CH2_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_Msk = 0x400
	// Bit GPIO_EVT_CH2_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_FALL_EDGE_ST_CLR = 0x400
	// Position of GPIO_EVT_CH3_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_Pos = 0xb
	// Bit mask of GPIO_EVT_CH3_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_Msk = 0x800
	// Bit GPIO_EVT_CH3_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_FALL_EDGE_ST_CLR = 0x800
	// Position of GPIO_EVT_CH4_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_Pos = 0xc
	// Bit mask of GPIO_EVT_CH4_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_Msk = 0x1000
	// Bit GPIO_EVT_CH4_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_FALL_EDGE_ST_CLR = 0x1000
	// Position of GPIO_EVT_CH5_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_Pos = 0xd
	// Bit mask of GPIO_EVT_CH5_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_Msk = 0x2000
	// Bit GPIO_EVT_CH5_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_FALL_EDGE_ST_CLR = 0x2000
	// Position of GPIO_EVT_CH6_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_Pos = 0xe
	// Bit mask of GPIO_EVT_CH6_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_Msk = 0x4000
	// Bit GPIO_EVT_CH6_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_FALL_EDGE_ST_CLR = 0x4000
	// Position of GPIO_EVT_CH7_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_Pos = 0xf
	// Bit mask of GPIO_EVT_CH7_FALL_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_Msk = 0x8000
	// Bit GPIO_EVT_CH7_FALL_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_FALL_EDGE_ST_CLR = 0x8000
	// Position of GPIO_EVT_CH0_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_Pos = 0x10
	// Bit mask of GPIO_EVT_CH0_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_Msk = 0x10000
	// Bit GPIO_EVT_CH0_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH0_ANY_EDGE_ST_CLR = 0x10000
	// Position of GPIO_EVT_CH1_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_Pos = 0x11
	// Bit mask of GPIO_EVT_CH1_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_Msk = 0x20000
	// Bit GPIO_EVT_CH1_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH1_ANY_EDGE_ST_CLR = 0x20000
	// Position of GPIO_EVT_CH2_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_Pos = 0x12
	// Bit mask of GPIO_EVT_CH2_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_Msk = 0x40000
	// Bit GPIO_EVT_CH2_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH2_ANY_EDGE_ST_CLR = 0x40000
	// Position of GPIO_EVT_CH3_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_Pos = 0x13
	// Bit mask of GPIO_EVT_CH3_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_Msk = 0x80000
	// Bit GPIO_EVT_CH3_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH3_ANY_EDGE_ST_CLR = 0x80000
	// Position of GPIO_EVT_CH4_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_Pos = 0x14
	// Bit mask of GPIO_EVT_CH4_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_Msk = 0x100000
	// Bit GPIO_EVT_CH4_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH4_ANY_EDGE_ST_CLR = 0x100000
	// Position of GPIO_EVT_CH5_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_Pos = 0x15
	// Bit mask of GPIO_EVT_CH5_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_Msk = 0x200000
	// Bit GPIO_EVT_CH5_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH5_ANY_EDGE_ST_CLR = 0x200000
	// Position of GPIO_EVT_CH6_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_Pos = 0x16
	// Bit mask of GPIO_EVT_CH6_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_Msk = 0x400000
	// Bit GPIO_EVT_CH6_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH6_ANY_EDGE_ST_CLR = 0x400000
	// Position of GPIO_EVT_CH7_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_Pos = 0x17
	// Bit mask of GPIO_EVT_CH7_ANY_EDGE_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_Msk = 0x800000
	// Bit GPIO_EVT_CH7_ANY_EDGE_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_CH7_ANY_EDGE_ST_CLR = 0x800000
	// Position of GPIO_EVT_ZERO_DET_POS0_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS0_ST_CLR_Pos = 0x18
	// Bit mask of GPIO_EVT_ZERO_DET_POS0_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS0_ST_CLR_Msk = 0x1000000
	// Bit GPIO_EVT_ZERO_DET_POS0_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS0_ST_CLR = 0x1000000
	// Position of GPIO_EVT_ZERO_DET_NEG0_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_Pos = 0x19
	// Bit mask of GPIO_EVT_ZERO_DET_NEG0_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_Msk = 0x2000000
	// Bit GPIO_EVT_ZERO_DET_NEG0_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG0_ST_CLR = 0x2000000
	// Position of GPIO_EVT_ZERO_DET_POS1_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS1_ST_CLR_Pos = 0x1a
	// Bit mask of GPIO_EVT_ZERO_DET_POS1_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS1_ST_CLR_Msk = 0x4000000
	// Bit GPIO_EVT_ZERO_DET_POS1_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_POS1_ST_CLR = 0x4000000
	// Position of GPIO_EVT_ZERO_DET_NEG1_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_Pos = 0x1b
	// Bit mask of GPIO_EVT_ZERO_DET_NEG1_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_Msk = 0x8000000
	// Bit GPIO_EVT_ZERO_DET_NEG1_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_GPIO_EVT_ZERO_DET_NEG1_ST_CLR = 0x8000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_Pos = 0x1c
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_Msk = 0x10000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR = 0x10000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_Pos = 0x1d
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_Msk = 0x20000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR = 0x20000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_Pos = 0x1e
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_Msk = 0x40000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR = 0x40000000
	// Position of LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_Pos = 0x1f
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR field.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_Msk = 0x80000000
	// Bit LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR.
	SOC_ETM_EVT_ST0_CLR_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR = 0x80000000

	// EVT_ST1: Events trigger status register
	// Position of LEDC_EVT_DUTY_CHNG_END_CH4_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH4_ST_Pos = 0x0
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH4_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH4_ST_Msk = 0x1
	// Bit LEDC_EVT_DUTY_CHNG_END_CH4_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH4_ST = 0x1
	// Position of LEDC_EVT_DUTY_CHNG_END_CH5_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH5_ST_Pos = 0x1
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH5_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH5_ST_Msk = 0x2
	// Bit LEDC_EVT_DUTY_CHNG_END_CH5_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH5_ST = 0x2
	// Position of LEDC_EVT_DUTY_CHNG_END_CH6_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH6_ST_Pos = 0x2
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH6_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH6_ST_Msk = 0x4
	// Bit LEDC_EVT_DUTY_CHNG_END_CH6_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH6_ST = 0x4
	// Position of LEDC_EVT_DUTY_CHNG_END_CH7_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH7_ST_Pos = 0x3
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH7_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH7_ST_Msk = 0x8
	// Bit LEDC_EVT_DUTY_CHNG_END_CH7_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_DUTY_CHNG_END_CH7_ST = 0x8
	// Position of LEDC_EVT_OVF_CNT_PLS_CH0_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH0_ST_Pos = 0x4
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH0_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH0_ST_Msk = 0x10
	// Bit LEDC_EVT_OVF_CNT_PLS_CH0_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH0_ST = 0x10
	// Position of LEDC_EVT_OVF_CNT_PLS_CH1_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH1_ST_Pos = 0x5
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH1_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH1_ST_Msk = 0x20
	// Bit LEDC_EVT_OVF_CNT_PLS_CH1_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH1_ST = 0x20
	// Position of LEDC_EVT_OVF_CNT_PLS_CH2_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH2_ST_Pos = 0x6
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH2_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH2_ST_Msk = 0x40
	// Bit LEDC_EVT_OVF_CNT_PLS_CH2_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH2_ST = 0x40
	// Position of LEDC_EVT_OVF_CNT_PLS_CH3_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH3_ST_Pos = 0x7
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH3_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH3_ST_Msk = 0x80
	// Bit LEDC_EVT_OVF_CNT_PLS_CH3_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH3_ST = 0x80
	// Position of LEDC_EVT_OVF_CNT_PLS_CH4_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH4_ST_Pos = 0x8
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH4_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH4_ST_Msk = 0x100
	// Bit LEDC_EVT_OVF_CNT_PLS_CH4_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH4_ST = 0x100
	// Position of LEDC_EVT_OVF_CNT_PLS_CH5_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH5_ST_Pos = 0x9
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH5_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH5_ST_Msk = 0x200
	// Bit LEDC_EVT_OVF_CNT_PLS_CH5_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH5_ST = 0x200
	// Position of LEDC_EVT_OVF_CNT_PLS_CH6_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH6_ST_Pos = 0xa
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH6_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH6_ST_Msk = 0x400
	// Bit LEDC_EVT_OVF_CNT_PLS_CH6_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH6_ST = 0x400
	// Position of LEDC_EVT_OVF_CNT_PLS_CH7_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH7_ST_Pos = 0xb
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH7_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH7_ST_Msk = 0x800
	// Bit LEDC_EVT_OVF_CNT_PLS_CH7_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_OVF_CNT_PLS_CH7_ST = 0x800
	// Position of LEDC_EVT_TIME_OVF_TIMER0_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER0_ST_Pos = 0xc
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER0_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER0_ST_Msk = 0x1000
	// Bit LEDC_EVT_TIME_OVF_TIMER0_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER0_ST = 0x1000
	// Position of LEDC_EVT_TIME_OVF_TIMER1_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER1_ST_Pos = 0xd
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER1_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER1_ST_Msk = 0x2000
	// Bit LEDC_EVT_TIME_OVF_TIMER1_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER1_ST = 0x2000
	// Position of LEDC_EVT_TIME_OVF_TIMER2_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER2_ST_Pos = 0xe
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER2_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER2_ST_Msk = 0x4000
	// Bit LEDC_EVT_TIME_OVF_TIMER2_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER2_ST = 0x4000
	// Position of LEDC_EVT_TIME_OVF_TIMER3_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER3_ST_Pos = 0xf
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER3_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER3_ST_Msk = 0x8000
	// Bit LEDC_EVT_TIME_OVF_TIMER3_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIME_OVF_TIMER3_ST = 0x8000
	// Position of LEDC_EVT_TIMER0_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER0_CMP_ST_Pos = 0x10
	// Bit mask of LEDC_EVT_TIMER0_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER0_CMP_ST_Msk = 0x10000
	// Bit LEDC_EVT_TIMER0_CMP_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER0_CMP_ST = 0x10000
	// Position of LEDC_EVT_TIMER1_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER1_CMP_ST_Pos = 0x11
	// Bit mask of LEDC_EVT_TIMER1_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER1_CMP_ST_Msk = 0x20000
	// Bit LEDC_EVT_TIMER1_CMP_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER1_CMP_ST = 0x20000
	// Position of LEDC_EVT_TIMER2_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER2_CMP_ST_Pos = 0x12
	// Bit mask of LEDC_EVT_TIMER2_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER2_CMP_ST_Msk = 0x40000
	// Bit LEDC_EVT_TIMER2_CMP_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER2_CMP_ST = 0x40000
	// Position of LEDC_EVT_TIMER3_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER3_CMP_ST_Pos = 0x13
	// Bit mask of LEDC_EVT_TIMER3_CMP_ST field.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER3_CMP_ST_Msk = 0x80000
	// Bit LEDC_EVT_TIMER3_CMP_ST.
	SOC_ETM_EVT_ST1_LEDC_EVT_TIMER3_CMP_ST = 0x80000
	// Position of TG0_EVT_CNT_CMP_TIMER0_ST field.
	SOC_ETM_EVT_ST1_TG0_EVT_CNT_CMP_TIMER0_ST_Pos = 0x14
	// Bit mask of TG0_EVT_CNT_CMP_TIMER0_ST field.
	SOC_ETM_EVT_ST1_TG0_EVT_CNT_CMP_TIMER0_ST_Msk = 0x100000
	// Bit TG0_EVT_CNT_CMP_TIMER0_ST.
	SOC_ETM_EVT_ST1_TG0_EVT_CNT_CMP_TIMER0_ST = 0x100000
	// Position of TG0_EVT_CNT_CMP_TIMER1_ST field.
	SOC_ETM_EVT_ST1_TG0_EVT_CNT_CMP_TIMER1_ST_Pos = 0x15
	// Bit mask of TG0_EVT_CNT_CMP_TIMER1_ST field.
	SOC_ETM_EVT_ST1_TG0_EVT_CNT_CMP_TIMER1_ST_Msk = 0x200000
	// Bit TG0_EVT_CNT_CMP_TIMER1_ST.
	SOC_ETM_EVT_ST1_TG0_EVT_CNT_CMP_TIMER1_ST = 0x200000
	// Position of TG1_EVT_CNT_CMP_TIMER0_ST field.
	SOC_ETM_EVT_ST1_TG1_EVT_CNT_CMP_TIMER0_ST_Pos = 0x16
	// Bit mask of TG1_EVT_CNT_CMP_TIMER0_ST field.
	SOC_ETM_EVT_ST1_TG1_EVT_CNT_CMP_TIMER0_ST_Msk = 0x400000
	// Bit TG1_EVT_CNT_CMP_TIMER0_ST.
	SOC_ETM_EVT_ST1_TG1_EVT_CNT_CMP_TIMER0_ST = 0x400000
	// Position of TG1_EVT_CNT_CMP_TIMER1_ST field.
	SOC_ETM_EVT_ST1_TG1_EVT_CNT_CMP_TIMER1_ST_Pos = 0x17
	// Bit mask of TG1_EVT_CNT_CMP_TIMER1_ST field.
	SOC_ETM_EVT_ST1_TG1_EVT_CNT_CMP_TIMER1_ST_Msk = 0x800000
	// Bit TG1_EVT_CNT_CMP_TIMER1_ST.
	SOC_ETM_EVT_ST1_TG1_EVT_CNT_CMP_TIMER1_ST = 0x800000
	// Position of SYSTIMER_EVT_CNT_CMP0_ST field.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP0_ST_Pos = 0x18
	// Bit mask of SYSTIMER_EVT_CNT_CMP0_ST field.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP0_ST_Msk = 0x1000000
	// Bit SYSTIMER_EVT_CNT_CMP0_ST.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP0_ST = 0x1000000
	// Position of SYSTIMER_EVT_CNT_CMP1_ST field.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP1_ST_Pos = 0x19
	// Bit mask of SYSTIMER_EVT_CNT_CMP1_ST field.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP1_ST_Msk = 0x2000000
	// Bit SYSTIMER_EVT_CNT_CMP1_ST.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP1_ST = 0x2000000
	// Position of SYSTIMER_EVT_CNT_CMP2_ST field.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP2_ST_Pos = 0x1a
	// Bit mask of SYSTIMER_EVT_CNT_CMP2_ST field.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP2_ST_Msk = 0x4000000
	// Bit SYSTIMER_EVT_CNT_CMP2_ST.
	SOC_ETM_EVT_ST1_SYSTIMER_EVT_CNT_CMP2_ST = 0x4000000
	// Position of MCPWM0_EVT_TIMER0_STOP_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER0_STOP_ST_Pos = 0x1b
	// Bit mask of MCPWM0_EVT_TIMER0_STOP_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER0_STOP_ST_Msk = 0x8000000
	// Bit MCPWM0_EVT_TIMER0_STOP_ST.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER0_STOP_ST = 0x8000000
	// Position of MCPWM0_EVT_TIMER1_STOP_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER1_STOP_ST_Pos = 0x1c
	// Bit mask of MCPWM0_EVT_TIMER1_STOP_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER1_STOP_ST_Msk = 0x10000000
	// Bit MCPWM0_EVT_TIMER1_STOP_ST.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER1_STOP_ST = 0x10000000
	// Position of MCPWM0_EVT_TIMER2_STOP_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER2_STOP_ST_Pos = 0x1d
	// Bit mask of MCPWM0_EVT_TIMER2_STOP_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER2_STOP_ST_Msk = 0x20000000
	// Bit MCPWM0_EVT_TIMER2_STOP_ST.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER2_STOP_ST = 0x20000000
	// Position of MCPWM0_EVT_TIMER0_TEZ_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER0_TEZ_ST_Pos = 0x1e
	// Bit mask of MCPWM0_EVT_TIMER0_TEZ_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER0_TEZ_ST_Msk = 0x40000000
	// Bit MCPWM0_EVT_TIMER0_TEZ_ST.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER0_TEZ_ST = 0x40000000
	// Position of MCPWM0_EVT_TIMER1_TEZ_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER1_TEZ_ST_Pos = 0x1f
	// Bit mask of MCPWM0_EVT_TIMER1_TEZ_ST field.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER1_TEZ_ST_Msk = 0x80000000
	// Bit MCPWM0_EVT_TIMER1_TEZ_ST.
	SOC_ETM_EVT_ST1_MCPWM0_EVT_TIMER1_TEZ_ST = 0x80000000

	// EVT_ST1_CLR: Events trigger status clear register
	// Position of LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_Pos = 0x0
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_Msk = 0x1
	// Bit LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR = 0x1
	// Position of LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_Pos = 0x1
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_Msk = 0x2
	// Bit LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR = 0x2
	// Position of LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_Pos = 0x2
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_Msk = 0x4
	// Bit LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR = 0x4
	// Position of LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_Pos = 0x3
	// Bit mask of LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_Msk = 0x8
	// Bit LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR = 0x8
	// Position of LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_Pos = 0x4
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_Msk = 0x10
	// Bit LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR = 0x10
	// Position of LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_Pos = 0x5
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_Msk = 0x20
	// Bit LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR = 0x20
	// Position of LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_Pos = 0x6
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_Msk = 0x40
	// Bit LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR = 0x40
	// Position of LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_Pos = 0x7
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_Msk = 0x80
	// Bit LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR = 0x80
	// Position of LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_Pos = 0x8
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_Msk = 0x100
	// Bit LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR = 0x100
	// Position of LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_Pos = 0x9
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_Msk = 0x200
	// Bit LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR = 0x200
	// Position of LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_Pos = 0xa
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_Msk = 0x400
	// Bit LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR = 0x400
	// Position of LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_Pos = 0xb
	// Bit mask of LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_Msk = 0x800
	// Bit LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR = 0x800
	// Position of LEDC_EVT_TIME_OVF_TIMER0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_Pos = 0xc
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_Msk = 0x1000
	// Bit LEDC_EVT_TIME_OVF_TIMER0_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR = 0x1000
	// Position of LEDC_EVT_TIME_OVF_TIMER1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_Pos = 0xd
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_Msk = 0x2000
	// Bit LEDC_EVT_TIME_OVF_TIMER1_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR = 0x2000
	// Position of LEDC_EVT_TIME_OVF_TIMER2_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_Pos = 0xe
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER2_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_Msk = 0x4000
	// Bit LEDC_EVT_TIME_OVF_TIMER2_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR = 0x4000
	// Position of LEDC_EVT_TIME_OVF_TIMER3_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_Pos = 0xf
	// Bit mask of LEDC_EVT_TIME_OVF_TIMER3_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_Msk = 0x8000
	// Bit LEDC_EVT_TIME_OVF_TIMER3_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR = 0x8000
	// Position of LEDC_EVT_TIMER0_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER0_CMP_ST_CLR_Pos = 0x10
	// Bit mask of LEDC_EVT_TIMER0_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER0_CMP_ST_CLR_Msk = 0x10000
	// Bit LEDC_EVT_TIMER0_CMP_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER0_CMP_ST_CLR = 0x10000
	// Position of LEDC_EVT_TIMER1_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER1_CMP_ST_CLR_Pos = 0x11
	// Bit mask of LEDC_EVT_TIMER1_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER1_CMP_ST_CLR_Msk = 0x20000
	// Bit LEDC_EVT_TIMER1_CMP_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER1_CMP_ST_CLR = 0x20000
	// Position of LEDC_EVT_TIMER2_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER2_CMP_ST_CLR_Pos = 0x12
	// Bit mask of LEDC_EVT_TIMER2_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER2_CMP_ST_CLR_Msk = 0x40000
	// Bit LEDC_EVT_TIMER2_CMP_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER2_CMP_ST_CLR = 0x40000
	// Position of LEDC_EVT_TIMER3_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER3_CMP_ST_CLR_Pos = 0x13
	// Bit mask of LEDC_EVT_TIMER3_CMP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER3_CMP_ST_CLR_Msk = 0x80000
	// Bit LEDC_EVT_TIMER3_CMP_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_LEDC_EVT_TIMER3_CMP_ST_CLR = 0x80000
	// Position of TG0_EVT_CNT_CMP_TIMER0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_Pos = 0x14
	// Bit mask of TG0_EVT_CNT_CMP_TIMER0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_Msk = 0x100000
	// Bit TG0_EVT_CNT_CMP_TIMER0_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER0_ST_CLR = 0x100000
	// Position of TG0_EVT_CNT_CMP_TIMER1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_Pos = 0x15
	// Bit mask of TG0_EVT_CNT_CMP_TIMER1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_Msk = 0x200000
	// Bit TG0_EVT_CNT_CMP_TIMER1_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_TG0_EVT_CNT_CMP_TIMER1_ST_CLR = 0x200000
	// Position of TG1_EVT_CNT_CMP_TIMER0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_Pos = 0x16
	// Bit mask of TG1_EVT_CNT_CMP_TIMER0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_Msk = 0x400000
	// Bit TG1_EVT_CNT_CMP_TIMER0_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER0_ST_CLR = 0x400000
	// Position of TG1_EVT_CNT_CMP_TIMER1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_Pos = 0x17
	// Bit mask of TG1_EVT_CNT_CMP_TIMER1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_Msk = 0x800000
	// Bit TG1_EVT_CNT_CMP_TIMER1_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_TG1_EVT_CNT_CMP_TIMER1_ST_CLR = 0x800000
	// Position of SYSTIMER_EVT_CNT_CMP0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP0_ST_CLR_Pos = 0x18
	// Bit mask of SYSTIMER_EVT_CNT_CMP0_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP0_ST_CLR_Msk = 0x1000000
	// Bit SYSTIMER_EVT_CNT_CMP0_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP0_ST_CLR = 0x1000000
	// Position of SYSTIMER_EVT_CNT_CMP1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP1_ST_CLR_Pos = 0x19
	// Bit mask of SYSTIMER_EVT_CNT_CMP1_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP1_ST_CLR_Msk = 0x2000000
	// Bit SYSTIMER_EVT_CNT_CMP1_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP1_ST_CLR = 0x2000000
	// Position of SYSTIMER_EVT_CNT_CMP2_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP2_ST_CLR_Pos = 0x1a
	// Bit mask of SYSTIMER_EVT_CNT_CMP2_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP2_ST_CLR_Msk = 0x4000000
	// Bit SYSTIMER_EVT_CNT_CMP2_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_SYSTIMER_EVT_CNT_CMP2_ST_CLR = 0x4000000
	// Position of MCPWM0_EVT_TIMER0_STOP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER0_STOP_ST_CLR_Pos = 0x1b
	// Bit mask of MCPWM0_EVT_TIMER0_STOP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER0_STOP_ST_CLR_Msk = 0x8000000
	// Bit MCPWM0_EVT_TIMER0_STOP_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER0_STOP_ST_CLR = 0x8000000
	// Position of MCPWM0_EVT_TIMER1_STOP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER1_STOP_ST_CLR_Pos = 0x1c
	// Bit mask of MCPWM0_EVT_TIMER1_STOP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER1_STOP_ST_CLR_Msk = 0x10000000
	// Bit MCPWM0_EVT_TIMER1_STOP_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER1_STOP_ST_CLR = 0x10000000
	// Position of MCPWM0_EVT_TIMER2_STOP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER2_STOP_ST_CLR_Pos = 0x1d
	// Bit mask of MCPWM0_EVT_TIMER2_STOP_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER2_STOP_ST_CLR_Msk = 0x20000000
	// Bit MCPWM0_EVT_TIMER2_STOP_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER2_STOP_ST_CLR = 0x20000000
	// Position of MCPWM0_EVT_TIMER0_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_Pos = 0x1e
	// Bit mask of MCPWM0_EVT_TIMER0_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER0_TEZ_ST_CLR_Msk = 0x40000000
	// Bit MCPWM0_EVT_TIMER0_TEZ_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER0_TEZ_ST_CLR = 0x40000000
	// Position of MCPWM0_EVT_TIMER1_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_Pos = 0x1f
	// Bit mask of MCPWM0_EVT_TIMER1_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER1_TEZ_ST_CLR_Msk = 0x80000000
	// Bit MCPWM0_EVT_TIMER1_TEZ_ST_CLR.
	SOC_ETM_EVT_ST1_CLR_MCPWM0_EVT_TIMER1_TEZ_ST_CLR = 0x80000000

	// EVT_ST2: Events trigger status register
	// Position of MCPWM0_EVT_TIMER2_TEZ_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER2_TEZ_ST_Pos = 0x0
	// Bit mask of MCPWM0_EVT_TIMER2_TEZ_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER2_TEZ_ST_Msk = 0x1
	// Bit MCPWM0_EVT_TIMER2_TEZ_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER2_TEZ_ST = 0x1
	// Position of MCPWM0_EVT_TIMER0_TEP_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER0_TEP_ST_Pos = 0x1
	// Bit mask of MCPWM0_EVT_TIMER0_TEP_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER0_TEP_ST_Msk = 0x2
	// Bit MCPWM0_EVT_TIMER0_TEP_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER0_TEP_ST = 0x2
	// Position of MCPWM0_EVT_TIMER1_TEP_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER1_TEP_ST_Pos = 0x2
	// Bit mask of MCPWM0_EVT_TIMER1_TEP_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER1_TEP_ST_Msk = 0x4
	// Bit MCPWM0_EVT_TIMER1_TEP_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER1_TEP_ST = 0x4
	// Position of MCPWM0_EVT_TIMER2_TEP_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER2_TEP_ST_Pos = 0x3
	// Bit mask of MCPWM0_EVT_TIMER2_TEP_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER2_TEP_ST_Msk = 0x8
	// Bit MCPWM0_EVT_TIMER2_TEP_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TIMER2_TEP_ST = 0x8
	// Position of MCPWM0_EVT_OP0_TEA_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEA_ST_Pos = 0x4
	// Bit mask of MCPWM0_EVT_OP0_TEA_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEA_ST_Msk = 0x10
	// Bit MCPWM0_EVT_OP0_TEA_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEA_ST = 0x10
	// Position of MCPWM0_EVT_OP1_TEA_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEA_ST_Pos = 0x5
	// Bit mask of MCPWM0_EVT_OP1_TEA_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEA_ST_Msk = 0x20
	// Bit MCPWM0_EVT_OP1_TEA_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEA_ST = 0x20
	// Position of MCPWM0_EVT_OP2_TEA_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEA_ST_Pos = 0x6
	// Bit mask of MCPWM0_EVT_OP2_TEA_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEA_ST_Msk = 0x40
	// Bit MCPWM0_EVT_OP2_TEA_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEA_ST = 0x40
	// Position of MCPWM0_EVT_OP0_TEB_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEB_ST_Pos = 0x7
	// Bit mask of MCPWM0_EVT_OP0_TEB_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEB_ST_Msk = 0x80
	// Bit MCPWM0_EVT_OP0_TEB_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEB_ST = 0x80
	// Position of MCPWM0_EVT_OP1_TEB_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEB_ST_Pos = 0x8
	// Bit mask of MCPWM0_EVT_OP1_TEB_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEB_ST_Msk = 0x100
	// Bit MCPWM0_EVT_OP1_TEB_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEB_ST = 0x100
	// Position of MCPWM0_EVT_OP2_TEB_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEB_ST_Pos = 0x9
	// Bit mask of MCPWM0_EVT_OP2_TEB_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEB_ST_Msk = 0x200
	// Bit MCPWM0_EVT_OP2_TEB_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEB_ST = 0x200
	// Position of MCPWM0_EVT_F0_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F0_ST_Pos = 0xa
	// Bit mask of MCPWM0_EVT_F0_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F0_ST_Msk = 0x400
	// Bit MCPWM0_EVT_F0_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F0_ST = 0x400
	// Position of MCPWM0_EVT_F1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F1_ST_Pos = 0xb
	// Bit mask of MCPWM0_EVT_F1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F1_ST_Msk = 0x800
	// Bit MCPWM0_EVT_F1_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F1_ST = 0x800
	// Position of MCPWM0_EVT_F2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F2_ST_Pos = 0xc
	// Bit mask of MCPWM0_EVT_F2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F2_ST_Msk = 0x1000
	// Bit MCPWM0_EVT_F2_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F2_ST = 0x1000
	// Position of MCPWM0_EVT_F0_CLR_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F0_CLR_ST_Pos = 0xd
	// Bit mask of MCPWM0_EVT_F0_CLR_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F0_CLR_ST_Msk = 0x2000
	// Bit MCPWM0_EVT_F0_CLR_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F0_CLR_ST = 0x2000
	// Position of MCPWM0_EVT_F1_CLR_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F1_CLR_ST_Pos = 0xe
	// Bit mask of MCPWM0_EVT_F1_CLR_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F1_CLR_ST_Msk = 0x4000
	// Bit MCPWM0_EVT_F1_CLR_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F1_CLR_ST = 0x4000
	// Position of MCPWM0_EVT_F2_CLR_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F2_CLR_ST_Pos = 0xf
	// Bit mask of MCPWM0_EVT_F2_CLR_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F2_CLR_ST_Msk = 0x8000
	// Bit MCPWM0_EVT_F2_CLR_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_F2_CLR_ST = 0x8000
	// Position of MCPWM0_EVT_TZ0_CBC_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ0_CBC_ST_Pos = 0x10
	// Bit mask of MCPWM0_EVT_TZ0_CBC_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ0_CBC_ST_Msk = 0x10000
	// Bit MCPWM0_EVT_TZ0_CBC_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ0_CBC_ST = 0x10000
	// Position of MCPWM0_EVT_TZ1_CBC_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ1_CBC_ST_Pos = 0x11
	// Bit mask of MCPWM0_EVT_TZ1_CBC_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ1_CBC_ST_Msk = 0x20000
	// Bit MCPWM0_EVT_TZ1_CBC_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ1_CBC_ST = 0x20000
	// Position of MCPWM0_EVT_TZ2_CBC_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ2_CBC_ST_Pos = 0x12
	// Bit mask of MCPWM0_EVT_TZ2_CBC_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ2_CBC_ST_Msk = 0x40000
	// Bit MCPWM0_EVT_TZ2_CBC_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ2_CBC_ST = 0x40000
	// Position of MCPWM0_EVT_TZ0_OST_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ0_OST_ST_Pos = 0x13
	// Bit mask of MCPWM0_EVT_TZ0_OST_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ0_OST_ST_Msk = 0x80000
	// Bit MCPWM0_EVT_TZ0_OST_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ0_OST_ST = 0x80000
	// Position of MCPWM0_EVT_TZ1_OST_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ1_OST_ST_Pos = 0x14
	// Bit mask of MCPWM0_EVT_TZ1_OST_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ1_OST_ST_Msk = 0x100000
	// Bit MCPWM0_EVT_TZ1_OST_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ1_OST_ST = 0x100000
	// Position of MCPWM0_EVT_TZ2_OST_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ2_OST_ST_Pos = 0x15
	// Bit mask of MCPWM0_EVT_TZ2_OST_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ2_OST_ST_Msk = 0x200000
	// Bit MCPWM0_EVT_TZ2_OST_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_TZ2_OST_ST = 0x200000
	// Position of MCPWM0_EVT_CAP0_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP0_ST_Pos = 0x16
	// Bit mask of MCPWM0_EVT_CAP0_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP0_ST_Msk = 0x400000
	// Bit MCPWM0_EVT_CAP0_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP0_ST = 0x400000
	// Position of MCPWM0_EVT_CAP1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP1_ST_Pos = 0x17
	// Bit mask of MCPWM0_EVT_CAP1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP1_ST_Msk = 0x800000
	// Bit MCPWM0_EVT_CAP1_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP1_ST = 0x800000
	// Position of MCPWM0_EVT_CAP2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP2_ST_Pos = 0x18
	// Bit mask of MCPWM0_EVT_CAP2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP2_ST_Msk = 0x1000000
	// Bit MCPWM0_EVT_CAP2_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_CAP2_ST = 0x1000000
	// Position of MCPWM0_EVT_OP0_TEE1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEE1_ST_Pos = 0x19
	// Bit mask of MCPWM0_EVT_OP0_TEE1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEE1_ST_Msk = 0x2000000
	// Bit MCPWM0_EVT_OP0_TEE1_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEE1_ST = 0x2000000
	// Position of MCPWM0_EVT_OP1_TEE1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEE1_ST_Pos = 0x1a
	// Bit mask of MCPWM0_EVT_OP1_TEE1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEE1_ST_Msk = 0x4000000
	// Bit MCPWM0_EVT_OP1_TEE1_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEE1_ST = 0x4000000
	// Position of MCPWM0_EVT_OP2_TEE1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEE1_ST_Pos = 0x1b
	// Bit mask of MCPWM0_EVT_OP2_TEE1_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEE1_ST_Msk = 0x8000000
	// Bit MCPWM0_EVT_OP2_TEE1_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEE1_ST = 0x8000000
	// Position of MCPWM0_EVT_OP0_TEE2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEE2_ST_Pos = 0x1c
	// Bit mask of MCPWM0_EVT_OP0_TEE2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEE2_ST_Msk = 0x10000000
	// Bit MCPWM0_EVT_OP0_TEE2_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP0_TEE2_ST = 0x10000000
	// Position of MCPWM0_EVT_OP1_TEE2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEE2_ST_Pos = 0x1d
	// Bit mask of MCPWM0_EVT_OP1_TEE2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEE2_ST_Msk = 0x20000000
	// Bit MCPWM0_EVT_OP1_TEE2_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP1_TEE2_ST = 0x20000000
	// Position of MCPWM0_EVT_OP2_TEE2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEE2_ST_Pos = 0x1e
	// Bit mask of MCPWM0_EVT_OP2_TEE2_ST field.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEE2_ST_Msk = 0x40000000
	// Bit MCPWM0_EVT_OP2_TEE2_ST.
	SOC_ETM_EVT_ST2_MCPWM0_EVT_OP2_TEE2_ST = 0x40000000
	// Position of MCPWM1_EVT_TIMER0_STOP_ST field.
	SOC_ETM_EVT_ST2_MCPWM1_EVT_TIMER0_STOP_ST_Pos = 0x1f
	// Bit mask of MCPWM1_EVT_TIMER0_STOP_ST field.
	SOC_ETM_EVT_ST2_MCPWM1_EVT_TIMER0_STOP_ST_Msk = 0x80000000
	// Bit MCPWM1_EVT_TIMER0_STOP_ST.
	SOC_ETM_EVT_ST2_MCPWM1_EVT_TIMER0_STOP_ST = 0x80000000

	// EVT_ST2_CLR: Events trigger status clear register
	// Position of MCPWM0_EVT_TIMER2_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_Pos = 0x0
	// Bit mask of MCPWM0_EVT_TIMER2_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEZ_ST_CLR_Msk = 0x1
	// Bit MCPWM0_EVT_TIMER2_TEZ_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEZ_ST_CLR = 0x1
	// Position of MCPWM0_EVT_TIMER0_TEP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER0_TEP_ST_CLR_Pos = 0x1
	// Bit mask of MCPWM0_EVT_TIMER0_TEP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER0_TEP_ST_CLR_Msk = 0x2
	// Bit MCPWM0_EVT_TIMER0_TEP_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER0_TEP_ST_CLR = 0x2
	// Position of MCPWM0_EVT_TIMER1_TEP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER1_TEP_ST_CLR_Pos = 0x2
	// Bit mask of MCPWM0_EVT_TIMER1_TEP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER1_TEP_ST_CLR_Msk = 0x4
	// Bit MCPWM0_EVT_TIMER1_TEP_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER1_TEP_ST_CLR = 0x4
	// Position of MCPWM0_EVT_TIMER2_TEP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEP_ST_CLR_Pos = 0x3
	// Bit mask of MCPWM0_EVT_TIMER2_TEP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEP_ST_CLR_Msk = 0x8
	// Bit MCPWM0_EVT_TIMER2_TEP_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TIMER2_TEP_ST_CLR = 0x8
	// Position of MCPWM0_EVT_OP0_TEA_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEA_ST_CLR_Pos = 0x4
	// Bit mask of MCPWM0_EVT_OP0_TEA_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEA_ST_CLR_Msk = 0x10
	// Bit MCPWM0_EVT_OP0_TEA_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEA_ST_CLR = 0x10
	// Position of MCPWM0_EVT_OP1_TEA_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEA_ST_CLR_Pos = 0x5
	// Bit mask of MCPWM0_EVT_OP1_TEA_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEA_ST_CLR_Msk = 0x20
	// Bit MCPWM0_EVT_OP1_TEA_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEA_ST_CLR = 0x20
	// Position of MCPWM0_EVT_OP2_TEA_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEA_ST_CLR_Pos = 0x6
	// Bit mask of MCPWM0_EVT_OP2_TEA_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEA_ST_CLR_Msk = 0x40
	// Bit MCPWM0_EVT_OP2_TEA_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEA_ST_CLR = 0x40
	// Position of MCPWM0_EVT_OP0_TEB_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEB_ST_CLR_Pos = 0x7
	// Bit mask of MCPWM0_EVT_OP0_TEB_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEB_ST_CLR_Msk = 0x80
	// Bit MCPWM0_EVT_OP0_TEB_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEB_ST_CLR = 0x80
	// Position of MCPWM0_EVT_OP1_TEB_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEB_ST_CLR_Pos = 0x8
	// Bit mask of MCPWM0_EVT_OP1_TEB_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEB_ST_CLR_Msk = 0x100
	// Bit MCPWM0_EVT_OP1_TEB_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEB_ST_CLR = 0x100
	// Position of MCPWM0_EVT_OP2_TEB_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEB_ST_CLR_Pos = 0x9
	// Bit mask of MCPWM0_EVT_OP2_TEB_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEB_ST_CLR_Msk = 0x200
	// Bit MCPWM0_EVT_OP2_TEB_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEB_ST_CLR = 0x200
	// Position of MCPWM0_EVT_F0_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F0_ST_CLR_Pos = 0xa
	// Bit mask of MCPWM0_EVT_F0_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F0_ST_CLR_Msk = 0x400
	// Bit MCPWM0_EVT_F0_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F0_ST_CLR = 0x400
	// Position of MCPWM0_EVT_F1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F1_ST_CLR_Pos = 0xb
	// Bit mask of MCPWM0_EVT_F1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F1_ST_CLR_Msk = 0x800
	// Bit MCPWM0_EVT_F1_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F1_ST_CLR = 0x800
	// Position of MCPWM0_EVT_F2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F2_ST_CLR_Pos = 0xc
	// Bit mask of MCPWM0_EVT_F2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F2_ST_CLR_Msk = 0x1000
	// Bit MCPWM0_EVT_F2_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F2_ST_CLR = 0x1000
	// Position of MCPWM0_EVT_F0_CLR_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F0_CLR_ST_CLR_Pos = 0xd
	// Bit mask of MCPWM0_EVT_F0_CLR_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F0_CLR_ST_CLR_Msk = 0x2000
	// Bit MCPWM0_EVT_F0_CLR_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F0_CLR_ST_CLR = 0x2000
	// Position of MCPWM0_EVT_F1_CLR_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F1_CLR_ST_CLR_Pos = 0xe
	// Bit mask of MCPWM0_EVT_F1_CLR_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F1_CLR_ST_CLR_Msk = 0x4000
	// Bit MCPWM0_EVT_F1_CLR_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F1_CLR_ST_CLR = 0x4000
	// Position of MCPWM0_EVT_F2_CLR_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F2_CLR_ST_CLR_Pos = 0xf
	// Bit mask of MCPWM0_EVT_F2_CLR_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F2_CLR_ST_CLR_Msk = 0x8000
	// Bit MCPWM0_EVT_F2_CLR_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_F2_CLR_ST_CLR = 0x8000
	// Position of MCPWM0_EVT_TZ0_CBC_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ0_CBC_ST_CLR_Pos = 0x10
	// Bit mask of MCPWM0_EVT_TZ0_CBC_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ0_CBC_ST_CLR_Msk = 0x10000
	// Bit MCPWM0_EVT_TZ0_CBC_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ0_CBC_ST_CLR = 0x10000
	// Position of MCPWM0_EVT_TZ1_CBC_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ1_CBC_ST_CLR_Pos = 0x11
	// Bit mask of MCPWM0_EVT_TZ1_CBC_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ1_CBC_ST_CLR_Msk = 0x20000
	// Bit MCPWM0_EVT_TZ1_CBC_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ1_CBC_ST_CLR = 0x20000
	// Position of MCPWM0_EVT_TZ2_CBC_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ2_CBC_ST_CLR_Pos = 0x12
	// Bit mask of MCPWM0_EVT_TZ2_CBC_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ2_CBC_ST_CLR_Msk = 0x40000
	// Bit MCPWM0_EVT_TZ2_CBC_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ2_CBC_ST_CLR = 0x40000
	// Position of MCPWM0_EVT_TZ0_OST_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ0_OST_ST_CLR_Pos = 0x13
	// Bit mask of MCPWM0_EVT_TZ0_OST_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ0_OST_ST_CLR_Msk = 0x80000
	// Bit MCPWM0_EVT_TZ0_OST_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ0_OST_ST_CLR = 0x80000
	// Position of MCPWM0_EVT_TZ1_OST_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ1_OST_ST_CLR_Pos = 0x14
	// Bit mask of MCPWM0_EVT_TZ1_OST_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ1_OST_ST_CLR_Msk = 0x100000
	// Bit MCPWM0_EVT_TZ1_OST_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ1_OST_ST_CLR = 0x100000
	// Position of MCPWM0_EVT_TZ2_OST_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ2_OST_ST_CLR_Pos = 0x15
	// Bit mask of MCPWM0_EVT_TZ2_OST_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ2_OST_ST_CLR_Msk = 0x200000
	// Bit MCPWM0_EVT_TZ2_OST_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_TZ2_OST_ST_CLR = 0x200000
	// Position of MCPWM0_EVT_CAP0_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP0_ST_CLR_Pos = 0x16
	// Bit mask of MCPWM0_EVT_CAP0_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP0_ST_CLR_Msk = 0x400000
	// Bit MCPWM0_EVT_CAP0_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP0_ST_CLR = 0x400000
	// Position of MCPWM0_EVT_CAP1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP1_ST_CLR_Pos = 0x17
	// Bit mask of MCPWM0_EVT_CAP1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP1_ST_CLR_Msk = 0x800000
	// Bit MCPWM0_EVT_CAP1_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP1_ST_CLR = 0x800000
	// Position of MCPWM0_EVT_CAP2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP2_ST_CLR_Pos = 0x18
	// Bit mask of MCPWM0_EVT_CAP2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP2_ST_CLR_Msk = 0x1000000
	// Bit MCPWM0_EVT_CAP2_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_CAP2_ST_CLR = 0x1000000
	// Position of MCPWM0_EVT_OP0_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEE1_ST_CLR_Pos = 0x19
	// Bit mask of MCPWM0_EVT_OP0_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEE1_ST_CLR_Msk = 0x2000000
	// Bit MCPWM0_EVT_OP0_TEE1_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEE1_ST_CLR = 0x2000000
	// Position of MCPWM0_EVT_OP1_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEE1_ST_CLR_Pos = 0x1a
	// Bit mask of MCPWM0_EVT_OP1_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEE1_ST_CLR_Msk = 0x4000000
	// Bit MCPWM0_EVT_OP1_TEE1_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEE1_ST_CLR = 0x4000000
	// Position of MCPWM0_EVT_OP2_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEE1_ST_CLR_Pos = 0x1b
	// Bit mask of MCPWM0_EVT_OP2_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEE1_ST_CLR_Msk = 0x8000000
	// Bit MCPWM0_EVT_OP2_TEE1_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEE1_ST_CLR = 0x8000000
	// Position of MCPWM0_EVT_OP0_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEE2_ST_CLR_Pos = 0x1c
	// Bit mask of MCPWM0_EVT_OP0_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEE2_ST_CLR_Msk = 0x10000000
	// Bit MCPWM0_EVT_OP0_TEE2_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP0_TEE2_ST_CLR = 0x10000000
	// Position of MCPWM0_EVT_OP1_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEE2_ST_CLR_Pos = 0x1d
	// Bit mask of MCPWM0_EVT_OP1_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEE2_ST_CLR_Msk = 0x20000000
	// Bit MCPWM0_EVT_OP1_TEE2_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP1_TEE2_ST_CLR = 0x20000000
	// Position of MCPWM0_EVT_OP2_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEE2_ST_CLR_Pos = 0x1e
	// Bit mask of MCPWM0_EVT_OP2_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEE2_ST_CLR_Msk = 0x40000000
	// Bit MCPWM0_EVT_OP2_TEE2_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM0_EVT_OP2_TEE2_ST_CLR = 0x40000000
	// Position of MCPWM1_EVT_TIMER0_STOP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM1_EVT_TIMER0_STOP_ST_CLR_Pos = 0x1f
	// Bit mask of MCPWM1_EVT_TIMER0_STOP_ST_CLR field.
	SOC_ETM_EVT_ST2_CLR_MCPWM1_EVT_TIMER0_STOP_ST_CLR_Msk = 0x80000000
	// Bit MCPWM1_EVT_TIMER0_STOP_ST_CLR.
	SOC_ETM_EVT_ST2_CLR_MCPWM1_EVT_TIMER0_STOP_ST_CLR = 0x80000000

	// EVT_ST3: Events trigger status register
	// Position of MCPWM1_EVT_TIMER1_STOP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_STOP_ST_Pos = 0x0
	// Bit mask of MCPWM1_EVT_TIMER1_STOP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_STOP_ST_Msk = 0x1
	// Bit MCPWM1_EVT_TIMER1_STOP_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_STOP_ST = 0x1
	// Position of MCPWM1_EVT_TIMER2_STOP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_STOP_ST_Pos = 0x1
	// Bit mask of MCPWM1_EVT_TIMER2_STOP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_STOP_ST_Msk = 0x2
	// Bit MCPWM1_EVT_TIMER2_STOP_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_STOP_ST = 0x2
	// Position of MCPWM1_EVT_TIMER0_TEZ_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER0_TEZ_ST_Pos = 0x2
	// Bit mask of MCPWM1_EVT_TIMER0_TEZ_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER0_TEZ_ST_Msk = 0x4
	// Bit MCPWM1_EVT_TIMER0_TEZ_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER0_TEZ_ST = 0x4
	// Position of MCPWM1_EVT_TIMER1_TEZ_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_TEZ_ST_Pos = 0x3
	// Bit mask of MCPWM1_EVT_TIMER1_TEZ_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_TEZ_ST_Msk = 0x8
	// Bit MCPWM1_EVT_TIMER1_TEZ_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_TEZ_ST = 0x8
	// Position of MCPWM1_EVT_TIMER2_TEZ_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_TEZ_ST_Pos = 0x4
	// Bit mask of MCPWM1_EVT_TIMER2_TEZ_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_TEZ_ST_Msk = 0x10
	// Bit MCPWM1_EVT_TIMER2_TEZ_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_TEZ_ST = 0x10
	// Position of MCPWM1_EVT_TIMER0_TEP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER0_TEP_ST_Pos = 0x5
	// Bit mask of MCPWM1_EVT_TIMER0_TEP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER0_TEP_ST_Msk = 0x20
	// Bit MCPWM1_EVT_TIMER0_TEP_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER0_TEP_ST = 0x20
	// Position of MCPWM1_EVT_TIMER1_TEP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_TEP_ST_Pos = 0x6
	// Bit mask of MCPWM1_EVT_TIMER1_TEP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_TEP_ST_Msk = 0x40
	// Bit MCPWM1_EVT_TIMER1_TEP_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER1_TEP_ST = 0x40
	// Position of MCPWM1_EVT_TIMER2_TEP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_TEP_ST_Pos = 0x7
	// Bit mask of MCPWM1_EVT_TIMER2_TEP_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_TEP_ST_Msk = 0x80
	// Bit MCPWM1_EVT_TIMER2_TEP_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TIMER2_TEP_ST = 0x80
	// Position of MCPWM1_EVT_OP0_TEA_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEA_ST_Pos = 0x8
	// Bit mask of MCPWM1_EVT_OP0_TEA_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEA_ST_Msk = 0x100
	// Bit MCPWM1_EVT_OP0_TEA_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEA_ST = 0x100
	// Position of MCPWM1_EVT_OP1_TEA_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEA_ST_Pos = 0x9
	// Bit mask of MCPWM1_EVT_OP1_TEA_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEA_ST_Msk = 0x200
	// Bit MCPWM1_EVT_OP1_TEA_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEA_ST = 0x200
	// Position of MCPWM1_EVT_OP2_TEA_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEA_ST_Pos = 0xa
	// Bit mask of MCPWM1_EVT_OP2_TEA_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEA_ST_Msk = 0x400
	// Bit MCPWM1_EVT_OP2_TEA_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEA_ST = 0x400
	// Position of MCPWM1_EVT_OP0_TEB_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEB_ST_Pos = 0xb
	// Bit mask of MCPWM1_EVT_OP0_TEB_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEB_ST_Msk = 0x800
	// Bit MCPWM1_EVT_OP0_TEB_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEB_ST = 0x800
	// Position of MCPWM1_EVT_OP1_TEB_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEB_ST_Pos = 0xc
	// Bit mask of MCPWM1_EVT_OP1_TEB_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEB_ST_Msk = 0x1000
	// Bit MCPWM1_EVT_OP1_TEB_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEB_ST = 0x1000
	// Position of MCPWM1_EVT_OP2_TEB_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEB_ST_Pos = 0xd
	// Bit mask of MCPWM1_EVT_OP2_TEB_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEB_ST_Msk = 0x2000
	// Bit MCPWM1_EVT_OP2_TEB_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEB_ST = 0x2000
	// Position of MCPWM1_EVT_F0_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F0_ST_Pos = 0xe
	// Bit mask of MCPWM1_EVT_F0_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F0_ST_Msk = 0x4000
	// Bit MCPWM1_EVT_F0_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F0_ST = 0x4000
	// Position of MCPWM1_EVT_F1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F1_ST_Pos = 0xf
	// Bit mask of MCPWM1_EVT_F1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F1_ST_Msk = 0x8000
	// Bit MCPWM1_EVT_F1_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F1_ST = 0x8000
	// Position of MCPWM1_EVT_F2_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F2_ST_Pos = 0x10
	// Bit mask of MCPWM1_EVT_F2_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F2_ST_Msk = 0x10000
	// Bit MCPWM1_EVT_F2_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F2_ST = 0x10000
	// Position of MCPWM1_EVT_F0_CLR_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F0_CLR_ST_Pos = 0x11
	// Bit mask of MCPWM1_EVT_F0_CLR_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F0_CLR_ST_Msk = 0x20000
	// Bit MCPWM1_EVT_F0_CLR_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F0_CLR_ST = 0x20000
	// Position of MCPWM1_EVT_F1_CLR_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F1_CLR_ST_Pos = 0x12
	// Bit mask of MCPWM1_EVT_F1_CLR_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F1_CLR_ST_Msk = 0x40000
	// Bit MCPWM1_EVT_F1_CLR_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F1_CLR_ST = 0x40000
	// Position of MCPWM1_EVT_F2_CLR_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F2_CLR_ST_Pos = 0x13
	// Bit mask of MCPWM1_EVT_F2_CLR_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F2_CLR_ST_Msk = 0x80000
	// Bit MCPWM1_EVT_F2_CLR_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_F2_CLR_ST = 0x80000
	// Position of MCPWM1_EVT_TZ0_CBC_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ0_CBC_ST_Pos = 0x14
	// Bit mask of MCPWM1_EVT_TZ0_CBC_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ0_CBC_ST_Msk = 0x100000
	// Bit MCPWM1_EVT_TZ0_CBC_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ0_CBC_ST = 0x100000
	// Position of MCPWM1_EVT_TZ1_CBC_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ1_CBC_ST_Pos = 0x15
	// Bit mask of MCPWM1_EVT_TZ1_CBC_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ1_CBC_ST_Msk = 0x200000
	// Bit MCPWM1_EVT_TZ1_CBC_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ1_CBC_ST = 0x200000
	// Position of MCPWM1_EVT_TZ2_CBC_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ2_CBC_ST_Pos = 0x16
	// Bit mask of MCPWM1_EVT_TZ2_CBC_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ2_CBC_ST_Msk = 0x400000
	// Bit MCPWM1_EVT_TZ2_CBC_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ2_CBC_ST = 0x400000
	// Position of MCPWM1_EVT_TZ0_OST_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ0_OST_ST_Pos = 0x17
	// Bit mask of MCPWM1_EVT_TZ0_OST_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ0_OST_ST_Msk = 0x800000
	// Bit MCPWM1_EVT_TZ0_OST_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ0_OST_ST = 0x800000
	// Position of MCPWM1_EVT_TZ1_OST_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ1_OST_ST_Pos = 0x18
	// Bit mask of MCPWM1_EVT_TZ1_OST_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ1_OST_ST_Msk = 0x1000000
	// Bit MCPWM1_EVT_TZ1_OST_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ1_OST_ST = 0x1000000
	// Position of MCPWM1_EVT_TZ2_OST_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ2_OST_ST_Pos = 0x19
	// Bit mask of MCPWM1_EVT_TZ2_OST_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ2_OST_ST_Msk = 0x2000000
	// Bit MCPWM1_EVT_TZ2_OST_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_TZ2_OST_ST = 0x2000000
	// Position of MCPWM1_EVT_CAP0_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP0_ST_Pos = 0x1a
	// Bit mask of MCPWM1_EVT_CAP0_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP0_ST_Msk = 0x4000000
	// Bit MCPWM1_EVT_CAP0_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP0_ST = 0x4000000
	// Position of MCPWM1_EVT_CAP1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP1_ST_Pos = 0x1b
	// Bit mask of MCPWM1_EVT_CAP1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP1_ST_Msk = 0x8000000
	// Bit MCPWM1_EVT_CAP1_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP1_ST = 0x8000000
	// Position of MCPWM1_EVT_CAP2_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP2_ST_Pos = 0x1c
	// Bit mask of MCPWM1_EVT_CAP2_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP2_ST_Msk = 0x10000000
	// Bit MCPWM1_EVT_CAP2_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_CAP2_ST = 0x10000000
	// Position of MCPWM1_EVT_OP0_TEE1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEE1_ST_Pos = 0x1d
	// Bit mask of MCPWM1_EVT_OP0_TEE1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEE1_ST_Msk = 0x20000000
	// Bit MCPWM1_EVT_OP0_TEE1_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP0_TEE1_ST = 0x20000000
	// Position of MCPWM1_EVT_OP1_TEE1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEE1_ST_Pos = 0x1e
	// Bit mask of MCPWM1_EVT_OP1_TEE1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEE1_ST_Msk = 0x40000000
	// Bit MCPWM1_EVT_OP1_TEE1_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP1_TEE1_ST = 0x40000000
	// Position of MCPWM1_EVT_OP2_TEE1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEE1_ST_Pos = 0x1f
	// Bit mask of MCPWM1_EVT_OP2_TEE1_ST field.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEE1_ST_Msk = 0x80000000
	// Bit MCPWM1_EVT_OP2_TEE1_ST.
	SOC_ETM_EVT_ST3_MCPWM1_EVT_OP2_TEE1_ST = 0x80000000

	// EVT_ST3_CLR: Events trigger status clear register
	// Position of MCPWM1_EVT_TIMER1_STOP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_STOP_ST_CLR_Pos = 0x0
	// Bit mask of MCPWM1_EVT_TIMER1_STOP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_STOP_ST_CLR_Msk = 0x1
	// Bit MCPWM1_EVT_TIMER1_STOP_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_STOP_ST_CLR = 0x1
	// Position of MCPWM1_EVT_TIMER2_STOP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_STOP_ST_CLR_Pos = 0x1
	// Bit mask of MCPWM1_EVT_TIMER2_STOP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_STOP_ST_CLR_Msk = 0x2
	// Bit MCPWM1_EVT_TIMER2_STOP_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_STOP_ST_CLR = 0x2
	// Position of MCPWM1_EVT_TIMER0_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_Pos = 0x2
	// Bit mask of MCPWM1_EVT_TIMER0_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEZ_ST_CLR_Msk = 0x4
	// Bit MCPWM1_EVT_TIMER0_TEZ_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEZ_ST_CLR = 0x4
	// Position of MCPWM1_EVT_TIMER1_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_Pos = 0x3
	// Bit mask of MCPWM1_EVT_TIMER1_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEZ_ST_CLR_Msk = 0x8
	// Bit MCPWM1_EVT_TIMER1_TEZ_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEZ_ST_CLR = 0x8
	// Position of MCPWM1_EVT_TIMER2_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_Pos = 0x4
	// Bit mask of MCPWM1_EVT_TIMER2_TEZ_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEZ_ST_CLR_Msk = 0x10
	// Bit MCPWM1_EVT_TIMER2_TEZ_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEZ_ST_CLR = 0x10
	// Position of MCPWM1_EVT_TIMER0_TEP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEP_ST_CLR_Pos = 0x5
	// Bit mask of MCPWM1_EVT_TIMER0_TEP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEP_ST_CLR_Msk = 0x20
	// Bit MCPWM1_EVT_TIMER0_TEP_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER0_TEP_ST_CLR = 0x20
	// Position of MCPWM1_EVT_TIMER1_TEP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEP_ST_CLR_Pos = 0x6
	// Bit mask of MCPWM1_EVT_TIMER1_TEP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEP_ST_CLR_Msk = 0x40
	// Bit MCPWM1_EVT_TIMER1_TEP_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER1_TEP_ST_CLR = 0x40
	// Position of MCPWM1_EVT_TIMER2_TEP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEP_ST_CLR_Pos = 0x7
	// Bit mask of MCPWM1_EVT_TIMER2_TEP_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEP_ST_CLR_Msk = 0x80
	// Bit MCPWM1_EVT_TIMER2_TEP_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TIMER2_TEP_ST_CLR = 0x80
	// Position of MCPWM1_EVT_OP0_TEA_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEA_ST_CLR_Pos = 0x8
	// Bit mask of MCPWM1_EVT_OP0_TEA_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEA_ST_CLR_Msk = 0x100
	// Bit MCPWM1_EVT_OP0_TEA_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEA_ST_CLR = 0x100
	// Position of MCPWM1_EVT_OP1_TEA_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEA_ST_CLR_Pos = 0x9
	// Bit mask of MCPWM1_EVT_OP1_TEA_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEA_ST_CLR_Msk = 0x200
	// Bit MCPWM1_EVT_OP1_TEA_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEA_ST_CLR = 0x200
	// Position of MCPWM1_EVT_OP2_TEA_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEA_ST_CLR_Pos = 0xa
	// Bit mask of MCPWM1_EVT_OP2_TEA_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEA_ST_CLR_Msk = 0x400
	// Bit MCPWM1_EVT_OP2_TEA_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEA_ST_CLR = 0x400
	// Position of MCPWM1_EVT_OP0_TEB_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEB_ST_CLR_Pos = 0xb
	// Bit mask of MCPWM1_EVT_OP0_TEB_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEB_ST_CLR_Msk = 0x800
	// Bit MCPWM1_EVT_OP0_TEB_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEB_ST_CLR = 0x800
	// Position of MCPWM1_EVT_OP1_TEB_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEB_ST_CLR_Pos = 0xc
	// Bit mask of MCPWM1_EVT_OP1_TEB_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEB_ST_CLR_Msk = 0x1000
	// Bit MCPWM1_EVT_OP1_TEB_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEB_ST_CLR = 0x1000
	// Position of MCPWM1_EVT_OP2_TEB_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEB_ST_CLR_Pos = 0xd
	// Bit mask of MCPWM1_EVT_OP2_TEB_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEB_ST_CLR_Msk = 0x2000
	// Bit MCPWM1_EVT_OP2_TEB_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEB_ST_CLR = 0x2000
	// Position of MCPWM1_EVT_F0_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F0_ST_CLR_Pos = 0xe
	// Bit mask of MCPWM1_EVT_F0_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F0_ST_CLR_Msk = 0x4000
	// Bit MCPWM1_EVT_F0_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F0_ST_CLR = 0x4000
	// Position of MCPWM1_EVT_F1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F1_ST_CLR_Pos = 0xf
	// Bit mask of MCPWM1_EVT_F1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F1_ST_CLR_Msk = 0x8000
	// Bit MCPWM1_EVT_F1_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F1_ST_CLR = 0x8000
	// Position of MCPWM1_EVT_F2_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F2_ST_CLR_Pos = 0x10
	// Bit mask of MCPWM1_EVT_F2_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F2_ST_CLR_Msk = 0x10000
	// Bit MCPWM1_EVT_F2_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F2_ST_CLR = 0x10000
	// Position of MCPWM1_EVT_F0_CLR_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F0_CLR_ST_CLR_Pos = 0x11
	// Bit mask of MCPWM1_EVT_F0_CLR_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F0_CLR_ST_CLR_Msk = 0x20000
	// Bit MCPWM1_EVT_F0_CLR_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F0_CLR_ST_CLR = 0x20000
	// Position of MCPWM1_EVT_F1_CLR_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F1_CLR_ST_CLR_Pos = 0x12
	// Bit mask of MCPWM1_EVT_F1_CLR_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F1_CLR_ST_CLR_Msk = 0x40000
	// Bit MCPWM1_EVT_F1_CLR_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F1_CLR_ST_CLR = 0x40000
	// Position of MCPWM1_EVT_F2_CLR_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F2_CLR_ST_CLR_Pos = 0x13
	// Bit mask of MCPWM1_EVT_F2_CLR_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F2_CLR_ST_CLR_Msk = 0x80000
	// Bit MCPWM1_EVT_F2_CLR_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_F2_CLR_ST_CLR = 0x80000
	// Position of MCPWM1_EVT_TZ0_CBC_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ0_CBC_ST_CLR_Pos = 0x14
	// Bit mask of MCPWM1_EVT_TZ0_CBC_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ0_CBC_ST_CLR_Msk = 0x100000
	// Bit MCPWM1_EVT_TZ0_CBC_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ0_CBC_ST_CLR = 0x100000
	// Position of MCPWM1_EVT_TZ1_CBC_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ1_CBC_ST_CLR_Pos = 0x15
	// Bit mask of MCPWM1_EVT_TZ1_CBC_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ1_CBC_ST_CLR_Msk = 0x200000
	// Bit MCPWM1_EVT_TZ1_CBC_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ1_CBC_ST_CLR = 0x200000
	// Position of MCPWM1_EVT_TZ2_CBC_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ2_CBC_ST_CLR_Pos = 0x16
	// Bit mask of MCPWM1_EVT_TZ2_CBC_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ2_CBC_ST_CLR_Msk = 0x400000
	// Bit MCPWM1_EVT_TZ2_CBC_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ2_CBC_ST_CLR = 0x400000
	// Position of MCPWM1_EVT_TZ0_OST_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ0_OST_ST_CLR_Pos = 0x17
	// Bit mask of MCPWM1_EVT_TZ0_OST_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ0_OST_ST_CLR_Msk = 0x800000
	// Bit MCPWM1_EVT_TZ0_OST_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ0_OST_ST_CLR = 0x800000
	// Position of MCPWM1_EVT_TZ1_OST_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ1_OST_ST_CLR_Pos = 0x18
	// Bit mask of MCPWM1_EVT_TZ1_OST_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ1_OST_ST_CLR_Msk = 0x1000000
	// Bit MCPWM1_EVT_TZ1_OST_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ1_OST_ST_CLR = 0x1000000
	// Position of MCPWM1_EVT_TZ2_OST_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ2_OST_ST_CLR_Pos = 0x19
	// Bit mask of MCPWM1_EVT_TZ2_OST_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ2_OST_ST_CLR_Msk = 0x2000000
	// Bit MCPWM1_EVT_TZ2_OST_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_TZ2_OST_ST_CLR = 0x2000000
	// Position of MCPWM1_EVT_CAP0_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP0_ST_CLR_Pos = 0x1a
	// Bit mask of MCPWM1_EVT_CAP0_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP0_ST_CLR_Msk = 0x4000000
	// Bit MCPWM1_EVT_CAP0_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP0_ST_CLR = 0x4000000
	// Position of MCPWM1_EVT_CAP1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP1_ST_CLR_Pos = 0x1b
	// Bit mask of MCPWM1_EVT_CAP1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP1_ST_CLR_Msk = 0x8000000
	// Bit MCPWM1_EVT_CAP1_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP1_ST_CLR = 0x8000000
	// Position of MCPWM1_EVT_CAP2_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP2_ST_CLR_Pos = 0x1c
	// Bit mask of MCPWM1_EVT_CAP2_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP2_ST_CLR_Msk = 0x10000000
	// Bit MCPWM1_EVT_CAP2_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_CAP2_ST_CLR = 0x10000000
	// Position of MCPWM1_EVT_OP0_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEE1_ST_CLR_Pos = 0x1d
	// Bit mask of MCPWM1_EVT_OP0_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEE1_ST_CLR_Msk = 0x20000000
	// Bit MCPWM1_EVT_OP0_TEE1_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP0_TEE1_ST_CLR = 0x20000000
	// Position of MCPWM1_EVT_OP1_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEE1_ST_CLR_Pos = 0x1e
	// Bit mask of MCPWM1_EVT_OP1_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEE1_ST_CLR_Msk = 0x40000000
	// Bit MCPWM1_EVT_OP1_TEE1_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP1_TEE1_ST_CLR = 0x40000000
	// Position of MCPWM1_EVT_OP2_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEE1_ST_CLR_Pos = 0x1f
	// Bit mask of MCPWM1_EVT_OP2_TEE1_ST_CLR field.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEE1_ST_CLR_Msk = 0x80000000
	// Bit MCPWM1_EVT_OP2_TEE1_ST_CLR.
	SOC_ETM_EVT_ST3_CLR_MCPWM1_EVT_OP2_TEE1_ST_CLR = 0x80000000

	// EVT_ST4: Events trigger status register
	// Position of MCPWM1_EVT_OP0_TEE2_ST field.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP0_TEE2_ST_Pos = 0x0
	// Bit mask of MCPWM1_EVT_OP0_TEE2_ST field.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP0_TEE2_ST_Msk = 0x1
	// Bit MCPWM1_EVT_OP0_TEE2_ST.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP0_TEE2_ST = 0x1
	// Position of MCPWM1_EVT_OP1_TEE2_ST field.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP1_TEE2_ST_Pos = 0x1
	// Bit mask of MCPWM1_EVT_OP1_TEE2_ST field.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP1_TEE2_ST_Msk = 0x2
	// Bit MCPWM1_EVT_OP1_TEE2_ST.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP1_TEE2_ST = 0x2
	// Position of MCPWM1_EVT_OP2_TEE2_ST field.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP2_TEE2_ST_Pos = 0x2
	// Bit mask of MCPWM1_EVT_OP2_TEE2_ST field.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP2_TEE2_ST_Msk = 0x4
	// Bit MCPWM1_EVT_OP2_TEE2_ST.
	SOC_ETM_EVT_ST4_MCPWM1_EVT_OP2_TEE2_ST = 0x4
	// Position of ADC_EVT_CONV_CMPLT0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_CONV_CMPLT0_ST_Pos = 0x3
	// Bit mask of ADC_EVT_CONV_CMPLT0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_CONV_CMPLT0_ST_Msk = 0x8
	// Bit ADC_EVT_CONV_CMPLT0_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_CONV_CMPLT0_ST = 0x8
	// Position of ADC_EVT_EQ_ABOVE_THRESH0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_ABOVE_THRESH0_ST_Pos = 0x4
	// Bit mask of ADC_EVT_EQ_ABOVE_THRESH0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_ABOVE_THRESH0_ST_Msk = 0x10
	// Bit ADC_EVT_EQ_ABOVE_THRESH0_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_ABOVE_THRESH0_ST = 0x10
	// Position of ADC_EVT_EQ_ABOVE_THRESH1_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_ABOVE_THRESH1_ST_Pos = 0x5
	// Bit mask of ADC_EVT_EQ_ABOVE_THRESH1_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_ABOVE_THRESH1_ST_Msk = 0x20
	// Bit ADC_EVT_EQ_ABOVE_THRESH1_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_ABOVE_THRESH1_ST = 0x20
	// Position of ADC_EVT_EQ_BELOW_THRESH0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_BELOW_THRESH0_ST_Pos = 0x6
	// Bit mask of ADC_EVT_EQ_BELOW_THRESH0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_BELOW_THRESH0_ST_Msk = 0x40
	// Bit ADC_EVT_EQ_BELOW_THRESH0_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_BELOW_THRESH0_ST = 0x40
	// Position of ADC_EVT_EQ_BELOW_THRESH1_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_BELOW_THRESH1_ST_Pos = 0x7
	// Bit mask of ADC_EVT_EQ_BELOW_THRESH1_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_BELOW_THRESH1_ST_Msk = 0x80
	// Bit ADC_EVT_EQ_BELOW_THRESH1_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_EQ_BELOW_THRESH1_ST = 0x80
	// Position of ADC_EVT_RESULT_DONE0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_RESULT_DONE0_ST_Pos = 0x8
	// Bit mask of ADC_EVT_RESULT_DONE0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_RESULT_DONE0_ST_Msk = 0x100
	// Bit ADC_EVT_RESULT_DONE0_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_RESULT_DONE0_ST = 0x100
	// Position of ADC_EVT_STOPPED0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_STOPPED0_ST_Pos = 0x9
	// Bit mask of ADC_EVT_STOPPED0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_STOPPED0_ST_Msk = 0x200
	// Bit ADC_EVT_STOPPED0_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_STOPPED0_ST = 0x200
	// Position of ADC_EVT_STARTED0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_STARTED0_ST_Pos = 0xa
	// Bit mask of ADC_EVT_STARTED0_ST field.
	SOC_ETM_EVT_ST4_ADC_EVT_STARTED0_ST_Msk = 0x400
	// Bit ADC_EVT_STARTED0_ST.
	SOC_ETM_EVT_ST4_ADC_EVT_STARTED0_ST = 0x400
	// Position of REGDMA_EVT_DONE0_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE0_ST_Pos = 0xb
	// Bit mask of REGDMA_EVT_DONE0_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE0_ST_Msk = 0x800
	// Bit REGDMA_EVT_DONE0_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE0_ST = 0x800
	// Position of REGDMA_EVT_DONE1_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE1_ST_Pos = 0xc
	// Bit mask of REGDMA_EVT_DONE1_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE1_ST_Msk = 0x1000
	// Bit REGDMA_EVT_DONE1_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE1_ST = 0x1000
	// Position of REGDMA_EVT_DONE2_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE2_ST_Pos = 0xd
	// Bit mask of REGDMA_EVT_DONE2_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE2_ST_Msk = 0x2000
	// Bit REGDMA_EVT_DONE2_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE2_ST = 0x2000
	// Position of REGDMA_EVT_DONE3_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE3_ST_Pos = 0xe
	// Bit mask of REGDMA_EVT_DONE3_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE3_ST_Msk = 0x4000
	// Bit REGDMA_EVT_DONE3_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_DONE3_ST = 0x4000
	// Position of REGDMA_EVT_ERR0_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR0_ST_Pos = 0xf
	// Bit mask of REGDMA_EVT_ERR0_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR0_ST_Msk = 0x8000
	// Bit REGDMA_EVT_ERR0_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR0_ST = 0x8000
	// Position of REGDMA_EVT_ERR1_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR1_ST_Pos = 0x10
	// Bit mask of REGDMA_EVT_ERR1_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR1_ST_Msk = 0x10000
	// Bit REGDMA_EVT_ERR1_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR1_ST = 0x10000
	// Position of REGDMA_EVT_ERR2_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR2_ST_Pos = 0x11
	// Bit mask of REGDMA_EVT_ERR2_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR2_ST_Msk = 0x20000
	// Bit REGDMA_EVT_ERR2_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR2_ST = 0x20000
	// Position of REGDMA_EVT_ERR3_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR3_ST_Pos = 0x12
	// Bit mask of REGDMA_EVT_ERR3_ST field.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR3_ST_Msk = 0x40000
	// Bit REGDMA_EVT_ERR3_ST.
	SOC_ETM_EVT_ST4_REGDMA_EVT_ERR3_ST = 0x40000
	// Position of TMPSNSR_EVT_OVER_LIMIT_ST field.
	SOC_ETM_EVT_ST4_TMPSNSR_EVT_OVER_LIMIT_ST_Pos = 0x13
	// Bit mask of TMPSNSR_EVT_OVER_LIMIT_ST field.
	SOC_ETM_EVT_ST4_TMPSNSR_EVT_OVER_LIMIT_ST_Msk = 0x80000
	// Bit TMPSNSR_EVT_OVER_LIMIT_ST.
	SOC_ETM_EVT_ST4_TMPSNSR_EVT_OVER_LIMIT_ST = 0x80000
	// Position of I2S0_EVT_RX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_RX_DONE_ST_Pos = 0x14
	// Bit mask of I2S0_EVT_RX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_RX_DONE_ST_Msk = 0x100000
	// Bit I2S0_EVT_RX_DONE_ST.
	SOC_ETM_EVT_ST4_I2S0_EVT_RX_DONE_ST = 0x100000
	// Position of I2S0_EVT_TX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_TX_DONE_ST_Pos = 0x15
	// Bit mask of I2S0_EVT_TX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_TX_DONE_ST_Msk = 0x200000
	// Bit I2S0_EVT_TX_DONE_ST.
	SOC_ETM_EVT_ST4_I2S0_EVT_TX_DONE_ST = 0x200000
	// Position of I2S0_EVT_X_WORDS_RECEIVED_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_X_WORDS_RECEIVED_ST_Pos = 0x16
	// Bit mask of I2S0_EVT_X_WORDS_RECEIVED_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_X_WORDS_RECEIVED_ST_Msk = 0x400000
	// Bit I2S0_EVT_X_WORDS_RECEIVED_ST.
	SOC_ETM_EVT_ST4_I2S0_EVT_X_WORDS_RECEIVED_ST = 0x400000
	// Position of I2S0_EVT_X_WORDS_SENT_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_X_WORDS_SENT_ST_Pos = 0x17
	// Bit mask of I2S0_EVT_X_WORDS_SENT_ST field.
	SOC_ETM_EVT_ST4_I2S0_EVT_X_WORDS_SENT_ST_Msk = 0x800000
	// Bit I2S0_EVT_X_WORDS_SENT_ST.
	SOC_ETM_EVT_ST4_I2S0_EVT_X_WORDS_SENT_ST = 0x800000
	// Position of I2S1_EVT_RX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_RX_DONE_ST_Pos = 0x18
	// Bit mask of I2S1_EVT_RX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_RX_DONE_ST_Msk = 0x1000000
	// Bit I2S1_EVT_RX_DONE_ST.
	SOC_ETM_EVT_ST4_I2S1_EVT_RX_DONE_ST = 0x1000000
	// Position of I2S1_EVT_TX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_TX_DONE_ST_Pos = 0x19
	// Bit mask of I2S1_EVT_TX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_TX_DONE_ST_Msk = 0x2000000
	// Bit I2S1_EVT_TX_DONE_ST.
	SOC_ETM_EVT_ST4_I2S1_EVT_TX_DONE_ST = 0x2000000
	// Position of I2S1_EVT_X_WORDS_RECEIVED_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_X_WORDS_RECEIVED_ST_Pos = 0x1a
	// Bit mask of I2S1_EVT_X_WORDS_RECEIVED_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_X_WORDS_RECEIVED_ST_Msk = 0x4000000
	// Bit I2S1_EVT_X_WORDS_RECEIVED_ST.
	SOC_ETM_EVT_ST4_I2S1_EVT_X_WORDS_RECEIVED_ST = 0x4000000
	// Position of I2S1_EVT_X_WORDS_SENT_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_X_WORDS_SENT_ST_Pos = 0x1b
	// Bit mask of I2S1_EVT_X_WORDS_SENT_ST field.
	SOC_ETM_EVT_ST4_I2S1_EVT_X_WORDS_SENT_ST_Msk = 0x8000000
	// Bit I2S1_EVT_X_WORDS_SENT_ST.
	SOC_ETM_EVT_ST4_I2S1_EVT_X_WORDS_SENT_ST = 0x8000000
	// Position of I2S2_EVT_RX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_RX_DONE_ST_Pos = 0x1c
	// Bit mask of I2S2_EVT_RX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_RX_DONE_ST_Msk = 0x10000000
	// Bit I2S2_EVT_RX_DONE_ST.
	SOC_ETM_EVT_ST4_I2S2_EVT_RX_DONE_ST = 0x10000000
	// Position of I2S2_EVT_TX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_TX_DONE_ST_Pos = 0x1d
	// Bit mask of I2S2_EVT_TX_DONE_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_TX_DONE_ST_Msk = 0x20000000
	// Bit I2S2_EVT_TX_DONE_ST.
	SOC_ETM_EVT_ST4_I2S2_EVT_TX_DONE_ST = 0x20000000
	// Position of I2S2_EVT_X_WORDS_RECEIVED_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_X_WORDS_RECEIVED_ST_Pos = 0x1e
	// Bit mask of I2S2_EVT_X_WORDS_RECEIVED_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_X_WORDS_RECEIVED_ST_Msk = 0x40000000
	// Bit I2S2_EVT_X_WORDS_RECEIVED_ST.
	SOC_ETM_EVT_ST4_I2S2_EVT_X_WORDS_RECEIVED_ST = 0x40000000
	// Position of I2S2_EVT_X_WORDS_SENT_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_X_WORDS_SENT_ST_Pos = 0x1f
	// Bit mask of I2S2_EVT_X_WORDS_SENT_ST field.
	SOC_ETM_EVT_ST4_I2S2_EVT_X_WORDS_SENT_ST_Msk = 0x80000000
	// Bit I2S2_EVT_X_WORDS_SENT_ST.
	SOC_ETM_EVT_ST4_I2S2_EVT_X_WORDS_SENT_ST = 0x80000000

	// EVT_ST4_CLR: Events trigger status clear register
	// Position of MCPWM1_EVT_OP0_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP0_TEE2_ST_CLR_Pos = 0x0
	// Bit mask of MCPWM1_EVT_OP0_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP0_TEE2_ST_CLR_Msk = 0x1
	// Bit MCPWM1_EVT_OP0_TEE2_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP0_TEE2_ST_CLR = 0x1
	// Position of MCPWM1_EVT_OP1_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP1_TEE2_ST_CLR_Pos = 0x1
	// Bit mask of MCPWM1_EVT_OP1_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP1_TEE2_ST_CLR_Msk = 0x2
	// Bit MCPWM1_EVT_OP1_TEE2_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP1_TEE2_ST_CLR = 0x2
	// Position of MCPWM1_EVT_OP2_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP2_TEE2_ST_CLR_Pos = 0x2
	// Bit mask of MCPWM1_EVT_OP2_TEE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP2_TEE2_ST_CLR_Msk = 0x4
	// Bit MCPWM1_EVT_OP2_TEE2_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_MCPWM1_EVT_OP2_TEE2_ST_CLR = 0x4
	// Position of ADC_EVT_CONV_CMPLT0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_CONV_CMPLT0_ST_CLR_Pos = 0x3
	// Bit mask of ADC_EVT_CONV_CMPLT0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_CONV_CMPLT0_ST_CLR_Msk = 0x8
	// Bit ADC_EVT_CONV_CMPLT0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_CONV_CMPLT0_ST_CLR = 0x8
	// Position of ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_Pos = 0x4
	// Bit mask of ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_Msk = 0x10
	// Bit ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR = 0x10
	// Position of ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_Pos = 0x5
	// Bit mask of ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_Msk = 0x20
	// Bit ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR = 0x20
	// Position of ADC_EVT_EQ_BELOW_THRESH0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_Pos = 0x6
	// Bit mask of ADC_EVT_EQ_BELOW_THRESH0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_Msk = 0x40
	// Bit ADC_EVT_EQ_BELOW_THRESH0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR = 0x40
	// Position of ADC_EVT_EQ_BELOW_THRESH1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_Pos = 0x7
	// Bit mask of ADC_EVT_EQ_BELOW_THRESH1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_Msk = 0x80
	// Bit ADC_EVT_EQ_BELOW_THRESH1_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR = 0x80
	// Position of ADC_EVT_RESULT_DONE0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_RESULT_DONE0_ST_CLR_Pos = 0x8
	// Bit mask of ADC_EVT_RESULT_DONE0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_RESULT_DONE0_ST_CLR_Msk = 0x100
	// Bit ADC_EVT_RESULT_DONE0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_RESULT_DONE0_ST_CLR = 0x100
	// Position of ADC_EVT_STOPPED0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_STOPPED0_ST_CLR_Pos = 0x9
	// Bit mask of ADC_EVT_STOPPED0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_STOPPED0_ST_CLR_Msk = 0x200
	// Bit ADC_EVT_STOPPED0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_STOPPED0_ST_CLR = 0x200
	// Position of ADC_EVT_STARTED0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_STARTED0_ST_CLR_Pos = 0xa
	// Bit mask of ADC_EVT_STARTED0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_STARTED0_ST_CLR_Msk = 0x400
	// Bit ADC_EVT_STARTED0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_ADC_EVT_STARTED0_ST_CLR = 0x400
	// Position of REGDMA_EVT_DONE0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE0_ST_CLR_Pos = 0xb
	// Bit mask of REGDMA_EVT_DONE0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE0_ST_CLR_Msk = 0x800
	// Bit REGDMA_EVT_DONE0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE0_ST_CLR = 0x800
	// Position of REGDMA_EVT_DONE1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE1_ST_CLR_Pos = 0xc
	// Bit mask of REGDMA_EVT_DONE1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE1_ST_CLR_Msk = 0x1000
	// Bit REGDMA_EVT_DONE1_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE1_ST_CLR = 0x1000
	// Position of REGDMA_EVT_DONE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE2_ST_CLR_Pos = 0xd
	// Bit mask of REGDMA_EVT_DONE2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE2_ST_CLR_Msk = 0x2000
	// Bit REGDMA_EVT_DONE2_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE2_ST_CLR = 0x2000
	// Position of REGDMA_EVT_DONE3_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE3_ST_CLR_Pos = 0xe
	// Bit mask of REGDMA_EVT_DONE3_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE3_ST_CLR_Msk = 0x4000
	// Bit REGDMA_EVT_DONE3_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_DONE3_ST_CLR = 0x4000
	// Position of REGDMA_EVT_ERR0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR0_ST_CLR_Pos = 0xf
	// Bit mask of REGDMA_EVT_ERR0_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR0_ST_CLR_Msk = 0x8000
	// Bit REGDMA_EVT_ERR0_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR0_ST_CLR = 0x8000
	// Position of REGDMA_EVT_ERR1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR1_ST_CLR_Pos = 0x10
	// Bit mask of REGDMA_EVT_ERR1_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR1_ST_CLR_Msk = 0x10000
	// Bit REGDMA_EVT_ERR1_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR1_ST_CLR = 0x10000
	// Position of REGDMA_EVT_ERR2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR2_ST_CLR_Pos = 0x11
	// Bit mask of REGDMA_EVT_ERR2_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR2_ST_CLR_Msk = 0x20000
	// Bit REGDMA_EVT_ERR2_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR2_ST_CLR = 0x20000
	// Position of REGDMA_EVT_ERR3_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR3_ST_CLR_Pos = 0x12
	// Bit mask of REGDMA_EVT_ERR3_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR3_ST_CLR_Msk = 0x40000
	// Bit REGDMA_EVT_ERR3_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_REGDMA_EVT_ERR3_ST_CLR = 0x40000
	// Position of TMPSNSR_EVT_OVER_LIMIT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_Pos = 0x13
	// Bit mask of TMPSNSR_EVT_OVER_LIMIT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_Msk = 0x80000
	// Bit TMPSNSR_EVT_OVER_LIMIT_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_TMPSNSR_EVT_OVER_LIMIT_ST_CLR = 0x80000
	// Position of I2S0_EVT_RX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_RX_DONE_ST_CLR_Pos = 0x14
	// Bit mask of I2S0_EVT_RX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_RX_DONE_ST_CLR_Msk = 0x100000
	// Bit I2S0_EVT_RX_DONE_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_RX_DONE_ST_CLR = 0x100000
	// Position of I2S0_EVT_TX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_TX_DONE_ST_CLR_Pos = 0x15
	// Bit mask of I2S0_EVT_TX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_TX_DONE_ST_CLR_Msk = 0x200000
	// Bit I2S0_EVT_TX_DONE_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_TX_DONE_ST_CLR = 0x200000
	// Position of I2S0_EVT_X_WORDS_RECEIVED_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_Pos = 0x16
	// Bit mask of I2S0_EVT_X_WORDS_RECEIVED_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_Msk = 0x400000
	// Bit I2S0_EVT_X_WORDS_RECEIVED_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR = 0x400000
	// Position of I2S0_EVT_X_WORDS_SENT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_X_WORDS_SENT_ST_CLR_Pos = 0x17
	// Bit mask of I2S0_EVT_X_WORDS_SENT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_X_WORDS_SENT_ST_CLR_Msk = 0x800000
	// Bit I2S0_EVT_X_WORDS_SENT_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S0_EVT_X_WORDS_SENT_ST_CLR = 0x800000
	// Position of I2S1_EVT_RX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_RX_DONE_ST_CLR_Pos = 0x18
	// Bit mask of I2S1_EVT_RX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_RX_DONE_ST_CLR_Msk = 0x1000000
	// Bit I2S1_EVT_RX_DONE_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_RX_DONE_ST_CLR = 0x1000000
	// Position of I2S1_EVT_TX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_TX_DONE_ST_CLR_Pos = 0x19
	// Bit mask of I2S1_EVT_TX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_TX_DONE_ST_CLR_Msk = 0x2000000
	// Bit I2S1_EVT_TX_DONE_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_TX_DONE_ST_CLR = 0x2000000
	// Position of I2S1_EVT_X_WORDS_RECEIVED_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_Pos = 0x1a
	// Bit mask of I2S1_EVT_X_WORDS_RECEIVED_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_Msk = 0x4000000
	// Bit I2S1_EVT_X_WORDS_RECEIVED_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR = 0x4000000
	// Position of I2S1_EVT_X_WORDS_SENT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_X_WORDS_SENT_ST_CLR_Pos = 0x1b
	// Bit mask of I2S1_EVT_X_WORDS_SENT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_X_WORDS_SENT_ST_CLR_Msk = 0x8000000
	// Bit I2S1_EVT_X_WORDS_SENT_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S1_EVT_X_WORDS_SENT_ST_CLR = 0x8000000
	// Position of I2S2_EVT_RX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_RX_DONE_ST_CLR_Pos = 0x1c
	// Bit mask of I2S2_EVT_RX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_RX_DONE_ST_CLR_Msk = 0x10000000
	// Bit I2S2_EVT_RX_DONE_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_RX_DONE_ST_CLR = 0x10000000
	// Position of I2S2_EVT_TX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_TX_DONE_ST_CLR_Pos = 0x1d
	// Bit mask of I2S2_EVT_TX_DONE_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_TX_DONE_ST_CLR_Msk = 0x20000000
	// Bit I2S2_EVT_TX_DONE_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_TX_DONE_ST_CLR = 0x20000000
	// Position of I2S2_EVT_X_WORDS_RECEIVED_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_Pos = 0x1e
	// Bit mask of I2S2_EVT_X_WORDS_RECEIVED_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_Msk = 0x40000000
	// Bit I2S2_EVT_X_WORDS_RECEIVED_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_X_WORDS_RECEIVED_ST_CLR = 0x40000000
	// Position of I2S2_EVT_X_WORDS_SENT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_X_WORDS_SENT_ST_CLR_Pos = 0x1f
	// Bit mask of I2S2_EVT_X_WORDS_SENT_ST_CLR field.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_X_WORDS_SENT_ST_CLR_Msk = 0x80000000
	// Bit I2S2_EVT_X_WORDS_SENT_ST_CLR.
	SOC_ETM_EVT_ST4_CLR_I2S2_EVT_X_WORDS_SENT_ST_CLR = 0x80000000

	// EVT_ST5: Events trigger status register
	// Position of ULP_EVT_ERR_INTR_ST field.
	SOC_ETM_EVT_ST5_ULP_EVT_ERR_INTR_ST_Pos = 0x0
	// Bit mask of ULP_EVT_ERR_INTR_ST field.
	SOC_ETM_EVT_ST5_ULP_EVT_ERR_INTR_ST_Msk = 0x1
	// Bit ULP_EVT_ERR_INTR_ST.
	SOC_ETM_EVT_ST5_ULP_EVT_ERR_INTR_ST = 0x1
	// Position of ULP_EVT_HALT_ST field.
	SOC_ETM_EVT_ST5_ULP_EVT_HALT_ST_Pos = 0x1
	// Bit mask of ULP_EVT_HALT_ST field.
	SOC_ETM_EVT_ST5_ULP_EVT_HALT_ST_Msk = 0x2
	// Bit ULP_EVT_HALT_ST.
	SOC_ETM_EVT_ST5_ULP_EVT_HALT_ST = 0x2
	// Position of ULP_EVT_START_INTR_ST field.
	SOC_ETM_EVT_ST5_ULP_EVT_START_INTR_ST_Pos = 0x2
	// Bit mask of ULP_EVT_START_INTR_ST field.
	SOC_ETM_EVT_ST5_ULP_EVT_START_INTR_ST_Msk = 0x4
	// Bit ULP_EVT_START_INTR_ST.
	SOC_ETM_EVT_ST5_ULP_EVT_START_INTR_ST = 0x4
	// Position of RTC_EVT_TICK_ST field.
	SOC_ETM_EVT_ST5_RTC_EVT_TICK_ST_Pos = 0x3
	// Bit mask of RTC_EVT_TICK_ST field.
	SOC_ETM_EVT_ST5_RTC_EVT_TICK_ST_Msk = 0x8
	// Bit RTC_EVT_TICK_ST.
	SOC_ETM_EVT_ST5_RTC_EVT_TICK_ST = 0x8
	// Position of RTC_EVT_OVF_ST field.
	SOC_ETM_EVT_ST5_RTC_EVT_OVF_ST_Pos = 0x4
	// Bit mask of RTC_EVT_OVF_ST field.
	SOC_ETM_EVT_ST5_RTC_EVT_OVF_ST_Msk = 0x10
	// Bit RTC_EVT_OVF_ST.
	SOC_ETM_EVT_ST5_RTC_EVT_OVF_ST = 0x10
	// Position of RTC_EVT_CMP_ST field.
	SOC_ETM_EVT_ST5_RTC_EVT_CMP_ST_Pos = 0x5
	// Bit mask of RTC_EVT_CMP_ST field.
	SOC_ETM_EVT_ST5_RTC_EVT_CMP_ST_Msk = 0x20
	// Bit RTC_EVT_CMP_ST.
	SOC_ETM_EVT_ST5_RTC_EVT_CMP_ST = 0x20
	// Position of PDMA_AHB_EVT_IN_DONE_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH0_ST_Pos = 0x6
	// Bit mask of PDMA_AHB_EVT_IN_DONE_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH0_ST_Msk = 0x40
	// Bit PDMA_AHB_EVT_IN_DONE_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH0_ST = 0x40
	// Position of PDMA_AHB_EVT_IN_DONE_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH1_ST_Pos = 0x7
	// Bit mask of PDMA_AHB_EVT_IN_DONE_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH1_ST_Msk = 0x80
	// Bit PDMA_AHB_EVT_IN_DONE_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH1_ST = 0x80
	// Position of PDMA_AHB_EVT_IN_DONE_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH2_ST_Pos = 0x8
	// Bit mask of PDMA_AHB_EVT_IN_DONE_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH2_ST_Msk = 0x100
	// Bit PDMA_AHB_EVT_IN_DONE_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_DONE_CH2_ST = 0x100
	// Position of PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_Pos = 0x9
	// Bit mask of PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_Msk = 0x200
	// Bit PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST = 0x200
	// Position of PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_Pos = 0xa
	// Bit mask of PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_Msk = 0x400
	// Bit PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST = 0x400
	// Position of PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_Pos = 0xb
	// Bit mask of PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_Msk = 0x800
	// Bit PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST = 0x800
	// Position of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_Pos = 0xc
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_Msk = 0x1000
	// Bit PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST = 0x1000
	// Position of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_Pos = 0xd
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_Msk = 0x2000
	// Bit PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST = 0x2000
	// Position of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_Pos = 0xe
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_Msk = 0x4000
	// Bit PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST = 0x4000
	// Position of PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_Pos = 0xf
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_Msk = 0x8000
	// Bit PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST = 0x8000
	// Position of PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_Pos = 0x10
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_Msk = 0x10000
	// Bit PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST = 0x10000
	// Position of PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_Pos = 0x11
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_Msk = 0x20000
	// Bit PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST = 0x20000
	// Position of PDMA_AHB_EVT_OUT_DONE_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH0_ST_Pos = 0x12
	// Bit mask of PDMA_AHB_EVT_OUT_DONE_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH0_ST_Msk = 0x40000
	// Bit PDMA_AHB_EVT_OUT_DONE_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH0_ST = 0x40000
	// Position of PDMA_AHB_EVT_OUT_DONE_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH1_ST_Pos = 0x13
	// Bit mask of PDMA_AHB_EVT_OUT_DONE_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH1_ST_Msk = 0x80000
	// Bit PDMA_AHB_EVT_OUT_DONE_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH1_ST = 0x80000
	// Position of PDMA_AHB_EVT_OUT_DONE_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH2_ST_Pos = 0x14
	// Bit mask of PDMA_AHB_EVT_OUT_DONE_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH2_ST_Msk = 0x100000
	// Bit PDMA_AHB_EVT_OUT_DONE_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_DONE_CH2_ST = 0x100000
	// Position of PDMA_AHB_EVT_OUT_EOF_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH0_ST_Pos = 0x15
	// Bit mask of PDMA_AHB_EVT_OUT_EOF_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH0_ST_Msk = 0x200000
	// Bit PDMA_AHB_EVT_OUT_EOF_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH0_ST = 0x200000
	// Position of PDMA_AHB_EVT_OUT_EOF_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH1_ST_Pos = 0x16
	// Bit mask of PDMA_AHB_EVT_OUT_EOF_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH1_ST_Msk = 0x400000
	// Bit PDMA_AHB_EVT_OUT_EOF_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH1_ST = 0x400000
	// Position of PDMA_AHB_EVT_OUT_EOF_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH2_ST_Pos = 0x17
	// Bit mask of PDMA_AHB_EVT_OUT_EOF_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH2_ST_Msk = 0x800000
	// Bit PDMA_AHB_EVT_OUT_EOF_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_EOF_CH2_ST = 0x800000
	// Position of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_Pos = 0x18
	// Bit mask of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_Msk = 0x1000000
	// Bit PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST = 0x1000000
	// Position of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_Pos = 0x19
	// Bit mask of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_Msk = 0x2000000
	// Bit PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST = 0x2000000
	// Position of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_Pos = 0x1a
	// Bit mask of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_Msk = 0x4000000
	// Bit PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST = 0x4000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_Pos = 0x1b
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_Msk = 0x8000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST = 0x8000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_Pos = 0x1c
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_Msk = 0x10000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST = 0x10000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_Pos = 0x1d
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_Msk = 0x20000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST = 0x20000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_Pos = 0x1e
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_Msk = 0x40000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST = 0x40000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_Pos = 0x1f
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_Msk = 0x80000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST.
	SOC_ETM_EVT_ST5_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST = 0x80000000

	// EVT_ST5_CLR: Events trigger status clear register
	// Position of ULP_EVT_ERR_INTR_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_ERR_INTR_ST_CLR_Pos = 0x0
	// Bit mask of ULP_EVT_ERR_INTR_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_ERR_INTR_ST_CLR_Msk = 0x1
	// Bit ULP_EVT_ERR_INTR_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_ERR_INTR_ST_CLR = 0x1
	// Position of ULP_EVT_HALT_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_HALT_ST_CLR_Pos = 0x1
	// Bit mask of ULP_EVT_HALT_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_HALT_ST_CLR_Msk = 0x2
	// Bit ULP_EVT_HALT_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_HALT_ST_CLR = 0x2
	// Position of ULP_EVT_START_INTR_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_START_INTR_ST_CLR_Pos = 0x2
	// Bit mask of ULP_EVT_START_INTR_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_START_INTR_ST_CLR_Msk = 0x4
	// Bit ULP_EVT_START_INTR_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_ULP_EVT_START_INTR_ST_CLR = 0x4
	// Position of RTC_EVT_TICK_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_TICK_ST_CLR_Pos = 0x3
	// Bit mask of RTC_EVT_TICK_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_TICK_ST_CLR_Msk = 0x8
	// Bit RTC_EVT_TICK_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_TICK_ST_CLR = 0x8
	// Position of RTC_EVT_OVF_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_OVF_ST_CLR_Pos = 0x4
	// Bit mask of RTC_EVT_OVF_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_OVF_ST_CLR_Msk = 0x10
	// Bit RTC_EVT_OVF_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_OVF_ST_CLR = 0x10
	// Position of RTC_EVT_CMP_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_CMP_ST_CLR_Pos = 0x5
	// Bit mask of RTC_EVT_CMP_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_CMP_ST_CLR_Msk = 0x20
	// Bit RTC_EVT_CMP_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_RTC_EVT_CMP_ST_CLR = 0x20
	// Position of PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_Pos = 0x6
	// Bit mask of PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_Msk = 0x40
	// Bit PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR = 0x40
	// Position of PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_Pos = 0x7
	// Bit mask of PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_Msk = 0x80
	// Bit PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR = 0x80
	// Position of PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_Pos = 0x8
	// Bit mask of PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_Msk = 0x100
	// Bit PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR = 0x100
	// Position of PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_Pos = 0x9
	// Bit mask of PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_Msk = 0x200
	// Bit PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR = 0x200
	// Position of PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_Pos = 0xa
	// Bit mask of PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_Msk = 0x400
	// Bit PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR = 0x400
	// Position of PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_Pos = 0xb
	// Bit mask of PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_Msk = 0x800
	// Bit PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR = 0x800
	// Position of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_Pos = 0xc
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_Msk = 0x1000
	// Bit PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR = 0x1000
	// Position of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_Pos = 0xd
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_Msk = 0x2000
	// Bit PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR = 0x2000
	// Position of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_Pos = 0xe
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_Msk = 0x4000
	// Bit PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR = 0x4000
	// Position of PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_Pos = 0xf
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_Msk = 0x8000
	// Bit PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR = 0x8000
	// Position of PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_Pos = 0x10
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_Msk = 0x10000
	// Bit PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR = 0x10000
	// Position of PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_Pos = 0x11
	// Bit mask of PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_Msk = 0x20000
	// Bit PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR = 0x20000
	// Position of PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_Pos = 0x12
	// Bit mask of PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_Msk = 0x40000
	// Bit PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR = 0x40000
	// Position of PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_Pos = 0x13
	// Bit mask of PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_Msk = 0x80000
	// Bit PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR = 0x80000
	// Position of PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_Pos = 0x14
	// Bit mask of PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_Msk = 0x100000
	// Bit PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR = 0x100000
	// Position of PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_Pos = 0x15
	// Bit mask of PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_Msk = 0x200000
	// Bit PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR = 0x200000
	// Position of PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_Pos = 0x16
	// Bit mask of PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_Msk = 0x400000
	// Bit PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR = 0x400000
	// Position of PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_Pos = 0x17
	// Bit mask of PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_Msk = 0x800000
	// Bit PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR = 0x800000
	// Position of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_Pos = 0x18
	// Bit mask of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_Msk = 0x1000000
	// Bit PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR = 0x1000000
	// Position of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_Pos = 0x19
	// Bit mask of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_Msk = 0x2000000
	// Bit PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR = 0x2000000
	// Position of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_Pos = 0x1a
	// Bit mask of PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_Msk = 0x4000000
	// Bit PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR = 0x4000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_Pos = 0x1b
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_Msk = 0x8000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR = 0x8000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_Pos = 0x1c
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_Msk = 0x10000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR = 0x10000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_Pos = 0x1d
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_Msk = 0x20000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR = 0x20000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_Pos = 0x1e
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_Msk = 0x40000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR = 0x40000000
	// Position of PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_Pos = 0x1f
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_Msk = 0x80000000
	// Bit PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR.
	SOC_ETM_EVT_ST5_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR = 0x80000000

	// EVT_ST6: Events trigger status register
	// Position of PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_Pos = 0x0
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_Msk = 0x1
	// Bit PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST = 0x1
	// Position of PDMA_AXI_EVT_IN_DONE_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH0_ST_Pos = 0x1
	// Bit mask of PDMA_AXI_EVT_IN_DONE_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH0_ST_Msk = 0x2
	// Bit PDMA_AXI_EVT_IN_DONE_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH0_ST = 0x2
	// Position of PDMA_AXI_EVT_IN_DONE_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH1_ST_Pos = 0x2
	// Bit mask of PDMA_AXI_EVT_IN_DONE_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH1_ST_Msk = 0x4
	// Bit PDMA_AXI_EVT_IN_DONE_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH1_ST = 0x4
	// Position of PDMA_AXI_EVT_IN_DONE_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH2_ST_Pos = 0x3
	// Bit mask of PDMA_AXI_EVT_IN_DONE_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH2_ST_Msk = 0x8
	// Bit PDMA_AXI_EVT_IN_DONE_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_DONE_CH2_ST = 0x8
	// Position of PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_Pos = 0x4
	// Bit mask of PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_Msk = 0x10
	// Bit PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST = 0x10
	// Position of PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_Pos = 0x5
	// Bit mask of PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_Msk = 0x20
	// Bit PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST = 0x20
	// Position of PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_Pos = 0x6
	// Bit mask of PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_Msk = 0x40
	// Bit PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST = 0x40
	// Position of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_Pos = 0x7
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_Msk = 0x80
	// Bit PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST = 0x80
	// Position of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_Pos = 0x8
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_Msk = 0x100
	// Bit PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST = 0x100
	// Position of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_Pos = 0x9
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_Msk = 0x200
	// Bit PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST = 0x200
	// Position of PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_Pos = 0xa
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_Msk = 0x400
	// Bit PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST = 0x400
	// Position of PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_Pos = 0xb
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_Msk = 0x800
	// Bit PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST = 0x800
	// Position of PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_Pos = 0xc
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_Msk = 0x1000
	// Bit PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST = 0x1000
	// Position of PDMA_AXI_EVT_OUT_DONE_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH0_ST_Pos = 0xd
	// Bit mask of PDMA_AXI_EVT_OUT_DONE_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH0_ST_Msk = 0x2000
	// Bit PDMA_AXI_EVT_OUT_DONE_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH0_ST = 0x2000
	// Position of PDMA_AXI_EVT_OUT_DONE_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH1_ST_Pos = 0xe
	// Bit mask of PDMA_AXI_EVT_OUT_DONE_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH1_ST_Msk = 0x4000
	// Bit PDMA_AXI_EVT_OUT_DONE_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH1_ST = 0x4000
	// Position of PDMA_AXI_EVT_OUT_DONE_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH2_ST_Pos = 0xf
	// Bit mask of PDMA_AXI_EVT_OUT_DONE_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH2_ST_Msk = 0x8000
	// Bit PDMA_AXI_EVT_OUT_DONE_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_DONE_CH2_ST = 0x8000
	// Position of PDMA_AXI_EVT_OUT_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH0_ST_Pos = 0x10
	// Bit mask of PDMA_AXI_EVT_OUT_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH0_ST_Msk = 0x10000
	// Bit PDMA_AXI_EVT_OUT_EOF_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH0_ST = 0x10000
	// Position of PDMA_AXI_EVT_OUT_EOF_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH1_ST_Pos = 0x11
	// Bit mask of PDMA_AXI_EVT_OUT_EOF_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH1_ST_Msk = 0x20000
	// Bit PDMA_AXI_EVT_OUT_EOF_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH1_ST = 0x20000
	// Position of PDMA_AXI_EVT_OUT_EOF_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH2_ST_Pos = 0x12
	// Bit mask of PDMA_AXI_EVT_OUT_EOF_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH2_ST_Msk = 0x40000
	// Bit PDMA_AXI_EVT_OUT_EOF_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_EOF_CH2_ST = 0x40000
	// Position of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_Pos = 0x13
	// Bit mask of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_Msk = 0x80000
	// Bit PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST = 0x80000
	// Position of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_Pos = 0x14
	// Bit mask of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_Msk = 0x100000
	// Bit PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST = 0x100000
	// Position of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_Pos = 0x15
	// Bit mask of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_Msk = 0x200000
	// Bit PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST = 0x200000
	// Position of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_Pos = 0x16
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_Msk = 0x400000
	// Bit PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST = 0x400000
	// Position of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_Pos = 0x17
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_Msk = 0x800000
	// Bit PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST = 0x800000
	// Position of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_Pos = 0x18
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_Msk = 0x1000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST = 0x1000000
	// Position of PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_Pos = 0x19
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_Msk = 0x2000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST = 0x2000000
	// Position of PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_Pos = 0x1a
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_Msk = 0x4000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST = 0x4000000
	// Position of PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_Pos = 0x1b
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST field.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_Msk = 0x8000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST.
	SOC_ETM_EVT_ST6_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST = 0x8000000
	// Position of PMU_EVT_SLEEP_WEEKUP_ST field.
	SOC_ETM_EVT_ST6_PMU_EVT_SLEEP_WEEKUP_ST_Pos = 0x1c
	// Bit mask of PMU_EVT_SLEEP_WEEKUP_ST field.
	SOC_ETM_EVT_ST6_PMU_EVT_SLEEP_WEEKUP_ST_Msk = 0x10000000
	// Bit PMU_EVT_SLEEP_WEEKUP_ST.
	SOC_ETM_EVT_ST6_PMU_EVT_SLEEP_WEEKUP_ST = 0x10000000
	// Position of DMA2D_EVT_IN_DONE_CH0_ST field.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_DONE_CH0_ST_Pos = 0x1d
	// Bit mask of DMA2D_EVT_IN_DONE_CH0_ST field.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_DONE_CH0_ST_Msk = 0x20000000
	// Bit DMA2D_EVT_IN_DONE_CH0_ST.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_DONE_CH0_ST = 0x20000000
	// Position of DMA2D_EVT_IN_DONE_CH1_ST field.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_DONE_CH1_ST_Pos = 0x1e
	// Bit mask of DMA2D_EVT_IN_DONE_CH1_ST field.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_DONE_CH1_ST_Msk = 0x40000000
	// Bit DMA2D_EVT_IN_DONE_CH1_ST.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_DONE_CH1_ST = 0x40000000
	// Position of DMA2D_EVT_IN_SUC_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_SUC_EOF_CH0_ST_Pos = 0x1f
	// Bit mask of DMA2D_EVT_IN_SUC_EOF_CH0_ST field.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_SUC_EOF_CH0_ST_Msk = 0x80000000
	// Bit DMA2D_EVT_IN_SUC_EOF_CH0_ST.
	SOC_ETM_EVT_ST6_DMA2D_EVT_IN_SUC_EOF_CH0_ST = 0x80000000

	// EVT_ST6_CLR: Events trigger status clear register
	// Position of PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_Pos = 0x0
	// Bit mask of PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_Msk = 0x1
	// Bit PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR = 0x1
	// Position of PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_Pos = 0x1
	// Bit mask of PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_Msk = 0x2
	// Bit PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR = 0x2
	// Position of PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_Pos = 0x2
	// Bit mask of PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_Msk = 0x4
	// Bit PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR = 0x4
	// Position of PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_Pos = 0x3
	// Bit mask of PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_Msk = 0x8
	// Bit PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR = 0x8
	// Position of PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_Pos = 0x4
	// Bit mask of PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_Msk = 0x10
	// Bit PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR = 0x10
	// Position of PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_Pos = 0x5
	// Bit mask of PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_Msk = 0x20
	// Bit PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR = 0x20
	// Position of PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_Pos = 0x6
	// Bit mask of PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_Msk = 0x40
	// Bit PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR = 0x40
	// Position of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_Pos = 0x7
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_Msk = 0x80
	// Bit PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR = 0x80
	// Position of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_Pos = 0x8
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_Msk = 0x100
	// Bit PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR = 0x100
	// Position of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_Pos = 0x9
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_Msk = 0x200
	// Bit PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR = 0x200
	// Position of PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_Pos = 0xa
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_Msk = 0x400
	// Bit PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR = 0x400
	// Position of PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_Pos = 0xb
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_Msk = 0x800
	// Bit PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR = 0x800
	// Position of PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_Pos = 0xc
	// Bit mask of PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_Msk = 0x1000
	// Bit PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR = 0x1000
	// Position of PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_Pos = 0xd
	// Bit mask of PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_Msk = 0x2000
	// Bit PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR = 0x2000
	// Position of PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_Pos = 0xe
	// Bit mask of PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_Msk = 0x4000
	// Bit PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR = 0x4000
	// Position of PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_Pos = 0xf
	// Bit mask of PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_Msk = 0x8000
	// Bit PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR = 0x8000
	// Position of PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_Pos = 0x10
	// Bit mask of PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_Msk = 0x10000
	// Bit PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR = 0x10000
	// Position of PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_Pos = 0x11
	// Bit mask of PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_Msk = 0x20000
	// Bit PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR = 0x20000
	// Position of PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_Pos = 0x12
	// Bit mask of PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_Msk = 0x40000
	// Bit PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR = 0x40000
	// Position of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_Pos = 0x13
	// Bit mask of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_Msk = 0x80000
	// Bit PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR = 0x80000
	// Position of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_Pos = 0x14
	// Bit mask of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_Msk = 0x100000
	// Bit PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR = 0x100000
	// Position of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_Pos = 0x15
	// Bit mask of PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_Msk = 0x200000
	// Bit PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR = 0x200000
	// Position of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_Pos = 0x16
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_Msk = 0x400000
	// Bit PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR = 0x400000
	// Position of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_Pos = 0x17
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_Msk = 0x800000
	// Bit PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR = 0x800000
	// Position of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_Pos = 0x18
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_Msk = 0x1000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR = 0x1000000
	// Position of PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_Pos = 0x19
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_Msk = 0x2000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR = 0x2000000
	// Position of PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_Pos = 0x1a
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_Msk = 0x4000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR = 0x4000000
	// Position of PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_Pos = 0x1b
	// Bit mask of PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_Msk = 0x8000000
	// Bit PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR = 0x8000000
	// Position of PMU_EVT_SLEEP_WEEKUP_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PMU_EVT_SLEEP_WEEKUP_ST_CLR_Pos = 0x1c
	// Bit mask of PMU_EVT_SLEEP_WEEKUP_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_PMU_EVT_SLEEP_WEEKUP_ST_CLR_Msk = 0x10000000
	// Bit PMU_EVT_SLEEP_WEEKUP_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_PMU_EVT_SLEEP_WEEKUP_ST_CLR = 0x10000000
	// Position of DMA2D_EVT_IN_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH0_ST_CLR_Pos = 0x1d
	// Bit mask of DMA2D_EVT_IN_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH0_ST_CLR_Msk = 0x20000000
	// Bit DMA2D_EVT_IN_DONE_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH0_ST_CLR = 0x20000000
	// Position of DMA2D_EVT_IN_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH1_ST_CLR_Pos = 0x1e
	// Bit mask of DMA2D_EVT_IN_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH1_ST_CLR_Msk = 0x40000000
	// Bit DMA2D_EVT_IN_DONE_CH1_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_DONE_CH1_ST_CLR = 0x40000000
	// Position of DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_Pos = 0x1f
	// Bit mask of DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_Msk = 0x80000000
	// Bit DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST6_CLR_DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR = 0x80000000

	// EVT_ST7: Events trigger status register
	// Position of DMA2D_EVT_IN_SUC_EOF_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_IN_SUC_EOF_CH1_ST_Pos = 0x0
	// Bit mask of DMA2D_EVT_IN_SUC_EOF_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_IN_SUC_EOF_CH1_ST_Msk = 0x1
	// Bit DMA2D_EVT_IN_SUC_EOF_CH1_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_IN_SUC_EOF_CH1_ST = 0x1
	// Position of DMA2D_EVT_OUT_DONE_CH0_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH0_ST_Pos = 0x1
	// Bit mask of DMA2D_EVT_OUT_DONE_CH0_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH0_ST_Msk = 0x2
	// Bit DMA2D_EVT_OUT_DONE_CH0_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH0_ST = 0x2
	// Position of DMA2D_EVT_OUT_DONE_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH1_ST_Pos = 0x2
	// Bit mask of DMA2D_EVT_OUT_DONE_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH1_ST_Msk = 0x4
	// Bit DMA2D_EVT_OUT_DONE_CH1_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH1_ST = 0x4
	// Position of DMA2D_EVT_OUT_DONE_CH2_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH2_ST_Pos = 0x3
	// Bit mask of DMA2D_EVT_OUT_DONE_CH2_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH2_ST_Msk = 0x8
	// Bit DMA2D_EVT_OUT_DONE_CH2_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_DONE_CH2_ST = 0x8
	// Position of DMA2D_EVT_OUT_EOF_CH0_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH0_ST_Pos = 0x4
	// Bit mask of DMA2D_EVT_OUT_EOF_CH0_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH0_ST_Msk = 0x10
	// Bit DMA2D_EVT_OUT_EOF_CH0_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH0_ST = 0x10
	// Position of DMA2D_EVT_OUT_EOF_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH1_ST_Pos = 0x5
	// Bit mask of DMA2D_EVT_OUT_EOF_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH1_ST_Msk = 0x20
	// Bit DMA2D_EVT_OUT_EOF_CH1_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH1_ST = 0x20
	// Position of DMA2D_EVT_OUT_EOF_CH2_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH2_ST_Pos = 0x6
	// Bit mask of DMA2D_EVT_OUT_EOF_CH2_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH2_ST_Msk = 0x40
	// Bit DMA2D_EVT_OUT_EOF_CH2_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_EOF_CH2_ST = 0x40
	// Position of DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_Pos = 0x7
	// Bit mask of DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_Msk = 0x80
	// Bit DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST = 0x80
	// Position of DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_Pos = 0x8
	// Bit mask of DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_Msk = 0x100
	// Bit DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST = 0x100
	// Position of DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_Pos = 0x9
	// Bit mask of DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST field.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_Msk = 0x200
	// Bit DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST.
	SOC_ETM_EVT_ST7_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST = 0x200

	// EVT_ST7_CLR: Events trigger status clear register
	// Position of DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_Pos = 0x0
	// Bit mask of DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_Msk = 0x1
	// Bit DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR = 0x1
	// Position of DMA2D_EVT_OUT_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_Pos = 0x1
	// Bit mask of DMA2D_EVT_OUT_DONE_CH0_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH0_ST_CLR_Msk = 0x2
	// Bit DMA2D_EVT_OUT_DONE_CH0_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH0_ST_CLR = 0x2
	// Position of DMA2D_EVT_OUT_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_Pos = 0x2
	// Bit mask of DMA2D_EVT_OUT_DONE_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH1_ST_CLR_Msk = 0x4
	// Bit DMA2D_EVT_OUT_DONE_CH1_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH1_ST_CLR = 0x4
	// Position of DMA2D_EVT_OUT_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_Pos = 0x3
	// Bit mask of DMA2D_EVT_OUT_DONE_CH2_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH2_ST_CLR_Msk = 0x8
	// Bit DMA2D_EVT_OUT_DONE_CH2_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_DONE_CH2_ST_CLR = 0x8
	// Position of DMA2D_EVT_OUT_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_Pos = 0x4
	// Bit mask of DMA2D_EVT_OUT_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH0_ST_CLR_Msk = 0x10
	// Bit DMA2D_EVT_OUT_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH0_ST_CLR = 0x10
	// Position of DMA2D_EVT_OUT_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_Pos = 0x5
	// Bit mask of DMA2D_EVT_OUT_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH1_ST_CLR_Msk = 0x20
	// Bit DMA2D_EVT_OUT_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH1_ST_CLR = 0x20
	// Position of DMA2D_EVT_OUT_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_Pos = 0x6
	// Bit mask of DMA2D_EVT_OUT_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH2_ST_CLR_Msk = 0x40
	// Bit DMA2D_EVT_OUT_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_EOF_CH2_ST_CLR = 0x40
	// Position of DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_Pos = 0x7
	// Bit mask of DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_Msk = 0x80
	// Bit DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR = 0x80
	// Position of DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_Pos = 0x8
	// Bit mask of DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_Msk = 0x100
	// Bit DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR = 0x100
	// Position of DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_Pos = 0x9
	// Bit mask of DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR field.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_Msk = 0x200
	// Bit DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR.
	SOC_ETM_EVT_ST7_CLR_DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR = 0x200

	// TASK_ST0: Tasks trigger status register
	// Position of GPIO_TASK_CH0_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_SET_ST_Pos = 0x0
	// Bit mask of GPIO_TASK_CH0_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_SET_ST_Msk = 0x1
	// Bit GPIO_TASK_CH0_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_SET_ST = 0x1
	// Position of GPIO_TASK_CH1_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_SET_ST_Pos = 0x1
	// Bit mask of GPIO_TASK_CH1_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_SET_ST_Msk = 0x2
	// Bit GPIO_TASK_CH1_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_SET_ST = 0x2
	// Position of GPIO_TASK_CH2_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_SET_ST_Pos = 0x2
	// Bit mask of GPIO_TASK_CH2_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_SET_ST_Msk = 0x4
	// Bit GPIO_TASK_CH2_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_SET_ST = 0x4
	// Position of GPIO_TASK_CH3_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_SET_ST_Pos = 0x3
	// Bit mask of GPIO_TASK_CH3_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_SET_ST_Msk = 0x8
	// Bit GPIO_TASK_CH3_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_SET_ST = 0x8
	// Position of GPIO_TASK_CH4_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_SET_ST_Pos = 0x4
	// Bit mask of GPIO_TASK_CH4_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_SET_ST_Msk = 0x10
	// Bit GPIO_TASK_CH4_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_SET_ST = 0x10
	// Position of GPIO_TASK_CH5_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_SET_ST_Pos = 0x5
	// Bit mask of GPIO_TASK_CH5_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_SET_ST_Msk = 0x20
	// Bit GPIO_TASK_CH5_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_SET_ST = 0x20
	// Position of GPIO_TASK_CH6_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_SET_ST_Pos = 0x6
	// Bit mask of GPIO_TASK_CH6_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_SET_ST_Msk = 0x40
	// Bit GPIO_TASK_CH6_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_SET_ST = 0x40
	// Position of GPIO_TASK_CH7_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_SET_ST_Pos = 0x7
	// Bit mask of GPIO_TASK_CH7_SET_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_SET_ST_Msk = 0x80
	// Bit GPIO_TASK_CH7_SET_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_SET_ST = 0x80
	// Position of GPIO_TASK_CH0_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_CLEAR_ST_Pos = 0x8
	// Bit mask of GPIO_TASK_CH0_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_CLEAR_ST_Msk = 0x100
	// Bit GPIO_TASK_CH0_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_CLEAR_ST = 0x100
	// Position of GPIO_TASK_CH1_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_CLEAR_ST_Pos = 0x9
	// Bit mask of GPIO_TASK_CH1_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_CLEAR_ST_Msk = 0x200
	// Bit GPIO_TASK_CH1_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_CLEAR_ST = 0x200
	// Position of GPIO_TASK_CH2_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_CLEAR_ST_Pos = 0xa
	// Bit mask of GPIO_TASK_CH2_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_CLEAR_ST_Msk = 0x400
	// Bit GPIO_TASK_CH2_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_CLEAR_ST = 0x400
	// Position of GPIO_TASK_CH3_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_CLEAR_ST_Pos = 0xb
	// Bit mask of GPIO_TASK_CH3_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_CLEAR_ST_Msk = 0x800
	// Bit GPIO_TASK_CH3_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_CLEAR_ST = 0x800
	// Position of GPIO_TASK_CH4_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_CLEAR_ST_Pos = 0xc
	// Bit mask of GPIO_TASK_CH4_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_CLEAR_ST_Msk = 0x1000
	// Bit GPIO_TASK_CH4_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_CLEAR_ST = 0x1000
	// Position of GPIO_TASK_CH5_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_CLEAR_ST_Pos = 0xd
	// Bit mask of GPIO_TASK_CH5_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_CLEAR_ST_Msk = 0x2000
	// Bit GPIO_TASK_CH5_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_CLEAR_ST = 0x2000
	// Position of GPIO_TASK_CH6_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_CLEAR_ST_Pos = 0xe
	// Bit mask of GPIO_TASK_CH6_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_CLEAR_ST_Msk = 0x4000
	// Bit GPIO_TASK_CH6_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_CLEAR_ST = 0x4000
	// Position of GPIO_TASK_CH7_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_CLEAR_ST_Pos = 0xf
	// Bit mask of GPIO_TASK_CH7_CLEAR_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_CLEAR_ST_Msk = 0x8000
	// Bit GPIO_TASK_CH7_CLEAR_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_CLEAR_ST = 0x8000
	// Position of GPIO_TASK_CH0_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_TOGGLE_ST_Pos = 0x10
	// Bit mask of GPIO_TASK_CH0_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_TOGGLE_ST_Msk = 0x10000
	// Bit GPIO_TASK_CH0_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH0_TOGGLE_ST = 0x10000
	// Position of GPIO_TASK_CH1_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_TOGGLE_ST_Pos = 0x11
	// Bit mask of GPIO_TASK_CH1_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_TOGGLE_ST_Msk = 0x20000
	// Bit GPIO_TASK_CH1_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH1_TOGGLE_ST = 0x20000
	// Position of GPIO_TASK_CH2_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_TOGGLE_ST_Pos = 0x12
	// Bit mask of GPIO_TASK_CH2_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_TOGGLE_ST_Msk = 0x40000
	// Bit GPIO_TASK_CH2_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH2_TOGGLE_ST = 0x40000
	// Position of GPIO_TASK_CH3_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_TOGGLE_ST_Pos = 0x13
	// Bit mask of GPIO_TASK_CH3_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_TOGGLE_ST_Msk = 0x80000
	// Bit GPIO_TASK_CH3_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH3_TOGGLE_ST = 0x80000
	// Position of GPIO_TASK_CH4_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_TOGGLE_ST_Pos = 0x14
	// Bit mask of GPIO_TASK_CH4_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_TOGGLE_ST_Msk = 0x100000
	// Bit GPIO_TASK_CH4_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH4_TOGGLE_ST = 0x100000
	// Position of GPIO_TASK_CH5_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_TOGGLE_ST_Pos = 0x15
	// Bit mask of GPIO_TASK_CH5_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_TOGGLE_ST_Msk = 0x200000
	// Bit GPIO_TASK_CH5_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH5_TOGGLE_ST = 0x200000
	// Position of GPIO_TASK_CH6_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_TOGGLE_ST_Pos = 0x16
	// Bit mask of GPIO_TASK_CH6_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_TOGGLE_ST_Msk = 0x400000
	// Bit GPIO_TASK_CH6_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH6_TOGGLE_ST = 0x400000
	// Position of GPIO_TASK_CH7_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_TOGGLE_ST_Pos = 0x17
	// Bit mask of GPIO_TASK_CH7_TOGGLE_ST field.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_TOGGLE_ST_Msk = 0x800000
	// Bit GPIO_TASK_CH7_TOGGLE_ST.
	SOC_ETM_TASK_ST0_GPIO_TASK_CH7_TOGGLE_ST = 0x800000
	// Position of LEDC_TASK_TIMER0_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER0_RES_UPDATE_ST_Pos = 0x18
	// Bit mask of LEDC_TASK_TIMER0_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER0_RES_UPDATE_ST_Msk = 0x1000000
	// Bit LEDC_TASK_TIMER0_RES_UPDATE_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER0_RES_UPDATE_ST = 0x1000000
	// Position of LEDC_TASK_TIMER1_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER1_RES_UPDATE_ST_Pos = 0x19
	// Bit mask of LEDC_TASK_TIMER1_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER1_RES_UPDATE_ST_Msk = 0x2000000
	// Bit LEDC_TASK_TIMER1_RES_UPDATE_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER1_RES_UPDATE_ST = 0x2000000
	// Position of LEDC_TASK_TIMER2_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER2_RES_UPDATE_ST_Pos = 0x1a
	// Bit mask of LEDC_TASK_TIMER2_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER2_RES_UPDATE_ST_Msk = 0x4000000
	// Bit LEDC_TASK_TIMER2_RES_UPDATE_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER2_RES_UPDATE_ST = 0x4000000
	// Position of LEDC_TASK_TIMER3_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER3_RES_UPDATE_ST_Pos = 0x1b
	// Bit mask of LEDC_TASK_TIMER3_RES_UPDATE_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER3_RES_UPDATE_ST_Msk = 0x8000000
	// Bit LEDC_TASK_TIMER3_RES_UPDATE_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_TIMER3_RES_UPDATE_ST = 0x8000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_Pos = 0x1c
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_Msk = 0x10000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST = 0x10000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_Pos = 0x1d
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_Msk = 0x20000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST = 0x20000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_Pos = 0x1e
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_Msk = 0x40000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST = 0x40000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_Pos = 0x1f
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST field.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_Msk = 0x80000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST.
	SOC_ETM_TASK_ST0_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST = 0x80000000

	// TASK_ST0_CLR: Tasks trigger status clear register
	// Position of GPIO_TASK_CH0_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_SET_ST_CLR_Pos = 0x0
	// Bit mask of GPIO_TASK_CH0_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_SET_ST_CLR_Msk = 0x1
	// Bit GPIO_TASK_CH0_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_SET_ST_CLR = 0x1
	// Position of GPIO_TASK_CH1_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_SET_ST_CLR_Pos = 0x1
	// Bit mask of GPIO_TASK_CH1_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_SET_ST_CLR_Msk = 0x2
	// Bit GPIO_TASK_CH1_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_SET_ST_CLR = 0x2
	// Position of GPIO_TASK_CH2_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_SET_ST_CLR_Pos = 0x2
	// Bit mask of GPIO_TASK_CH2_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_SET_ST_CLR_Msk = 0x4
	// Bit GPIO_TASK_CH2_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_SET_ST_CLR = 0x4
	// Position of GPIO_TASK_CH3_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_SET_ST_CLR_Pos = 0x3
	// Bit mask of GPIO_TASK_CH3_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_SET_ST_CLR_Msk = 0x8
	// Bit GPIO_TASK_CH3_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_SET_ST_CLR = 0x8
	// Position of GPIO_TASK_CH4_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_SET_ST_CLR_Pos = 0x4
	// Bit mask of GPIO_TASK_CH4_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_SET_ST_CLR_Msk = 0x10
	// Bit GPIO_TASK_CH4_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_SET_ST_CLR = 0x10
	// Position of GPIO_TASK_CH5_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_SET_ST_CLR_Pos = 0x5
	// Bit mask of GPIO_TASK_CH5_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_SET_ST_CLR_Msk = 0x20
	// Bit GPIO_TASK_CH5_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_SET_ST_CLR = 0x20
	// Position of GPIO_TASK_CH6_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_SET_ST_CLR_Pos = 0x6
	// Bit mask of GPIO_TASK_CH6_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_SET_ST_CLR_Msk = 0x40
	// Bit GPIO_TASK_CH6_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_SET_ST_CLR = 0x40
	// Position of GPIO_TASK_CH7_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_SET_ST_CLR_Pos = 0x7
	// Bit mask of GPIO_TASK_CH7_SET_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_SET_ST_CLR_Msk = 0x80
	// Bit GPIO_TASK_CH7_SET_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_SET_ST_CLR = 0x80
	// Position of GPIO_TASK_CH0_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_CLEAR_ST_CLR_Pos = 0x8
	// Bit mask of GPIO_TASK_CH0_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_CLEAR_ST_CLR_Msk = 0x100
	// Bit GPIO_TASK_CH0_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_CLEAR_ST_CLR = 0x100
	// Position of GPIO_TASK_CH1_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_CLEAR_ST_CLR_Pos = 0x9
	// Bit mask of GPIO_TASK_CH1_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_CLEAR_ST_CLR_Msk = 0x200
	// Bit GPIO_TASK_CH1_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_CLEAR_ST_CLR = 0x200
	// Position of GPIO_TASK_CH2_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_CLEAR_ST_CLR_Pos = 0xa
	// Bit mask of GPIO_TASK_CH2_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_CLEAR_ST_CLR_Msk = 0x400
	// Bit GPIO_TASK_CH2_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_CLEAR_ST_CLR = 0x400
	// Position of GPIO_TASK_CH3_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_CLEAR_ST_CLR_Pos = 0xb
	// Bit mask of GPIO_TASK_CH3_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_CLEAR_ST_CLR_Msk = 0x800
	// Bit GPIO_TASK_CH3_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_CLEAR_ST_CLR = 0x800
	// Position of GPIO_TASK_CH4_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_CLEAR_ST_CLR_Pos = 0xc
	// Bit mask of GPIO_TASK_CH4_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_CLEAR_ST_CLR_Msk = 0x1000
	// Bit GPIO_TASK_CH4_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_CLEAR_ST_CLR = 0x1000
	// Position of GPIO_TASK_CH5_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_CLEAR_ST_CLR_Pos = 0xd
	// Bit mask of GPIO_TASK_CH5_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_CLEAR_ST_CLR_Msk = 0x2000
	// Bit GPIO_TASK_CH5_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_CLEAR_ST_CLR = 0x2000
	// Position of GPIO_TASK_CH6_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_CLEAR_ST_CLR_Pos = 0xe
	// Bit mask of GPIO_TASK_CH6_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_CLEAR_ST_CLR_Msk = 0x4000
	// Bit GPIO_TASK_CH6_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_CLEAR_ST_CLR = 0x4000
	// Position of GPIO_TASK_CH7_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_CLEAR_ST_CLR_Pos = 0xf
	// Bit mask of GPIO_TASK_CH7_CLEAR_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_CLEAR_ST_CLR_Msk = 0x8000
	// Bit GPIO_TASK_CH7_CLEAR_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_CLEAR_ST_CLR = 0x8000
	// Position of GPIO_TASK_CH0_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_TOGGLE_ST_CLR_Pos = 0x10
	// Bit mask of GPIO_TASK_CH0_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_TOGGLE_ST_CLR_Msk = 0x10000
	// Bit GPIO_TASK_CH0_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH0_TOGGLE_ST_CLR = 0x10000
	// Position of GPIO_TASK_CH1_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_TOGGLE_ST_CLR_Pos = 0x11
	// Bit mask of GPIO_TASK_CH1_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_TOGGLE_ST_CLR_Msk = 0x20000
	// Bit GPIO_TASK_CH1_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH1_TOGGLE_ST_CLR = 0x20000
	// Position of GPIO_TASK_CH2_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_TOGGLE_ST_CLR_Pos = 0x12
	// Bit mask of GPIO_TASK_CH2_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_TOGGLE_ST_CLR_Msk = 0x40000
	// Bit GPIO_TASK_CH2_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH2_TOGGLE_ST_CLR = 0x40000
	// Position of GPIO_TASK_CH3_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_TOGGLE_ST_CLR_Pos = 0x13
	// Bit mask of GPIO_TASK_CH3_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_TOGGLE_ST_CLR_Msk = 0x80000
	// Bit GPIO_TASK_CH3_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH3_TOGGLE_ST_CLR = 0x80000
	// Position of GPIO_TASK_CH4_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_TOGGLE_ST_CLR_Pos = 0x14
	// Bit mask of GPIO_TASK_CH4_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_TOGGLE_ST_CLR_Msk = 0x100000
	// Bit GPIO_TASK_CH4_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH4_TOGGLE_ST_CLR = 0x100000
	// Position of GPIO_TASK_CH5_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_TOGGLE_ST_CLR_Pos = 0x15
	// Bit mask of GPIO_TASK_CH5_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_TOGGLE_ST_CLR_Msk = 0x200000
	// Bit GPIO_TASK_CH5_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH5_TOGGLE_ST_CLR = 0x200000
	// Position of GPIO_TASK_CH6_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_TOGGLE_ST_CLR_Pos = 0x16
	// Bit mask of GPIO_TASK_CH6_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_TOGGLE_ST_CLR_Msk = 0x400000
	// Bit GPIO_TASK_CH6_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH6_TOGGLE_ST_CLR = 0x400000
	// Position of GPIO_TASK_CH7_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_TOGGLE_ST_CLR_Pos = 0x17
	// Bit mask of GPIO_TASK_CH7_TOGGLE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_TOGGLE_ST_CLR_Msk = 0x800000
	// Bit GPIO_TASK_CH7_TOGGLE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_GPIO_TASK_CH7_TOGGLE_ST_CLR = 0x800000
	// Position of LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_Pos = 0x18
	// Bit mask of LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_Msk = 0x1000000
	// Bit LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR = 0x1000000
	// Position of LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_Pos = 0x19
	// Bit mask of LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_Msk = 0x2000000
	// Bit LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR = 0x2000000
	// Position of LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_Pos = 0x1a
	// Bit mask of LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_Msk = 0x4000000
	// Bit LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR = 0x4000000
	// Position of LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_Pos = 0x1b
	// Bit mask of LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_Msk = 0x8000000
	// Bit LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR = 0x8000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_Pos = 0x1c
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_Msk = 0x10000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR = 0x10000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_Pos = 0x1d
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_Msk = 0x20000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR = 0x20000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_Pos = 0x1e
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_Msk = 0x40000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR = 0x40000000
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_Pos = 0x1f
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR field.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_Msk = 0x80000000
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR.
	SOC_ETM_TASK_ST0_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR = 0x80000000

	// TASK_ST1: Tasks trigger status register
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_Pos = 0x0
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_Msk = 0x1
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST = 0x1
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_Pos = 0x1
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_Msk = 0x2
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST = 0x2
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_Pos = 0x2
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_Msk = 0x4
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST = 0x4
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_Pos = 0x3
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_Msk = 0x8
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST = 0x8
	// Position of LEDC_TASK_TIMER0_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_CAP_ST_Pos = 0x4
	// Bit mask of LEDC_TASK_TIMER0_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_CAP_ST_Msk = 0x10
	// Bit LEDC_TASK_TIMER0_CAP_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_CAP_ST = 0x10
	// Position of LEDC_TASK_TIMER1_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_CAP_ST_Pos = 0x5
	// Bit mask of LEDC_TASK_TIMER1_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_CAP_ST_Msk = 0x20
	// Bit LEDC_TASK_TIMER1_CAP_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_CAP_ST = 0x20
	// Position of LEDC_TASK_TIMER2_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_CAP_ST_Pos = 0x6
	// Bit mask of LEDC_TASK_TIMER2_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_CAP_ST_Msk = 0x40
	// Bit LEDC_TASK_TIMER2_CAP_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_CAP_ST = 0x40
	// Position of LEDC_TASK_TIMER3_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_CAP_ST_Pos = 0x7
	// Bit mask of LEDC_TASK_TIMER3_CAP_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_CAP_ST_Msk = 0x80
	// Bit LEDC_TASK_TIMER3_CAP_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_CAP_ST = 0x80
	// Position of LEDC_TASK_SIG_OUT_DIS_CH0_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH0_ST_Pos = 0x8
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH0_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH0_ST_Msk = 0x100
	// Bit LEDC_TASK_SIG_OUT_DIS_CH0_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH0_ST = 0x100
	// Position of LEDC_TASK_SIG_OUT_DIS_CH1_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH1_ST_Pos = 0x9
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH1_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH1_ST_Msk = 0x200
	// Bit LEDC_TASK_SIG_OUT_DIS_CH1_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH1_ST = 0x200
	// Position of LEDC_TASK_SIG_OUT_DIS_CH2_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH2_ST_Pos = 0xa
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH2_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH2_ST_Msk = 0x400
	// Bit LEDC_TASK_SIG_OUT_DIS_CH2_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH2_ST = 0x400
	// Position of LEDC_TASK_SIG_OUT_DIS_CH3_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH3_ST_Pos = 0xb
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH3_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH3_ST_Msk = 0x800
	// Bit LEDC_TASK_SIG_OUT_DIS_CH3_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH3_ST = 0x800
	// Position of LEDC_TASK_SIG_OUT_DIS_CH4_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH4_ST_Pos = 0xc
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH4_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH4_ST_Msk = 0x1000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH4_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH4_ST = 0x1000
	// Position of LEDC_TASK_SIG_OUT_DIS_CH5_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH5_ST_Pos = 0xd
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH5_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH5_ST_Msk = 0x2000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH5_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH5_ST = 0x2000
	// Position of LEDC_TASK_SIG_OUT_DIS_CH6_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH6_ST_Pos = 0xe
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH6_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH6_ST_Msk = 0x4000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH6_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH6_ST = 0x4000
	// Position of LEDC_TASK_SIG_OUT_DIS_CH7_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH7_ST_Pos = 0xf
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH7_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH7_ST_Msk = 0x8000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH7_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_SIG_OUT_DIS_CH7_ST = 0x8000
	// Position of LEDC_TASK_OVF_CNT_RST_CH0_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH0_ST_Pos = 0x10
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH0_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH0_ST_Msk = 0x10000
	// Bit LEDC_TASK_OVF_CNT_RST_CH0_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH0_ST = 0x10000
	// Position of LEDC_TASK_OVF_CNT_RST_CH1_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH1_ST_Pos = 0x11
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH1_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH1_ST_Msk = 0x20000
	// Bit LEDC_TASK_OVF_CNT_RST_CH1_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH1_ST = 0x20000
	// Position of LEDC_TASK_OVF_CNT_RST_CH2_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH2_ST_Pos = 0x12
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH2_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH2_ST_Msk = 0x40000
	// Bit LEDC_TASK_OVF_CNT_RST_CH2_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH2_ST = 0x40000
	// Position of LEDC_TASK_OVF_CNT_RST_CH3_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH3_ST_Pos = 0x13
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH3_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH3_ST_Msk = 0x80000
	// Bit LEDC_TASK_OVF_CNT_RST_CH3_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH3_ST = 0x80000
	// Position of LEDC_TASK_OVF_CNT_RST_CH4_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH4_ST_Pos = 0x14
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH4_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH4_ST_Msk = 0x100000
	// Bit LEDC_TASK_OVF_CNT_RST_CH4_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH4_ST = 0x100000
	// Position of LEDC_TASK_OVF_CNT_RST_CH5_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH5_ST_Pos = 0x15
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH5_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH5_ST_Msk = 0x200000
	// Bit LEDC_TASK_OVF_CNT_RST_CH5_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH5_ST = 0x200000
	// Position of LEDC_TASK_OVF_CNT_RST_CH6_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH6_ST_Pos = 0x16
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH6_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH6_ST_Msk = 0x400000
	// Bit LEDC_TASK_OVF_CNT_RST_CH6_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH6_ST = 0x400000
	// Position of LEDC_TASK_OVF_CNT_RST_CH7_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH7_ST_Pos = 0x17
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH7_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH7_ST_Msk = 0x800000
	// Bit LEDC_TASK_OVF_CNT_RST_CH7_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_OVF_CNT_RST_CH7_ST = 0x800000
	// Position of LEDC_TASK_TIMER0_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_RST_ST_Pos = 0x18
	// Bit mask of LEDC_TASK_TIMER0_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_RST_ST_Msk = 0x1000000
	// Bit LEDC_TASK_TIMER0_RST_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_RST_ST = 0x1000000
	// Position of LEDC_TASK_TIMER1_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_RST_ST_Pos = 0x19
	// Bit mask of LEDC_TASK_TIMER1_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_RST_ST_Msk = 0x2000000
	// Bit LEDC_TASK_TIMER1_RST_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_RST_ST = 0x2000000
	// Position of LEDC_TASK_TIMER2_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_RST_ST_Pos = 0x1a
	// Bit mask of LEDC_TASK_TIMER2_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_RST_ST_Msk = 0x4000000
	// Bit LEDC_TASK_TIMER2_RST_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_RST_ST = 0x4000000
	// Position of LEDC_TASK_TIMER3_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_RST_ST_Pos = 0x1b
	// Bit mask of LEDC_TASK_TIMER3_RST_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_RST_ST_Msk = 0x8000000
	// Bit LEDC_TASK_TIMER3_RST_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_RST_ST = 0x8000000
	// Position of LEDC_TASK_TIMER0_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_RESUME_ST_Pos = 0x1c
	// Bit mask of LEDC_TASK_TIMER0_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_RESUME_ST_Msk = 0x10000000
	// Bit LEDC_TASK_TIMER0_RESUME_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER0_RESUME_ST = 0x10000000
	// Position of LEDC_TASK_TIMER1_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_RESUME_ST_Pos = 0x1d
	// Bit mask of LEDC_TASK_TIMER1_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_RESUME_ST_Msk = 0x20000000
	// Bit LEDC_TASK_TIMER1_RESUME_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER1_RESUME_ST = 0x20000000
	// Position of LEDC_TASK_TIMER2_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_RESUME_ST_Pos = 0x1e
	// Bit mask of LEDC_TASK_TIMER2_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_RESUME_ST_Msk = 0x40000000
	// Bit LEDC_TASK_TIMER2_RESUME_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER2_RESUME_ST = 0x40000000
	// Position of LEDC_TASK_TIMER3_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_RESUME_ST_Pos = 0x1f
	// Bit mask of LEDC_TASK_TIMER3_RESUME_ST field.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_RESUME_ST_Msk = 0x80000000
	// Bit LEDC_TASK_TIMER3_RESUME_ST.
	SOC_ETM_TASK_ST1_LEDC_TASK_TIMER3_RESUME_ST = 0x80000000

	// TASK_ST1_CLR: Tasks trigger status clear register
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_Pos = 0x0
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_Msk = 0x1
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR = 0x1
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_Pos = 0x1
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_Msk = 0x2
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR = 0x2
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_Pos = 0x2
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_Msk = 0x4
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR = 0x4
	// Position of LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_Pos = 0x3
	// Bit mask of LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_Msk = 0x8
	// Bit LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR = 0x8
	// Position of LEDC_TASK_TIMER0_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_CAP_ST_CLR_Pos = 0x4
	// Bit mask of LEDC_TASK_TIMER0_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_CAP_ST_CLR_Msk = 0x10
	// Bit LEDC_TASK_TIMER0_CAP_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_CAP_ST_CLR = 0x10
	// Position of LEDC_TASK_TIMER1_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_CAP_ST_CLR_Pos = 0x5
	// Bit mask of LEDC_TASK_TIMER1_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_CAP_ST_CLR_Msk = 0x20
	// Bit LEDC_TASK_TIMER1_CAP_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_CAP_ST_CLR = 0x20
	// Position of LEDC_TASK_TIMER2_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_CAP_ST_CLR_Pos = 0x6
	// Bit mask of LEDC_TASK_TIMER2_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_CAP_ST_CLR_Msk = 0x40
	// Bit LEDC_TASK_TIMER2_CAP_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_CAP_ST_CLR = 0x40
	// Position of LEDC_TASK_TIMER3_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_CAP_ST_CLR_Pos = 0x7
	// Bit mask of LEDC_TASK_TIMER3_CAP_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_CAP_ST_CLR_Msk = 0x80
	// Bit LEDC_TASK_TIMER3_CAP_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_CAP_ST_CLR = 0x80
	// Position of LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_Pos = 0x8
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_Msk = 0x100
	// Bit LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR = 0x100
	// Position of LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_Pos = 0x9
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_Msk = 0x200
	// Bit LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR = 0x200
	// Position of LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_Pos = 0xa
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_Msk = 0x400
	// Bit LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR = 0x400
	// Position of LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_Pos = 0xb
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_Msk = 0x800
	// Bit LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR = 0x800
	// Position of LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_Pos = 0xc
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_Msk = 0x1000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR = 0x1000
	// Position of LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_Pos = 0xd
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_Msk = 0x2000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR = 0x2000
	// Position of LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_Pos = 0xe
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_Msk = 0x4000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR = 0x4000
	// Position of LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_Pos = 0xf
	// Bit mask of LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_Msk = 0x8000
	// Bit LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR = 0x8000
	// Position of LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_Pos = 0x10
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_Msk = 0x10000
	// Bit LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR = 0x10000
	// Position of LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_Pos = 0x11
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_Msk = 0x20000
	// Bit LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR = 0x20000
	// Position of LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_Pos = 0x12
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_Msk = 0x40000
	// Bit LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR = 0x40000
	// Position of LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_Pos = 0x13
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_Msk = 0x80000
	// Bit LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR = 0x80000
	// Position of LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_Pos = 0x14
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_Msk = 0x100000
	// Bit LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR = 0x100000
	// Position of LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_Pos = 0x15
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_Msk = 0x200000
	// Bit LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR = 0x200000
	// Position of LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_Pos = 0x16
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_Msk = 0x400000
	// Bit LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR = 0x400000
	// Position of LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_Pos = 0x17
	// Bit mask of LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_Msk = 0x800000
	// Bit LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR = 0x800000
	// Position of LEDC_TASK_TIMER0_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_RST_ST_CLR_Pos = 0x18
	// Bit mask of LEDC_TASK_TIMER0_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_RST_ST_CLR_Msk = 0x1000000
	// Bit LEDC_TASK_TIMER0_RST_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_RST_ST_CLR = 0x1000000
	// Position of LEDC_TASK_TIMER1_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_RST_ST_CLR_Pos = 0x19
	// Bit mask of LEDC_TASK_TIMER1_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_RST_ST_CLR_Msk = 0x2000000
	// Bit LEDC_TASK_TIMER1_RST_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_RST_ST_CLR = 0x2000000
	// Position of LEDC_TASK_TIMER2_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_RST_ST_CLR_Pos = 0x1a
	// Bit mask of LEDC_TASK_TIMER2_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_RST_ST_CLR_Msk = 0x4000000
	// Bit LEDC_TASK_TIMER2_RST_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_RST_ST_CLR = 0x4000000
	// Position of LEDC_TASK_TIMER3_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_RST_ST_CLR_Pos = 0x1b
	// Bit mask of LEDC_TASK_TIMER3_RST_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_RST_ST_CLR_Msk = 0x8000000
	// Bit LEDC_TASK_TIMER3_RST_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_RST_ST_CLR = 0x8000000
	// Position of LEDC_TASK_TIMER0_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_RESUME_ST_CLR_Pos = 0x1c
	// Bit mask of LEDC_TASK_TIMER0_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_RESUME_ST_CLR_Msk = 0x10000000
	// Bit LEDC_TASK_TIMER0_RESUME_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER0_RESUME_ST_CLR = 0x10000000
	// Position of LEDC_TASK_TIMER1_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_RESUME_ST_CLR_Pos = 0x1d
	// Bit mask of LEDC_TASK_TIMER1_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_RESUME_ST_CLR_Msk = 0x20000000
	// Bit LEDC_TASK_TIMER1_RESUME_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER1_RESUME_ST_CLR = 0x20000000
	// Position of LEDC_TASK_TIMER2_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_RESUME_ST_CLR_Pos = 0x1e
	// Bit mask of LEDC_TASK_TIMER2_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_RESUME_ST_CLR_Msk = 0x40000000
	// Bit LEDC_TASK_TIMER2_RESUME_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER2_RESUME_ST_CLR = 0x40000000
	// Position of LEDC_TASK_TIMER3_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_RESUME_ST_CLR_Pos = 0x1f
	// Bit mask of LEDC_TASK_TIMER3_RESUME_ST_CLR field.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_RESUME_ST_CLR_Msk = 0x80000000
	// Bit LEDC_TASK_TIMER3_RESUME_ST_CLR.
	SOC_ETM_TASK_ST1_CLR_LEDC_TASK_TIMER3_RESUME_ST_CLR = 0x80000000

	// TASK_ST2: Tasks trigger status register
	// Position of LEDC_TASK_TIMER0_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER0_PAUSE_ST_Pos = 0x0
	// Bit mask of LEDC_TASK_TIMER0_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER0_PAUSE_ST_Msk = 0x1
	// Bit LEDC_TASK_TIMER0_PAUSE_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER0_PAUSE_ST = 0x1
	// Position of LEDC_TASK_TIMER1_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER1_PAUSE_ST_Pos = 0x1
	// Bit mask of LEDC_TASK_TIMER1_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER1_PAUSE_ST_Msk = 0x2
	// Bit LEDC_TASK_TIMER1_PAUSE_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER1_PAUSE_ST = 0x2
	// Position of LEDC_TASK_TIMER2_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER2_PAUSE_ST_Pos = 0x2
	// Bit mask of LEDC_TASK_TIMER2_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER2_PAUSE_ST_Msk = 0x4
	// Bit LEDC_TASK_TIMER2_PAUSE_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER2_PAUSE_ST = 0x4
	// Position of LEDC_TASK_TIMER3_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER3_PAUSE_ST_Pos = 0x3
	// Bit mask of LEDC_TASK_TIMER3_PAUSE_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER3_PAUSE_ST_Msk = 0x8
	// Bit LEDC_TASK_TIMER3_PAUSE_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_TIMER3_PAUSE_ST = 0x8
	// Position of LEDC_TASK_GAMMA_RESTART_CH0_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH0_ST_Pos = 0x4
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH0_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH0_ST_Msk = 0x10
	// Bit LEDC_TASK_GAMMA_RESTART_CH0_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH0_ST = 0x10
	// Position of LEDC_TASK_GAMMA_RESTART_CH1_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH1_ST_Pos = 0x5
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH1_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH1_ST_Msk = 0x20
	// Bit LEDC_TASK_GAMMA_RESTART_CH1_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH1_ST = 0x20
	// Position of LEDC_TASK_GAMMA_RESTART_CH2_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH2_ST_Pos = 0x6
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH2_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH2_ST_Msk = 0x40
	// Bit LEDC_TASK_GAMMA_RESTART_CH2_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH2_ST = 0x40
	// Position of LEDC_TASK_GAMMA_RESTART_CH3_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH3_ST_Pos = 0x7
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH3_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH3_ST_Msk = 0x80
	// Bit LEDC_TASK_GAMMA_RESTART_CH3_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH3_ST = 0x80
	// Position of LEDC_TASK_GAMMA_RESTART_CH4_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH4_ST_Pos = 0x8
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH4_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH4_ST_Msk = 0x100
	// Bit LEDC_TASK_GAMMA_RESTART_CH4_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH4_ST = 0x100
	// Position of LEDC_TASK_GAMMA_RESTART_CH5_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH5_ST_Pos = 0x9
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH5_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH5_ST_Msk = 0x200
	// Bit LEDC_TASK_GAMMA_RESTART_CH5_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH5_ST = 0x200
	// Position of LEDC_TASK_GAMMA_RESTART_CH6_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH6_ST_Pos = 0xa
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH6_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH6_ST_Msk = 0x400
	// Bit LEDC_TASK_GAMMA_RESTART_CH6_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH6_ST = 0x400
	// Position of LEDC_TASK_GAMMA_RESTART_CH7_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH7_ST_Pos = 0xb
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH7_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH7_ST_Msk = 0x800
	// Bit LEDC_TASK_GAMMA_RESTART_CH7_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESTART_CH7_ST = 0x800
	// Position of LEDC_TASK_GAMMA_PAUSE_CH0_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH0_ST_Pos = 0xc
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH0_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH0_ST_Msk = 0x1000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH0_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH0_ST = 0x1000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH1_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH1_ST_Pos = 0xd
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH1_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH1_ST_Msk = 0x2000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH1_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH1_ST = 0x2000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH2_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH2_ST_Pos = 0xe
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH2_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH2_ST_Msk = 0x4000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH2_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH2_ST = 0x4000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH3_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH3_ST_Pos = 0xf
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH3_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH3_ST_Msk = 0x8000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH3_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH3_ST = 0x8000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH4_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH4_ST_Pos = 0x10
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH4_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH4_ST_Msk = 0x10000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH4_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH4_ST = 0x10000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH5_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH5_ST_Pos = 0x11
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH5_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH5_ST_Msk = 0x20000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH5_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH5_ST = 0x20000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH6_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH6_ST_Pos = 0x12
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH6_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH6_ST_Msk = 0x40000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH6_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH6_ST = 0x40000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH7_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH7_ST_Pos = 0x13
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH7_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH7_ST_Msk = 0x80000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH7_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_PAUSE_CH7_ST = 0x80000
	// Position of LEDC_TASK_GAMMA_RESUME_CH0_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH0_ST_Pos = 0x14
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH0_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH0_ST_Msk = 0x100000
	// Bit LEDC_TASK_GAMMA_RESUME_CH0_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH0_ST = 0x100000
	// Position of LEDC_TASK_GAMMA_RESUME_CH1_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH1_ST_Pos = 0x15
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH1_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH1_ST_Msk = 0x200000
	// Bit LEDC_TASK_GAMMA_RESUME_CH1_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH1_ST = 0x200000
	// Position of LEDC_TASK_GAMMA_RESUME_CH2_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH2_ST_Pos = 0x16
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH2_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH2_ST_Msk = 0x400000
	// Bit LEDC_TASK_GAMMA_RESUME_CH2_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH2_ST = 0x400000
	// Position of LEDC_TASK_GAMMA_RESUME_CH3_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH3_ST_Pos = 0x17
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH3_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH3_ST_Msk = 0x800000
	// Bit LEDC_TASK_GAMMA_RESUME_CH3_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH3_ST = 0x800000
	// Position of LEDC_TASK_GAMMA_RESUME_CH4_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH4_ST_Pos = 0x18
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH4_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH4_ST_Msk = 0x1000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH4_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH4_ST = 0x1000000
	// Position of LEDC_TASK_GAMMA_RESUME_CH5_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH5_ST_Pos = 0x19
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH5_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH5_ST_Msk = 0x2000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH5_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH5_ST = 0x2000000
	// Position of LEDC_TASK_GAMMA_RESUME_CH6_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH6_ST_Pos = 0x1a
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH6_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH6_ST_Msk = 0x4000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH6_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH6_ST = 0x4000000
	// Position of LEDC_TASK_GAMMA_RESUME_CH7_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH7_ST_Pos = 0x1b
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH7_ST field.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH7_ST_Msk = 0x8000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH7_ST.
	SOC_ETM_TASK_ST2_LEDC_TASK_GAMMA_RESUME_CH7_ST = 0x8000000
	// Position of TG0_TASK_CNT_START_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_START_TIMER0_ST_Pos = 0x1c
	// Bit mask of TG0_TASK_CNT_START_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_START_TIMER0_ST_Msk = 0x10000000
	// Bit TG0_TASK_CNT_START_TIMER0_ST.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_START_TIMER0_ST = 0x10000000
	// Position of TG0_TASK_ALARM_START_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_ALARM_START_TIMER0_ST_Pos = 0x1d
	// Bit mask of TG0_TASK_ALARM_START_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_ALARM_START_TIMER0_ST_Msk = 0x20000000
	// Bit TG0_TASK_ALARM_START_TIMER0_ST.
	SOC_ETM_TASK_ST2_TG0_TASK_ALARM_START_TIMER0_ST = 0x20000000
	// Position of TG0_TASK_CNT_STOP_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_STOP_TIMER0_ST_Pos = 0x1e
	// Bit mask of TG0_TASK_CNT_STOP_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_STOP_TIMER0_ST_Msk = 0x40000000
	// Bit TG0_TASK_CNT_STOP_TIMER0_ST.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_STOP_TIMER0_ST = 0x40000000
	// Position of TG0_TASK_CNT_RELOAD_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_RELOAD_TIMER0_ST_Pos = 0x1f
	// Bit mask of TG0_TASK_CNT_RELOAD_TIMER0_ST field.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_RELOAD_TIMER0_ST_Msk = 0x80000000
	// Bit TG0_TASK_CNT_RELOAD_TIMER0_ST.
	SOC_ETM_TASK_ST2_TG0_TASK_CNT_RELOAD_TIMER0_ST = 0x80000000

	// TASK_ST2_CLR: Tasks trigger status clear register
	// Position of LEDC_TASK_TIMER0_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER0_PAUSE_ST_CLR_Pos = 0x0
	// Bit mask of LEDC_TASK_TIMER0_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER0_PAUSE_ST_CLR_Msk = 0x1
	// Bit LEDC_TASK_TIMER0_PAUSE_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER0_PAUSE_ST_CLR = 0x1
	// Position of LEDC_TASK_TIMER1_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER1_PAUSE_ST_CLR_Pos = 0x1
	// Bit mask of LEDC_TASK_TIMER1_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER1_PAUSE_ST_CLR_Msk = 0x2
	// Bit LEDC_TASK_TIMER1_PAUSE_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER1_PAUSE_ST_CLR = 0x2
	// Position of LEDC_TASK_TIMER2_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER2_PAUSE_ST_CLR_Pos = 0x2
	// Bit mask of LEDC_TASK_TIMER2_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER2_PAUSE_ST_CLR_Msk = 0x4
	// Bit LEDC_TASK_TIMER2_PAUSE_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER2_PAUSE_ST_CLR = 0x4
	// Position of LEDC_TASK_TIMER3_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER3_PAUSE_ST_CLR_Pos = 0x3
	// Bit mask of LEDC_TASK_TIMER3_PAUSE_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER3_PAUSE_ST_CLR_Msk = 0x8
	// Bit LEDC_TASK_TIMER3_PAUSE_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_TIMER3_PAUSE_ST_CLR = 0x8
	// Position of LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_Pos = 0x4
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_Msk = 0x10
	// Bit LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR = 0x10
	// Position of LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_Pos = 0x5
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_Msk = 0x20
	// Bit LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR = 0x20
	// Position of LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_Pos = 0x6
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_Msk = 0x40
	// Bit LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR = 0x40
	// Position of LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_Pos = 0x7
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_Msk = 0x80
	// Bit LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR = 0x80
	// Position of LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_Pos = 0x8
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_Msk = 0x100
	// Bit LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR = 0x100
	// Position of LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_Pos = 0x9
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_Msk = 0x200
	// Bit LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR = 0x200
	// Position of LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_Pos = 0xa
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_Msk = 0x400
	// Bit LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR = 0x400
	// Position of LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_Pos = 0xb
	// Bit mask of LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_Msk = 0x800
	// Bit LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR = 0x800
	// Position of LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_Pos = 0xc
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_Msk = 0x1000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR = 0x1000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_Pos = 0xd
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_Msk = 0x2000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR = 0x2000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_Pos = 0xe
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_Msk = 0x4000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR = 0x4000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_Pos = 0xf
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_Msk = 0x8000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR = 0x8000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_Pos = 0x10
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_Msk = 0x10000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR = 0x10000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_Pos = 0x11
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_Msk = 0x20000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR = 0x20000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_Pos = 0x12
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_Msk = 0x40000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR = 0x40000
	// Position of LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_Pos = 0x13
	// Bit mask of LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_Msk = 0x80000
	// Bit LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR = 0x80000
	// Position of LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_Pos = 0x14
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_Msk = 0x100000
	// Bit LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR = 0x100000
	// Position of LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_Pos = 0x15
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_Msk = 0x200000
	// Bit LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR = 0x200000
	// Position of LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_Pos = 0x16
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_Msk = 0x400000
	// Bit LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR = 0x400000
	// Position of LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_Pos = 0x17
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_Msk = 0x800000
	// Bit LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR = 0x800000
	// Position of LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_Pos = 0x18
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_Msk = 0x1000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR = 0x1000000
	// Position of LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_Pos = 0x19
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_Msk = 0x2000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR = 0x2000000
	// Position of LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_Pos = 0x1a
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_Msk = 0x4000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR = 0x4000000
	// Position of LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_Pos = 0x1b
	// Bit mask of LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_Msk = 0x8000000
	// Bit LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR = 0x8000000
	// Position of TG0_TASK_CNT_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_START_TIMER0_ST_CLR_Pos = 0x1c
	// Bit mask of TG0_TASK_CNT_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_START_TIMER0_ST_CLR_Msk = 0x10000000
	// Bit TG0_TASK_CNT_START_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_START_TIMER0_ST_CLR = 0x10000000
	// Position of TG0_TASK_ALARM_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_ALARM_START_TIMER0_ST_CLR_Pos = 0x1d
	// Bit mask of TG0_TASK_ALARM_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_ALARM_START_TIMER0_ST_CLR_Msk = 0x20000000
	// Bit TG0_TASK_ALARM_START_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_ALARM_START_TIMER0_ST_CLR = 0x20000000
	// Position of TG0_TASK_CNT_STOP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_Pos = 0x1e
	// Bit mask of TG0_TASK_CNT_STOP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_Msk = 0x40000000
	// Bit TG0_TASK_CNT_STOP_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_STOP_TIMER0_ST_CLR = 0x40000000
	// Position of TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_Pos = 0x1f
	// Bit mask of TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_Msk = 0x80000000
	// Bit TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST2_CLR_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR = 0x80000000

	// TASK_ST3: Tasks trigger status register
	// Position of TG0_TASK_CNT_CAP_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_CAP_TIMER0_ST_Pos = 0x0
	// Bit mask of TG0_TASK_CNT_CAP_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_CAP_TIMER0_ST_Msk = 0x1
	// Bit TG0_TASK_CNT_CAP_TIMER0_ST.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_CAP_TIMER0_ST = 0x1
	// Position of TG0_TASK_CNT_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_START_TIMER1_ST_Pos = 0x1
	// Bit mask of TG0_TASK_CNT_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_START_TIMER1_ST_Msk = 0x2
	// Bit TG0_TASK_CNT_START_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_START_TIMER1_ST = 0x2
	// Position of TG0_TASK_ALARM_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_ALARM_START_TIMER1_ST_Pos = 0x2
	// Bit mask of TG0_TASK_ALARM_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_ALARM_START_TIMER1_ST_Msk = 0x4
	// Bit TG0_TASK_ALARM_START_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG0_TASK_ALARM_START_TIMER1_ST = 0x4
	// Position of TG0_TASK_CNT_STOP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_STOP_TIMER1_ST_Pos = 0x3
	// Bit mask of TG0_TASK_CNT_STOP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_STOP_TIMER1_ST_Msk = 0x8
	// Bit TG0_TASK_CNT_STOP_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_STOP_TIMER1_ST = 0x8
	// Position of TG0_TASK_CNT_RELOAD_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_RELOAD_TIMER1_ST_Pos = 0x4
	// Bit mask of TG0_TASK_CNT_RELOAD_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_RELOAD_TIMER1_ST_Msk = 0x10
	// Bit TG0_TASK_CNT_RELOAD_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_RELOAD_TIMER1_ST = 0x10
	// Position of TG0_TASK_CNT_CAP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_CAP_TIMER1_ST_Pos = 0x5
	// Bit mask of TG0_TASK_CNT_CAP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_CAP_TIMER1_ST_Msk = 0x20
	// Bit TG0_TASK_CNT_CAP_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG0_TASK_CNT_CAP_TIMER1_ST = 0x20
	// Position of TG1_TASK_CNT_START_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_START_TIMER0_ST_Pos = 0x6
	// Bit mask of TG1_TASK_CNT_START_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_START_TIMER0_ST_Msk = 0x40
	// Bit TG1_TASK_CNT_START_TIMER0_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_START_TIMER0_ST = 0x40
	// Position of TG1_TASK_ALARM_START_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_ALARM_START_TIMER0_ST_Pos = 0x7
	// Bit mask of TG1_TASK_ALARM_START_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_ALARM_START_TIMER0_ST_Msk = 0x80
	// Bit TG1_TASK_ALARM_START_TIMER0_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_ALARM_START_TIMER0_ST = 0x80
	// Position of TG1_TASK_CNT_STOP_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_STOP_TIMER0_ST_Pos = 0x8
	// Bit mask of TG1_TASK_CNT_STOP_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_STOP_TIMER0_ST_Msk = 0x100
	// Bit TG1_TASK_CNT_STOP_TIMER0_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_STOP_TIMER0_ST = 0x100
	// Position of TG1_TASK_CNT_RELOAD_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_RELOAD_TIMER0_ST_Pos = 0x9
	// Bit mask of TG1_TASK_CNT_RELOAD_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_RELOAD_TIMER0_ST_Msk = 0x200
	// Bit TG1_TASK_CNT_RELOAD_TIMER0_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_RELOAD_TIMER0_ST = 0x200
	// Position of TG1_TASK_CNT_CAP_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_CAP_TIMER0_ST_Pos = 0xa
	// Bit mask of TG1_TASK_CNT_CAP_TIMER0_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_CAP_TIMER0_ST_Msk = 0x400
	// Bit TG1_TASK_CNT_CAP_TIMER0_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_CAP_TIMER0_ST = 0x400
	// Position of TG1_TASK_CNT_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_START_TIMER1_ST_Pos = 0xb
	// Bit mask of TG1_TASK_CNT_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_START_TIMER1_ST_Msk = 0x800
	// Bit TG1_TASK_CNT_START_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_START_TIMER1_ST = 0x800
	// Position of TG1_TASK_ALARM_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_ALARM_START_TIMER1_ST_Pos = 0xc
	// Bit mask of TG1_TASK_ALARM_START_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_ALARM_START_TIMER1_ST_Msk = 0x1000
	// Bit TG1_TASK_ALARM_START_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_ALARM_START_TIMER1_ST = 0x1000
	// Position of TG1_TASK_CNT_STOP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_STOP_TIMER1_ST_Pos = 0xd
	// Bit mask of TG1_TASK_CNT_STOP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_STOP_TIMER1_ST_Msk = 0x2000
	// Bit TG1_TASK_CNT_STOP_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_STOP_TIMER1_ST = 0x2000
	// Position of TG1_TASK_CNT_RELOAD_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_RELOAD_TIMER1_ST_Pos = 0xe
	// Bit mask of TG1_TASK_CNT_RELOAD_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_RELOAD_TIMER1_ST_Msk = 0x4000
	// Bit TG1_TASK_CNT_RELOAD_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_RELOAD_TIMER1_ST = 0x4000
	// Position of TG1_TASK_CNT_CAP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_CAP_TIMER1_ST_Pos = 0xf
	// Bit mask of TG1_TASK_CNT_CAP_TIMER1_ST field.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_CAP_TIMER1_ST_Msk = 0x8000
	// Bit TG1_TASK_CNT_CAP_TIMER1_ST.
	SOC_ETM_TASK_ST3_TG1_TASK_CNT_CAP_TIMER1_ST = 0x8000
	// Position of MCPWM0_TASK_CMPR0_A_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR0_A_UP_ST_Pos = 0x10
	// Bit mask of MCPWM0_TASK_CMPR0_A_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR0_A_UP_ST_Msk = 0x10000
	// Bit MCPWM0_TASK_CMPR0_A_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR0_A_UP_ST = 0x10000
	// Position of MCPWM0_TASK_CMPR1_A_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR1_A_UP_ST_Pos = 0x11
	// Bit mask of MCPWM0_TASK_CMPR1_A_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR1_A_UP_ST_Msk = 0x20000
	// Bit MCPWM0_TASK_CMPR1_A_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR1_A_UP_ST = 0x20000
	// Position of MCPWM0_TASK_CMPR2_A_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR2_A_UP_ST_Pos = 0x12
	// Bit mask of MCPWM0_TASK_CMPR2_A_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR2_A_UP_ST_Msk = 0x40000
	// Bit MCPWM0_TASK_CMPR2_A_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR2_A_UP_ST = 0x40000
	// Position of MCPWM0_TASK_CMPR0_B_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR0_B_UP_ST_Pos = 0x13
	// Bit mask of MCPWM0_TASK_CMPR0_B_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR0_B_UP_ST_Msk = 0x80000
	// Bit MCPWM0_TASK_CMPR0_B_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR0_B_UP_ST = 0x80000
	// Position of MCPWM0_TASK_CMPR1_B_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR1_B_UP_ST_Pos = 0x14
	// Bit mask of MCPWM0_TASK_CMPR1_B_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR1_B_UP_ST_Msk = 0x100000
	// Bit MCPWM0_TASK_CMPR1_B_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR1_B_UP_ST = 0x100000
	// Position of MCPWM0_TASK_CMPR2_B_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR2_B_UP_ST_Pos = 0x15
	// Bit mask of MCPWM0_TASK_CMPR2_B_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR2_B_UP_ST_Msk = 0x200000
	// Bit MCPWM0_TASK_CMPR2_B_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_CMPR2_B_UP_ST = 0x200000
	// Position of MCPWM0_TASK_GEN_STOP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_GEN_STOP_ST_Pos = 0x16
	// Bit mask of MCPWM0_TASK_GEN_STOP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_GEN_STOP_ST_Msk = 0x400000
	// Bit MCPWM0_TASK_GEN_STOP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_GEN_STOP_ST = 0x400000
	// Position of MCPWM0_TASK_TIMER0_SYN_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER0_SYN_ST_Pos = 0x17
	// Bit mask of MCPWM0_TASK_TIMER0_SYN_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER0_SYN_ST_Msk = 0x800000
	// Bit MCPWM0_TASK_TIMER0_SYN_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER0_SYN_ST = 0x800000
	// Position of MCPWM0_TASK_TIMER1_SYN_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER1_SYN_ST_Pos = 0x18
	// Bit mask of MCPWM0_TASK_TIMER1_SYN_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER1_SYN_ST_Msk = 0x1000000
	// Bit MCPWM0_TASK_TIMER1_SYN_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER1_SYN_ST = 0x1000000
	// Position of MCPWM0_TASK_TIMER2_SYN_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER2_SYN_ST_Pos = 0x19
	// Bit mask of MCPWM0_TASK_TIMER2_SYN_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER2_SYN_ST_Msk = 0x2000000
	// Bit MCPWM0_TASK_TIMER2_SYN_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER2_SYN_ST = 0x2000000
	// Position of MCPWM0_TASK_TIMER0_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_Pos = 0x1a
	// Bit mask of MCPWM0_TASK_TIMER0_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_Msk = 0x4000000
	// Bit MCPWM0_TASK_TIMER0_PERIOD_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER0_PERIOD_UP_ST = 0x4000000
	// Position of MCPWM0_TASK_TIMER1_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_Pos = 0x1b
	// Bit mask of MCPWM0_TASK_TIMER1_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_Msk = 0x8000000
	// Bit MCPWM0_TASK_TIMER1_PERIOD_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER1_PERIOD_UP_ST = 0x8000000
	// Position of MCPWM0_TASK_TIMER2_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_Pos = 0x1c
	// Bit mask of MCPWM0_TASK_TIMER2_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_Msk = 0x10000000
	// Bit MCPWM0_TASK_TIMER2_PERIOD_UP_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TIMER2_PERIOD_UP_ST = 0x10000000
	// Position of MCPWM0_TASK_TZ0_OST_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ0_OST_ST_Pos = 0x1d
	// Bit mask of MCPWM0_TASK_TZ0_OST_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ0_OST_ST_Msk = 0x20000000
	// Bit MCPWM0_TASK_TZ0_OST_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ0_OST_ST = 0x20000000
	// Position of MCPWM0_TASK_TZ1_OST_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ1_OST_ST_Pos = 0x1e
	// Bit mask of MCPWM0_TASK_TZ1_OST_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ1_OST_ST_Msk = 0x40000000
	// Bit MCPWM0_TASK_TZ1_OST_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ1_OST_ST = 0x40000000
	// Position of MCPWM0_TASK_TZ2_OST_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ2_OST_ST_Pos = 0x1f
	// Bit mask of MCPWM0_TASK_TZ2_OST_ST field.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ2_OST_ST_Msk = 0x80000000
	// Bit MCPWM0_TASK_TZ2_OST_ST.
	SOC_ETM_TASK_ST3_MCPWM0_TASK_TZ2_OST_ST = 0x80000000

	// TASK_ST3_CLR: Tasks trigger status clear register
	// Position of TG0_TASK_CNT_CAP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_Pos = 0x0
	// Bit mask of TG0_TASK_CNT_CAP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_Msk = 0x1
	// Bit TG0_TASK_CNT_CAP_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER0_ST_CLR = 0x1
	// Position of TG0_TASK_CNT_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_START_TIMER1_ST_CLR_Pos = 0x1
	// Bit mask of TG0_TASK_CNT_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_START_TIMER1_ST_CLR_Msk = 0x2
	// Bit TG0_TASK_CNT_START_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_START_TIMER1_ST_CLR = 0x2
	// Position of TG0_TASK_ALARM_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_ALARM_START_TIMER1_ST_CLR_Pos = 0x2
	// Bit mask of TG0_TASK_ALARM_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_ALARM_START_TIMER1_ST_CLR_Msk = 0x4
	// Bit TG0_TASK_ALARM_START_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_ALARM_START_TIMER1_ST_CLR = 0x4
	// Position of TG0_TASK_CNT_STOP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_Pos = 0x3
	// Bit mask of TG0_TASK_CNT_STOP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_Msk = 0x8
	// Bit TG0_TASK_CNT_STOP_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_STOP_TIMER1_ST_CLR = 0x8
	// Position of TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_Pos = 0x4
	// Bit mask of TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_Msk = 0x10
	// Bit TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR = 0x10
	// Position of TG0_TASK_CNT_CAP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_Pos = 0x5
	// Bit mask of TG0_TASK_CNT_CAP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_Msk = 0x20
	// Bit TG0_TASK_CNT_CAP_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG0_TASK_CNT_CAP_TIMER1_ST_CLR = 0x20
	// Position of TG1_TASK_CNT_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_START_TIMER0_ST_CLR_Pos = 0x6
	// Bit mask of TG1_TASK_CNT_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_START_TIMER0_ST_CLR_Msk = 0x40
	// Bit TG1_TASK_CNT_START_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_START_TIMER0_ST_CLR = 0x40
	// Position of TG1_TASK_ALARM_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER0_ST_CLR_Pos = 0x7
	// Bit mask of TG1_TASK_ALARM_START_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER0_ST_CLR_Msk = 0x80
	// Bit TG1_TASK_ALARM_START_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER0_ST_CLR = 0x80
	// Position of TG1_TASK_CNT_STOP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_Pos = 0x8
	// Bit mask of TG1_TASK_CNT_STOP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_Msk = 0x100
	// Bit TG1_TASK_CNT_STOP_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER0_ST_CLR = 0x100
	// Position of TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_Pos = 0x9
	// Bit mask of TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_Msk = 0x200
	// Bit TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR = 0x200
	// Position of TG1_TASK_CNT_CAP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_Pos = 0xa
	// Bit mask of TG1_TASK_CNT_CAP_TIMER0_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_Msk = 0x400
	// Bit TG1_TASK_CNT_CAP_TIMER0_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER0_ST_CLR = 0x400
	// Position of TG1_TASK_CNT_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_START_TIMER1_ST_CLR_Pos = 0xb
	// Bit mask of TG1_TASK_CNT_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_START_TIMER1_ST_CLR_Msk = 0x800
	// Bit TG1_TASK_CNT_START_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_START_TIMER1_ST_CLR = 0x800
	// Position of TG1_TASK_ALARM_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER1_ST_CLR_Pos = 0xc
	// Bit mask of TG1_TASK_ALARM_START_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER1_ST_CLR_Msk = 0x1000
	// Bit TG1_TASK_ALARM_START_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_ALARM_START_TIMER1_ST_CLR = 0x1000
	// Position of TG1_TASK_CNT_STOP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_Pos = 0xd
	// Bit mask of TG1_TASK_CNT_STOP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_Msk = 0x2000
	// Bit TG1_TASK_CNT_STOP_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_STOP_TIMER1_ST_CLR = 0x2000
	// Position of TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_Pos = 0xe
	// Bit mask of TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_Msk = 0x4000
	// Bit TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR = 0x4000
	// Position of TG1_TASK_CNT_CAP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_Pos = 0xf
	// Bit mask of TG1_TASK_CNT_CAP_TIMER1_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_Msk = 0x8000
	// Bit TG1_TASK_CNT_CAP_TIMER1_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_TG1_TASK_CNT_CAP_TIMER1_ST_CLR = 0x8000
	// Position of MCPWM0_TASK_CMPR0_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_Pos = 0x10
	// Bit mask of MCPWM0_TASK_CMPR0_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR0_A_UP_ST_CLR_Msk = 0x10000
	// Bit MCPWM0_TASK_CMPR0_A_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR0_A_UP_ST_CLR = 0x10000
	// Position of MCPWM0_TASK_CMPR1_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_Pos = 0x11
	// Bit mask of MCPWM0_TASK_CMPR1_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR1_A_UP_ST_CLR_Msk = 0x20000
	// Bit MCPWM0_TASK_CMPR1_A_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR1_A_UP_ST_CLR = 0x20000
	// Position of MCPWM0_TASK_CMPR2_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_Pos = 0x12
	// Bit mask of MCPWM0_TASK_CMPR2_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR2_A_UP_ST_CLR_Msk = 0x40000
	// Bit MCPWM0_TASK_CMPR2_A_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR2_A_UP_ST_CLR = 0x40000
	// Position of MCPWM0_TASK_CMPR0_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_Pos = 0x13
	// Bit mask of MCPWM0_TASK_CMPR0_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR0_B_UP_ST_CLR_Msk = 0x80000
	// Bit MCPWM0_TASK_CMPR0_B_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR0_B_UP_ST_CLR = 0x80000
	// Position of MCPWM0_TASK_CMPR1_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_Pos = 0x14
	// Bit mask of MCPWM0_TASK_CMPR1_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR1_B_UP_ST_CLR_Msk = 0x100000
	// Bit MCPWM0_TASK_CMPR1_B_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR1_B_UP_ST_CLR = 0x100000
	// Position of MCPWM0_TASK_CMPR2_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_Pos = 0x15
	// Bit mask of MCPWM0_TASK_CMPR2_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR2_B_UP_ST_CLR_Msk = 0x200000
	// Bit MCPWM0_TASK_CMPR2_B_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_CMPR2_B_UP_ST_CLR = 0x200000
	// Position of MCPWM0_TASK_GEN_STOP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_GEN_STOP_ST_CLR_Pos = 0x16
	// Bit mask of MCPWM0_TASK_GEN_STOP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_GEN_STOP_ST_CLR_Msk = 0x400000
	// Bit MCPWM0_TASK_GEN_STOP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_GEN_STOP_ST_CLR = 0x400000
	// Position of MCPWM0_TASK_TIMER0_SYN_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER0_SYN_ST_CLR_Pos = 0x17
	// Bit mask of MCPWM0_TASK_TIMER0_SYN_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER0_SYN_ST_CLR_Msk = 0x800000
	// Bit MCPWM0_TASK_TIMER0_SYN_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER0_SYN_ST_CLR = 0x800000
	// Position of MCPWM0_TASK_TIMER1_SYN_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER1_SYN_ST_CLR_Pos = 0x18
	// Bit mask of MCPWM0_TASK_TIMER1_SYN_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER1_SYN_ST_CLR_Msk = 0x1000000
	// Bit MCPWM0_TASK_TIMER1_SYN_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER1_SYN_ST_CLR = 0x1000000
	// Position of MCPWM0_TASK_TIMER2_SYN_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER2_SYN_ST_CLR_Pos = 0x19
	// Bit mask of MCPWM0_TASK_TIMER2_SYN_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER2_SYN_ST_CLR_Msk = 0x2000000
	// Bit MCPWM0_TASK_TIMER2_SYN_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER2_SYN_ST_CLR = 0x2000000
	// Position of MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_Pos = 0x1a
	// Bit mask of MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_Msk = 0x4000000
	// Bit MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR = 0x4000000
	// Position of MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_Pos = 0x1b
	// Bit mask of MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_Msk = 0x8000000
	// Bit MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR = 0x8000000
	// Position of MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_Pos = 0x1c
	// Bit mask of MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_Msk = 0x10000000
	// Bit MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR = 0x10000000
	// Position of MCPWM0_TASK_TZ0_OST_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ0_OST_ST_CLR_Pos = 0x1d
	// Bit mask of MCPWM0_TASK_TZ0_OST_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ0_OST_ST_CLR_Msk = 0x20000000
	// Bit MCPWM0_TASK_TZ0_OST_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ0_OST_ST_CLR = 0x20000000
	// Position of MCPWM0_TASK_TZ1_OST_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ1_OST_ST_CLR_Pos = 0x1e
	// Bit mask of MCPWM0_TASK_TZ1_OST_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ1_OST_ST_CLR_Msk = 0x40000000
	// Bit MCPWM0_TASK_TZ1_OST_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ1_OST_ST_CLR = 0x40000000
	// Position of MCPWM0_TASK_TZ2_OST_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ2_OST_ST_CLR_Pos = 0x1f
	// Bit mask of MCPWM0_TASK_TZ2_OST_ST_CLR field.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ2_OST_ST_CLR_Msk = 0x80000000
	// Bit MCPWM0_TASK_TZ2_OST_ST_CLR.
	SOC_ETM_TASK_ST3_CLR_MCPWM0_TASK_TZ2_OST_ST_CLR = 0x80000000

	// TASK_ST4: Tasks trigger status register
	// Position of MCPWM0_TASK_CLR0_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR0_OST_ST_Pos = 0x0
	// Bit mask of MCPWM0_TASK_CLR0_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR0_OST_ST_Msk = 0x1
	// Bit MCPWM0_TASK_CLR0_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR0_OST_ST = 0x1
	// Position of MCPWM0_TASK_CLR1_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR1_OST_ST_Pos = 0x1
	// Bit mask of MCPWM0_TASK_CLR1_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR1_OST_ST_Msk = 0x2
	// Bit MCPWM0_TASK_CLR1_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR1_OST_ST = 0x2
	// Position of MCPWM0_TASK_CLR2_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR2_OST_ST_Pos = 0x2
	// Bit mask of MCPWM0_TASK_CLR2_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR2_OST_ST_Msk = 0x4
	// Bit MCPWM0_TASK_CLR2_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CLR2_OST_ST = 0x4
	// Position of MCPWM0_TASK_CAP0_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP0_ST_Pos = 0x3
	// Bit mask of MCPWM0_TASK_CAP0_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP0_ST_Msk = 0x8
	// Bit MCPWM0_TASK_CAP0_ST.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP0_ST = 0x8
	// Position of MCPWM0_TASK_CAP1_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP1_ST_Pos = 0x4
	// Bit mask of MCPWM0_TASK_CAP1_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP1_ST_Msk = 0x10
	// Bit MCPWM0_TASK_CAP1_ST.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP1_ST = 0x10
	// Position of MCPWM0_TASK_CAP2_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP2_ST_Pos = 0x5
	// Bit mask of MCPWM0_TASK_CAP2_ST field.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP2_ST_Msk = 0x20
	// Bit MCPWM0_TASK_CAP2_ST.
	SOC_ETM_TASK_ST4_MCPWM0_TASK_CAP2_ST = 0x20
	// Position of MCPWM1_TASK_CMPR0_A_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR0_A_UP_ST_Pos = 0x6
	// Bit mask of MCPWM1_TASK_CMPR0_A_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR0_A_UP_ST_Msk = 0x40
	// Bit MCPWM1_TASK_CMPR0_A_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR0_A_UP_ST = 0x40
	// Position of MCPWM1_TASK_CMPR1_A_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR1_A_UP_ST_Pos = 0x7
	// Bit mask of MCPWM1_TASK_CMPR1_A_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR1_A_UP_ST_Msk = 0x80
	// Bit MCPWM1_TASK_CMPR1_A_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR1_A_UP_ST = 0x80
	// Position of MCPWM1_TASK_CMPR2_A_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR2_A_UP_ST_Pos = 0x8
	// Bit mask of MCPWM1_TASK_CMPR2_A_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR2_A_UP_ST_Msk = 0x100
	// Bit MCPWM1_TASK_CMPR2_A_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR2_A_UP_ST = 0x100
	// Position of MCPWM1_TASK_CMPR0_B_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR0_B_UP_ST_Pos = 0x9
	// Bit mask of MCPWM1_TASK_CMPR0_B_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR0_B_UP_ST_Msk = 0x200
	// Bit MCPWM1_TASK_CMPR0_B_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR0_B_UP_ST = 0x200
	// Position of MCPWM1_TASK_CMPR1_B_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR1_B_UP_ST_Pos = 0xa
	// Bit mask of MCPWM1_TASK_CMPR1_B_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR1_B_UP_ST_Msk = 0x400
	// Bit MCPWM1_TASK_CMPR1_B_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR1_B_UP_ST = 0x400
	// Position of MCPWM1_TASK_CMPR2_B_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR2_B_UP_ST_Pos = 0xb
	// Bit mask of MCPWM1_TASK_CMPR2_B_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR2_B_UP_ST_Msk = 0x800
	// Bit MCPWM1_TASK_CMPR2_B_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CMPR2_B_UP_ST = 0x800
	// Position of MCPWM1_TASK_GEN_STOP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_GEN_STOP_ST_Pos = 0xc
	// Bit mask of MCPWM1_TASK_GEN_STOP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_GEN_STOP_ST_Msk = 0x1000
	// Bit MCPWM1_TASK_GEN_STOP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_GEN_STOP_ST = 0x1000
	// Position of MCPWM1_TASK_TIMER0_SYN_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER0_SYN_ST_Pos = 0xd
	// Bit mask of MCPWM1_TASK_TIMER0_SYN_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER0_SYN_ST_Msk = 0x2000
	// Bit MCPWM1_TASK_TIMER0_SYN_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER0_SYN_ST = 0x2000
	// Position of MCPWM1_TASK_TIMER1_SYN_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER1_SYN_ST_Pos = 0xe
	// Bit mask of MCPWM1_TASK_TIMER1_SYN_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER1_SYN_ST_Msk = 0x4000
	// Bit MCPWM1_TASK_TIMER1_SYN_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER1_SYN_ST = 0x4000
	// Position of MCPWM1_TASK_TIMER2_SYN_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER2_SYN_ST_Pos = 0xf
	// Bit mask of MCPWM1_TASK_TIMER2_SYN_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER2_SYN_ST_Msk = 0x8000
	// Bit MCPWM1_TASK_TIMER2_SYN_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER2_SYN_ST = 0x8000
	// Position of MCPWM1_TASK_TIMER0_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_Pos = 0x10
	// Bit mask of MCPWM1_TASK_TIMER0_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_Msk = 0x10000
	// Bit MCPWM1_TASK_TIMER0_PERIOD_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER0_PERIOD_UP_ST = 0x10000
	// Position of MCPWM1_TASK_TIMER1_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_Pos = 0x11
	// Bit mask of MCPWM1_TASK_TIMER1_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_Msk = 0x20000
	// Bit MCPWM1_TASK_TIMER1_PERIOD_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER1_PERIOD_UP_ST = 0x20000
	// Position of MCPWM1_TASK_TIMER2_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_Pos = 0x12
	// Bit mask of MCPWM1_TASK_TIMER2_PERIOD_UP_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_Msk = 0x40000
	// Bit MCPWM1_TASK_TIMER2_PERIOD_UP_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TIMER2_PERIOD_UP_ST = 0x40000
	// Position of MCPWM1_TASK_TZ0_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ0_OST_ST_Pos = 0x13
	// Bit mask of MCPWM1_TASK_TZ0_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ0_OST_ST_Msk = 0x80000
	// Bit MCPWM1_TASK_TZ0_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ0_OST_ST = 0x80000
	// Position of MCPWM1_TASK_TZ1_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ1_OST_ST_Pos = 0x14
	// Bit mask of MCPWM1_TASK_TZ1_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ1_OST_ST_Msk = 0x100000
	// Bit MCPWM1_TASK_TZ1_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ1_OST_ST = 0x100000
	// Position of MCPWM1_TASK_TZ2_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ2_OST_ST_Pos = 0x15
	// Bit mask of MCPWM1_TASK_TZ2_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ2_OST_ST_Msk = 0x200000
	// Bit MCPWM1_TASK_TZ2_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_TZ2_OST_ST = 0x200000
	// Position of MCPWM1_TASK_CLR0_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR0_OST_ST_Pos = 0x16
	// Bit mask of MCPWM1_TASK_CLR0_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR0_OST_ST_Msk = 0x400000
	// Bit MCPWM1_TASK_CLR0_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR0_OST_ST = 0x400000
	// Position of MCPWM1_TASK_CLR1_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR1_OST_ST_Pos = 0x17
	// Bit mask of MCPWM1_TASK_CLR1_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR1_OST_ST_Msk = 0x800000
	// Bit MCPWM1_TASK_CLR1_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR1_OST_ST = 0x800000
	// Position of MCPWM1_TASK_CLR2_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR2_OST_ST_Pos = 0x18
	// Bit mask of MCPWM1_TASK_CLR2_OST_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR2_OST_ST_Msk = 0x1000000
	// Bit MCPWM1_TASK_CLR2_OST_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CLR2_OST_ST = 0x1000000
	// Position of MCPWM1_TASK_CAP0_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP0_ST_Pos = 0x19
	// Bit mask of MCPWM1_TASK_CAP0_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP0_ST_Msk = 0x2000000
	// Bit MCPWM1_TASK_CAP0_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP0_ST = 0x2000000
	// Position of MCPWM1_TASK_CAP1_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP1_ST_Pos = 0x1a
	// Bit mask of MCPWM1_TASK_CAP1_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP1_ST_Msk = 0x4000000
	// Bit MCPWM1_TASK_CAP1_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP1_ST = 0x4000000
	// Position of MCPWM1_TASK_CAP2_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP2_ST_Pos = 0x1b
	// Bit mask of MCPWM1_TASK_CAP2_ST field.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP2_ST_Msk = 0x8000000
	// Bit MCPWM1_TASK_CAP2_ST.
	SOC_ETM_TASK_ST4_MCPWM1_TASK_CAP2_ST = 0x8000000
	// Position of ADC_TASK_SAMPLE0_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_SAMPLE0_ST_Pos = 0x1c
	// Bit mask of ADC_TASK_SAMPLE0_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_SAMPLE0_ST_Msk = 0x10000000
	// Bit ADC_TASK_SAMPLE0_ST.
	SOC_ETM_TASK_ST4_ADC_TASK_SAMPLE0_ST = 0x10000000
	// Position of ADC_TASK_SAMPLE1_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_SAMPLE1_ST_Pos = 0x1d
	// Bit mask of ADC_TASK_SAMPLE1_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_SAMPLE1_ST_Msk = 0x20000000
	// Bit ADC_TASK_SAMPLE1_ST.
	SOC_ETM_TASK_ST4_ADC_TASK_SAMPLE1_ST = 0x20000000
	// Position of ADC_TASK_START0_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_START0_ST_Pos = 0x1e
	// Bit mask of ADC_TASK_START0_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_START0_ST_Msk = 0x40000000
	// Bit ADC_TASK_START0_ST.
	SOC_ETM_TASK_ST4_ADC_TASK_START0_ST = 0x40000000
	// Position of ADC_TASK_STOP0_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_STOP0_ST_Pos = 0x1f
	// Bit mask of ADC_TASK_STOP0_ST field.
	SOC_ETM_TASK_ST4_ADC_TASK_STOP0_ST_Msk = 0x80000000
	// Bit ADC_TASK_STOP0_ST.
	SOC_ETM_TASK_ST4_ADC_TASK_STOP0_ST = 0x80000000

	// TASK_ST4_CLR: Tasks trigger status clear register
	// Position of MCPWM0_TASK_CLR0_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR0_OST_ST_CLR_Pos = 0x0
	// Bit mask of MCPWM0_TASK_CLR0_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR0_OST_ST_CLR_Msk = 0x1
	// Bit MCPWM0_TASK_CLR0_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR0_OST_ST_CLR = 0x1
	// Position of MCPWM0_TASK_CLR1_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR1_OST_ST_CLR_Pos = 0x1
	// Bit mask of MCPWM0_TASK_CLR1_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR1_OST_ST_CLR_Msk = 0x2
	// Bit MCPWM0_TASK_CLR1_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR1_OST_ST_CLR = 0x2
	// Position of MCPWM0_TASK_CLR2_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR2_OST_ST_CLR_Pos = 0x2
	// Bit mask of MCPWM0_TASK_CLR2_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR2_OST_ST_CLR_Msk = 0x4
	// Bit MCPWM0_TASK_CLR2_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CLR2_OST_ST_CLR = 0x4
	// Position of MCPWM0_TASK_CAP0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP0_ST_CLR_Pos = 0x3
	// Bit mask of MCPWM0_TASK_CAP0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP0_ST_CLR_Msk = 0x8
	// Bit MCPWM0_TASK_CAP0_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP0_ST_CLR = 0x8
	// Position of MCPWM0_TASK_CAP1_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP1_ST_CLR_Pos = 0x4
	// Bit mask of MCPWM0_TASK_CAP1_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP1_ST_CLR_Msk = 0x10
	// Bit MCPWM0_TASK_CAP1_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP1_ST_CLR = 0x10
	// Position of MCPWM0_TASK_CAP2_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP2_ST_CLR_Pos = 0x5
	// Bit mask of MCPWM0_TASK_CAP2_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP2_ST_CLR_Msk = 0x20
	// Bit MCPWM0_TASK_CAP2_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM0_TASK_CAP2_ST_CLR = 0x20
	// Position of MCPWM1_TASK_CMPR0_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_Pos = 0x6
	// Bit mask of MCPWM1_TASK_CMPR0_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR0_A_UP_ST_CLR_Msk = 0x40
	// Bit MCPWM1_TASK_CMPR0_A_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR0_A_UP_ST_CLR = 0x40
	// Position of MCPWM1_TASK_CMPR1_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_Pos = 0x7
	// Bit mask of MCPWM1_TASK_CMPR1_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR1_A_UP_ST_CLR_Msk = 0x80
	// Bit MCPWM1_TASK_CMPR1_A_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR1_A_UP_ST_CLR = 0x80
	// Position of MCPWM1_TASK_CMPR2_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_Pos = 0x8
	// Bit mask of MCPWM1_TASK_CMPR2_A_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR2_A_UP_ST_CLR_Msk = 0x100
	// Bit MCPWM1_TASK_CMPR2_A_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR2_A_UP_ST_CLR = 0x100
	// Position of MCPWM1_TASK_CMPR0_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_Pos = 0x9
	// Bit mask of MCPWM1_TASK_CMPR0_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR0_B_UP_ST_CLR_Msk = 0x200
	// Bit MCPWM1_TASK_CMPR0_B_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR0_B_UP_ST_CLR = 0x200
	// Position of MCPWM1_TASK_CMPR1_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_Pos = 0xa
	// Bit mask of MCPWM1_TASK_CMPR1_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR1_B_UP_ST_CLR_Msk = 0x400
	// Bit MCPWM1_TASK_CMPR1_B_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR1_B_UP_ST_CLR = 0x400
	// Position of MCPWM1_TASK_CMPR2_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_Pos = 0xb
	// Bit mask of MCPWM1_TASK_CMPR2_B_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR2_B_UP_ST_CLR_Msk = 0x800
	// Bit MCPWM1_TASK_CMPR2_B_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CMPR2_B_UP_ST_CLR = 0x800
	// Position of MCPWM1_TASK_GEN_STOP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_GEN_STOP_ST_CLR_Pos = 0xc
	// Bit mask of MCPWM1_TASK_GEN_STOP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_GEN_STOP_ST_CLR_Msk = 0x1000
	// Bit MCPWM1_TASK_GEN_STOP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_GEN_STOP_ST_CLR = 0x1000
	// Position of MCPWM1_TASK_TIMER0_SYN_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER0_SYN_ST_CLR_Pos = 0xd
	// Bit mask of MCPWM1_TASK_TIMER0_SYN_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER0_SYN_ST_CLR_Msk = 0x2000
	// Bit MCPWM1_TASK_TIMER0_SYN_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER0_SYN_ST_CLR = 0x2000
	// Position of MCPWM1_TASK_TIMER1_SYN_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER1_SYN_ST_CLR_Pos = 0xe
	// Bit mask of MCPWM1_TASK_TIMER1_SYN_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER1_SYN_ST_CLR_Msk = 0x4000
	// Bit MCPWM1_TASK_TIMER1_SYN_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER1_SYN_ST_CLR = 0x4000
	// Position of MCPWM1_TASK_TIMER2_SYN_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER2_SYN_ST_CLR_Pos = 0xf
	// Bit mask of MCPWM1_TASK_TIMER2_SYN_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER2_SYN_ST_CLR_Msk = 0x8000
	// Bit MCPWM1_TASK_TIMER2_SYN_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER2_SYN_ST_CLR = 0x8000
	// Position of MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_Pos = 0x10
	// Bit mask of MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_Msk = 0x10000
	// Bit MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR = 0x10000
	// Position of MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_Pos = 0x11
	// Bit mask of MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_Msk = 0x20000
	// Bit MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR = 0x20000
	// Position of MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_Pos = 0x12
	// Bit mask of MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_Msk = 0x40000
	// Bit MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR = 0x40000
	// Position of MCPWM1_TASK_TZ0_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ0_OST_ST_CLR_Pos = 0x13
	// Bit mask of MCPWM1_TASK_TZ0_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ0_OST_ST_CLR_Msk = 0x80000
	// Bit MCPWM1_TASK_TZ0_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ0_OST_ST_CLR = 0x80000
	// Position of MCPWM1_TASK_TZ1_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ1_OST_ST_CLR_Pos = 0x14
	// Bit mask of MCPWM1_TASK_TZ1_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ1_OST_ST_CLR_Msk = 0x100000
	// Bit MCPWM1_TASK_TZ1_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ1_OST_ST_CLR = 0x100000
	// Position of MCPWM1_TASK_TZ2_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ2_OST_ST_CLR_Pos = 0x15
	// Bit mask of MCPWM1_TASK_TZ2_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ2_OST_ST_CLR_Msk = 0x200000
	// Bit MCPWM1_TASK_TZ2_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_TZ2_OST_ST_CLR = 0x200000
	// Position of MCPWM1_TASK_CLR0_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR0_OST_ST_CLR_Pos = 0x16
	// Bit mask of MCPWM1_TASK_CLR0_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR0_OST_ST_CLR_Msk = 0x400000
	// Bit MCPWM1_TASK_CLR0_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR0_OST_ST_CLR = 0x400000
	// Position of MCPWM1_TASK_CLR1_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR1_OST_ST_CLR_Pos = 0x17
	// Bit mask of MCPWM1_TASK_CLR1_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR1_OST_ST_CLR_Msk = 0x800000
	// Bit MCPWM1_TASK_CLR1_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR1_OST_ST_CLR = 0x800000
	// Position of MCPWM1_TASK_CLR2_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR2_OST_ST_CLR_Pos = 0x18
	// Bit mask of MCPWM1_TASK_CLR2_OST_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR2_OST_ST_CLR_Msk = 0x1000000
	// Bit MCPWM1_TASK_CLR2_OST_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CLR2_OST_ST_CLR = 0x1000000
	// Position of MCPWM1_TASK_CAP0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP0_ST_CLR_Pos = 0x19
	// Bit mask of MCPWM1_TASK_CAP0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP0_ST_CLR_Msk = 0x2000000
	// Bit MCPWM1_TASK_CAP0_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP0_ST_CLR = 0x2000000
	// Position of MCPWM1_TASK_CAP1_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP1_ST_CLR_Pos = 0x1a
	// Bit mask of MCPWM1_TASK_CAP1_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP1_ST_CLR_Msk = 0x4000000
	// Bit MCPWM1_TASK_CAP1_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP1_ST_CLR = 0x4000000
	// Position of MCPWM1_TASK_CAP2_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP2_ST_CLR_Pos = 0x1b
	// Bit mask of MCPWM1_TASK_CAP2_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP2_ST_CLR_Msk = 0x8000000
	// Bit MCPWM1_TASK_CAP2_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_MCPWM1_TASK_CAP2_ST_CLR = 0x8000000
	// Position of ADC_TASK_SAMPLE0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_SAMPLE0_ST_CLR_Pos = 0x1c
	// Bit mask of ADC_TASK_SAMPLE0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_SAMPLE0_ST_CLR_Msk = 0x10000000
	// Bit ADC_TASK_SAMPLE0_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_SAMPLE0_ST_CLR = 0x10000000
	// Position of ADC_TASK_SAMPLE1_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_SAMPLE1_ST_CLR_Pos = 0x1d
	// Bit mask of ADC_TASK_SAMPLE1_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_SAMPLE1_ST_CLR_Msk = 0x20000000
	// Bit ADC_TASK_SAMPLE1_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_SAMPLE1_ST_CLR = 0x20000000
	// Position of ADC_TASK_START0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_START0_ST_CLR_Pos = 0x1e
	// Bit mask of ADC_TASK_START0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_START0_ST_CLR_Msk = 0x40000000
	// Bit ADC_TASK_START0_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_START0_ST_CLR = 0x40000000
	// Position of ADC_TASK_STOP0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_STOP0_ST_CLR_Pos = 0x1f
	// Bit mask of ADC_TASK_STOP0_ST_CLR field.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_STOP0_ST_CLR_Msk = 0x80000000
	// Bit ADC_TASK_STOP0_ST_CLR.
	SOC_ETM_TASK_ST4_CLR_ADC_TASK_STOP0_ST_CLR = 0x80000000

	// TASK_ST5: Tasks trigger status register
	// Position of REGDMA_TASK_START0_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START0_ST_Pos = 0x0
	// Bit mask of REGDMA_TASK_START0_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START0_ST_Msk = 0x1
	// Bit REGDMA_TASK_START0_ST.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START0_ST = 0x1
	// Position of REGDMA_TASK_START1_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START1_ST_Pos = 0x1
	// Bit mask of REGDMA_TASK_START1_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START1_ST_Msk = 0x2
	// Bit REGDMA_TASK_START1_ST.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START1_ST = 0x2
	// Position of REGDMA_TASK_START2_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START2_ST_Pos = 0x2
	// Bit mask of REGDMA_TASK_START2_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START2_ST_Msk = 0x4
	// Bit REGDMA_TASK_START2_ST.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START2_ST = 0x4
	// Position of REGDMA_TASK_START3_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START3_ST_Pos = 0x3
	// Bit mask of REGDMA_TASK_START3_ST field.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START3_ST_Msk = 0x8
	// Bit REGDMA_TASK_START3_ST.
	SOC_ETM_TASK_ST5_REGDMA_TASK_START3_ST = 0x8
	// Position of TMPSNSR_TASK_START_SAMPLE_ST field.
	SOC_ETM_TASK_ST5_TMPSNSR_TASK_START_SAMPLE_ST_Pos = 0x4
	// Bit mask of TMPSNSR_TASK_START_SAMPLE_ST field.
	SOC_ETM_TASK_ST5_TMPSNSR_TASK_START_SAMPLE_ST_Msk = 0x10
	// Bit TMPSNSR_TASK_START_SAMPLE_ST.
	SOC_ETM_TASK_ST5_TMPSNSR_TASK_START_SAMPLE_ST = 0x10
	// Position of TMPSNSR_TASK_STOP_SAMPLE_ST field.
	SOC_ETM_TASK_ST5_TMPSNSR_TASK_STOP_SAMPLE_ST_Pos = 0x5
	// Bit mask of TMPSNSR_TASK_STOP_SAMPLE_ST field.
	SOC_ETM_TASK_ST5_TMPSNSR_TASK_STOP_SAMPLE_ST_Msk = 0x20
	// Bit TMPSNSR_TASK_STOP_SAMPLE_ST.
	SOC_ETM_TASK_ST5_TMPSNSR_TASK_STOP_SAMPLE_ST = 0x20
	// Position of I2S0_TASK_START_RX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_START_RX_ST_Pos = 0x6
	// Bit mask of I2S0_TASK_START_RX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_START_RX_ST_Msk = 0x40
	// Bit I2S0_TASK_START_RX_ST.
	SOC_ETM_TASK_ST5_I2S0_TASK_START_RX_ST = 0x40
	// Position of I2S0_TASK_START_TX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_START_TX_ST_Pos = 0x7
	// Bit mask of I2S0_TASK_START_TX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_START_TX_ST_Msk = 0x80
	// Bit I2S0_TASK_START_TX_ST.
	SOC_ETM_TASK_ST5_I2S0_TASK_START_TX_ST = 0x80
	// Position of I2S0_TASK_STOP_RX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_STOP_RX_ST_Pos = 0x8
	// Bit mask of I2S0_TASK_STOP_RX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_STOP_RX_ST_Msk = 0x100
	// Bit I2S0_TASK_STOP_RX_ST.
	SOC_ETM_TASK_ST5_I2S0_TASK_STOP_RX_ST = 0x100
	// Position of I2S0_TASK_STOP_TX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_STOP_TX_ST_Pos = 0x9
	// Bit mask of I2S0_TASK_STOP_TX_ST field.
	SOC_ETM_TASK_ST5_I2S0_TASK_STOP_TX_ST_Msk = 0x200
	// Bit I2S0_TASK_STOP_TX_ST.
	SOC_ETM_TASK_ST5_I2S0_TASK_STOP_TX_ST = 0x200
	// Position of I2S1_TASK_START_RX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_START_RX_ST_Pos = 0xa
	// Bit mask of I2S1_TASK_START_RX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_START_RX_ST_Msk = 0x400
	// Bit I2S1_TASK_START_RX_ST.
	SOC_ETM_TASK_ST5_I2S1_TASK_START_RX_ST = 0x400
	// Position of I2S1_TASK_START_TX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_START_TX_ST_Pos = 0xb
	// Bit mask of I2S1_TASK_START_TX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_START_TX_ST_Msk = 0x800
	// Bit I2S1_TASK_START_TX_ST.
	SOC_ETM_TASK_ST5_I2S1_TASK_START_TX_ST = 0x800
	// Position of I2S1_TASK_STOP_RX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_STOP_RX_ST_Pos = 0xc
	// Bit mask of I2S1_TASK_STOP_RX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_STOP_RX_ST_Msk = 0x1000
	// Bit I2S1_TASK_STOP_RX_ST.
	SOC_ETM_TASK_ST5_I2S1_TASK_STOP_RX_ST = 0x1000
	// Position of I2S1_TASK_STOP_TX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_STOP_TX_ST_Pos = 0xd
	// Bit mask of I2S1_TASK_STOP_TX_ST field.
	SOC_ETM_TASK_ST5_I2S1_TASK_STOP_TX_ST_Msk = 0x2000
	// Bit I2S1_TASK_STOP_TX_ST.
	SOC_ETM_TASK_ST5_I2S1_TASK_STOP_TX_ST = 0x2000
	// Position of I2S2_TASK_START_RX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_START_RX_ST_Pos = 0xe
	// Bit mask of I2S2_TASK_START_RX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_START_RX_ST_Msk = 0x4000
	// Bit I2S2_TASK_START_RX_ST.
	SOC_ETM_TASK_ST5_I2S2_TASK_START_RX_ST = 0x4000
	// Position of I2S2_TASK_START_TX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_START_TX_ST_Pos = 0xf
	// Bit mask of I2S2_TASK_START_TX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_START_TX_ST_Msk = 0x8000
	// Bit I2S2_TASK_START_TX_ST.
	SOC_ETM_TASK_ST5_I2S2_TASK_START_TX_ST = 0x8000
	// Position of I2S2_TASK_STOP_RX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_STOP_RX_ST_Pos = 0x10
	// Bit mask of I2S2_TASK_STOP_RX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_STOP_RX_ST_Msk = 0x10000
	// Bit I2S2_TASK_STOP_RX_ST.
	SOC_ETM_TASK_ST5_I2S2_TASK_STOP_RX_ST = 0x10000
	// Position of I2S2_TASK_STOP_TX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_STOP_TX_ST_Pos = 0x11
	// Bit mask of I2S2_TASK_STOP_TX_ST field.
	SOC_ETM_TASK_ST5_I2S2_TASK_STOP_TX_ST_Msk = 0x20000
	// Bit I2S2_TASK_STOP_TX_ST.
	SOC_ETM_TASK_ST5_I2S2_TASK_STOP_TX_ST = 0x20000
	// Position of ULP_TASK_WAKEUP_CPU_ST field.
	SOC_ETM_TASK_ST5_ULP_TASK_WAKEUP_CPU_ST_Pos = 0x12
	// Bit mask of ULP_TASK_WAKEUP_CPU_ST field.
	SOC_ETM_TASK_ST5_ULP_TASK_WAKEUP_CPU_ST_Msk = 0x40000
	// Bit ULP_TASK_WAKEUP_CPU_ST.
	SOC_ETM_TASK_ST5_ULP_TASK_WAKEUP_CPU_ST = 0x40000
	// Position of ULP_TASK_INT_CPU_ST field.
	SOC_ETM_TASK_ST5_ULP_TASK_INT_CPU_ST_Pos = 0x13
	// Bit mask of ULP_TASK_INT_CPU_ST field.
	SOC_ETM_TASK_ST5_ULP_TASK_INT_CPU_ST_Msk = 0x80000
	// Bit ULP_TASK_INT_CPU_ST.
	SOC_ETM_TASK_ST5_ULP_TASK_INT_CPU_ST = 0x80000
	// Position of RTC_TASK_START_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_START_ST_Pos = 0x14
	// Bit mask of RTC_TASK_START_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_START_ST_Msk = 0x100000
	// Bit RTC_TASK_START_ST.
	SOC_ETM_TASK_ST5_RTC_TASK_START_ST = 0x100000
	// Position of RTC_TASK_STOP_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_STOP_ST_Pos = 0x15
	// Bit mask of RTC_TASK_STOP_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_STOP_ST_Msk = 0x200000
	// Bit RTC_TASK_STOP_ST.
	SOC_ETM_TASK_ST5_RTC_TASK_STOP_ST = 0x200000
	// Position of RTC_TASK_CLR_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_CLR_ST_Pos = 0x16
	// Bit mask of RTC_TASK_CLR_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_CLR_ST_Msk = 0x400000
	// Bit RTC_TASK_CLR_ST.
	SOC_ETM_TASK_ST5_RTC_TASK_CLR_ST = 0x400000
	// Position of RTC_TASK_TRIGGERFLW_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_TRIGGERFLW_ST_Pos = 0x17
	// Bit mask of RTC_TASK_TRIGGERFLW_ST field.
	SOC_ETM_TASK_ST5_RTC_TASK_TRIGGERFLW_ST_Msk = 0x800000
	// Bit RTC_TASK_TRIGGERFLW_ST.
	SOC_ETM_TASK_ST5_RTC_TASK_TRIGGERFLW_ST = 0x800000
	// Position of PDMA_AHB_TASK_IN_START_CH0_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH0_ST_Pos = 0x18
	// Bit mask of PDMA_AHB_TASK_IN_START_CH0_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH0_ST_Msk = 0x1000000
	// Bit PDMA_AHB_TASK_IN_START_CH0_ST.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH0_ST = 0x1000000
	// Position of PDMA_AHB_TASK_IN_START_CH1_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH1_ST_Pos = 0x19
	// Bit mask of PDMA_AHB_TASK_IN_START_CH1_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH1_ST_Msk = 0x2000000
	// Bit PDMA_AHB_TASK_IN_START_CH1_ST.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH1_ST = 0x2000000
	// Position of PDMA_AHB_TASK_IN_START_CH2_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH2_ST_Pos = 0x1a
	// Bit mask of PDMA_AHB_TASK_IN_START_CH2_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH2_ST_Msk = 0x4000000
	// Bit PDMA_AHB_TASK_IN_START_CH2_ST.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_IN_START_CH2_ST = 0x4000000
	// Position of PDMA_AHB_TASK_OUT_START_CH0_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH0_ST_Pos = 0x1b
	// Bit mask of PDMA_AHB_TASK_OUT_START_CH0_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH0_ST_Msk = 0x8000000
	// Bit PDMA_AHB_TASK_OUT_START_CH0_ST.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH0_ST = 0x8000000
	// Position of PDMA_AHB_TASK_OUT_START_CH1_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH1_ST_Pos = 0x1c
	// Bit mask of PDMA_AHB_TASK_OUT_START_CH1_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH1_ST_Msk = 0x10000000
	// Bit PDMA_AHB_TASK_OUT_START_CH1_ST.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH1_ST = 0x10000000
	// Position of PDMA_AHB_TASK_OUT_START_CH2_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH2_ST_Pos = 0x1d
	// Bit mask of PDMA_AHB_TASK_OUT_START_CH2_ST field.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH2_ST_Msk = 0x20000000
	// Bit PDMA_AHB_TASK_OUT_START_CH2_ST.
	SOC_ETM_TASK_ST5_PDMA_AHB_TASK_OUT_START_CH2_ST = 0x20000000
	// Position of PDMA_AXI_TASK_IN_START_CH0_ST field.
	SOC_ETM_TASK_ST5_PDMA_AXI_TASK_IN_START_CH0_ST_Pos = 0x1e
	// Bit mask of PDMA_AXI_TASK_IN_START_CH0_ST field.
	SOC_ETM_TASK_ST5_PDMA_AXI_TASK_IN_START_CH0_ST_Msk = 0x40000000
	// Bit PDMA_AXI_TASK_IN_START_CH0_ST.
	SOC_ETM_TASK_ST5_PDMA_AXI_TASK_IN_START_CH0_ST = 0x40000000
	// Position of PDMA_AXI_TASK_IN_START_CH1_ST field.
	SOC_ETM_TASK_ST5_PDMA_AXI_TASK_IN_START_CH1_ST_Pos = 0x1f
	// Bit mask of PDMA_AXI_TASK_IN_START_CH1_ST field.
	SOC_ETM_TASK_ST5_PDMA_AXI_TASK_IN_START_CH1_ST_Msk = 0x80000000
	// Bit PDMA_AXI_TASK_IN_START_CH1_ST.
	SOC_ETM_TASK_ST5_PDMA_AXI_TASK_IN_START_CH1_ST = 0x80000000

	// TASK_ST5_CLR: Tasks trigger status clear register
	// Position of REGDMA_TASK_START0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START0_ST_CLR_Pos = 0x0
	// Bit mask of REGDMA_TASK_START0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START0_ST_CLR_Msk = 0x1
	// Bit REGDMA_TASK_START0_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START0_ST_CLR = 0x1
	// Position of REGDMA_TASK_START1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START1_ST_CLR_Pos = 0x1
	// Bit mask of REGDMA_TASK_START1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START1_ST_CLR_Msk = 0x2
	// Bit REGDMA_TASK_START1_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START1_ST_CLR = 0x2
	// Position of REGDMA_TASK_START2_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START2_ST_CLR_Pos = 0x2
	// Bit mask of REGDMA_TASK_START2_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START2_ST_CLR_Msk = 0x4
	// Bit REGDMA_TASK_START2_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START2_ST_CLR = 0x4
	// Position of REGDMA_TASK_START3_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START3_ST_CLR_Pos = 0x3
	// Bit mask of REGDMA_TASK_START3_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START3_ST_CLR_Msk = 0x8
	// Bit REGDMA_TASK_START3_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_REGDMA_TASK_START3_ST_CLR = 0x8
	// Position of TMPSNSR_TASK_START_SAMPLE_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_TMPSNSR_TASK_START_SAMPLE_ST_CLR_Pos = 0x4
	// Bit mask of TMPSNSR_TASK_START_SAMPLE_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_TMPSNSR_TASK_START_SAMPLE_ST_CLR_Msk = 0x10
	// Bit TMPSNSR_TASK_START_SAMPLE_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_TMPSNSR_TASK_START_SAMPLE_ST_CLR = 0x10
	// Position of TMPSNSR_TASK_STOP_SAMPLE_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_Pos = 0x5
	// Bit mask of TMPSNSR_TASK_STOP_SAMPLE_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_Msk = 0x20
	// Bit TMPSNSR_TASK_STOP_SAMPLE_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR = 0x20
	// Position of I2S0_TASK_START_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_START_RX_ST_CLR_Pos = 0x6
	// Bit mask of I2S0_TASK_START_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_START_RX_ST_CLR_Msk = 0x40
	// Bit I2S0_TASK_START_RX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_START_RX_ST_CLR = 0x40
	// Position of I2S0_TASK_START_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_START_TX_ST_CLR_Pos = 0x7
	// Bit mask of I2S0_TASK_START_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_START_TX_ST_CLR_Msk = 0x80
	// Bit I2S0_TASK_START_TX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_START_TX_ST_CLR = 0x80
	// Position of I2S0_TASK_STOP_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_STOP_RX_ST_CLR_Pos = 0x8
	// Bit mask of I2S0_TASK_STOP_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_STOP_RX_ST_CLR_Msk = 0x100
	// Bit I2S0_TASK_STOP_RX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_STOP_RX_ST_CLR = 0x100
	// Position of I2S0_TASK_STOP_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_STOP_TX_ST_CLR_Pos = 0x9
	// Bit mask of I2S0_TASK_STOP_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_STOP_TX_ST_CLR_Msk = 0x200
	// Bit I2S0_TASK_STOP_TX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S0_TASK_STOP_TX_ST_CLR = 0x200
	// Position of I2S1_TASK_START_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_START_RX_ST_CLR_Pos = 0xa
	// Bit mask of I2S1_TASK_START_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_START_RX_ST_CLR_Msk = 0x400
	// Bit I2S1_TASK_START_RX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_START_RX_ST_CLR = 0x400
	// Position of I2S1_TASK_START_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_START_TX_ST_CLR_Pos = 0xb
	// Bit mask of I2S1_TASK_START_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_START_TX_ST_CLR_Msk = 0x800
	// Bit I2S1_TASK_START_TX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_START_TX_ST_CLR = 0x800
	// Position of I2S1_TASK_STOP_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_STOP_RX_ST_CLR_Pos = 0xc
	// Bit mask of I2S1_TASK_STOP_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_STOP_RX_ST_CLR_Msk = 0x1000
	// Bit I2S1_TASK_STOP_RX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_STOP_RX_ST_CLR = 0x1000
	// Position of I2S1_TASK_STOP_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_STOP_TX_ST_CLR_Pos = 0xd
	// Bit mask of I2S1_TASK_STOP_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_STOP_TX_ST_CLR_Msk = 0x2000
	// Bit I2S1_TASK_STOP_TX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S1_TASK_STOP_TX_ST_CLR = 0x2000
	// Position of I2S2_TASK_START_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_START_RX_ST_CLR_Pos = 0xe
	// Bit mask of I2S2_TASK_START_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_START_RX_ST_CLR_Msk = 0x4000
	// Bit I2S2_TASK_START_RX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_START_RX_ST_CLR = 0x4000
	// Position of I2S2_TASK_START_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_START_TX_ST_CLR_Pos = 0xf
	// Bit mask of I2S2_TASK_START_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_START_TX_ST_CLR_Msk = 0x8000
	// Bit I2S2_TASK_START_TX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_START_TX_ST_CLR = 0x8000
	// Position of I2S2_TASK_STOP_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_STOP_RX_ST_CLR_Pos = 0x10
	// Bit mask of I2S2_TASK_STOP_RX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_STOP_RX_ST_CLR_Msk = 0x10000
	// Bit I2S2_TASK_STOP_RX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_STOP_RX_ST_CLR = 0x10000
	// Position of I2S2_TASK_STOP_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_STOP_TX_ST_CLR_Pos = 0x11
	// Bit mask of I2S2_TASK_STOP_TX_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_STOP_TX_ST_CLR_Msk = 0x20000
	// Bit I2S2_TASK_STOP_TX_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_I2S2_TASK_STOP_TX_ST_CLR = 0x20000
	// Position of ULP_TASK_WAKEUP_CPU_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_ULP_TASK_WAKEUP_CPU_ST_CLR_Pos = 0x12
	// Bit mask of ULP_TASK_WAKEUP_CPU_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_ULP_TASK_WAKEUP_CPU_ST_CLR_Msk = 0x40000
	// Bit ULP_TASK_WAKEUP_CPU_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_ULP_TASK_WAKEUP_CPU_ST_CLR = 0x40000
	// Position of ULP_TASK_INT_CPU_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_ULP_TASK_INT_CPU_ST_CLR_Pos = 0x13
	// Bit mask of ULP_TASK_INT_CPU_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_ULP_TASK_INT_CPU_ST_CLR_Msk = 0x80000
	// Bit ULP_TASK_INT_CPU_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_ULP_TASK_INT_CPU_ST_CLR = 0x80000
	// Position of RTC_TASK_START_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_START_ST_CLR_Pos = 0x14
	// Bit mask of RTC_TASK_START_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_START_ST_CLR_Msk = 0x100000
	// Bit RTC_TASK_START_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_START_ST_CLR = 0x100000
	// Position of RTC_TASK_STOP_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_STOP_ST_CLR_Pos = 0x15
	// Bit mask of RTC_TASK_STOP_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_STOP_ST_CLR_Msk = 0x200000
	// Bit RTC_TASK_STOP_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_STOP_ST_CLR = 0x200000
	// Position of RTC_TASK_CLR_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_CLR_ST_CLR_Pos = 0x16
	// Bit mask of RTC_TASK_CLR_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_CLR_ST_CLR_Msk = 0x400000
	// Bit RTC_TASK_CLR_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_CLR_ST_CLR = 0x400000
	// Position of RTC_TASK_TRIGGERFLW_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_TRIGGERFLW_ST_CLR_Pos = 0x17
	// Bit mask of RTC_TASK_TRIGGERFLW_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_TRIGGERFLW_ST_CLR_Msk = 0x800000
	// Bit RTC_TASK_TRIGGERFLW_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_RTC_TASK_TRIGGERFLW_ST_CLR = 0x800000
	// Position of PDMA_AHB_TASK_IN_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_Pos = 0x18
	// Bit mask of PDMA_AHB_TASK_IN_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH0_ST_CLR_Msk = 0x1000000
	// Bit PDMA_AHB_TASK_IN_START_CH0_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH0_ST_CLR = 0x1000000
	// Position of PDMA_AHB_TASK_IN_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_Pos = 0x19
	// Bit mask of PDMA_AHB_TASK_IN_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH1_ST_CLR_Msk = 0x2000000
	// Bit PDMA_AHB_TASK_IN_START_CH1_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH1_ST_CLR = 0x2000000
	// Position of PDMA_AHB_TASK_IN_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_Pos = 0x1a
	// Bit mask of PDMA_AHB_TASK_IN_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH2_ST_CLR_Msk = 0x4000000
	// Bit PDMA_AHB_TASK_IN_START_CH2_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_IN_START_CH2_ST_CLR = 0x4000000
	// Position of PDMA_AHB_TASK_OUT_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_Pos = 0x1b
	// Bit mask of PDMA_AHB_TASK_OUT_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_Msk = 0x8000000
	// Bit PDMA_AHB_TASK_OUT_START_CH0_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH0_ST_CLR = 0x8000000
	// Position of PDMA_AHB_TASK_OUT_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_Pos = 0x1c
	// Bit mask of PDMA_AHB_TASK_OUT_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_Msk = 0x10000000
	// Bit PDMA_AHB_TASK_OUT_START_CH1_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH1_ST_CLR = 0x10000000
	// Position of PDMA_AHB_TASK_OUT_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_Pos = 0x1d
	// Bit mask of PDMA_AHB_TASK_OUT_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_Msk = 0x20000000
	// Bit PDMA_AHB_TASK_OUT_START_CH2_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AHB_TASK_OUT_START_CH2_ST_CLR = 0x20000000
	// Position of PDMA_AXI_TASK_IN_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_Pos = 0x1e
	// Bit mask of PDMA_AXI_TASK_IN_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH0_ST_CLR_Msk = 0x40000000
	// Bit PDMA_AXI_TASK_IN_START_CH0_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH0_ST_CLR = 0x40000000
	// Position of PDMA_AXI_TASK_IN_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_Pos = 0x1f
	// Bit mask of PDMA_AXI_TASK_IN_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH1_ST_CLR_Msk = 0x80000000
	// Bit PDMA_AXI_TASK_IN_START_CH1_ST_CLR.
	SOC_ETM_TASK_ST5_CLR_PDMA_AXI_TASK_IN_START_CH1_ST_CLR = 0x80000000

	// TASK_ST6: Tasks trigger status register
	// Position of PDMA_AXI_TASK_IN_START_CH2_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_IN_START_CH2_ST_Pos = 0x0
	// Bit mask of PDMA_AXI_TASK_IN_START_CH2_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_IN_START_CH2_ST_Msk = 0x1
	// Bit PDMA_AXI_TASK_IN_START_CH2_ST.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_IN_START_CH2_ST = 0x1
	// Position of PDMA_AXI_TASK_OUT_START_CH0_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH0_ST_Pos = 0x1
	// Bit mask of PDMA_AXI_TASK_OUT_START_CH0_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH0_ST_Msk = 0x2
	// Bit PDMA_AXI_TASK_OUT_START_CH0_ST.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH0_ST = 0x2
	// Position of PDMA_AXI_TASK_OUT_START_CH1_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH1_ST_Pos = 0x2
	// Bit mask of PDMA_AXI_TASK_OUT_START_CH1_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH1_ST_Msk = 0x4
	// Bit PDMA_AXI_TASK_OUT_START_CH1_ST.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH1_ST = 0x4
	// Position of PDMA_AXI_TASK_OUT_START_CH2_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH2_ST_Pos = 0x3
	// Bit mask of PDMA_AXI_TASK_OUT_START_CH2_ST field.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH2_ST_Msk = 0x8
	// Bit PDMA_AXI_TASK_OUT_START_CH2_ST.
	SOC_ETM_TASK_ST6_PDMA_AXI_TASK_OUT_START_CH2_ST = 0x8
	// Position of PMU_TASK_SLEEP_REQ_ST field.
	SOC_ETM_TASK_ST6_PMU_TASK_SLEEP_REQ_ST_Pos = 0x4
	// Bit mask of PMU_TASK_SLEEP_REQ_ST field.
	SOC_ETM_TASK_ST6_PMU_TASK_SLEEP_REQ_ST_Msk = 0x10
	// Bit PMU_TASK_SLEEP_REQ_ST.
	SOC_ETM_TASK_ST6_PMU_TASK_SLEEP_REQ_ST = 0x10
	// Position of DMA2D_TASK_IN_START_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_START_CH0_ST_Pos = 0x5
	// Bit mask of DMA2D_TASK_IN_START_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_START_CH0_ST_Msk = 0x20
	// Bit DMA2D_TASK_IN_START_CH0_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_START_CH0_ST = 0x20
	// Position of DMA2D_TASK_IN_START_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_START_CH1_ST_Pos = 0x6
	// Bit mask of DMA2D_TASK_IN_START_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_START_CH1_ST_Msk = 0x40
	// Bit DMA2D_TASK_IN_START_CH1_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_START_CH1_ST = 0x40
	// Position of DMA2D_TASK_IN_DSCR_READY_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH0_ST_Pos = 0x7
	// Bit mask of DMA2D_TASK_IN_DSCR_READY_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH0_ST_Msk = 0x80
	// Bit DMA2D_TASK_IN_DSCR_READY_CH0_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH0_ST = 0x80
	// Position of DMA2D_TASK_IN_DSCR_READY_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH1_ST_Pos = 0x8
	// Bit mask of DMA2D_TASK_IN_DSCR_READY_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH1_ST_Msk = 0x100
	// Bit DMA2D_TASK_IN_DSCR_READY_CH1_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_IN_DSCR_READY_CH1_ST = 0x100
	// Position of DMA2D_TASK_OUT_START_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH0_ST_Pos = 0x9
	// Bit mask of DMA2D_TASK_OUT_START_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH0_ST_Msk = 0x200
	// Bit DMA2D_TASK_OUT_START_CH0_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH0_ST = 0x200
	// Position of DMA2D_TASK_OUT_START_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH1_ST_Pos = 0xa
	// Bit mask of DMA2D_TASK_OUT_START_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH1_ST_Msk = 0x400
	// Bit DMA2D_TASK_OUT_START_CH1_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH1_ST = 0x400
	// Position of DMA2D_TASK_OUT_START_CH2_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH2_ST_Pos = 0xb
	// Bit mask of DMA2D_TASK_OUT_START_CH2_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH2_ST_Msk = 0x800
	// Bit DMA2D_TASK_OUT_START_CH2_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_START_CH2_ST = 0x800
	// Position of DMA2D_TASK_OUT_DSCR_READY_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_Pos = 0xc
	// Bit mask of DMA2D_TASK_OUT_DSCR_READY_CH0_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_Msk = 0x1000
	// Bit DMA2D_TASK_OUT_DSCR_READY_CH0_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH0_ST = 0x1000
	// Position of DMA2D_TASK_OUT_DSCR_READY_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_Pos = 0xd
	// Bit mask of DMA2D_TASK_OUT_DSCR_READY_CH1_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_Msk = 0x2000
	// Bit DMA2D_TASK_OUT_DSCR_READY_CH1_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH1_ST = 0x2000
	// Position of DMA2D_TASK_OUT_DSCR_READY_CH2_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_Pos = 0xe
	// Bit mask of DMA2D_TASK_OUT_DSCR_READY_CH2_ST field.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_Msk = 0x4000
	// Bit DMA2D_TASK_OUT_DSCR_READY_CH2_ST.
	SOC_ETM_TASK_ST6_DMA2D_TASK_OUT_DSCR_READY_CH2_ST = 0x4000

	// TASK_ST6_CLR: Tasks trigger status clear register
	// Position of PDMA_AXI_TASK_IN_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_Pos = 0x0
	// Bit mask of PDMA_AXI_TASK_IN_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_IN_START_CH2_ST_CLR_Msk = 0x1
	// Bit PDMA_AXI_TASK_IN_START_CH2_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_IN_START_CH2_ST_CLR = 0x1
	// Position of PDMA_AXI_TASK_OUT_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_Pos = 0x1
	// Bit mask of PDMA_AXI_TASK_OUT_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_Msk = 0x2
	// Bit PDMA_AXI_TASK_OUT_START_CH0_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH0_ST_CLR = 0x2
	// Position of PDMA_AXI_TASK_OUT_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_Pos = 0x2
	// Bit mask of PDMA_AXI_TASK_OUT_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_Msk = 0x4
	// Bit PDMA_AXI_TASK_OUT_START_CH1_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH1_ST_CLR = 0x4
	// Position of PDMA_AXI_TASK_OUT_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_Pos = 0x3
	// Bit mask of PDMA_AXI_TASK_OUT_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_Msk = 0x8
	// Bit PDMA_AXI_TASK_OUT_START_CH2_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_PDMA_AXI_TASK_OUT_START_CH2_ST_CLR = 0x8
	// Position of PMU_TASK_SLEEP_REQ_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PMU_TASK_SLEEP_REQ_ST_CLR_Pos = 0x4
	// Bit mask of PMU_TASK_SLEEP_REQ_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_PMU_TASK_SLEEP_REQ_ST_CLR_Msk = 0x10
	// Bit PMU_TASK_SLEEP_REQ_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_PMU_TASK_SLEEP_REQ_ST_CLR = 0x10
	// Position of DMA2D_TASK_IN_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_START_CH0_ST_CLR_Pos = 0x5
	// Bit mask of DMA2D_TASK_IN_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_START_CH0_ST_CLR_Msk = 0x20
	// Bit DMA2D_TASK_IN_START_CH0_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_START_CH0_ST_CLR = 0x20
	// Position of DMA2D_TASK_IN_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_START_CH1_ST_CLR_Pos = 0x6
	// Bit mask of DMA2D_TASK_IN_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_START_CH1_ST_CLR_Msk = 0x40
	// Bit DMA2D_TASK_IN_START_CH1_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_START_CH1_ST_CLR = 0x40
	// Position of DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_Pos = 0x7
	// Bit mask of DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_Msk = 0x80
	// Bit DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR = 0x80
	// Position of DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_Pos = 0x8
	// Bit mask of DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_Msk = 0x100
	// Bit DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR = 0x100
	// Position of DMA2D_TASK_OUT_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH0_ST_CLR_Pos = 0x9
	// Bit mask of DMA2D_TASK_OUT_START_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH0_ST_CLR_Msk = 0x200
	// Bit DMA2D_TASK_OUT_START_CH0_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH0_ST_CLR = 0x200
	// Position of DMA2D_TASK_OUT_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH1_ST_CLR_Pos = 0xa
	// Bit mask of DMA2D_TASK_OUT_START_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH1_ST_CLR_Msk = 0x400
	// Bit DMA2D_TASK_OUT_START_CH1_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH1_ST_CLR = 0x400
	// Position of DMA2D_TASK_OUT_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH2_ST_CLR_Pos = 0xb
	// Bit mask of DMA2D_TASK_OUT_START_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH2_ST_CLR_Msk = 0x800
	// Bit DMA2D_TASK_OUT_START_CH2_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_START_CH2_ST_CLR = 0x800
	// Position of DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_Pos = 0xc
	// Bit mask of DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_Msk = 0x1000
	// Bit DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR = 0x1000
	// Position of DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_Pos = 0xd
	// Bit mask of DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_Msk = 0x2000
	// Bit DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR = 0x2000
	// Position of DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_Pos = 0xe
	// Bit mask of DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR field.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_Msk = 0x4000
	// Bit DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR.
	SOC_ETM_TASK_ST6_CLR_DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR = 0x4000

	// CLK_EN: ETM clock enable register
	// Position of CLK_EN field.
	SOC_ETM_CLK_EN_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	SOC_ETM_CLK_EN_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	SOC_ETM_CLK_EN_CLK_EN = 0x1

	// DATE: ETM date register
	// Position of DATE field.
	SOC_ETM_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	SOC_ETM_DATE_DATE_Msk = 0xfffffff
)

// Constants for SPI0: SPI (Serial Peripheral Interface) Controller 0
const (
	// SPI_MEM_CMD: SPI0 FSM status register
	// Position of SPI_MEM_MST_ST field.
	SPI0_SPI_MEM_CMD_SPI_MEM_MST_ST_Pos = 0x0
	// Bit mask of SPI_MEM_MST_ST field.
	SPI0_SPI_MEM_CMD_SPI_MEM_MST_ST_Msk = 0xf
	// Position of SPI_MEM_SLV_ST field.
	SPI0_SPI_MEM_CMD_SPI_MEM_SLV_ST_Pos = 0x4
	// Bit mask of SPI_MEM_SLV_ST field.
	SPI0_SPI_MEM_CMD_SPI_MEM_SLV_ST_Msk = 0xf0
	// Position of SPI_MEM_USR field.
	SPI0_SPI_MEM_CMD_SPI_MEM_USR_Pos = 0x12
	// Bit mask of SPI_MEM_USR field.
	SPI0_SPI_MEM_CMD_SPI_MEM_USR_Msk = 0x40000
	// Bit SPI_MEM_USR.
	SPI0_SPI_MEM_CMD_SPI_MEM_USR = 0x40000

	// SPI_MEM_CTRL: SPI0 control register.
	// Position of SPI_MEM_WDUMMY_DQS_ALWAYS_OUT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_Pos = 0x0
	// Bit mask of SPI_MEM_WDUMMY_DQS_ALWAYS_OUT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_Msk = 0x1
	// Bit SPI_MEM_WDUMMY_DQS_ALWAYS_OUT.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_DQS_ALWAYS_OUT = 0x1
	// Position of SPI_MEM_WDUMMY_ALWAYS_OUT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT_Pos = 0x1
	// Bit mask of SPI_MEM_WDUMMY_ALWAYS_OUT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT_Msk = 0x2
	// Bit SPI_MEM_WDUMMY_ALWAYS_OUT.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WDUMMY_ALWAYS_OUT = 0x2
	// Position of SPI_MEM_FDUMMY_RIN field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Pos = 0x2
	// Bit mask of SPI_MEM_FDUMMY_RIN field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Msk = 0x4
	// Bit SPI_MEM_FDUMMY_RIN.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN = 0x4
	// Position of SPI_MEM_FDUMMY_WOUT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Pos = 0x3
	// Bit mask of SPI_MEM_FDUMMY_WOUT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Msk = 0x8
	// Bit SPI_MEM_FDUMMY_WOUT.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT = 0x8
	// Position of SPI_MEM_FDOUT_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Pos = 0x4
	// Bit mask of SPI_MEM_FDOUT_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Msk = 0x10
	// Bit SPI_MEM_FDOUT_OCT.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT = 0x10
	// Position of SPI_MEM_FDIN_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Pos = 0x5
	// Bit mask of SPI_MEM_FDIN_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Msk = 0x20
	// Bit SPI_MEM_FDIN_OCT.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT = 0x20
	// Position of SPI_MEM_FADDR_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Pos = 0x6
	// Bit mask of SPI_MEM_FADDR_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Msk = 0x40
	// Bit SPI_MEM_FADDR_OCT.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT = 0x40
	// Position of SPI_MEM_FCMD_QUAD field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Pos = 0x8
	// Bit mask of SPI_MEM_FCMD_QUAD field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Msk = 0x100
	// Bit SPI_MEM_FCMD_QUAD.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD = 0x100
	// Position of SPI_MEM_FCMD_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Pos = 0x9
	// Bit mask of SPI_MEM_FCMD_OCT field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Msk = 0x200
	// Bit SPI_MEM_FCMD_OCT.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT = 0x200
	// Position of SPI_MEM_FASTRD_MODE field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Pos = 0xd
	// Bit mask of SPI_MEM_FASTRD_MODE field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Msk = 0x2000
	// Bit SPI_MEM_FASTRD_MODE.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE = 0x2000
	// Position of SPI_MEM_FREAD_DUAL field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Pos = 0xe
	// Bit mask of SPI_MEM_FREAD_DUAL field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Msk = 0x4000
	// Bit SPI_MEM_FREAD_DUAL.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL = 0x4000
	// Position of SPI_MEM_Q_POL field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL_Pos = 0x12
	// Bit mask of SPI_MEM_Q_POL field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL_Msk = 0x40000
	// Bit SPI_MEM_Q_POL.
	SPI0_SPI_MEM_CTRL_SPI_MEM_Q_POL = 0x40000
	// Position of SPI_MEM_D_POL field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL_Pos = 0x13
	// Bit mask of SPI_MEM_D_POL field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL_Msk = 0x80000
	// Bit SPI_MEM_D_POL.
	SPI0_SPI_MEM_CTRL_SPI_MEM_D_POL = 0x80000
	// Position of SPI_MEM_FREAD_QUAD field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Pos = 0x14
	// Bit mask of SPI_MEM_FREAD_QUAD field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Msk = 0x100000
	// Bit SPI_MEM_FREAD_QUAD.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD = 0x100000
	// Position of SPI_MEM_WP field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WP_Pos = 0x15
	// Bit mask of SPI_MEM_WP field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WP_Msk = 0x200000
	// Bit SPI_MEM_WP.
	SPI0_SPI_MEM_CTRL_SPI_MEM_WP = 0x200000
	// Position of SPI_MEM_FREAD_DIO field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Pos = 0x17
	// Bit mask of SPI_MEM_FREAD_DIO field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Msk = 0x800000
	// Bit SPI_MEM_FREAD_DIO.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO = 0x800000
	// Position of SPI_MEM_FREAD_QIO field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Pos = 0x18
	// Bit mask of SPI_MEM_FREAD_QIO field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Msk = 0x1000000
	// Bit SPI_MEM_FREAD_QIO.
	SPI0_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO = 0x1000000
	// Position of SPI_MEM_DQS_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON_Pos = 0x1e
	// Bit mask of SPI_MEM_DQS_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON_Msk = 0x40000000
	// Bit SPI_MEM_DQS_IE_ALWAYS_ON.
	SPI0_SPI_MEM_CTRL_SPI_MEM_DQS_IE_ALWAYS_ON = 0x40000000
	// Position of SPI_MEM_DATA_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON_Pos = 0x1f
	// Bit mask of SPI_MEM_DATA_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON_Msk = 0x80000000
	// Bit SPI_MEM_DATA_IE_ALWAYS_ON.
	SPI0_SPI_MEM_CTRL_SPI_MEM_DATA_IE_ALWAYS_ON = 0x80000000

	// SPI_MEM_CTRL1: SPI0 control1 register.
	// Position of SPI_MEM_CLK_MODE field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Pos = 0x0
	// Bit mask of SPI_MEM_CLK_MODE field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Msk = 0x3
	// Position of SPI_AR_SIZE0_1_SUPPORT_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN_Pos = 0x15
	// Bit mask of SPI_AR_SIZE0_1_SUPPORT_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN_Msk = 0x200000
	// Bit SPI_AR_SIZE0_1_SUPPORT_EN.
	SPI0_SPI_MEM_CTRL1_SPI_AR_SIZE0_1_SUPPORT_EN = 0x200000
	// Position of SPI_AW_SIZE0_1_SUPPORT_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN_Pos = 0x16
	// Bit mask of SPI_AW_SIZE0_1_SUPPORT_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN_Msk = 0x400000
	// Bit SPI_AW_SIZE0_1_SUPPORT_EN.
	SPI0_SPI_MEM_CTRL1_SPI_AW_SIZE0_1_SUPPORT_EN = 0x400000
	// Position of SPI_AXI_RDATA_BACK_FAST field.
	SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST_Pos = 0x17
	// Bit mask of SPI_AXI_RDATA_BACK_FAST field.
	SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST_Msk = 0x800000
	// Bit SPI_AXI_RDATA_BACK_FAST.
	SPI0_SPI_MEM_CTRL1_SPI_AXI_RDATA_BACK_FAST = 0x800000
	// Position of SPI_MEM_RRESP_ECC_ERR_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN_Pos = 0x18
	// Bit mask of SPI_MEM_RRESP_ECC_ERR_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN_Msk = 0x1000000
	// Bit SPI_MEM_RRESP_ECC_ERR_EN.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RRESP_ECC_ERR_EN = 0x1000000
	// Position of SPI_MEM_AR_SPLICE_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN_Pos = 0x19
	// Bit mask of SPI_MEM_AR_SPLICE_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN_Msk = 0x2000000
	// Bit SPI_MEM_AR_SPLICE_EN.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_AR_SPLICE_EN = 0x2000000
	// Position of SPI_MEM_AW_SPLICE_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN_Pos = 0x1a
	// Bit mask of SPI_MEM_AW_SPLICE_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN_Msk = 0x4000000
	// Bit SPI_MEM_AW_SPLICE_EN.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_AW_SPLICE_EN = 0x4000000
	// Position of SPI_MEM_RAM0_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN_Pos = 0x1b
	// Bit mask of SPI_MEM_RAM0_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN_Msk = 0x8000000
	// Bit SPI_MEM_RAM0_EN.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RAM0_EN = 0x8000000
	// Position of SPI_MEM_DUAL_RAM_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN_Pos = 0x1c
	// Bit mask of SPI_MEM_DUAL_RAM_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN_Msk = 0x10000000
	// Bit SPI_MEM_DUAL_RAM_EN.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_DUAL_RAM_EN = 0x10000000
	// Position of SPI_MEM_FAST_WRITE_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN_Pos = 0x1d
	// Bit mask of SPI_MEM_FAST_WRITE_EN field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN_Msk = 0x20000000
	// Bit SPI_MEM_FAST_WRITE_EN.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_FAST_WRITE_EN = 0x20000000
	// Position of SPI_MEM_RXFIFO_RST field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST_Pos = 0x1e
	// Bit mask of SPI_MEM_RXFIFO_RST field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST_Msk = 0x40000000
	// Bit SPI_MEM_RXFIFO_RST.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_RXFIFO_RST = 0x40000000
	// Position of SPI_MEM_TXFIFO_RST field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST_Pos = 0x1f
	// Bit mask of SPI_MEM_TXFIFO_RST field.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST_Msk = 0x80000000
	// Bit SPI_MEM_TXFIFO_RST.
	SPI0_SPI_MEM_CTRL1_SPI_MEM_TXFIFO_RST = 0x80000000

	// SPI_MEM_CTRL2: SPI0 control2 register.
	// Position of SPI_MEM_CS_SETUP_TIME field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME_Pos = 0x0
	// Bit mask of SPI_MEM_CS_SETUP_TIME field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_SETUP_TIME_Msk = 0x1f
	// Position of SPI_MEM_CS_HOLD_TIME field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME_Pos = 0x5
	// Bit mask of SPI_MEM_CS_HOLD_TIME field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_TIME_Msk = 0x3e0
	// Position of SPI_MEM_ECC_CS_HOLD_TIME field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME_Pos = 0xa
	// Bit mask of SPI_MEM_ECC_CS_HOLD_TIME field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_CS_HOLD_TIME_Msk = 0x1c00
	// Position of SPI_MEM_ECC_SKIP_PAGE_CORNER field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER_Pos = 0xd
	// Bit mask of SPI_MEM_ECC_SKIP_PAGE_CORNER field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER_Msk = 0x2000
	// Bit SPI_MEM_ECC_SKIP_PAGE_CORNER.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_SKIP_PAGE_CORNER = 0x2000
	// Position of SPI_MEM_ECC_16TO18_BYTE_EN field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN_Pos = 0xe
	// Bit mask of SPI_MEM_ECC_16TO18_BYTE_EN field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN_Msk = 0x4000
	// Bit SPI_MEM_ECC_16TO18_BYTE_EN.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_ECC_16TO18_BYTE_EN = 0x4000
	// Position of SPI_MEM_SPLIT_TRANS_EN field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN_Pos = 0x18
	// Bit mask of SPI_MEM_SPLIT_TRANS_EN field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN_Msk = 0x1000000
	// Bit SPI_MEM_SPLIT_TRANS_EN.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_SPLIT_TRANS_EN = 0x1000000
	// Position of SPI_MEM_CS_HOLD_DELAY field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY_Pos = 0x19
	// Bit mask of SPI_MEM_CS_HOLD_DELAY field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_CS_HOLD_DELAY_Msk = 0x7e000000
	// Position of SPI_MEM_SYNC_RESET field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Pos = 0x1f
	// Bit mask of SPI_MEM_SYNC_RESET field.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Msk = 0x80000000
	// Bit SPI_MEM_SYNC_RESET.
	SPI0_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET = 0x80000000

	// SPI_MEM_CLOCK: SPI clock division control register.
	// Position of SPI_MEM_CLKCNT_L field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Pos = 0x0
	// Bit mask of SPI_MEM_CLKCNT_L field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Msk = 0xff
	// Position of SPI_MEM_CLKCNT_H field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Pos = 0x8
	// Bit mask of SPI_MEM_CLKCNT_H field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Msk = 0xff00
	// Position of SPI_MEM_CLKCNT_N field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Pos = 0x10
	// Bit mask of SPI_MEM_CLKCNT_N field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Msk = 0xff0000
	// Position of SPI_MEM_CLK_EQU_SYSCLK field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Pos = 0x1f
	// Bit mask of SPI_MEM_CLK_EQU_SYSCLK field.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Msk = 0x80000000
	// Bit SPI_MEM_CLK_EQU_SYSCLK.
	SPI0_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK = 0x80000000

	// SPI_MEM_USER: SPI0 user register.
	// Position of SPI_MEM_CS_HOLD field.
	SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD_Pos = 0x6
	// Bit mask of SPI_MEM_CS_HOLD field.
	SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD_Msk = 0x40
	// Bit SPI_MEM_CS_HOLD.
	SPI0_SPI_MEM_USER_SPI_MEM_CS_HOLD = 0x40
	// Position of SPI_MEM_CS_SETUP field.
	SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP_Pos = 0x7
	// Bit mask of SPI_MEM_CS_SETUP field.
	SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP_Msk = 0x80
	// Bit SPI_MEM_CS_SETUP.
	SPI0_SPI_MEM_USER_SPI_MEM_CS_SETUP = 0x80
	// Position of SPI_MEM_CK_OUT_EDGE field.
	SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Pos = 0x9
	// Bit mask of SPI_MEM_CK_OUT_EDGE field.
	SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Msk = 0x200
	// Bit SPI_MEM_CK_OUT_EDGE.
	SPI0_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE = 0x200
	// Position of SPI_MEM_USR_DUMMY_IDLE field.
	SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Pos = 0x1a
	// Bit mask of SPI_MEM_USR_DUMMY_IDLE field.
	SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Msk = 0x4000000
	// Bit SPI_MEM_USR_DUMMY_IDLE.
	SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE = 0x4000000
	// Position of SPI_MEM_USR_DUMMY field.
	SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Pos = 0x1d
	// Bit mask of SPI_MEM_USR_DUMMY field.
	SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Msk = 0x20000000
	// Bit SPI_MEM_USR_DUMMY.
	SPI0_SPI_MEM_USER_SPI_MEM_USR_DUMMY = 0x20000000

	// SPI_MEM_USER1: SPI0 user1 register.
	// Position of SPI_MEM_USR_DUMMY_CYCLELEN field.
	SPI0_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Pos = 0x0
	// Bit mask of SPI_MEM_USR_DUMMY_CYCLELEN field.
	SPI0_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Msk = 0x3f
	// Position of SPI_MEM_USR_DBYTELEN field.
	SPI0_SPI_MEM_USER1_SPI_MEM_USR_DBYTELEN_Pos = 0x6
	// Bit mask of SPI_MEM_USR_DBYTELEN field.
	SPI0_SPI_MEM_USER1_SPI_MEM_USR_DBYTELEN_Msk = 0x1c0
	// Position of SPI_MEM_USR_ADDR_BITLEN field.
	SPI0_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Pos = 0x1a
	// Bit mask of SPI_MEM_USR_ADDR_BITLEN field.
	SPI0_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Msk = 0xfc000000

	// SPI_MEM_USER2: SPI0 user2 register.
	// Position of SPI_MEM_USR_COMMAND_VALUE field.
	SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Pos = 0x0
	// Bit mask of SPI_MEM_USR_COMMAND_VALUE field.
	SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Msk = 0xffff
	// Position of SPI_MEM_USR_COMMAND_BITLEN field.
	SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Pos = 0x1c
	// Bit mask of SPI_MEM_USR_COMMAND_BITLEN field.
	SPI0_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Msk = 0xf0000000

	// SPI_MEM_RD_STATUS: SPI0 read control register.
	// Position of SPI_MEM_WB_MODE field.
	SPI0_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Pos = 0x10
	// Bit mask of SPI_MEM_WB_MODE field.
	SPI0_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Msk = 0xff0000

	// SPI_MEM_MISC: SPI0 misc register
	// Position of SPI_MEM_FSUB_PIN field.
	SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN_Pos = 0x7
	// Bit mask of SPI_MEM_FSUB_PIN field.
	SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN_Msk = 0x80
	// Bit SPI_MEM_FSUB_PIN.
	SPI0_SPI_MEM_MISC_SPI_MEM_FSUB_PIN = 0x80
	// Position of SPI_MEM_SSUB_PIN field.
	SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN_Pos = 0x8
	// Bit mask of SPI_MEM_SSUB_PIN field.
	SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN_Msk = 0x100
	// Bit SPI_MEM_SSUB_PIN.
	SPI0_SPI_MEM_MISC_SPI_MEM_SSUB_PIN = 0x100
	// Position of SPI_MEM_CK_IDLE_EDGE field.
	SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Pos = 0x9
	// Bit mask of SPI_MEM_CK_IDLE_EDGE field.
	SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Msk = 0x200
	// Bit SPI_MEM_CK_IDLE_EDGE.
	SPI0_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE = 0x200
	// Position of SPI_MEM_CS_KEEP_ACTIVE field.
	SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Pos = 0xa
	// Bit mask of SPI_MEM_CS_KEEP_ACTIVE field.
	SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Msk = 0x400
	// Bit SPI_MEM_CS_KEEP_ACTIVE.
	SPI0_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE = 0x400

	// SPI_MEM_CACHE_FCTRL: SPI0 bit mode control register.
	// Position of SPI_MEM_AXI_REQ_EN field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN_Pos = 0x0
	// Bit mask of SPI_MEM_AXI_REQ_EN field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN_Msk = 0x1
	// Bit SPI_MEM_AXI_REQ_EN.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_AXI_REQ_EN = 0x1
	// Position of SPI_MEM_CACHE_USR_ADDR_4BYTE field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Pos = 0x1
	// Bit mask of SPI_MEM_CACHE_USR_ADDR_4BYTE field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Msk = 0x2
	// Bit SPI_MEM_CACHE_USR_ADDR_4BYTE.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE = 0x2
	// Position of SPI_MEM_CACHE_FLASH_USR_CMD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD_Pos = 0x2
	// Bit mask of SPI_MEM_CACHE_FLASH_USR_CMD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD_Msk = 0x4
	// Bit SPI_MEM_CACHE_FLASH_USR_CMD.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_FLASH_USR_CMD = 0x4
	// Position of SPI_MEM_FDIN_DUAL field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Pos = 0x3
	// Bit mask of SPI_MEM_FDIN_DUAL field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Msk = 0x8
	// Bit SPI_MEM_FDIN_DUAL.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL = 0x8
	// Position of SPI_MEM_FDOUT_DUAL field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Pos = 0x4
	// Bit mask of SPI_MEM_FDOUT_DUAL field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Msk = 0x10
	// Bit SPI_MEM_FDOUT_DUAL.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL = 0x10
	// Position of SPI_MEM_FADDR_DUAL field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Pos = 0x5
	// Bit mask of SPI_MEM_FADDR_DUAL field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Msk = 0x20
	// Bit SPI_MEM_FADDR_DUAL.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL = 0x20
	// Position of SPI_MEM_FDIN_QUAD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Pos = 0x6
	// Bit mask of SPI_MEM_FDIN_QUAD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Msk = 0x40
	// Bit SPI_MEM_FDIN_QUAD.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD = 0x40
	// Position of SPI_MEM_FDOUT_QUAD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Pos = 0x7
	// Bit mask of SPI_MEM_FDOUT_QUAD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Msk = 0x80
	// Bit SPI_MEM_FDOUT_QUAD.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD = 0x80
	// Position of SPI_MEM_FADDR_QUAD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Pos = 0x8
	// Bit mask of SPI_MEM_FADDR_QUAD field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Msk = 0x100
	// Bit SPI_MEM_FADDR_QUAD.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD = 0x100
	// Position of SPI_SAME_AW_AR_ADDR_CHK_EN field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN_Pos = 0x1e
	// Bit mask of SPI_SAME_AW_AR_ADDR_CHK_EN field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN_Msk = 0x40000000
	// Bit SPI_SAME_AW_AR_ADDR_CHK_EN.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_SAME_AW_AR_ADDR_CHK_EN = 0x40000000
	// Position of SPI_CLOSE_AXI_INF_EN field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN_Pos = 0x1f
	// Bit mask of SPI_CLOSE_AXI_INF_EN field.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN_Msk = 0x80000000
	// Bit SPI_CLOSE_AXI_INF_EN.
	SPI0_SPI_MEM_CACHE_FCTRL_SPI_CLOSE_AXI_INF_EN = 0x80000000

	// SPI_MEM_CACHE_SCTRL: SPI0 external RAM control register
	// Position of SPI_MEM_CACHE_USR_SADDR_4BYTE field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE_Pos = 0x0
	// Bit mask of SPI_MEM_CACHE_USR_SADDR_4BYTE field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE_Msk = 0x1
	// Bit SPI_MEM_CACHE_USR_SADDR_4BYTE.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_USR_SADDR_4BYTE = 0x1
	// Position of SPI_MEM_USR_SRAM_DIO field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO_Pos = 0x1
	// Bit mask of SPI_MEM_USR_SRAM_DIO field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO_Msk = 0x2
	// Bit SPI_MEM_USR_SRAM_DIO.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_DIO = 0x2
	// Position of SPI_MEM_USR_SRAM_QIO field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO_Pos = 0x2
	// Bit mask of SPI_MEM_USR_SRAM_QIO field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO_Msk = 0x4
	// Bit SPI_MEM_USR_SRAM_QIO.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_SRAM_QIO = 0x4
	// Position of SPI_MEM_USR_WR_SRAM_DUMMY field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY_Pos = 0x3
	// Bit mask of SPI_MEM_USR_WR_SRAM_DUMMY field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY_Msk = 0x8
	// Bit SPI_MEM_USR_WR_SRAM_DUMMY.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_WR_SRAM_DUMMY = 0x8
	// Position of SPI_MEM_USR_RD_SRAM_DUMMY field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY_Pos = 0x4
	// Bit mask of SPI_MEM_USR_RD_SRAM_DUMMY field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY_Msk = 0x10
	// Bit SPI_MEM_USR_RD_SRAM_DUMMY.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_USR_RD_SRAM_DUMMY = 0x10
	// Position of SPI_MEM_CACHE_SRAM_USR_RCMD field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD_Pos = 0x5
	// Bit mask of SPI_MEM_CACHE_SRAM_USR_RCMD field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD_Msk = 0x20
	// Bit SPI_MEM_CACHE_SRAM_USR_RCMD.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_RCMD = 0x20
	// Position of SPI_MEM_SRAM_RDUMMY_CYCLELEN field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN_Pos = 0x6
	// Bit mask of SPI_MEM_SRAM_RDUMMY_CYCLELEN field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_RDUMMY_CYCLELEN_Msk = 0xfc0
	// Position of SPI_MEM_SRAM_ADDR_BITLEN field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN_Pos = 0xe
	// Bit mask of SPI_MEM_SRAM_ADDR_BITLEN field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_ADDR_BITLEN_Msk = 0xfc000
	// Position of SPI_MEM_CACHE_SRAM_USR_WCMD field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD_Pos = 0x14
	// Bit mask of SPI_MEM_CACHE_SRAM_USR_WCMD field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD_Msk = 0x100000
	// Bit SPI_MEM_CACHE_SRAM_USR_WCMD.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_CACHE_SRAM_USR_WCMD = 0x100000
	// Position of SPI_MEM_SRAM_OCT field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT_Pos = 0x15
	// Bit mask of SPI_MEM_SRAM_OCT field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT_Msk = 0x200000
	// Bit SPI_MEM_SRAM_OCT.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_OCT = 0x200000
	// Position of SPI_MEM_SRAM_WDUMMY_CYCLELEN field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN_Pos = 0x16
	// Bit mask of SPI_MEM_SRAM_WDUMMY_CYCLELEN field.
	SPI0_SPI_MEM_CACHE_SCTRL_SPI_MEM_SRAM_WDUMMY_CYCLELEN_Msk = 0xfc00000

	// SPI_MEM_SRAM_CMD: SPI0 external RAM mode control register
	// Position of SPI_MEM_SCLK_MODE field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE_Pos = 0x0
	// Bit mask of SPI_MEM_SCLK_MODE field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCLK_MODE_Msk = 0x3
	// Position of SPI_MEM_SWB_MODE field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE_Pos = 0x2
	// Bit mask of SPI_MEM_SWB_MODE field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SWB_MODE_Msk = 0x3fc
	// Position of SPI_MEM_SDIN_DUAL field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL_Pos = 0xa
	// Bit mask of SPI_MEM_SDIN_DUAL field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL_Msk = 0x400
	// Bit SPI_MEM_SDIN_DUAL.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_DUAL = 0x400
	// Position of SPI_MEM_SDOUT_DUAL field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL_Pos = 0xb
	// Bit mask of SPI_MEM_SDOUT_DUAL field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL_Msk = 0x800
	// Bit SPI_MEM_SDOUT_DUAL.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_DUAL = 0x800
	// Position of SPI_MEM_SADDR_DUAL field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL_Pos = 0xc
	// Bit mask of SPI_MEM_SADDR_DUAL field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL_Msk = 0x1000
	// Bit SPI_MEM_SADDR_DUAL.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_DUAL = 0x1000
	// Position of SPI_MEM_SDIN_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD_Pos = 0xe
	// Bit mask of SPI_MEM_SDIN_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD_Msk = 0x4000
	// Bit SPI_MEM_SDIN_QUAD.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_QUAD = 0x4000
	// Position of SPI_MEM_SDOUT_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD_Pos = 0xf
	// Bit mask of SPI_MEM_SDOUT_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD_Msk = 0x8000
	// Bit SPI_MEM_SDOUT_QUAD.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_QUAD = 0x8000
	// Position of SPI_MEM_SADDR_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD_Pos = 0x10
	// Bit mask of SPI_MEM_SADDR_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD_Msk = 0x10000
	// Bit SPI_MEM_SADDR_QUAD.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_QUAD = 0x10000
	// Position of SPI_MEM_SCMD_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD_Pos = 0x11
	// Bit mask of SPI_MEM_SCMD_QUAD field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD_Msk = 0x20000
	// Bit SPI_MEM_SCMD_QUAD.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_QUAD = 0x20000
	// Position of SPI_MEM_SDIN_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT_Pos = 0x12
	// Bit mask of SPI_MEM_SDIN_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT_Msk = 0x40000
	// Bit SPI_MEM_SDIN_OCT.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_OCT = 0x40000
	// Position of SPI_MEM_SDOUT_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT_Pos = 0x13
	// Bit mask of SPI_MEM_SDOUT_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT_Msk = 0x80000
	// Bit SPI_MEM_SDOUT_OCT.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_OCT = 0x80000
	// Position of SPI_MEM_SADDR_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT_Pos = 0x14
	// Bit mask of SPI_MEM_SADDR_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT_Msk = 0x100000
	// Bit SPI_MEM_SADDR_OCT.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SADDR_OCT = 0x100000
	// Position of SPI_MEM_SCMD_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT_Pos = 0x15
	// Bit mask of SPI_MEM_SCMD_OCT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT_Msk = 0x200000
	// Bit SPI_MEM_SCMD_OCT.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SCMD_OCT = 0x200000
	// Position of SPI_MEM_SDUMMY_RIN field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN_Pos = 0x16
	// Bit mask of SPI_MEM_SDUMMY_RIN field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN_Msk = 0x400000
	// Bit SPI_MEM_SDUMMY_RIN.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_RIN = 0x400000
	// Position of SPI_MEM_SDUMMY_WOUT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT_Pos = 0x17
	// Bit mask of SPI_MEM_SDUMMY_WOUT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT_Msk = 0x800000
	// Bit SPI_MEM_SDUMMY_WOUT.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDUMMY_WOUT = 0x800000
	// Position of SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_Pos = 0x18
	// Bit mask of SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_Msk = 0x1000000
	// Bit SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT = 0x1000000
	// Position of SPI_SMEM_WDUMMY_ALWAYS_OUT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT_Pos = 0x19
	// Bit mask of SPI_SMEM_WDUMMY_ALWAYS_OUT field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT_Msk = 0x2000000
	// Bit SPI_SMEM_WDUMMY_ALWAYS_OUT.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_WDUMMY_ALWAYS_OUT = 0x2000000
	// Position of SPI_MEM_SDIN_HEX field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_HEX_Pos = 0x1a
	// Bit mask of SPI_MEM_SDIN_HEX field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_HEX_Msk = 0x4000000
	// Bit SPI_MEM_SDIN_HEX.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDIN_HEX = 0x4000000
	// Position of SPI_MEM_SDOUT_HEX field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_HEX_Pos = 0x1b
	// Bit mask of SPI_MEM_SDOUT_HEX field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_HEX_Msk = 0x8000000
	// Bit SPI_MEM_SDOUT_HEX.
	SPI0_SPI_MEM_SRAM_CMD_SPI_MEM_SDOUT_HEX = 0x8000000
	// Position of SPI_SMEM_DQS_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON_Pos = 0x1e
	// Bit mask of SPI_SMEM_DQS_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON_Msk = 0x40000000
	// Bit SPI_SMEM_DQS_IE_ALWAYS_ON.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DQS_IE_ALWAYS_ON = 0x40000000
	// Position of SPI_SMEM_DATA_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON_Pos = 0x1f
	// Bit mask of SPI_SMEM_DATA_IE_ALWAYS_ON field.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON_Msk = 0x80000000
	// Bit SPI_SMEM_DATA_IE_ALWAYS_ON.
	SPI0_SPI_MEM_SRAM_CMD_SPI_SMEM_DATA_IE_ALWAYS_ON = 0x80000000

	// SPI_MEM_SRAM_DRD_CMD: SPI0 external RAM DDR read command control register
	// Position of SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE field.
	SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_Pos = 0x0
	// Bit mask of SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE field.
	SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_Msk = 0xffff
	// Position of SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN field.
	SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_Pos = 0x1c
	// Bit mask of SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN field.
	SPI0_SPI_MEM_SRAM_DRD_CMD_SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_Msk = 0xf0000000

	// SPI_MEM_SRAM_DWR_CMD: SPI0 external RAM DDR write command control register
	// Position of SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE field.
	SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_Pos = 0x0
	// Bit mask of SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE field.
	SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_Msk = 0xffff
	// Position of SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN field.
	SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_Pos = 0x1c
	// Bit mask of SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN field.
	SPI0_SPI_MEM_SRAM_DWR_CMD_SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_Msk = 0xf0000000

	// SPI_MEM_SRAM_CLK: SPI0 external RAM clock control register
	// Position of SPI_MEM_SCLKCNT_L field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L_Pos = 0x0
	// Bit mask of SPI_MEM_SCLKCNT_L field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_L_Msk = 0xff
	// Position of SPI_MEM_SCLKCNT_H field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H_Pos = 0x8
	// Bit mask of SPI_MEM_SCLKCNT_H field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_H_Msk = 0xff00
	// Position of SPI_MEM_SCLKCNT_N field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N_Pos = 0x10
	// Bit mask of SPI_MEM_SCLKCNT_N field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLKCNT_N_Msk = 0xff0000
	// Position of SPI_MEM_SCLK_EQU_SYSCLK field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK_Pos = 0x1f
	// Bit mask of SPI_MEM_SCLK_EQU_SYSCLK field.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK_Msk = 0x80000000
	// Bit SPI_MEM_SCLK_EQU_SYSCLK.
	SPI0_SPI_MEM_SRAM_CLK_SPI_MEM_SCLK_EQU_SYSCLK = 0x80000000

	// SPI_MEM_FSM: SPI0 FSM status register
	// Position of SPI_MEM_LOCK_DELAY_TIME field.
	SPI0_SPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME_Pos = 0x7
	// Bit mask of SPI_MEM_LOCK_DELAY_TIME field.
	SPI0_SPI_MEM_FSM_SPI_MEM_LOCK_DELAY_TIME_Msk = 0xf80

	// SPI_MEM_INT_ENA: SPI0 interrupt enable register
	// Position of SPI_MEM_SLV_ST_END_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA = 0x10
	// Position of SPI_MEM_ECC_ERR_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA_Pos = 0x5
	// Bit mask of SPI_MEM_ECC_ERR_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA_Msk = 0x20
	// Bit SPI_MEM_ECC_ERR_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_ECC_ERR_INT_ENA = 0x20
	// Position of SPI_MEM_PMS_REJECT_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA_Pos = 0x6
	// Bit mask of SPI_MEM_PMS_REJECT_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA_Msk = 0x40
	// Bit SPI_MEM_PMS_REJECT_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_PMS_REJECT_INT_ENA = 0x40
	// Position of SPI_MEM_AXI_RADDR_ERR_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA_Pos = 0x7
	// Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA_Msk = 0x80
	// Bit SPI_MEM_AXI_RADDR_ERR_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_RADDR_ERR_INT_ENA = 0x80
	// Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_Pos = 0x8
	// Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_Msk = 0x100
	// Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA = 0x100
	// Position of SPI_MEM_AXI_WADDR_ERR_INT__ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA_Pos = 0x9
	// Bit mask of SPI_MEM_AXI_WADDR_ERR_INT__ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA_Msk = 0x200
	// Bit SPI_MEM_AXI_WADDR_ERR_INT__ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_AXI_WADDR_ERR_INT__ENA = 0x200
	// Position of SPI_MEM_DQS0_AFIFO_OVF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_Pos = 0x1c
	// Bit mask of SPI_MEM_DQS0_AFIFO_OVF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_Msk = 0x10000000
	// Bit SPI_MEM_DQS0_AFIFO_OVF_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_DQS0_AFIFO_OVF_INT_ENA = 0x10000000
	// Position of SPI_MEM_DQS1_AFIFO_OVF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_Pos = 0x1d
	// Bit mask of SPI_MEM_DQS1_AFIFO_OVF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_Msk = 0x20000000
	// Bit SPI_MEM_DQS1_AFIFO_OVF_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_DQS1_AFIFO_OVF_INT_ENA = 0x20000000
	// Position of SPI_MEM_BUS_FIFO1_UDF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO1_UDF_INT_ENA_Pos = 0x1e
	// Bit mask of SPI_MEM_BUS_FIFO1_UDF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO1_UDF_INT_ENA_Msk = 0x40000000
	// Bit SPI_MEM_BUS_FIFO1_UDF_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO1_UDF_INT_ENA = 0x40000000
	// Position of SPI_MEM_BUS_FIFO0_UDF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO0_UDF_INT_ENA_Pos = 0x1f
	// Bit mask of SPI_MEM_BUS_FIFO0_UDF_INT_ENA field.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO0_UDF_INT_ENA_Msk = 0x80000000
	// Bit SPI_MEM_BUS_FIFO0_UDF_INT_ENA.
	SPI0_SPI_MEM_INT_ENA_SPI_MEM_BUS_FIFO0_UDF_INT_ENA = 0x80000000

	// SPI_MEM_INT_CLR: SPI0 interrupt clear register
	// Position of SPI_MEM_SLV_ST_END_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR = 0x10
	// Position of SPI_MEM_ECC_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR_Pos = 0x5
	// Bit mask of SPI_MEM_ECC_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR_Msk = 0x20
	// Bit SPI_MEM_ECC_ERR_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_ECC_ERR_INT_CLR = 0x20
	// Position of SPI_MEM_PMS_REJECT_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR_Pos = 0x6
	// Bit mask of SPI_MEM_PMS_REJECT_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR_Msk = 0x40
	// Bit SPI_MEM_PMS_REJECT_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_PMS_REJECT_INT_CLR = 0x40
	// Position of SPI_MEM_AXI_RADDR_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR_Pos = 0x7
	// Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR_Msk = 0x80
	// Bit SPI_MEM_AXI_RADDR_ERR_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_RADDR_ERR_INT_CLR = 0x80
	// Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_Pos = 0x8
	// Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_Msk = 0x100
	// Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR = 0x100
	// Position of SPI_MEM_AXI_WADDR_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR_Pos = 0x9
	// Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR_Msk = 0x200
	// Bit SPI_MEM_AXI_WADDR_ERR_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_AXI_WADDR_ERR_INT_CLR = 0x200
	// Position of SPI_MEM_DQS0_AFIFO_OVF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_Pos = 0x1c
	// Bit mask of SPI_MEM_DQS0_AFIFO_OVF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_Msk = 0x10000000
	// Bit SPI_MEM_DQS0_AFIFO_OVF_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_DQS0_AFIFO_OVF_INT_CLR = 0x10000000
	// Position of SPI_MEM_DQS1_AFIFO_OVF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_Pos = 0x1d
	// Bit mask of SPI_MEM_DQS1_AFIFO_OVF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_Msk = 0x20000000
	// Bit SPI_MEM_DQS1_AFIFO_OVF_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_DQS1_AFIFO_OVF_INT_CLR = 0x20000000
	// Position of SPI_MEM_BUS_FIFO1_UDF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO1_UDF_INT_CLR_Pos = 0x1e
	// Bit mask of SPI_MEM_BUS_FIFO1_UDF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO1_UDF_INT_CLR_Msk = 0x40000000
	// Bit SPI_MEM_BUS_FIFO1_UDF_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO1_UDF_INT_CLR = 0x40000000
	// Position of SPI_MEM_BUS_FIFO0_UDF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO0_UDF_INT_CLR_Pos = 0x1f
	// Bit mask of SPI_MEM_BUS_FIFO0_UDF_INT_CLR field.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO0_UDF_INT_CLR_Msk = 0x80000000
	// Bit SPI_MEM_BUS_FIFO0_UDF_INT_CLR.
	SPI0_SPI_MEM_INT_CLR_SPI_MEM_BUS_FIFO0_UDF_INT_CLR = 0x80000000

	// SPI_MEM_INT_RAW: SPI0 interrupt raw register
	// Position of SPI_MEM_SLV_ST_END_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW = 0x10
	// Position of SPI_MEM_ECC_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW_Pos = 0x5
	// Bit mask of SPI_MEM_ECC_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW_Msk = 0x20
	// Bit SPI_MEM_ECC_ERR_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_ECC_ERR_INT_RAW = 0x20
	// Position of SPI_MEM_PMS_REJECT_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW_Pos = 0x6
	// Bit mask of SPI_MEM_PMS_REJECT_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW_Msk = 0x40
	// Bit SPI_MEM_PMS_REJECT_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_PMS_REJECT_INT_RAW = 0x40
	// Position of SPI_MEM_AXI_RADDR_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW_Pos = 0x7
	// Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW_Msk = 0x80
	// Bit SPI_MEM_AXI_RADDR_ERR_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_RADDR_ERR_INT_RAW = 0x80
	// Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_Pos = 0x8
	// Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_Msk = 0x100
	// Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW = 0x100
	// Position of SPI_MEM_AXI_WADDR_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW_Pos = 0x9
	// Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW_Msk = 0x200
	// Bit SPI_MEM_AXI_WADDR_ERR_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_AXI_WADDR_ERR_INT_RAW = 0x200
	// Position of SPI_MEM_DQS0_AFIFO_OVF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_Pos = 0x1c
	// Bit mask of SPI_MEM_DQS0_AFIFO_OVF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_Msk = 0x10000000
	// Bit SPI_MEM_DQS0_AFIFO_OVF_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_DQS0_AFIFO_OVF_INT_RAW = 0x10000000
	// Position of SPI_MEM_DQS1_AFIFO_OVF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_Pos = 0x1d
	// Bit mask of SPI_MEM_DQS1_AFIFO_OVF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_Msk = 0x20000000
	// Bit SPI_MEM_DQS1_AFIFO_OVF_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_DQS1_AFIFO_OVF_INT_RAW = 0x20000000
	// Position of SPI_MEM_BUS_FIFO1_UDF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO1_UDF_INT_RAW_Pos = 0x1e
	// Bit mask of SPI_MEM_BUS_FIFO1_UDF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO1_UDF_INT_RAW_Msk = 0x40000000
	// Bit SPI_MEM_BUS_FIFO1_UDF_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO1_UDF_INT_RAW = 0x40000000
	// Position of SPI_MEM_BUS_FIFO0_UDF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO0_UDF_INT_RAW_Pos = 0x1f
	// Bit mask of SPI_MEM_BUS_FIFO0_UDF_INT_RAW field.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO0_UDF_INT_RAW_Msk = 0x80000000
	// Bit SPI_MEM_BUS_FIFO0_UDF_INT_RAW.
	SPI0_SPI_MEM_INT_RAW_SPI_MEM_BUS_FIFO0_UDF_INT_RAW = 0x80000000

	// SPI_MEM_INT_ST: SPI0 interrupt status register
	// Position of SPI_MEM_SLV_ST_END_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST = 0x10
	// Position of SPI_MEM_ECC_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST_Pos = 0x5
	// Bit mask of SPI_MEM_ECC_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST_Msk = 0x20
	// Bit SPI_MEM_ECC_ERR_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_ECC_ERR_INT_ST = 0x20
	// Position of SPI_MEM_PMS_REJECT_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST_Pos = 0x6
	// Bit mask of SPI_MEM_PMS_REJECT_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST_Msk = 0x40
	// Bit SPI_MEM_PMS_REJECT_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_PMS_REJECT_INT_ST = 0x40
	// Position of SPI_MEM_AXI_RADDR_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST_Pos = 0x7
	// Bit mask of SPI_MEM_AXI_RADDR_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST_Msk = 0x80
	// Bit SPI_MEM_AXI_RADDR_ERR_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_RADDR_ERR_INT_ST = 0x80
	// Position of SPI_MEM_AXI_WR_FLASH_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_Pos = 0x8
	// Bit mask of SPI_MEM_AXI_WR_FLASH_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_Msk = 0x100
	// Bit SPI_MEM_AXI_WR_FLASH_ERR_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WR_FLASH_ERR_INT_ST = 0x100
	// Position of SPI_MEM_AXI_WADDR_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST_Pos = 0x9
	// Bit mask of SPI_MEM_AXI_WADDR_ERR_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST_Msk = 0x200
	// Bit SPI_MEM_AXI_WADDR_ERR_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_AXI_WADDR_ERR_INT_ST = 0x200
	// Position of SPI_MEM_DQS0_AFIFO_OVF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_DQS0_AFIFO_OVF_INT_ST_Pos = 0x1c
	// Bit mask of SPI_MEM_DQS0_AFIFO_OVF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_DQS0_AFIFO_OVF_INT_ST_Msk = 0x10000000
	// Bit SPI_MEM_DQS0_AFIFO_OVF_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_DQS0_AFIFO_OVF_INT_ST = 0x10000000
	// Position of SPI_MEM_DQS1_AFIFO_OVF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_DQS1_AFIFO_OVF_INT_ST_Pos = 0x1d
	// Bit mask of SPI_MEM_DQS1_AFIFO_OVF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_DQS1_AFIFO_OVF_INT_ST_Msk = 0x20000000
	// Bit SPI_MEM_DQS1_AFIFO_OVF_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_DQS1_AFIFO_OVF_INT_ST = 0x20000000
	// Position of SPI_MEM_BUS_FIFO1_UDF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_BUS_FIFO1_UDF_INT_ST_Pos = 0x1e
	// Bit mask of SPI_MEM_BUS_FIFO1_UDF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_BUS_FIFO1_UDF_INT_ST_Msk = 0x40000000
	// Bit SPI_MEM_BUS_FIFO1_UDF_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_BUS_FIFO1_UDF_INT_ST = 0x40000000
	// Position of SPI_MEM_BUS_FIFO0_UDF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_BUS_FIFO0_UDF_INT_ST_Pos = 0x1f
	// Bit mask of SPI_MEM_BUS_FIFO0_UDF_INT_ST field.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_BUS_FIFO0_UDF_INT_ST_Msk = 0x80000000
	// Bit SPI_MEM_BUS_FIFO0_UDF_INT_ST.
	SPI0_SPI_MEM_INT_ST_SPI_MEM_BUS_FIFO0_UDF_INT_ST = 0x80000000

	// SPI_MEM_DDR: SPI0 flash DDR mode control register
	// Position of SPI_FMEM_DDR_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Pos = 0x0
	// Bit mask of SPI_FMEM_DDR_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Msk = 0x1
	// Bit SPI_FMEM_DDR_EN.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_EN = 0x1
	// Position of SPI_FMEM_VAR_DUMMY field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1
	// Bit mask of SPI_FMEM_VAR_DUMMY field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2
	// Bit SPI_FMEM_VAR_DUMMY.
	SPI0_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY = 0x2
	// Position of SPI_FMEM_DDR_RDAT_SWP field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2
	// Bit mask of SPI_FMEM_DDR_RDAT_SWP field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4
	// Bit SPI_FMEM_DDR_RDAT_SWP.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4
	// Position of SPI_FMEM_DDR_WDAT_SWP field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3
	// Bit mask of SPI_FMEM_DDR_WDAT_SWP field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8
	// Bit SPI_FMEM_DDR_WDAT_SWP.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8
	// Position of SPI_FMEM_DDR_CMD_DIS field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4
	// Bit mask of SPI_FMEM_DDR_CMD_DIS field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10
	// Bit SPI_FMEM_DDR_CMD_DIS.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10
	// Position of SPI_FMEM_OUTMINBYTELEN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5
	// Bit mask of SPI_FMEM_OUTMINBYTELEN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0
	// Position of SPI_FMEM_TX_DDR_MSK_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN_Pos = 0xc
	// Bit mask of SPI_FMEM_TX_DDR_MSK_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN_Msk = 0x1000
	// Bit SPI_FMEM_TX_DDR_MSK_EN.
	SPI0_SPI_MEM_DDR_SPI_FMEM_TX_DDR_MSK_EN = 0x1000
	// Position of SPI_FMEM_RX_DDR_MSK_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN_Pos = 0xd
	// Bit mask of SPI_FMEM_RX_DDR_MSK_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN_Msk = 0x2000
	// Bit SPI_FMEM_RX_DDR_MSK_EN.
	SPI0_SPI_MEM_DDR_SPI_FMEM_RX_DDR_MSK_EN = 0x2000
	// Position of SPI_FMEM_USR_DDR_DQS_THD field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe
	// Bit mask of SPI_FMEM_USR_DDR_DQS_THD field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000
	// Position of SPI_FMEM_DDR_DQS_LOOP field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15
	// Bit mask of SPI_FMEM_DDR_DQS_LOOP field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000
	// Bit SPI_FMEM_DDR_DQS_LOOP.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000
	// Position of SPI_FMEM_CLK_DIFF_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18
	// Bit mask of SPI_FMEM_CLK_DIFF_EN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000
	// Bit SPI_FMEM_CLK_DIFF_EN.
	SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000
	// Position of SPI_FMEM_DQS_CA_IN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a
	// Bit mask of SPI_FMEM_DQS_CA_IN field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000
	// Bit SPI_FMEM_DQS_CA_IN.
	SPI0_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000
	// Position of SPI_FMEM_HYPERBUS_DUMMY_2X field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b
	// Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000
	// Bit SPI_FMEM_HYPERBUS_DUMMY_2X.
	SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000
	// Position of SPI_FMEM_CLK_DIFF_INV field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c
	// Bit mask of SPI_FMEM_CLK_DIFF_INV field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000
	// Bit SPI_FMEM_CLK_DIFF_INV.
	SPI0_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000
	// Position of SPI_FMEM_OCTA_RAM_ADDR field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d
	// Bit mask of SPI_FMEM_OCTA_RAM_ADDR field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000
	// Bit SPI_FMEM_OCTA_RAM_ADDR.
	SPI0_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000
	// Position of SPI_FMEM_HYPERBUS_CA field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e
	// Bit mask of SPI_FMEM_HYPERBUS_CA field.
	SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000
	// Bit SPI_FMEM_HYPERBUS_CA.
	SPI0_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000

	// SPI_SMEM_DDR: SPI0 external RAM DDR mode control register
	// Position of EN field.
	SPI0_SPI_SMEM_DDR_EN_Pos = 0x0
	// Bit mask of EN field.
	SPI0_SPI_SMEM_DDR_EN_Msk = 0x1
	// Bit EN.
	SPI0_SPI_SMEM_DDR_EN = 0x1
	// Position of SPI_SMEM_VAR_DUMMY field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Pos = 0x1
	// Bit mask of SPI_SMEM_VAR_DUMMY field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY_Msk = 0x2
	// Bit SPI_SMEM_VAR_DUMMY.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_VAR_DUMMY = 0x2
	// Position of RDAT_SWP field.
	SPI0_SPI_SMEM_DDR_RDAT_SWP_Pos = 0x2
	// Bit mask of RDAT_SWP field.
	SPI0_SPI_SMEM_DDR_RDAT_SWP_Msk = 0x4
	// Bit RDAT_SWP.
	SPI0_SPI_SMEM_DDR_RDAT_SWP = 0x4
	// Position of WDAT_SWP field.
	SPI0_SPI_SMEM_DDR_WDAT_SWP_Pos = 0x3
	// Bit mask of WDAT_SWP field.
	SPI0_SPI_SMEM_DDR_WDAT_SWP_Msk = 0x8
	// Bit WDAT_SWP.
	SPI0_SPI_SMEM_DDR_WDAT_SWP = 0x8
	// Position of CMD_DIS field.
	SPI0_SPI_SMEM_DDR_CMD_DIS_Pos = 0x4
	// Bit mask of CMD_DIS field.
	SPI0_SPI_SMEM_DDR_CMD_DIS_Msk = 0x10
	// Bit CMD_DIS.
	SPI0_SPI_SMEM_DDR_CMD_DIS = 0x10
	// Position of SPI_SMEM_OUTMINBYTELEN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Pos = 0x5
	// Bit mask of SPI_SMEM_OUTMINBYTELEN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_OUTMINBYTELEN_Msk = 0xfe0
	// Position of SPI_SMEM_TX_DDR_MSK_EN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Pos = 0xc
	// Bit mask of SPI_SMEM_TX_DDR_MSK_EN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN_Msk = 0x1000
	// Bit SPI_SMEM_TX_DDR_MSK_EN.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_TX_DDR_MSK_EN = 0x1000
	// Position of SPI_SMEM_RX_DDR_MSK_EN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Pos = 0xd
	// Bit mask of SPI_SMEM_RX_DDR_MSK_EN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN_Msk = 0x2000
	// Bit SPI_SMEM_RX_DDR_MSK_EN.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_RX_DDR_MSK_EN = 0x2000
	// Position of SPI_SMEM_USR_DDR_DQS_THD field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Pos = 0xe
	// Bit mask of SPI_SMEM_USR_DDR_DQS_THD field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_USR_DDR_DQS_THD_Msk = 0x1fc000
	// Position of DQS_LOOP field.
	SPI0_SPI_SMEM_DDR_DQS_LOOP_Pos = 0x15
	// Bit mask of DQS_LOOP field.
	SPI0_SPI_SMEM_DDR_DQS_LOOP_Msk = 0x200000
	// Bit DQS_LOOP.
	SPI0_SPI_SMEM_DDR_DQS_LOOP = 0x200000
	// Position of SPI_SMEM_CLK_DIFF_EN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Pos = 0x18
	// Bit mask of SPI_SMEM_CLK_DIFF_EN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN_Msk = 0x1000000
	// Bit SPI_SMEM_CLK_DIFF_EN.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_EN = 0x1000000
	// Position of SPI_SMEM_DQS_CA_IN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Pos = 0x1a
	// Bit mask of SPI_SMEM_DQS_CA_IN field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN_Msk = 0x4000000
	// Bit SPI_SMEM_DQS_CA_IN.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_DQS_CA_IN = 0x4000000
	// Position of SPI_SMEM_HYPERBUS_DUMMY_2X field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b
	// Bit mask of SPI_SMEM_HYPERBUS_DUMMY_2X field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000
	// Bit SPI_SMEM_HYPERBUS_DUMMY_2X.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_DUMMY_2X = 0x8000000
	// Position of SPI_SMEM_CLK_DIFF_INV field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Pos = 0x1c
	// Bit mask of SPI_SMEM_CLK_DIFF_INV field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV_Msk = 0x10000000
	// Bit SPI_SMEM_CLK_DIFF_INV.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_CLK_DIFF_INV = 0x10000000
	// Position of SPI_SMEM_OCTA_RAM_ADDR field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Pos = 0x1d
	// Bit mask of SPI_SMEM_OCTA_RAM_ADDR field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR_Msk = 0x20000000
	// Bit SPI_SMEM_OCTA_RAM_ADDR.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_OCTA_RAM_ADDR = 0x20000000
	// Position of SPI_SMEM_HYPERBUS_CA field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Pos = 0x1e
	// Bit mask of SPI_SMEM_HYPERBUS_CA field.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA_Msk = 0x40000000
	// Bit SPI_SMEM_HYPERBUS_CA.
	SPI0_SPI_SMEM_DDR_SPI_SMEM_HYPERBUS_CA = 0x40000000

	// SPI_FMEM_PMS0_ATTR: MSPI flash PMS section %s attribute register
	// Position of SPI_FMEM_PMS_RD_ATTR field.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR_Pos = 0x0
	// Bit mask of SPI_FMEM_PMS_RD_ATTR field.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR_Msk = 0x1
	// Bit SPI_FMEM_PMS_RD_ATTR.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_RD_ATTR = 0x1
	// Position of SPI_FMEM_PMS_WR_ATTR field.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR_Pos = 0x1
	// Bit mask of SPI_FMEM_PMS_WR_ATTR field.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR_Msk = 0x2
	// Bit SPI_FMEM_PMS_WR_ATTR.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_WR_ATTR = 0x2
	// Position of SPI_FMEM_PMS_ECC field.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC_Pos = 0x2
	// Bit mask of SPI_FMEM_PMS_ECC field.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC_Msk = 0x4
	// Bit SPI_FMEM_PMS_ECC.
	SPI0_SPI_FMEM_PMS_ATTR_SPI_FMEM_PMS_ECC = 0x4

	// SPI_FMEM_PMS0_ADDR: SPI1 flash PMS section %s start address register
	// Position of S field.
	SPI0_SPI_FMEM_PMS_ADDR_S_Pos = 0x0
	// Bit mask of S field.
	SPI0_SPI_FMEM_PMS_ADDR_S_Msk = 0x7ffffff

	// SPI_FMEM_PMS0_SIZE: SPI1 flash PMS section %s start address register
	// Position of SPI_FMEM_PMS_SIZE field.
	SPI0_SPI_FMEM_PMS_SIZE_SPI_FMEM_PMS_SIZE_Pos = 0x0
	// Bit mask of SPI_FMEM_PMS_SIZE field.
	SPI0_SPI_FMEM_PMS_SIZE_SPI_FMEM_PMS_SIZE_Msk = 0x7fff

	// SPI_SMEM_PMS0_ATTR: SPI1 flash PMS section %s start address register
	// Position of SPI_SMEM_PMS_RD_ATTR field.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR_Pos = 0x0
	// Bit mask of SPI_SMEM_PMS_RD_ATTR field.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR_Msk = 0x1
	// Bit SPI_SMEM_PMS_RD_ATTR.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_RD_ATTR = 0x1
	// Position of SPI_SMEM_PMS_WR_ATTR field.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR_Pos = 0x1
	// Bit mask of SPI_SMEM_PMS_WR_ATTR field.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR_Msk = 0x2
	// Bit SPI_SMEM_PMS_WR_ATTR.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_WR_ATTR = 0x2
	// Position of SPI_SMEM_PMS_ECC field.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC_Pos = 0x2
	// Bit mask of SPI_SMEM_PMS_ECC field.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC_Msk = 0x4
	// Bit SPI_SMEM_PMS_ECC.
	SPI0_SPI_SMEM_PMS_ATTR_SPI_SMEM_PMS_ECC = 0x4

	// SPI_SMEM_PMS0_ADDR: SPI1 external RAM PMS section %s start address register
	// Position of S field.
	SPI0_SPI_SMEM_PMS_ADDR_S_Pos = 0x0
	// Bit mask of S field.
	SPI0_SPI_SMEM_PMS_ADDR_S_Msk = 0x7ffffff

	// SPI_SMEM_PMS0_SIZE: SPI1 external RAM PMS section %s start address register
	// Position of SPI_SMEM_PMS_SIZE field.
	SPI0_SPI_SMEM_PMS_SIZE_SPI_SMEM_PMS_SIZE_Pos = 0x0
	// Bit mask of SPI_SMEM_PMS_SIZE field.
	SPI0_SPI_SMEM_PMS_SIZE_SPI_SMEM_PMS_SIZE_Msk = 0x7fff

	// SPI_MEM_PMS_REJECT: SPI1 access reject register
	// Position of SPI_MEM_REJECT_ADDR field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR_Pos = 0x0
	// Bit mask of SPI_MEM_REJECT_ADDR field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_REJECT_ADDR_Msk = 0x7ffffff
	// Position of SPI_MEM_PM_EN field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN_Pos = 0x1b
	// Bit mask of SPI_MEM_PM_EN field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN_Msk = 0x8000000
	// Bit SPI_MEM_PM_EN.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PM_EN = 0x8000000
	// Position of SPI_MEM_PMS_LD field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD_Pos = 0x1c
	// Bit mask of SPI_MEM_PMS_LD field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD_Msk = 0x10000000
	// Bit SPI_MEM_PMS_LD.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_LD = 0x10000000
	// Position of SPI_MEM_PMS_ST field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST_Pos = 0x1d
	// Bit mask of SPI_MEM_PMS_ST field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST_Msk = 0x20000000
	// Bit SPI_MEM_PMS_ST.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_ST = 0x20000000
	// Position of SPI_MEM_PMS_MULTI_HIT field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT_Pos = 0x1e
	// Bit mask of SPI_MEM_PMS_MULTI_HIT field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT_Msk = 0x40000000
	// Bit SPI_MEM_PMS_MULTI_HIT.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_MULTI_HIT = 0x40000000
	// Position of SPI_MEM_PMS_IVD field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD_Pos = 0x1f
	// Bit mask of SPI_MEM_PMS_IVD field.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD_Msk = 0x80000000
	// Bit SPI_MEM_PMS_IVD.
	SPI0_SPI_MEM_PMS_REJECT_SPI_MEM_PMS_IVD = 0x80000000

	// SPI_MEM_ECC_CTRL: MSPI ECC control register
	// Position of SPI_MEM_ECC_ERR_CNT field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_CNT_Pos = 0x5
	// Bit mask of SPI_MEM_ECC_ERR_CNT field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_CNT_Msk = 0x7e0
	// Position of SPI_FMEM_ECC_ERR_INT_NUM field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM_Pos = 0xb
	// Bit mask of SPI_FMEM_ECC_ERR_INT_NUM field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_NUM_Msk = 0x1f800
	// Position of SPI_FMEM_ECC_ERR_INT_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Pos = 0x11
	// Bit mask of SPI_FMEM_ECC_ERR_INT_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN_Msk = 0x20000
	// Bit SPI_FMEM_ECC_ERR_INT_EN.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ERR_INT_EN = 0x20000
	// Position of SPI_FMEM_PAGE_SIZE field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE_Pos = 0x12
	// Bit mask of SPI_FMEM_PAGE_SIZE field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_PAGE_SIZE_Msk = 0xc0000
	// Position of SPI_FMEM_ECC_ADDR_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN_Pos = 0x14
	// Bit mask of SPI_FMEM_ECC_ADDR_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN_Msk = 0x100000
	// Bit SPI_FMEM_ECC_ADDR_EN.
	SPI0_SPI_MEM_ECC_CTRL_SPI_FMEM_ECC_ADDR_EN = 0x100000
	// Position of SPI_MEM_USR_ECC_ADDR_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN_Pos = 0x15
	// Bit mask of SPI_MEM_USR_ECC_ADDR_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN_Msk = 0x200000
	// Bit SPI_MEM_USR_ECC_ADDR_EN.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_USR_ECC_ADDR_EN = 0x200000
	// Position of SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_Pos = 0x18
	// Bit mask of SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_Msk = 0x1000000
	// Bit SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN = 0x1000000
	// Position of SPI_MEM_ECC_ERR_BITS field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS_Pos = 0x19
	// Bit mask of SPI_MEM_ECC_ERR_BITS field.
	SPI0_SPI_MEM_ECC_CTRL_SPI_MEM_ECC_ERR_BITS_Msk = 0xfe000000

	// SPI_MEM_ECC_ERR_ADDR: MSPI ECC error address register
	// Position of SPI_MEM_ECC_ERR_ADDR field.
	SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_ADDR_Pos = 0x0
	// Bit mask of SPI_MEM_ECC_ERR_ADDR field.
	SPI0_SPI_MEM_ECC_ERR_ADDR_SPI_MEM_ECC_ERR_ADDR_Msk = 0x7ffffff

	// SPI_MEM_AXI_ERR_ADDR: SPI0 AXI request error address.
	// Position of SPI_MEM_AXI_ERR_ADDR field.
	SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_AXI_ERR_ADDR_Pos = 0x0
	// Bit mask of SPI_MEM_AXI_ERR_ADDR field.
	SPI0_SPI_MEM_AXI_ERR_ADDR_SPI_MEM_AXI_ERR_ADDR_Msk = 0x7ffffff

	// SPI_SMEM_ECC_CTRL: MSPI ECC control register
	// Position of SPI_SMEM_ECC_ERR_INT_EN field.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN_Pos = 0x11
	// Bit mask of SPI_SMEM_ECC_ERR_INT_EN field.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN_Msk = 0x20000
	// Bit SPI_SMEM_ECC_ERR_INT_EN.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ERR_INT_EN = 0x20000
	// Position of SPI_SMEM_PAGE_SIZE field.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE_Pos = 0x12
	// Bit mask of SPI_SMEM_PAGE_SIZE field.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_PAGE_SIZE_Msk = 0xc0000
	// Position of SPI_SMEM_ECC_ADDR_EN field.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN_Pos = 0x14
	// Bit mask of SPI_SMEM_ECC_ADDR_EN field.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN_Msk = 0x100000
	// Bit SPI_SMEM_ECC_ADDR_EN.
	SPI0_SPI_SMEM_ECC_CTRL_SPI_SMEM_ECC_ADDR_EN = 0x100000

	// SPI_SMEM_AXI_ADDR_CTRL: SPI0 AXI address control register
	// Position of SPI_MEM_ALL_FIFO_EMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_MEM_ALL_FIFO_EMPTY_Pos = 0x1a
	// Bit mask of SPI_MEM_ALL_FIFO_EMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_MEM_ALL_FIFO_EMPTY_Msk = 0x4000000
	// Bit SPI_MEM_ALL_FIFO_EMPTY.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_MEM_ALL_FIFO_EMPTY = 0x4000000
	// Position of SPI_RDATA_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_RDATA_AFIFO_REMPTY_Pos = 0x1b
	// Bit mask of SPI_RDATA_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_RDATA_AFIFO_REMPTY_Msk = 0x8000000
	// Bit SPI_RDATA_AFIFO_REMPTY.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_RDATA_AFIFO_REMPTY = 0x8000000
	// Position of SPI_RADDR_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_RADDR_AFIFO_REMPTY_Pos = 0x1c
	// Bit mask of SPI_RADDR_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_RADDR_AFIFO_REMPTY_Msk = 0x10000000
	// Bit SPI_RADDR_AFIFO_REMPTY.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_RADDR_AFIFO_REMPTY = 0x10000000
	// Position of SPI_WDATA_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_WDATA_AFIFO_REMPTY_Pos = 0x1d
	// Bit mask of SPI_WDATA_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_WDATA_AFIFO_REMPTY_Msk = 0x20000000
	// Bit SPI_WDATA_AFIFO_REMPTY.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_WDATA_AFIFO_REMPTY = 0x20000000
	// Position of SPI_WBLEN_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_WBLEN_AFIFO_REMPTY_Pos = 0x1e
	// Bit mask of SPI_WBLEN_AFIFO_REMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_WBLEN_AFIFO_REMPTY_Msk = 0x40000000
	// Bit SPI_WBLEN_AFIFO_REMPTY.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_WBLEN_AFIFO_REMPTY = 0x40000000
	// Position of SPI_ALL_AXI_TRANS_AFIFO_EMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_Pos = 0x1f
	// Bit mask of SPI_ALL_AXI_TRANS_AFIFO_EMPTY field.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_Msk = 0x80000000
	// Bit SPI_ALL_AXI_TRANS_AFIFO_EMPTY.
	SPI0_SPI_SMEM_AXI_ADDR_CTRL_SPI_ALL_AXI_TRANS_AFIFO_EMPTY = 0x80000000

	// SPI_MEM_AXI_ERR_RESP_EN: SPI0 AXI error response enable register
	// Position of SPI_MEM_AW_RESP_EN_MMU_VLD field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_VLD_Pos = 0x0
	// Bit mask of SPI_MEM_AW_RESP_EN_MMU_VLD field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_VLD_Msk = 0x1
	// Bit SPI_MEM_AW_RESP_EN_MMU_VLD.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_VLD = 0x1
	// Position of SPI_MEM_AW_RESP_EN_MMU_GID field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_GID_Pos = 0x1
	// Bit mask of SPI_MEM_AW_RESP_EN_MMU_GID field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_GID_Msk = 0x2
	// Bit SPI_MEM_AW_RESP_EN_MMU_GID.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_GID = 0x2
	// Position of SPI_MEM_AW_RESP_EN_AXI_SIZE field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_SIZE_Pos = 0x2
	// Bit mask of SPI_MEM_AW_RESP_EN_AXI_SIZE field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_SIZE_Msk = 0x4
	// Bit SPI_MEM_AW_RESP_EN_AXI_SIZE.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_SIZE = 0x4
	// Position of SPI_MEM_AW_RESP_EN_AXI_FLASH field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_FLASH_Pos = 0x3
	// Bit mask of SPI_MEM_AW_RESP_EN_AXI_FLASH field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_FLASH_Msk = 0x8
	// Bit SPI_MEM_AW_RESP_EN_AXI_FLASH.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_FLASH = 0x8
	// Position of SPI_MEM_AW_RESP_EN_MMU_ECC field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_ECC_Pos = 0x4
	// Bit mask of SPI_MEM_AW_RESP_EN_MMU_ECC field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_ECC_Msk = 0x10
	// Bit SPI_MEM_AW_RESP_EN_MMU_ECC.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_ECC = 0x10
	// Position of SPI_MEM_AW_RESP_EN_MMU_SENS field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_SENS_Pos = 0x5
	// Bit mask of SPI_MEM_AW_RESP_EN_MMU_SENS field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_SENS_Msk = 0x20
	// Bit SPI_MEM_AW_RESP_EN_MMU_SENS.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_MMU_SENS = 0x20
	// Position of SPI_MEM_AW_RESP_EN_AXI_WSTRB field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_WSTRB_Pos = 0x6
	// Bit mask of SPI_MEM_AW_RESP_EN_AXI_WSTRB field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_WSTRB_Msk = 0x40
	// Bit SPI_MEM_AW_RESP_EN_AXI_WSTRB.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AW_RESP_EN_AXI_WSTRB = 0x40
	// Position of SPI_MEM_AR_RESP_EN_MMU_VLD field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_VLD_Pos = 0x7
	// Bit mask of SPI_MEM_AR_RESP_EN_MMU_VLD field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_VLD_Msk = 0x80
	// Bit SPI_MEM_AR_RESP_EN_MMU_VLD.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_VLD = 0x80
	// Position of SPI_MEM_AR_RESP_EN_MMU_GID field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_GID_Pos = 0x8
	// Bit mask of SPI_MEM_AR_RESP_EN_MMU_GID field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_GID_Msk = 0x100
	// Bit SPI_MEM_AR_RESP_EN_MMU_GID.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_GID = 0x100
	// Position of SPI_MEM_AR_RESP_EN_MMU_ECC field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_ECC_Pos = 0x9
	// Bit mask of SPI_MEM_AR_RESP_EN_MMU_ECC field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_ECC_Msk = 0x200
	// Bit SPI_MEM_AR_RESP_EN_MMU_ECC.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_ECC = 0x200
	// Position of SPI_MEM_AR_RESP_EN_MMU_SENS field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_SENS_Pos = 0xa
	// Bit mask of SPI_MEM_AR_RESP_EN_MMU_SENS field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_SENS_Msk = 0x400
	// Bit SPI_MEM_AR_RESP_EN_MMU_SENS.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_MMU_SENS = 0x400
	// Position of SPI_MEM_AR_RESP_EN_AXI_SIZE field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_AXI_SIZE_Pos = 0xb
	// Bit mask of SPI_MEM_AR_RESP_EN_AXI_SIZE field.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_AXI_SIZE_Msk = 0x800
	// Bit SPI_MEM_AR_RESP_EN_AXI_SIZE.
	SPI0_SPI_MEM_AXI_ERR_RESP_EN_SPI_MEM_AR_RESP_EN_AXI_SIZE = 0x800

	// SPI_MEM_TIMING_CALI: SPI0 flash timing calibration register
	// Position of SPI_MEM_TIMING_CLK_ENA field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA_Pos = 0x0
	// Bit mask of SPI_MEM_TIMING_CLK_ENA field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA_Msk = 0x1
	// Bit SPI_MEM_TIMING_CLK_ENA.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CLK_ENA = 0x1
	// Position of SPI_MEM_TIMING_CALI field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Pos = 0x1
	// Bit mask of SPI_MEM_TIMING_CALI field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Msk = 0x2
	// Bit SPI_MEM_TIMING_CALI.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI = 0x2
	// Position of SPI_MEM_EXTRA_DUMMY_CYCLELEN field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2
	// Bit mask of SPI_MEM_EXTRA_DUMMY_CYCLELEN field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c
	// Position of SPI_MEM_DLL_TIMING_CALI field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI_Pos = 0x5
	// Bit mask of SPI_MEM_DLL_TIMING_CALI field.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI_Msk = 0x20
	// Bit SPI_MEM_DLL_TIMING_CALI.
	SPI0_SPI_MEM_TIMING_CALI_SPI_MEM_DLL_TIMING_CALI = 0x20
	// Position of UPDATE field.
	SPI0_SPI_MEM_TIMING_CALI_UPDATE_Pos = 0x6
	// Bit mask of UPDATE field.
	SPI0_SPI_MEM_TIMING_CALI_UPDATE_Msk = 0x40
	// Bit UPDATE.
	SPI0_SPI_MEM_TIMING_CALI_UPDATE = 0x40

	// SPI_MEM_DIN_MODE: MSPI flash input timing delay mode control register
	// Position of SPI_MEM_DIN0_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE_Pos = 0x0
	// Bit mask of SPI_MEM_DIN0_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN0_MODE_Msk = 0x7
	// Position of SPI_MEM_DIN1_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE_Pos = 0x3
	// Bit mask of SPI_MEM_DIN1_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN1_MODE_Msk = 0x38
	// Position of SPI_MEM_DIN2_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE_Pos = 0x6
	// Bit mask of SPI_MEM_DIN2_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN2_MODE_Msk = 0x1c0
	// Position of SPI_MEM_DIN3_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE_Pos = 0x9
	// Bit mask of SPI_MEM_DIN3_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN3_MODE_Msk = 0xe00
	// Position of SPI_MEM_DIN4_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE_Pos = 0xc
	// Bit mask of SPI_MEM_DIN4_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN4_MODE_Msk = 0x7000
	// Position of SPI_MEM_DIN5_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE_Pos = 0xf
	// Bit mask of SPI_MEM_DIN5_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN5_MODE_Msk = 0x38000
	// Position of SPI_MEM_DIN6_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE_Pos = 0x12
	// Bit mask of SPI_MEM_DIN6_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN6_MODE_Msk = 0x1c0000
	// Position of SPI_MEM_DIN7_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE_Pos = 0x15
	// Bit mask of SPI_MEM_DIN7_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DIN7_MODE_Msk = 0xe00000
	// Position of SPI_MEM_DINS_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE_Pos = 0x18
	// Bit mask of SPI_MEM_DINS_MODE field.
	SPI0_SPI_MEM_DIN_MODE_SPI_MEM_DINS_MODE_Msk = 0x7000000

	// SPI_MEM_DIN_NUM: MSPI flash input timing delay number control register
	// Position of SPI_MEM_DIN0_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM_Pos = 0x0
	// Bit mask of SPI_MEM_DIN0_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN0_NUM_Msk = 0x3
	// Position of SPI_MEM_DIN1_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM_Pos = 0x2
	// Bit mask of SPI_MEM_DIN1_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN1_NUM_Msk = 0xc
	// Position of SPI_MEM_DIN2_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM_Pos = 0x4
	// Bit mask of SPI_MEM_DIN2_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN2_NUM_Msk = 0x30
	// Position of SPI_MEM_DIN3_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM_Pos = 0x6
	// Bit mask of SPI_MEM_DIN3_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN3_NUM_Msk = 0xc0
	// Position of SPI_MEM_DIN4_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM_Pos = 0x8
	// Bit mask of SPI_MEM_DIN4_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN4_NUM_Msk = 0x300
	// Position of SPI_MEM_DIN5_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM_Pos = 0xa
	// Bit mask of SPI_MEM_DIN5_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN5_NUM_Msk = 0xc00
	// Position of SPI_MEM_DIN6_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM_Pos = 0xc
	// Bit mask of SPI_MEM_DIN6_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN6_NUM_Msk = 0x3000
	// Position of SPI_MEM_DIN7_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM_Pos = 0xe
	// Bit mask of SPI_MEM_DIN7_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DIN7_NUM_Msk = 0xc000
	// Position of SPI_MEM_DINS_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM_Pos = 0x10
	// Bit mask of SPI_MEM_DINS_NUM field.
	SPI0_SPI_MEM_DIN_NUM_SPI_MEM_DINS_NUM_Msk = 0x30000

	// SPI_MEM_DOUT_MODE: MSPI flash output timing adjustment control register
	// Position of SPI_MEM_DOUT0_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE_Pos = 0x0
	// Bit mask of SPI_MEM_DOUT0_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE_Msk = 0x1
	// Bit SPI_MEM_DOUT0_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT0_MODE = 0x1
	// Position of SPI_MEM_DOUT1_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE_Pos = 0x1
	// Bit mask of SPI_MEM_DOUT1_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE_Msk = 0x2
	// Bit SPI_MEM_DOUT1_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT1_MODE = 0x2
	// Position of SPI_MEM_DOUT2_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE_Pos = 0x2
	// Bit mask of SPI_MEM_DOUT2_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE_Msk = 0x4
	// Bit SPI_MEM_DOUT2_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT2_MODE = 0x4
	// Position of SPI_MEM_DOUT3_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE_Pos = 0x3
	// Bit mask of SPI_MEM_DOUT3_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE_Msk = 0x8
	// Bit SPI_MEM_DOUT3_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT3_MODE = 0x8
	// Position of SPI_MEM_DOUT4_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE_Pos = 0x4
	// Bit mask of SPI_MEM_DOUT4_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE_Msk = 0x10
	// Bit SPI_MEM_DOUT4_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT4_MODE = 0x10
	// Position of SPI_MEM_DOUT5_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE_Pos = 0x5
	// Bit mask of SPI_MEM_DOUT5_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE_Msk = 0x20
	// Bit SPI_MEM_DOUT5_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT5_MODE = 0x20
	// Position of SPI_MEM_DOUT6_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE_Pos = 0x6
	// Bit mask of SPI_MEM_DOUT6_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE_Msk = 0x40
	// Bit SPI_MEM_DOUT6_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT6_MODE = 0x40
	// Position of SPI_MEM_DOUT7_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE_Pos = 0x7
	// Bit mask of SPI_MEM_DOUT7_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE_Msk = 0x80
	// Bit SPI_MEM_DOUT7_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUT7_MODE = 0x80
	// Position of SPI_MEM_DOUTS_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE_Pos = 0x8
	// Bit mask of SPI_MEM_DOUTS_MODE field.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE_Msk = 0x100
	// Bit SPI_MEM_DOUTS_MODE.
	SPI0_SPI_MEM_DOUT_MODE_SPI_MEM_DOUTS_MODE = 0x100

	// SPI_SMEM_TIMING_CALI: MSPI external RAM timing calibration register
	// Position of SPI_SMEM_TIMING_CLK_ENA field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Pos = 0x0
	// Bit mask of SPI_SMEM_TIMING_CLK_ENA field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA_Msk = 0x1
	// Bit SPI_SMEM_TIMING_CLK_ENA.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CLK_ENA = 0x1
	// Position of SPI_SMEM_TIMING_CALI field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Pos = 0x1
	// Bit mask of SPI_SMEM_TIMING_CALI field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI_Msk = 0x2
	// Bit SPI_SMEM_TIMING_CALI.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_TIMING_CALI = 0x2
	// Position of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2
	// Bit mask of SPI_SMEM_EXTRA_DUMMY_CYCLELEN field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c
	// Position of SPI_SMEM_DLL_TIMING_CALI field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI_Pos = 0x5
	// Bit mask of SPI_SMEM_DLL_TIMING_CALI field.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI_Msk = 0x20
	// Bit SPI_SMEM_DLL_TIMING_CALI.
	SPI0_SPI_SMEM_TIMING_CALI_SPI_SMEM_DLL_TIMING_CALI = 0x20

	// SPI_SMEM_DIN_MODE: MSPI external RAM input timing delay mode control register
	// Position of SPI_SMEM_DIN0_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Pos = 0x0
	// Bit mask of SPI_SMEM_DIN0_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN0_MODE_Msk = 0x7
	// Position of SPI_SMEM_DIN1_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Pos = 0x3
	// Bit mask of SPI_SMEM_DIN1_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN1_MODE_Msk = 0x38
	// Position of SPI_SMEM_DIN2_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Pos = 0x6
	// Bit mask of SPI_SMEM_DIN2_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN2_MODE_Msk = 0x1c0
	// Position of SPI_SMEM_DIN3_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Pos = 0x9
	// Bit mask of SPI_SMEM_DIN3_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN3_MODE_Msk = 0xe00
	// Position of SPI_SMEM_DIN4_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Pos = 0xc
	// Bit mask of SPI_SMEM_DIN4_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN4_MODE_Msk = 0x7000
	// Position of SPI_SMEM_DIN5_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Pos = 0xf
	// Bit mask of SPI_SMEM_DIN5_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN5_MODE_Msk = 0x38000
	// Position of SPI_SMEM_DIN6_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Pos = 0x12
	// Bit mask of SPI_SMEM_DIN6_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN6_MODE_Msk = 0x1c0000
	// Position of SPI_SMEM_DIN7_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Pos = 0x15
	// Bit mask of SPI_SMEM_DIN7_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DIN7_MODE_Msk = 0xe00000
	// Position of SPI_SMEM_DINS_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Pos = 0x18
	// Bit mask of SPI_SMEM_DINS_MODE field.
	SPI0_SPI_SMEM_DIN_MODE_SPI_SMEM_DINS_MODE_Msk = 0x7000000

	// SPI_SMEM_DIN_NUM: MSPI external RAM input timing delay number control register
	// Position of SPI_SMEM_DIN0_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Pos = 0x0
	// Bit mask of SPI_SMEM_DIN0_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN0_NUM_Msk = 0x3
	// Position of SPI_SMEM_DIN1_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Pos = 0x2
	// Bit mask of SPI_SMEM_DIN1_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN1_NUM_Msk = 0xc
	// Position of SPI_SMEM_DIN2_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Pos = 0x4
	// Bit mask of SPI_SMEM_DIN2_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN2_NUM_Msk = 0x30
	// Position of SPI_SMEM_DIN3_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Pos = 0x6
	// Bit mask of SPI_SMEM_DIN3_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN3_NUM_Msk = 0xc0
	// Position of SPI_SMEM_DIN4_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Pos = 0x8
	// Bit mask of SPI_SMEM_DIN4_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN4_NUM_Msk = 0x300
	// Position of SPI_SMEM_DIN5_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Pos = 0xa
	// Bit mask of SPI_SMEM_DIN5_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN5_NUM_Msk = 0xc00
	// Position of SPI_SMEM_DIN6_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Pos = 0xc
	// Bit mask of SPI_SMEM_DIN6_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN6_NUM_Msk = 0x3000
	// Position of SPI_SMEM_DIN7_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Pos = 0xe
	// Bit mask of SPI_SMEM_DIN7_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DIN7_NUM_Msk = 0xc000
	// Position of SPI_SMEM_DINS_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Pos = 0x10
	// Bit mask of SPI_SMEM_DINS_NUM field.
	SPI0_SPI_SMEM_DIN_NUM_SPI_SMEM_DINS_NUM_Msk = 0x30000

	// SPI_SMEM_DOUT_MODE: MSPI external RAM output timing adjustment control register
	// Position of SPI_SMEM_DOUT0_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Pos = 0x0
	// Bit mask of SPI_SMEM_DOUT0_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE_Msk = 0x1
	// Bit SPI_SMEM_DOUT0_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT0_MODE = 0x1
	// Position of SPI_SMEM_DOUT1_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Pos = 0x1
	// Bit mask of SPI_SMEM_DOUT1_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE_Msk = 0x2
	// Bit SPI_SMEM_DOUT1_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT1_MODE = 0x2
	// Position of SPI_SMEM_DOUT2_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Pos = 0x2
	// Bit mask of SPI_SMEM_DOUT2_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE_Msk = 0x4
	// Bit SPI_SMEM_DOUT2_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT2_MODE = 0x4
	// Position of SPI_SMEM_DOUT3_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Pos = 0x3
	// Bit mask of SPI_SMEM_DOUT3_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE_Msk = 0x8
	// Bit SPI_SMEM_DOUT3_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT3_MODE = 0x8
	// Position of SPI_SMEM_DOUT4_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Pos = 0x4
	// Bit mask of SPI_SMEM_DOUT4_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE_Msk = 0x10
	// Bit SPI_SMEM_DOUT4_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT4_MODE = 0x10
	// Position of SPI_SMEM_DOUT5_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Pos = 0x5
	// Bit mask of SPI_SMEM_DOUT5_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE_Msk = 0x20
	// Bit SPI_SMEM_DOUT5_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT5_MODE = 0x20
	// Position of SPI_SMEM_DOUT6_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Pos = 0x6
	// Bit mask of SPI_SMEM_DOUT6_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE_Msk = 0x40
	// Bit SPI_SMEM_DOUT6_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT6_MODE = 0x40
	// Position of SPI_SMEM_DOUT7_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Pos = 0x7
	// Bit mask of SPI_SMEM_DOUT7_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE_Msk = 0x80
	// Bit SPI_SMEM_DOUT7_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUT7_MODE = 0x80
	// Position of SPI_SMEM_DOUTS_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Pos = 0x8
	// Bit mask of SPI_SMEM_DOUTS_MODE field.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE_Msk = 0x100
	// Bit SPI_SMEM_DOUTS_MODE.
	SPI0_SPI_SMEM_DOUT_MODE_SPI_SMEM_DOUTS_MODE = 0x100

	// SPI_SMEM_AC: MSPI external RAM ECC and SPI CS timing control register
	// Position of SPI_SMEM_CS_SETUP field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Pos = 0x0
	// Bit mask of SPI_SMEM_CS_SETUP field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_Msk = 0x1
	// Bit SPI_SMEM_CS_SETUP.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP = 0x1
	// Position of SPI_SMEM_CS_HOLD field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Pos = 0x1
	// Bit mask of SPI_SMEM_CS_HOLD field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_Msk = 0x2
	// Bit SPI_SMEM_CS_HOLD.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD = 0x2
	// Position of SPI_SMEM_CS_SETUP_TIME field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Pos = 0x2
	// Bit mask of SPI_SMEM_CS_SETUP_TIME field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_SETUP_TIME_Msk = 0x7c
	// Position of SPI_SMEM_CS_HOLD_TIME field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Pos = 0x7
	// Bit mask of SPI_SMEM_CS_HOLD_TIME field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_TIME_Msk = 0xf80
	// Position of SPI_SMEM_ECC_CS_HOLD_TIME field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Pos = 0xc
	// Bit mask of SPI_SMEM_ECC_CS_HOLD_TIME field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_CS_HOLD_TIME_Msk = 0x7000
	// Position of SPI_SMEM_ECC_SKIP_PAGE_CORNER field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Pos = 0xf
	// Bit mask of SPI_SMEM_ECC_SKIP_PAGE_CORNER field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER_Msk = 0x8000
	// Bit SPI_SMEM_ECC_SKIP_PAGE_CORNER.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_SKIP_PAGE_CORNER = 0x8000
	// Position of SPI_SMEM_ECC_16TO18_BYTE_EN field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Pos = 0x10
	// Bit mask of SPI_SMEM_ECC_16TO18_BYTE_EN field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN_Msk = 0x10000
	// Bit SPI_SMEM_ECC_16TO18_BYTE_EN.
	SPI0_SPI_SMEM_AC_SPI_SMEM_ECC_16TO18_BYTE_EN = 0x10000
	// Position of SPI_SMEM_CS_HOLD_DELAY field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Pos = 0x19
	// Bit mask of SPI_SMEM_CS_HOLD_DELAY field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_CS_HOLD_DELAY_Msk = 0x7e000000
	// Position of SPI_SMEM_SPLIT_TRANS_EN field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN_Pos = 0x1f
	// Bit mask of SPI_SMEM_SPLIT_TRANS_EN field.
	SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN_Msk = 0x80000000
	// Bit SPI_SMEM_SPLIT_TRANS_EN.
	SPI0_SPI_SMEM_AC_SPI_SMEM_SPLIT_TRANS_EN = 0x80000000

	// SPI_SMEM_DIN_HEX_MODE: MSPI 16x external RAM input timing delay mode control register
	// Position of SPI_SMEM_DIN08_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN08_MODE_Pos = 0x0
	// Bit mask of SPI_SMEM_DIN08_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN08_MODE_Msk = 0x7
	// Position of SPI_SMEM_DIN09_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN09_MODE_Pos = 0x3
	// Bit mask of SPI_SMEM_DIN09_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN09_MODE_Msk = 0x38
	// Position of SPI_SMEM_DIN10_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN10_MODE_Pos = 0x6
	// Bit mask of SPI_SMEM_DIN10_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN10_MODE_Msk = 0x1c0
	// Position of SPI_SMEM_DIN11_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN11_MODE_Pos = 0x9
	// Bit mask of SPI_SMEM_DIN11_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN11_MODE_Msk = 0xe00
	// Position of SPI_SMEM_DIN12_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN12_MODE_Pos = 0xc
	// Bit mask of SPI_SMEM_DIN12_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN12_MODE_Msk = 0x7000
	// Position of SPI_SMEM_DIN13_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN13_MODE_Pos = 0xf
	// Bit mask of SPI_SMEM_DIN13_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN13_MODE_Msk = 0x38000
	// Position of SPI_SMEM_DIN14_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN14_MODE_Pos = 0x12
	// Bit mask of SPI_SMEM_DIN14_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN14_MODE_Msk = 0x1c0000
	// Position of SPI_SMEM_DIN15_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN15_MODE_Pos = 0x15
	// Bit mask of SPI_SMEM_DIN15_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DIN15_MODE_Msk = 0xe00000
	// Position of SPI_SMEM_DINS_HEX_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DINS_HEX_MODE_Pos = 0x18
	// Bit mask of SPI_SMEM_DINS_HEX_MODE field.
	SPI0_SPI_SMEM_DIN_HEX_MODE_SPI_SMEM_DINS_HEX_MODE_Msk = 0x7000000

	// SPI_SMEM_DIN_HEX_NUM: MSPI 16x external RAM input timing delay number control register
	// Position of SPI_SMEM_DIN08_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN08_NUM_Pos = 0x0
	// Bit mask of SPI_SMEM_DIN08_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN08_NUM_Msk = 0x3
	// Position of SPI_SMEM_DIN09_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN09_NUM_Pos = 0x2
	// Bit mask of SPI_SMEM_DIN09_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN09_NUM_Msk = 0xc
	// Position of SPI_SMEM_DIN10_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN10_NUM_Pos = 0x4
	// Bit mask of SPI_SMEM_DIN10_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN10_NUM_Msk = 0x30
	// Position of SPI_SMEM_DIN11_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN11_NUM_Pos = 0x6
	// Bit mask of SPI_SMEM_DIN11_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN11_NUM_Msk = 0xc0
	// Position of SPI_SMEM_DIN12_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN12_NUM_Pos = 0x8
	// Bit mask of SPI_SMEM_DIN12_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN12_NUM_Msk = 0x300
	// Position of SPI_SMEM_DIN13_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN13_NUM_Pos = 0xa
	// Bit mask of SPI_SMEM_DIN13_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN13_NUM_Msk = 0xc00
	// Position of SPI_SMEM_DIN14_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN14_NUM_Pos = 0xc
	// Bit mask of SPI_SMEM_DIN14_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN14_NUM_Msk = 0x3000
	// Position of SPI_SMEM_DIN15_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN15_NUM_Pos = 0xe
	// Bit mask of SPI_SMEM_DIN15_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DIN15_NUM_Msk = 0xc000
	// Position of SPI_SMEM_DINS_HEX_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DINS_HEX_NUM_Pos = 0x10
	// Bit mask of SPI_SMEM_DINS_HEX_NUM field.
	SPI0_SPI_SMEM_DIN_HEX_NUM_SPI_SMEM_DINS_HEX_NUM_Msk = 0x30000

	// SPI_SMEM_DOUT_HEX_MODE: MSPI 16x external RAM output timing adjustment control register
	// Position of SPI_SMEM_DOUT08_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT08_MODE_Pos = 0x0
	// Bit mask of SPI_SMEM_DOUT08_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT08_MODE_Msk = 0x1
	// Bit SPI_SMEM_DOUT08_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT08_MODE = 0x1
	// Position of SPI_SMEM_DOUT09_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT09_MODE_Pos = 0x1
	// Bit mask of SPI_SMEM_DOUT09_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT09_MODE_Msk = 0x2
	// Bit SPI_SMEM_DOUT09_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT09_MODE = 0x2
	// Position of SPI_SMEM_DOUT10_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT10_MODE_Pos = 0x2
	// Bit mask of SPI_SMEM_DOUT10_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT10_MODE_Msk = 0x4
	// Bit SPI_SMEM_DOUT10_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT10_MODE = 0x4
	// Position of SPI_SMEM_DOUT11_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT11_MODE_Pos = 0x3
	// Bit mask of SPI_SMEM_DOUT11_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT11_MODE_Msk = 0x8
	// Bit SPI_SMEM_DOUT11_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT11_MODE = 0x8
	// Position of SPI_SMEM_DOUT12_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT12_MODE_Pos = 0x4
	// Bit mask of SPI_SMEM_DOUT12_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT12_MODE_Msk = 0x10
	// Bit SPI_SMEM_DOUT12_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT12_MODE = 0x10
	// Position of SPI_SMEM_DOUT13_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT13_MODE_Pos = 0x5
	// Bit mask of SPI_SMEM_DOUT13_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT13_MODE_Msk = 0x20
	// Bit SPI_SMEM_DOUT13_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT13_MODE = 0x20
	// Position of SPI_SMEM_DOUT14_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT14_MODE_Pos = 0x6
	// Bit mask of SPI_SMEM_DOUT14_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT14_MODE_Msk = 0x40
	// Bit SPI_SMEM_DOUT14_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT14_MODE = 0x40
	// Position of SPI_SMEM_DOUT15_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT15_MODE_Pos = 0x7
	// Bit mask of SPI_SMEM_DOUT15_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT15_MODE_Msk = 0x80
	// Bit SPI_SMEM_DOUT15_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUT15_MODE = 0x80
	// Position of SPI_SMEM_DOUTS_HEX_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUTS_HEX_MODE_Pos = 0x8
	// Bit mask of SPI_SMEM_DOUTS_HEX_MODE field.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUTS_HEX_MODE_Msk = 0x100
	// Bit SPI_SMEM_DOUTS_HEX_MODE.
	SPI0_SPI_SMEM_DOUT_HEX_MODE_SPI_SMEM_DOUTS_HEX_MODE = 0x100

	// SPI_MEM_CLOCK_GATE: SPI0 clock gate register
	// Position of SPI_CLK_EN field.
	SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN_Pos = 0x0
	// Bit mask of SPI_CLK_EN field.
	SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN_Msk = 0x1
	// Bit SPI_CLK_EN.
	SPI0_SPI_MEM_CLOCK_GATE_SPI_CLK_EN = 0x1

	// SPI_MEM_XTS_PLAIN_BASE: The base address of the memory that stores plaintext in Manual Encryption
	// Position of SPI_XTS_PLAIN field.
	SPI0_SPI_MEM_XTS_PLAIN_BASE_SPI_XTS_PLAIN_Pos = 0x0
	// Bit mask of SPI_XTS_PLAIN field.
	SPI0_SPI_MEM_XTS_PLAIN_BASE_SPI_XTS_PLAIN_Msk = 0xffffffff

	// SPI_MEM_XTS_LINESIZE: Manual Encryption Line-Size register
	// Position of SPI_XTS_LINESIZE field.
	SPI0_SPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE_Pos = 0x0
	// Bit mask of SPI_XTS_LINESIZE field.
	SPI0_SPI_MEM_XTS_LINESIZE_SPI_XTS_LINESIZE_Msk = 0x3

	// SPI_MEM_XTS_DESTINATION: Manual Encryption destination register
	// Position of SPI_XTS_DESTINATION field.
	SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION_Pos = 0x0
	// Bit mask of SPI_XTS_DESTINATION field.
	SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION_Msk = 0x1
	// Bit SPI_XTS_DESTINATION.
	SPI0_SPI_MEM_XTS_DESTINATION_SPI_XTS_DESTINATION = 0x1

	// SPI_MEM_XTS_PHYSICAL_ADDRESS: Manual Encryption physical address register
	// Position of SPI_XTS_PHYSICAL_ADDRESS field.
	SPI0_SPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS_Pos = 0x0
	// Bit mask of SPI_XTS_PHYSICAL_ADDRESS field.
	SPI0_SPI_MEM_XTS_PHYSICAL_ADDRESS_SPI_XTS_PHYSICAL_ADDRESS_Msk = 0x3ffffff

	// SPI_MEM_XTS_TRIGGER: Manual Encryption physical address register
	// Position of SPI_XTS_TRIGGER field.
	SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER_Pos = 0x0
	// Bit mask of SPI_XTS_TRIGGER field.
	SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER_Msk = 0x1
	// Bit SPI_XTS_TRIGGER.
	SPI0_SPI_MEM_XTS_TRIGGER_SPI_XTS_TRIGGER = 0x1

	// SPI_MEM_XTS_RELEASE: Manual Encryption physical address register
	// Position of SPI_XTS_RELEASE field.
	SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE_Pos = 0x0
	// Bit mask of SPI_XTS_RELEASE field.
	SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE_Msk = 0x1
	// Bit SPI_XTS_RELEASE.
	SPI0_SPI_MEM_XTS_RELEASE_SPI_XTS_RELEASE = 0x1

	// SPI_MEM_XTS_DESTROY: Manual Encryption physical address register
	// Position of SPI_XTS_DESTROY field.
	SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY_Pos = 0x0
	// Bit mask of SPI_XTS_DESTROY field.
	SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY_Msk = 0x1
	// Bit SPI_XTS_DESTROY.
	SPI0_SPI_MEM_XTS_DESTROY_SPI_XTS_DESTROY = 0x1

	// SPI_MEM_XTS_STATE: Manual Encryption physical address register
	// Position of SPI_XTS_STATE field.
	SPI0_SPI_MEM_XTS_STATE_SPI_XTS_STATE_Pos = 0x0
	// Bit mask of SPI_XTS_STATE field.
	SPI0_SPI_MEM_XTS_STATE_SPI_XTS_STATE_Msk = 0x3

	// SPI_MEM_XTS_DATE: Manual Encryption version register
	// Position of SPI_XTS_DATE field.
	SPI0_SPI_MEM_XTS_DATE_SPI_XTS_DATE_Pos = 0x0
	// Bit mask of SPI_XTS_DATE field.
	SPI0_SPI_MEM_XTS_DATE_SPI_XTS_DATE_Msk = 0x3fffffff

	// SPI_MEM_MMU_ITEM_CONTENT: MSPI-MMU item content register
	// Position of SPI_MMU_ITEM_CONTENT field.
	SPI0_SPI_MEM_MMU_ITEM_CONTENT_SPI_MMU_ITEM_CONTENT_Pos = 0x0
	// Bit mask of SPI_MMU_ITEM_CONTENT field.
	SPI0_SPI_MEM_MMU_ITEM_CONTENT_SPI_MMU_ITEM_CONTENT_Msk = 0xffffffff

	// SPI_MEM_MMU_ITEM_INDEX: MSPI-MMU item index register
	// Position of SPI_MMU_ITEM_INDEX field.
	SPI0_SPI_MEM_MMU_ITEM_INDEX_SPI_MMU_ITEM_INDEX_Pos = 0x0
	// Bit mask of SPI_MMU_ITEM_INDEX field.
	SPI0_SPI_MEM_MMU_ITEM_INDEX_SPI_MMU_ITEM_INDEX_Msk = 0xffffffff

	// SPI_MEM_MMU_POWER_CTRL: MSPI MMU power control register
	// Position of SPI_MMU_MEM_FORCE_ON field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON_Pos = 0x0
	// Bit mask of SPI_MMU_MEM_FORCE_ON field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON_Msk = 0x1
	// Bit SPI_MMU_MEM_FORCE_ON.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_ON = 0x1
	// Position of SPI_MMU_MEM_FORCE_PD field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD_Pos = 0x1
	// Bit mask of SPI_MMU_MEM_FORCE_PD field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD_Msk = 0x2
	// Bit SPI_MMU_MEM_FORCE_PD.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PD = 0x2
	// Position of SPI_MMU_MEM_FORCE_PU field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU_Pos = 0x2
	// Bit mask of SPI_MMU_MEM_FORCE_PU field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU_Msk = 0x4
	// Bit SPI_MMU_MEM_FORCE_PU.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MMU_MEM_FORCE_PU = 0x4
	// Position of SPI_MEM_AUX_CTRL field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL_Pos = 0x10
	// Bit mask of SPI_MEM_AUX_CTRL field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_AUX_CTRL_Msk = 0x3fff0000
	// Position of SPI_MEM_RDN_ENA field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA_Pos = 0x1e
	// Bit mask of SPI_MEM_RDN_ENA field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA_Msk = 0x40000000
	// Bit SPI_MEM_RDN_ENA.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_ENA = 0x40000000
	// Position of SPI_MEM_RDN_RESULT field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT_Pos = 0x1f
	// Bit mask of SPI_MEM_RDN_RESULT field.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT_Msk = 0x80000000
	// Bit SPI_MEM_RDN_RESULT.
	SPI0_SPI_MEM_MMU_POWER_CTRL_SPI_MEM_RDN_RESULT = 0x80000000

	// SPI_MEM_DPA_CTRL: SPI memory cryption DPA register
	// Position of SPI_CRYPT_SECURITY_LEVEL field.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL_Pos = 0x0
	// Bit mask of SPI_CRYPT_SECURITY_LEVEL field.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_SECURITY_LEVEL_Msk = 0x7
	// Position of SPI_CRYPT_CALC_D_DPA_EN field.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN_Pos = 0x3
	// Bit mask of SPI_CRYPT_CALC_D_DPA_EN field.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN_Msk = 0x8
	// Bit SPI_CRYPT_CALC_D_DPA_EN.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_CALC_D_DPA_EN = 0x8
	// Position of SPI_CRYPT_DPA_SELECT_REGISTER field.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER_Pos = 0x4
	// Bit mask of SPI_CRYPT_DPA_SELECT_REGISTER field.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER_Msk = 0x10
	// Bit SPI_CRYPT_DPA_SELECT_REGISTER.
	SPI0_SPI_MEM_DPA_CTRL_SPI_CRYPT_DPA_SELECT_REGISTER = 0x10

	// SPI_MEM_REGISTERRND_ECO_HIGH: MSPI ECO high register
	// Position of SPI_MEM_REGISTERRND_ECO_HIGH field.
	SPI0_SPI_MEM_REGISTERRND_ECO_HIGH_SPI_MEM_REGISTERRND_ECO_HIGH_Pos = 0x0
	// Bit mask of SPI_MEM_REGISTERRND_ECO_HIGH field.
	SPI0_SPI_MEM_REGISTERRND_ECO_HIGH_SPI_MEM_REGISTERRND_ECO_HIGH_Msk = 0xffffffff

	// SPI_MEM_REGISTERRND_ECO_LOW: MSPI ECO low register
	// Position of SPI_MEM_REGISTERRND_ECO_LOW field.
	SPI0_SPI_MEM_REGISTERRND_ECO_LOW_SPI_MEM_REGISTERRND_ECO_LOW_Pos = 0x0
	// Bit mask of SPI_MEM_REGISTERRND_ECO_LOW field.
	SPI0_SPI_MEM_REGISTERRND_ECO_LOW_SPI_MEM_REGISTERRND_ECO_LOW_Msk = 0xffffffff

	// SPI_MEM_DATE: SPI0 version control register
	// Position of SPI_MEM_DATE field.
	SPI0_SPI_MEM_DATE_SPI_MEM_DATE_Pos = 0x0
	// Bit mask of SPI_MEM_DATE field.
	SPI0_SPI_MEM_DATE_SPI_MEM_DATE_Msk = 0xfffffff
)

// Constants for SPI1: SPI (Serial Peripheral Interface) Controller 1
const (
	// SPI_MEM_CMD: SPI1 memory command register
	// Position of SPI_MEM_MST_ST field.
	SPI1_SPI_MEM_CMD_SPI_MEM_MST_ST_Pos = 0x0
	// Bit mask of SPI_MEM_MST_ST field.
	SPI1_SPI_MEM_CMD_SPI_MEM_MST_ST_Msk = 0xf
	// Position of SPI_MEM_SLV_ST field.
	SPI1_SPI_MEM_CMD_SPI_MEM_SLV_ST_Pos = 0x4
	// Bit mask of SPI_MEM_SLV_ST field.
	SPI1_SPI_MEM_CMD_SPI_MEM_SLV_ST_Msk = 0xf0
	// Position of SPI_MEM_FLASH_PE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE_Pos = 0x11
	// Bit mask of SPI_MEM_FLASH_PE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE_Msk = 0x20000
	// Bit SPI_MEM_FLASH_PE.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PE = 0x20000
	// Position of SPI_MEM_USR field.
	SPI1_SPI_MEM_CMD_SPI_MEM_USR_Pos = 0x12
	// Bit mask of SPI_MEM_USR field.
	SPI1_SPI_MEM_CMD_SPI_MEM_USR_Msk = 0x40000
	// Bit SPI_MEM_USR.
	SPI1_SPI_MEM_CMD_SPI_MEM_USR = 0x40000
	// Position of SPI_MEM_FLASH_HPM field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM_Pos = 0x13
	// Bit mask of SPI_MEM_FLASH_HPM field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM_Msk = 0x80000
	// Bit SPI_MEM_FLASH_HPM.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_HPM = 0x80000
	// Position of SPI_MEM_FLASH_RES field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES_Pos = 0x14
	// Bit mask of SPI_MEM_FLASH_RES field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES_Msk = 0x100000
	// Bit SPI_MEM_FLASH_RES.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RES = 0x100000
	// Position of SPI_MEM_FLASH_DP field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP_Pos = 0x15
	// Bit mask of SPI_MEM_FLASH_DP field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP_Msk = 0x200000
	// Bit SPI_MEM_FLASH_DP.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_DP = 0x200000
	// Position of SPI_MEM_FLASH_CE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE_Pos = 0x16
	// Bit mask of SPI_MEM_FLASH_CE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE_Msk = 0x400000
	// Bit SPI_MEM_FLASH_CE.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_CE = 0x400000
	// Position of SPI_MEM_FLASH_BE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE_Pos = 0x17
	// Bit mask of SPI_MEM_FLASH_BE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE_Msk = 0x800000
	// Bit SPI_MEM_FLASH_BE.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_BE = 0x800000
	// Position of SPI_MEM_FLASH_SE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE_Pos = 0x18
	// Bit mask of SPI_MEM_FLASH_SE field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE_Msk = 0x1000000
	// Bit SPI_MEM_FLASH_SE.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_SE = 0x1000000
	// Position of SPI_MEM_FLASH_PP field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP_Pos = 0x19
	// Bit mask of SPI_MEM_FLASH_PP field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP_Msk = 0x2000000
	// Bit SPI_MEM_FLASH_PP.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_PP = 0x2000000
	// Position of SPI_MEM_FLASH_WRSR field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR_Pos = 0x1a
	// Bit mask of SPI_MEM_FLASH_WRSR field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR_Msk = 0x4000000
	// Bit SPI_MEM_FLASH_WRSR.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRSR = 0x4000000
	// Position of SPI_MEM_FLASH_RDSR field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR_Pos = 0x1b
	// Bit mask of SPI_MEM_FLASH_RDSR field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR_Msk = 0x8000000
	// Bit SPI_MEM_FLASH_RDSR.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDSR = 0x8000000
	// Position of SPI_MEM_FLASH_RDID field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID_Pos = 0x1c
	// Bit mask of SPI_MEM_FLASH_RDID field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID_Msk = 0x10000000
	// Bit SPI_MEM_FLASH_RDID.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_RDID = 0x10000000
	// Position of SPI_MEM_FLASH_WRDI field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI_Pos = 0x1d
	// Bit mask of SPI_MEM_FLASH_WRDI field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI_Msk = 0x20000000
	// Bit SPI_MEM_FLASH_WRDI.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WRDI = 0x20000000
	// Position of SPI_MEM_FLASH_WREN field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN_Pos = 0x1e
	// Bit mask of SPI_MEM_FLASH_WREN field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN_Msk = 0x40000000
	// Bit SPI_MEM_FLASH_WREN.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_WREN = 0x40000000
	// Position of SPI_MEM_FLASH_READ field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ_Pos = 0x1f
	// Bit mask of SPI_MEM_FLASH_READ field.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ_Msk = 0x80000000
	// Bit SPI_MEM_FLASH_READ.
	SPI1_SPI_MEM_CMD_SPI_MEM_FLASH_READ = 0x80000000

	// SPI_MEM_ADDR: SPI1 address register
	// Position of SPI_MEM_USR_ADDR_VALUE field.
	SPI1_SPI_MEM_ADDR_SPI_MEM_USR_ADDR_VALUE_Pos = 0x0
	// Bit mask of SPI_MEM_USR_ADDR_VALUE field.
	SPI1_SPI_MEM_ADDR_SPI_MEM_USR_ADDR_VALUE_Msk = 0xffffffff

	// SPI_MEM_CTRL: SPI1 control register.
	// Position of SPI_MEM_FDUMMY_RIN field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Pos = 0x2
	// Bit mask of SPI_MEM_FDUMMY_RIN field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN_Msk = 0x4
	// Bit SPI_MEM_FDUMMY_RIN.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_RIN = 0x4
	// Position of SPI_MEM_FDUMMY_WOUT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Pos = 0x3
	// Bit mask of SPI_MEM_FDUMMY_WOUT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT_Msk = 0x8
	// Bit SPI_MEM_FDUMMY_WOUT.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDUMMY_WOUT = 0x8
	// Position of SPI_MEM_FDOUT_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Pos = 0x4
	// Bit mask of SPI_MEM_FDOUT_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT_Msk = 0x10
	// Bit SPI_MEM_FDOUT_OCT.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDOUT_OCT = 0x10
	// Position of SPI_MEM_FDIN_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Pos = 0x5
	// Bit mask of SPI_MEM_FDIN_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT_Msk = 0x20
	// Bit SPI_MEM_FDIN_OCT.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FDIN_OCT = 0x20
	// Position of SPI_MEM_FADDR_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Pos = 0x6
	// Bit mask of SPI_MEM_FADDR_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT_Msk = 0x40
	// Bit SPI_MEM_FADDR_OCT.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FADDR_OCT = 0x40
	// Position of SPI_MEM_FCMD_QUAD field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Pos = 0x8
	// Bit mask of SPI_MEM_FCMD_QUAD field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD_Msk = 0x100
	// Bit SPI_MEM_FCMD_QUAD.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_QUAD = 0x100
	// Position of SPI_MEM_FCMD_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Pos = 0x9
	// Bit mask of SPI_MEM_FCMD_OCT field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT_Msk = 0x200
	// Bit SPI_MEM_FCMD_OCT.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCMD_OCT = 0x200
	// Position of SPI_MEM_FCS_CRC_EN field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN_Pos = 0xa
	// Bit mask of SPI_MEM_FCS_CRC_EN field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN_Msk = 0x400
	// Bit SPI_MEM_FCS_CRC_EN.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FCS_CRC_EN = 0x400
	// Position of SPI_MEM_TX_CRC_EN field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN_Pos = 0xb
	// Bit mask of SPI_MEM_TX_CRC_EN field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN_Msk = 0x800
	// Bit SPI_MEM_TX_CRC_EN.
	SPI1_SPI_MEM_CTRL_SPI_MEM_TX_CRC_EN = 0x800
	// Position of SPI_MEM_FASTRD_MODE field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Pos = 0xd
	// Bit mask of SPI_MEM_FASTRD_MODE field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE_Msk = 0x2000
	// Bit SPI_MEM_FASTRD_MODE.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FASTRD_MODE = 0x2000
	// Position of SPI_MEM_FREAD_DUAL field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Pos = 0xe
	// Bit mask of SPI_MEM_FREAD_DUAL field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL_Msk = 0x4000
	// Bit SPI_MEM_FREAD_DUAL.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DUAL = 0x4000
	// Position of SPI_MEM_RESANDRES field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES_Pos = 0xf
	// Bit mask of SPI_MEM_RESANDRES field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES_Msk = 0x8000
	// Bit SPI_MEM_RESANDRES.
	SPI1_SPI_MEM_CTRL_SPI_MEM_RESANDRES = 0x8000
	// Position of SPI_MEM_Q_POL field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL_Pos = 0x12
	// Bit mask of SPI_MEM_Q_POL field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL_Msk = 0x40000
	// Bit SPI_MEM_Q_POL.
	SPI1_SPI_MEM_CTRL_SPI_MEM_Q_POL = 0x40000
	// Position of SPI_MEM_D_POL field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL_Pos = 0x13
	// Bit mask of SPI_MEM_D_POL field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL_Msk = 0x80000
	// Bit SPI_MEM_D_POL.
	SPI1_SPI_MEM_CTRL_SPI_MEM_D_POL = 0x80000
	// Position of SPI_MEM_FREAD_QUAD field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Pos = 0x14
	// Bit mask of SPI_MEM_FREAD_QUAD field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD_Msk = 0x100000
	// Bit SPI_MEM_FREAD_QUAD.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QUAD = 0x100000
	// Position of SPI_MEM_WP field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_WP_Pos = 0x15
	// Bit mask of SPI_MEM_WP field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_WP_Msk = 0x200000
	// Bit SPI_MEM_WP.
	SPI1_SPI_MEM_CTRL_SPI_MEM_WP = 0x200000
	// Position of SPI_MEM_WRSR_2B field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B_Pos = 0x16
	// Bit mask of SPI_MEM_WRSR_2B field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B_Msk = 0x400000
	// Bit SPI_MEM_WRSR_2B.
	SPI1_SPI_MEM_CTRL_SPI_MEM_WRSR_2B = 0x400000
	// Position of SPI_MEM_FREAD_DIO field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Pos = 0x17
	// Bit mask of SPI_MEM_FREAD_DIO field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO_Msk = 0x800000
	// Bit SPI_MEM_FREAD_DIO.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_DIO = 0x800000
	// Position of SPI_MEM_FREAD_QIO field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Pos = 0x18
	// Bit mask of SPI_MEM_FREAD_QIO field.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO_Msk = 0x1000000
	// Bit SPI_MEM_FREAD_QIO.
	SPI1_SPI_MEM_CTRL_SPI_MEM_FREAD_QIO = 0x1000000

	// SPI_MEM_CTRL1: SPI1 control1 register.
	// Position of SPI_MEM_CLK_MODE field.
	SPI1_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Pos = 0x0
	// Bit mask of SPI_MEM_CLK_MODE field.
	SPI1_SPI_MEM_CTRL1_SPI_MEM_CLK_MODE_Msk = 0x3
	// Position of SPI_MEM_CS_HOLD_DLY_RES field.
	SPI1_SPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES_Pos = 0x2
	// Bit mask of SPI_MEM_CS_HOLD_DLY_RES field.
	SPI1_SPI_MEM_CTRL1_SPI_MEM_CS_HOLD_DLY_RES_Msk = 0xffc

	// SPI_MEM_CTRL2: SPI1 control2 register.
	// Position of SPI_MEM_SYNC_RESET field.
	SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Pos = 0x1f
	// Bit mask of SPI_MEM_SYNC_RESET field.
	SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET_Msk = 0x80000000
	// Bit SPI_MEM_SYNC_RESET.
	SPI1_SPI_MEM_CTRL2_SPI_MEM_SYNC_RESET = 0x80000000

	// SPI_MEM_CLOCK: SPI1 clock division control register.
	// Position of SPI_MEM_CLKCNT_L field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Pos = 0x0
	// Bit mask of SPI_MEM_CLKCNT_L field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_L_Msk = 0xff
	// Position of SPI_MEM_CLKCNT_H field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Pos = 0x8
	// Bit mask of SPI_MEM_CLKCNT_H field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_H_Msk = 0xff00
	// Position of SPI_MEM_CLKCNT_N field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Pos = 0x10
	// Bit mask of SPI_MEM_CLKCNT_N field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLKCNT_N_Msk = 0xff0000
	// Position of SPI_MEM_CLK_EQU_SYSCLK field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Pos = 0x1f
	// Bit mask of SPI_MEM_CLK_EQU_SYSCLK field.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK_Msk = 0x80000000
	// Bit SPI_MEM_CLK_EQU_SYSCLK.
	SPI1_SPI_MEM_CLOCK_SPI_MEM_CLK_EQU_SYSCLK = 0x80000000

	// SPI_MEM_USER: SPI1 user register.
	// Position of SPI_MEM_CK_OUT_EDGE field.
	SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Pos = 0x9
	// Bit mask of SPI_MEM_CK_OUT_EDGE field.
	SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE_Msk = 0x200
	// Bit SPI_MEM_CK_OUT_EDGE.
	SPI1_SPI_MEM_USER_SPI_MEM_CK_OUT_EDGE = 0x200
	// Position of SPI_MEM_FWRITE_DUAL field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL_Pos = 0xc
	// Bit mask of SPI_MEM_FWRITE_DUAL field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL_Msk = 0x1000
	// Bit SPI_MEM_FWRITE_DUAL.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DUAL = 0x1000
	// Position of SPI_MEM_FWRITE_QUAD field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD_Pos = 0xd
	// Bit mask of SPI_MEM_FWRITE_QUAD field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD_Msk = 0x2000
	// Bit SPI_MEM_FWRITE_QUAD.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QUAD = 0x2000
	// Position of SPI_MEM_FWRITE_DIO field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO_Pos = 0xe
	// Bit mask of SPI_MEM_FWRITE_DIO field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO_Msk = 0x4000
	// Bit SPI_MEM_FWRITE_DIO.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_DIO = 0x4000
	// Position of SPI_MEM_FWRITE_QIO field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO_Pos = 0xf
	// Bit mask of SPI_MEM_FWRITE_QIO field.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO_Msk = 0x8000
	// Bit SPI_MEM_FWRITE_QIO.
	SPI1_SPI_MEM_USER_SPI_MEM_FWRITE_QIO = 0x8000
	// Position of SPI_MEM_USR_MISO_HIGHPART field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART_Pos = 0x18
	// Bit mask of SPI_MEM_USR_MISO_HIGHPART field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART_Msk = 0x1000000
	// Bit SPI_MEM_USR_MISO_HIGHPART.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_HIGHPART = 0x1000000
	// Position of SPI_MEM_USR_MOSI_HIGHPART field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART_Pos = 0x19
	// Bit mask of SPI_MEM_USR_MOSI_HIGHPART field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART_Msk = 0x2000000
	// Bit SPI_MEM_USR_MOSI_HIGHPART.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_HIGHPART = 0x2000000
	// Position of SPI_MEM_USR_DUMMY_IDLE field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Pos = 0x1a
	// Bit mask of SPI_MEM_USR_DUMMY_IDLE field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE_Msk = 0x4000000
	// Bit SPI_MEM_USR_DUMMY_IDLE.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_IDLE = 0x4000000
	// Position of SPI_MEM_USR_MOSI field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_Pos = 0x1b
	// Bit mask of SPI_MEM_USR_MOSI field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI_Msk = 0x8000000
	// Bit SPI_MEM_USR_MOSI.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MOSI = 0x8000000
	// Position of SPI_MEM_USR_MISO field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_Pos = 0x1c
	// Bit mask of SPI_MEM_USR_MISO field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO_Msk = 0x10000000
	// Bit SPI_MEM_USR_MISO.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_MISO = 0x10000000
	// Position of SPI_MEM_USR_DUMMY field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Pos = 0x1d
	// Bit mask of SPI_MEM_USR_DUMMY field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY_Msk = 0x20000000
	// Bit SPI_MEM_USR_DUMMY.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_DUMMY = 0x20000000
	// Position of SPI_MEM_USR_ADDR field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR_Pos = 0x1e
	// Bit mask of SPI_MEM_USR_ADDR field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR_Msk = 0x40000000
	// Bit SPI_MEM_USR_ADDR.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_ADDR = 0x40000000
	// Position of SPI_MEM_USR_COMMAND field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND_Pos = 0x1f
	// Bit mask of SPI_MEM_USR_COMMAND field.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND_Msk = 0x80000000
	// Bit SPI_MEM_USR_COMMAND.
	SPI1_SPI_MEM_USER_SPI_MEM_USR_COMMAND = 0x80000000

	// SPI_MEM_USER1: SPI1 user1 register.
	// Position of SPI_MEM_USR_DUMMY_CYCLELEN field.
	SPI1_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Pos = 0x0
	// Bit mask of SPI_MEM_USR_DUMMY_CYCLELEN field.
	SPI1_SPI_MEM_USER1_SPI_MEM_USR_DUMMY_CYCLELEN_Msk = 0x3f
	// Position of SPI_MEM_USR_ADDR_BITLEN field.
	SPI1_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Pos = 0x1a
	// Bit mask of SPI_MEM_USR_ADDR_BITLEN field.
	SPI1_SPI_MEM_USER1_SPI_MEM_USR_ADDR_BITLEN_Msk = 0xfc000000

	// SPI_MEM_USER2: SPI1 user2 register.
	// Position of SPI_MEM_USR_COMMAND_VALUE field.
	SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Pos = 0x0
	// Bit mask of SPI_MEM_USR_COMMAND_VALUE field.
	SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_VALUE_Msk = 0xffff
	// Position of SPI_MEM_USR_COMMAND_BITLEN field.
	SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Pos = 0x1c
	// Bit mask of SPI_MEM_USR_COMMAND_BITLEN field.
	SPI1_SPI_MEM_USER2_SPI_MEM_USR_COMMAND_BITLEN_Msk = 0xf0000000

	// SPI_MEM_MOSI_DLEN: SPI1 send data bit length control register.
	// Position of SPI_MEM_USR_MOSI_DBITLEN field.
	SPI1_SPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN_Pos = 0x0
	// Bit mask of SPI_MEM_USR_MOSI_DBITLEN field.
	SPI1_SPI_MEM_MOSI_DLEN_SPI_MEM_USR_MOSI_DBITLEN_Msk = 0x3ff

	// SPI_MEM_MISO_DLEN: SPI1 receive data bit length control register.
	// Position of SPI_MEM_USR_MISO_DBITLEN field.
	SPI1_SPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN_Pos = 0x0
	// Bit mask of SPI_MEM_USR_MISO_DBITLEN field.
	SPI1_SPI_MEM_MISO_DLEN_SPI_MEM_USR_MISO_DBITLEN_Msk = 0x3ff

	// SPI_MEM_RD_STATUS: SPI1 status register.
	// Position of SPI_MEM_STATUS field.
	SPI1_SPI_MEM_RD_STATUS_SPI_MEM_STATUS_Pos = 0x0
	// Bit mask of SPI_MEM_STATUS field.
	SPI1_SPI_MEM_RD_STATUS_SPI_MEM_STATUS_Msk = 0xffff
	// Position of SPI_MEM_WB_MODE field.
	SPI1_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Pos = 0x10
	// Bit mask of SPI_MEM_WB_MODE field.
	SPI1_SPI_MEM_RD_STATUS_SPI_MEM_WB_MODE_Msk = 0xff0000

	// SPI_MEM_MISC: SPI1 misc register
	// Position of SPI_MEM_CS0_DIS field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS_Pos = 0x0
	// Bit mask of SPI_MEM_CS0_DIS field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS_Msk = 0x1
	// Bit SPI_MEM_CS0_DIS.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS0_DIS = 0x1
	// Position of SPI_MEM_CS1_DIS field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS_Pos = 0x1
	// Bit mask of SPI_MEM_CS1_DIS field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS_Msk = 0x2
	// Bit SPI_MEM_CS1_DIS.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS1_DIS = 0x2
	// Position of SPI_MEM_CK_IDLE_EDGE field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Pos = 0x9
	// Bit mask of SPI_MEM_CK_IDLE_EDGE field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE_Msk = 0x200
	// Bit SPI_MEM_CK_IDLE_EDGE.
	SPI1_SPI_MEM_MISC_SPI_MEM_CK_IDLE_EDGE = 0x200
	// Position of SPI_MEM_CS_KEEP_ACTIVE field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Pos = 0xa
	// Bit mask of SPI_MEM_CS_KEEP_ACTIVE field.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE_Msk = 0x400
	// Bit SPI_MEM_CS_KEEP_ACTIVE.
	SPI1_SPI_MEM_MISC_SPI_MEM_CS_KEEP_ACTIVE = 0x400

	// SPI_MEM_TX_CRC: SPI1 TX CRC data register.
	// Position of DATA field.
	SPI1_SPI_MEM_TX_CRC_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SPI1_SPI_MEM_TX_CRC_DATA_Msk = 0xffffffff

	// SPI_MEM_CACHE_FCTRL: SPI1 bit mode control register.
	// Position of SPI_MEM_CACHE_USR_ADDR_4BYTE field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Pos = 0x1
	// Bit mask of SPI_MEM_CACHE_USR_ADDR_4BYTE field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE_Msk = 0x2
	// Bit SPI_MEM_CACHE_USR_ADDR_4BYTE.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_CACHE_USR_ADDR_4BYTE = 0x2
	// Position of SPI_MEM_FDIN_DUAL field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Pos = 0x3
	// Bit mask of SPI_MEM_FDIN_DUAL field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL_Msk = 0x8
	// Bit SPI_MEM_FDIN_DUAL.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_DUAL = 0x8
	// Position of SPI_MEM_FDOUT_DUAL field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Pos = 0x4
	// Bit mask of SPI_MEM_FDOUT_DUAL field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL_Msk = 0x10
	// Bit SPI_MEM_FDOUT_DUAL.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_DUAL = 0x10
	// Position of SPI_MEM_FADDR_DUAL field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Pos = 0x5
	// Bit mask of SPI_MEM_FADDR_DUAL field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL_Msk = 0x20
	// Bit SPI_MEM_FADDR_DUAL.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_DUAL = 0x20
	// Position of SPI_MEM_FDIN_QUAD field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Pos = 0x6
	// Bit mask of SPI_MEM_FDIN_QUAD field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD_Msk = 0x40
	// Bit SPI_MEM_FDIN_QUAD.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDIN_QUAD = 0x40
	// Position of SPI_MEM_FDOUT_QUAD field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Pos = 0x7
	// Bit mask of SPI_MEM_FDOUT_QUAD field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD_Msk = 0x80
	// Bit SPI_MEM_FDOUT_QUAD.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FDOUT_QUAD = 0x80
	// Position of SPI_MEM_FADDR_QUAD field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Pos = 0x8
	// Bit mask of SPI_MEM_FADDR_QUAD field.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD_Msk = 0x100
	// Bit SPI_MEM_FADDR_QUAD.
	SPI1_SPI_MEM_CACHE_FCTRL_SPI_MEM_FADDR_QUAD = 0x100

	// SPI_MEM_W0: SPI1 memory data buffer0
	// Position of SPI_MEM_BUF0 field.
	SPI1_SPI_MEM_W0_SPI_MEM_BUF0_Pos = 0x0
	// Bit mask of SPI_MEM_BUF0 field.
	SPI1_SPI_MEM_W0_SPI_MEM_BUF0_Msk = 0xffffffff

	// SPI_MEM_W1: SPI1 memory data buffer1
	// Position of SPI_MEM_BUF1 field.
	SPI1_SPI_MEM_W1_SPI_MEM_BUF1_Pos = 0x0
	// Bit mask of SPI_MEM_BUF1 field.
	SPI1_SPI_MEM_W1_SPI_MEM_BUF1_Msk = 0xffffffff

	// SPI_MEM_W2: SPI1 memory data buffer2
	// Position of SPI_MEM_BUF2 field.
	SPI1_SPI_MEM_W2_SPI_MEM_BUF2_Pos = 0x0
	// Bit mask of SPI_MEM_BUF2 field.
	SPI1_SPI_MEM_W2_SPI_MEM_BUF2_Msk = 0xffffffff

	// SPI_MEM_W3: SPI1 memory data buffer3
	// Position of SPI_MEM_BUF3 field.
	SPI1_SPI_MEM_W3_SPI_MEM_BUF3_Pos = 0x0
	// Bit mask of SPI_MEM_BUF3 field.
	SPI1_SPI_MEM_W3_SPI_MEM_BUF3_Msk = 0xffffffff

	// SPI_MEM_W4: SPI1 memory data buffer4
	// Position of SPI_MEM_BUF4 field.
	SPI1_SPI_MEM_W4_SPI_MEM_BUF4_Pos = 0x0
	// Bit mask of SPI_MEM_BUF4 field.
	SPI1_SPI_MEM_W4_SPI_MEM_BUF4_Msk = 0xffffffff

	// SPI_MEM_W5: SPI1 memory data buffer5
	// Position of SPI_MEM_BUF5 field.
	SPI1_SPI_MEM_W5_SPI_MEM_BUF5_Pos = 0x0
	// Bit mask of SPI_MEM_BUF5 field.
	SPI1_SPI_MEM_W5_SPI_MEM_BUF5_Msk = 0xffffffff

	// SPI_MEM_W6: SPI1 memory data buffer6
	// Position of SPI_MEM_BUF6 field.
	SPI1_SPI_MEM_W6_SPI_MEM_BUF6_Pos = 0x0
	// Bit mask of SPI_MEM_BUF6 field.
	SPI1_SPI_MEM_W6_SPI_MEM_BUF6_Msk = 0xffffffff

	// SPI_MEM_W7: SPI1 memory data buffer7
	// Position of SPI_MEM_BUF7 field.
	SPI1_SPI_MEM_W7_SPI_MEM_BUF7_Pos = 0x0
	// Bit mask of SPI_MEM_BUF7 field.
	SPI1_SPI_MEM_W7_SPI_MEM_BUF7_Msk = 0xffffffff

	// SPI_MEM_W8: SPI1 memory data buffer8
	// Position of SPI_MEM_BUF8 field.
	SPI1_SPI_MEM_W8_SPI_MEM_BUF8_Pos = 0x0
	// Bit mask of SPI_MEM_BUF8 field.
	SPI1_SPI_MEM_W8_SPI_MEM_BUF8_Msk = 0xffffffff

	// SPI_MEM_W9: SPI1 memory data buffer9
	// Position of SPI_MEM_BUF9 field.
	SPI1_SPI_MEM_W9_SPI_MEM_BUF9_Pos = 0x0
	// Bit mask of SPI_MEM_BUF9 field.
	SPI1_SPI_MEM_W9_SPI_MEM_BUF9_Msk = 0xffffffff

	// SPI_MEM_W10: SPI1 memory data buffer10
	// Position of SPI_MEM_BUF10 field.
	SPI1_SPI_MEM_W10_SPI_MEM_BUF10_Pos = 0x0
	// Bit mask of SPI_MEM_BUF10 field.
	SPI1_SPI_MEM_W10_SPI_MEM_BUF10_Msk = 0xffffffff

	// SPI_MEM_W11: SPI1 memory data buffer11
	// Position of SPI_MEM_BUF11 field.
	SPI1_SPI_MEM_W11_SPI_MEM_BUF11_Pos = 0x0
	// Bit mask of SPI_MEM_BUF11 field.
	SPI1_SPI_MEM_W11_SPI_MEM_BUF11_Msk = 0xffffffff

	// SPI_MEM_W12: SPI1 memory data buffer12
	// Position of SPI_MEM_BUF12 field.
	SPI1_SPI_MEM_W12_SPI_MEM_BUF12_Pos = 0x0
	// Bit mask of SPI_MEM_BUF12 field.
	SPI1_SPI_MEM_W12_SPI_MEM_BUF12_Msk = 0xffffffff

	// SPI_MEM_W13: SPI1 memory data buffer13
	// Position of SPI_MEM_BUF13 field.
	SPI1_SPI_MEM_W13_SPI_MEM_BUF13_Pos = 0x0
	// Bit mask of SPI_MEM_BUF13 field.
	SPI1_SPI_MEM_W13_SPI_MEM_BUF13_Msk = 0xffffffff

	// SPI_MEM_W14: SPI1 memory data buffer14
	// Position of SPI_MEM_BUF14 field.
	SPI1_SPI_MEM_W14_SPI_MEM_BUF14_Pos = 0x0
	// Bit mask of SPI_MEM_BUF14 field.
	SPI1_SPI_MEM_W14_SPI_MEM_BUF14_Msk = 0xffffffff

	// SPI_MEM_W15: SPI1 memory data buffer15
	// Position of SPI_MEM_BUF15 field.
	SPI1_SPI_MEM_W15_SPI_MEM_BUF15_Pos = 0x0
	// Bit mask of SPI_MEM_BUF15 field.
	SPI1_SPI_MEM_W15_SPI_MEM_BUF15_Msk = 0xffffffff

	// SPI_MEM_FLASH_WAITI_CTRL: SPI1 wait idle control register
	// Position of SPI_MEM_WAITI_EN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN_Pos = 0x0
	// Bit mask of SPI_MEM_WAITI_EN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN_Msk = 0x1
	// Bit SPI_MEM_WAITI_EN.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_EN = 0x1
	// Position of SPI_MEM_WAITI_DUMMY field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_Pos = 0x1
	// Bit mask of SPI_MEM_WAITI_DUMMY field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_Msk = 0x2
	// Bit SPI_MEM_WAITI_DUMMY.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY = 0x2
	// Position of SPI_MEM_WAITI_ADDR_EN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN_Pos = 0x2
	// Bit mask of SPI_MEM_WAITI_ADDR_EN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN_Msk = 0x4
	// Bit SPI_MEM_WAITI_ADDR_EN.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_EN = 0x4
	// Position of SPI_MEM_WAITI_ADDR_CYCLELEN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN_Pos = 0x3
	// Bit mask of SPI_MEM_WAITI_ADDR_CYCLELEN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_ADDR_CYCLELEN_Msk = 0x18
	// Position of SPI_MEM_WAITI_CMD_2B field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B_Pos = 0x9
	// Bit mask of SPI_MEM_WAITI_CMD_2B field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B_Msk = 0x200
	// Bit SPI_MEM_WAITI_CMD_2B.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_2B = 0x200
	// Position of SPI_MEM_WAITI_DUMMY_CYCLELEN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN_Pos = 0xa
	// Bit mask of SPI_MEM_WAITI_DUMMY_CYCLELEN field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_DUMMY_CYCLELEN_Msk = 0xfc00
	// Position of SPI_MEM_WAITI_CMD field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_Pos = 0x10
	// Bit mask of SPI_MEM_WAITI_CMD field.
	SPI1_SPI_MEM_FLASH_WAITI_CTRL_SPI_MEM_WAITI_CMD_Msk = 0xffff0000

	// SPI_MEM_FLASH_SUS_CTRL: SPI1 flash suspend control register
	// Position of SPI_MEM_FLASH_PER field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_Pos = 0x0
	// Bit mask of SPI_MEM_FLASH_PER field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_Msk = 0x1
	// Bit SPI_MEM_FLASH_PER.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER = 0x1
	// Position of SPI_MEM_FLASH_PES field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_Pos = 0x1
	// Bit mask of SPI_MEM_FLASH_PES field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_Msk = 0x2
	// Bit SPI_MEM_FLASH_PES.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES = 0x2
	// Position of SPI_MEM_FLASH_PER_WAIT_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN_Pos = 0x2
	// Bit mask of SPI_MEM_FLASH_PER_WAIT_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN_Msk = 0x4
	// Bit SPI_MEM_FLASH_PER_WAIT_EN.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PER_WAIT_EN = 0x4
	// Position of SPI_MEM_FLASH_PES_WAIT_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN_Pos = 0x3
	// Bit mask of SPI_MEM_FLASH_PES_WAIT_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN_Msk = 0x8
	// Bit SPI_MEM_FLASH_PES_WAIT_EN.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_WAIT_EN = 0x8
	// Position of SPI_MEM_PES_PER_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN_Pos = 0x4
	// Bit mask of SPI_MEM_PES_PER_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN_Msk = 0x10
	// Bit SPI_MEM_PES_PER_EN.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_PER_EN = 0x10
	// Position of SPI_MEM_FLASH_PES_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN_Pos = 0x5
	// Bit mask of SPI_MEM_FLASH_PES_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN_Msk = 0x20
	// Bit SPI_MEM_FLASH_PES_EN.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_FLASH_PES_EN = 0x20
	// Position of SPI_MEM_PESR_END_MSK field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK_Pos = 0x6
	// Bit mask of SPI_MEM_PESR_END_MSK field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PESR_END_MSK_Msk = 0x3fffc0
	// Position of SPI_FMEM_RD_SUS_2B field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Pos = 0x16
	// Bit mask of SPI_FMEM_RD_SUS_2B field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B_Msk = 0x400000
	// Bit SPI_FMEM_RD_SUS_2B.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_FMEM_RD_SUS_2B = 0x400000
	// Position of SPI_MEM_PER_END_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN_Pos = 0x17
	// Bit mask of SPI_MEM_PER_END_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN_Msk = 0x800000
	// Bit SPI_MEM_PER_END_EN.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PER_END_EN = 0x800000
	// Position of SPI_MEM_PES_END_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN_Pos = 0x18
	// Bit mask of SPI_MEM_PES_END_EN field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN_Msk = 0x1000000
	// Bit SPI_MEM_PES_END_EN.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_PES_END_EN = 0x1000000
	// Position of SPI_MEM_SUS_TIMEOUT_CNT field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT_Pos = 0x19
	// Bit mask of SPI_MEM_SUS_TIMEOUT_CNT field.
	SPI1_SPI_MEM_FLASH_SUS_CTRL_SPI_MEM_SUS_TIMEOUT_CNT_Msk = 0xfe000000

	// SPI_MEM_FLASH_SUS_CMD: SPI1 flash suspend command register
	// Position of SPI_MEM_FLASH_PES_COMMAND field.
	SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND_Pos = 0x0
	// Bit mask of SPI_MEM_FLASH_PES_COMMAND field.
	SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_FLASH_PES_COMMAND_Msk = 0xffff
	// Position of SPI_MEM_WAIT_PESR_COMMAND field.
	SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND_Pos = 0x10
	// Bit mask of SPI_MEM_WAIT_PESR_COMMAND field.
	SPI1_SPI_MEM_FLASH_SUS_CMD_SPI_MEM_WAIT_PESR_COMMAND_Msk = 0xffff0000

	// SPI_MEM_SUS_STATUS: SPI1 flash suspend status register
	// Position of SPI_MEM_FLASH_SUS field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS_Pos = 0x0
	// Bit mask of SPI_MEM_FLASH_SUS field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS_Msk = 0x1
	// Bit SPI_MEM_FLASH_SUS.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_SUS = 0x1
	// Position of SPI_MEM_WAIT_PESR_CMD_2B field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B_Pos = 0x1
	// Bit mask of SPI_MEM_WAIT_PESR_CMD_2B field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B_Msk = 0x2
	// Bit SPI_MEM_WAIT_PESR_CMD_2B.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_WAIT_PESR_CMD_2B = 0x2
	// Position of SPI_MEM_FLASH_HPM_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128_Pos = 0x2
	// Bit mask of SPI_MEM_FLASH_HPM_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128_Msk = 0x4
	// Bit SPI_MEM_FLASH_HPM_DLY_128.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_HPM_DLY_128 = 0x4
	// Position of SPI_MEM_FLASH_RES_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128_Pos = 0x3
	// Bit mask of SPI_MEM_FLASH_RES_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128_Msk = 0x8
	// Bit SPI_MEM_FLASH_RES_DLY_128.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_RES_DLY_128 = 0x8
	// Position of SPI_MEM_FLASH_DP_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128_Pos = 0x4
	// Bit mask of SPI_MEM_FLASH_DP_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128_Msk = 0x10
	// Bit SPI_MEM_FLASH_DP_DLY_128.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_DP_DLY_128 = 0x10
	// Position of SPI_MEM_FLASH_PER_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128_Pos = 0x5
	// Bit mask of SPI_MEM_FLASH_PER_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128_Msk = 0x20
	// Bit SPI_MEM_FLASH_PER_DLY_128.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_DLY_128 = 0x20
	// Position of SPI_MEM_FLASH_PES_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128_Pos = 0x6
	// Bit mask of SPI_MEM_FLASH_PES_DLY_128 field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128_Msk = 0x40
	// Bit SPI_MEM_FLASH_PES_DLY_128.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PES_DLY_128 = 0x40
	// Position of SPI_MEM_SPI0_LOCK_EN field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN_Pos = 0x7
	// Bit mask of SPI_MEM_SPI0_LOCK_EN field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN_Msk = 0x80
	// Bit SPI_MEM_SPI0_LOCK_EN.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_SPI0_LOCK_EN = 0x80
	// Position of SPI_MEM_FLASH_PESR_CMD_2B field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B_Pos = 0xf
	// Bit mask of SPI_MEM_FLASH_PESR_CMD_2B field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B_Msk = 0x8000
	// Bit SPI_MEM_FLASH_PESR_CMD_2B.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PESR_CMD_2B = 0x8000
	// Position of SPI_MEM_FLASH_PER_COMMAND field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND_Pos = 0x10
	// Bit mask of SPI_MEM_FLASH_PER_COMMAND field.
	SPI1_SPI_MEM_SUS_STATUS_SPI_MEM_FLASH_PER_COMMAND_Msk = 0xffff0000

	// SPI_MEM_INT_ENA: SPI1 interrupt enable register
	// Position of SPI_MEM_PER_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA_Pos = 0x0
	// Bit mask of SPI_MEM_PER_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA_Msk = 0x1
	// Bit SPI_MEM_PER_END_INT_ENA.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_PER_END_INT_ENA = 0x1
	// Position of SPI_MEM_PES_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA_Pos = 0x1
	// Bit mask of SPI_MEM_PES_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA_Msk = 0x2
	// Bit SPI_MEM_PES_END_INT_ENA.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_PES_END_INT_ENA = 0x2
	// Position of SPI_MEM_WPE_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA_Pos = 0x2
	// Bit mask of SPI_MEM_WPE_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA_Msk = 0x4
	// Bit SPI_MEM_WPE_END_INT_ENA.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_WPE_END_INT_ENA = 0x4
	// Position of SPI_MEM_SLV_ST_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_ENA.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_SLV_ST_END_INT_ENA = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_ENA.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_MST_ST_END_INT_ENA = 0x10
	// Position of SPI_MEM_BROWN_OUT_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA_Pos = 0xa
	// Bit mask of SPI_MEM_BROWN_OUT_INT_ENA field.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA_Msk = 0x400
	// Bit SPI_MEM_BROWN_OUT_INT_ENA.
	SPI1_SPI_MEM_INT_ENA_SPI_MEM_BROWN_OUT_INT_ENA = 0x400

	// SPI_MEM_INT_CLR: SPI1 interrupt clear register
	// Position of SPI_MEM_PER_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR_Pos = 0x0
	// Bit mask of SPI_MEM_PER_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR_Msk = 0x1
	// Bit SPI_MEM_PER_END_INT_CLR.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_PER_END_INT_CLR = 0x1
	// Position of SPI_MEM_PES_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR_Pos = 0x1
	// Bit mask of SPI_MEM_PES_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR_Msk = 0x2
	// Bit SPI_MEM_PES_END_INT_CLR.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_PES_END_INT_CLR = 0x2
	// Position of SPI_MEM_WPE_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR_Pos = 0x2
	// Bit mask of SPI_MEM_WPE_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR_Msk = 0x4
	// Bit SPI_MEM_WPE_END_INT_CLR.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_WPE_END_INT_CLR = 0x4
	// Position of SPI_MEM_SLV_ST_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_CLR.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_SLV_ST_END_INT_CLR = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_CLR.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_MST_ST_END_INT_CLR = 0x10
	// Position of SPI_MEM_BROWN_OUT_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR_Pos = 0xa
	// Bit mask of SPI_MEM_BROWN_OUT_INT_CLR field.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR_Msk = 0x400
	// Bit SPI_MEM_BROWN_OUT_INT_CLR.
	SPI1_SPI_MEM_INT_CLR_SPI_MEM_BROWN_OUT_INT_CLR = 0x400

	// SPI_MEM_INT_RAW: SPI1 interrupt raw register
	// Position of SPI_MEM_PER_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW_Pos = 0x0
	// Bit mask of SPI_MEM_PER_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW_Msk = 0x1
	// Bit SPI_MEM_PER_END_INT_RAW.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_PER_END_INT_RAW = 0x1
	// Position of SPI_MEM_PES_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW_Pos = 0x1
	// Bit mask of SPI_MEM_PES_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW_Msk = 0x2
	// Bit SPI_MEM_PES_END_INT_RAW.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_PES_END_INT_RAW = 0x2
	// Position of SPI_MEM_WPE_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW_Pos = 0x2
	// Bit mask of SPI_MEM_WPE_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW_Msk = 0x4
	// Bit SPI_MEM_WPE_END_INT_RAW.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_WPE_END_INT_RAW = 0x4
	// Position of SPI_MEM_SLV_ST_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_RAW.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_SLV_ST_END_INT_RAW = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_RAW.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_MST_ST_END_INT_RAW = 0x10
	// Position of SPI_MEM_BROWN_OUT_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW_Pos = 0xa
	// Bit mask of SPI_MEM_BROWN_OUT_INT_RAW field.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW_Msk = 0x400
	// Bit SPI_MEM_BROWN_OUT_INT_RAW.
	SPI1_SPI_MEM_INT_RAW_SPI_MEM_BROWN_OUT_INT_RAW = 0x400

	// SPI_MEM_INT_ST: SPI1 interrupt status register
	// Position of SPI_MEM_PER_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST_Pos = 0x0
	// Bit mask of SPI_MEM_PER_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST_Msk = 0x1
	// Bit SPI_MEM_PER_END_INT_ST.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_PER_END_INT_ST = 0x1
	// Position of SPI_MEM_PES_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST_Pos = 0x1
	// Bit mask of SPI_MEM_PES_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST_Msk = 0x2
	// Bit SPI_MEM_PES_END_INT_ST.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_PES_END_INT_ST = 0x2
	// Position of SPI_MEM_WPE_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST_Pos = 0x2
	// Bit mask of SPI_MEM_WPE_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST_Msk = 0x4
	// Bit SPI_MEM_WPE_END_INT_ST.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_WPE_END_INT_ST = 0x4
	// Position of SPI_MEM_SLV_ST_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Pos = 0x3
	// Bit mask of SPI_MEM_SLV_ST_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST_Msk = 0x8
	// Bit SPI_MEM_SLV_ST_END_INT_ST.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_SLV_ST_END_INT_ST = 0x8
	// Position of SPI_MEM_MST_ST_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Pos = 0x4
	// Bit mask of SPI_MEM_MST_ST_END_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST_Msk = 0x10
	// Bit SPI_MEM_MST_ST_END_INT_ST.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_MST_ST_END_INT_ST = 0x10
	// Position of SPI_MEM_BROWN_OUT_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST_Pos = 0xa
	// Bit mask of SPI_MEM_BROWN_OUT_INT_ST field.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST_Msk = 0x400
	// Bit SPI_MEM_BROWN_OUT_INT_ST.
	SPI1_SPI_MEM_INT_ST_SPI_MEM_BROWN_OUT_INT_ST = 0x400

	// SPI_MEM_DDR: SPI1 DDR control register
	// Position of SPI_FMEM_DDR_EN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Pos = 0x0
	// Bit mask of SPI_FMEM_DDR_EN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN_Msk = 0x1
	// Bit SPI_FMEM_DDR_EN.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_EN = 0x1
	// Position of SPI_FMEM_VAR_DUMMY field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Pos = 0x1
	// Bit mask of SPI_FMEM_VAR_DUMMY field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY_Msk = 0x2
	// Bit SPI_FMEM_VAR_DUMMY.
	SPI1_SPI_MEM_DDR_SPI_FMEM_VAR_DUMMY = 0x2
	// Position of SPI_FMEM_DDR_RDAT_SWP field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Pos = 0x2
	// Bit mask of SPI_FMEM_DDR_RDAT_SWP field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP_Msk = 0x4
	// Bit SPI_FMEM_DDR_RDAT_SWP.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_RDAT_SWP = 0x4
	// Position of SPI_FMEM_DDR_WDAT_SWP field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Pos = 0x3
	// Bit mask of SPI_FMEM_DDR_WDAT_SWP field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP_Msk = 0x8
	// Bit SPI_FMEM_DDR_WDAT_SWP.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_WDAT_SWP = 0x8
	// Position of SPI_FMEM_DDR_CMD_DIS field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Pos = 0x4
	// Bit mask of SPI_FMEM_DDR_CMD_DIS field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS_Msk = 0x10
	// Bit SPI_FMEM_DDR_CMD_DIS.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_CMD_DIS = 0x10
	// Position of SPI_FMEM_OUTMINBYTELEN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Pos = 0x5
	// Bit mask of SPI_FMEM_OUTMINBYTELEN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_OUTMINBYTELEN_Msk = 0xfe0
	// Position of SPI_FMEM_USR_DDR_DQS_THD field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Pos = 0xe
	// Bit mask of SPI_FMEM_USR_DDR_DQS_THD field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_USR_DDR_DQS_THD_Msk = 0x1fc000
	// Position of SPI_FMEM_DDR_DQS_LOOP field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Pos = 0x15
	// Bit mask of SPI_FMEM_DDR_DQS_LOOP field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP_Msk = 0x200000
	// Bit SPI_FMEM_DDR_DQS_LOOP.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DDR_DQS_LOOP = 0x200000
	// Position of SPI_FMEM_CLK_DIFF_EN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Pos = 0x18
	// Bit mask of SPI_FMEM_CLK_DIFF_EN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN_Msk = 0x1000000
	// Bit SPI_FMEM_CLK_DIFF_EN.
	SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_EN = 0x1000000
	// Position of SPI_FMEM_DQS_CA_IN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Pos = 0x1a
	// Bit mask of SPI_FMEM_DQS_CA_IN field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN_Msk = 0x4000000
	// Bit SPI_FMEM_DQS_CA_IN.
	SPI1_SPI_MEM_DDR_SPI_FMEM_DQS_CA_IN = 0x4000000
	// Position of SPI_FMEM_HYPERBUS_DUMMY_2X field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Pos = 0x1b
	// Bit mask of SPI_FMEM_HYPERBUS_DUMMY_2X field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X_Msk = 0x8000000
	// Bit SPI_FMEM_HYPERBUS_DUMMY_2X.
	SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_DUMMY_2X = 0x8000000
	// Position of SPI_FMEM_CLK_DIFF_INV field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Pos = 0x1c
	// Bit mask of SPI_FMEM_CLK_DIFF_INV field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV_Msk = 0x10000000
	// Bit SPI_FMEM_CLK_DIFF_INV.
	SPI1_SPI_MEM_DDR_SPI_FMEM_CLK_DIFF_INV = 0x10000000
	// Position of SPI_FMEM_OCTA_RAM_ADDR field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Pos = 0x1d
	// Bit mask of SPI_FMEM_OCTA_RAM_ADDR field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR_Msk = 0x20000000
	// Bit SPI_FMEM_OCTA_RAM_ADDR.
	SPI1_SPI_MEM_DDR_SPI_FMEM_OCTA_RAM_ADDR = 0x20000000
	// Position of SPI_FMEM_HYPERBUS_CA field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Pos = 0x1e
	// Bit mask of SPI_FMEM_HYPERBUS_CA field.
	SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA_Msk = 0x40000000
	// Bit SPI_FMEM_HYPERBUS_CA.
	SPI1_SPI_MEM_DDR_SPI_FMEM_HYPERBUS_CA = 0x40000000

	// SPI_MEM_TIMING_CALI: SPI1 timing control register
	// Position of SPI_MEM_TIMING_CALI field.
	SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Pos = 0x1
	// Bit mask of SPI_MEM_TIMING_CALI field.
	SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI_Msk = 0x2
	// Bit SPI_MEM_TIMING_CALI.
	SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_TIMING_CALI = 0x2
	// Position of SPI_MEM_EXTRA_DUMMY_CYCLELEN field.
	SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Pos = 0x2
	// Bit mask of SPI_MEM_EXTRA_DUMMY_CYCLELEN field.
	SPI1_SPI_MEM_TIMING_CALI_SPI_MEM_EXTRA_DUMMY_CYCLELEN_Msk = 0x1c

	// SPI_MEM_CLOCK_GATE: SPI1 clk_gate register
	// Position of SPI_MEM_CLK_EN field.
	SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN_Pos = 0x0
	// Bit mask of SPI_MEM_CLK_EN field.
	SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN_Msk = 0x1
	// Bit SPI_MEM_CLK_EN.
	SPI1_SPI_MEM_CLOCK_GATE_SPI_MEM_CLK_EN = 0x1

	// SPI_MEM_DATE: Version control register
	// Position of SPI_MEM_DATE field.
	SPI1_SPI_MEM_DATE_SPI_MEM_DATE_Pos = 0x0
	// Bit mask of SPI_MEM_DATE field.
	SPI1_SPI_MEM_DATE_SPI_MEM_DATE_Msk = 0xfffffff
)

// Constants for SPI2: SPI (Serial Peripheral Interface) Controller 2
const (
	// SPI_CMD: Command control register
	// Position of SPI_CONF_BITLEN field.
	SPI2_SPI_CMD_SPI_CONF_BITLEN_Pos = 0x0
	// Bit mask of SPI_CONF_BITLEN field.
	SPI2_SPI_CMD_SPI_CONF_BITLEN_Msk = 0x3ffff
	// Position of SPI_UPDATE field.
	SPI2_SPI_CMD_SPI_UPDATE_Pos = 0x17
	// Bit mask of SPI_UPDATE field.
	SPI2_SPI_CMD_SPI_UPDATE_Msk = 0x800000
	// Bit SPI_UPDATE.
	SPI2_SPI_CMD_SPI_UPDATE = 0x800000
	// Position of SPI_USR field.
	SPI2_SPI_CMD_SPI_USR_Pos = 0x18
	// Bit mask of SPI_USR field.
	SPI2_SPI_CMD_SPI_USR_Msk = 0x1000000
	// Bit SPI_USR.
	SPI2_SPI_CMD_SPI_USR = 0x1000000

	// SPI_ADDR: Address value register
	// Position of SPI_USR_ADDR_VALUE field.
	SPI2_SPI_ADDR_SPI_USR_ADDR_VALUE_Pos = 0x0
	// Bit mask of SPI_USR_ADDR_VALUE field.
	SPI2_SPI_ADDR_SPI_USR_ADDR_VALUE_Msk = 0xffffffff

	// SPI_CTRL: SPI control register
	// Position of SPI_DUMMY_OUT field.
	SPI2_SPI_CTRL_SPI_DUMMY_OUT_Pos = 0x3
	// Bit mask of SPI_DUMMY_OUT field.
	SPI2_SPI_CTRL_SPI_DUMMY_OUT_Msk = 0x8
	// Bit SPI_DUMMY_OUT.
	SPI2_SPI_CTRL_SPI_DUMMY_OUT = 0x8
	// Position of SPI_FADDR_DUAL field.
	SPI2_SPI_CTRL_SPI_FADDR_DUAL_Pos = 0x5
	// Bit mask of SPI_FADDR_DUAL field.
	SPI2_SPI_CTRL_SPI_FADDR_DUAL_Msk = 0x20
	// Bit SPI_FADDR_DUAL.
	SPI2_SPI_CTRL_SPI_FADDR_DUAL = 0x20
	// Position of SPI_FADDR_QUAD field.
	SPI2_SPI_CTRL_SPI_FADDR_QUAD_Pos = 0x6
	// Bit mask of SPI_FADDR_QUAD field.
	SPI2_SPI_CTRL_SPI_FADDR_QUAD_Msk = 0x40
	// Bit SPI_FADDR_QUAD.
	SPI2_SPI_CTRL_SPI_FADDR_QUAD = 0x40
	// Position of SPI_FADDR_OCT field.
	SPI2_SPI_CTRL_SPI_FADDR_OCT_Pos = 0x7
	// Bit mask of SPI_FADDR_OCT field.
	SPI2_SPI_CTRL_SPI_FADDR_OCT_Msk = 0x80
	// Bit SPI_FADDR_OCT.
	SPI2_SPI_CTRL_SPI_FADDR_OCT = 0x80
	// Position of SPI_FCMD_DUAL field.
	SPI2_SPI_CTRL_SPI_FCMD_DUAL_Pos = 0x8
	// Bit mask of SPI_FCMD_DUAL field.
	SPI2_SPI_CTRL_SPI_FCMD_DUAL_Msk = 0x100
	// Bit SPI_FCMD_DUAL.
	SPI2_SPI_CTRL_SPI_FCMD_DUAL = 0x100
	// Position of SPI_FCMD_QUAD field.
	SPI2_SPI_CTRL_SPI_FCMD_QUAD_Pos = 0x9
	// Bit mask of SPI_FCMD_QUAD field.
	SPI2_SPI_CTRL_SPI_FCMD_QUAD_Msk = 0x200
	// Bit SPI_FCMD_QUAD.
	SPI2_SPI_CTRL_SPI_FCMD_QUAD = 0x200
	// Position of SPI_FCMD_OCT field.
	SPI2_SPI_CTRL_SPI_FCMD_OCT_Pos = 0xa
	// Bit mask of SPI_FCMD_OCT field.
	SPI2_SPI_CTRL_SPI_FCMD_OCT_Msk = 0x400
	// Bit SPI_FCMD_OCT.
	SPI2_SPI_CTRL_SPI_FCMD_OCT = 0x400
	// Position of SPI_FREAD_DUAL field.
	SPI2_SPI_CTRL_SPI_FREAD_DUAL_Pos = 0xe
	// Bit mask of SPI_FREAD_DUAL field.
	SPI2_SPI_CTRL_SPI_FREAD_DUAL_Msk = 0x4000
	// Bit SPI_FREAD_DUAL.
	SPI2_SPI_CTRL_SPI_FREAD_DUAL = 0x4000
	// Position of SPI_FREAD_QUAD field.
	SPI2_SPI_CTRL_SPI_FREAD_QUAD_Pos = 0xf
	// Bit mask of SPI_FREAD_QUAD field.
	SPI2_SPI_CTRL_SPI_FREAD_QUAD_Msk = 0x8000
	// Bit SPI_FREAD_QUAD.
	SPI2_SPI_CTRL_SPI_FREAD_QUAD = 0x8000
	// Position of SPI_FREAD_OCT field.
	SPI2_SPI_CTRL_SPI_FREAD_OCT_Pos = 0x10
	// Bit mask of SPI_FREAD_OCT field.
	SPI2_SPI_CTRL_SPI_FREAD_OCT_Msk = 0x10000
	// Bit SPI_FREAD_OCT.
	SPI2_SPI_CTRL_SPI_FREAD_OCT = 0x10000
	// Position of SPI_Q_POL field.
	SPI2_SPI_CTRL_SPI_Q_POL_Pos = 0x12
	// Bit mask of SPI_Q_POL field.
	SPI2_SPI_CTRL_SPI_Q_POL_Msk = 0x40000
	// Bit SPI_Q_POL.
	SPI2_SPI_CTRL_SPI_Q_POL = 0x40000
	// Position of SPI_D_POL field.
	SPI2_SPI_CTRL_SPI_D_POL_Pos = 0x13
	// Bit mask of SPI_D_POL field.
	SPI2_SPI_CTRL_SPI_D_POL_Msk = 0x80000
	// Bit SPI_D_POL.
	SPI2_SPI_CTRL_SPI_D_POL = 0x80000
	// Position of SPI_HOLD_POL field.
	SPI2_SPI_CTRL_SPI_HOLD_POL_Pos = 0x14
	// Bit mask of SPI_HOLD_POL field.
	SPI2_SPI_CTRL_SPI_HOLD_POL_Msk = 0x100000
	// Bit SPI_HOLD_POL.
	SPI2_SPI_CTRL_SPI_HOLD_POL = 0x100000
	// Position of SPI_WP_POL field.
	SPI2_SPI_CTRL_SPI_WP_POL_Pos = 0x15
	// Bit mask of SPI_WP_POL field.
	SPI2_SPI_CTRL_SPI_WP_POL_Msk = 0x200000
	// Bit SPI_WP_POL.
	SPI2_SPI_CTRL_SPI_WP_POL = 0x200000
	// Position of SPI_RD_BIT_ORDER field.
	SPI2_SPI_CTRL_SPI_RD_BIT_ORDER_Pos = 0x17
	// Bit mask of SPI_RD_BIT_ORDER field.
	SPI2_SPI_CTRL_SPI_RD_BIT_ORDER_Msk = 0x1800000
	// Position of SPI_WR_BIT_ORDER field.
	SPI2_SPI_CTRL_SPI_WR_BIT_ORDER_Pos = 0x19
	// Bit mask of SPI_WR_BIT_ORDER field.
	SPI2_SPI_CTRL_SPI_WR_BIT_ORDER_Msk = 0x6000000

	// SPI_CLOCK: SPI clock control register
	// Position of SPI_CLKCNT_L field.
	SPI2_SPI_CLOCK_SPI_CLKCNT_L_Pos = 0x0
	// Bit mask of SPI_CLKCNT_L field.
	SPI2_SPI_CLOCK_SPI_CLKCNT_L_Msk = 0x3f
	// Position of SPI_CLKCNT_H field.
	SPI2_SPI_CLOCK_SPI_CLKCNT_H_Pos = 0x6
	// Bit mask of SPI_CLKCNT_H field.
	SPI2_SPI_CLOCK_SPI_CLKCNT_H_Msk = 0xfc0
	// Position of SPI_CLKCNT_N field.
	SPI2_SPI_CLOCK_SPI_CLKCNT_N_Pos = 0xc
	// Bit mask of SPI_CLKCNT_N field.
	SPI2_SPI_CLOCK_SPI_CLKCNT_N_Msk = 0x3f000
	// Position of SPI_CLKDIV_PRE field.
	SPI2_SPI_CLOCK_SPI_CLKDIV_PRE_Pos = 0x12
	// Bit mask of SPI_CLKDIV_PRE field.
	SPI2_SPI_CLOCK_SPI_CLKDIV_PRE_Msk = 0x3c0000
	// Position of SPI_CLK_EQU_SYSCLK field.
	SPI2_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Pos = 0x1f
	// Bit mask of SPI_CLK_EQU_SYSCLK field.
	SPI2_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Msk = 0x80000000
	// Bit SPI_CLK_EQU_SYSCLK.
	SPI2_SPI_CLOCK_SPI_CLK_EQU_SYSCLK = 0x80000000

	// SPI_USER: SPI USER control register
	// Position of SPI_DOUTDIN field.
	SPI2_SPI_USER_SPI_DOUTDIN_Pos = 0x0
	// Bit mask of SPI_DOUTDIN field.
	SPI2_SPI_USER_SPI_DOUTDIN_Msk = 0x1
	// Bit SPI_DOUTDIN.
	SPI2_SPI_USER_SPI_DOUTDIN = 0x1
	// Position of SPI_QPI_MODE field.
	SPI2_SPI_USER_SPI_QPI_MODE_Pos = 0x3
	// Bit mask of SPI_QPI_MODE field.
	SPI2_SPI_USER_SPI_QPI_MODE_Msk = 0x8
	// Bit SPI_QPI_MODE.
	SPI2_SPI_USER_SPI_QPI_MODE = 0x8
	// Position of SPI_OPI_MODE field.
	SPI2_SPI_USER_SPI_OPI_MODE_Pos = 0x4
	// Bit mask of SPI_OPI_MODE field.
	SPI2_SPI_USER_SPI_OPI_MODE_Msk = 0x10
	// Bit SPI_OPI_MODE.
	SPI2_SPI_USER_SPI_OPI_MODE = 0x10
	// Position of SPI_TSCK_I_EDGE field.
	SPI2_SPI_USER_SPI_TSCK_I_EDGE_Pos = 0x5
	// Bit mask of SPI_TSCK_I_EDGE field.
	SPI2_SPI_USER_SPI_TSCK_I_EDGE_Msk = 0x20
	// Bit SPI_TSCK_I_EDGE.
	SPI2_SPI_USER_SPI_TSCK_I_EDGE = 0x20
	// Position of SPI_CS_HOLD field.
	SPI2_SPI_USER_SPI_CS_HOLD_Pos = 0x6
	// Bit mask of SPI_CS_HOLD field.
	SPI2_SPI_USER_SPI_CS_HOLD_Msk = 0x40
	// Bit SPI_CS_HOLD.
	SPI2_SPI_USER_SPI_CS_HOLD = 0x40
	// Position of SPI_CS_SETUP field.
	SPI2_SPI_USER_SPI_CS_SETUP_Pos = 0x7
	// Bit mask of SPI_CS_SETUP field.
	SPI2_SPI_USER_SPI_CS_SETUP_Msk = 0x80
	// Bit SPI_CS_SETUP.
	SPI2_SPI_USER_SPI_CS_SETUP = 0x80
	// Position of SPI_RSCK_I_EDGE field.
	SPI2_SPI_USER_SPI_RSCK_I_EDGE_Pos = 0x8
	// Bit mask of SPI_RSCK_I_EDGE field.
	SPI2_SPI_USER_SPI_RSCK_I_EDGE_Msk = 0x100
	// Bit SPI_RSCK_I_EDGE.
	SPI2_SPI_USER_SPI_RSCK_I_EDGE = 0x100
	// Position of SPI_CK_OUT_EDGE field.
	SPI2_SPI_USER_SPI_CK_OUT_EDGE_Pos = 0x9
	// Bit mask of SPI_CK_OUT_EDGE field.
	SPI2_SPI_USER_SPI_CK_OUT_EDGE_Msk = 0x200
	// Bit SPI_CK_OUT_EDGE.
	SPI2_SPI_USER_SPI_CK_OUT_EDGE = 0x200
	// Position of SPI_FWRITE_DUAL field.
	SPI2_SPI_USER_SPI_FWRITE_DUAL_Pos = 0xc
	// Bit mask of SPI_FWRITE_DUAL field.
	SPI2_SPI_USER_SPI_FWRITE_DUAL_Msk = 0x1000
	// Bit SPI_FWRITE_DUAL.
	SPI2_SPI_USER_SPI_FWRITE_DUAL = 0x1000
	// Position of SPI_FWRITE_QUAD field.
	SPI2_SPI_USER_SPI_FWRITE_QUAD_Pos = 0xd
	// Bit mask of SPI_FWRITE_QUAD field.
	SPI2_SPI_USER_SPI_FWRITE_QUAD_Msk = 0x2000
	// Bit SPI_FWRITE_QUAD.
	SPI2_SPI_USER_SPI_FWRITE_QUAD = 0x2000
	// Position of SPI_FWRITE_OCT field.
	SPI2_SPI_USER_SPI_FWRITE_OCT_Pos = 0xe
	// Bit mask of SPI_FWRITE_OCT field.
	SPI2_SPI_USER_SPI_FWRITE_OCT_Msk = 0x4000
	// Bit SPI_FWRITE_OCT.
	SPI2_SPI_USER_SPI_FWRITE_OCT = 0x4000
	// Position of SPI_USR_CONF_NXT field.
	SPI2_SPI_USER_SPI_USR_CONF_NXT_Pos = 0xf
	// Bit mask of SPI_USR_CONF_NXT field.
	SPI2_SPI_USER_SPI_USR_CONF_NXT_Msk = 0x8000
	// Bit SPI_USR_CONF_NXT.
	SPI2_SPI_USER_SPI_USR_CONF_NXT = 0x8000
	// Position of SPI_SIO field.
	SPI2_SPI_USER_SPI_SIO_Pos = 0x11
	// Bit mask of SPI_SIO field.
	SPI2_SPI_USER_SPI_SIO_Msk = 0x20000
	// Bit SPI_SIO.
	SPI2_SPI_USER_SPI_SIO = 0x20000
	// Position of SPI_USR_MISO_HIGHPART field.
	SPI2_SPI_USER_SPI_USR_MISO_HIGHPART_Pos = 0x18
	// Bit mask of SPI_USR_MISO_HIGHPART field.
	SPI2_SPI_USER_SPI_USR_MISO_HIGHPART_Msk = 0x1000000
	// Bit SPI_USR_MISO_HIGHPART.
	SPI2_SPI_USER_SPI_USR_MISO_HIGHPART = 0x1000000
	// Position of SPI_USR_MOSI_HIGHPART field.
	SPI2_SPI_USER_SPI_USR_MOSI_HIGHPART_Pos = 0x19
	// Bit mask of SPI_USR_MOSI_HIGHPART field.
	SPI2_SPI_USER_SPI_USR_MOSI_HIGHPART_Msk = 0x2000000
	// Bit SPI_USR_MOSI_HIGHPART.
	SPI2_SPI_USER_SPI_USR_MOSI_HIGHPART = 0x2000000
	// Position of SPI_USR_DUMMY_IDLE field.
	SPI2_SPI_USER_SPI_USR_DUMMY_IDLE_Pos = 0x1a
	// Bit mask of SPI_USR_DUMMY_IDLE field.
	SPI2_SPI_USER_SPI_USR_DUMMY_IDLE_Msk = 0x4000000
	// Bit SPI_USR_DUMMY_IDLE.
	SPI2_SPI_USER_SPI_USR_DUMMY_IDLE = 0x4000000
	// Position of SPI_USR_MOSI field.
	SPI2_SPI_USER_SPI_USR_MOSI_Pos = 0x1b
	// Bit mask of SPI_USR_MOSI field.
	SPI2_SPI_USER_SPI_USR_MOSI_Msk = 0x8000000
	// Bit SPI_USR_MOSI.
	SPI2_SPI_USER_SPI_USR_MOSI = 0x8000000
	// Position of SPI_USR_MISO field.
	SPI2_SPI_USER_SPI_USR_MISO_Pos = 0x1c
	// Bit mask of SPI_USR_MISO field.
	SPI2_SPI_USER_SPI_USR_MISO_Msk = 0x10000000
	// Bit SPI_USR_MISO.
	SPI2_SPI_USER_SPI_USR_MISO = 0x10000000
	// Position of SPI_USR_DUMMY field.
	SPI2_SPI_USER_SPI_USR_DUMMY_Pos = 0x1d
	// Bit mask of SPI_USR_DUMMY field.
	SPI2_SPI_USER_SPI_USR_DUMMY_Msk = 0x20000000
	// Bit SPI_USR_DUMMY.
	SPI2_SPI_USER_SPI_USR_DUMMY = 0x20000000
	// Position of SPI_USR_ADDR field.
	SPI2_SPI_USER_SPI_USR_ADDR_Pos = 0x1e
	// Bit mask of SPI_USR_ADDR field.
	SPI2_SPI_USER_SPI_USR_ADDR_Msk = 0x40000000
	// Bit SPI_USR_ADDR.
	SPI2_SPI_USER_SPI_USR_ADDR = 0x40000000
	// Position of SPI_USR_COMMAND field.
	SPI2_SPI_USER_SPI_USR_COMMAND_Pos = 0x1f
	// Bit mask of SPI_USR_COMMAND field.
	SPI2_SPI_USER_SPI_USR_COMMAND_Msk = 0x80000000
	// Bit SPI_USR_COMMAND.
	SPI2_SPI_USER_SPI_USR_COMMAND = 0x80000000

	// SPI_USER1: SPI USER control register 1
	// Position of SPI_USR_DUMMY_CYCLELEN field.
	SPI2_SPI_USER1_SPI_USR_DUMMY_CYCLELEN_Pos = 0x0
	// Bit mask of SPI_USR_DUMMY_CYCLELEN field.
	SPI2_SPI_USER1_SPI_USR_DUMMY_CYCLELEN_Msk = 0xff
	// Position of SPI_MST_WFULL_ERR_END_EN field.
	SPI2_SPI_USER1_SPI_MST_WFULL_ERR_END_EN_Pos = 0x10
	// Bit mask of SPI_MST_WFULL_ERR_END_EN field.
	SPI2_SPI_USER1_SPI_MST_WFULL_ERR_END_EN_Msk = 0x10000
	// Bit SPI_MST_WFULL_ERR_END_EN.
	SPI2_SPI_USER1_SPI_MST_WFULL_ERR_END_EN = 0x10000
	// Position of SPI_CS_SETUP_TIME field.
	SPI2_SPI_USER1_SPI_CS_SETUP_TIME_Pos = 0x11
	// Bit mask of SPI_CS_SETUP_TIME field.
	SPI2_SPI_USER1_SPI_CS_SETUP_TIME_Msk = 0x3e0000
	// Position of SPI_CS_HOLD_TIME field.
	SPI2_SPI_USER1_SPI_CS_HOLD_TIME_Pos = 0x16
	// Bit mask of SPI_CS_HOLD_TIME field.
	SPI2_SPI_USER1_SPI_CS_HOLD_TIME_Msk = 0x7c00000
	// Position of SPI_USR_ADDR_BITLEN field.
	SPI2_SPI_USER1_SPI_USR_ADDR_BITLEN_Pos = 0x1b
	// Bit mask of SPI_USR_ADDR_BITLEN field.
	SPI2_SPI_USER1_SPI_USR_ADDR_BITLEN_Msk = 0xf8000000

	// SPI_USER2: SPI USER control register 2
	// Position of SPI_USR_COMMAND_VALUE field.
	SPI2_SPI_USER2_SPI_USR_COMMAND_VALUE_Pos = 0x0
	// Bit mask of SPI_USR_COMMAND_VALUE field.
	SPI2_SPI_USER2_SPI_USR_COMMAND_VALUE_Msk = 0xffff
	// Position of SPI_MST_REMPTY_ERR_END_EN field.
	SPI2_SPI_USER2_SPI_MST_REMPTY_ERR_END_EN_Pos = 0x1b
	// Bit mask of SPI_MST_REMPTY_ERR_END_EN field.
	SPI2_SPI_USER2_SPI_MST_REMPTY_ERR_END_EN_Msk = 0x8000000
	// Bit SPI_MST_REMPTY_ERR_END_EN.
	SPI2_SPI_USER2_SPI_MST_REMPTY_ERR_END_EN = 0x8000000
	// Position of SPI_USR_COMMAND_BITLEN field.
	SPI2_SPI_USER2_SPI_USR_COMMAND_BITLEN_Pos = 0x1c
	// Bit mask of SPI_USR_COMMAND_BITLEN field.
	SPI2_SPI_USER2_SPI_USR_COMMAND_BITLEN_Msk = 0xf0000000

	// SPI_MS_DLEN: SPI data bit length control register
	// Position of SPI_MS_DATA_BITLEN field.
	SPI2_SPI_MS_DLEN_SPI_MS_DATA_BITLEN_Pos = 0x0
	// Bit mask of SPI_MS_DATA_BITLEN field.
	SPI2_SPI_MS_DLEN_SPI_MS_DATA_BITLEN_Msk = 0x3ffff

	// SPI_MISC: SPI misc register
	// Position of SPI_CS0_DIS field.
	SPI2_SPI_MISC_SPI_CS0_DIS_Pos = 0x0
	// Bit mask of SPI_CS0_DIS field.
	SPI2_SPI_MISC_SPI_CS0_DIS_Msk = 0x1
	// Bit SPI_CS0_DIS.
	SPI2_SPI_MISC_SPI_CS0_DIS = 0x1
	// Position of SPI_CS1_DIS field.
	SPI2_SPI_MISC_SPI_CS1_DIS_Pos = 0x1
	// Bit mask of SPI_CS1_DIS field.
	SPI2_SPI_MISC_SPI_CS1_DIS_Msk = 0x2
	// Bit SPI_CS1_DIS.
	SPI2_SPI_MISC_SPI_CS1_DIS = 0x2
	// Position of SPI_CS2_DIS field.
	SPI2_SPI_MISC_SPI_CS2_DIS_Pos = 0x2
	// Bit mask of SPI_CS2_DIS field.
	SPI2_SPI_MISC_SPI_CS2_DIS_Msk = 0x4
	// Bit SPI_CS2_DIS.
	SPI2_SPI_MISC_SPI_CS2_DIS = 0x4
	// Position of SPI_CS3_DIS field.
	SPI2_SPI_MISC_SPI_CS3_DIS_Pos = 0x3
	// Bit mask of SPI_CS3_DIS field.
	SPI2_SPI_MISC_SPI_CS3_DIS_Msk = 0x8
	// Bit SPI_CS3_DIS.
	SPI2_SPI_MISC_SPI_CS3_DIS = 0x8
	// Position of SPI_CS4_DIS field.
	SPI2_SPI_MISC_SPI_CS4_DIS_Pos = 0x4
	// Bit mask of SPI_CS4_DIS field.
	SPI2_SPI_MISC_SPI_CS4_DIS_Msk = 0x10
	// Bit SPI_CS4_DIS.
	SPI2_SPI_MISC_SPI_CS4_DIS = 0x10
	// Position of SPI_CS5_DIS field.
	SPI2_SPI_MISC_SPI_CS5_DIS_Pos = 0x5
	// Bit mask of SPI_CS5_DIS field.
	SPI2_SPI_MISC_SPI_CS5_DIS_Msk = 0x20
	// Bit SPI_CS5_DIS.
	SPI2_SPI_MISC_SPI_CS5_DIS = 0x20
	// Position of SPI_CK_DIS field.
	SPI2_SPI_MISC_SPI_CK_DIS_Pos = 0x6
	// Bit mask of SPI_CK_DIS field.
	SPI2_SPI_MISC_SPI_CK_DIS_Msk = 0x40
	// Bit SPI_CK_DIS.
	SPI2_SPI_MISC_SPI_CK_DIS = 0x40
	// Position of SPI_MASTER_CS_POL field.
	SPI2_SPI_MISC_SPI_MASTER_CS_POL_Pos = 0x7
	// Bit mask of SPI_MASTER_CS_POL field.
	SPI2_SPI_MISC_SPI_MASTER_CS_POL_Msk = 0x1f80
	// Position of SPI_CLK_DATA_DTR_EN field.
	SPI2_SPI_MISC_SPI_CLK_DATA_DTR_EN_Pos = 0x10
	// Bit mask of SPI_CLK_DATA_DTR_EN field.
	SPI2_SPI_MISC_SPI_CLK_DATA_DTR_EN_Msk = 0x10000
	// Bit SPI_CLK_DATA_DTR_EN.
	SPI2_SPI_MISC_SPI_CLK_DATA_DTR_EN = 0x10000
	// Position of SPI_DATA_DTR_EN field.
	SPI2_SPI_MISC_SPI_DATA_DTR_EN_Pos = 0x11
	// Bit mask of SPI_DATA_DTR_EN field.
	SPI2_SPI_MISC_SPI_DATA_DTR_EN_Msk = 0x20000
	// Bit SPI_DATA_DTR_EN.
	SPI2_SPI_MISC_SPI_DATA_DTR_EN = 0x20000
	// Position of SPI_ADDR_DTR_EN field.
	SPI2_SPI_MISC_SPI_ADDR_DTR_EN_Pos = 0x12
	// Bit mask of SPI_ADDR_DTR_EN field.
	SPI2_SPI_MISC_SPI_ADDR_DTR_EN_Msk = 0x40000
	// Bit SPI_ADDR_DTR_EN.
	SPI2_SPI_MISC_SPI_ADDR_DTR_EN = 0x40000
	// Position of SPI_CMD_DTR_EN field.
	SPI2_SPI_MISC_SPI_CMD_DTR_EN_Pos = 0x13
	// Bit mask of SPI_CMD_DTR_EN field.
	SPI2_SPI_MISC_SPI_CMD_DTR_EN_Msk = 0x80000
	// Bit SPI_CMD_DTR_EN.
	SPI2_SPI_MISC_SPI_CMD_DTR_EN = 0x80000
	// Position of SPI_SLAVE_CS_POL field.
	SPI2_SPI_MISC_SPI_SLAVE_CS_POL_Pos = 0x17
	// Bit mask of SPI_SLAVE_CS_POL field.
	SPI2_SPI_MISC_SPI_SLAVE_CS_POL_Msk = 0x800000
	// Bit SPI_SLAVE_CS_POL.
	SPI2_SPI_MISC_SPI_SLAVE_CS_POL = 0x800000
	// Position of SPI_DQS_IDLE_EDGE field.
	SPI2_SPI_MISC_SPI_DQS_IDLE_EDGE_Pos = 0x18
	// Bit mask of SPI_DQS_IDLE_EDGE field.
	SPI2_SPI_MISC_SPI_DQS_IDLE_EDGE_Msk = 0x1000000
	// Bit SPI_DQS_IDLE_EDGE.
	SPI2_SPI_MISC_SPI_DQS_IDLE_EDGE = 0x1000000
	// Position of SPI_CK_IDLE_EDGE field.
	SPI2_SPI_MISC_SPI_CK_IDLE_EDGE_Pos = 0x1d
	// Bit mask of SPI_CK_IDLE_EDGE field.
	SPI2_SPI_MISC_SPI_CK_IDLE_EDGE_Msk = 0x20000000
	// Bit SPI_CK_IDLE_EDGE.
	SPI2_SPI_MISC_SPI_CK_IDLE_EDGE = 0x20000000
	// Position of SPI_CS_KEEP_ACTIVE field.
	SPI2_SPI_MISC_SPI_CS_KEEP_ACTIVE_Pos = 0x1e
	// Bit mask of SPI_CS_KEEP_ACTIVE field.
	SPI2_SPI_MISC_SPI_CS_KEEP_ACTIVE_Msk = 0x40000000
	// Bit SPI_CS_KEEP_ACTIVE.
	SPI2_SPI_MISC_SPI_CS_KEEP_ACTIVE = 0x40000000
	// Position of SPI_QUAD_DIN_PIN_SWAP field.
	SPI2_SPI_MISC_SPI_QUAD_DIN_PIN_SWAP_Pos = 0x1f
	// Bit mask of SPI_QUAD_DIN_PIN_SWAP field.
	SPI2_SPI_MISC_SPI_QUAD_DIN_PIN_SWAP_Msk = 0x80000000
	// Bit SPI_QUAD_DIN_PIN_SWAP.
	SPI2_SPI_MISC_SPI_QUAD_DIN_PIN_SWAP = 0x80000000

	// SPI_DIN_MODE: SPI input delay mode configuration
	// Position of SPI_DIN0_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN0_MODE_Pos = 0x0
	// Bit mask of SPI_DIN0_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN0_MODE_Msk = 0x3
	// Position of SPI_DIN1_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN1_MODE_Pos = 0x2
	// Bit mask of SPI_DIN1_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN1_MODE_Msk = 0xc
	// Position of SPI_DIN2_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN2_MODE_Pos = 0x4
	// Bit mask of SPI_DIN2_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN2_MODE_Msk = 0x30
	// Position of SPI_DIN3_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN3_MODE_Pos = 0x6
	// Bit mask of SPI_DIN3_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN3_MODE_Msk = 0xc0
	// Position of SPI_DIN4_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN4_MODE_Pos = 0x8
	// Bit mask of SPI_DIN4_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN4_MODE_Msk = 0x300
	// Position of SPI_DIN5_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN5_MODE_Pos = 0xa
	// Bit mask of SPI_DIN5_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN5_MODE_Msk = 0xc00
	// Position of SPI_DIN6_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN6_MODE_Pos = 0xc
	// Bit mask of SPI_DIN6_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN6_MODE_Msk = 0x3000
	// Position of SPI_DIN7_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN7_MODE_Pos = 0xe
	// Bit mask of SPI_DIN7_MODE field.
	SPI2_SPI_DIN_MODE_SPI_DIN7_MODE_Msk = 0xc000
	// Position of SPI_TIMING_HCLK_ACTIVE field.
	SPI2_SPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE_Pos = 0x10
	// Bit mask of SPI_TIMING_HCLK_ACTIVE field.
	SPI2_SPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE_Msk = 0x10000
	// Bit SPI_TIMING_HCLK_ACTIVE.
	SPI2_SPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE = 0x10000

	// SPI_DIN_NUM: SPI input delay number configuration
	// Position of SPI_DIN0_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN0_NUM_Pos = 0x0
	// Bit mask of SPI_DIN0_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN0_NUM_Msk = 0x3
	// Position of SPI_DIN1_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN1_NUM_Pos = 0x2
	// Bit mask of SPI_DIN1_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN1_NUM_Msk = 0xc
	// Position of SPI_DIN2_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN2_NUM_Pos = 0x4
	// Bit mask of SPI_DIN2_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN2_NUM_Msk = 0x30
	// Position of SPI_DIN3_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN3_NUM_Pos = 0x6
	// Bit mask of SPI_DIN3_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN3_NUM_Msk = 0xc0
	// Position of SPI_DIN4_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN4_NUM_Pos = 0x8
	// Bit mask of SPI_DIN4_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN4_NUM_Msk = 0x300
	// Position of SPI_DIN5_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN5_NUM_Pos = 0xa
	// Bit mask of SPI_DIN5_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN5_NUM_Msk = 0xc00
	// Position of SPI_DIN6_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN6_NUM_Pos = 0xc
	// Bit mask of SPI_DIN6_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN6_NUM_Msk = 0x3000
	// Position of SPI_DIN7_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN7_NUM_Pos = 0xe
	// Bit mask of SPI_DIN7_NUM field.
	SPI2_SPI_DIN_NUM_SPI_DIN7_NUM_Msk = 0xc000

	// SPI_DOUT_MODE: SPI output delay mode configuration
	// Position of SPI_DOUT0_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT0_MODE_Pos = 0x0
	// Bit mask of SPI_DOUT0_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT0_MODE_Msk = 0x1
	// Bit SPI_DOUT0_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT0_MODE = 0x1
	// Position of SPI_DOUT1_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT1_MODE_Pos = 0x1
	// Bit mask of SPI_DOUT1_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT1_MODE_Msk = 0x2
	// Bit SPI_DOUT1_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT1_MODE = 0x2
	// Position of SPI_DOUT2_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT2_MODE_Pos = 0x2
	// Bit mask of SPI_DOUT2_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT2_MODE_Msk = 0x4
	// Bit SPI_DOUT2_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT2_MODE = 0x4
	// Position of SPI_DOUT3_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT3_MODE_Pos = 0x3
	// Bit mask of SPI_DOUT3_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT3_MODE_Msk = 0x8
	// Bit SPI_DOUT3_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT3_MODE = 0x8
	// Position of SPI_DOUT4_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT4_MODE_Pos = 0x4
	// Bit mask of SPI_DOUT4_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT4_MODE_Msk = 0x10
	// Bit SPI_DOUT4_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT4_MODE = 0x10
	// Position of SPI_DOUT5_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT5_MODE_Pos = 0x5
	// Bit mask of SPI_DOUT5_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT5_MODE_Msk = 0x20
	// Bit SPI_DOUT5_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT5_MODE = 0x20
	// Position of SPI_DOUT6_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT6_MODE_Pos = 0x6
	// Bit mask of SPI_DOUT6_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT6_MODE_Msk = 0x40
	// Bit SPI_DOUT6_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT6_MODE = 0x40
	// Position of SPI_DOUT7_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT7_MODE_Pos = 0x7
	// Bit mask of SPI_DOUT7_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_DOUT7_MODE_Msk = 0x80
	// Bit SPI_DOUT7_MODE.
	SPI2_SPI_DOUT_MODE_SPI_DOUT7_MODE = 0x80
	// Position of SPI_D_DQS_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_D_DQS_MODE_Pos = 0x8
	// Bit mask of SPI_D_DQS_MODE field.
	SPI2_SPI_DOUT_MODE_SPI_D_DQS_MODE_Msk = 0x100
	// Bit SPI_D_DQS_MODE.
	SPI2_SPI_DOUT_MODE_SPI_D_DQS_MODE = 0x100

	// SPI_DMA_CONF: SPI DMA control register
	// Position of SPI_DMA_OUTFIFO_EMPTY field.
	SPI2_SPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY_Pos = 0x0
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY field.
	SPI2_SPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY_Msk = 0x1
	// Bit SPI_DMA_OUTFIFO_EMPTY.
	SPI2_SPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY = 0x1
	// Position of SPI_DMA_INFIFO_FULL field.
	SPI2_SPI_DMA_CONF_SPI_DMA_INFIFO_FULL_Pos = 0x1
	// Bit mask of SPI_DMA_INFIFO_FULL field.
	SPI2_SPI_DMA_CONF_SPI_DMA_INFIFO_FULL_Msk = 0x2
	// Bit SPI_DMA_INFIFO_FULL.
	SPI2_SPI_DMA_CONF_SPI_DMA_INFIFO_FULL = 0x2
	// Position of SPI_DMA_SLV_SEG_TRANS_EN field.
	SPI2_SPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN_Pos = 0x12
	// Bit mask of SPI_DMA_SLV_SEG_TRANS_EN field.
	SPI2_SPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000
	// Bit SPI_DMA_SLV_SEG_TRANS_EN.
	SPI2_SPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN = 0x40000
	// Position of SPI_SLV_RX_SEG_TRANS_CLR_EN field.
	SPI2_SPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13
	// Bit mask of SPI_SLV_RX_SEG_TRANS_CLR_EN field.
	SPI2_SPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000
	// Bit SPI_SLV_RX_SEG_TRANS_CLR_EN.
	SPI2_SPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN = 0x80000
	// Position of SPI_SLV_TX_SEG_TRANS_CLR_EN field.
	SPI2_SPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14
	// Bit mask of SPI_SLV_TX_SEG_TRANS_CLR_EN field.
	SPI2_SPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000
	// Bit SPI_SLV_TX_SEG_TRANS_CLR_EN.
	SPI2_SPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN = 0x100000
	// Position of SPI_RX_EOF_EN field.
	SPI2_SPI_DMA_CONF_SPI_RX_EOF_EN_Pos = 0x15
	// Bit mask of SPI_RX_EOF_EN field.
	SPI2_SPI_DMA_CONF_SPI_RX_EOF_EN_Msk = 0x200000
	// Bit SPI_RX_EOF_EN.
	SPI2_SPI_DMA_CONF_SPI_RX_EOF_EN = 0x200000
	// Position of SPI_DMA_RX_ENA field.
	SPI2_SPI_DMA_CONF_SPI_DMA_RX_ENA_Pos = 0x1b
	// Bit mask of SPI_DMA_RX_ENA field.
	SPI2_SPI_DMA_CONF_SPI_DMA_RX_ENA_Msk = 0x8000000
	// Bit SPI_DMA_RX_ENA.
	SPI2_SPI_DMA_CONF_SPI_DMA_RX_ENA = 0x8000000
	// Position of SPI_DMA_TX_ENA field.
	SPI2_SPI_DMA_CONF_SPI_DMA_TX_ENA_Pos = 0x1c
	// Bit mask of SPI_DMA_TX_ENA field.
	SPI2_SPI_DMA_CONF_SPI_DMA_TX_ENA_Msk = 0x10000000
	// Bit SPI_DMA_TX_ENA.
	SPI2_SPI_DMA_CONF_SPI_DMA_TX_ENA = 0x10000000
	// Position of SPI_RX_AFIFO_RST field.
	SPI2_SPI_DMA_CONF_SPI_RX_AFIFO_RST_Pos = 0x1d
	// Bit mask of SPI_RX_AFIFO_RST field.
	SPI2_SPI_DMA_CONF_SPI_RX_AFIFO_RST_Msk = 0x20000000
	// Bit SPI_RX_AFIFO_RST.
	SPI2_SPI_DMA_CONF_SPI_RX_AFIFO_RST = 0x20000000
	// Position of SPI_BUF_AFIFO_RST field.
	SPI2_SPI_DMA_CONF_SPI_BUF_AFIFO_RST_Pos = 0x1e
	// Bit mask of SPI_BUF_AFIFO_RST field.
	SPI2_SPI_DMA_CONF_SPI_BUF_AFIFO_RST_Msk = 0x40000000
	// Bit SPI_BUF_AFIFO_RST.
	SPI2_SPI_DMA_CONF_SPI_BUF_AFIFO_RST = 0x40000000
	// Position of SPI_DMA_AFIFO_RST field.
	SPI2_SPI_DMA_CONF_SPI_DMA_AFIFO_RST_Pos = 0x1f
	// Bit mask of SPI_DMA_AFIFO_RST field.
	SPI2_SPI_DMA_CONF_SPI_DMA_AFIFO_RST_Msk = 0x80000000
	// Bit SPI_DMA_AFIFO_RST.
	SPI2_SPI_DMA_CONF_SPI_DMA_AFIFO_RST = 0x80000000

	// SPI_DMA_INT_ENA: SPI interrupt enable register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x2
	// Position of SPI_SLV_EX_QPI_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA = 0x4
	// Position of SPI_SLV_EN_QPI_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA = 0x8
	// Position of SPI_SLV_CMD7_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA = 0x10
	// Position of SPI_SLV_CMD8_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA = 0x20
	// Position of SPI_SLV_CMD9_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA = 0x40
	// Position of SPI_SLV_CMDA_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA = 0x800
	// Position of SPI_TRANS_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA = 0x2000
	// Position of SPI_SEG_MAGIC_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SEG_MAGIC_ERR_INT_ENA_Pos = 0xe
	// Bit mask of SPI_SEG_MAGIC_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SEG_MAGIC_ERR_INT_ENA_Msk = 0x4000
	// Bit SPI_SEG_MAGIC_ERR_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SEG_MAGIC_ERR_INT_ENA = 0x4000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA = 0x40000
	// Position of SPI_APP2_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_APP2_INT_ENA_Pos = 0x13
	// Bit mask of SPI_APP2_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_APP2_INT_ENA_Msk = 0x80000
	// Bit SPI_APP2_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_APP2_INT_ENA = 0x80000
	// Position of SPI_APP1_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_APP1_INT_ENA_Pos = 0x14
	// Bit mask of SPI_APP1_INT_ENA field.
	SPI2_SPI_DMA_INT_ENA_SPI_APP1_INT_ENA_Msk = 0x100000
	// Bit SPI_APP1_INT_ENA.
	SPI2_SPI_DMA_INT_ENA_SPI_APP1_INT_ENA = 0x100000

	// SPI_DMA_INT_CLR: SPI interrupt clear register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR = 0x2
	// Position of SPI_SLV_EX_QPI_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR = 0x4
	// Position of SPI_SLV_EN_QPI_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR = 0x8
	// Position of SPI_SLV_CMD7_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR = 0x10
	// Position of SPI_SLV_CMD8_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR = 0x20
	// Position of SPI_SLV_CMD9_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR = 0x40
	// Position of SPI_SLV_CMDA_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR = 0x800
	// Position of SPI_TRANS_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR = 0x2000
	// Position of SPI_SEG_MAGIC_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SEG_MAGIC_ERR_INT_CLR_Pos = 0xe
	// Bit mask of SPI_SEG_MAGIC_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SEG_MAGIC_ERR_INT_CLR_Msk = 0x4000
	// Bit SPI_SEG_MAGIC_ERR_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SEG_MAGIC_ERR_INT_CLR = 0x4000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR = 0x40000
	// Position of SPI_APP2_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_APP2_INT_CLR_Pos = 0x13
	// Bit mask of SPI_APP2_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_APP2_INT_CLR_Msk = 0x80000
	// Bit SPI_APP2_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_APP2_INT_CLR = 0x80000
	// Position of SPI_APP1_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_APP1_INT_CLR_Pos = 0x14
	// Bit mask of SPI_APP1_INT_CLR field.
	SPI2_SPI_DMA_INT_CLR_SPI_APP1_INT_CLR_Msk = 0x100000
	// Bit SPI_APP1_INT_CLR.
	SPI2_SPI_DMA_INT_CLR_SPI_APP1_INT_CLR = 0x100000

	// SPI_DMA_INT_RAW: SPI interrupt raw register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW = 0x2
	// Position of SPI_SLV_EX_QPI_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW = 0x4
	// Position of SPI_SLV_EN_QPI_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW = 0x8
	// Position of SPI_SLV_CMD7_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW = 0x10
	// Position of SPI_SLV_CMD8_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW = 0x20
	// Position of SPI_SLV_CMD9_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW = 0x40
	// Position of SPI_SLV_CMDA_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW = 0x800
	// Position of SPI_TRANS_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW = 0x2000
	// Position of SPI_SEG_MAGIC_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SEG_MAGIC_ERR_INT_RAW_Pos = 0xe
	// Bit mask of SPI_SEG_MAGIC_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SEG_MAGIC_ERR_INT_RAW_Msk = 0x4000
	// Bit SPI_SEG_MAGIC_ERR_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SEG_MAGIC_ERR_INT_RAW = 0x4000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW = 0x40000
	// Position of SPI_APP2_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_APP2_INT_RAW_Pos = 0x13
	// Bit mask of SPI_APP2_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_APP2_INT_RAW_Msk = 0x80000
	// Bit SPI_APP2_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_APP2_INT_RAW = 0x80000
	// Position of SPI_APP1_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_APP1_INT_RAW_Pos = 0x14
	// Bit mask of SPI_APP1_INT_RAW field.
	SPI2_SPI_DMA_INT_RAW_SPI_APP1_INT_RAW_Msk = 0x100000
	// Bit SPI_APP1_INT_RAW.
	SPI2_SPI_DMA_INT_RAW_SPI_APP1_INT_RAW = 0x100000

	// SPI_DMA_INT_ST: SPI interrupt status register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST = 0x2
	// Position of SPI_SLV_EX_QPI_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST = 0x4
	// Position of SPI_SLV_EN_QPI_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST = 0x8
	// Position of SPI_SLV_CMD7_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST = 0x10
	// Position of SPI_SLV_CMD8_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST = 0x20
	// Position of SPI_SLV_CMD9_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST = 0x40
	// Position of SPI_SLV_CMDA_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST = 0x800
	// Position of SPI_TRANS_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST = 0x2000
	// Position of SPI_SEG_MAGIC_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SEG_MAGIC_ERR_INT_ST_Pos = 0xe
	// Bit mask of SPI_SEG_MAGIC_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SEG_MAGIC_ERR_INT_ST_Msk = 0x4000
	// Bit SPI_SEG_MAGIC_ERR_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SEG_MAGIC_ERR_INT_ST = 0x4000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST = 0x40000
	// Position of SPI_APP2_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_APP2_INT_ST_Pos = 0x13
	// Bit mask of SPI_APP2_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_APP2_INT_ST_Msk = 0x80000
	// Bit SPI_APP2_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_APP2_INT_ST = 0x80000
	// Position of SPI_APP1_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_APP1_INT_ST_Pos = 0x14
	// Bit mask of SPI_APP1_INT_ST field.
	SPI2_SPI_DMA_INT_ST_SPI_APP1_INT_ST_Msk = 0x100000
	// Bit SPI_APP1_INT_ST.
	SPI2_SPI_DMA_INT_ST_SPI_APP1_INT_ST = 0x100000

	// SPI_DMA_INT_SET: SPI interrupt software set register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET = 0x2
	// Position of SPI_SLV_EX_QPI_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET = 0x4
	// Position of SPI_SLV_EN_QPI_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET = 0x8
	// Position of SPI_SLV_CMD7_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET = 0x10
	// Position of SPI_SLV_CMD8_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET = 0x20
	// Position of SPI_SLV_CMD9_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET = 0x40
	// Position of SPI_SLV_CMDA_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET = 0x800
	// Position of SPI_TRANS_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET = 0x2000
	// Position of SPI_SEG_MAGIC_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SEG_MAGIC_ERR_INT_SET_Pos = 0xe
	// Bit mask of SPI_SEG_MAGIC_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SEG_MAGIC_ERR_INT_SET_Msk = 0x4000
	// Bit SPI_SEG_MAGIC_ERR_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SEG_MAGIC_ERR_INT_SET = 0x4000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET = 0x40000
	// Position of SPI_APP2_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_APP2_INT_SET_Pos = 0x13
	// Bit mask of SPI_APP2_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_APP2_INT_SET_Msk = 0x80000
	// Bit SPI_APP2_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_APP2_INT_SET = 0x80000
	// Position of SPI_APP1_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_APP1_INT_SET_Pos = 0x14
	// Bit mask of SPI_APP1_INT_SET field.
	SPI2_SPI_DMA_INT_SET_SPI_APP1_INT_SET_Msk = 0x100000
	// Bit SPI_APP1_INT_SET.
	SPI2_SPI_DMA_INT_SET_SPI_APP1_INT_SET = 0x100000

	// SPI_W0: SPI CPU-controlled buffer0
	// Position of SPI_BUF0 field.
	SPI2_SPI_W0_SPI_BUF0_Pos = 0x0
	// Bit mask of SPI_BUF0 field.
	SPI2_SPI_W0_SPI_BUF0_Msk = 0xffffffff

	// SPI_W1: SPI CPU-controlled buffer1
	// Position of SPI_BUF1 field.
	SPI2_SPI_W1_SPI_BUF1_Pos = 0x0
	// Bit mask of SPI_BUF1 field.
	SPI2_SPI_W1_SPI_BUF1_Msk = 0xffffffff

	// SPI_W2: SPI CPU-controlled buffer2
	// Position of SPI_BUF2 field.
	SPI2_SPI_W2_SPI_BUF2_Pos = 0x0
	// Bit mask of SPI_BUF2 field.
	SPI2_SPI_W2_SPI_BUF2_Msk = 0xffffffff

	// SPI_W3: SPI CPU-controlled buffer3
	// Position of SPI_BUF3 field.
	SPI2_SPI_W3_SPI_BUF3_Pos = 0x0
	// Bit mask of SPI_BUF3 field.
	SPI2_SPI_W3_SPI_BUF3_Msk = 0xffffffff

	// SPI_W4: SPI CPU-controlled buffer4
	// Position of SPI_BUF4 field.
	SPI2_SPI_W4_SPI_BUF4_Pos = 0x0
	// Bit mask of SPI_BUF4 field.
	SPI2_SPI_W4_SPI_BUF4_Msk = 0xffffffff

	// SPI_W5: SPI CPU-controlled buffer5
	// Position of SPI_BUF5 field.
	SPI2_SPI_W5_SPI_BUF5_Pos = 0x0
	// Bit mask of SPI_BUF5 field.
	SPI2_SPI_W5_SPI_BUF5_Msk = 0xffffffff

	// SPI_W6: SPI CPU-controlled buffer6
	// Position of SPI_BUF6 field.
	SPI2_SPI_W6_SPI_BUF6_Pos = 0x0
	// Bit mask of SPI_BUF6 field.
	SPI2_SPI_W6_SPI_BUF6_Msk = 0xffffffff

	// SPI_W7: SPI CPU-controlled buffer7
	// Position of SPI_BUF7 field.
	SPI2_SPI_W7_SPI_BUF7_Pos = 0x0
	// Bit mask of SPI_BUF7 field.
	SPI2_SPI_W7_SPI_BUF7_Msk = 0xffffffff

	// SPI_W8: SPI CPU-controlled buffer8
	// Position of SPI_BUF8 field.
	SPI2_SPI_W8_SPI_BUF8_Pos = 0x0
	// Bit mask of SPI_BUF8 field.
	SPI2_SPI_W8_SPI_BUF8_Msk = 0xffffffff

	// SPI_W9: SPI CPU-controlled buffer9
	// Position of SPI_BUF9 field.
	SPI2_SPI_W9_SPI_BUF9_Pos = 0x0
	// Bit mask of SPI_BUF9 field.
	SPI2_SPI_W9_SPI_BUF9_Msk = 0xffffffff

	// SPI_W10: SPI CPU-controlled buffer10
	// Position of SPI_BUF10 field.
	SPI2_SPI_W10_SPI_BUF10_Pos = 0x0
	// Bit mask of SPI_BUF10 field.
	SPI2_SPI_W10_SPI_BUF10_Msk = 0xffffffff

	// SPI_W11: SPI CPU-controlled buffer11
	// Position of SPI_BUF11 field.
	SPI2_SPI_W11_SPI_BUF11_Pos = 0x0
	// Bit mask of SPI_BUF11 field.
	SPI2_SPI_W11_SPI_BUF11_Msk = 0xffffffff

	// SPI_W12: SPI CPU-controlled buffer12
	// Position of SPI_BUF12 field.
	SPI2_SPI_W12_SPI_BUF12_Pos = 0x0
	// Bit mask of SPI_BUF12 field.
	SPI2_SPI_W12_SPI_BUF12_Msk = 0xffffffff

	// SPI_W13: SPI CPU-controlled buffer13
	// Position of SPI_BUF13 field.
	SPI2_SPI_W13_SPI_BUF13_Pos = 0x0
	// Bit mask of SPI_BUF13 field.
	SPI2_SPI_W13_SPI_BUF13_Msk = 0xffffffff

	// SPI_W14: SPI CPU-controlled buffer14
	// Position of SPI_BUF14 field.
	SPI2_SPI_W14_SPI_BUF14_Pos = 0x0
	// Bit mask of SPI_BUF14 field.
	SPI2_SPI_W14_SPI_BUF14_Msk = 0xffffffff

	// SPI_W15: SPI CPU-controlled buffer15
	// Position of SPI_BUF15 field.
	SPI2_SPI_W15_SPI_BUF15_Pos = 0x0
	// Bit mask of SPI_BUF15 field.
	SPI2_SPI_W15_SPI_BUF15_Msk = 0xffffffff

	// SPI_SLAVE: SPI slave control register
	// Position of SPI_CLK_MODE field.
	SPI2_SPI_SLAVE_SPI_CLK_MODE_Pos = 0x0
	// Bit mask of SPI_CLK_MODE field.
	SPI2_SPI_SLAVE_SPI_CLK_MODE_Msk = 0x3
	// Position of SPI_CLK_MODE_13 field.
	SPI2_SPI_SLAVE_SPI_CLK_MODE_13_Pos = 0x2
	// Bit mask of SPI_CLK_MODE_13 field.
	SPI2_SPI_SLAVE_SPI_CLK_MODE_13_Msk = 0x4
	// Bit SPI_CLK_MODE_13.
	SPI2_SPI_SLAVE_SPI_CLK_MODE_13 = 0x4
	// Position of SPI_RSCK_DATA_OUT field.
	SPI2_SPI_SLAVE_SPI_RSCK_DATA_OUT_Pos = 0x3
	// Bit mask of SPI_RSCK_DATA_OUT field.
	SPI2_SPI_SLAVE_SPI_RSCK_DATA_OUT_Msk = 0x8
	// Bit SPI_RSCK_DATA_OUT.
	SPI2_SPI_SLAVE_SPI_RSCK_DATA_OUT = 0x8
	// Position of SPI_SLV_RDDMA_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN_Pos = 0x8
	// Bit mask of SPI_SLV_RDDMA_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN_Msk = 0x100
	// Bit SPI_SLV_RDDMA_BITLEN_EN.
	SPI2_SPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN = 0x100
	// Position of SPI_SLV_WRDMA_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN_Pos = 0x9
	// Bit mask of SPI_SLV_WRDMA_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN_Msk = 0x200
	// Bit SPI_SLV_WRDMA_BITLEN_EN.
	SPI2_SPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN = 0x200
	// Position of SPI_SLV_RDBUF_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN_Pos = 0xa
	// Bit mask of SPI_SLV_RDBUF_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN_Msk = 0x400
	// Bit SPI_SLV_RDBUF_BITLEN_EN.
	SPI2_SPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN = 0x400
	// Position of SPI_SLV_WRBUF_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN_Pos = 0xb
	// Bit mask of SPI_SLV_WRBUF_BITLEN_EN field.
	SPI2_SPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN_Msk = 0x800
	// Bit SPI_SLV_WRBUF_BITLEN_EN.
	SPI2_SPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN = 0x800
	// Position of SPI_SLV_LAST_BYTE_STRB field.
	SPI2_SPI_SLAVE_SPI_SLV_LAST_BYTE_STRB_Pos = 0xc
	// Bit mask of SPI_SLV_LAST_BYTE_STRB field.
	SPI2_SPI_SLAVE_SPI_SLV_LAST_BYTE_STRB_Msk = 0xff000
	// Position of SPI_DMA_SEG_MAGIC_VALUE field.
	SPI2_SPI_SLAVE_SPI_DMA_SEG_MAGIC_VALUE_Pos = 0x16
	// Bit mask of SPI_DMA_SEG_MAGIC_VALUE field.
	SPI2_SPI_SLAVE_SPI_DMA_SEG_MAGIC_VALUE_Msk = 0x3c00000
	// Position of MODE field.
	SPI2_SPI_SLAVE_MODE_Pos = 0x1a
	// Bit mask of MODE field.
	SPI2_SPI_SLAVE_MODE_Msk = 0x4000000
	// Bit MODE.
	SPI2_SPI_SLAVE_MODE = 0x4000000
	// Position of SPI_SOFT_RESET field.
	SPI2_SPI_SLAVE_SPI_SOFT_RESET_Pos = 0x1b
	// Bit mask of SPI_SOFT_RESET field.
	SPI2_SPI_SLAVE_SPI_SOFT_RESET_Msk = 0x8000000
	// Bit SPI_SOFT_RESET.
	SPI2_SPI_SLAVE_SPI_SOFT_RESET = 0x8000000
	// Position of SPI_USR_CONF field.
	SPI2_SPI_SLAVE_SPI_USR_CONF_Pos = 0x1c
	// Bit mask of SPI_USR_CONF field.
	SPI2_SPI_SLAVE_SPI_USR_CONF_Msk = 0x10000000
	// Bit SPI_USR_CONF.
	SPI2_SPI_SLAVE_SPI_USR_CONF = 0x10000000
	// Position of SPI_MST_FD_WAIT_DMA_TX_DATA field.
	SPI2_SPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA_Pos = 0x1d
	// Bit mask of SPI_MST_FD_WAIT_DMA_TX_DATA field.
	SPI2_SPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA_Msk = 0x20000000
	// Bit SPI_MST_FD_WAIT_DMA_TX_DATA.
	SPI2_SPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA = 0x20000000

	// SPI_SLAVE1: SPI slave control register 1
	// Position of SPI_SLV_DATA_BITLEN field.
	SPI2_SPI_SLAVE1_SPI_SLV_DATA_BITLEN_Pos = 0x0
	// Bit mask of SPI_SLV_DATA_BITLEN field.
	SPI2_SPI_SLAVE1_SPI_SLV_DATA_BITLEN_Msk = 0x3ffff
	// Position of SPI_SLV_LAST_COMMAND field.
	SPI2_SPI_SLAVE1_SPI_SLV_LAST_COMMAND_Pos = 0x12
	// Bit mask of SPI_SLV_LAST_COMMAND field.
	SPI2_SPI_SLAVE1_SPI_SLV_LAST_COMMAND_Msk = 0x3fc0000
	// Position of SPI_SLV_LAST_ADDR field.
	SPI2_SPI_SLAVE1_SPI_SLV_LAST_ADDR_Pos = 0x1a
	// Bit mask of SPI_SLV_LAST_ADDR field.
	SPI2_SPI_SLAVE1_SPI_SLV_LAST_ADDR_Msk = 0xfc000000

	// SPI_CLK_GATE: SPI module clock and register clock control
	// Position of SPI_CLK_EN field.
	SPI2_SPI_CLK_GATE_SPI_CLK_EN_Pos = 0x0
	// Bit mask of SPI_CLK_EN field.
	SPI2_SPI_CLK_GATE_SPI_CLK_EN_Msk = 0x1
	// Bit SPI_CLK_EN.
	SPI2_SPI_CLK_GATE_SPI_CLK_EN = 0x1
	// Position of SPI_MST_CLK_ACTIVE field.
	SPI2_SPI_CLK_GATE_SPI_MST_CLK_ACTIVE_Pos = 0x1
	// Bit mask of SPI_MST_CLK_ACTIVE field.
	SPI2_SPI_CLK_GATE_SPI_MST_CLK_ACTIVE_Msk = 0x2
	// Bit SPI_MST_CLK_ACTIVE.
	SPI2_SPI_CLK_GATE_SPI_MST_CLK_ACTIVE = 0x2
	// Position of SPI_MST_CLK_SEL field.
	SPI2_SPI_CLK_GATE_SPI_MST_CLK_SEL_Pos = 0x2
	// Bit mask of SPI_MST_CLK_SEL field.
	SPI2_SPI_CLK_GATE_SPI_MST_CLK_SEL_Msk = 0x4
	// Bit SPI_MST_CLK_SEL.
	SPI2_SPI_CLK_GATE_SPI_MST_CLK_SEL = 0x4

	// SPI_DATE: Version control
	// Position of SPI_DATE field.
	SPI2_SPI_DATE_SPI_DATE_Pos = 0x0
	// Bit mask of SPI_DATE field.
	SPI2_SPI_DATE_SPI_DATE_Msk = 0xfffffff
)

// Constants for SPI3: SPI (Serial Peripheral Interface) Controller 3
const (
	// SPI_CMD: Command control register
	// Position of SPI_UPDATE field.
	SPI3_SPI_CMD_SPI_UPDATE_Pos = 0x17
	// Bit mask of SPI_UPDATE field.
	SPI3_SPI_CMD_SPI_UPDATE_Msk = 0x800000
	// Bit SPI_UPDATE.
	SPI3_SPI_CMD_SPI_UPDATE = 0x800000
	// Position of SPI_USR field.
	SPI3_SPI_CMD_SPI_USR_Pos = 0x18
	// Bit mask of SPI_USR field.
	SPI3_SPI_CMD_SPI_USR_Msk = 0x1000000
	// Bit SPI_USR.
	SPI3_SPI_CMD_SPI_USR = 0x1000000

	// SPI_ADDR: Address value register
	// Position of SPI_USR_ADDR_VALUE field.
	SPI3_SPI_ADDR_SPI_USR_ADDR_VALUE_Pos = 0x0
	// Bit mask of SPI_USR_ADDR_VALUE field.
	SPI3_SPI_ADDR_SPI_USR_ADDR_VALUE_Msk = 0xffffffff

	// SPI_CTRL: SPI control register
	// Position of SPI_DUMMY_OUT field.
	SPI3_SPI_CTRL_SPI_DUMMY_OUT_Pos = 0x3
	// Bit mask of SPI_DUMMY_OUT field.
	SPI3_SPI_CTRL_SPI_DUMMY_OUT_Msk = 0x8
	// Bit SPI_DUMMY_OUT.
	SPI3_SPI_CTRL_SPI_DUMMY_OUT = 0x8
	// Position of SPI_FADDR_DUAL field.
	SPI3_SPI_CTRL_SPI_FADDR_DUAL_Pos = 0x5
	// Bit mask of SPI_FADDR_DUAL field.
	SPI3_SPI_CTRL_SPI_FADDR_DUAL_Msk = 0x20
	// Bit SPI_FADDR_DUAL.
	SPI3_SPI_CTRL_SPI_FADDR_DUAL = 0x20
	// Position of SPI_FADDR_QUAD field.
	SPI3_SPI_CTRL_SPI_FADDR_QUAD_Pos = 0x6
	// Bit mask of SPI_FADDR_QUAD field.
	SPI3_SPI_CTRL_SPI_FADDR_QUAD_Msk = 0x40
	// Bit SPI_FADDR_QUAD.
	SPI3_SPI_CTRL_SPI_FADDR_QUAD = 0x40
	// Position of SPI_FCMD_DUAL field.
	SPI3_SPI_CTRL_SPI_FCMD_DUAL_Pos = 0x8
	// Bit mask of SPI_FCMD_DUAL field.
	SPI3_SPI_CTRL_SPI_FCMD_DUAL_Msk = 0x100
	// Bit SPI_FCMD_DUAL.
	SPI3_SPI_CTRL_SPI_FCMD_DUAL = 0x100
	// Position of SPI_FCMD_QUAD field.
	SPI3_SPI_CTRL_SPI_FCMD_QUAD_Pos = 0x9
	// Bit mask of SPI_FCMD_QUAD field.
	SPI3_SPI_CTRL_SPI_FCMD_QUAD_Msk = 0x200
	// Bit SPI_FCMD_QUAD.
	SPI3_SPI_CTRL_SPI_FCMD_QUAD = 0x200
	// Position of SPI_FREAD_DUAL field.
	SPI3_SPI_CTRL_SPI_FREAD_DUAL_Pos = 0xe
	// Bit mask of SPI_FREAD_DUAL field.
	SPI3_SPI_CTRL_SPI_FREAD_DUAL_Msk = 0x4000
	// Bit SPI_FREAD_DUAL.
	SPI3_SPI_CTRL_SPI_FREAD_DUAL = 0x4000
	// Position of SPI_FREAD_QUAD field.
	SPI3_SPI_CTRL_SPI_FREAD_QUAD_Pos = 0xf
	// Bit mask of SPI_FREAD_QUAD field.
	SPI3_SPI_CTRL_SPI_FREAD_QUAD_Msk = 0x8000
	// Bit SPI_FREAD_QUAD.
	SPI3_SPI_CTRL_SPI_FREAD_QUAD = 0x8000
	// Position of SPI_Q_POL field.
	SPI3_SPI_CTRL_SPI_Q_POL_Pos = 0x12
	// Bit mask of SPI_Q_POL field.
	SPI3_SPI_CTRL_SPI_Q_POL_Msk = 0x40000
	// Bit SPI_Q_POL.
	SPI3_SPI_CTRL_SPI_Q_POL = 0x40000
	// Position of SPI_D_POL field.
	SPI3_SPI_CTRL_SPI_D_POL_Pos = 0x13
	// Bit mask of SPI_D_POL field.
	SPI3_SPI_CTRL_SPI_D_POL_Msk = 0x80000
	// Bit SPI_D_POL.
	SPI3_SPI_CTRL_SPI_D_POL = 0x80000
	// Position of SPI_HOLD_POL field.
	SPI3_SPI_CTRL_SPI_HOLD_POL_Pos = 0x14
	// Bit mask of SPI_HOLD_POL field.
	SPI3_SPI_CTRL_SPI_HOLD_POL_Msk = 0x100000
	// Bit SPI_HOLD_POL.
	SPI3_SPI_CTRL_SPI_HOLD_POL = 0x100000
	// Position of SPI_WP_POL field.
	SPI3_SPI_CTRL_SPI_WP_POL_Pos = 0x15
	// Bit mask of SPI_WP_POL field.
	SPI3_SPI_CTRL_SPI_WP_POL_Msk = 0x200000
	// Bit SPI_WP_POL.
	SPI3_SPI_CTRL_SPI_WP_POL = 0x200000
	// Position of SPI_RD_BIT_ORDER field.
	SPI3_SPI_CTRL_SPI_RD_BIT_ORDER_Pos = 0x17
	// Bit mask of SPI_RD_BIT_ORDER field.
	SPI3_SPI_CTRL_SPI_RD_BIT_ORDER_Msk = 0x1800000
	// Position of SPI_WR_BIT_ORDER field.
	SPI3_SPI_CTRL_SPI_WR_BIT_ORDER_Pos = 0x19
	// Bit mask of SPI_WR_BIT_ORDER field.
	SPI3_SPI_CTRL_SPI_WR_BIT_ORDER_Msk = 0x6000000

	// SPI_CLOCK: SPI clock control register
	// Position of SPI_CLKCNT_L field.
	SPI3_SPI_CLOCK_SPI_CLKCNT_L_Pos = 0x0
	// Bit mask of SPI_CLKCNT_L field.
	SPI3_SPI_CLOCK_SPI_CLKCNT_L_Msk = 0x3f
	// Position of SPI_CLKCNT_H field.
	SPI3_SPI_CLOCK_SPI_CLKCNT_H_Pos = 0x6
	// Bit mask of SPI_CLKCNT_H field.
	SPI3_SPI_CLOCK_SPI_CLKCNT_H_Msk = 0xfc0
	// Position of SPI_CLKCNT_N field.
	SPI3_SPI_CLOCK_SPI_CLKCNT_N_Pos = 0xc
	// Bit mask of SPI_CLKCNT_N field.
	SPI3_SPI_CLOCK_SPI_CLKCNT_N_Msk = 0x3f000
	// Position of SPI_CLKDIV_PRE field.
	SPI3_SPI_CLOCK_SPI_CLKDIV_PRE_Pos = 0x12
	// Bit mask of SPI_CLKDIV_PRE field.
	SPI3_SPI_CLOCK_SPI_CLKDIV_PRE_Msk = 0x3c0000
	// Position of SPI_CLK_EQU_SYSCLK field.
	SPI3_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Pos = 0x1f
	// Bit mask of SPI_CLK_EQU_SYSCLK field.
	SPI3_SPI_CLOCK_SPI_CLK_EQU_SYSCLK_Msk = 0x80000000
	// Bit SPI_CLK_EQU_SYSCLK.
	SPI3_SPI_CLOCK_SPI_CLK_EQU_SYSCLK = 0x80000000

	// SPI_USER: SPI USER control register
	// Position of SPI_DOUTDIN field.
	SPI3_SPI_USER_SPI_DOUTDIN_Pos = 0x0
	// Bit mask of SPI_DOUTDIN field.
	SPI3_SPI_USER_SPI_DOUTDIN_Msk = 0x1
	// Bit SPI_DOUTDIN.
	SPI3_SPI_USER_SPI_DOUTDIN = 0x1
	// Position of SPI_QPI_MODE field.
	SPI3_SPI_USER_SPI_QPI_MODE_Pos = 0x3
	// Bit mask of SPI_QPI_MODE field.
	SPI3_SPI_USER_SPI_QPI_MODE_Msk = 0x8
	// Bit SPI_QPI_MODE.
	SPI3_SPI_USER_SPI_QPI_MODE = 0x8
	// Position of SPI_TSCK_I_EDGE field.
	SPI3_SPI_USER_SPI_TSCK_I_EDGE_Pos = 0x5
	// Bit mask of SPI_TSCK_I_EDGE field.
	SPI3_SPI_USER_SPI_TSCK_I_EDGE_Msk = 0x20
	// Bit SPI_TSCK_I_EDGE.
	SPI3_SPI_USER_SPI_TSCK_I_EDGE = 0x20
	// Position of SPI_CS_HOLD field.
	SPI3_SPI_USER_SPI_CS_HOLD_Pos = 0x6
	// Bit mask of SPI_CS_HOLD field.
	SPI3_SPI_USER_SPI_CS_HOLD_Msk = 0x40
	// Bit SPI_CS_HOLD.
	SPI3_SPI_USER_SPI_CS_HOLD = 0x40
	// Position of SPI_CS_SETUP field.
	SPI3_SPI_USER_SPI_CS_SETUP_Pos = 0x7
	// Bit mask of SPI_CS_SETUP field.
	SPI3_SPI_USER_SPI_CS_SETUP_Msk = 0x80
	// Bit SPI_CS_SETUP.
	SPI3_SPI_USER_SPI_CS_SETUP = 0x80
	// Position of SPI_RSCK_I_EDGE field.
	SPI3_SPI_USER_SPI_RSCK_I_EDGE_Pos = 0x8
	// Bit mask of SPI_RSCK_I_EDGE field.
	SPI3_SPI_USER_SPI_RSCK_I_EDGE_Msk = 0x100
	// Bit SPI_RSCK_I_EDGE.
	SPI3_SPI_USER_SPI_RSCK_I_EDGE = 0x100
	// Position of SPI_CK_OUT_EDGE field.
	SPI3_SPI_USER_SPI_CK_OUT_EDGE_Pos = 0x9
	// Bit mask of SPI_CK_OUT_EDGE field.
	SPI3_SPI_USER_SPI_CK_OUT_EDGE_Msk = 0x200
	// Bit SPI_CK_OUT_EDGE.
	SPI3_SPI_USER_SPI_CK_OUT_EDGE = 0x200
	// Position of SPI_FWRITE_DUAL field.
	SPI3_SPI_USER_SPI_FWRITE_DUAL_Pos = 0xc
	// Bit mask of SPI_FWRITE_DUAL field.
	SPI3_SPI_USER_SPI_FWRITE_DUAL_Msk = 0x1000
	// Bit SPI_FWRITE_DUAL.
	SPI3_SPI_USER_SPI_FWRITE_DUAL = 0x1000
	// Position of SPI_FWRITE_QUAD field.
	SPI3_SPI_USER_SPI_FWRITE_QUAD_Pos = 0xd
	// Bit mask of SPI_FWRITE_QUAD field.
	SPI3_SPI_USER_SPI_FWRITE_QUAD_Msk = 0x2000
	// Bit SPI_FWRITE_QUAD.
	SPI3_SPI_USER_SPI_FWRITE_QUAD = 0x2000
	// Position of SPI_SIO field.
	SPI3_SPI_USER_SPI_SIO_Pos = 0x11
	// Bit mask of SPI_SIO field.
	SPI3_SPI_USER_SPI_SIO_Msk = 0x20000
	// Bit SPI_SIO.
	SPI3_SPI_USER_SPI_SIO = 0x20000
	// Position of SPI_USR_MISO_HIGHPART field.
	SPI3_SPI_USER_SPI_USR_MISO_HIGHPART_Pos = 0x18
	// Bit mask of SPI_USR_MISO_HIGHPART field.
	SPI3_SPI_USER_SPI_USR_MISO_HIGHPART_Msk = 0x1000000
	// Bit SPI_USR_MISO_HIGHPART.
	SPI3_SPI_USER_SPI_USR_MISO_HIGHPART = 0x1000000
	// Position of SPI_USR_MOSI_HIGHPART field.
	SPI3_SPI_USER_SPI_USR_MOSI_HIGHPART_Pos = 0x19
	// Bit mask of SPI_USR_MOSI_HIGHPART field.
	SPI3_SPI_USER_SPI_USR_MOSI_HIGHPART_Msk = 0x2000000
	// Bit SPI_USR_MOSI_HIGHPART.
	SPI3_SPI_USER_SPI_USR_MOSI_HIGHPART = 0x2000000
	// Position of SPI_USR_DUMMY_IDLE field.
	SPI3_SPI_USER_SPI_USR_DUMMY_IDLE_Pos = 0x1a
	// Bit mask of SPI_USR_DUMMY_IDLE field.
	SPI3_SPI_USER_SPI_USR_DUMMY_IDLE_Msk = 0x4000000
	// Bit SPI_USR_DUMMY_IDLE.
	SPI3_SPI_USER_SPI_USR_DUMMY_IDLE = 0x4000000
	// Position of SPI_USR_MOSI field.
	SPI3_SPI_USER_SPI_USR_MOSI_Pos = 0x1b
	// Bit mask of SPI_USR_MOSI field.
	SPI3_SPI_USER_SPI_USR_MOSI_Msk = 0x8000000
	// Bit SPI_USR_MOSI.
	SPI3_SPI_USER_SPI_USR_MOSI = 0x8000000
	// Position of SPI_USR_MISO field.
	SPI3_SPI_USER_SPI_USR_MISO_Pos = 0x1c
	// Bit mask of SPI_USR_MISO field.
	SPI3_SPI_USER_SPI_USR_MISO_Msk = 0x10000000
	// Bit SPI_USR_MISO.
	SPI3_SPI_USER_SPI_USR_MISO = 0x10000000
	// Position of SPI_USR_DUMMY field.
	SPI3_SPI_USER_SPI_USR_DUMMY_Pos = 0x1d
	// Bit mask of SPI_USR_DUMMY field.
	SPI3_SPI_USER_SPI_USR_DUMMY_Msk = 0x20000000
	// Bit SPI_USR_DUMMY.
	SPI3_SPI_USER_SPI_USR_DUMMY = 0x20000000
	// Position of SPI_USR_ADDR field.
	SPI3_SPI_USER_SPI_USR_ADDR_Pos = 0x1e
	// Bit mask of SPI_USR_ADDR field.
	SPI3_SPI_USER_SPI_USR_ADDR_Msk = 0x40000000
	// Bit SPI_USR_ADDR.
	SPI3_SPI_USER_SPI_USR_ADDR = 0x40000000
	// Position of SPI_USR_COMMAND field.
	SPI3_SPI_USER_SPI_USR_COMMAND_Pos = 0x1f
	// Bit mask of SPI_USR_COMMAND field.
	SPI3_SPI_USER_SPI_USR_COMMAND_Msk = 0x80000000
	// Bit SPI_USR_COMMAND.
	SPI3_SPI_USER_SPI_USR_COMMAND = 0x80000000

	// SPI_USER1: SPI USER control register 1
	// Position of SPI_USR_DUMMY_CYCLELEN field.
	SPI3_SPI_USER1_SPI_USR_DUMMY_CYCLELEN_Pos = 0x0
	// Bit mask of SPI_USR_DUMMY_CYCLELEN field.
	SPI3_SPI_USER1_SPI_USR_DUMMY_CYCLELEN_Msk = 0xff
	// Position of SPI_MST_WFULL_ERR_END_EN field.
	SPI3_SPI_USER1_SPI_MST_WFULL_ERR_END_EN_Pos = 0x10
	// Bit mask of SPI_MST_WFULL_ERR_END_EN field.
	SPI3_SPI_USER1_SPI_MST_WFULL_ERR_END_EN_Msk = 0x10000
	// Bit SPI_MST_WFULL_ERR_END_EN.
	SPI3_SPI_USER1_SPI_MST_WFULL_ERR_END_EN = 0x10000
	// Position of SPI_CS_SETUP_TIME field.
	SPI3_SPI_USER1_SPI_CS_SETUP_TIME_Pos = 0x11
	// Bit mask of SPI_CS_SETUP_TIME field.
	SPI3_SPI_USER1_SPI_CS_SETUP_TIME_Msk = 0x3e0000
	// Position of SPI_CS_HOLD_TIME field.
	SPI3_SPI_USER1_SPI_CS_HOLD_TIME_Pos = 0x16
	// Bit mask of SPI_CS_HOLD_TIME field.
	SPI3_SPI_USER1_SPI_CS_HOLD_TIME_Msk = 0x7c00000
	// Position of SPI_USR_ADDR_BITLEN field.
	SPI3_SPI_USER1_SPI_USR_ADDR_BITLEN_Pos = 0x1b
	// Bit mask of SPI_USR_ADDR_BITLEN field.
	SPI3_SPI_USER1_SPI_USR_ADDR_BITLEN_Msk = 0xf8000000

	// SPI_USER2: SPI USER control register 2
	// Position of SPI_USR_COMMAND_VALUE field.
	SPI3_SPI_USER2_SPI_USR_COMMAND_VALUE_Pos = 0x0
	// Bit mask of SPI_USR_COMMAND_VALUE field.
	SPI3_SPI_USER2_SPI_USR_COMMAND_VALUE_Msk = 0xffff
	// Position of SPI_MST_REMPTY_ERR_END_EN field.
	SPI3_SPI_USER2_SPI_MST_REMPTY_ERR_END_EN_Pos = 0x1b
	// Bit mask of SPI_MST_REMPTY_ERR_END_EN field.
	SPI3_SPI_USER2_SPI_MST_REMPTY_ERR_END_EN_Msk = 0x8000000
	// Bit SPI_MST_REMPTY_ERR_END_EN.
	SPI3_SPI_USER2_SPI_MST_REMPTY_ERR_END_EN = 0x8000000
	// Position of SPI_USR_COMMAND_BITLEN field.
	SPI3_SPI_USER2_SPI_USR_COMMAND_BITLEN_Pos = 0x1c
	// Bit mask of SPI_USR_COMMAND_BITLEN field.
	SPI3_SPI_USER2_SPI_USR_COMMAND_BITLEN_Msk = 0xf0000000

	// SPI_MS_DLEN: SPI data bit length control register
	// Position of SPI_MS_DATA_BITLEN field.
	SPI3_SPI_MS_DLEN_SPI_MS_DATA_BITLEN_Pos = 0x0
	// Bit mask of SPI_MS_DATA_BITLEN field.
	SPI3_SPI_MS_DLEN_SPI_MS_DATA_BITLEN_Msk = 0x3ffff

	// SPI_MISC: SPI misc register
	// Position of SPI_CS0_DIS field.
	SPI3_SPI_MISC_SPI_CS0_DIS_Pos = 0x0
	// Bit mask of SPI_CS0_DIS field.
	SPI3_SPI_MISC_SPI_CS0_DIS_Msk = 0x1
	// Bit SPI_CS0_DIS.
	SPI3_SPI_MISC_SPI_CS0_DIS = 0x1
	// Position of SPI_CS1_DIS field.
	SPI3_SPI_MISC_SPI_CS1_DIS_Pos = 0x1
	// Bit mask of SPI_CS1_DIS field.
	SPI3_SPI_MISC_SPI_CS1_DIS_Msk = 0x2
	// Bit SPI_CS1_DIS.
	SPI3_SPI_MISC_SPI_CS1_DIS = 0x2
	// Position of SPI_CS2_DIS field.
	SPI3_SPI_MISC_SPI_CS2_DIS_Pos = 0x2
	// Bit mask of SPI_CS2_DIS field.
	SPI3_SPI_MISC_SPI_CS2_DIS_Msk = 0x4
	// Bit SPI_CS2_DIS.
	SPI3_SPI_MISC_SPI_CS2_DIS = 0x4
	// Position of SPI_CK_DIS field.
	SPI3_SPI_MISC_SPI_CK_DIS_Pos = 0x6
	// Bit mask of SPI_CK_DIS field.
	SPI3_SPI_MISC_SPI_CK_DIS_Msk = 0x40
	// Bit SPI_CK_DIS.
	SPI3_SPI_MISC_SPI_CK_DIS = 0x40
	// Position of SPI_MASTER_CS_POL field.
	SPI3_SPI_MISC_SPI_MASTER_CS_POL_Pos = 0x7
	// Bit mask of SPI_MASTER_CS_POL field.
	SPI3_SPI_MISC_SPI_MASTER_CS_POL_Msk = 0x380
	// Position of SPI_SLAVE_CS_POL field.
	SPI3_SPI_MISC_SPI_SLAVE_CS_POL_Pos = 0x17
	// Bit mask of SPI_SLAVE_CS_POL field.
	SPI3_SPI_MISC_SPI_SLAVE_CS_POL_Msk = 0x800000
	// Bit SPI_SLAVE_CS_POL.
	SPI3_SPI_MISC_SPI_SLAVE_CS_POL = 0x800000
	// Position of SPI_CK_IDLE_EDGE field.
	SPI3_SPI_MISC_SPI_CK_IDLE_EDGE_Pos = 0x1d
	// Bit mask of SPI_CK_IDLE_EDGE field.
	SPI3_SPI_MISC_SPI_CK_IDLE_EDGE_Msk = 0x20000000
	// Bit SPI_CK_IDLE_EDGE.
	SPI3_SPI_MISC_SPI_CK_IDLE_EDGE = 0x20000000
	// Position of SPI_CS_KEEP_ACTIVE field.
	SPI3_SPI_MISC_SPI_CS_KEEP_ACTIVE_Pos = 0x1e
	// Bit mask of SPI_CS_KEEP_ACTIVE field.
	SPI3_SPI_MISC_SPI_CS_KEEP_ACTIVE_Msk = 0x40000000
	// Bit SPI_CS_KEEP_ACTIVE.
	SPI3_SPI_MISC_SPI_CS_KEEP_ACTIVE = 0x40000000
	// Position of SPI_QUAD_DIN_PIN_SWAP field.
	SPI3_SPI_MISC_SPI_QUAD_DIN_PIN_SWAP_Pos = 0x1f
	// Bit mask of SPI_QUAD_DIN_PIN_SWAP field.
	SPI3_SPI_MISC_SPI_QUAD_DIN_PIN_SWAP_Msk = 0x80000000
	// Bit SPI_QUAD_DIN_PIN_SWAP.
	SPI3_SPI_MISC_SPI_QUAD_DIN_PIN_SWAP = 0x80000000

	// SPI_DIN_MODE: SPI input delay mode configuration
	// Position of SPI_DIN0_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN0_MODE_Pos = 0x0
	// Bit mask of SPI_DIN0_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN0_MODE_Msk = 0x3
	// Position of SPI_DIN1_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN1_MODE_Pos = 0x2
	// Bit mask of SPI_DIN1_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN1_MODE_Msk = 0xc
	// Position of SPI_DIN2_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN2_MODE_Pos = 0x4
	// Bit mask of SPI_DIN2_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN2_MODE_Msk = 0x30
	// Position of SPI_DIN3_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN3_MODE_Pos = 0x6
	// Bit mask of SPI_DIN3_MODE field.
	SPI3_SPI_DIN_MODE_SPI_DIN3_MODE_Msk = 0xc0
	// Position of SPI_TIMING_HCLK_ACTIVE field.
	SPI3_SPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE_Pos = 0x10
	// Bit mask of SPI_TIMING_HCLK_ACTIVE field.
	SPI3_SPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE_Msk = 0x10000
	// Bit SPI_TIMING_HCLK_ACTIVE.
	SPI3_SPI_DIN_MODE_SPI_TIMING_HCLK_ACTIVE = 0x10000

	// SPI_DIN_NUM: SPI input delay number configuration
	// Position of SPI_DIN0_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN0_NUM_Pos = 0x0
	// Bit mask of SPI_DIN0_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN0_NUM_Msk = 0x3
	// Position of SPI_DIN1_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN1_NUM_Pos = 0x2
	// Bit mask of SPI_DIN1_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN1_NUM_Msk = 0xc
	// Position of SPI_DIN2_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN2_NUM_Pos = 0x4
	// Bit mask of SPI_DIN2_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN2_NUM_Msk = 0x30
	// Position of SPI_DIN3_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN3_NUM_Pos = 0x6
	// Bit mask of SPI_DIN3_NUM field.
	SPI3_SPI_DIN_NUM_SPI_DIN3_NUM_Msk = 0xc0

	// SPI_DOUT_MODE: SPI output delay mode configuration
	// Position of SPI_DOUT0_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT0_MODE_Pos = 0x0
	// Bit mask of SPI_DOUT0_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT0_MODE_Msk = 0x1
	// Bit SPI_DOUT0_MODE.
	SPI3_SPI_DOUT_MODE_SPI_DOUT0_MODE = 0x1
	// Position of SPI_DOUT1_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT1_MODE_Pos = 0x1
	// Bit mask of SPI_DOUT1_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT1_MODE_Msk = 0x2
	// Bit SPI_DOUT1_MODE.
	SPI3_SPI_DOUT_MODE_SPI_DOUT1_MODE = 0x2
	// Position of SPI_DOUT2_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT2_MODE_Pos = 0x2
	// Bit mask of SPI_DOUT2_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT2_MODE_Msk = 0x4
	// Bit SPI_DOUT2_MODE.
	SPI3_SPI_DOUT_MODE_SPI_DOUT2_MODE = 0x4
	// Position of SPI_DOUT3_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT3_MODE_Pos = 0x3
	// Bit mask of SPI_DOUT3_MODE field.
	SPI3_SPI_DOUT_MODE_SPI_DOUT3_MODE_Msk = 0x8
	// Bit SPI_DOUT3_MODE.
	SPI3_SPI_DOUT_MODE_SPI_DOUT3_MODE = 0x8

	// SPI_DMA_CONF: SPI DMA control register
	// Position of SPI_DMA_OUTFIFO_EMPTY field.
	SPI3_SPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY_Pos = 0x0
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY field.
	SPI3_SPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY_Msk = 0x1
	// Bit SPI_DMA_OUTFIFO_EMPTY.
	SPI3_SPI_DMA_CONF_SPI_DMA_OUTFIFO_EMPTY = 0x1
	// Position of SPI_DMA_INFIFO_FULL field.
	SPI3_SPI_DMA_CONF_SPI_DMA_INFIFO_FULL_Pos = 0x1
	// Bit mask of SPI_DMA_INFIFO_FULL field.
	SPI3_SPI_DMA_CONF_SPI_DMA_INFIFO_FULL_Msk = 0x2
	// Bit SPI_DMA_INFIFO_FULL.
	SPI3_SPI_DMA_CONF_SPI_DMA_INFIFO_FULL = 0x2
	// Position of SPI_DMA_SLV_SEG_TRANS_EN field.
	SPI3_SPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN_Pos = 0x12
	// Bit mask of SPI_DMA_SLV_SEG_TRANS_EN field.
	SPI3_SPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN_Msk = 0x40000
	// Bit SPI_DMA_SLV_SEG_TRANS_EN.
	SPI3_SPI_DMA_CONF_SPI_DMA_SLV_SEG_TRANS_EN = 0x40000
	// Position of SPI_SLV_RX_SEG_TRANS_CLR_EN field.
	SPI3_SPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN_Pos = 0x13
	// Bit mask of SPI_SLV_RX_SEG_TRANS_CLR_EN field.
	SPI3_SPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN_Msk = 0x80000
	// Bit SPI_SLV_RX_SEG_TRANS_CLR_EN.
	SPI3_SPI_DMA_CONF_SPI_SLV_RX_SEG_TRANS_CLR_EN = 0x80000
	// Position of SPI_SLV_TX_SEG_TRANS_CLR_EN field.
	SPI3_SPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN_Pos = 0x14
	// Bit mask of SPI_SLV_TX_SEG_TRANS_CLR_EN field.
	SPI3_SPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN_Msk = 0x100000
	// Bit SPI_SLV_TX_SEG_TRANS_CLR_EN.
	SPI3_SPI_DMA_CONF_SPI_SLV_TX_SEG_TRANS_CLR_EN = 0x100000
	// Position of SPI_RX_EOF_EN field.
	SPI3_SPI_DMA_CONF_SPI_RX_EOF_EN_Pos = 0x15
	// Bit mask of SPI_RX_EOF_EN field.
	SPI3_SPI_DMA_CONF_SPI_RX_EOF_EN_Msk = 0x200000
	// Bit SPI_RX_EOF_EN.
	SPI3_SPI_DMA_CONF_SPI_RX_EOF_EN = 0x200000
	// Position of SPI_DMA_RX_ENA field.
	SPI3_SPI_DMA_CONF_SPI_DMA_RX_ENA_Pos = 0x1b
	// Bit mask of SPI_DMA_RX_ENA field.
	SPI3_SPI_DMA_CONF_SPI_DMA_RX_ENA_Msk = 0x8000000
	// Bit SPI_DMA_RX_ENA.
	SPI3_SPI_DMA_CONF_SPI_DMA_RX_ENA = 0x8000000
	// Position of SPI_DMA_TX_ENA field.
	SPI3_SPI_DMA_CONF_SPI_DMA_TX_ENA_Pos = 0x1c
	// Bit mask of SPI_DMA_TX_ENA field.
	SPI3_SPI_DMA_CONF_SPI_DMA_TX_ENA_Msk = 0x10000000
	// Bit SPI_DMA_TX_ENA.
	SPI3_SPI_DMA_CONF_SPI_DMA_TX_ENA = 0x10000000
	// Position of SPI_RX_AFIFO_RST field.
	SPI3_SPI_DMA_CONF_SPI_RX_AFIFO_RST_Pos = 0x1d
	// Bit mask of SPI_RX_AFIFO_RST field.
	SPI3_SPI_DMA_CONF_SPI_RX_AFIFO_RST_Msk = 0x20000000
	// Bit SPI_RX_AFIFO_RST.
	SPI3_SPI_DMA_CONF_SPI_RX_AFIFO_RST = 0x20000000
	// Position of SPI_BUF_AFIFO_RST field.
	SPI3_SPI_DMA_CONF_SPI_BUF_AFIFO_RST_Pos = 0x1e
	// Bit mask of SPI_BUF_AFIFO_RST field.
	SPI3_SPI_DMA_CONF_SPI_BUF_AFIFO_RST_Msk = 0x40000000
	// Bit SPI_BUF_AFIFO_RST.
	SPI3_SPI_DMA_CONF_SPI_BUF_AFIFO_RST = 0x40000000
	// Position of SPI_DMA_AFIFO_RST field.
	SPI3_SPI_DMA_CONF_SPI_DMA_AFIFO_RST_Pos = 0x1f
	// Bit mask of SPI_DMA_AFIFO_RST field.
	SPI3_SPI_DMA_CONF_SPI_DMA_AFIFO_RST_Msk = 0x80000000
	// Bit SPI_DMA_AFIFO_RST.
	SPI3_SPI_DMA_CONF_SPI_DMA_AFIFO_RST = 0x80000000

	// SPI_DMA_INT_ENA: SPI interrupt enable register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_INFIFO_FULL_ERR_INT_ENA = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA = 0x2
	// Position of SPI_SLV_EX_QPI_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_EX_QPI_INT_ENA = 0x4
	// Position of SPI_SLV_EN_QPI_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_EN_QPI_INT_ENA = 0x8
	// Position of SPI_SLV_CMD7_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD7_INT_ENA = 0x10
	// Position of SPI_SLV_CMD8_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD8_INT_ENA = 0x20
	// Position of SPI_SLV_CMD9_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD9_INT_ENA = 0x40
	// Position of SPI_SLV_CMDA_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMDA_INT_ENA = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_RD_DMA_DONE_INT_ENA = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_WR_DMA_DONE_INT_ENA = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_RD_BUF_DONE_INT_ENA = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_WR_BUF_DONE_INT_ENA = 0x800
	// Position of SPI_TRANS_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_TRANS_DONE_INT_ENA = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_DMA_SEG_TRANS_DONE_INT_ENA = 0x2000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_BUF_ADDR_ERR_INT_ENA = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_SLV_CMD_ERR_INT_ENA = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA = 0x40000
	// Position of SPI_APP2_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_APP2_INT_ENA_Pos = 0x13
	// Bit mask of SPI_APP2_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_APP2_INT_ENA_Msk = 0x80000
	// Bit SPI_APP2_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_APP2_INT_ENA = 0x80000
	// Position of SPI_APP1_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_APP1_INT_ENA_Pos = 0x14
	// Bit mask of SPI_APP1_INT_ENA field.
	SPI3_SPI_DMA_INT_ENA_SPI_APP1_INT_ENA_Msk = 0x100000
	// Bit SPI_APP1_INT_ENA.
	SPI3_SPI_DMA_INT_ENA_SPI_APP1_INT_ENA = 0x100000

	// SPI_DMA_INT_CLR: SPI interrupt clear register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_INFIFO_FULL_ERR_INT_CLR = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR = 0x2
	// Position of SPI_SLV_EX_QPI_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_EX_QPI_INT_CLR = 0x4
	// Position of SPI_SLV_EN_QPI_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_EN_QPI_INT_CLR = 0x8
	// Position of SPI_SLV_CMD7_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD7_INT_CLR = 0x10
	// Position of SPI_SLV_CMD8_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD8_INT_CLR = 0x20
	// Position of SPI_SLV_CMD9_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD9_INT_CLR = 0x40
	// Position of SPI_SLV_CMDA_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMDA_INT_CLR = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_RD_DMA_DONE_INT_CLR = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_WR_DMA_DONE_INT_CLR = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_RD_BUF_DONE_INT_CLR = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_WR_BUF_DONE_INT_CLR = 0x800
	// Position of SPI_TRANS_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_TRANS_DONE_INT_CLR = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_DMA_SEG_TRANS_DONE_INT_CLR = 0x2000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_BUF_ADDR_ERR_INT_CLR = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_SLV_CMD_ERR_INT_CLR = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR = 0x40000
	// Position of SPI_APP2_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_APP2_INT_CLR_Pos = 0x13
	// Bit mask of SPI_APP2_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_APP2_INT_CLR_Msk = 0x80000
	// Bit SPI_APP2_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_APP2_INT_CLR = 0x80000
	// Position of SPI_APP1_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_APP1_INT_CLR_Pos = 0x14
	// Bit mask of SPI_APP1_INT_CLR field.
	SPI3_SPI_DMA_INT_CLR_SPI_APP1_INT_CLR_Msk = 0x100000
	// Bit SPI_APP1_INT_CLR.
	SPI3_SPI_DMA_INT_CLR_SPI_APP1_INT_CLR = 0x100000

	// SPI_DMA_INT_RAW: SPI interrupt raw register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_INFIFO_FULL_ERR_INT_RAW = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW = 0x2
	// Position of SPI_SLV_EX_QPI_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_EX_QPI_INT_RAW = 0x4
	// Position of SPI_SLV_EN_QPI_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_EN_QPI_INT_RAW = 0x8
	// Position of SPI_SLV_CMD7_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD7_INT_RAW = 0x10
	// Position of SPI_SLV_CMD8_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD8_INT_RAW = 0x20
	// Position of SPI_SLV_CMD9_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD9_INT_RAW = 0x40
	// Position of SPI_SLV_CMDA_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMDA_INT_RAW = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_RD_DMA_DONE_INT_RAW = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_WR_DMA_DONE_INT_RAW = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_RD_BUF_DONE_INT_RAW = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_WR_BUF_DONE_INT_RAW = 0x800
	// Position of SPI_TRANS_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_TRANS_DONE_INT_RAW = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_DMA_SEG_TRANS_DONE_INT_RAW = 0x2000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_BUF_ADDR_ERR_INT_RAW = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_SLV_CMD_ERR_INT_RAW = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW = 0x40000
	// Position of SPI_APP2_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_APP2_INT_RAW_Pos = 0x13
	// Bit mask of SPI_APP2_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_APP2_INT_RAW_Msk = 0x80000
	// Bit SPI_APP2_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_APP2_INT_RAW = 0x80000
	// Position of SPI_APP1_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_APP1_INT_RAW_Pos = 0x14
	// Bit mask of SPI_APP1_INT_RAW field.
	SPI3_SPI_DMA_INT_RAW_SPI_APP1_INT_RAW_Msk = 0x100000
	// Bit SPI_APP1_INT_RAW.
	SPI3_SPI_DMA_INT_RAW_SPI_APP1_INT_RAW = 0x100000

	// SPI_DMA_INT_ST: SPI interrupt status register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_INFIFO_FULL_ERR_INT_ST = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST = 0x2
	// Position of SPI_SLV_EX_QPI_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_EX_QPI_INT_ST = 0x4
	// Position of SPI_SLV_EN_QPI_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_EN_QPI_INT_ST = 0x8
	// Position of SPI_SLV_CMD7_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD7_INT_ST = 0x10
	// Position of SPI_SLV_CMD8_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD8_INT_ST = 0x20
	// Position of SPI_SLV_CMD9_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD9_INT_ST = 0x40
	// Position of SPI_SLV_CMDA_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMDA_INT_ST = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_RD_DMA_DONE_INT_ST = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_WR_DMA_DONE_INT_ST = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_RD_BUF_DONE_INT_ST = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_WR_BUF_DONE_INT_ST = 0x800
	// Position of SPI_TRANS_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_TRANS_DONE_INT_ST = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_DMA_SEG_TRANS_DONE_INT_ST = 0x2000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_BUF_ADDR_ERR_INT_ST = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_SLV_CMD_ERR_INT_ST = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST = 0x40000
	// Position of SPI_APP2_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_APP2_INT_ST_Pos = 0x13
	// Bit mask of SPI_APP2_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_APP2_INT_ST_Msk = 0x80000
	// Bit SPI_APP2_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_APP2_INT_ST = 0x80000
	// Position of SPI_APP1_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_APP1_INT_ST_Pos = 0x14
	// Bit mask of SPI_APP1_INT_ST field.
	SPI3_SPI_DMA_INT_ST_SPI_APP1_INT_ST_Msk = 0x100000
	// Bit SPI_APP1_INT_ST.
	SPI3_SPI_DMA_INT_ST_SPI_APP1_INT_ST = 0x100000

	// SPI_DMA_INT_SET: SPI interrupt software set register
	// Position of SPI_DMA_INFIFO_FULL_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET_Pos = 0x0
	// Bit mask of SPI_DMA_INFIFO_FULL_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET_Msk = 0x1
	// Bit SPI_DMA_INFIFO_FULL_ERR_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_INFIFO_FULL_ERR_INT_SET = 0x1
	// Position of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Pos = 0x1
	// Bit mask of SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_Msk = 0x2
	// Bit SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET = 0x2
	// Position of SPI_SLV_EX_QPI_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET_Pos = 0x2
	// Bit mask of SPI_SLV_EX_QPI_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET_Msk = 0x4
	// Bit SPI_SLV_EX_QPI_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_EX_QPI_INT_SET = 0x4
	// Position of SPI_SLV_EN_QPI_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET_Pos = 0x3
	// Bit mask of SPI_SLV_EN_QPI_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET_Msk = 0x8
	// Bit SPI_SLV_EN_QPI_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_EN_QPI_INT_SET = 0x8
	// Position of SPI_SLV_CMD7_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET_Pos = 0x4
	// Bit mask of SPI_SLV_CMD7_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET_Msk = 0x10
	// Bit SPI_SLV_CMD7_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD7_INT_SET = 0x10
	// Position of SPI_SLV_CMD8_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET_Pos = 0x5
	// Bit mask of SPI_SLV_CMD8_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET_Msk = 0x20
	// Bit SPI_SLV_CMD8_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD8_INT_SET = 0x20
	// Position of SPI_SLV_CMD9_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET_Pos = 0x6
	// Bit mask of SPI_SLV_CMD9_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET_Msk = 0x40
	// Bit SPI_SLV_CMD9_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD9_INT_SET = 0x40
	// Position of SPI_SLV_CMDA_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET_Pos = 0x7
	// Bit mask of SPI_SLV_CMDA_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET_Msk = 0x80
	// Bit SPI_SLV_CMDA_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMDA_INT_SET = 0x80
	// Position of SPI_SLV_RD_DMA_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET_Pos = 0x8
	// Bit mask of SPI_SLV_RD_DMA_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET_Msk = 0x100
	// Bit SPI_SLV_RD_DMA_DONE_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_RD_DMA_DONE_INT_SET = 0x100
	// Position of SPI_SLV_WR_DMA_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET_Pos = 0x9
	// Bit mask of SPI_SLV_WR_DMA_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET_Msk = 0x200
	// Bit SPI_SLV_WR_DMA_DONE_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_WR_DMA_DONE_INT_SET = 0x200
	// Position of SPI_SLV_RD_BUF_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET_Pos = 0xa
	// Bit mask of SPI_SLV_RD_BUF_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET_Msk = 0x400
	// Bit SPI_SLV_RD_BUF_DONE_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_RD_BUF_DONE_INT_SET = 0x400
	// Position of SPI_SLV_WR_BUF_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET_Pos = 0xb
	// Bit mask of SPI_SLV_WR_BUF_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET_Msk = 0x800
	// Bit SPI_SLV_WR_BUF_DONE_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_WR_BUF_DONE_INT_SET = 0x800
	// Position of SPI_TRANS_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET_Pos = 0xc
	// Bit mask of SPI_TRANS_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET_Msk = 0x1000
	// Bit SPI_TRANS_DONE_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_TRANS_DONE_INT_SET = 0x1000
	// Position of SPI_DMA_SEG_TRANS_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET_Pos = 0xd
	// Bit mask of SPI_DMA_SEG_TRANS_DONE_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET_Msk = 0x2000
	// Bit SPI_DMA_SEG_TRANS_DONE_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_DMA_SEG_TRANS_DONE_INT_SET = 0x2000
	// Position of SPI_SLV_BUF_ADDR_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET_Pos = 0xf
	// Bit mask of SPI_SLV_BUF_ADDR_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET_Msk = 0x8000
	// Bit SPI_SLV_BUF_ADDR_ERR_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_BUF_ADDR_ERR_INT_SET = 0x8000
	// Position of SPI_SLV_CMD_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET_Pos = 0x10
	// Bit mask of SPI_SLV_CMD_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET_Msk = 0x10000
	// Bit SPI_SLV_CMD_ERR_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_SLV_CMD_ERR_INT_SET = 0x10000
	// Position of SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_Pos = 0x11
	// Bit mask of SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_Msk = 0x20000
	// Bit SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET = 0x20000
	// Position of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Pos = 0x12
	// Bit mask of SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_Msk = 0x40000
	// Bit SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET = 0x40000
	// Position of SPI_APP2_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_APP2_INT_SET_Pos = 0x13
	// Bit mask of SPI_APP2_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_APP2_INT_SET_Msk = 0x80000
	// Bit SPI_APP2_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_APP2_INT_SET = 0x80000
	// Position of SPI_APP1_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_APP1_INT_SET_Pos = 0x14
	// Bit mask of SPI_APP1_INT_SET field.
	SPI3_SPI_DMA_INT_SET_SPI_APP1_INT_SET_Msk = 0x100000
	// Bit SPI_APP1_INT_SET.
	SPI3_SPI_DMA_INT_SET_SPI_APP1_INT_SET = 0x100000

	// SPI_W0: SPI CPU-controlled buffer0
	// Position of SPI_BUF0 field.
	SPI3_SPI_W0_SPI_BUF0_Pos = 0x0
	// Bit mask of SPI_BUF0 field.
	SPI3_SPI_W0_SPI_BUF0_Msk = 0xffffffff

	// SPI_W1: SPI CPU-controlled buffer1
	// Position of SPI_BUF1 field.
	SPI3_SPI_W1_SPI_BUF1_Pos = 0x0
	// Bit mask of SPI_BUF1 field.
	SPI3_SPI_W1_SPI_BUF1_Msk = 0xffffffff

	// SPI_W2: SPI CPU-controlled buffer2
	// Position of SPI_BUF2 field.
	SPI3_SPI_W2_SPI_BUF2_Pos = 0x0
	// Bit mask of SPI_BUF2 field.
	SPI3_SPI_W2_SPI_BUF2_Msk = 0xffffffff

	// SPI_W3: SPI CPU-controlled buffer3
	// Position of SPI_BUF3 field.
	SPI3_SPI_W3_SPI_BUF3_Pos = 0x0
	// Bit mask of SPI_BUF3 field.
	SPI3_SPI_W3_SPI_BUF3_Msk = 0xffffffff

	// SPI_W4: SPI CPU-controlled buffer4
	// Position of SPI_BUF4 field.
	SPI3_SPI_W4_SPI_BUF4_Pos = 0x0
	// Bit mask of SPI_BUF4 field.
	SPI3_SPI_W4_SPI_BUF4_Msk = 0xffffffff

	// SPI_W5: SPI CPU-controlled buffer5
	// Position of SPI_BUF5 field.
	SPI3_SPI_W5_SPI_BUF5_Pos = 0x0
	// Bit mask of SPI_BUF5 field.
	SPI3_SPI_W5_SPI_BUF5_Msk = 0xffffffff

	// SPI_W6: SPI CPU-controlled buffer6
	// Position of SPI_BUF6 field.
	SPI3_SPI_W6_SPI_BUF6_Pos = 0x0
	// Bit mask of SPI_BUF6 field.
	SPI3_SPI_W6_SPI_BUF6_Msk = 0xffffffff

	// SPI_W7: SPI CPU-controlled buffer7
	// Position of SPI_BUF7 field.
	SPI3_SPI_W7_SPI_BUF7_Pos = 0x0
	// Bit mask of SPI_BUF7 field.
	SPI3_SPI_W7_SPI_BUF7_Msk = 0xffffffff

	// SPI_W8: SPI CPU-controlled buffer8
	// Position of SPI_BUF8 field.
	SPI3_SPI_W8_SPI_BUF8_Pos = 0x0
	// Bit mask of SPI_BUF8 field.
	SPI3_SPI_W8_SPI_BUF8_Msk = 0xffffffff

	// SPI_W9: SPI CPU-controlled buffer9
	// Position of SPI_BUF9 field.
	SPI3_SPI_W9_SPI_BUF9_Pos = 0x0
	// Bit mask of SPI_BUF9 field.
	SPI3_SPI_W9_SPI_BUF9_Msk = 0xffffffff

	// SPI_W10: SPI CPU-controlled buffer10
	// Position of SPI_BUF10 field.
	SPI3_SPI_W10_SPI_BUF10_Pos = 0x0
	// Bit mask of SPI_BUF10 field.
	SPI3_SPI_W10_SPI_BUF10_Msk = 0xffffffff

	// SPI_W11: SPI CPU-controlled buffer11
	// Position of SPI_BUF11 field.
	SPI3_SPI_W11_SPI_BUF11_Pos = 0x0
	// Bit mask of SPI_BUF11 field.
	SPI3_SPI_W11_SPI_BUF11_Msk = 0xffffffff

	// SPI_W12: SPI CPU-controlled buffer12
	// Position of SPI_BUF12 field.
	SPI3_SPI_W12_SPI_BUF12_Pos = 0x0
	// Bit mask of SPI_BUF12 field.
	SPI3_SPI_W12_SPI_BUF12_Msk = 0xffffffff

	// SPI_W13: SPI CPU-controlled buffer13
	// Position of SPI_BUF13 field.
	SPI3_SPI_W13_SPI_BUF13_Pos = 0x0
	// Bit mask of SPI_BUF13 field.
	SPI3_SPI_W13_SPI_BUF13_Msk = 0xffffffff

	// SPI_W14: SPI CPU-controlled buffer14
	// Position of SPI_BUF14 field.
	SPI3_SPI_W14_SPI_BUF14_Pos = 0x0
	// Bit mask of SPI_BUF14 field.
	SPI3_SPI_W14_SPI_BUF14_Msk = 0xffffffff

	// SPI_W15: SPI CPU-controlled buffer15
	// Position of SPI_BUF15 field.
	SPI3_SPI_W15_SPI_BUF15_Pos = 0x0
	// Bit mask of SPI_BUF15 field.
	SPI3_SPI_W15_SPI_BUF15_Msk = 0xffffffff

	// SPI_SLAVE: SPI slave control register
	// Position of SPI_CLK_MODE field.
	SPI3_SPI_SLAVE_SPI_CLK_MODE_Pos = 0x0
	// Bit mask of SPI_CLK_MODE field.
	SPI3_SPI_SLAVE_SPI_CLK_MODE_Msk = 0x3
	// Position of SPI_CLK_MODE_13 field.
	SPI3_SPI_SLAVE_SPI_CLK_MODE_13_Pos = 0x2
	// Bit mask of SPI_CLK_MODE_13 field.
	SPI3_SPI_SLAVE_SPI_CLK_MODE_13_Msk = 0x4
	// Bit SPI_CLK_MODE_13.
	SPI3_SPI_SLAVE_SPI_CLK_MODE_13 = 0x4
	// Position of SPI_RSCK_DATA_OUT field.
	SPI3_SPI_SLAVE_SPI_RSCK_DATA_OUT_Pos = 0x3
	// Bit mask of SPI_RSCK_DATA_OUT field.
	SPI3_SPI_SLAVE_SPI_RSCK_DATA_OUT_Msk = 0x8
	// Bit SPI_RSCK_DATA_OUT.
	SPI3_SPI_SLAVE_SPI_RSCK_DATA_OUT = 0x8
	// Position of SPI_SLV_RDDMA_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN_Pos = 0x8
	// Bit mask of SPI_SLV_RDDMA_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN_Msk = 0x100
	// Bit SPI_SLV_RDDMA_BITLEN_EN.
	SPI3_SPI_SLAVE_SPI_SLV_RDDMA_BITLEN_EN = 0x100
	// Position of SPI_SLV_WRDMA_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN_Pos = 0x9
	// Bit mask of SPI_SLV_WRDMA_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN_Msk = 0x200
	// Bit SPI_SLV_WRDMA_BITLEN_EN.
	SPI3_SPI_SLAVE_SPI_SLV_WRDMA_BITLEN_EN = 0x200
	// Position of SPI_SLV_RDBUF_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN_Pos = 0xa
	// Bit mask of SPI_SLV_RDBUF_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN_Msk = 0x400
	// Bit SPI_SLV_RDBUF_BITLEN_EN.
	SPI3_SPI_SLAVE_SPI_SLV_RDBUF_BITLEN_EN = 0x400
	// Position of SPI_SLV_WRBUF_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN_Pos = 0xb
	// Bit mask of SPI_SLV_WRBUF_BITLEN_EN field.
	SPI3_SPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN_Msk = 0x800
	// Bit SPI_SLV_WRBUF_BITLEN_EN.
	SPI3_SPI_SLAVE_SPI_SLV_WRBUF_BITLEN_EN = 0x800
	// Position of SPI_SLV_LAST_BYTE_STRB field.
	SPI3_SPI_SLAVE_SPI_SLV_LAST_BYTE_STRB_Pos = 0xc
	// Bit mask of SPI_SLV_LAST_BYTE_STRB field.
	SPI3_SPI_SLAVE_SPI_SLV_LAST_BYTE_STRB_Msk = 0xff000
	// Position of MODE field.
	SPI3_SPI_SLAVE_MODE_Pos = 0x1a
	// Bit mask of MODE field.
	SPI3_SPI_SLAVE_MODE_Msk = 0x4000000
	// Bit MODE.
	SPI3_SPI_SLAVE_MODE = 0x4000000
	// Position of SPI_SOFT_RESET field.
	SPI3_SPI_SLAVE_SPI_SOFT_RESET_Pos = 0x1b
	// Bit mask of SPI_SOFT_RESET field.
	SPI3_SPI_SLAVE_SPI_SOFT_RESET_Msk = 0x8000000
	// Bit SPI_SOFT_RESET.
	SPI3_SPI_SLAVE_SPI_SOFT_RESET = 0x8000000
	// Position of SPI_MST_FD_WAIT_DMA_TX_DATA field.
	SPI3_SPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA_Pos = 0x1d
	// Bit mask of SPI_MST_FD_WAIT_DMA_TX_DATA field.
	SPI3_SPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA_Msk = 0x20000000
	// Bit SPI_MST_FD_WAIT_DMA_TX_DATA.
	SPI3_SPI_SLAVE_SPI_MST_FD_WAIT_DMA_TX_DATA = 0x20000000

	// SPI_SLAVE1: SPI slave control register 1
	// Position of SPI_SLV_DATA_BITLEN field.
	SPI3_SPI_SLAVE1_SPI_SLV_DATA_BITLEN_Pos = 0x0
	// Bit mask of SPI_SLV_DATA_BITLEN field.
	SPI3_SPI_SLAVE1_SPI_SLV_DATA_BITLEN_Msk = 0x3ffff
	// Position of SPI_SLV_LAST_COMMAND field.
	SPI3_SPI_SLAVE1_SPI_SLV_LAST_COMMAND_Pos = 0x12
	// Bit mask of SPI_SLV_LAST_COMMAND field.
	SPI3_SPI_SLAVE1_SPI_SLV_LAST_COMMAND_Msk = 0x3fc0000
	// Position of SPI_SLV_LAST_ADDR field.
	SPI3_SPI_SLAVE1_SPI_SLV_LAST_ADDR_Pos = 0x1a
	// Bit mask of SPI_SLV_LAST_ADDR field.
	SPI3_SPI_SLAVE1_SPI_SLV_LAST_ADDR_Msk = 0xfc000000

	// SPI_CLK_GATE: SPI module clock and register clock control
	// Position of SPI_CLK_EN field.
	SPI3_SPI_CLK_GATE_SPI_CLK_EN_Pos = 0x0
	// Bit mask of SPI_CLK_EN field.
	SPI3_SPI_CLK_GATE_SPI_CLK_EN_Msk = 0x1
	// Bit SPI_CLK_EN.
	SPI3_SPI_CLK_GATE_SPI_CLK_EN = 0x1
	// Position of SPI_MST_CLK_ACTIVE field.
	SPI3_SPI_CLK_GATE_SPI_MST_CLK_ACTIVE_Pos = 0x1
	// Bit mask of SPI_MST_CLK_ACTIVE field.
	SPI3_SPI_CLK_GATE_SPI_MST_CLK_ACTIVE_Msk = 0x2
	// Bit SPI_MST_CLK_ACTIVE.
	SPI3_SPI_CLK_GATE_SPI_MST_CLK_ACTIVE = 0x2
	// Position of SPI_MST_CLK_SEL field.
	SPI3_SPI_CLK_GATE_SPI_MST_CLK_SEL_Pos = 0x2
	// Bit mask of SPI_MST_CLK_SEL field.
	SPI3_SPI_CLK_GATE_SPI_MST_CLK_SEL_Msk = 0x4
	// Bit SPI_MST_CLK_SEL.
	SPI3_SPI_CLK_GATE_SPI_MST_CLK_SEL = 0x4

	// SPI_DATE: Version control
	// Position of SPI_DATE field.
	SPI3_SPI_DATE_SPI_DATE_Pos = 0x0
	// Bit mask of SPI_DATE field.
	SPI3_SPI_DATE_SPI_DATE_Msk = 0xfffffff
)

// Constants for SYSTIMER: System Timer
const (
	// CONF: Configure system timer clock
	// Position of SYSTIMER_CLK_FO field.
	SYSTIMER_CONF_SYSTIMER_CLK_FO_Pos = 0x0
	// Bit mask of SYSTIMER_CLK_FO field.
	SYSTIMER_CONF_SYSTIMER_CLK_FO_Msk = 0x1
	// Bit SYSTIMER_CLK_FO.
	SYSTIMER_CONF_SYSTIMER_CLK_FO = 0x1
	// Position of ETM_EN field.
	SYSTIMER_CONF_ETM_EN_Pos = 0x1
	// Bit mask of ETM_EN field.
	SYSTIMER_CONF_ETM_EN_Msk = 0x2
	// Bit ETM_EN.
	SYSTIMER_CONF_ETM_EN = 0x2
	// Position of TARGET2_WORK_EN field.
	SYSTIMER_CONF_TARGET2_WORK_EN_Pos = 0x16
	// Bit mask of TARGET2_WORK_EN field.
	SYSTIMER_CONF_TARGET2_WORK_EN_Msk = 0x400000
	// Bit TARGET2_WORK_EN.
	SYSTIMER_CONF_TARGET2_WORK_EN = 0x400000
	// Position of TARGET1_WORK_EN field.
	SYSTIMER_CONF_TARGET1_WORK_EN_Pos = 0x17
	// Bit mask of TARGET1_WORK_EN field.
	SYSTIMER_CONF_TARGET1_WORK_EN_Msk = 0x800000
	// Bit TARGET1_WORK_EN.
	SYSTIMER_CONF_TARGET1_WORK_EN = 0x800000
	// Position of TARGET0_WORK_EN field.
	SYSTIMER_CONF_TARGET0_WORK_EN_Pos = 0x18
	// Bit mask of TARGET0_WORK_EN field.
	SYSTIMER_CONF_TARGET0_WORK_EN_Msk = 0x1000000
	// Bit TARGET0_WORK_EN.
	SYSTIMER_CONF_TARGET0_WORK_EN = 0x1000000
	// Position of TIMER_UNIT1_CORE1_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Pos = 0x19
	// Bit mask of TIMER_UNIT1_CORE1_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN_Msk = 0x2000000
	// Bit TIMER_UNIT1_CORE1_STALL_EN.
	SYSTIMER_CONF_TIMER_UNIT1_CORE1_STALL_EN = 0x2000000
	// Position of TIMER_UNIT1_CORE0_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Pos = 0x1a
	// Bit mask of TIMER_UNIT1_CORE0_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN_Msk = 0x4000000
	// Bit TIMER_UNIT1_CORE0_STALL_EN.
	SYSTIMER_CONF_TIMER_UNIT1_CORE0_STALL_EN = 0x4000000
	// Position of TIMER_UNIT0_CORE1_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Pos = 0x1b
	// Bit mask of TIMER_UNIT0_CORE1_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN_Msk = 0x8000000
	// Bit TIMER_UNIT0_CORE1_STALL_EN.
	SYSTIMER_CONF_TIMER_UNIT0_CORE1_STALL_EN = 0x8000000
	// Position of TIMER_UNIT0_CORE0_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Pos = 0x1c
	// Bit mask of TIMER_UNIT0_CORE0_STALL_EN field.
	SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN_Msk = 0x10000000
	// Bit TIMER_UNIT0_CORE0_STALL_EN.
	SYSTIMER_CONF_TIMER_UNIT0_CORE0_STALL_EN = 0x10000000
	// Position of TIMER_UNIT1_WORK_EN field.
	SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Pos = 0x1d
	// Bit mask of TIMER_UNIT1_WORK_EN field.
	SYSTIMER_CONF_TIMER_UNIT1_WORK_EN_Msk = 0x20000000
	// Bit TIMER_UNIT1_WORK_EN.
	SYSTIMER_CONF_TIMER_UNIT1_WORK_EN = 0x20000000
	// Position of TIMER_UNIT0_WORK_EN field.
	SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Pos = 0x1e
	// Bit mask of TIMER_UNIT0_WORK_EN field.
	SYSTIMER_CONF_TIMER_UNIT0_WORK_EN_Msk = 0x40000000
	// Bit TIMER_UNIT0_WORK_EN.
	SYSTIMER_CONF_TIMER_UNIT0_WORK_EN = 0x40000000
	// Position of CLK_EN field.
	SYSTIMER_CONF_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	SYSTIMER_CONF_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	SYSTIMER_CONF_CLK_EN = 0x80000000

	// UNIT0_OP: system timer unit0 value update register
	// Position of TIMER_UNIT0_VALUE_VALID field.
	SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Pos = 0x1d
	// Bit mask of TIMER_UNIT0_VALUE_VALID field.
	SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID_Msk = 0x20000000
	// Bit TIMER_UNIT0_VALUE_VALID.
	SYSTIMER_UNIT0_OP_TIMER_UNIT0_VALUE_VALID = 0x20000000
	// Position of TIMER_UNIT0_UPDATE field.
	SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Pos = 0x1e
	// Bit mask of TIMER_UNIT0_UPDATE field.
	SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE_Msk = 0x40000000
	// Bit TIMER_UNIT0_UPDATE.
	SYSTIMER_UNIT0_OP_TIMER_UNIT0_UPDATE = 0x40000000

	// UNIT1_OP: system timer unit1 value update register
	// Position of TIMER_UNIT1_VALUE_VALID field.
	SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Pos = 0x1d
	// Bit mask of TIMER_UNIT1_VALUE_VALID field.
	SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID_Msk = 0x20000000
	// Bit TIMER_UNIT1_VALUE_VALID.
	SYSTIMER_UNIT1_OP_TIMER_UNIT1_VALUE_VALID = 0x20000000
	// Position of TIMER_UNIT1_UPDATE field.
	SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Pos = 0x1e
	// Bit mask of TIMER_UNIT1_UPDATE field.
	SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE_Msk = 0x40000000
	// Bit TIMER_UNIT1_UPDATE.
	SYSTIMER_UNIT1_OP_TIMER_UNIT1_UPDATE = 0x40000000

	// UNIT0_LOAD_HI: system timer unit0 value high load register
	// Position of TIMER_UNIT0_LOAD_HI field.
	SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Pos = 0x0
	// Bit mask of TIMER_UNIT0_LOAD_HI field.
	SYSTIMER_UNIT0_LOAD_HI_TIMER_UNIT0_LOAD_HI_Msk = 0xfffff

	// UNIT0_LOAD_LO: system timer unit0 value low load register
	// Position of TIMER_UNIT0_LOAD_LO field.
	SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Pos = 0x0
	// Bit mask of TIMER_UNIT0_LOAD_LO field.
	SYSTIMER_UNIT0_LOAD_LO_TIMER_UNIT0_LOAD_LO_Msk = 0xffffffff

	// UNIT1_LOAD_HI: system timer unit1 value high load register
	// Position of TIMER_UNIT1_LOAD_HI field.
	SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Pos = 0x0
	// Bit mask of TIMER_UNIT1_LOAD_HI field.
	SYSTIMER_UNIT1_LOAD_HI_TIMER_UNIT1_LOAD_HI_Msk = 0xfffff

	// UNIT1_LOAD_LO: system timer unit1 value low load register
	// Position of TIMER_UNIT1_LOAD_LO field.
	SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Pos = 0x0
	// Bit mask of TIMER_UNIT1_LOAD_LO field.
	SYSTIMER_UNIT1_LOAD_LO_TIMER_UNIT1_LOAD_LO_Msk = 0xffffffff

	// TARGET0_HI: system timer comp0 value high register
	// Position of TIMER_TARGET0_HI field.
	SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Pos = 0x0
	// Bit mask of TIMER_TARGET0_HI field.
	SYSTIMER_TARGET0_HI_TIMER_TARGET0_HI_Msk = 0xfffff

	// TARGET0_LO: system timer comp0 value low register
	// Position of TIMER_TARGET0_LO field.
	SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Pos = 0x0
	// Bit mask of TIMER_TARGET0_LO field.
	SYSTIMER_TARGET0_LO_TIMER_TARGET0_LO_Msk = 0xffffffff

	// TARGET1_HI: system timer comp1 value high register
	// Position of TIMER_TARGET1_HI field.
	SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Pos = 0x0
	// Bit mask of TIMER_TARGET1_HI field.
	SYSTIMER_TARGET1_HI_TIMER_TARGET1_HI_Msk = 0xfffff

	// TARGET1_LO: system timer comp1 value low register
	// Position of TIMER_TARGET1_LO field.
	SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Pos = 0x0
	// Bit mask of TIMER_TARGET1_LO field.
	SYSTIMER_TARGET1_LO_TIMER_TARGET1_LO_Msk = 0xffffffff

	// TARGET2_HI: system timer comp2 value high register
	// Position of TIMER_TARGET2_HI field.
	SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Pos = 0x0
	// Bit mask of TIMER_TARGET2_HI field.
	SYSTIMER_TARGET2_HI_TIMER_TARGET2_HI_Msk = 0xfffff

	// TARGET2_LO: system timer comp2 value low register
	// Position of TIMER_TARGET2_LO field.
	SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Pos = 0x0
	// Bit mask of TIMER_TARGET2_LO field.
	SYSTIMER_TARGET2_LO_TIMER_TARGET2_LO_Msk = 0xffffffff

	// TARGET0_CONF: system timer comp0 target mode register
	// Position of TARGET0_PERIOD field.
	SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Pos = 0x0
	// Bit mask of TARGET0_PERIOD field.
	SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_Msk = 0x3ffffff
	// Position of TARGET0_PERIOD_MODE field.
	SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Pos = 0x1e
	// Bit mask of TARGET0_PERIOD_MODE field.
	SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE_Msk = 0x40000000
	// Bit TARGET0_PERIOD_MODE.
	SYSTIMER_TARGET0_CONF_TARGET0_PERIOD_MODE = 0x40000000
	// Position of TARGET0_TIMER_UNIT_SEL field.
	SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Pos = 0x1f
	// Bit mask of TARGET0_TIMER_UNIT_SEL field.
	SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL_Msk = 0x80000000
	// Bit TARGET0_TIMER_UNIT_SEL.
	SYSTIMER_TARGET0_CONF_TARGET0_TIMER_UNIT_SEL = 0x80000000

	// TARGET1_CONF: system timer comp1 target mode register
	// Position of TARGET1_PERIOD field.
	SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Pos = 0x0
	// Bit mask of TARGET1_PERIOD field.
	SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_Msk = 0x3ffffff
	// Position of TARGET1_PERIOD_MODE field.
	SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Pos = 0x1e
	// Bit mask of TARGET1_PERIOD_MODE field.
	SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE_Msk = 0x40000000
	// Bit TARGET1_PERIOD_MODE.
	SYSTIMER_TARGET1_CONF_TARGET1_PERIOD_MODE = 0x40000000
	// Position of TARGET1_TIMER_UNIT_SEL field.
	SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Pos = 0x1f
	// Bit mask of TARGET1_TIMER_UNIT_SEL field.
	SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL_Msk = 0x80000000
	// Bit TARGET1_TIMER_UNIT_SEL.
	SYSTIMER_TARGET1_CONF_TARGET1_TIMER_UNIT_SEL = 0x80000000

	// TARGET2_CONF: system timer comp2 target mode register
	// Position of TARGET2_PERIOD field.
	SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Pos = 0x0
	// Bit mask of TARGET2_PERIOD field.
	SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_Msk = 0x3ffffff
	// Position of TARGET2_PERIOD_MODE field.
	SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Pos = 0x1e
	// Bit mask of TARGET2_PERIOD_MODE field.
	SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE_Msk = 0x40000000
	// Bit TARGET2_PERIOD_MODE.
	SYSTIMER_TARGET2_CONF_TARGET2_PERIOD_MODE = 0x40000000
	// Position of TARGET2_TIMER_UNIT_SEL field.
	SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Pos = 0x1f
	// Bit mask of TARGET2_TIMER_UNIT_SEL field.
	SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL_Msk = 0x80000000
	// Bit TARGET2_TIMER_UNIT_SEL.
	SYSTIMER_TARGET2_CONF_TARGET2_TIMER_UNIT_SEL = 0x80000000

	// UNIT0_VALUE_HI: system timer unit0 value high register
	// Position of TIMER_UNIT0_VALUE_HI field.
	SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Pos = 0x0
	// Bit mask of TIMER_UNIT0_VALUE_HI field.
	SYSTIMER_UNIT0_VALUE_HI_TIMER_UNIT0_VALUE_HI_Msk = 0xfffff

	// UNIT0_VALUE_LO: system timer unit0 value low register
	// Position of TIMER_UNIT0_VALUE_LO field.
	SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Pos = 0x0
	// Bit mask of TIMER_UNIT0_VALUE_LO field.
	SYSTIMER_UNIT0_VALUE_LO_TIMER_UNIT0_VALUE_LO_Msk = 0xffffffff

	// UNIT1_VALUE_HI: system timer unit1 value high register
	// Position of TIMER_UNIT1_VALUE_HI field.
	SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Pos = 0x0
	// Bit mask of TIMER_UNIT1_VALUE_HI field.
	SYSTIMER_UNIT1_VALUE_HI_TIMER_UNIT1_VALUE_HI_Msk = 0xfffff

	// UNIT1_VALUE_LO: system timer unit1 value low register
	// Position of TIMER_UNIT1_VALUE_LO field.
	SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Pos = 0x0
	// Bit mask of TIMER_UNIT1_VALUE_LO field.
	SYSTIMER_UNIT1_VALUE_LO_TIMER_UNIT1_VALUE_LO_Msk = 0xffffffff

	// COMP0_LOAD: system timer comp0 conf sync register
	// Position of TIMER_COMP0_LOAD field.
	SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Pos = 0x0
	// Bit mask of TIMER_COMP0_LOAD field.
	SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD_Msk = 0x1
	// Bit TIMER_COMP0_LOAD.
	SYSTIMER_COMP0_LOAD_TIMER_COMP0_LOAD = 0x1

	// COMP1_LOAD: system timer comp1 conf sync register
	// Position of TIMER_COMP1_LOAD field.
	SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Pos = 0x0
	// Bit mask of TIMER_COMP1_LOAD field.
	SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD_Msk = 0x1
	// Bit TIMER_COMP1_LOAD.
	SYSTIMER_COMP1_LOAD_TIMER_COMP1_LOAD = 0x1

	// COMP2_LOAD: system timer comp2 conf sync register
	// Position of TIMER_COMP2_LOAD field.
	SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Pos = 0x0
	// Bit mask of TIMER_COMP2_LOAD field.
	SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD_Msk = 0x1
	// Bit TIMER_COMP2_LOAD.
	SYSTIMER_COMP2_LOAD_TIMER_COMP2_LOAD = 0x1

	// UNIT0_LOAD: system timer unit0 conf sync register
	// Position of TIMER_UNIT0_LOAD field.
	SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Pos = 0x0
	// Bit mask of TIMER_UNIT0_LOAD field.
	SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD_Msk = 0x1
	// Bit TIMER_UNIT0_LOAD.
	SYSTIMER_UNIT0_LOAD_TIMER_UNIT0_LOAD = 0x1

	// UNIT1_LOAD: system timer unit1 conf sync register
	// Position of TIMER_UNIT1_LOAD field.
	SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Pos = 0x0
	// Bit mask of TIMER_UNIT1_LOAD field.
	SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD_Msk = 0x1
	// Bit TIMER_UNIT1_LOAD.
	SYSTIMER_UNIT1_LOAD_TIMER_UNIT1_LOAD = 0x1

	// INT_ENA: systimer interrupt enable register
	// Position of TARGET0_INT_ENA field.
	SYSTIMER_INT_ENA_TARGET0_INT_ENA_Pos = 0x0
	// Bit mask of TARGET0_INT_ENA field.
	SYSTIMER_INT_ENA_TARGET0_INT_ENA_Msk = 0x1
	// Bit TARGET0_INT_ENA.
	SYSTIMER_INT_ENA_TARGET0_INT_ENA = 0x1
	// Position of TARGET1_INT_ENA field.
	SYSTIMER_INT_ENA_TARGET1_INT_ENA_Pos = 0x1
	// Bit mask of TARGET1_INT_ENA field.
	SYSTIMER_INT_ENA_TARGET1_INT_ENA_Msk = 0x2
	// Bit TARGET1_INT_ENA.
	SYSTIMER_INT_ENA_TARGET1_INT_ENA = 0x2
	// Position of TARGET2_INT_ENA field.
	SYSTIMER_INT_ENA_TARGET2_INT_ENA_Pos = 0x2
	// Bit mask of TARGET2_INT_ENA field.
	SYSTIMER_INT_ENA_TARGET2_INT_ENA_Msk = 0x4
	// Bit TARGET2_INT_ENA.
	SYSTIMER_INT_ENA_TARGET2_INT_ENA = 0x4

	// INT_RAW: systimer interrupt raw register
	// Position of TARGET0_INT_RAW field.
	SYSTIMER_INT_RAW_TARGET0_INT_RAW_Pos = 0x0
	// Bit mask of TARGET0_INT_RAW field.
	SYSTIMER_INT_RAW_TARGET0_INT_RAW_Msk = 0x1
	// Bit TARGET0_INT_RAW.
	SYSTIMER_INT_RAW_TARGET0_INT_RAW = 0x1
	// Position of TARGET1_INT_RAW field.
	SYSTIMER_INT_RAW_TARGET1_INT_RAW_Pos = 0x1
	// Bit mask of TARGET1_INT_RAW field.
	SYSTIMER_INT_RAW_TARGET1_INT_RAW_Msk = 0x2
	// Bit TARGET1_INT_RAW.
	SYSTIMER_INT_RAW_TARGET1_INT_RAW = 0x2
	// Position of TARGET2_INT_RAW field.
	SYSTIMER_INT_RAW_TARGET2_INT_RAW_Pos = 0x2
	// Bit mask of TARGET2_INT_RAW field.
	SYSTIMER_INT_RAW_TARGET2_INT_RAW_Msk = 0x4
	// Bit TARGET2_INT_RAW.
	SYSTIMER_INT_RAW_TARGET2_INT_RAW = 0x4

	// INT_CLR: systimer interrupt clear register
	// Position of TARGET0_INT_CLR field.
	SYSTIMER_INT_CLR_TARGET0_INT_CLR_Pos = 0x0
	// Bit mask of TARGET0_INT_CLR field.
	SYSTIMER_INT_CLR_TARGET0_INT_CLR_Msk = 0x1
	// Bit TARGET0_INT_CLR.
	SYSTIMER_INT_CLR_TARGET0_INT_CLR = 0x1
	// Position of TARGET1_INT_CLR field.
	SYSTIMER_INT_CLR_TARGET1_INT_CLR_Pos = 0x1
	// Bit mask of TARGET1_INT_CLR field.
	SYSTIMER_INT_CLR_TARGET1_INT_CLR_Msk = 0x2
	// Bit TARGET1_INT_CLR.
	SYSTIMER_INT_CLR_TARGET1_INT_CLR = 0x2
	// Position of TARGET2_INT_CLR field.
	SYSTIMER_INT_CLR_TARGET2_INT_CLR_Pos = 0x2
	// Bit mask of TARGET2_INT_CLR field.
	SYSTIMER_INT_CLR_TARGET2_INT_CLR_Msk = 0x4
	// Bit TARGET2_INT_CLR.
	SYSTIMER_INT_CLR_TARGET2_INT_CLR = 0x4

	// INT_ST: systimer interrupt status register
	// Position of TARGET0_INT_ST field.
	SYSTIMER_INT_ST_TARGET0_INT_ST_Pos = 0x0
	// Bit mask of TARGET0_INT_ST field.
	SYSTIMER_INT_ST_TARGET0_INT_ST_Msk = 0x1
	// Bit TARGET0_INT_ST.
	SYSTIMER_INT_ST_TARGET0_INT_ST = 0x1
	// Position of TARGET1_INT_ST field.
	SYSTIMER_INT_ST_TARGET1_INT_ST_Pos = 0x1
	// Bit mask of TARGET1_INT_ST field.
	SYSTIMER_INT_ST_TARGET1_INT_ST_Msk = 0x2
	// Bit TARGET1_INT_ST.
	SYSTIMER_INT_ST_TARGET1_INT_ST = 0x2
	// Position of TARGET2_INT_ST field.
	SYSTIMER_INT_ST_TARGET2_INT_ST_Pos = 0x2
	// Bit mask of TARGET2_INT_ST field.
	SYSTIMER_INT_ST_TARGET2_INT_ST_Msk = 0x4
	// Bit TARGET2_INT_ST.
	SYSTIMER_INT_ST_TARGET2_INT_ST = 0x4

	// REAL_TARGET0_LO: system timer comp0 actual target value low register
	// Position of TARGET0_LO_RO field.
	SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Pos = 0x0
	// Bit mask of TARGET0_LO_RO field.
	SYSTIMER_REAL_TARGET0_LO_TARGET0_LO_RO_Msk = 0xffffffff

	// REAL_TARGET0_HI: system timer comp0 actual target value high register
	// Position of TARGET0_HI_RO field.
	SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Pos = 0x0
	// Bit mask of TARGET0_HI_RO field.
	SYSTIMER_REAL_TARGET0_HI_TARGET0_HI_RO_Msk = 0xfffff

	// REAL_TARGET1_LO: system timer comp1 actual target value low register
	// Position of TARGET1_LO_RO field.
	SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Pos = 0x0
	// Bit mask of TARGET1_LO_RO field.
	SYSTIMER_REAL_TARGET1_LO_TARGET1_LO_RO_Msk = 0xffffffff

	// REAL_TARGET1_HI: system timer comp1 actual target value high register
	// Position of TARGET1_HI_RO field.
	SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Pos = 0x0
	// Bit mask of TARGET1_HI_RO field.
	SYSTIMER_REAL_TARGET1_HI_TARGET1_HI_RO_Msk = 0xfffff

	// REAL_TARGET2_LO: system timer comp2 actual target value low register
	// Position of TARGET2_LO_RO field.
	SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Pos = 0x0
	// Bit mask of TARGET2_LO_RO field.
	SYSTIMER_REAL_TARGET2_LO_TARGET2_LO_RO_Msk = 0xffffffff

	// REAL_TARGET2_HI: system timer comp2 actual target value high register
	// Position of TARGET2_HI_RO field.
	SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Pos = 0x0
	// Bit mask of TARGET2_HI_RO field.
	SYSTIMER_REAL_TARGET2_HI_TARGET2_HI_RO_Msk = 0xfffff

	// DATE: system timer version control register
	// Position of DATE field.
	SYSTIMER_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	SYSTIMER_DATE_DATE_Msk = 0xffffffff
)

// Constants for TIMG0: Timer Group 0
const (
	// T0CONFIG: Timer %s configuration register
	// Position of USE_XTAL field.
	TIMG_T0CONFIG_USE_XTAL_Pos = 0x9
	// Bit mask of USE_XTAL field.
	TIMG_T0CONFIG_USE_XTAL_Msk = 0x200
	// Bit USE_XTAL.
	TIMG_T0CONFIG_USE_XTAL = 0x200
	// Position of ALARM_EN field.
	TIMG_T0CONFIG_ALARM_EN_Pos = 0xa
	// Bit mask of ALARM_EN field.
	TIMG_T0CONFIG_ALARM_EN_Msk = 0x400
	// Bit ALARM_EN.
	TIMG_T0CONFIG_ALARM_EN = 0x400
	// Position of DIVCNT_RST field.
	TIMG_T0CONFIG_DIVCNT_RST_Pos = 0xc
	// Bit mask of DIVCNT_RST field.
	TIMG_T0CONFIG_DIVCNT_RST_Msk = 0x1000
	// Bit DIVCNT_RST.
	TIMG_T0CONFIG_DIVCNT_RST = 0x1000
	// Position of DIVIDER field.
	TIMG_T0CONFIG_DIVIDER_Pos = 0xd
	// Bit mask of DIVIDER field.
	TIMG_T0CONFIG_DIVIDER_Msk = 0x1fffe000
	// Position of AUTORELOAD field.
	TIMG_T0CONFIG_AUTORELOAD_Pos = 0x1d
	// Bit mask of AUTORELOAD field.
	TIMG_T0CONFIG_AUTORELOAD_Msk = 0x20000000
	// Bit AUTORELOAD.
	TIMG_T0CONFIG_AUTORELOAD = 0x20000000
	// Position of INCREASE field.
	TIMG_T0CONFIG_INCREASE_Pos = 0x1e
	// Bit mask of INCREASE field.
	TIMG_T0CONFIG_INCREASE_Msk = 0x40000000
	// Bit INCREASE.
	TIMG_T0CONFIG_INCREASE = 0x40000000
	// Position of EN field.
	TIMG_T0CONFIG_EN_Pos = 0x1f
	// Bit mask of EN field.
	TIMG_T0CONFIG_EN_Msk = 0x80000000
	// Bit EN.
	TIMG_T0CONFIG_EN = 0x80000000

	// T0LO: Timer %s current value, low 32 bits
	// Position of LO field.
	TIMG_T0LO_LO_Pos = 0x0
	// Bit mask of LO field.
	TIMG_T0LO_LO_Msk = 0xffffffff

	// T0HI: Timer %s current value, high 22 bits
	// Position of HI field.
	TIMG_T0HI_HI_Pos = 0x0
	// Bit mask of HI field.
	TIMG_T0HI_HI_Msk = 0x3fffff

	// T0UPDATE: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG
	// Position of UPDATE field.
	TIMG_T0UPDATE_UPDATE_Pos = 0x1f
	// Bit mask of UPDATE field.
	TIMG_T0UPDATE_UPDATE_Msk = 0x80000000
	// Bit UPDATE.
	TIMG_T0UPDATE_UPDATE = 0x80000000

	// T0ALARMLO: Timer %s alarm value, low 32 bits
	// Position of ALARM_LO field.
	TIMG_T0ALARMLO_ALARM_LO_Pos = 0x0
	// Bit mask of ALARM_LO field.
	TIMG_T0ALARMLO_ALARM_LO_Msk = 0xffffffff

	// T0ALARMHI: Timer %s alarm value, high bits
	// Position of ALARM_HI field.
	TIMG_T0ALARMHI_ALARM_HI_Pos = 0x0
	// Bit mask of ALARM_HI field.
	TIMG_T0ALARMHI_ALARM_HI_Msk = 0x3fffff

	// T0LOADLO: Timer %s reload value, low 32 bits
	// Position of LOAD_LO field.
	TIMG_T0LOADLO_LOAD_LO_Pos = 0x0
	// Bit mask of LOAD_LO field.
	TIMG_T0LOADLO_LOAD_LO_Msk = 0xffffffff

	// T0LOADHI: Timer %s reload value, high 22 bits
	// Position of LOAD_HI field.
	TIMG_T0LOADHI_LOAD_HI_Pos = 0x0
	// Bit mask of LOAD_HI field.
	TIMG_T0LOADHI_LOAD_HI_Msk = 0x3fffff

	// T0LOAD: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG
	// Position of LOAD field.
	TIMG_T0LOAD_LOAD_Pos = 0x0
	// Bit mask of LOAD field.
	TIMG_T0LOAD_LOAD_Msk = 0xffffffff

	// WDTCONFIG0: Watchdog timer configuration register
	// Position of WDT_APPCPU_RESET_EN field.
	TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Pos = 0xc
	// Bit mask of WDT_APPCPU_RESET_EN field.
	TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN_Msk = 0x1000
	// Bit WDT_APPCPU_RESET_EN.
	TIMG_WDTCONFIG0_WDT_APPCPU_RESET_EN = 0x1000
	// Position of WDT_PROCPU_RESET_EN field.
	TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Pos = 0xd
	// Bit mask of WDT_PROCPU_RESET_EN field.
	TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN_Msk = 0x2000
	// Bit WDT_PROCPU_RESET_EN.
	TIMG_WDTCONFIG0_WDT_PROCPU_RESET_EN = 0x2000
	// Position of WDT_FLASHBOOT_MOD_EN field.
	TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Pos = 0xe
	// Bit mask of WDT_FLASHBOOT_MOD_EN field.
	TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN_Msk = 0x4000
	// Bit WDT_FLASHBOOT_MOD_EN.
	TIMG_WDTCONFIG0_WDT_FLASHBOOT_MOD_EN = 0x4000
	// Position of WDT_SYS_RESET_LENGTH field.
	TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Pos = 0xf
	// Bit mask of WDT_SYS_RESET_LENGTH field.
	TIMG_WDTCONFIG0_WDT_SYS_RESET_LENGTH_Msk = 0x38000
	// Position of WDT_CPU_RESET_LENGTH field.
	TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Pos = 0x12
	// Bit mask of WDT_CPU_RESET_LENGTH field.
	TIMG_WDTCONFIG0_WDT_CPU_RESET_LENGTH_Msk = 0x1c0000
	// Position of WDT_USE_XTAL field.
	TIMG_WDTCONFIG0_WDT_USE_XTAL_Pos = 0x15
	// Bit mask of WDT_USE_XTAL field.
	TIMG_WDTCONFIG0_WDT_USE_XTAL_Msk = 0x200000
	// Bit WDT_USE_XTAL.
	TIMG_WDTCONFIG0_WDT_USE_XTAL = 0x200000
	// Position of WDT_CONF_UPDATE_EN field.
	TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Pos = 0x16
	// Bit mask of WDT_CONF_UPDATE_EN field.
	TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN_Msk = 0x400000
	// Bit WDT_CONF_UPDATE_EN.
	TIMG_WDTCONFIG0_WDT_CONF_UPDATE_EN = 0x400000
	// Position of WDT_STG3 field.
	TIMG_WDTCONFIG0_WDT_STG3_Pos = 0x17
	// Bit mask of WDT_STG3 field.
	TIMG_WDTCONFIG0_WDT_STG3_Msk = 0x1800000
	// Position of WDT_STG2 field.
	TIMG_WDTCONFIG0_WDT_STG2_Pos = 0x19
	// Bit mask of WDT_STG2 field.
	TIMG_WDTCONFIG0_WDT_STG2_Msk = 0x6000000
	// Position of WDT_STG1 field.
	TIMG_WDTCONFIG0_WDT_STG1_Pos = 0x1b
	// Bit mask of WDT_STG1 field.
	TIMG_WDTCONFIG0_WDT_STG1_Msk = 0x18000000
	// Position of WDT_STG0 field.
	TIMG_WDTCONFIG0_WDT_STG0_Pos = 0x1d
	// Bit mask of WDT_STG0 field.
	TIMG_WDTCONFIG0_WDT_STG0_Msk = 0x60000000
	// Position of WDT_EN field.
	TIMG_WDTCONFIG0_WDT_EN_Pos = 0x1f
	// Bit mask of WDT_EN field.
	TIMG_WDTCONFIG0_WDT_EN_Msk = 0x80000000
	// Bit WDT_EN.
	TIMG_WDTCONFIG0_WDT_EN = 0x80000000

	// WDTCONFIG1: Watchdog timer prescaler register
	// Position of WDT_DIVCNT_RST field.
	TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Pos = 0x0
	// Bit mask of WDT_DIVCNT_RST field.
	TIMG_WDTCONFIG1_WDT_DIVCNT_RST_Msk = 0x1
	// Bit WDT_DIVCNT_RST.
	TIMG_WDTCONFIG1_WDT_DIVCNT_RST = 0x1
	// Position of WDT_CLK_PRESCALE field.
	TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Pos = 0x10
	// Bit mask of WDT_CLK_PRESCALE field.
	TIMG_WDTCONFIG1_WDT_CLK_PRESCALE_Msk = 0xffff0000

	// WDTCONFIG2: Watchdog timer stage 0 timeout value
	// Position of WDT_STG0_HOLD field.
	TIMG_WDTCONFIG2_WDT_STG0_HOLD_Pos = 0x0
	// Bit mask of WDT_STG0_HOLD field.
	TIMG_WDTCONFIG2_WDT_STG0_HOLD_Msk = 0xffffffff

	// WDTCONFIG3: Watchdog timer stage 1 timeout value
	// Position of WDT_STG1_HOLD field.
	TIMG_WDTCONFIG3_WDT_STG1_HOLD_Pos = 0x0
	// Bit mask of WDT_STG1_HOLD field.
	TIMG_WDTCONFIG3_WDT_STG1_HOLD_Msk = 0xffffffff

	// WDTCONFIG4: Watchdog timer stage 2 timeout value
	// Position of WDT_STG2_HOLD field.
	TIMG_WDTCONFIG4_WDT_STG2_HOLD_Pos = 0x0
	// Bit mask of WDT_STG2_HOLD field.
	TIMG_WDTCONFIG4_WDT_STG2_HOLD_Msk = 0xffffffff

	// WDTCONFIG5: Watchdog timer stage 3 timeout value
	// Position of WDT_STG3_HOLD field.
	TIMG_WDTCONFIG5_WDT_STG3_HOLD_Pos = 0x0
	// Bit mask of WDT_STG3_HOLD field.
	TIMG_WDTCONFIG5_WDT_STG3_HOLD_Msk = 0xffffffff

	// WDTFEED: Write to feed the watchdog timer
	// Position of WDT_FEED field.
	TIMG_WDTFEED_WDT_FEED_Pos = 0x0
	// Bit mask of WDT_FEED field.
	TIMG_WDTFEED_WDT_FEED_Msk = 0xffffffff

	// WDTWPROTECT: Watchdog write protect register
	// Position of WDT_WKEY field.
	TIMG_WDTWPROTECT_WDT_WKEY_Pos = 0x0
	// Bit mask of WDT_WKEY field.
	TIMG_WDTWPROTECT_WDT_WKEY_Msk = 0xffffffff

	// RTCCALICFG: RTC calibration configure register
	// Position of RTC_CALI_START_CYCLING field.
	TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Pos = 0xc
	// Bit mask of RTC_CALI_START_CYCLING field.
	TIMG_RTCCALICFG_RTC_CALI_START_CYCLING_Msk = 0x1000
	// Bit RTC_CALI_START_CYCLING.
	TIMG_RTCCALICFG_RTC_CALI_START_CYCLING = 0x1000
	// Position of RTC_CALI_CLK_SEL field.
	TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Pos = 0xd
	// Bit mask of RTC_CALI_CLK_SEL field.
	TIMG_RTCCALICFG_RTC_CALI_CLK_SEL_Msk = 0x6000
	// Position of RTC_CALI_RDY field.
	TIMG_RTCCALICFG_RTC_CALI_RDY_Pos = 0xf
	// Bit mask of RTC_CALI_RDY field.
	TIMG_RTCCALICFG_RTC_CALI_RDY_Msk = 0x8000
	// Bit RTC_CALI_RDY.
	TIMG_RTCCALICFG_RTC_CALI_RDY = 0x8000
	// Position of RTC_CALI_MAX field.
	TIMG_RTCCALICFG_RTC_CALI_MAX_Pos = 0x10
	// Bit mask of RTC_CALI_MAX field.
	TIMG_RTCCALICFG_RTC_CALI_MAX_Msk = 0x7fff0000
	// Position of RTC_CALI_START field.
	TIMG_RTCCALICFG_RTC_CALI_START_Pos = 0x1f
	// Bit mask of RTC_CALI_START field.
	TIMG_RTCCALICFG_RTC_CALI_START_Msk = 0x80000000
	// Bit RTC_CALI_START.
	TIMG_RTCCALICFG_RTC_CALI_START = 0x80000000

	// RTCCALICFG1: RTC calibration configure1 register
	// Position of RTC_CALI_CYCLING_DATA_VLD field.
	TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Pos = 0x0
	// Bit mask of RTC_CALI_CYCLING_DATA_VLD field.
	TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD_Msk = 0x1
	// Bit RTC_CALI_CYCLING_DATA_VLD.
	TIMG_RTCCALICFG1_RTC_CALI_CYCLING_DATA_VLD = 0x1
	// Position of RTC_CALI_VALUE field.
	TIMG_RTCCALICFG1_RTC_CALI_VALUE_Pos = 0x7
	// Bit mask of RTC_CALI_VALUE field.
	TIMG_RTCCALICFG1_RTC_CALI_VALUE_Msk = 0xffffff80

	// INT_ENA_TIMERS: Interrupt enable bits
	// Position of T0_INT_ENA field.
	TIMG_INT_ENA_TIMERS_T0_INT_ENA_Pos = 0x0
	// Bit mask of T0_INT_ENA field.
	TIMG_INT_ENA_TIMERS_T0_INT_ENA_Msk = 0x1
	// Bit T0_INT_ENA.
	TIMG_INT_ENA_TIMERS_T0_INT_ENA = 0x1
	// Position of T1_INT_ENA field.
	TIMG_INT_ENA_TIMERS_T1_INT_ENA_Pos = 0x1
	// Bit mask of T1_INT_ENA field.
	TIMG_INT_ENA_TIMERS_T1_INT_ENA_Msk = 0x2
	// Bit T1_INT_ENA.
	TIMG_INT_ENA_TIMERS_T1_INT_ENA = 0x2
	// Position of WDT_INT_ENA field.
	TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Pos = 0x2
	// Bit mask of WDT_INT_ENA field.
	TIMG_INT_ENA_TIMERS_WDT_INT_ENA_Msk = 0x4
	// Bit WDT_INT_ENA.
	TIMG_INT_ENA_TIMERS_WDT_INT_ENA = 0x4

	// INT_RAW_TIMERS: Raw interrupt status
	// Position of T0_INT_RAW field.
	TIMG_INT_RAW_TIMERS_T0_INT_RAW_Pos = 0x0
	// Bit mask of T0_INT_RAW field.
	TIMG_INT_RAW_TIMERS_T0_INT_RAW_Msk = 0x1
	// Bit T0_INT_RAW.
	TIMG_INT_RAW_TIMERS_T0_INT_RAW = 0x1
	// Position of T1_INT_RAW field.
	TIMG_INT_RAW_TIMERS_T1_INT_RAW_Pos = 0x1
	// Bit mask of T1_INT_RAW field.
	TIMG_INT_RAW_TIMERS_T1_INT_RAW_Msk = 0x2
	// Bit T1_INT_RAW.
	TIMG_INT_RAW_TIMERS_T1_INT_RAW = 0x2
	// Position of WDT_INT_RAW field.
	TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Pos = 0x2
	// Bit mask of WDT_INT_RAW field.
	TIMG_INT_RAW_TIMERS_WDT_INT_RAW_Msk = 0x4
	// Bit WDT_INT_RAW.
	TIMG_INT_RAW_TIMERS_WDT_INT_RAW = 0x4

	// INT_ST_TIMERS: Masked interrupt status
	// Position of T0_INT_ST field.
	TIMG_INT_ST_TIMERS_T0_INT_ST_Pos = 0x0
	// Bit mask of T0_INT_ST field.
	TIMG_INT_ST_TIMERS_T0_INT_ST_Msk = 0x1
	// Bit T0_INT_ST.
	TIMG_INT_ST_TIMERS_T0_INT_ST = 0x1
	// Position of T1_INT_ST field.
	TIMG_INT_ST_TIMERS_T1_INT_ST_Pos = 0x1
	// Bit mask of T1_INT_ST field.
	TIMG_INT_ST_TIMERS_T1_INT_ST_Msk = 0x2
	// Bit T1_INT_ST.
	TIMG_INT_ST_TIMERS_T1_INT_ST = 0x2
	// Position of WDT_INT_ST field.
	TIMG_INT_ST_TIMERS_WDT_INT_ST_Pos = 0x2
	// Bit mask of WDT_INT_ST field.
	TIMG_INT_ST_TIMERS_WDT_INT_ST_Msk = 0x4
	// Bit WDT_INT_ST.
	TIMG_INT_ST_TIMERS_WDT_INT_ST = 0x4

	// INT_CLR_TIMERS: Interrupt clear bits
	// Position of T0_INT_CLR field.
	TIMG_INT_CLR_TIMERS_T0_INT_CLR_Pos = 0x0
	// Bit mask of T0_INT_CLR field.
	TIMG_INT_CLR_TIMERS_T0_INT_CLR_Msk = 0x1
	// Bit T0_INT_CLR.
	TIMG_INT_CLR_TIMERS_T0_INT_CLR = 0x1
	// Position of T1_INT_CLR field.
	TIMG_INT_CLR_TIMERS_T1_INT_CLR_Pos = 0x1
	// Bit mask of T1_INT_CLR field.
	TIMG_INT_CLR_TIMERS_T1_INT_CLR_Msk = 0x2
	// Bit T1_INT_CLR.
	TIMG_INT_CLR_TIMERS_T1_INT_CLR = 0x2
	// Position of WDT_INT_CLR field.
	TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Pos = 0x2
	// Bit mask of WDT_INT_CLR field.
	TIMG_INT_CLR_TIMERS_WDT_INT_CLR_Msk = 0x4
	// Bit WDT_INT_CLR.
	TIMG_INT_CLR_TIMERS_WDT_INT_CLR = 0x4

	// RTCCALICFG2: Timer group calibration register
	// Position of RTC_CALI_TIMEOUT field.
	TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Pos = 0x0
	// Bit mask of RTC_CALI_TIMEOUT field.
	TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_Msk = 0x1
	// Bit RTC_CALI_TIMEOUT.
	TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT = 0x1
	// Position of RTC_CALI_TIMEOUT_RST_CNT field.
	TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Pos = 0x3
	// Bit mask of RTC_CALI_TIMEOUT_RST_CNT field.
	TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_RST_CNT_Msk = 0x78
	// Position of RTC_CALI_TIMEOUT_THRES field.
	TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Pos = 0x7
	// Bit mask of RTC_CALI_TIMEOUT_THRES field.
	TIMG_RTCCALICFG2_RTC_CALI_TIMEOUT_THRES_Msk = 0xffffff80

	// NTIMERS_DATE: Timer version control register
	// Position of NTIMGS_DATE field.
	TIMG_NTIMERS_DATE_NTIMGS_DATE_Pos = 0x0
	// Bit mask of NTIMGS_DATE field.
	TIMG_NTIMERS_DATE_NTIMGS_DATE_Msk = 0xfffffff

	// REGCLK: Timer group clock gate register
	// Position of ETM_EN field.
	TIMG_REGCLK_ETM_EN_Pos = 0x1c
	// Bit mask of ETM_EN field.
	TIMG_REGCLK_ETM_EN_Msk = 0x10000000
	// Bit ETM_EN.
	TIMG_REGCLK_ETM_EN = 0x10000000
	// Position of WDT_CLK_IS_ACTIVE field.
	TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Pos = 0x1d
	// Bit mask of WDT_CLK_IS_ACTIVE field.
	TIMG_REGCLK_WDT_CLK_IS_ACTIVE_Msk = 0x20000000
	// Bit WDT_CLK_IS_ACTIVE.
	TIMG_REGCLK_WDT_CLK_IS_ACTIVE = 0x20000000
	// Position of TIMER_CLK_IS_ACTIVE field.
	TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Pos = 0x1e
	// Bit mask of TIMER_CLK_IS_ACTIVE field.
	TIMG_REGCLK_TIMER_CLK_IS_ACTIVE_Msk = 0x40000000
	// Bit TIMER_CLK_IS_ACTIVE.
	TIMG_REGCLK_TIMER_CLK_IS_ACTIVE = 0x40000000
	// Position of CLK_EN field.
	TIMG_REGCLK_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	TIMG_REGCLK_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	TIMG_REGCLK_CLK_EN = 0x80000000
)

// Constants for TRACE0: TRACE0 Peripheral
const (
	// MEM_START_ADDR: mem start addr
	// Position of MEM_START_ADDR field.
	TRACE_MEM_START_ADDR_MEM_START_ADDR_Pos = 0x0
	// Bit mask of MEM_START_ADDR field.
	TRACE_MEM_START_ADDR_MEM_START_ADDR_Msk = 0xffffffff

	// MEM_END_ADDR: mem end addr
	// Position of MEM_END_ADDR field.
	TRACE_MEM_END_ADDR_MEM_END_ADDR_Pos = 0x0
	// Bit mask of MEM_END_ADDR field.
	TRACE_MEM_END_ADDR_MEM_END_ADDR_Msk = 0xffffffff

	// MEM_CURRENT_ADDR: mem current addr
	// Position of MEM_CURRENT_ADDR field.
	TRACE_MEM_CURRENT_ADDR_MEM_CURRENT_ADDR_Pos = 0x0
	// Bit mask of MEM_CURRENT_ADDR field.
	TRACE_MEM_CURRENT_ADDR_MEM_CURRENT_ADDR_Msk = 0xffffffff

	// MEM_ADDR_UPDATE: mem addr update
	// Position of MEM_CURRENT_ADDR_UPDATE field.
	TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE_Pos = 0x0
	// Bit mask of MEM_CURRENT_ADDR_UPDATE field.
	TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE_Msk = 0x1
	// Bit MEM_CURRENT_ADDR_UPDATE.
	TRACE_MEM_ADDR_UPDATE_MEM_CURRENT_ADDR_UPDATE = 0x1

	// FIFO_STATUS: fifo status register
	// Position of FIFO_EMPTY field.
	TRACE_FIFO_STATUS_FIFO_EMPTY_Pos = 0x0
	// Bit mask of FIFO_EMPTY field.
	TRACE_FIFO_STATUS_FIFO_EMPTY_Msk = 0x1
	// Bit FIFO_EMPTY.
	TRACE_FIFO_STATUS_FIFO_EMPTY = 0x1
	// Position of WORK_STATUS field.
	TRACE_FIFO_STATUS_WORK_STATUS_Pos = 0x1
	// Bit mask of WORK_STATUS field.
	TRACE_FIFO_STATUS_WORK_STATUS_Msk = 0x6

	// INTR_ENA: interrupt enable register
	// Position of FIFO_OVERFLOW_INTR_ENA field.
	TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA_Pos = 0x0
	// Bit mask of FIFO_OVERFLOW_INTR_ENA field.
	TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA_Msk = 0x1
	// Bit FIFO_OVERFLOW_INTR_ENA.
	TRACE_INTR_ENA_FIFO_OVERFLOW_INTR_ENA = 0x1
	// Position of MEM_FULL_INTR_ENA field.
	TRACE_INTR_ENA_MEM_FULL_INTR_ENA_Pos = 0x1
	// Bit mask of MEM_FULL_INTR_ENA field.
	TRACE_INTR_ENA_MEM_FULL_INTR_ENA_Msk = 0x2
	// Bit MEM_FULL_INTR_ENA.
	TRACE_INTR_ENA_MEM_FULL_INTR_ENA = 0x2

	// INTR_RAW: interrupt status register
	// Position of FIFO_OVERFLOW_INTR_RAW field.
	TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW_Pos = 0x0
	// Bit mask of FIFO_OVERFLOW_INTR_RAW field.
	TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW_Msk = 0x1
	// Bit FIFO_OVERFLOW_INTR_RAW.
	TRACE_INTR_RAW_FIFO_OVERFLOW_INTR_RAW = 0x1
	// Position of MEM_FULL_INTR_RAW field.
	TRACE_INTR_RAW_MEM_FULL_INTR_RAW_Pos = 0x1
	// Bit mask of MEM_FULL_INTR_RAW field.
	TRACE_INTR_RAW_MEM_FULL_INTR_RAW_Msk = 0x2
	// Bit MEM_FULL_INTR_RAW.
	TRACE_INTR_RAW_MEM_FULL_INTR_RAW = 0x2

	// INTR_CLR: interrupt clear register
	// Position of FIFO_OVERFLOW_INTR_CLR field.
	TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR_Pos = 0x0
	// Bit mask of FIFO_OVERFLOW_INTR_CLR field.
	TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR_Msk = 0x1
	// Bit FIFO_OVERFLOW_INTR_CLR.
	TRACE_INTR_CLR_FIFO_OVERFLOW_INTR_CLR = 0x1
	// Position of MEM_FULL_INTR_CLR field.
	TRACE_INTR_CLR_MEM_FULL_INTR_CLR_Pos = 0x1
	// Bit mask of MEM_FULL_INTR_CLR field.
	TRACE_INTR_CLR_MEM_FULL_INTR_CLR_Msk = 0x2
	// Bit MEM_FULL_INTR_CLR.
	TRACE_INTR_CLR_MEM_FULL_INTR_CLR = 0x2

	// TRIGGER: trigger register
	// Position of ON field.
	TRACE_TRIGGER_ON_Pos = 0x0
	// Bit mask of ON field.
	TRACE_TRIGGER_ON_Msk = 0x1
	// Bit ON.
	TRACE_TRIGGER_ON = 0x1
	// Position of OFF field.
	TRACE_TRIGGER_OFF_Pos = 0x1
	// Bit mask of OFF field.
	TRACE_TRIGGER_OFF_Msk = 0x2
	// Bit OFF.
	TRACE_TRIGGER_OFF = 0x2
	// Position of MEM_LOOP field.
	TRACE_TRIGGER_MEM_LOOP_Pos = 0x2
	// Bit mask of MEM_LOOP field.
	TRACE_TRIGGER_MEM_LOOP_Msk = 0x4
	// Bit MEM_LOOP.
	TRACE_TRIGGER_MEM_LOOP = 0x4
	// Position of RESTART_ENA field.
	TRACE_TRIGGER_RESTART_ENA_Pos = 0x3
	// Bit mask of RESTART_ENA field.
	TRACE_TRIGGER_RESTART_ENA_Msk = 0x8
	// Bit RESTART_ENA.
	TRACE_TRIGGER_RESTART_ENA = 0x8

	// CONFIG: trace configuration register
	// Position of DM_TRIGGER_ENA field.
	TRACE_CONFIG_DM_TRIGGER_ENA_Pos = 0x0
	// Bit mask of DM_TRIGGER_ENA field.
	TRACE_CONFIG_DM_TRIGGER_ENA_Msk = 0x1
	// Bit DM_TRIGGER_ENA.
	TRACE_CONFIG_DM_TRIGGER_ENA = 0x1
	// Position of RESET_ENA field.
	TRACE_CONFIG_RESET_ENA_Pos = 0x1
	// Bit mask of RESET_ENA field.
	TRACE_CONFIG_RESET_ENA_Msk = 0x2
	// Bit RESET_ENA.
	TRACE_CONFIG_RESET_ENA = 0x2
	// Position of HALT_ENA field.
	TRACE_CONFIG_HALT_ENA_Pos = 0x2
	// Bit mask of HALT_ENA field.
	TRACE_CONFIG_HALT_ENA_Msk = 0x4
	// Bit HALT_ENA.
	TRACE_CONFIG_HALT_ENA = 0x4
	// Position of STALL_ENA field.
	TRACE_CONFIG_STALL_ENA_Pos = 0x3
	// Bit mask of STALL_ENA field.
	TRACE_CONFIG_STALL_ENA_Msk = 0x8
	// Bit STALL_ENA.
	TRACE_CONFIG_STALL_ENA = 0x8
	// Position of FULL_ADDRESS field.
	TRACE_CONFIG_FULL_ADDRESS_Pos = 0x4
	// Bit mask of FULL_ADDRESS field.
	TRACE_CONFIG_FULL_ADDRESS_Msk = 0x10
	// Bit FULL_ADDRESS.
	TRACE_CONFIG_FULL_ADDRESS = 0x10
	// Position of IMPLICIT_EXCEPT field.
	TRACE_CONFIG_IMPLICIT_EXCEPT_Pos = 0x5
	// Bit mask of IMPLICIT_EXCEPT field.
	TRACE_CONFIG_IMPLICIT_EXCEPT_Msk = 0x20
	// Bit IMPLICIT_EXCEPT.
	TRACE_CONFIG_IMPLICIT_EXCEPT = 0x20

	// FILTER_CONTROL: filter control register
	// Position of FILTER_EN field.
	TRACE_FILTER_CONTROL_FILTER_EN_Pos = 0x0
	// Bit mask of FILTER_EN field.
	TRACE_FILTER_CONTROL_FILTER_EN_Msk = 0x1
	// Bit FILTER_EN.
	TRACE_FILTER_CONTROL_FILTER_EN = 0x1
	// Position of MATCH_COMP field.
	TRACE_FILTER_CONTROL_MATCH_COMP_Pos = 0x1
	// Bit mask of MATCH_COMP field.
	TRACE_FILTER_CONTROL_MATCH_COMP_Msk = 0x2
	// Bit MATCH_COMP.
	TRACE_FILTER_CONTROL_MATCH_COMP = 0x2
	// Position of MATCH_PRIVILEGE field.
	TRACE_FILTER_CONTROL_MATCH_PRIVILEGE_Pos = 0x2
	// Bit mask of MATCH_PRIVILEGE field.
	TRACE_FILTER_CONTROL_MATCH_PRIVILEGE_Msk = 0x4
	// Bit MATCH_PRIVILEGE.
	TRACE_FILTER_CONTROL_MATCH_PRIVILEGE = 0x4
	// Position of MATCH_ECAUSE field.
	TRACE_FILTER_CONTROL_MATCH_ECAUSE_Pos = 0x3
	// Bit mask of MATCH_ECAUSE field.
	TRACE_FILTER_CONTROL_MATCH_ECAUSE_Msk = 0x8
	// Bit MATCH_ECAUSE.
	TRACE_FILTER_CONTROL_MATCH_ECAUSE = 0x8
	// Position of MATCH_INTERRUPT field.
	TRACE_FILTER_CONTROL_MATCH_INTERRUPT_Pos = 0x4
	// Bit mask of MATCH_INTERRUPT field.
	TRACE_FILTER_CONTROL_MATCH_INTERRUPT_Msk = 0x10
	// Bit MATCH_INTERRUPT.
	TRACE_FILTER_CONTROL_MATCH_INTERRUPT = 0x10

	// FILTER_MATCH_CONTROL: filter match control register
	// Position of MATCH_CHOICE_PRIVILEGE field.
	TRACE_FILTER_MATCH_CONTROL_MATCH_CHOICE_PRIVILEGE_Pos = 0x0
	// Bit mask of MATCH_CHOICE_PRIVILEGE field.
	TRACE_FILTER_MATCH_CONTROL_MATCH_CHOICE_PRIVILEGE_Msk = 0x1
	// Bit MATCH_CHOICE_PRIVILEGE.
	TRACE_FILTER_MATCH_CONTROL_MATCH_CHOICE_PRIVILEGE = 0x1
	// Position of MATCH_VALUE_INTERRUPT field.
	TRACE_FILTER_MATCH_CONTROL_MATCH_VALUE_INTERRUPT_Pos = 0x1
	// Bit mask of MATCH_VALUE_INTERRUPT field.
	TRACE_FILTER_MATCH_CONTROL_MATCH_VALUE_INTERRUPT_Msk = 0x2
	// Bit MATCH_VALUE_INTERRUPT.
	TRACE_FILTER_MATCH_CONTROL_MATCH_VALUE_INTERRUPT = 0x2
	// Position of MATCH_CHOICE_ECAUSE field.
	TRACE_FILTER_MATCH_CONTROL_MATCH_CHOICE_ECAUSE_Pos = 0x2
	// Bit mask of MATCH_CHOICE_ECAUSE field.
	TRACE_FILTER_MATCH_CONTROL_MATCH_CHOICE_ECAUSE_Msk = 0xfc

	// FILTER_COMPARATOR_CONTROL: filter comparator match control register
	// Position of P_INPUT field.
	TRACE_FILTER_COMPARATOR_CONTROL_P_INPUT_Pos = 0x0
	// Bit mask of P_INPUT field.
	TRACE_FILTER_COMPARATOR_CONTROL_P_INPUT_Msk = 0x1
	// Bit P_INPUT.
	TRACE_FILTER_COMPARATOR_CONTROL_P_INPUT = 0x1
	// Position of P_FUNCTION field.
	TRACE_FILTER_COMPARATOR_CONTROL_P_FUNCTION_Pos = 0x2
	// Bit mask of P_FUNCTION field.
	TRACE_FILTER_COMPARATOR_CONTROL_P_FUNCTION_Msk = 0x1c
	// Position of P_NOTIFY field.
	TRACE_FILTER_COMPARATOR_CONTROL_P_NOTIFY_Pos = 0x5
	// Bit mask of P_NOTIFY field.
	TRACE_FILTER_COMPARATOR_CONTROL_P_NOTIFY_Msk = 0x20
	// Bit P_NOTIFY.
	TRACE_FILTER_COMPARATOR_CONTROL_P_NOTIFY = 0x20
	// Position of S_INPUT field.
	TRACE_FILTER_COMPARATOR_CONTROL_S_INPUT_Pos = 0x8
	// Bit mask of S_INPUT field.
	TRACE_FILTER_COMPARATOR_CONTROL_S_INPUT_Msk = 0x100
	// Bit S_INPUT.
	TRACE_FILTER_COMPARATOR_CONTROL_S_INPUT = 0x100
	// Position of S_FUNCTION field.
	TRACE_FILTER_COMPARATOR_CONTROL_S_FUNCTION_Pos = 0xa
	// Bit mask of S_FUNCTION field.
	TRACE_FILTER_COMPARATOR_CONTROL_S_FUNCTION_Msk = 0x1c00
	// Position of S_NOTIFY field.
	TRACE_FILTER_COMPARATOR_CONTROL_S_NOTIFY_Pos = 0xd
	// Bit mask of S_NOTIFY field.
	TRACE_FILTER_COMPARATOR_CONTROL_S_NOTIFY_Msk = 0x2000
	// Bit S_NOTIFY.
	TRACE_FILTER_COMPARATOR_CONTROL_S_NOTIFY = 0x2000
	// Position of MATCH_MODE field.
	TRACE_FILTER_COMPARATOR_CONTROL_MATCH_MODE_Pos = 0x10
	// Bit mask of MATCH_MODE field.
	TRACE_FILTER_COMPARATOR_CONTROL_MATCH_MODE_Msk = 0x30000

	// FILTER_P_COMPARATOR_MATCH: primary comparator match value
	// Position of P_MATCH field.
	TRACE_FILTER_P_COMPARATOR_MATCH_P_MATCH_Pos = 0x0
	// Bit mask of P_MATCH field.
	TRACE_FILTER_P_COMPARATOR_MATCH_P_MATCH_Msk = 0xffffffff

	// FILTER_S_COMPARATOR_MATCH: secondary comparator match value
	// Position of S_MATCH field.
	TRACE_FILTER_S_COMPARATOR_MATCH_S_MATCH_Pos = 0x0
	// Bit mask of S_MATCH field.
	TRACE_FILTER_S_COMPARATOR_MATCH_S_MATCH_Msk = 0xffffffff

	// RESYNC_PROLONGED: resync configuration register
	// Position of RESYNC_PROLONGED field.
	TRACE_RESYNC_PROLONGED_RESYNC_PROLONGED_Pos = 0x0
	// Bit mask of RESYNC_PROLONGED field.
	TRACE_RESYNC_PROLONGED_RESYNC_PROLONGED_Msk = 0xffffff
	// Position of RESYNC_MODE field.
	TRACE_RESYNC_PROLONGED_RESYNC_MODE_Pos = 0x18
	// Bit mask of RESYNC_MODE field.
	TRACE_RESYNC_PROLONGED_RESYNC_MODE_Msk = 0x3000000

	// AHB_CONFIG: AHB config register
	// Position of HBURST field.
	TRACE_AHB_CONFIG_HBURST_Pos = 0x0
	// Bit mask of HBURST field.
	TRACE_AHB_CONFIG_HBURST_Msk = 0x7
	// Position of MAX_INCR field.
	TRACE_AHB_CONFIG_MAX_INCR_Pos = 0x3
	// Bit mask of MAX_INCR field.
	TRACE_AHB_CONFIG_MAX_INCR_Msk = 0x38

	// CLOCK_GATE: Clock gate control register
	// Position of CLK_EN field.
	TRACE_CLOCK_GATE_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	TRACE_CLOCK_GATE_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	TRACE_CLOCK_GATE_CLK_EN = 0x1

	// DATE: Version control register
	// Position of DATE field.
	TRACE_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	TRACE_DATE_DATE_Msk = 0xfffffff
)

// Constants for LP_TSENS: Low-power Temperature Sensor
const (
	// CTRL: Tsens configuration.
	// Position of OUT field.
	TSENS_CTRL_OUT_Pos = 0x0
	// Bit mask of OUT field.
	TSENS_CTRL_OUT_Msk = 0xff
	// Position of READY field.
	TSENS_CTRL_READY_Pos = 0x8
	// Bit mask of READY field.
	TSENS_CTRL_READY_Msk = 0x100
	// Bit READY.
	TSENS_CTRL_READY = 0x100
	// Position of SAMPLE_EN field.
	TSENS_CTRL_SAMPLE_EN_Pos = 0x9
	// Bit mask of SAMPLE_EN field.
	TSENS_CTRL_SAMPLE_EN_Msk = 0x200
	// Bit SAMPLE_EN.
	TSENS_CTRL_SAMPLE_EN = 0x200
	// Position of WAKEUP_MASK field.
	TSENS_CTRL_WAKEUP_MASK_Pos = 0xa
	// Bit mask of WAKEUP_MASK field.
	TSENS_CTRL_WAKEUP_MASK_Msk = 0x400
	// Bit WAKEUP_MASK.
	TSENS_CTRL_WAKEUP_MASK = 0x400
	// Position of INT_EN field.
	TSENS_CTRL_INT_EN_Pos = 0xc
	// Bit mask of INT_EN field.
	TSENS_CTRL_INT_EN_Msk = 0x1000
	// Bit INT_EN.
	TSENS_CTRL_INT_EN = 0x1000
	// Position of IN_INV field.
	TSENS_CTRL_IN_INV_Pos = 0xd
	// Bit mask of IN_INV field.
	TSENS_CTRL_IN_INV_Msk = 0x2000
	// Bit IN_INV.
	TSENS_CTRL_IN_INV = 0x2000
	// Position of CLK_DIV field.
	TSENS_CTRL_CLK_DIV_Pos = 0xe
	// Bit mask of CLK_DIV field.
	TSENS_CTRL_CLK_DIV_Msk = 0x3fc000
	// Position of POWER_UP field.
	TSENS_CTRL_POWER_UP_Pos = 0x16
	// Bit mask of POWER_UP field.
	TSENS_CTRL_POWER_UP_Msk = 0x400000
	// Bit POWER_UP.
	TSENS_CTRL_POWER_UP = 0x400000
	// Position of POWER_UP_FORCE field.
	TSENS_CTRL_POWER_UP_FORCE_Pos = 0x17
	// Bit mask of POWER_UP_FORCE field.
	TSENS_CTRL_POWER_UP_FORCE_Msk = 0x800000
	// Bit POWER_UP_FORCE.
	TSENS_CTRL_POWER_UP_FORCE = 0x800000

	// CTRL2: Tsens configuration.
	// Position of XPD_WAIT field.
	TSENS_CTRL2_XPD_WAIT_Pos = 0x0
	// Bit mask of XPD_WAIT field.
	TSENS_CTRL2_XPD_WAIT_Msk = 0xfff
	// Position of XPD_FORCE field.
	TSENS_CTRL2_XPD_FORCE_Pos = 0xc
	// Bit mask of XPD_FORCE field.
	TSENS_CTRL2_XPD_FORCE_Msk = 0x3000
	// Position of CLK_INV field.
	TSENS_CTRL2_CLK_INV_Pos = 0xe
	// Bit mask of CLK_INV field.
	TSENS_CTRL2_CLK_INV_Msk = 0x4000
	// Bit CLK_INV.
	TSENS_CTRL2_CLK_INV = 0x4000

	// INT_RAW: Tsens interrupt raw registers.
	// Position of COCPU_TSENS_WAKE_INT_RAW field.
	TSENS_INT_RAW_COCPU_TSENS_WAKE_INT_RAW_Pos = 0x0
	// Bit mask of COCPU_TSENS_WAKE_INT_RAW field.
	TSENS_INT_RAW_COCPU_TSENS_WAKE_INT_RAW_Msk = 0x1
	// Bit COCPU_TSENS_WAKE_INT_RAW.
	TSENS_INT_RAW_COCPU_TSENS_WAKE_INT_RAW = 0x1

	// INT_ST: Tsens interrupt status registers.
	// Position of COCPU_TSENS_WAKE_INT_ST field.
	TSENS_INT_ST_COCPU_TSENS_WAKE_INT_ST_Pos = 0x0
	// Bit mask of COCPU_TSENS_WAKE_INT_ST field.
	TSENS_INT_ST_COCPU_TSENS_WAKE_INT_ST_Msk = 0x1
	// Bit COCPU_TSENS_WAKE_INT_ST.
	TSENS_INT_ST_COCPU_TSENS_WAKE_INT_ST = 0x1

	// INT_ENA: Tsens interrupt enable registers.
	// Position of COCPU_TSENS_WAKE_INT_ENA field.
	TSENS_INT_ENA_COCPU_TSENS_WAKE_INT_ENA_Pos = 0x0
	// Bit mask of COCPU_TSENS_WAKE_INT_ENA field.
	TSENS_INT_ENA_COCPU_TSENS_WAKE_INT_ENA_Msk = 0x1
	// Bit COCPU_TSENS_WAKE_INT_ENA.
	TSENS_INT_ENA_COCPU_TSENS_WAKE_INT_ENA = 0x1

	// INT_CLR: Tsens interrupt clear registers.
	// Position of COCPU_TSENS_WAKE_INT_CLR field.
	TSENS_INT_CLR_COCPU_TSENS_WAKE_INT_CLR_Pos = 0x0
	// Bit mask of COCPU_TSENS_WAKE_INT_CLR field.
	TSENS_INT_CLR_COCPU_TSENS_WAKE_INT_CLR_Msk = 0x1
	// Bit COCPU_TSENS_WAKE_INT_CLR.
	TSENS_INT_CLR_COCPU_TSENS_WAKE_INT_CLR = 0x1

	// CLK_CONF: Tsens regbank configuration registers.
	// Position of CLK_EN field.
	TSENS_CLK_CONF_CLK_EN_Pos = 0x0
	// Bit mask of CLK_EN field.
	TSENS_CLK_CONF_CLK_EN_Msk = 0x1
	// Bit CLK_EN.
	TSENS_CLK_CONF_CLK_EN = 0x1

	// INT_ENA_W1TS: Tsens wakeup interrupt enable assert.
	// Position of COCPU_TSENS_WAKE_INT_ENA_W1TS field.
	TSENS_INT_ENA_W1TS_COCPU_TSENS_WAKE_INT_ENA_W1TS_Pos = 0x0
	// Bit mask of COCPU_TSENS_WAKE_INT_ENA_W1TS field.
	TSENS_INT_ENA_W1TS_COCPU_TSENS_WAKE_INT_ENA_W1TS_Msk = 0x1
	// Bit COCPU_TSENS_WAKE_INT_ENA_W1TS.
	TSENS_INT_ENA_W1TS_COCPU_TSENS_WAKE_INT_ENA_W1TS = 0x1

	// INT_ENA_W1TC: Tsens wakeup interrupt enable deassert.
	// Position of COCPU_TSENS_WAKE_INT_ENA_W1TC field.
	TSENS_INT_ENA_W1TC_COCPU_TSENS_WAKE_INT_ENA_W1TC_Pos = 0x0
	// Bit mask of COCPU_TSENS_WAKE_INT_ENA_W1TC field.
	TSENS_INT_ENA_W1TC_COCPU_TSENS_WAKE_INT_ENA_W1TC_Msk = 0x1
	// Bit COCPU_TSENS_WAKE_INT_ENA_W1TC.
	TSENS_INT_ENA_W1TC_COCPU_TSENS_WAKE_INT_ENA_W1TC = 0x1

	// WAKEUP_CTRL: Tsens wakeup control registers.
	// Position of WAKEUP_TH_LOW field.
	TSENS_WAKEUP_CTRL_WAKEUP_TH_LOW_Pos = 0x0
	// Bit mask of WAKEUP_TH_LOW field.
	TSENS_WAKEUP_CTRL_WAKEUP_TH_LOW_Msk = 0xff
	// Position of WAKEUP_TH_HIGH field.
	TSENS_WAKEUP_CTRL_WAKEUP_TH_HIGH_Pos = 0xe
	// Bit mask of WAKEUP_TH_HIGH field.
	TSENS_WAKEUP_CTRL_WAKEUP_TH_HIGH_Msk = 0x3fc000
	// Position of WAKEUP_OVER_UPPER_TH field.
	TSENS_WAKEUP_CTRL_WAKEUP_OVER_UPPER_TH_Pos = 0x1d
	// Bit mask of WAKEUP_OVER_UPPER_TH field.
	TSENS_WAKEUP_CTRL_WAKEUP_OVER_UPPER_TH_Msk = 0x20000000
	// Bit WAKEUP_OVER_UPPER_TH.
	TSENS_WAKEUP_CTRL_WAKEUP_OVER_UPPER_TH = 0x20000000
	// Position of WAKEUP_EN field.
	TSENS_WAKEUP_CTRL_WAKEUP_EN_Pos = 0x1e
	// Bit mask of WAKEUP_EN field.
	TSENS_WAKEUP_CTRL_WAKEUP_EN_Msk = 0x40000000
	// Bit WAKEUP_EN.
	TSENS_WAKEUP_CTRL_WAKEUP_EN = 0x40000000
	// Position of WAKEUP_MODE field.
	TSENS_WAKEUP_CTRL_WAKEUP_MODE_Pos = 0x1f
	// Bit mask of WAKEUP_MODE field.
	TSENS_WAKEUP_CTRL_WAKEUP_MODE_Msk = 0x80000000
	// Bit WAKEUP_MODE.
	TSENS_WAKEUP_CTRL_WAKEUP_MODE = 0x80000000

	// SAMPLE_RATE: Hardware automatic sampling control registers.
	// Position of SAMPLE_RATE field.
	TSENS_SAMPLE_RATE_SAMPLE_RATE_Pos = 0x0
	// Bit mask of SAMPLE_RATE field.
	TSENS_SAMPLE_RATE_SAMPLE_RATE_Msk = 0xffff

	// RND_ECO_LOW: N/A
	// Position of RND_ECO_LOW field.
	TSENS_RND_ECO_LOW_RND_ECO_LOW_Pos = 0x0
	// Bit mask of RND_ECO_LOW field.
	TSENS_RND_ECO_LOW_RND_ECO_LOW_Msk = 0xffffffff

	// RND_ECO_HIGH: N/A
	// Position of RND_ECO_HIGH field.
	TSENS_RND_ECO_HIGH_RND_ECO_HIGH_Pos = 0x0
	// Bit mask of RND_ECO_HIGH field.
	TSENS_RND_ECO_HIGH_RND_ECO_HIGH_Msk = 0xffffffff

	// RND_ECO_CS: N/A
	// Position of RND_ECO_EN field.
	TSENS_RND_ECO_CS_RND_ECO_EN_Pos = 0x0
	// Bit mask of RND_ECO_EN field.
	TSENS_RND_ECO_CS_RND_ECO_EN_Msk = 0x1
	// Bit RND_ECO_EN.
	TSENS_RND_ECO_CS_RND_ECO_EN = 0x1
	// Position of RND_ECO_RESULT field.
	TSENS_RND_ECO_CS_RND_ECO_RESULT_Pos = 0x1
	// Bit mask of RND_ECO_RESULT field.
	TSENS_RND_ECO_CS_RND_ECO_RESULT_Msk = 0x2
	// Bit RND_ECO_RESULT.
	TSENS_RND_ECO_CS_RND_ECO_RESULT = 0x2
)

// Constants for TWAI0: Two-Wire Automotive Interface
const (
	// MODE: TWAI mode register.
	// Position of RESET_MODE field.
	TWAI_MODE_RESET_MODE_Pos = 0x0
	// Bit mask of RESET_MODE field.
	TWAI_MODE_RESET_MODE_Msk = 0x1
	// Bit RESET_MODE.
	TWAI_MODE_RESET_MODE = 0x1
	// Position of LISTEN_ONLY_MODE field.
	TWAI_MODE_LISTEN_ONLY_MODE_Pos = 0x1
	// Bit mask of LISTEN_ONLY_MODE field.
	TWAI_MODE_LISTEN_ONLY_MODE_Msk = 0x2
	// Bit LISTEN_ONLY_MODE.
	TWAI_MODE_LISTEN_ONLY_MODE = 0x2
	// Position of SELF_TEST_MODE field.
	TWAI_MODE_SELF_TEST_MODE_Pos = 0x2
	// Bit mask of SELF_TEST_MODE field.
	TWAI_MODE_SELF_TEST_MODE_Msk = 0x4
	// Bit SELF_TEST_MODE.
	TWAI_MODE_SELF_TEST_MODE = 0x4
	// Position of ACCEPTANCE_FILTER_MODE field.
	TWAI_MODE_ACCEPTANCE_FILTER_MODE_Pos = 0x3
	// Bit mask of ACCEPTANCE_FILTER_MODE field.
	TWAI_MODE_ACCEPTANCE_FILTER_MODE_Msk = 0x8
	// Bit ACCEPTANCE_FILTER_MODE.
	TWAI_MODE_ACCEPTANCE_FILTER_MODE = 0x8

	// CMD: TWAI command register.
	// Position of TX_REQUEST field.
	TWAI_CMD_TX_REQUEST_Pos = 0x0
	// Bit mask of TX_REQUEST field.
	TWAI_CMD_TX_REQUEST_Msk = 0x1
	// Bit TX_REQUEST.
	TWAI_CMD_TX_REQUEST = 0x1
	// Position of ABORT_TX field.
	TWAI_CMD_ABORT_TX_Pos = 0x1
	// Bit mask of ABORT_TX field.
	TWAI_CMD_ABORT_TX_Msk = 0x2
	// Bit ABORT_TX.
	TWAI_CMD_ABORT_TX = 0x2
	// Position of RELEASE_BUFFER field.
	TWAI_CMD_RELEASE_BUFFER_Pos = 0x2
	// Bit mask of RELEASE_BUFFER field.
	TWAI_CMD_RELEASE_BUFFER_Msk = 0x4
	// Bit RELEASE_BUFFER.
	TWAI_CMD_RELEASE_BUFFER = 0x4
	// Position of CLEAR_DATA_OVERRUN field.
	TWAI_CMD_CLEAR_DATA_OVERRUN_Pos = 0x3
	// Bit mask of CLEAR_DATA_OVERRUN field.
	TWAI_CMD_CLEAR_DATA_OVERRUN_Msk = 0x8
	// Bit CLEAR_DATA_OVERRUN.
	TWAI_CMD_CLEAR_DATA_OVERRUN = 0x8
	// Position of SELF_RX_REQUEST field.
	TWAI_CMD_SELF_RX_REQUEST_Pos = 0x4
	// Bit mask of SELF_RX_REQUEST field.
	TWAI_CMD_SELF_RX_REQUEST_Msk = 0x10
	// Bit SELF_RX_REQUEST.
	TWAI_CMD_SELF_RX_REQUEST = 0x10

	// STATUS: TWAI status register.
	// Position of RECEIVE_BUFFER field.
	TWAI_STATUS_RECEIVE_BUFFER_Pos = 0x0
	// Bit mask of RECEIVE_BUFFER field.
	TWAI_STATUS_RECEIVE_BUFFER_Msk = 0x1
	// Bit RECEIVE_BUFFER.
	TWAI_STATUS_RECEIVE_BUFFER = 0x1
	// Position of OVERRUN field.
	TWAI_STATUS_OVERRUN_Pos = 0x1
	// Bit mask of OVERRUN field.
	TWAI_STATUS_OVERRUN_Msk = 0x2
	// Bit OVERRUN.
	TWAI_STATUS_OVERRUN = 0x2
	// Position of TRANSMIT_BUFFER field.
	TWAI_STATUS_TRANSMIT_BUFFER_Pos = 0x2
	// Bit mask of TRANSMIT_BUFFER field.
	TWAI_STATUS_TRANSMIT_BUFFER_Msk = 0x4
	// Bit TRANSMIT_BUFFER.
	TWAI_STATUS_TRANSMIT_BUFFER = 0x4
	// Position of TRANSMISSION_COMPLETE field.
	TWAI_STATUS_TRANSMISSION_COMPLETE_Pos = 0x3
	// Bit mask of TRANSMISSION_COMPLETE field.
	TWAI_STATUS_TRANSMISSION_COMPLETE_Msk = 0x8
	// Bit TRANSMISSION_COMPLETE.
	TWAI_STATUS_TRANSMISSION_COMPLETE = 0x8
	// Position of RECEIVE field.
	TWAI_STATUS_RECEIVE_Pos = 0x4
	// Bit mask of RECEIVE field.
	TWAI_STATUS_RECEIVE_Msk = 0x10
	// Bit RECEIVE.
	TWAI_STATUS_RECEIVE = 0x10
	// Position of TRANSMIT field.
	TWAI_STATUS_TRANSMIT_Pos = 0x5
	// Bit mask of TRANSMIT field.
	TWAI_STATUS_TRANSMIT_Msk = 0x20
	// Bit TRANSMIT.
	TWAI_STATUS_TRANSMIT = 0x20
	// Position of ERR field.
	TWAI_STATUS_ERR_Pos = 0x6
	// Bit mask of ERR field.
	TWAI_STATUS_ERR_Msk = 0x40
	// Bit ERR.
	TWAI_STATUS_ERR = 0x40
	// Position of NODE_BUS_OFF field.
	TWAI_STATUS_NODE_BUS_OFF_Pos = 0x7
	// Bit mask of NODE_BUS_OFF field.
	TWAI_STATUS_NODE_BUS_OFF_Msk = 0x80
	// Bit NODE_BUS_OFF.
	TWAI_STATUS_NODE_BUS_OFF = 0x80
	// Position of MISS field.
	TWAI_STATUS_MISS_Pos = 0x8
	// Bit mask of MISS field.
	TWAI_STATUS_MISS_Msk = 0x100
	// Bit MISS.
	TWAI_STATUS_MISS = 0x100

	// INTERRUPT: Interrupt signals' register.
	// Position of RECEIVE_INT_ST field.
	TWAI_INTERRUPT_RECEIVE_INT_ST_Pos = 0x0
	// Bit mask of RECEIVE_INT_ST field.
	TWAI_INTERRUPT_RECEIVE_INT_ST_Msk = 0x1
	// Bit RECEIVE_INT_ST.
	TWAI_INTERRUPT_RECEIVE_INT_ST = 0x1
	// Position of TRANSMIT_INT_ST field.
	TWAI_INTERRUPT_TRANSMIT_INT_ST_Pos = 0x1
	// Bit mask of TRANSMIT_INT_ST field.
	TWAI_INTERRUPT_TRANSMIT_INT_ST_Msk = 0x2
	// Bit TRANSMIT_INT_ST.
	TWAI_INTERRUPT_TRANSMIT_INT_ST = 0x2
	// Position of ERR_WARNING_INT_ST field.
	TWAI_INTERRUPT_ERR_WARNING_INT_ST_Pos = 0x2
	// Bit mask of ERR_WARNING_INT_ST field.
	TWAI_INTERRUPT_ERR_WARNING_INT_ST_Msk = 0x4
	// Bit ERR_WARNING_INT_ST.
	TWAI_INTERRUPT_ERR_WARNING_INT_ST = 0x4
	// Position of DATA_OVERRUN_INT_ST field.
	TWAI_INTERRUPT_DATA_OVERRUN_INT_ST_Pos = 0x3
	// Bit mask of DATA_OVERRUN_INT_ST field.
	TWAI_INTERRUPT_DATA_OVERRUN_INT_ST_Msk = 0x8
	// Bit DATA_OVERRUN_INT_ST.
	TWAI_INTERRUPT_DATA_OVERRUN_INT_ST = 0x8
	// Position of TS_COUNTER_OVFL_INT_ST field.
	TWAI_INTERRUPT_TS_COUNTER_OVFL_INT_ST_Pos = 0x4
	// Bit mask of TS_COUNTER_OVFL_INT_ST field.
	TWAI_INTERRUPT_TS_COUNTER_OVFL_INT_ST_Msk = 0x10
	// Bit TS_COUNTER_OVFL_INT_ST.
	TWAI_INTERRUPT_TS_COUNTER_OVFL_INT_ST = 0x10
	// Position of ERR_PASSIVE_INT_ST field.
	TWAI_INTERRUPT_ERR_PASSIVE_INT_ST_Pos = 0x5
	// Bit mask of ERR_PASSIVE_INT_ST field.
	TWAI_INTERRUPT_ERR_PASSIVE_INT_ST_Msk = 0x20
	// Bit ERR_PASSIVE_INT_ST.
	TWAI_INTERRUPT_ERR_PASSIVE_INT_ST = 0x20
	// Position of ARBITRATION_LOST_INT_ST field.
	TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST_Pos = 0x6
	// Bit mask of ARBITRATION_LOST_INT_ST field.
	TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST_Msk = 0x40
	// Bit ARBITRATION_LOST_INT_ST.
	TWAI_INTERRUPT_ARBITRATION_LOST_INT_ST = 0x40
	// Position of BUS_ERR_INT_ST field.
	TWAI_INTERRUPT_BUS_ERR_INT_ST_Pos = 0x7
	// Bit mask of BUS_ERR_INT_ST field.
	TWAI_INTERRUPT_BUS_ERR_INT_ST_Msk = 0x80
	// Bit BUS_ERR_INT_ST.
	TWAI_INTERRUPT_BUS_ERR_INT_ST = 0x80
	// Position of IDLE_INT_ST field.
	TWAI_INTERRUPT_IDLE_INT_ST_Pos = 0x8
	// Bit mask of IDLE_INT_ST field.
	TWAI_INTERRUPT_IDLE_INT_ST_Msk = 0x100
	// Bit IDLE_INT_ST.
	TWAI_INTERRUPT_IDLE_INT_ST = 0x100

	// INTERRUPT_ENABLE: Interrupt enable register.
	// Position of EXT_RECEIVE_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA_Pos = 0x0
	// Bit mask of EXT_RECEIVE_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA_Msk = 0x1
	// Bit EXT_RECEIVE_INT_ENA.
	TWAI_INTERRUPT_ENABLE_EXT_RECEIVE_INT_ENA = 0x1
	// Position of EXT_TRANSMIT_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA_Pos = 0x1
	// Bit mask of EXT_TRANSMIT_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA_Msk = 0x2
	// Bit EXT_TRANSMIT_INT_ENA.
	TWAI_INTERRUPT_ENABLE_EXT_TRANSMIT_INT_ENA = 0x2
	// Position of EXT_ERR_WARNING_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA_Pos = 0x2
	// Bit mask of EXT_ERR_WARNING_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA_Msk = 0x4
	// Bit EXT_ERR_WARNING_INT_ENA.
	TWAI_INTERRUPT_ENABLE_EXT_ERR_WARNING_INT_ENA = 0x4
	// Position of EXT_DATA_OVERRUN_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA_Pos = 0x3
	// Bit mask of EXT_DATA_OVERRUN_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA_Msk = 0x8
	// Bit EXT_DATA_OVERRUN_INT_ENA.
	TWAI_INTERRUPT_ENABLE_EXT_DATA_OVERRUN_INT_ENA = 0x8
	// Position of TS_COUNTER_OVFL_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_TS_COUNTER_OVFL_INT_ENA_Pos = 0x4
	// Bit mask of TS_COUNTER_OVFL_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_TS_COUNTER_OVFL_INT_ENA_Msk = 0x10
	// Bit TS_COUNTER_OVFL_INT_ENA.
	TWAI_INTERRUPT_ENABLE_TS_COUNTER_OVFL_INT_ENA = 0x10
	// Position of ERR_PASSIVE_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA_Pos = 0x5
	// Bit mask of ERR_PASSIVE_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA_Msk = 0x20
	// Bit ERR_PASSIVE_INT_ENA.
	TWAI_INTERRUPT_ENABLE_ERR_PASSIVE_INT_ENA = 0x20
	// Position of ARBITRATION_LOST_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA_Pos = 0x6
	// Bit mask of ARBITRATION_LOST_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA_Msk = 0x40
	// Bit ARBITRATION_LOST_INT_ENA.
	TWAI_INTERRUPT_ENABLE_ARBITRATION_LOST_INT_ENA = 0x40
	// Position of BUS_ERR_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA_Pos = 0x7
	// Bit mask of BUS_ERR_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA_Msk = 0x80
	// Bit BUS_ERR_INT_ENA.
	TWAI_INTERRUPT_ENABLE_BUS_ERR_INT_ENA = 0x80
	// Position of IDLE_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA_Pos = 0x8
	// Bit mask of IDLE_INT_ENA field.
	TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA_Msk = 0x100
	// Bit IDLE_INT_ENA.
	TWAI_INTERRUPT_ENABLE_IDLE_INT_ENA = 0x100

	// BUS_TIMING_0: Bit timing configuration register 0.
	// Position of BAUD_PRESC field.
	TWAI_BUS_TIMING_0_BAUD_PRESC_Pos = 0x0
	// Bit mask of BAUD_PRESC field.
	TWAI_BUS_TIMING_0_BAUD_PRESC_Msk = 0x3fff
	// Position of SYNC_JUMP_WIDTH field.
	TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Pos = 0xe
	// Bit mask of SYNC_JUMP_WIDTH field.
	TWAI_BUS_TIMING_0_SYNC_JUMP_WIDTH_Msk = 0xc000

	// BUS_TIMING_1: Bit timing configuration register 1.
	// Position of TIME_SEGMENT1 field.
	TWAI_BUS_TIMING_1_TIME_SEGMENT1_Pos = 0x0
	// Bit mask of TIME_SEGMENT1 field.
	TWAI_BUS_TIMING_1_TIME_SEGMENT1_Msk = 0xf
	// Position of TIME_SEGMENT2 field.
	TWAI_BUS_TIMING_1_TIME_SEGMENT2_Pos = 0x4
	// Bit mask of TIME_SEGMENT2 field.
	TWAI_BUS_TIMING_1_TIME_SEGMENT2_Msk = 0x70
	// Position of TIME_SAMPLING field.
	TWAI_BUS_TIMING_1_TIME_SAMPLING_Pos = 0x7
	// Bit mask of TIME_SAMPLING field.
	TWAI_BUS_TIMING_1_TIME_SAMPLING_Msk = 0x80
	// Bit TIME_SAMPLING.
	TWAI_BUS_TIMING_1_TIME_SAMPLING = 0x80

	// ARB_LOST_CAP: TWAI arbiter lost capture register.
	// Position of ARBITRATION_LOST_CAPTURE field.
	TWAI_ARB_LOST_CAP_ARBITRATION_LOST_CAPTURE_Pos = 0x0
	// Bit mask of ARBITRATION_LOST_CAPTURE field.
	TWAI_ARB_LOST_CAP_ARBITRATION_LOST_CAPTURE_Msk = 0x1f

	// ERR_CODE_CAP: TWAI error info capture register.
	// Position of ERR_CAPTURE_CODE_SEGMENT field.
	TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT_Pos = 0x0
	// Bit mask of ERR_CAPTURE_CODE_SEGMENT field.
	TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_SEGMENT_Msk = 0x1f
	// Position of ERR_CAPTURE_CODE_DIRECTION field.
	TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION_Pos = 0x5
	// Bit mask of ERR_CAPTURE_CODE_DIRECTION field.
	TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION_Msk = 0x20
	// Bit ERR_CAPTURE_CODE_DIRECTION.
	TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_DIRECTION = 0x20
	// Position of ERR_CAPTURE_CODE_TYPE field.
	TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE_Pos = 0x6
	// Bit mask of ERR_CAPTURE_CODE_TYPE field.
	TWAI_ERR_CODE_CAP_ERR_CAPTURE_CODE_TYPE_Msk = 0xc0

	// ERR_WARNING_LIMIT: TWAI error threshold configuration register.
	// Position of ERR_WARNING_LIMIT field.
	TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Pos = 0x0
	// Bit mask of ERR_WARNING_LIMIT field.
	TWAI_ERR_WARNING_LIMIT_ERR_WARNING_LIMIT_Msk = 0xff

	// RX_ERR_CNT: Rx error counter register.
	// Position of RX_ERR_CNT field.
	TWAI_RX_ERR_CNT_RX_ERR_CNT_Pos = 0x0
	// Bit mask of RX_ERR_CNT field.
	TWAI_RX_ERR_CNT_RX_ERR_CNT_Msk = 0xff

	// TX_ERR_CNT: Tx error counter register.
	// Position of TX_ERR_CNT field.
	TWAI_TX_ERR_CNT_TX_ERR_CNT_Pos = 0x0
	// Bit mask of TX_ERR_CNT field.
	TWAI_TX_ERR_CNT_TX_ERR_CNT_Msk = 0xff

	// DATA_0: Data register 0.
	// Position of DATA_0 field.
	TWAI_DATA_0_DATA_0_Pos = 0x0
	// Bit mask of DATA_0 field.
	TWAI_DATA_0_DATA_0_Msk = 0xff

	// DATA_1: Data register 1.
	// Position of DATA_1 field.
	TWAI_DATA_1_DATA_1_Pos = 0x0
	// Bit mask of DATA_1 field.
	TWAI_DATA_1_DATA_1_Msk = 0xff

	// DATA_2: Data register 2.
	// Position of DATA_2 field.
	TWAI_DATA_2_DATA_2_Pos = 0x0
	// Bit mask of DATA_2 field.
	TWAI_DATA_2_DATA_2_Msk = 0xff

	// DATA_3: Data register 3.
	// Position of DATA_3 field.
	TWAI_DATA_3_DATA_3_Pos = 0x0
	// Bit mask of DATA_3 field.
	TWAI_DATA_3_DATA_3_Msk = 0xff

	// DATA_4: Data register 4.
	// Position of DATA_4 field.
	TWAI_DATA_4_DATA_4_Pos = 0x0
	// Bit mask of DATA_4 field.
	TWAI_DATA_4_DATA_4_Msk = 0xff

	// DATA_5: Data register 5.
	// Position of DATA_5 field.
	TWAI_DATA_5_DATA_5_Pos = 0x0
	// Bit mask of DATA_5 field.
	TWAI_DATA_5_DATA_5_Msk = 0xff

	// DATA_6: Data register 6.
	// Position of DATA_6 field.
	TWAI_DATA_6_DATA_6_Pos = 0x0
	// Bit mask of DATA_6 field.
	TWAI_DATA_6_DATA_6_Msk = 0xff

	// DATA_7: Data register 7.
	// Position of DATA_7 field.
	TWAI_DATA_7_DATA_7_Pos = 0x0
	// Bit mask of DATA_7 field.
	TWAI_DATA_7_DATA_7_Msk = 0xff

	// DATA_8: Data register 8.
	// Position of DATA_8 field.
	TWAI_DATA_8_DATA_8_Pos = 0x0
	// Bit mask of DATA_8 field.
	TWAI_DATA_8_DATA_8_Msk = 0xff

	// DATA_9: Data register 9.
	// Position of DATA_9 field.
	TWAI_DATA_9_DATA_9_Pos = 0x0
	// Bit mask of DATA_9 field.
	TWAI_DATA_9_DATA_9_Msk = 0xff

	// DATA_10: Data register 10.
	// Position of DATA_10 field.
	TWAI_DATA_10_DATA_10_Pos = 0x0
	// Bit mask of DATA_10 field.
	TWAI_DATA_10_DATA_10_Msk = 0xff

	// DATA_11: Data register 11.
	// Position of DATA_11 field.
	TWAI_DATA_11_DATA_11_Pos = 0x0
	// Bit mask of DATA_11 field.
	TWAI_DATA_11_DATA_11_Msk = 0xff

	// DATA_12: Data register 12.
	// Position of DATA_12 field.
	TWAI_DATA_12_DATA_12_Pos = 0x0
	// Bit mask of DATA_12 field.
	TWAI_DATA_12_DATA_12_Msk = 0xff

	// RX_MESSAGE_COUNTER: Received message counter register.
	// Position of RX_MESSAGE_COUNTER field.
	TWAI_RX_MESSAGE_COUNTER_RX_MESSAGE_COUNTER_Pos = 0x0
	// Bit mask of RX_MESSAGE_COUNTER field.
	TWAI_RX_MESSAGE_COUNTER_RX_MESSAGE_COUNTER_Msk = 0x7f

	// CLOCK_DIVIDER: Clock divider register.
	// Position of CD field.
	TWAI_CLOCK_DIVIDER_CD_Pos = 0x0
	// Bit mask of CD field.
	TWAI_CLOCK_DIVIDER_CD_Msk = 0xff
	// Position of CLOCK_OFF field.
	TWAI_CLOCK_DIVIDER_CLOCK_OFF_Pos = 0x8
	// Bit mask of CLOCK_OFF field.
	TWAI_CLOCK_DIVIDER_CLOCK_OFF_Msk = 0x100
	// Bit CLOCK_OFF.
	TWAI_CLOCK_DIVIDER_CLOCK_OFF = 0x100

	// SW_STANDBY_CFG: Software configure standby pin directly.
	// Position of SW_STANDBY_EN field.
	TWAI_SW_STANDBY_CFG_SW_STANDBY_EN_Pos = 0x0
	// Bit mask of SW_STANDBY_EN field.
	TWAI_SW_STANDBY_CFG_SW_STANDBY_EN_Msk = 0x1
	// Bit SW_STANDBY_EN.
	TWAI_SW_STANDBY_CFG_SW_STANDBY_EN = 0x1
	// Position of SW_STANDBY_CLR field.
	TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR_Pos = 0x1
	// Bit mask of SW_STANDBY_CLR field.
	TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR_Msk = 0x2
	// Bit SW_STANDBY_CLR.
	TWAI_SW_STANDBY_CFG_SW_STANDBY_CLR = 0x2

	// HW_CFG: Hardware configure standby pin.
	// Position of HW_STANDBY_EN field.
	TWAI_HW_CFG_HW_STANDBY_EN_Pos = 0x0
	// Bit mask of HW_STANDBY_EN field.
	TWAI_HW_CFG_HW_STANDBY_EN_Msk = 0x1
	// Bit HW_STANDBY_EN.
	TWAI_HW_CFG_HW_STANDBY_EN = 0x1

	// HW_STANDBY_CNT: Configure standby counter.
	// Position of STANDBY_WAIT_CNT field.
	TWAI_HW_STANDBY_CNT_STANDBY_WAIT_CNT_Pos = 0x0
	// Bit mask of STANDBY_WAIT_CNT field.
	TWAI_HW_STANDBY_CNT_STANDBY_WAIT_CNT_Msk = 0xffffffff

	// IDLE_INTR_CNT: Configure idle interrupt counter.
	// Position of IDLE_INTR_CNT field.
	TWAI_IDLE_INTR_CNT_IDLE_INTR_CNT_Pos = 0x0
	// Bit mask of IDLE_INTR_CNT field.
	TWAI_IDLE_INTR_CNT_IDLE_INTR_CNT_Msk = 0xffffffff

	// ECO_CFG: ECO configuration register.
	// Position of RDN_ENA field.
	TWAI_ECO_CFG_RDN_ENA_Pos = 0x0
	// Bit mask of RDN_ENA field.
	TWAI_ECO_CFG_RDN_ENA_Msk = 0x1
	// Bit RDN_ENA.
	TWAI_ECO_CFG_RDN_ENA = 0x1
	// Position of RDN_RESULT field.
	TWAI_ECO_CFG_RDN_RESULT_Pos = 0x1
	// Bit mask of RDN_RESULT field.
	TWAI_ECO_CFG_RDN_RESULT_Msk = 0x2
	// Bit RDN_RESULT.
	TWAI_ECO_CFG_RDN_RESULT = 0x2

	// TIMESTAMP_DATA: Timestamp data register
	// Position of TIMESTAMP_DATA field.
	TWAI_TIMESTAMP_DATA_TIMESTAMP_DATA_Pos = 0x0
	// Bit mask of TIMESTAMP_DATA field.
	TWAI_TIMESTAMP_DATA_TIMESTAMP_DATA_Msk = 0xffffffff

	// TIMESTAMP_PRESCALER: Timestamp configuration register
	// Position of TS_DIV_NUM field.
	TWAI_TIMESTAMP_PRESCALER_TS_DIV_NUM_Pos = 0x0
	// Bit mask of TS_DIV_NUM field.
	TWAI_TIMESTAMP_PRESCALER_TS_DIV_NUM_Msk = 0xffff

	// TIMESTAMP_CFG: Timestamp configuration register
	// Position of TS_ENABLE field.
	TWAI_TIMESTAMP_CFG_TS_ENABLE_Pos = 0x0
	// Bit mask of TS_ENABLE field.
	TWAI_TIMESTAMP_CFG_TS_ENABLE_Msk = 0x1
	// Bit TS_ENABLE.
	TWAI_TIMESTAMP_CFG_TS_ENABLE = 0x1
)

// Constants for UART0: UART (Universal Asynchronous Receiver-Transmitter) Controller 0
const (
	// FIFO: FIFO data register
	// Position of RXFIFO_RD_BYTE field.
	UART_FIFO_RXFIFO_RD_BYTE_Pos = 0x0
	// Bit mask of RXFIFO_RD_BYTE field.
	UART_FIFO_RXFIFO_RD_BYTE_Msk = 0xff

	// INT_RAW: Raw interrupt status
	// Position of RXFIFO_FULL_INT_RAW field.
	UART_INT_RAW_RXFIFO_FULL_INT_RAW_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_RAW field.
	UART_INT_RAW_RXFIFO_FULL_INT_RAW_Msk = 0x1
	// Bit RXFIFO_FULL_INT_RAW.
	UART_INT_RAW_RXFIFO_FULL_INT_RAW = 0x1
	// Position of TXFIFO_EMPTY_INT_RAW field.
	UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_RAW field.
	UART_INT_RAW_TXFIFO_EMPTY_INT_RAW_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_RAW.
	UART_INT_RAW_TXFIFO_EMPTY_INT_RAW = 0x2
	// Position of PARITY_ERR_INT_RAW field.
	UART_INT_RAW_PARITY_ERR_INT_RAW_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_RAW field.
	UART_INT_RAW_PARITY_ERR_INT_RAW_Msk = 0x4
	// Bit PARITY_ERR_INT_RAW.
	UART_INT_RAW_PARITY_ERR_INT_RAW = 0x4
	// Position of FRM_ERR_INT_RAW field.
	UART_INT_RAW_FRM_ERR_INT_RAW_Pos = 0x3
	// Bit mask of FRM_ERR_INT_RAW field.
	UART_INT_RAW_FRM_ERR_INT_RAW_Msk = 0x8
	// Bit FRM_ERR_INT_RAW.
	UART_INT_RAW_FRM_ERR_INT_RAW = 0x8
	// Position of RXFIFO_OVF_INT_RAW field.
	UART_INT_RAW_RXFIFO_OVF_INT_RAW_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_RAW field.
	UART_INT_RAW_RXFIFO_OVF_INT_RAW_Msk = 0x10
	// Bit RXFIFO_OVF_INT_RAW.
	UART_INT_RAW_RXFIFO_OVF_INT_RAW = 0x10
	// Position of DSR_CHG_INT_RAW field.
	UART_INT_RAW_DSR_CHG_INT_RAW_Pos = 0x5
	// Bit mask of DSR_CHG_INT_RAW field.
	UART_INT_RAW_DSR_CHG_INT_RAW_Msk = 0x20
	// Bit DSR_CHG_INT_RAW.
	UART_INT_RAW_DSR_CHG_INT_RAW = 0x20
	// Position of CTS_CHG_INT_RAW field.
	UART_INT_RAW_CTS_CHG_INT_RAW_Pos = 0x6
	// Bit mask of CTS_CHG_INT_RAW field.
	UART_INT_RAW_CTS_CHG_INT_RAW_Msk = 0x40
	// Bit CTS_CHG_INT_RAW.
	UART_INT_RAW_CTS_CHG_INT_RAW = 0x40
	// Position of BRK_DET_INT_RAW field.
	UART_INT_RAW_BRK_DET_INT_RAW_Pos = 0x7
	// Bit mask of BRK_DET_INT_RAW field.
	UART_INT_RAW_BRK_DET_INT_RAW_Msk = 0x80
	// Bit BRK_DET_INT_RAW.
	UART_INT_RAW_BRK_DET_INT_RAW = 0x80
	// Position of RXFIFO_TOUT_INT_RAW field.
	UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_RAW field.
	UART_INT_RAW_RXFIFO_TOUT_INT_RAW_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_RAW.
	UART_INT_RAW_RXFIFO_TOUT_INT_RAW = 0x100
	// Position of SW_XON_INT_RAW field.
	UART_INT_RAW_SW_XON_INT_RAW_Pos = 0x9
	// Bit mask of SW_XON_INT_RAW field.
	UART_INT_RAW_SW_XON_INT_RAW_Msk = 0x200
	// Bit SW_XON_INT_RAW.
	UART_INT_RAW_SW_XON_INT_RAW = 0x200
	// Position of SW_XOFF_INT_RAW field.
	UART_INT_RAW_SW_XOFF_INT_RAW_Pos = 0xa
	// Bit mask of SW_XOFF_INT_RAW field.
	UART_INT_RAW_SW_XOFF_INT_RAW_Msk = 0x400
	// Bit SW_XOFF_INT_RAW.
	UART_INT_RAW_SW_XOFF_INT_RAW = 0x400
	// Position of GLITCH_DET_INT_RAW field.
	UART_INT_RAW_GLITCH_DET_INT_RAW_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_RAW field.
	UART_INT_RAW_GLITCH_DET_INT_RAW_Msk = 0x800
	// Bit GLITCH_DET_INT_RAW.
	UART_INT_RAW_GLITCH_DET_INT_RAW = 0x800
	// Position of TX_BRK_DONE_INT_RAW field.
	UART_INT_RAW_TX_BRK_DONE_INT_RAW_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_RAW field.
	UART_INT_RAW_TX_BRK_DONE_INT_RAW_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_RAW.
	UART_INT_RAW_TX_BRK_DONE_INT_RAW = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_RAW field.
	UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_RAW field.
	UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_RAW.
	UART_INT_RAW_TX_BRK_IDLE_DONE_INT_RAW = 0x2000
	// Position of TX_DONE_INT_RAW field.
	UART_INT_RAW_TX_DONE_INT_RAW_Pos = 0xe
	// Bit mask of TX_DONE_INT_RAW field.
	UART_INT_RAW_TX_DONE_INT_RAW_Msk = 0x4000
	// Bit TX_DONE_INT_RAW.
	UART_INT_RAW_TX_DONE_INT_RAW = 0x4000
	// Position of RS485_PARITY_ERR_INT_RAW field.
	UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Pos = 0xf
	// Bit mask of RS485_PARITY_ERR_INT_RAW field.
	UART_INT_RAW_RS485_PARITY_ERR_INT_RAW_Msk = 0x8000
	// Bit RS485_PARITY_ERR_INT_RAW.
	UART_INT_RAW_RS485_PARITY_ERR_INT_RAW = 0x8000
	// Position of RS485_FRM_ERR_INT_RAW field.
	UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Pos = 0x10
	// Bit mask of RS485_FRM_ERR_INT_RAW field.
	UART_INT_RAW_RS485_FRM_ERR_INT_RAW_Msk = 0x10000
	// Bit RS485_FRM_ERR_INT_RAW.
	UART_INT_RAW_RS485_FRM_ERR_INT_RAW = 0x10000
	// Position of RS485_CLASH_INT_RAW field.
	UART_INT_RAW_RS485_CLASH_INT_RAW_Pos = 0x11
	// Bit mask of RS485_CLASH_INT_RAW field.
	UART_INT_RAW_RS485_CLASH_INT_RAW_Msk = 0x20000
	// Bit RS485_CLASH_INT_RAW.
	UART_INT_RAW_RS485_CLASH_INT_RAW = 0x20000
	// Position of AT_CMD_CHAR_DET_INT_RAW field.
	UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_RAW field.
	UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_RAW.
	UART_INT_RAW_AT_CMD_CHAR_DET_INT_RAW = 0x40000
	// Position of WAKEUP_INT_RAW field.
	UART_INT_RAW_WAKEUP_INT_RAW_Pos = 0x13
	// Bit mask of WAKEUP_INT_RAW field.
	UART_INT_RAW_WAKEUP_INT_RAW_Msk = 0x80000
	// Bit WAKEUP_INT_RAW.
	UART_INT_RAW_WAKEUP_INT_RAW = 0x80000

	// INT_ST: Masked interrupt status
	// Position of RXFIFO_FULL_INT_ST field.
	UART_INT_ST_RXFIFO_FULL_INT_ST_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_ST field.
	UART_INT_ST_RXFIFO_FULL_INT_ST_Msk = 0x1
	// Bit RXFIFO_FULL_INT_ST.
	UART_INT_ST_RXFIFO_FULL_INT_ST = 0x1
	// Position of TXFIFO_EMPTY_INT_ST field.
	UART_INT_ST_TXFIFO_EMPTY_INT_ST_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_ST field.
	UART_INT_ST_TXFIFO_EMPTY_INT_ST_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_ST.
	UART_INT_ST_TXFIFO_EMPTY_INT_ST = 0x2
	// Position of PARITY_ERR_INT_ST field.
	UART_INT_ST_PARITY_ERR_INT_ST_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_ST field.
	UART_INT_ST_PARITY_ERR_INT_ST_Msk = 0x4
	// Bit PARITY_ERR_INT_ST.
	UART_INT_ST_PARITY_ERR_INT_ST = 0x4
	// Position of FRM_ERR_INT_ST field.
	UART_INT_ST_FRM_ERR_INT_ST_Pos = 0x3
	// Bit mask of FRM_ERR_INT_ST field.
	UART_INT_ST_FRM_ERR_INT_ST_Msk = 0x8
	// Bit FRM_ERR_INT_ST.
	UART_INT_ST_FRM_ERR_INT_ST = 0x8
	// Position of RXFIFO_OVF_INT_ST field.
	UART_INT_ST_RXFIFO_OVF_INT_ST_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_ST field.
	UART_INT_ST_RXFIFO_OVF_INT_ST_Msk = 0x10
	// Bit RXFIFO_OVF_INT_ST.
	UART_INT_ST_RXFIFO_OVF_INT_ST = 0x10
	// Position of DSR_CHG_INT_ST field.
	UART_INT_ST_DSR_CHG_INT_ST_Pos = 0x5
	// Bit mask of DSR_CHG_INT_ST field.
	UART_INT_ST_DSR_CHG_INT_ST_Msk = 0x20
	// Bit DSR_CHG_INT_ST.
	UART_INT_ST_DSR_CHG_INT_ST = 0x20
	// Position of CTS_CHG_INT_ST field.
	UART_INT_ST_CTS_CHG_INT_ST_Pos = 0x6
	// Bit mask of CTS_CHG_INT_ST field.
	UART_INT_ST_CTS_CHG_INT_ST_Msk = 0x40
	// Bit CTS_CHG_INT_ST.
	UART_INT_ST_CTS_CHG_INT_ST = 0x40
	// Position of BRK_DET_INT_ST field.
	UART_INT_ST_BRK_DET_INT_ST_Pos = 0x7
	// Bit mask of BRK_DET_INT_ST field.
	UART_INT_ST_BRK_DET_INT_ST_Msk = 0x80
	// Bit BRK_DET_INT_ST.
	UART_INT_ST_BRK_DET_INT_ST = 0x80
	// Position of RXFIFO_TOUT_INT_ST field.
	UART_INT_ST_RXFIFO_TOUT_INT_ST_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_ST field.
	UART_INT_ST_RXFIFO_TOUT_INT_ST_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_ST.
	UART_INT_ST_RXFIFO_TOUT_INT_ST = 0x100
	// Position of SW_XON_INT_ST field.
	UART_INT_ST_SW_XON_INT_ST_Pos = 0x9
	// Bit mask of SW_XON_INT_ST field.
	UART_INT_ST_SW_XON_INT_ST_Msk = 0x200
	// Bit SW_XON_INT_ST.
	UART_INT_ST_SW_XON_INT_ST = 0x200
	// Position of SW_XOFF_INT_ST field.
	UART_INT_ST_SW_XOFF_INT_ST_Pos = 0xa
	// Bit mask of SW_XOFF_INT_ST field.
	UART_INT_ST_SW_XOFF_INT_ST_Msk = 0x400
	// Bit SW_XOFF_INT_ST.
	UART_INT_ST_SW_XOFF_INT_ST = 0x400
	// Position of GLITCH_DET_INT_ST field.
	UART_INT_ST_GLITCH_DET_INT_ST_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_ST field.
	UART_INT_ST_GLITCH_DET_INT_ST_Msk = 0x800
	// Bit GLITCH_DET_INT_ST.
	UART_INT_ST_GLITCH_DET_INT_ST = 0x800
	// Position of TX_BRK_DONE_INT_ST field.
	UART_INT_ST_TX_BRK_DONE_INT_ST_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_ST field.
	UART_INT_ST_TX_BRK_DONE_INT_ST_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_ST.
	UART_INT_ST_TX_BRK_DONE_INT_ST = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_ST field.
	UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_ST field.
	UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_ST.
	UART_INT_ST_TX_BRK_IDLE_DONE_INT_ST = 0x2000
	// Position of TX_DONE_INT_ST field.
	UART_INT_ST_TX_DONE_INT_ST_Pos = 0xe
	// Bit mask of TX_DONE_INT_ST field.
	UART_INT_ST_TX_DONE_INT_ST_Msk = 0x4000
	// Bit TX_DONE_INT_ST.
	UART_INT_ST_TX_DONE_INT_ST = 0x4000
	// Position of RS485_PARITY_ERR_INT_ST field.
	UART_INT_ST_RS485_PARITY_ERR_INT_ST_Pos = 0xf
	// Bit mask of RS485_PARITY_ERR_INT_ST field.
	UART_INT_ST_RS485_PARITY_ERR_INT_ST_Msk = 0x8000
	// Bit RS485_PARITY_ERR_INT_ST.
	UART_INT_ST_RS485_PARITY_ERR_INT_ST = 0x8000
	// Position of RS485_FRM_ERR_INT_ST field.
	UART_INT_ST_RS485_FRM_ERR_INT_ST_Pos = 0x10
	// Bit mask of RS485_FRM_ERR_INT_ST field.
	UART_INT_ST_RS485_FRM_ERR_INT_ST_Msk = 0x10000
	// Bit RS485_FRM_ERR_INT_ST.
	UART_INT_ST_RS485_FRM_ERR_INT_ST = 0x10000
	// Position of RS485_CLASH_INT_ST field.
	UART_INT_ST_RS485_CLASH_INT_ST_Pos = 0x11
	// Bit mask of RS485_CLASH_INT_ST field.
	UART_INT_ST_RS485_CLASH_INT_ST_Msk = 0x20000
	// Bit RS485_CLASH_INT_ST.
	UART_INT_ST_RS485_CLASH_INT_ST = 0x20000
	// Position of AT_CMD_CHAR_DET_INT_ST field.
	UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_ST field.
	UART_INT_ST_AT_CMD_CHAR_DET_INT_ST_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_ST.
	UART_INT_ST_AT_CMD_CHAR_DET_INT_ST = 0x40000
	// Position of WAKEUP_INT_ST field.
	UART_INT_ST_WAKEUP_INT_ST_Pos = 0x13
	// Bit mask of WAKEUP_INT_ST field.
	UART_INT_ST_WAKEUP_INT_ST_Msk = 0x80000
	// Bit WAKEUP_INT_ST.
	UART_INT_ST_WAKEUP_INT_ST = 0x80000

	// INT_ENA: Interrupt enable bits
	// Position of RXFIFO_FULL_INT_ENA field.
	UART_INT_ENA_RXFIFO_FULL_INT_ENA_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_ENA field.
	UART_INT_ENA_RXFIFO_FULL_INT_ENA_Msk = 0x1
	// Bit RXFIFO_FULL_INT_ENA.
	UART_INT_ENA_RXFIFO_FULL_INT_ENA = 0x1
	// Position of TXFIFO_EMPTY_INT_ENA field.
	UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_ENA field.
	UART_INT_ENA_TXFIFO_EMPTY_INT_ENA_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_ENA.
	UART_INT_ENA_TXFIFO_EMPTY_INT_ENA = 0x2
	// Position of PARITY_ERR_INT_ENA field.
	UART_INT_ENA_PARITY_ERR_INT_ENA_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_ENA field.
	UART_INT_ENA_PARITY_ERR_INT_ENA_Msk = 0x4
	// Bit PARITY_ERR_INT_ENA.
	UART_INT_ENA_PARITY_ERR_INT_ENA = 0x4
	// Position of FRM_ERR_INT_ENA field.
	UART_INT_ENA_FRM_ERR_INT_ENA_Pos = 0x3
	// Bit mask of FRM_ERR_INT_ENA field.
	UART_INT_ENA_FRM_ERR_INT_ENA_Msk = 0x8
	// Bit FRM_ERR_INT_ENA.
	UART_INT_ENA_FRM_ERR_INT_ENA = 0x8
	// Position of RXFIFO_OVF_INT_ENA field.
	UART_INT_ENA_RXFIFO_OVF_INT_ENA_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_ENA field.
	UART_INT_ENA_RXFIFO_OVF_INT_ENA_Msk = 0x10
	// Bit RXFIFO_OVF_INT_ENA.
	UART_INT_ENA_RXFIFO_OVF_INT_ENA = 0x10
	// Position of DSR_CHG_INT_ENA field.
	UART_INT_ENA_DSR_CHG_INT_ENA_Pos = 0x5
	// Bit mask of DSR_CHG_INT_ENA field.
	UART_INT_ENA_DSR_CHG_INT_ENA_Msk = 0x20
	// Bit DSR_CHG_INT_ENA.
	UART_INT_ENA_DSR_CHG_INT_ENA = 0x20
	// Position of CTS_CHG_INT_ENA field.
	UART_INT_ENA_CTS_CHG_INT_ENA_Pos = 0x6
	// Bit mask of CTS_CHG_INT_ENA field.
	UART_INT_ENA_CTS_CHG_INT_ENA_Msk = 0x40
	// Bit CTS_CHG_INT_ENA.
	UART_INT_ENA_CTS_CHG_INT_ENA = 0x40
	// Position of BRK_DET_INT_ENA field.
	UART_INT_ENA_BRK_DET_INT_ENA_Pos = 0x7
	// Bit mask of BRK_DET_INT_ENA field.
	UART_INT_ENA_BRK_DET_INT_ENA_Msk = 0x80
	// Bit BRK_DET_INT_ENA.
	UART_INT_ENA_BRK_DET_INT_ENA = 0x80
	// Position of RXFIFO_TOUT_INT_ENA field.
	UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_ENA field.
	UART_INT_ENA_RXFIFO_TOUT_INT_ENA_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_ENA.
	UART_INT_ENA_RXFIFO_TOUT_INT_ENA = 0x100
	// Position of SW_XON_INT_ENA field.
	UART_INT_ENA_SW_XON_INT_ENA_Pos = 0x9
	// Bit mask of SW_XON_INT_ENA field.
	UART_INT_ENA_SW_XON_INT_ENA_Msk = 0x200
	// Bit SW_XON_INT_ENA.
	UART_INT_ENA_SW_XON_INT_ENA = 0x200
	// Position of SW_XOFF_INT_ENA field.
	UART_INT_ENA_SW_XOFF_INT_ENA_Pos = 0xa
	// Bit mask of SW_XOFF_INT_ENA field.
	UART_INT_ENA_SW_XOFF_INT_ENA_Msk = 0x400
	// Bit SW_XOFF_INT_ENA.
	UART_INT_ENA_SW_XOFF_INT_ENA = 0x400
	// Position of GLITCH_DET_INT_ENA field.
	UART_INT_ENA_GLITCH_DET_INT_ENA_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_ENA field.
	UART_INT_ENA_GLITCH_DET_INT_ENA_Msk = 0x800
	// Bit GLITCH_DET_INT_ENA.
	UART_INT_ENA_GLITCH_DET_INT_ENA = 0x800
	// Position of TX_BRK_DONE_INT_ENA field.
	UART_INT_ENA_TX_BRK_DONE_INT_ENA_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_ENA field.
	UART_INT_ENA_TX_BRK_DONE_INT_ENA_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_ENA.
	UART_INT_ENA_TX_BRK_DONE_INT_ENA = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_ENA field.
	UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_ENA field.
	UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_ENA.
	UART_INT_ENA_TX_BRK_IDLE_DONE_INT_ENA = 0x2000
	// Position of TX_DONE_INT_ENA field.
	UART_INT_ENA_TX_DONE_INT_ENA_Pos = 0xe
	// Bit mask of TX_DONE_INT_ENA field.
	UART_INT_ENA_TX_DONE_INT_ENA_Msk = 0x4000
	// Bit TX_DONE_INT_ENA.
	UART_INT_ENA_TX_DONE_INT_ENA = 0x4000
	// Position of RS485_PARITY_ERR_INT_ENA field.
	UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Pos = 0xf
	// Bit mask of RS485_PARITY_ERR_INT_ENA field.
	UART_INT_ENA_RS485_PARITY_ERR_INT_ENA_Msk = 0x8000
	// Bit RS485_PARITY_ERR_INT_ENA.
	UART_INT_ENA_RS485_PARITY_ERR_INT_ENA = 0x8000
	// Position of RS485_FRM_ERR_INT_ENA field.
	UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Pos = 0x10
	// Bit mask of RS485_FRM_ERR_INT_ENA field.
	UART_INT_ENA_RS485_FRM_ERR_INT_ENA_Msk = 0x10000
	// Bit RS485_FRM_ERR_INT_ENA.
	UART_INT_ENA_RS485_FRM_ERR_INT_ENA = 0x10000
	// Position of RS485_CLASH_INT_ENA field.
	UART_INT_ENA_RS485_CLASH_INT_ENA_Pos = 0x11
	// Bit mask of RS485_CLASH_INT_ENA field.
	UART_INT_ENA_RS485_CLASH_INT_ENA_Msk = 0x20000
	// Bit RS485_CLASH_INT_ENA.
	UART_INT_ENA_RS485_CLASH_INT_ENA = 0x20000
	// Position of AT_CMD_CHAR_DET_INT_ENA field.
	UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_ENA field.
	UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_ENA.
	UART_INT_ENA_AT_CMD_CHAR_DET_INT_ENA = 0x40000
	// Position of WAKEUP_INT_ENA field.
	UART_INT_ENA_WAKEUP_INT_ENA_Pos = 0x13
	// Bit mask of WAKEUP_INT_ENA field.
	UART_INT_ENA_WAKEUP_INT_ENA_Msk = 0x80000
	// Bit WAKEUP_INT_ENA.
	UART_INT_ENA_WAKEUP_INT_ENA = 0x80000

	// INT_CLR: Interrupt clear bits
	// Position of RXFIFO_FULL_INT_CLR field.
	UART_INT_CLR_RXFIFO_FULL_INT_CLR_Pos = 0x0
	// Bit mask of RXFIFO_FULL_INT_CLR field.
	UART_INT_CLR_RXFIFO_FULL_INT_CLR_Msk = 0x1
	// Bit RXFIFO_FULL_INT_CLR.
	UART_INT_CLR_RXFIFO_FULL_INT_CLR = 0x1
	// Position of TXFIFO_EMPTY_INT_CLR field.
	UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Pos = 0x1
	// Bit mask of TXFIFO_EMPTY_INT_CLR field.
	UART_INT_CLR_TXFIFO_EMPTY_INT_CLR_Msk = 0x2
	// Bit TXFIFO_EMPTY_INT_CLR.
	UART_INT_CLR_TXFIFO_EMPTY_INT_CLR = 0x2
	// Position of PARITY_ERR_INT_CLR field.
	UART_INT_CLR_PARITY_ERR_INT_CLR_Pos = 0x2
	// Bit mask of PARITY_ERR_INT_CLR field.
	UART_INT_CLR_PARITY_ERR_INT_CLR_Msk = 0x4
	// Bit PARITY_ERR_INT_CLR.
	UART_INT_CLR_PARITY_ERR_INT_CLR = 0x4
	// Position of FRM_ERR_INT_CLR field.
	UART_INT_CLR_FRM_ERR_INT_CLR_Pos = 0x3
	// Bit mask of FRM_ERR_INT_CLR field.
	UART_INT_CLR_FRM_ERR_INT_CLR_Msk = 0x8
	// Bit FRM_ERR_INT_CLR.
	UART_INT_CLR_FRM_ERR_INT_CLR = 0x8
	// Position of RXFIFO_OVF_INT_CLR field.
	UART_INT_CLR_RXFIFO_OVF_INT_CLR_Pos = 0x4
	// Bit mask of RXFIFO_OVF_INT_CLR field.
	UART_INT_CLR_RXFIFO_OVF_INT_CLR_Msk = 0x10
	// Bit RXFIFO_OVF_INT_CLR.
	UART_INT_CLR_RXFIFO_OVF_INT_CLR = 0x10
	// Position of DSR_CHG_INT_CLR field.
	UART_INT_CLR_DSR_CHG_INT_CLR_Pos = 0x5
	// Bit mask of DSR_CHG_INT_CLR field.
	UART_INT_CLR_DSR_CHG_INT_CLR_Msk = 0x20
	// Bit DSR_CHG_INT_CLR.
	UART_INT_CLR_DSR_CHG_INT_CLR = 0x20
	// Position of CTS_CHG_INT_CLR field.
	UART_INT_CLR_CTS_CHG_INT_CLR_Pos = 0x6
	// Bit mask of CTS_CHG_INT_CLR field.
	UART_INT_CLR_CTS_CHG_INT_CLR_Msk = 0x40
	// Bit CTS_CHG_INT_CLR.
	UART_INT_CLR_CTS_CHG_INT_CLR = 0x40
	// Position of BRK_DET_INT_CLR field.
	UART_INT_CLR_BRK_DET_INT_CLR_Pos = 0x7
	// Bit mask of BRK_DET_INT_CLR field.
	UART_INT_CLR_BRK_DET_INT_CLR_Msk = 0x80
	// Bit BRK_DET_INT_CLR.
	UART_INT_CLR_BRK_DET_INT_CLR = 0x80
	// Position of RXFIFO_TOUT_INT_CLR field.
	UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Pos = 0x8
	// Bit mask of RXFIFO_TOUT_INT_CLR field.
	UART_INT_CLR_RXFIFO_TOUT_INT_CLR_Msk = 0x100
	// Bit RXFIFO_TOUT_INT_CLR.
	UART_INT_CLR_RXFIFO_TOUT_INT_CLR = 0x100
	// Position of SW_XON_INT_CLR field.
	UART_INT_CLR_SW_XON_INT_CLR_Pos = 0x9
	// Bit mask of SW_XON_INT_CLR field.
	UART_INT_CLR_SW_XON_INT_CLR_Msk = 0x200
	// Bit SW_XON_INT_CLR.
	UART_INT_CLR_SW_XON_INT_CLR = 0x200
	// Position of SW_XOFF_INT_CLR field.
	UART_INT_CLR_SW_XOFF_INT_CLR_Pos = 0xa
	// Bit mask of SW_XOFF_INT_CLR field.
	UART_INT_CLR_SW_XOFF_INT_CLR_Msk = 0x400
	// Bit SW_XOFF_INT_CLR.
	UART_INT_CLR_SW_XOFF_INT_CLR = 0x400
	// Position of GLITCH_DET_INT_CLR field.
	UART_INT_CLR_GLITCH_DET_INT_CLR_Pos = 0xb
	// Bit mask of GLITCH_DET_INT_CLR field.
	UART_INT_CLR_GLITCH_DET_INT_CLR_Msk = 0x800
	// Bit GLITCH_DET_INT_CLR.
	UART_INT_CLR_GLITCH_DET_INT_CLR = 0x800
	// Position of TX_BRK_DONE_INT_CLR field.
	UART_INT_CLR_TX_BRK_DONE_INT_CLR_Pos = 0xc
	// Bit mask of TX_BRK_DONE_INT_CLR field.
	UART_INT_CLR_TX_BRK_DONE_INT_CLR_Msk = 0x1000
	// Bit TX_BRK_DONE_INT_CLR.
	UART_INT_CLR_TX_BRK_DONE_INT_CLR = 0x1000
	// Position of TX_BRK_IDLE_DONE_INT_CLR field.
	UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Pos = 0xd
	// Bit mask of TX_BRK_IDLE_DONE_INT_CLR field.
	UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR_Msk = 0x2000
	// Bit TX_BRK_IDLE_DONE_INT_CLR.
	UART_INT_CLR_TX_BRK_IDLE_DONE_INT_CLR = 0x2000
	// Position of TX_DONE_INT_CLR field.
	UART_INT_CLR_TX_DONE_INT_CLR_Pos = 0xe
	// Bit mask of TX_DONE_INT_CLR field.
	UART_INT_CLR_TX_DONE_INT_CLR_Msk = 0x4000
	// Bit TX_DONE_INT_CLR.
	UART_INT_CLR_TX_DONE_INT_CLR = 0x4000
	// Position of RS485_PARITY_ERR_INT_CLR field.
	UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Pos = 0xf
	// Bit mask of RS485_PARITY_ERR_INT_CLR field.
	UART_INT_CLR_RS485_PARITY_ERR_INT_CLR_Msk = 0x8000
	// Bit RS485_PARITY_ERR_INT_CLR.
	UART_INT_CLR_RS485_PARITY_ERR_INT_CLR = 0x8000
	// Position of RS485_FRM_ERR_INT_CLR field.
	UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Pos = 0x10
	// Bit mask of RS485_FRM_ERR_INT_CLR field.
	UART_INT_CLR_RS485_FRM_ERR_INT_CLR_Msk = 0x10000
	// Bit RS485_FRM_ERR_INT_CLR.
	UART_INT_CLR_RS485_FRM_ERR_INT_CLR = 0x10000
	// Position of RS485_CLASH_INT_CLR field.
	UART_INT_CLR_RS485_CLASH_INT_CLR_Pos = 0x11
	// Bit mask of RS485_CLASH_INT_CLR field.
	UART_INT_CLR_RS485_CLASH_INT_CLR_Msk = 0x20000
	// Bit RS485_CLASH_INT_CLR.
	UART_INT_CLR_RS485_CLASH_INT_CLR = 0x20000
	// Position of AT_CMD_CHAR_DET_INT_CLR field.
	UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Pos = 0x12
	// Bit mask of AT_CMD_CHAR_DET_INT_CLR field.
	UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR_Msk = 0x40000
	// Bit AT_CMD_CHAR_DET_INT_CLR.
	UART_INT_CLR_AT_CMD_CHAR_DET_INT_CLR = 0x40000
	// Position of WAKEUP_INT_CLR field.
	UART_INT_CLR_WAKEUP_INT_CLR_Pos = 0x13
	// Bit mask of WAKEUP_INT_CLR field.
	UART_INT_CLR_WAKEUP_INT_CLR_Msk = 0x80000
	// Bit WAKEUP_INT_CLR.
	UART_INT_CLR_WAKEUP_INT_CLR = 0x80000

	// CLKDIV_SYNC: Clock divider configuration
	// Position of CLKDIV field.
	UART_CLKDIV_SYNC_CLKDIV_Pos = 0x0
	// Bit mask of CLKDIV field.
	UART_CLKDIV_SYNC_CLKDIV_Msk = 0xfff
	// Position of CLKDIV_FRAG field.
	UART_CLKDIV_SYNC_CLKDIV_FRAG_Pos = 0x14
	// Bit mask of CLKDIV_FRAG field.
	UART_CLKDIV_SYNC_CLKDIV_FRAG_Msk = 0xf00000

	// RX_FILT: Rx Filter configuration
	// Position of GLITCH_FILT field.
	UART_RX_FILT_GLITCH_FILT_Pos = 0x0
	// Bit mask of GLITCH_FILT field.
	UART_RX_FILT_GLITCH_FILT_Msk = 0xff
	// Position of GLITCH_FILT_EN field.
	UART_RX_FILT_GLITCH_FILT_EN_Pos = 0x8
	// Bit mask of GLITCH_FILT_EN field.
	UART_RX_FILT_GLITCH_FILT_EN_Msk = 0x100
	// Bit GLITCH_FILT_EN.
	UART_RX_FILT_GLITCH_FILT_EN = 0x100

	// STATUS: UART status register
	// Position of RXFIFO_CNT field.
	UART_STATUS_RXFIFO_CNT_Pos = 0x0
	// Bit mask of RXFIFO_CNT field.
	UART_STATUS_RXFIFO_CNT_Msk = 0xff
	// Position of DSRN field.
	UART_STATUS_DSRN_Pos = 0xd
	// Bit mask of DSRN field.
	UART_STATUS_DSRN_Msk = 0x2000
	// Bit DSRN.
	UART_STATUS_DSRN = 0x2000
	// Position of CTSN field.
	UART_STATUS_CTSN_Pos = 0xe
	// Bit mask of CTSN field.
	UART_STATUS_CTSN_Msk = 0x4000
	// Bit CTSN.
	UART_STATUS_CTSN = 0x4000
	// Position of RXD field.
	UART_STATUS_RXD_Pos = 0xf
	// Bit mask of RXD field.
	UART_STATUS_RXD_Msk = 0x8000
	// Bit RXD.
	UART_STATUS_RXD = 0x8000
	// Position of TXFIFO_CNT field.
	UART_STATUS_TXFIFO_CNT_Pos = 0x10
	// Bit mask of TXFIFO_CNT field.
	UART_STATUS_TXFIFO_CNT_Msk = 0xff0000
	// Position of DTRN field.
	UART_STATUS_DTRN_Pos = 0x1d
	// Bit mask of DTRN field.
	UART_STATUS_DTRN_Msk = 0x20000000
	// Bit DTRN.
	UART_STATUS_DTRN = 0x20000000
	// Position of RTSN field.
	UART_STATUS_RTSN_Pos = 0x1e
	// Bit mask of RTSN field.
	UART_STATUS_RTSN_Msk = 0x40000000
	// Bit RTSN.
	UART_STATUS_RTSN = 0x40000000
	// Position of TXD field.
	UART_STATUS_TXD_Pos = 0x1f
	// Bit mask of TXD field.
	UART_STATUS_TXD_Msk = 0x80000000
	// Bit TXD.
	UART_STATUS_TXD = 0x80000000

	// CONF0_SYNC: a
	// Position of PARITY field.
	UART_CONF0_SYNC_PARITY_Pos = 0x0
	// Bit mask of PARITY field.
	UART_CONF0_SYNC_PARITY_Msk = 0x1
	// Bit PARITY.
	UART_CONF0_SYNC_PARITY = 0x1
	// Position of PARITY_EN field.
	UART_CONF0_SYNC_PARITY_EN_Pos = 0x1
	// Bit mask of PARITY_EN field.
	UART_CONF0_SYNC_PARITY_EN_Msk = 0x2
	// Bit PARITY_EN.
	UART_CONF0_SYNC_PARITY_EN = 0x2
	// Position of BIT_NUM field.
	UART_CONF0_SYNC_BIT_NUM_Pos = 0x2
	// Bit mask of BIT_NUM field.
	UART_CONF0_SYNC_BIT_NUM_Msk = 0xc
	// Position of STOP_BIT_NUM field.
	UART_CONF0_SYNC_STOP_BIT_NUM_Pos = 0x4
	// Bit mask of STOP_BIT_NUM field.
	UART_CONF0_SYNC_STOP_BIT_NUM_Msk = 0x30
	// Position of TXD_BRK field.
	UART_CONF0_SYNC_TXD_BRK_Pos = 0x6
	// Bit mask of TXD_BRK field.
	UART_CONF0_SYNC_TXD_BRK_Msk = 0x40
	// Bit TXD_BRK.
	UART_CONF0_SYNC_TXD_BRK = 0x40
	// Position of IRDA_DPLX field.
	UART_CONF0_SYNC_IRDA_DPLX_Pos = 0x7
	// Bit mask of IRDA_DPLX field.
	UART_CONF0_SYNC_IRDA_DPLX_Msk = 0x80
	// Bit IRDA_DPLX.
	UART_CONF0_SYNC_IRDA_DPLX = 0x80
	// Position of IRDA_TX_EN field.
	UART_CONF0_SYNC_IRDA_TX_EN_Pos = 0x8
	// Bit mask of IRDA_TX_EN field.
	UART_CONF0_SYNC_IRDA_TX_EN_Msk = 0x100
	// Bit IRDA_TX_EN.
	UART_CONF0_SYNC_IRDA_TX_EN = 0x100
	// Position of IRDA_WCTL field.
	UART_CONF0_SYNC_IRDA_WCTL_Pos = 0x9
	// Bit mask of IRDA_WCTL field.
	UART_CONF0_SYNC_IRDA_WCTL_Msk = 0x200
	// Bit IRDA_WCTL.
	UART_CONF0_SYNC_IRDA_WCTL = 0x200
	// Position of IRDA_TX_INV field.
	UART_CONF0_SYNC_IRDA_TX_INV_Pos = 0xa
	// Bit mask of IRDA_TX_INV field.
	UART_CONF0_SYNC_IRDA_TX_INV_Msk = 0x400
	// Bit IRDA_TX_INV.
	UART_CONF0_SYNC_IRDA_TX_INV = 0x400
	// Position of IRDA_RX_INV field.
	UART_CONF0_SYNC_IRDA_RX_INV_Pos = 0xb
	// Bit mask of IRDA_RX_INV field.
	UART_CONF0_SYNC_IRDA_RX_INV_Msk = 0x800
	// Bit IRDA_RX_INV.
	UART_CONF0_SYNC_IRDA_RX_INV = 0x800
	// Position of LOOPBACK field.
	UART_CONF0_SYNC_LOOPBACK_Pos = 0xc
	// Bit mask of LOOPBACK field.
	UART_CONF0_SYNC_LOOPBACK_Msk = 0x1000
	// Bit LOOPBACK.
	UART_CONF0_SYNC_LOOPBACK = 0x1000
	// Position of TX_FLOW_EN field.
	UART_CONF0_SYNC_TX_FLOW_EN_Pos = 0xd
	// Bit mask of TX_FLOW_EN field.
	UART_CONF0_SYNC_TX_FLOW_EN_Msk = 0x2000
	// Bit TX_FLOW_EN.
	UART_CONF0_SYNC_TX_FLOW_EN = 0x2000
	// Position of IRDA_EN field.
	UART_CONF0_SYNC_IRDA_EN_Pos = 0xe
	// Bit mask of IRDA_EN field.
	UART_CONF0_SYNC_IRDA_EN_Msk = 0x4000
	// Bit IRDA_EN.
	UART_CONF0_SYNC_IRDA_EN = 0x4000
	// Position of RXD_INV field.
	UART_CONF0_SYNC_RXD_INV_Pos = 0xf
	// Bit mask of RXD_INV field.
	UART_CONF0_SYNC_RXD_INV_Msk = 0x8000
	// Bit RXD_INV.
	UART_CONF0_SYNC_RXD_INV = 0x8000
	// Position of TXD_INV field.
	UART_CONF0_SYNC_TXD_INV_Pos = 0x10
	// Bit mask of TXD_INV field.
	UART_CONF0_SYNC_TXD_INV_Msk = 0x10000
	// Bit TXD_INV.
	UART_CONF0_SYNC_TXD_INV = 0x10000
	// Position of DIS_RX_DAT_OVF field.
	UART_CONF0_SYNC_DIS_RX_DAT_OVF_Pos = 0x11
	// Bit mask of DIS_RX_DAT_OVF field.
	UART_CONF0_SYNC_DIS_RX_DAT_OVF_Msk = 0x20000
	// Bit DIS_RX_DAT_OVF.
	UART_CONF0_SYNC_DIS_RX_DAT_OVF = 0x20000
	// Position of ERR_WR_MASK field.
	UART_CONF0_SYNC_ERR_WR_MASK_Pos = 0x12
	// Bit mask of ERR_WR_MASK field.
	UART_CONF0_SYNC_ERR_WR_MASK_Msk = 0x40000
	// Bit ERR_WR_MASK.
	UART_CONF0_SYNC_ERR_WR_MASK = 0x40000
	// Position of AUTOBAUD_EN field.
	UART_CONF0_SYNC_AUTOBAUD_EN_Pos = 0x13
	// Bit mask of AUTOBAUD_EN field.
	UART_CONF0_SYNC_AUTOBAUD_EN_Msk = 0x80000
	// Bit AUTOBAUD_EN.
	UART_CONF0_SYNC_AUTOBAUD_EN = 0x80000
	// Position of MEM_CLK_EN field.
	UART_CONF0_SYNC_MEM_CLK_EN_Pos = 0x14
	// Bit mask of MEM_CLK_EN field.
	UART_CONF0_SYNC_MEM_CLK_EN_Msk = 0x100000
	// Bit MEM_CLK_EN.
	UART_CONF0_SYNC_MEM_CLK_EN = 0x100000
	// Position of SW_RTS field.
	UART_CONF0_SYNC_SW_RTS_Pos = 0x15
	// Bit mask of SW_RTS field.
	UART_CONF0_SYNC_SW_RTS_Msk = 0x200000
	// Bit SW_RTS.
	UART_CONF0_SYNC_SW_RTS = 0x200000
	// Position of RXFIFO_RST field.
	UART_CONF0_SYNC_RXFIFO_RST_Pos = 0x16
	// Bit mask of RXFIFO_RST field.
	UART_CONF0_SYNC_RXFIFO_RST_Msk = 0x400000
	// Bit RXFIFO_RST.
	UART_CONF0_SYNC_RXFIFO_RST = 0x400000
	// Position of TXFIFO_RST field.
	UART_CONF0_SYNC_TXFIFO_RST_Pos = 0x17
	// Bit mask of TXFIFO_RST field.
	UART_CONF0_SYNC_TXFIFO_RST_Msk = 0x800000
	// Bit TXFIFO_RST.
	UART_CONF0_SYNC_TXFIFO_RST = 0x800000

	// CONF1: Configuration register 1
	// Position of RXFIFO_FULL_THRHD field.
	UART_CONF1_RXFIFO_FULL_THRHD_Pos = 0x0
	// Bit mask of RXFIFO_FULL_THRHD field.
	UART_CONF1_RXFIFO_FULL_THRHD_Msk = 0xff
	// Position of TXFIFO_EMPTY_THRHD field.
	UART_CONF1_TXFIFO_EMPTY_THRHD_Pos = 0x8
	// Bit mask of TXFIFO_EMPTY_THRHD field.
	UART_CONF1_TXFIFO_EMPTY_THRHD_Msk = 0xff00
	// Position of CTS_INV field.
	UART_CONF1_CTS_INV_Pos = 0x10
	// Bit mask of CTS_INV field.
	UART_CONF1_CTS_INV_Msk = 0x10000
	// Bit CTS_INV.
	UART_CONF1_CTS_INV = 0x10000
	// Position of DSR_INV field.
	UART_CONF1_DSR_INV_Pos = 0x11
	// Bit mask of DSR_INV field.
	UART_CONF1_DSR_INV_Msk = 0x20000
	// Bit DSR_INV.
	UART_CONF1_DSR_INV = 0x20000
	// Position of RTS_INV field.
	UART_CONF1_RTS_INV_Pos = 0x12
	// Bit mask of RTS_INV field.
	UART_CONF1_RTS_INV_Msk = 0x40000
	// Bit RTS_INV.
	UART_CONF1_RTS_INV = 0x40000
	// Position of DTR_INV field.
	UART_CONF1_DTR_INV_Pos = 0x13
	// Bit mask of DTR_INV field.
	UART_CONF1_DTR_INV_Msk = 0x80000
	// Bit DTR_INV.
	UART_CONF1_DTR_INV = 0x80000
	// Position of SW_DTR field.
	UART_CONF1_SW_DTR_Pos = 0x14
	// Bit mask of SW_DTR field.
	UART_CONF1_SW_DTR_Msk = 0x100000
	// Bit SW_DTR.
	UART_CONF1_SW_DTR = 0x100000
	// Position of CLK_EN field.
	UART_CONF1_CLK_EN_Pos = 0x15
	// Bit mask of CLK_EN field.
	UART_CONF1_CLK_EN_Msk = 0x200000
	// Bit CLK_EN.
	UART_CONF1_CLK_EN = 0x200000

	// HWFC_CONF_SYNC: Hardware flow-control configuration
	// Position of RX_FLOW_THRHD field.
	UART_HWFC_CONF_SYNC_RX_FLOW_THRHD_Pos = 0x0
	// Bit mask of RX_FLOW_THRHD field.
	UART_HWFC_CONF_SYNC_RX_FLOW_THRHD_Msk = 0xff
	// Position of RX_FLOW_EN field.
	UART_HWFC_CONF_SYNC_RX_FLOW_EN_Pos = 0x8
	// Bit mask of RX_FLOW_EN field.
	UART_HWFC_CONF_SYNC_RX_FLOW_EN_Msk = 0x100
	// Bit RX_FLOW_EN.
	UART_HWFC_CONF_SYNC_RX_FLOW_EN = 0x100

	// SLEEP_CONF0: UART sleep configure register 0
	// Position of WK_CHAR1 field.
	UART_SLEEP_CONF0_WK_CHAR1_Pos = 0x0
	// Bit mask of WK_CHAR1 field.
	UART_SLEEP_CONF0_WK_CHAR1_Msk = 0xff
	// Position of WK_CHAR2 field.
	UART_SLEEP_CONF0_WK_CHAR2_Pos = 0x8
	// Bit mask of WK_CHAR2 field.
	UART_SLEEP_CONF0_WK_CHAR2_Msk = 0xff00
	// Position of WK_CHAR3 field.
	UART_SLEEP_CONF0_WK_CHAR3_Pos = 0x10
	// Bit mask of WK_CHAR3 field.
	UART_SLEEP_CONF0_WK_CHAR3_Msk = 0xff0000
	// Position of WK_CHAR4 field.
	UART_SLEEP_CONF0_WK_CHAR4_Pos = 0x18
	// Bit mask of WK_CHAR4 field.
	UART_SLEEP_CONF0_WK_CHAR4_Msk = 0xff000000

	// SLEEP_CONF1: UART sleep configure register 1
	// Position of WK_CHAR0 field.
	UART_SLEEP_CONF1_WK_CHAR0_Pos = 0x0
	// Bit mask of WK_CHAR0 field.
	UART_SLEEP_CONF1_WK_CHAR0_Msk = 0xff

	// SLEEP_CONF2: UART sleep configure register 2
	// Position of ACTIVE_THRESHOLD field.
	UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Pos = 0x0
	// Bit mask of ACTIVE_THRESHOLD field.
	UART_SLEEP_CONF2_ACTIVE_THRESHOLD_Msk = 0x3ff
	// Position of RX_WAKE_UP_THRHD field.
	UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Pos = 0xa
	// Bit mask of RX_WAKE_UP_THRHD field.
	UART_SLEEP_CONF2_RX_WAKE_UP_THRHD_Msk = 0x3fc00
	// Position of WK_CHAR_NUM field.
	UART_SLEEP_CONF2_WK_CHAR_NUM_Pos = 0x12
	// Bit mask of WK_CHAR_NUM field.
	UART_SLEEP_CONF2_WK_CHAR_NUM_Msk = 0x1c0000
	// Position of WK_CHAR_MASK field.
	UART_SLEEP_CONF2_WK_CHAR_MASK_Pos = 0x15
	// Bit mask of WK_CHAR_MASK field.
	UART_SLEEP_CONF2_WK_CHAR_MASK_Msk = 0x3e00000
	// Position of WK_MODE_SEL field.
	UART_SLEEP_CONF2_WK_MODE_SEL_Pos = 0x1a
	// Bit mask of WK_MODE_SEL field.
	UART_SLEEP_CONF2_WK_MODE_SEL_Msk = 0xc000000

	// SWFC_CONF0_SYNC: Software flow-control character configuration
	// Position of XON_CHAR field.
	UART_SWFC_CONF0_SYNC_XON_CHAR_Pos = 0x0
	// Bit mask of XON_CHAR field.
	UART_SWFC_CONF0_SYNC_XON_CHAR_Msk = 0xff
	// Position of XOFF_CHAR field.
	UART_SWFC_CONF0_SYNC_XOFF_CHAR_Pos = 0x8
	// Bit mask of XOFF_CHAR field.
	UART_SWFC_CONF0_SYNC_XOFF_CHAR_Msk = 0xff00
	// Position of XON_XOFF_STILL_SEND field.
	UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND_Pos = 0x10
	// Bit mask of XON_XOFF_STILL_SEND field.
	UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND_Msk = 0x10000
	// Bit XON_XOFF_STILL_SEND.
	UART_SWFC_CONF0_SYNC_XON_XOFF_STILL_SEND = 0x10000
	// Position of SW_FLOW_CON_EN field.
	UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN_Pos = 0x11
	// Bit mask of SW_FLOW_CON_EN field.
	UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN_Msk = 0x20000
	// Bit SW_FLOW_CON_EN.
	UART_SWFC_CONF0_SYNC_SW_FLOW_CON_EN = 0x20000
	// Position of XONOFF_DEL field.
	UART_SWFC_CONF0_SYNC_XONOFF_DEL_Pos = 0x12
	// Bit mask of XONOFF_DEL field.
	UART_SWFC_CONF0_SYNC_XONOFF_DEL_Msk = 0x40000
	// Bit XONOFF_DEL.
	UART_SWFC_CONF0_SYNC_XONOFF_DEL = 0x40000
	// Position of FORCE_XON field.
	UART_SWFC_CONF0_SYNC_FORCE_XON_Pos = 0x13
	// Bit mask of FORCE_XON field.
	UART_SWFC_CONF0_SYNC_FORCE_XON_Msk = 0x80000
	// Bit FORCE_XON.
	UART_SWFC_CONF0_SYNC_FORCE_XON = 0x80000
	// Position of FORCE_XOFF field.
	UART_SWFC_CONF0_SYNC_FORCE_XOFF_Pos = 0x14
	// Bit mask of FORCE_XOFF field.
	UART_SWFC_CONF0_SYNC_FORCE_XOFF_Msk = 0x100000
	// Bit FORCE_XOFF.
	UART_SWFC_CONF0_SYNC_FORCE_XOFF = 0x100000
	// Position of SEND_XON field.
	UART_SWFC_CONF0_SYNC_SEND_XON_Pos = 0x15
	// Bit mask of SEND_XON field.
	UART_SWFC_CONF0_SYNC_SEND_XON_Msk = 0x200000
	// Bit SEND_XON.
	UART_SWFC_CONF0_SYNC_SEND_XON = 0x200000
	// Position of SEND_XOFF field.
	UART_SWFC_CONF0_SYNC_SEND_XOFF_Pos = 0x16
	// Bit mask of SEND_XOFF field.
	UART_SWFC_CONF0_SYNC_SEND_XOFF_Msk = 0x400000
	// Bit SEND_XOFF.
	UART_SWFC_CONF0_SYNC_SEND_XOFF = 0x400000

	// SWFC_CONF1: Software flow-control character configuration
	// Position of XON_THRESHOLD field.
	UART_SWFC_CONF1_XON_THRESHOLD_Pos = 0x0
	// Bit mask of XON_THRESHOLD field.
	UART_SWFC_CONF1_XON_THRESHOLD_Msk = 0xff
	// Position of XOFF_THRESHOLD field.
	UART_SWFC_CONF1_XOFF_THRESHOLD_Pos = 0x8
	// Bit mask of XOFF_THRESHOLD field.
	UART_SWFC_CONF1_XOFF_THRESHOLD_Msk = 0xff00

	// TXBRK_CONF_SYNC: Tx Break character configuration
	// Position of TX_BRK_NUM field.
	UART_TXBRK_CONF_SYNC_TX_BRK_NUM_Pos = 0x0
	// Bit mask of TX_BRK_NUM field.
	UART_TXBRK_CONF_SYNC_TX_BRK_NUM_Msk = 0xff

	// IDLE_CONF_SYNC: Frame-end idle configuration
	// Position of RX_IDLE_THRHD field.
	UART_IDLE_CONF_SYNC_RX_IDLE_THRHD_Pos = 0x0
	// Bit mask of RX_IDLE_THRHD field.
	UART_IDLE_CONF_SYNC_RX_IDLE_THRHD_Msk = 0x3ff
	// Position of TX_IDLE_NUM field.
	UART_IDLE_CONF_SYNC_TX_IDLE_NUM_Pos = 0xa
	// Bit mask of TX_IDLE_NUM field.
	UART_IDLE_CONF_SYNC_TX_IDLE_NUM_Msk = 0xffc00

	// RS485_CONF_SYNC: RS485 mode configuration
	// Position of RS485_EN field.
	UART_RS485_CONF_SYNC_RS485_EN_Pos = 0x0
	// Bit mask of RS485_EN field.
	UART_RS485_CONF_SYNC_RS485_EN_Msk = 0x1
	// Bit RS485_EN.
	UART_RS485_CONF_SYNC_RS485_EN = 0x1
	// Position of DL0_EN field.
	UART_RS485_CONF_SYNC_DL0_EN_Pos = 0x1
	// Bit mask of DL0_EN field.
	UART_RS485_CONF_SYNC_DL0_EN_Msk = 0x2
	// Bit DL0_EN.
	UART_RS485_CONF_SYNC_DL0_EN = 0x2
	// Position of DL1_EN field.
	UART_RS485_CONF_SYNC_DL1_EN_Pos = 0x2
	// Bit mask of DL1_EN field.
	UART_RS485_CONF_SYNC_DL1_EN_Msk = 0x4
	// Bit DL1_EN.
	UART_RS485_CONF_SYNC_DL1_EN = 0x4
	// Position of RS485TX_RX_EN field.
	UART_RS485_CONF_SYNC_RS485TX_RX_EN_Pos = 0x3
	// Bit mask of RS485TX_RX_EN field.
	UART_RS485_CONF_SYNC_RS485TX_RX_EN_Msk = 0x8
	// Bit RS485TX_RX_EN.
	UART_RS485_CONF_SYNC_RS485TX_RX_EN = 0x8
	// Position of RS485RXBY_TX_EN field.
	UART_RS485_CONF_SYNC_RS485RXBY_TX_EN_Pos = 0x4
	// Bit mask of RS485RXBY_TX_EN field.
	UART_RS485_CONF_SYNC_RS485RXBY_TX_EN_Msk = 0x10
	// Bit RS485RXBY_TX_EN.
	UART_RS485_CONF_SYNC_RS485RXBY_TX_EN = 0x10
	// Position of RS485_RX_DLY_NUM field.
	UART_RS485_CONF_SYNC_RS485_RX_DLY_NUM_Pos = 0x5
	// Bit mask of RS485_RX_DLY_NUM field.
	UART_RS485_CONF_SYNC_RS485_RX_DLY_NUM_Msk = 0x20
	// Bit RS485_RX_DLY_NUM.
	UART_RS485_CONF_SYNC_RS485_RX_DLY_NUM = 0x20
	// Position of RS485_TX_DLY_NUM field.
	UART_RS485_CONF_SYNC_RS485_TX_DLY_NUM_Pos = 0x6
	// Bit mask of RS485_TX_DLY_NUM field.
	UART_RS485_CONF_SYNC_RS485_TX_DLY_NUM_Msk = 0x3c0

	// AT_CMD_PRECNT_SYNC: Pre-sequence timing configuration
	// Position of PRE_IDLE_NUM field.
	UART_AT_CMD_PRECNT_SYNC_PRE_IDLE_NUM_Pos = 0x0
	// Bit mask of PRE_IDLE_NUM field.
	UART_AT_CMD_PRECNT_SYNC_PRE_IDLE_NUM_Msk = 0xffff

	// AT_CMD_POSTCNT_SYNC: Post-sequence timing configuration
	// Position of POST_IDLE_NUM field.
	UART_AT_CMD_POSTCNT_SYNC_POST_IDLE_NUM_Pos = 0x0
	// Bit mask of POST_IDLE_NUM field.
	UART_AT_CMD_POSTCNT_SYNC_POST_IDLE_NUM_Msk = 0xffff

	// AT_CMD_GAPTOUT_SYNC: Timeout configuration
	// Position of RX_GAP_TOUT field.
	UART_AT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT_Pos = 0x0
	// Bit mask of RX_GAP_TOUT field.
	UART_AT_CMD_GAPTOUT_SYNC_RX_GAP_TOUT_Msk = 0xffff

	// AT_CMD_CHAR_SYNC: AT escape sequence detection configuration
	// Position of AT_CMD_CHAR field.
	UART_AT_CMD_CHAR_SYNC_AT_CMD_CHAR_Pos = 0x0
	// Bit mask of AT_CMD_CHAR field.
	UART_AT_CMD_CHAR_SYNC_AT_CMD_CHAR_Msk = 0xff
	// Position of CHAR_NUM field.
	UART_AT_CMD_CHAR_SYNC_CHAR_NUM_Pos = 0x8
	// Bit mask of CHAR_NUM field.
	UART_AT_CMD_CHAR_SYNC_CHAR_NUM_Msk = 0xff00

	// MEM_CONF: UART memory power configuration
	// Position of MEM_FORCE_PD field.
	UART_MEM_CONF_MEM_FORCE_PD_Pos = 0x19
	// Bit mask of MEM_FORCE_PD field.
	UART_MEM_CONF_MEM_FORCE_PD_Msk = 0x2000000
	// Bit MEM_FORCE_PD.
	UART_MEM_CONF_MEM_FORCE_PD = 0x2000000
	// Position of MEM_FORCE_PU field.
	UART_MEM_CONF_MEM_FORCE_PU_Pos = 0x1a
	// Bit mask of MEM_FORCE_PU field.
	UART_MEM_CONF_MEM_FORCE_PU_Msk = 0x4000000
	// Bit MEM_FORCE_PU.
	UART_MEM_CONF_MEM_FORCE_PU = 0x4000000

	// TOUT_CONF_SYNC: UART threshold and allocation configuration
	// Position of RX_TOUT_EN field.
	UART_TOUT_CONF_SYNC_RX_TOUT_EN_Pos = 0x0
	// Bit mask of RX_TOUT_EN field.
	UART_TOUT_CONF_SYNC_RX_TOUT_EN_Msk = 0x1
	// Bit RX_TOUT_EN.
	UART_TOUT_CONF_SYNC_RX_TOUT_EN = 0x1
	// Position of RX_TOUT_FLOW_DIS field.
	UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS_Pos = 0x1
	// Bit mask of RX_TOUT_FLOW_DIS field.
	UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS_Msk = 0x2
	// Bit RX_TOUT_FLOW_DIS.
	UART_TOUT_CONF_SYNC_RX_TOUT_FLOW_DIS = 0x2
	// Position of RX_TOUT_THRHD field.
	UART_TOUT_CONF_SYNC_RX_TOUT_THRHD_Pos = 0x2
	// Bit mask of RX_TOUT_THRHD field.
	UART_TOUT_CONF_SYNC_RX_TOUT_THRHD_Msk = 0xffc

	// MEM_TX_STATUS: Tx-SRAM write and read offset address.
	// Position of TX_SRAM_WADDR field.
	UART_MEM_TX_STATUS_TX_SRAM_WADDR_Pos = 0x0
	// Bit mask of TX_SRAM_WADDR field.
	UART_MEM_TX_STATUS_TX_SRAM_WADDR_Msk = 0xff
	// Position of TX_SRAM_RADDR field.
	UART_MEM_TX_STATUS_TX_SRAM_RADDR_Pos = 0x9
	// Bit mask of TX_SRAM_RADDR field.
	UART_MEM_TX_STATUS_TX_SRAM_RADDR_Msk = 0x1fe00

	// MEM_RX_STATUS: Rx-SRAM write and read offset address.
	// Position of RX_SRAM_RADDR field.
	UART_MEM_RX_STATUS_RX_SRAM_RADDR_Pos = 0x0
	// Bit mask of RX_SRAM_RADDR field.
	UART_MEM_RX_STATUS_RX_SRAM_RADDR_Msk = 0xff
	// Position of RX_SRAM_WADDR field.
	UART_MEM_RX_STATUS_RX_SRAM_WADDR_Pos = 0x9
	// Bit mask of RX_SRAM_WADDR field.
	UART_MEM_RX_STATUS_RX_SRAM_WADDR_Msk = 0x1fe00

	// FSM_STATUS: UART transmit and receive status.
	// Position of ST_URX_OUT field.
	UART_FSM_STATUS_ST_URX_OUT_Pos = 0x0
	// Bit mask of ST_URX_OUT field.
	UART_FSM_STATUS_ST_URX_OUT_Msk = 0xf
	// Position of ST_UTX_OUT field.
	UART_FSM_STATUS_ST_UTX_OUT_Pos = 0x4
	// Bit mask of ST_UTX_OUT field.
	UART_FSM_STATUS_ST_UTX_OUT_Msk = 0xf0

	// POSPULSE: Autobaud high pulse register
	// Position of POSEDGE_MIN_CNT field.
	UART_POSPULSE_POSEDGE_MIN_CNT_Pos = 0x0
	// Bit mask of POSEDGE_MIN_CNT field.
	UART_POSPULSE_POSEDGE_MIN_CNT_Msk = 0xfff

	// NEGPULSE: Autobaud low pulse register
	// Position of NEGEDGE_MIN_CNT field.
	UART_NEGPULSE_NEGEDGE_MIN_CNT_Pos = 0x0
	// Bit mask of NEGEDGE_MIN_CNT field.
	UART_NEGPULSE_NEGEDGE_MIN_CNT_Msk = 0xfff

	// LOWPULSE: Autobaud minimum low pulse duration register
	// Position of MIN_CNT field.
	UART_LOWPULSE_MIN_CNT_Pos = 0x0
	// Bit mask of MIN_CNT field.
	UART_LOWPULSE_MIN_CNT_Msk = 0xfff

	// HIGHPULSE: Autobaud minimum high pulse duration register
	// Position of MIN_CNT field.
	UART_HIGHPULSE_MIN_CNT_Pos = 0x0
	// Bit mask of MIN_CNT field.
	UART_HIGHPULSE_MIN_CNT_Msk = 0xfff

	// RXD_CNT: Autobaud edge change count register
	// Position of RXD_EDGE_CNT field.
	UART_RXD_CNT_RXD_EDGE_CNT_Pos = 0x0
	// Bit mask of RXD_EDGE_CNT field.
	UART_RXD_CNT_RXD_EDGE_CNT_Msk = 0x3ff

	// CLK_CONF: UART core clock configuration
	// Position of TX_SCLK_EN field.
	UART_CLK_CONF_TX_SCLK_EN_Pos = 0x18
	// Bit mask of TX_SCLK_EN field.
	UART_CLK_CONF_TX_SCLK_EN_Msk = 0x1000000
	// Bit TX_SCLK_EN.
	UART_CLK_CONF_TX_SCLK_EN = 0x1000000
	// Position of RX_SCLK_EN field.
	UART_CLK_CONF_RX_SCLK_EN_Pos = 0x19
	// Bit mask of RX_SCLK_EN field.
	UART_CLK_CONF_RX_SCLK_EN_Msk = 0x2000000
	// Bit RX_SCLK_EN.
	UART_CLK_CONF_RX_SCLK_EN = 0x2000000
	// Position of TX_RST_CORE field.
	UART_CLK_CONF_TX_RST_CORE_Pos = 0x1a
	// Bit mask of TX_RST_CORE field.
	UART_CLK_CONF_TX_RST_CORE_Msk = 0x4000000
	// Bit TX_RST_CORE.
	UART_CLK_CONF_TX_RST_CORE = 0x4000000
	// Position of RX_RST_CORE field.
	UART_CLK_CONF_RX_RST_CORE_Pos = 0x1b
	// Bit mask of RX_RST_CORE field.
	UART_CLK_CONF_RX_RST_CORE_Msk = 0x8000000
	// Bit RX_RST_CORE.
	UART_CLK_CONF_RX_RST_CORE = 0x8000000

	// DATE: UART Version register
	// Position of DATE field.
	UART_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	UART_DATE_DATE_Msk = 0xffffffff

	// AFIFO_STATUS: UART AFIFO Status
	// Position of TX_AFIFO_FULL field.
	UART_AFIFO_STATUS_TX_AFIFO_FULL_Pos = 0x0
	// Bit mask of TX_AFIFO_FULL field.
	UART_AFIFO_STATUS_TX_AFIFO_FULL_Msk = 0x1
	// Bit TX_AFIFO_FULL.
	UART_AFIFO_STATUS_TX_AFIFO_FULL = 0x1
	// Position of TX_AFIFO_EMPTY field.
	UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Pos = 0x1
	// Bit mask of TX_AFIFO_EMPTY field.
	UART_AFIFO_STATUS_TX_AFIFO_EMPTY_Msk = 0x2
	// Bit TX_AFIFO_EMPTY.
	UART_AFIFO_STATUS_TX_AFIFO_EMPTY = 0x2
	// Position of RX_AFIFO_FULL field.
	UART_AFIFO_STATUS_RX_AFIFO_FULL_Pos = 0x2
	// Bit mask of RX_AFIFO_FULL field.
	UART_AFIFO_STATUS_RX_AFIFO_FULL_Msk = 0x4
	// Bit RX_AFIFO_FULL.
	UART_AFIFO_STATUS_RX_AFIFO_FULL = 0x4
	// Position of RX_AFIFO_EMPTY field.
	UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Pos = 0x3
	// Bit mask of RX_AFIFO_EMPTY field.
	UART_AFIFO_STATUS_RX_AFIFO_EMPTY_Msk = 0x8
	// Bit RX_AFIFO_EMPTY.
	UART_AFIFO_STATUS_RX_AFIFO_EMPTY = 0x8

	// REG_UPDATE: UART Registers Configuration Update register
	// Position of REG_UPDATE field.
	UART_REG_UPDATE_REG_UPDATE_Pos = 0x0
	// Bit mask of REG_UPDATE field.
	UART_REG_UPDATE_REG_UPDATE_Msk = 0x1
	// Bit REG_UPDATE.
	UART_REG_UPDATE_REG_UPDATE = 0x1

	// ID: UART ID register
	// Position of ID field.
	UART_ID_ID_Pos = 0x0
	// Bit mask of ID field.
	UART_ID_ID_Msk = 0xffffffff
)

// Constants for UHCI0: Universal Host Controller Interface 0
const (
	// CONF0: UHCI Configuration Register0
	// Position of TX_RST field.
	UHCI_CONF0_TX_RST_Pos = 0x0
	// Bit mask of TX_RST field.
	UHCI_CONF0_TX_RST_Msk = 0x1
	// Bit TX_RST.
	UHCI_CONF0_TX_RST = 0x1
	// Position of RX_RST field.
	UHCI_CONF0_RX_RST_Pos = 0x1
	// Bit mask of RX_RST field.
	UHCI_CONF0_RX_RST_Msk = 0x2
	// Bit RX_RST.
	UHCI_CONF0_RX_RST = 0x2
	// Position of UART_SEL field.
	UHCI_CONF0_UART_SEL_Pos = 0x2
	// Bit mask of UART_SEL field.
	UHCI_CONF0_UART_SEL_Msk = 0x1c
	// Position of SEPER_EN field.
	UHCI_CONF0_SEPER_EN_Pos = 0x5
	// Bit mask of SEPER_EN field.
	UHCI_CONF0_SEPER_EN_Msk = 0x20
	// Bit SEPER_EN.
	UHCI_CONF0_SEPER_EN = 0x20
	// Position of HEAD_EN field.
	UHCI_CONF0_HEAD_EN_Pos = 0x6
	// Bit mask of HEAD_EN field.
	UHCI_CONF0_HEAD_EN_Msk = 0x40
	// Bit HEAD_EN.
	UHCI_CONF0_HEAD_EN = 0x40
	// Position of CRC_REC_EN field.
	UHCI_CONF0_CRC_REC_EN_Pos = 0x7
	// Bit mask of CRC_REC_EN field.
	UHCI_CONF0_CRC_REC_EN_Msk = 0x80
	// Bit CRC_REC_EN.
	UHCI_CONF0_CRC_REC_EN = 0x80
	// Position of UART_IDLE_EOF_EN field.
	UHCI_CONF0_UART_IDLE_EOF_EN_Pos = 0x8
	// Bit mask of UART_IDLE_EOF_EN field.
	UHCI_CONF0_UART_IDLE_EOF_EN_Msk = 0x100
	// Bit UART_IDLE_EOF_EN.
	UHCI_CONF0_UART_IDLE_EOF_EN = 0x100
	// Position of LEN_EOF_EN field.
	UHCI_CONF0_LEN_EOF_EN_Pos = 0x9
	// Bit mask of LEN_EOF_EN field.
	UHCI_CONF0_LEN_EOF_EN_Msk = 0x200
	// Bit LEN_EOF_EN.
	UHCI_CONF0_LEN_EOF_EN = 0x200
	// Position of ENCODE_CRC_EN field.
	UHCI_CONF0_ENCODE_CRC_EN_Pos = 0xa
	// Bit mask of ENCODE_CRC_EN field.
	UHCI_CONF0_ENCODE_CRC_EN_Msk = 0x400
	// Bit ENCODE_CRC_EN.
	UHCI_CONF0_ENCODE_CRC_EN = 0x400
	// Position of CLK_EN field.
	UHCI_CONF0_CLK_EN_Pos = 0xb
	// Bit mask of CLK_EN field.
	UHCI_CONF0_CLK_EN_Msk = 0x800
	// Bit CLK_EN.
	UHCI_CONF0_CLK_EN = 0x800
	// Position of UART_RX_BRK_EOF_EN field.
	UHCI_CONF0_UART_RX_BRK_EOF_EN_Pos = 0xc
	// Bit mask of UART_RX_BRK_EOF_EN field.
	UHCI_CONF0_UART_RX_BRK_EOF_EN_Msk = 0x1000
	// Bit UART_RX_BRK_EOF_EN.
	UHCI_CONF0_UART_RX_BRK_EOF_EN = 0x1000

	// INT_RAW: UHCI Interrupt Raw Register
	// Position of RX_START_INT_RAW field.
	UHCI_INT_RAW_RX_START_INT_RAW_Pos = 0x0
	// Bit mask of RX_START_INT_RAW field.
	UHCI_INT_RAW_RX_START_INT_RAW_Msk = 0x1
	// Bit RX_START_INT_RAW.
	UHCI_INT_RAW_RX_START_INT_RAW = 0x1
	// Position of TX_START_INT_RAW field.
	UHCI_INT_RAW_TX_START_INT_RAW_Pos = 0x1
	// Bit mask of TX_START_INT_RAW field.
	UHCI_INT_RAW_TX_START_INT_RAW_Msk = 0x2
	// Bit TX_START_INT_RAW.
	UHCI_INT_RAW_TX_START_INT_RAW = 0x2
	// Position of RX_HUNG_INT_RAW field.
	UHCI_INT_RAW_RX_HUNG_INT_RAW_Pos = 0x2
	// Bit mask of RX_HUNG_INT_RAW field.
	UHCI_INT_RAW_RX_HUNG_INT_RAW_Msk = 0x4
	// Bit RX_HUNG_INT_RAW.
	UHCI_INT_RAW_RX_HUNG_INT_RAW = 0x4
	// Position of TX_HUNG_INT_RAW field.
	UHCI_INT_RAW_TX_HUNG_INT_RAW_Pos = 0x3
	// Bit mask of TX_HUNG_INT_RAW field.
	UHCI_INT_RAW_TX_HUNG_INT_RAW_Msk = 0x8
	// Bit TX_HUNG_INT_RAW.
	UHCI_INT_RAW_TX_HUNG_INT_RAW = 0x8
	// Position of SEND_S_REG_Q_INT_RAW field.
	UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Pos = 0x4
	// Bit mask of SEND_S_REG_Q_INT_RAW field.
	UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW_Msk = 0x10
	// Bit SEND_S_REG_Q_INT_RAW.
	UHCI_INT_RAW_SEND_S_REG_Q_INT_RAW = 0x10
	// Position of SEND_A_REG_Q_INT_RAW field.
	UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Pos = 0x5
	// Bit mask of SEND_A_REG_Q_INT_RAW field.
	UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW_Msk = 0x20
	// Bit SEND_A_REG_Q_INT_RAW.
	UHCI_INT_RAW_SEND_A_REG_Q_INT_RAW = 0x20
	// Position of OUT_EOF_INT_RAW field.
	UHCI_INT_RAW_OUT_EOF_INT_RAW_Pos = 0x6
	// Bit mask of OUT_EOF_INT_RAW field.
	UHCI_INT_RAW_OUT_EOF_INT_RAW_Msk = 0x40
	// Bit OUT_EOF_INT_RAW.
	UHCI_INT_RAW_OUT_EOF_INT_RAW = 0x40
	// Position of APP_CTRL0_INT_RAW field.
	UHCI_INT_RAW_APP_CTRL0_INT_RAW_Pos = 0x7
	// Bit mask of APP_CTRL0_INT_RAW field.
	UHCI_INT_RAW_APP_CTRL0_INT_RAW_Msk = 0x80
	// Bit APP_CTRL0_INT_RAW.
	UHCI_INT_RAW_APP_CTRL0_INT_RAW = 0x80
	// Position of APP_CTRL1_INT_RAW field.
	UHCI_INT_RAW_APP_CTRL1_INT_RAW_Pos = 0x8
	// Bit mask of APP_CTRL1_INT_RAW field.
	UHCI_INT_RAW_APP_CTRL1_INT_RAW_Msk = 0x100
	// Bit APP_CTRL1_INT_RAW.
	UHCI_INT_RAW_APP_CTRL1_INT_RAW = 0x100

	// INT_ST: UHCI Interrupt Status Register
	// Position of RX_START_INT_ST field.
	UHCI_INT_ST_RX_START_INT_ST_Pos = 0x0
	// Bit mask of RX_START_INT_ST field.
	UHCI_INT_ST_RX_START_INT_ST_Msk = 0x1
	// Bit RX_START_INT_ST.
	UHCI_INT_ST_RX_START_INT_ST = 0x1
	// Position of TX_START_INT_ST field.
	UHCI_INT_ST_TX_START_INT_ST_Pos = 0x1
	// Bit mask of TX_START_INT_ST field.
	UHCI_INT_ST_TX_START_INT_ST_Msk = 0x2
	// Bit TX_START_INT_ST.
	UHCI_INT_ST_TX_START_INT_ST = 0x2
	// Position of RX_HUNG_INT_ST field.
	UHCI_INT_ST_RX_HUNG_INT_ST_Pos = 0x2
	// Bit mask of RX_HUNG_INT_ST field.
	UHCI_INT_ST_RX_HUNG_INT_ST_Msk = 0x4
	// Bit RX_HUNG_INT_ST.
	UHCI_INT_ST_RX_HUNG_INT_ST = 0x4
	// Position of TX_HUNG_INT_ST field.
	UHCI_INT_ST_TX_HUNG_INT_ST_Pos = 0x3
	// Bit mask of TX_HUNG_INT_ST field.
	UHCI_INT_ST_TX_HUNG_INT_ST_Msk = 0x8
	// Bit TX_HUNG_INT_ST.
	UHCI_INT_ST_TX_HUNG_INT_ST = 0x8
	// Position of SEND_S_REG_Q_INT_ST field.
	UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Pos = 0x4
	// Bit mask of SEND_S_REG_Q_INT_ST field.
	UHCI_INT_ST_SEND_S_REG_Q_INT_ST_Msk = 0x10
	// Bit SEND_S_REG_Q_INT_ST.
	UHCI_INT_ST_SEND_S_REG_Q_INT_ST = 0x10
	// Position of SEND_A_REG_Q_INT_ST field.
	UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Pos = 0x5
	// Bit mask of SEND_A_REG_Q_INT_ST field.
	UHCI_INT_ST_SEND_A_REG_Q_INT_ST_Msk = 0x20
	// Bit SEND_A_REG_Q_INT_ST.
	UHCI_INT_ST_SEND_A_REG_Q_INT_ST = 0x20
	// Position of OUTLINK_EOF_ERR_INT_ST field.
	UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Pos = 0x6
	// Bit mask of OUTLINK_EOF_ERR_INT_ST field.
	UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST_Msk = 0x40
	// Bit OUTLINK_EOF_ERR_INT_ST.
	UHCI_INT_ST_OUTLINK_EOF_ERR_INT_ST = 0x40
	// Position of APP_CTRL0_INT_ST field.
	UHCI_INT_ST_APP_CTRL0_INT_ST_Pos = 0x7
	// Bit mask of APP_CTRL0_INT_ST field.
	UHCI_INT_ST_APP_CTRL0_INT_ST_Msk = 0x80
	// Bit APP_CTRL0_INT_ST.
	UHCI_INT_ST_APP_CTRL0_INT_ST = 0x80
	// Position of APP_CTRL1_INT_ST field.
	UHCI_INT_ST_APP_CTRL1_INT_ST_Pos = 0x8
	// Bit mask of APP_CTRL1_INT_ST field.
	UHCI_INT_ST_APP_CTRL1_INT_ST_Msk = 0x100
	// Bit APP_CTRL1_INT_ST.
	UHCI_INT_ST_APP_CTRL1_INT_ST = 0x100

	// INT_ENA: UHCI Interrupt Enable Register
	// Position of RX_START_INT_ENA field.
	UHCI_INT_ENA_RX_START_INT_ENA_Pos = 0x0
	// Bit mask of RX_START_INT_ENA field.
	UHCI_INT_ENA_RX_START_INT_ENA_Msk = 0x1
	// Bit RX_START_INT_ENA.
	UHCI_INT_ENA_RX_START_INT_ENA = 0x1
	// Position of TX_START_INT_ENA field.
	UHCI_INT_ENA_TX_START_INT_ENA_Pos = 0x1
	// Bit mask of TX_START_INT_ENA field.
	UHCI_INT_ENA_TX_START_INT_ENA_Msk = 0x2
	// Bit TX_START_INT_ENA.
	UHCI_INT_ENA_TX_START_INT_ENA = 0x2
	// Position of RX_HUNG_INT_ENA field.
	UHCI_INT_ENA_RX_HUNG_INT_ENA_Pos = 0x2
	// Bit mask of RX_HUNG_INT_ENA field.
	UHCI_INT_ENA_RX_HUNG_INT_ENA_Msk = 0x4
	// Bit RX_HUNG_INT_ENA.
	UHCI_INT_ENA_RX_HUNG_INT_ENA = 0x4
	// Position of TX_HUNG_INT_ENA field.
	UHCI_INT_ENA_TX_HUNG_INT_ENA_Pos = 0x3
	// Bit mask of TX_HUNG_INT_ENA field.
	UHCI_INT_ENA_TX_HUNG_INT_ENA_Msk = 0x8
	// Bit TX_HUNG_INT_ENA.
	UHCI_INT_ENA_TX_HUNG_INT_ENA = 0x8
	// Position of SEND_S_REG_Q_INT_ENA field.
	UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Pos = 0x4
	// Bit mask of SEND_S_REG_Q_INT_ENA field.
	UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA_Msk = 0x10
	// Bit SEND_S_REG_Q_INT_ENA.
	UHCI_INT_ENA_SEND_S_REG_Q_INT_ENA = 0x10
	// Position of SEND_A_REG_Q_INT_ENA field.
	UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Pos = 0x5
	// Bit mask of SEND_A_REG_Q_INT_ENA field.
	UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA_Msk = 0x20
	// Bit SEND_A_REG_Q_INT_ENA.
	UHCI_INT_ENA_SEND_A_REG_Q_INT_ENA = 0x20
	// Position of OUTLINK_EOF_ERR_INT_ENA field.
	UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Pos = 0x6
	// Bit mask of OUTLINK_EOF_ERR_INT_ENA field.
	UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA_Msk = 0x40
	// Bit OUTLINK_EOF_ERR_INT_ENA.
	UHCI_INT_ENA_OUTLINK_EOF_ERR_INT_ENA = 0x40
	// Position of APP_CTRL0_INT_ENA field.
	UHCI_INT_ENA_APP_CTRL0_INT_ENA_Pos = 0x7
	// Bit mask of APP_CTRL0_INT_ENA field.
	UHCI_INT_ENA_APP_CTRL0_INT_ENA_Msk = 0x80
	// Bit APP_CTRL0_INT_ENA.
	UHCI_INT_ENA_APP_CTRL0_INT_ENA = 0x80
	// Position of APP_CTRL1_INT_ENA field.
	UHCI_INT_ENA_APP_CTRL1_INT_ENA_Pos = 0x8
	// Bit mask of APP_CTRL1_INT_ENA field.
	UHCI_INT_ENA_APP_CTRL1_INT_ENA_Msk = 0x100
	// Bit APP_CTRL1_INT_ENA.
	UHCI_INT_ENA_APP_CTRL1_INT_ENA = 0x100

	// INT_CLR: UHCI Interrupt Clear Register
	// Position of RX_START_INT_CLR field.
	UHCI_INT_CLR_RX_START_INT_CLR_Pos = 0x0
	// Bit mask of RX_START_INT_CLR field.
	UHCI_INT_CLR_RX_START_INT_CLR_Msk = 0x1
	// Bit RX_START_INT_CLR.
	UHCI_INT_CLR_RX_START_INT_CLR = 0x1
	// Position of TX_START_INT_CLR field.
	UHCI_INT_CLR_TX_START_INT_CLR_Pos = 0x1
	// Bit mask of TX_START_INT_CLR field.
	UHCI_INT_CLR_TX_START_INT_CLR_Msk = 0x2
	// Bit TX_START_INT_CLR.
	UHCI_INT_CLR_TX_START_INT_CLR = 0x2
	// Position of RX_HUNG_INT_CLR field.
	UHCI_INT_CLR_RX_HUNG_INT_CLR_Pos = 0x2
	// Bit mask of RX_HUNG_INT_CLR field.
	UHCI_INT_CLR_RX_HUNG_INT_CLR_Msk = 0x4
	// Bit RX_HUNG_INT_CLR.
	UHCI_INT_CLR_RX_HUNG_INT_CLR = 0x4
	// Position of TX_HUNG_INT_CLR field.
	UHCI_INT_CLR_TX_HUNG_INT_CLR_Pos = 0x3
	// Bit mask of TX_HUNG_INT_CLR field.
	UHCI_INT_CLR_TX_HUNG_INT_CLR_Msk = 0x8
	// Bit TX_HUNG_INT_CLR.
	UHCI_INT_CLR_TX_HUNG_INT_CLR = 0x8
	// Position of SEND_S_REG_Q_INT_CLR field.
	UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Pos = 0x4
	// Bit mask of SEND_S_REG_Q_INT_CLR field.
	UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR_Msk = 0x10
	// Bit SEND_S_REG_Q_INT_CLR.
	UHCI_INT_CLR_SEND_S_REG_Q_INT_CLR = 0x10
	// Position of SEND_A_REG_Q_INT_CLR field.
	UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Pos = 0x5
	// Bit mask of SEND_A_REG_Q_INT_CLR field.
	UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR_Msk = 0x20
	// Bit SEND_A_REG_Q_INT_CLR.
	UHCI_INT_CLR_SEND_A_REG_Q_INT_CLR = 0x20
	// Position of OUTLINK_EOF_ERR_INT_CLR field.
	UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Pos = 0x6
	// Bit mask of OUTLINK_EOF_ERR_INT_CLR field.
	UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR_Msk = 0x40
	// Bit OUTLINK_EOF_ERR_INT_CLR.
	UHCI_INT_CLR_OUTLINK_EOF_ERR_INT_CLR = 0x40
	// Position of APP_CTRL0_INT_CLR field.
	UHCI_INT_CLR_APP_CTRL0_INT_CLR_Pos = 0x7
	// Bit mask of APP_CTRL0_INT_CLR field.
	UHCI_INT_CLR_APP_CTRL0_INT_CLR_Msk = 0x80
	// Bit APP_CTRL0_INT_CLR.
	UHCI_INT_CLR_APP_CTRL0_INT_CLR = 0x80
	// Position of APP_CTRL1_INT_CLR field.
	UHCI_INT_CLR_APP_CTRL1_INT_CLR_Pos = 0x8
	// Bit mask of APP_CTRL1_INT_CLR field.
	UHCI_INT_CLR_APP_CTRL1_INT_CLR_Msk = 0x100
	// Bit APP_CTRL1_INT_CLR.
	UHCI_INT_CLR_APP_CTRL1_INT_CLR = 0x100

	// CONF1: UHCI Configuration Register1
	// Position of CHECK_SUM_EN field.
	UHCI_CONF1_CHECK_SUM_EN_Pos = 0x0
	// Bit mask of CHECK_SUM_EN field.
	UHCI_CONF1_CHECK_SUM_EN_Msk = 0x1
	// Bit CHECK_SUM_EN.
	UHCI_CONF1_CHECK_SUM_EN = 0x1
	// Position of CHECK_SEQ_EN field.
	UHCI_CONF1_CHECK_SEQ_EN_Pos = 0x1
	// Bit mask of CHECK_SEQ_EN field.
	UHCI_CONF1_CHECK_SEQ_EN_Msk = 0x2
	// Bit CHECK_SEQ_EN.
	UHCI_CONF1_CHECK_SEQ_EN = 0x2
	// Position of CRC_DISABLE field.
	UHCI_CONF1_CRC_DISABLE_Pos = 0x2
	// Bit mask of CRC_DISABLE field.
	UHCI_CONF1_CRC_DISABLE_Msk = 0x4
	// Bit CRC_DISABLE.
	UHCI_CONF1_CRC_DISABLE = 0x4
	// Position of SAVE_HEAD field.
	UHCI_CONF1_SAVE_HEAD_Pos = 0x3
	// Bit mask of SAVE_HEAD field.
	UHCI_CONF1_SAVE_HEAD_Msk = 0x8
	// Bit SAVE_HEAD.
	UHCI_CONF1_SAVE_HEAD = 0x8
	// Position of TX_CHECK_SUM_RE field.
	UHCI_CONF1_TX_CHECK_SUM_RE_Pos = 0x4
	// Bit mask of TX_CHECK_SUM_RE field.
	UHCI_CONF1_TX_CHECK_SUM_RE_Msk = 0x10
	// Bit TX_CHECK_SUM_RE.
	UHCI_CONF1_TX_CHECK_SUM_RE = 0x10
	// Position of TX_ACK_NUM_RE field.
	UHCI_CONF1_TX_ACK_NUM_RE_Pos = 0x5
	// Bit mask of TX_ACK_NUM_RE field.
	UHCI_CONF1_TX_ACK_NUM_RE_Msk = 0x20
	// Bit TX_ACK_NUM_RE.
	UHCI_CONF1_TX_ACK_NUM_RE = 0x20
	// Position of WAIT_SW_START field.
	UHCI_CONF1_WAIT_SW_START_Pos = 0x7
	// Bit mask of WAIT_SW_START field.
	UHCI_CONF1_WAIT_SW_START_Msk = 0x80
	// Bit WAIT_SW_START.
	UHCI_CONF1_WAIT_SW_START = 0x80
	// Position of SW_START field.
	UHCI_CONF1_SW_START_Pos = 0x8
	// Bit mask of SW_START field.
	UHCI_CONF1_SW_START_Msk = 0x100
	// Bit SW_START.
	UHCI_CONF1_SW_START = 0x100

	// STATE0: UHCI Receive Status Register
	// Position of RX_ERR_CAUSE field.
	UHCI_STATE0_RX_ERR_CAUSE_Pos = 0x0
	// Bit mask of RX_ERR_CAUSE field.
	UHCI_STATE0_RX_ERR_CAUSE_Msk = 0x7
	// Position of DECODE_STATE field.
	UHCI_STATE0_DECODE_STATE_Pos = 0x3
	// Bit mask of DECODE_STATE field.
	UHCI_STATE0_DECODE_STATE_Msk = 0x38

	// STATE1: UHCI Transmit Status Register
	// Position of ENCODE_STATE field.
	UHCI_STATE1_ENCODE_STATE_Pos = 0x0
	// Bit mask of ENCODE_STATE field.
	UHCI_STATE1_ENCODE_STATE_Msk = 0x7

	// ESCAPE_CONF: UHCI Escapes Configuration Register0
	// Position of TX_C0_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Pos = 0x0
	// Bit mask of TX_C0_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_C0_ESC_EN_Msk = 0x1
	// Bit TX_C0_ESC_EN.
	UHCI_ESCAPE_CONF_TX_C0_ESC_EN = 0x1
	// Position of TX_DB_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Pos = 0x1
	// Bit mask of TX_DB_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_DB_ESC_EN_Msk = 0x2
	// Bit TX_DB_ESC_EN.
	UHCI_ESCAPE_CONF_TX_DB_ESC_EN = 0x2
	// Position of TX_11_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_11_ESC_EN_Pos = 0x2
	// Bit mask of TX_11_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_11_ESC_EN_Msk = 0x4
	// Bit TX_11_ESC_EN.
	UHCI_ESCAPE_CONF_TX_11_ESC_EN = 0x4
	// Position of TX_13_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_13_ESC_EN_Pos = 0x3
	// Bit mask of TX_13_ESC_EN field.
	UHCI_ESCAPE_CONF_TX_13_ESC_EN_Msk = 0x8
	// Bit TX_13_ESC_EN.
	UHCI_ESCAPE_CONF_TX_13_ESC_EN = 0x8
	// Position of RX_C0_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Pos = 0x4
	// Bit mask of RX_C0_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_C0_ESC_EN_Msk = 0x10
	// Bit RX_C0_ESC_EN.
	UHCI_ESCAPE_CONF_RX_C0_ESC_EN = 0x10
	// Position of RX_DB_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Pos = 0x5
	// Bit mask of RX_DB_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_DB_ESC_EN_Msk = 0x20
	// Bit RX_DB_ESC_EN.
	UHCI_ESCAPE_CONF_RX_DB_ESC_EN = 0x20
	// Position of RX_11_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_11_ESC_EN_Pos = 0x6
	// Bit mask of RX_11_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_11_ESC_EN_Msk = 0x40
	// Bit RX_11_ESC_EN.
	UHCI_ESCAPE_CONF_RX_11_ESC_EN = 0x40
	// Position of RX_13_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_13_ESC_EN_Pos = 0x7
	// Bit mask of RX_13_ESC_EN field.
	UHCI_ESCAPE_CONF_RX_13_ESC_EN_Msk = 0x80
	// Bit RX_13_ESC_EN.
	UHCI_ESCAPE_CONF_RX_13_ESC_EN = 0x80

	// HUNG_CONF: UHCI Hung Configuration Register0
	// Position of TXFIFO_TIMEOUT field.
	UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Pos = 0x0
	// Bit mask of TXFIFO_TIMEOUT field.
	UHCI_HUNG_CONF_TXFIFO_TIMEOUT_Msk = 0xff
	// Position of TXFIFO_TIMEOUT_SHIFT field.
	UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Pos = 0x8
	// Bit mask of TXFIFO_TIMEOUT_SHIFT field.
	UHCI_HUNG_CONF_TXFIFO_TIMEOUT_SHIFT_Msk = 0x700
	// Position of TXFIFO_TIMEOUT_ENA field.
	UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Pos = 0xb
	// Bit mask of TXFIFO_TIMEOUT_ENA field.
	UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA_Msk = 0x800
	// Bit TXFIFO_TIMEOUT_ENA.
	UHCI_HUNG_CONF_TXFIFO_TIMEOUT_ENA = 0x800
	// Position of RXFIFO_TIMEOUT field.
	UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Pos = 0xc
	// Bit mask of RXFIFO_TIMEOUT field.
	UHCI_HUNG_CONF_RXFIFO_TIMEOUT_Msk = 0xff000
	// Position of RXFIFO_TIMEOUT_SHIFT field.
	UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Pos = 0x14
	// Bit mask of RXFIFO_TIMEOUT_SHIFT field.
	UHCI_HUNG_CONF_RXFIFO_TIMEOUT_SHIFT_Msk = 0x700000
	// Position of RXFIFO_TIMEOUT_ENA field.
	UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Pos = 0x17
	// Bit mask of RXFIFO_TIMEOUT_ENA field.
	UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA_Msk = 0x800000
	// Bit RXFIFO_TIMEOUT_ENA.
	UHCI_HUNG_CONF_RXFIFO_TIMEOUT_ENA = 0x800000

	// ACK_NUM: UHCI Ack Value Configuration Register0
	// Position of ACK_NUM field.
	UHCI_ACK_NUM_ACK_NUM_Pos = 0x0
	// Bit mask of ACK_NUM field.
	UHCI_ACK_NUM_ACK_NUM_Msk = 0x7
	// Position of LOAD field.
	UHCI_ACK_NUM_LOAD_Pos = 0x3
	// Bit mask of LOAD field.
	UHCI_ACK_NUM_LOAD_Msk = 0x8
	// Bit LOAD.
	UHCI_ACK_NUM_LOAD = 0x8

	// RX_HEAD: UHCI Head Register
	// Position of RX_HEAD field.
	UHCI_RX_HEAD_RX_HEAD_Pos = 0x0
	// Bit mask of RX_HEAD field.
	UHCI_RX_HEAD_RX_HEAD_Msk = 0xffffffff

	// QUICK_SENT: UCHI Quick send Register
	// Position of SINGLE_SEND_NUM field.
	UHCI_QUICK_SENT_SINGLE_SEND_NUM_Pos = 0x0
	// Bit mask of SINGLE_SEND_NUM field.
	UHCI_QUICK_SENT_SINGLE_SEND_NUM_Msk = 0x7
	// Position of SINGLE_SEND_EN field.
	UHCI_QUICK_SENT_SINGLE_SEND_EN_Pos = 0x3
	// Bit mask of SINGLE_SEND_EN field.
	UHCI_QUICK_SENT_SINGLE_SEND_EN_Msk = 0x8
	// Bit SINGLE_SEND_EN.
	UHCI_QUICK_SENT_SINGLE_SEND_EN = 0x8
	// Position of ALWAYS_SEND_NUM field.
	UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Pos = 0x4
	// Bit mask of ALWAYS_SEND_NUM field.
	UHCI_QUICK_SENT_ALWAYS_SEND_NUM_Msk = 0x70
	// Position of ALWAYS_SEND_EN field.
	UHCI_QUICK_SENT_ALWAYS_SEND_EN_Pos = 0x7
	// Bit mask of ALWAYS_SEND_EN field.
	UHCI_QUICK_SENT_ALWAYS_SEND_EN_Msk = 0x80
	// Bit ALWAYS_SEND_EN.
	UHCI_QUICK_SENT_ALWAYS_SEND_EN = 0x80

	// REG_Q0_WORD0: UHCI Q0_WORD0 Quick Send Register
	// Position of SEND_Q0_WORD0 field.
	UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Pos = 0x0
	// Bit mask of SEND_Q0_WORD0 field.
	UHCI_REG_Q0_WORD0_SEND_Q0_WORD0_Msk = 0xffffffff

	// REG_Q0_WORD1: UHCI Q0_WORD1 Quick Send Register
	// Position of SEND_Q0_WORD1 field.
	UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Pos = 0x0
	// Bit mask of SEND_Q0_WORD1 field.
	UHCI_REG_Q0_WORD1_SEND_Q0_WORD1_Msk = 0xffffffff

	// REG_Q1_WORD0: UHCI Q1_WORD0 Quick Send Register
	// Position of SEND_Q1_WORD0 field.
	UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Pos = 0x0
	// Bit mask of SEND_Q1_WORD0 field.
	UHCI_REG_Q1_WORD0_SEND_Q1_WORD0_Msk = 0xffffffff

	// REG_Q1_WORD1: UHCI Q1_WORD1 Quick Send Register
	// Position of SEND_Q1_WORD1 field.
	UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Pos = 0x0
	// Bit mask of SEND_Q1_WORD1 field.
	UHCI_REG_Q1_WORD1_SEND_Q1_WORD1_Msk = 0xffffffff

	// REG_Q2_WORD0: UHCI Q2_WORD0 Quick Send Register
	// Position of SEND_Q2_WORD0 field.
	UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Pos = 0x0
	// Bit mask of SEND_Q2_WORD0 field.
	UHCI_REG_Q2_WORD0_SEND_Q2_WORD0_Msk = 0xffffffff

	// REG_Q2_WORD1: UHCI Q2_WORD1 Quick Send Register
	// Position of SEND_Q2_WORD1 field.
	UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Pos = 0x0
	// Bit mask of SEND_Q2_WORD1 field.
	UHCI_REG_Q2_WORD1_SEND_Q2_WORD1_Msk = 0xffffffff

	// REG_Q3_WORD0: UHCI Q3_WORD0 Quick Send Register
	// Position of SEND_Q3_WORD0 field.
	UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Pos = 0x0
	// Bit mask of SEND_Q3_WORD0 field.
	UHCI_REG_Q3_WORD0_SEND_Q3_WORD0_Msk = 0xffffffff

	// REG_Q3_WORD1: UHCI Q3_WORD1 Quick Send Register
	// Position of SEND_Q3_WORD1 field.
	UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Pos = 0x0
	// Bit mask of SEND_Q3_WORD1 field.
	UHCI_REG_Q3_WORD1_SEND_Q3_WORD1_Msk = 0xffffffff

	// REG_Q4_WORD0: UHCI Q4_WORD0 Quick Send Register
	// Position of SEND_Q4_WORD0 field.
	UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Pos = 0x0
	// Bit mask of SEND_Q4_WORD0 field.
	UHCI_REG_Q4_WORD0_SEND_Q4_WORD0_Msk = 0xffffffff

	// REG_Q4_WORD1: UHCI Q4_WORD1 Quick Send Register
	// Position of SEND_Q4_WORD1 field.
	UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Pos = 0x0
	// Bit mask of SEND_Q4_WORD1 field.
	UHCI_REG_Q4_WORD1_SEND_Q4_WORD1_Msk = 0xffffffff

	// REG_Q5_WORD0: UHCI Q5_WORD0 Quick Send Register
	// Position of SEND_Q5_WORD0 field.
	UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Pos = 0x0
	// Bit mask of SEND_Q5_WORD0 field.
	UHCI_REG_Q5_WORD0_SEND_Q5_WORD0_Msk = 0xffffffff

	// REG_Q5_WORD1: UHCI Q5_WORD1 Quick Send Register
	// Position of SEND_Q5_WORD1 field.
	UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Pos = 0x0
	// Bit mask of SEND_Q5_WORD1 field.
	UHCI_REG_Q5_WORD1_SEND_Q5_WORD1_Msk = 0xffffffff

	// REG_Q6_WORD0: UHCI Q6_WORD0 Quick Send Register
	// Position of SEND_Q6_WORD0 field.
	UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Pos = 0x0
	// Bit mask of SEND_Q6_WORD0 field.
	UHCI_REG_Q6_WORD0_SEND_Q6_WORD0_Msk = 0xffffffff

	// REG_Q6_WORD1: UHCI Q6_WORD1 Quick Send Register
	// Position of SEND_Q6_WORD1 field.
	UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Pos = 0x0
	// Bit mask of SEND_Q6_WORD1 field.
	UHCI_REG_Q6_WORD1_SEND_Q6_WORD1_Msk = 0xffffffff

	// ESC_CONF0: UHCI Escapes Sequence Configuration Register0
	// Position of SEPER_CHAR field.
	UHCI_ESC_CONF0_SEPER_CHAR_Pos = 0x0
	// Bit mask of SEPER_CHAR field.
	UHCI_ESC_CONF0_SEPER_CHAR_Msk = 0xff
	// Position of SEPER_ESC_CHAR0 field.
	UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Pos = 0x8
	// Bit mask of SEPER_ESC_CHAR0 field.
	UHCI_ESC_CONF0_SEPER_ESC_CHAR0_Msk = 0xff00
	// Position of SEPER_ESC_CHAR1 field.
	UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Pos = 0x10
	// Bit mask of SEPER_ESC_CHAR1 field.
	UHCI_ESC_CONF0_SEPER_ESC_CHAR1_Msk = 0xff0000

	// ESC_CONF1: UHCI Escapes Sequence Configuration Register1
	// Position of ESC_SEQ0 field.
	UHCI_ESC_CONF1_ESC_SEQ0_Pos = 0x0
	// Bit mask of ESC_SEQ0 field.
	UHCI_ESC_CONF1_ESC_SEQ0_Msk = 0xff
	// Position of ESC_SEQ0_CHAR0 field.
	UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Pos = 0x8
	// Bit mask of ESC_SEQ0_CHAR0 field.
	UHCI_ESC_CONF1_ESC_SEQ0_CHAR0_Msk = 0xff00
	// Position of ESC_SEQ0_CHAR1 field.
	UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Pos = 0x10
	// Bit mask of ESC_SEQ0_CHAR1 field.
	UHCI_ESC_CONF1_ESC_SEQ0_CHAR1_Msk = 0xff0000

	// ESC_CONF2: UHCI Escapes Sequence Configuration Register2
	// Position of ESC_SEQ1 field.
	UHCI_ESC_CONF2_ESC_SEQ1_Pos = 0x0
	// Bit mask of ESC_SEQ1 field.
	UHCI_ESC_CONF2_ESC_SEQ1_Msk = 0xff
	// Position of ESC_SEQ1_CHAR0 field.
	UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Pos = 0x8
	// Bit mask of ESC_SEQ1_CHAR0 field.
	UHCI_ESC_CONF2_ESC_SEQ1_CHAR0_Msk = 0xff00
	// Position of ESC_SEQ1_CHAR1 field.
	UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Pos = 0x10
	// Bit mask of ESC_SEQ1_CHAR1 field.
	UHCI_ESC_CONF2_ESC_SEQ1_CHAR1_Msk = 0xff0000

	// ESC_CONF3: UHCI Escapes Sequence Configuration Register3
	// Position of ESC_SEQ2 field.
	UHCI_ESC_CONF3_ESC_SEQ2_Pos = 0x0
	// Bit mask of ESC_SEQ2 field.
	UHCI_ESC_CONF3_ESC_SEQ2_Msk = 0xff
	// Position of ESC_SEQ2_CHAR0 field.
	UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Pos = 0x8
	// Bit mask of ESC_SEQ2_CHAR0 field.
	UHCI_ESC_CONF3_ESC_SEQ2_CHAR0_Msk = 0xff00
	// Position of ESC_SEQ2_CHAR1 field.
	UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Pos = 0x10
	// Bit mask of ESC_SEQ2_CHAR1 field.
	UHCI_ESC_CONF3_ESC_SEQ2_CHAR1_Msk = 0xff0000

	// PKT_THRES: UCHI Packet Length Configuration Register
	// Position of PKT_THRS field.
	UHCI_PKT_THRES_PKT_THRS_Pos = 0x0
	// Bit mask of PKT_THRS field.
	UHCI_PKT_THRES_PKT_THRS_Msk = 0x1fff

	// DATE: UHCI Version Register
	// Position of DATE field.
	UHCI_DATE_DATE_Pos = 0x0
	// Bit mask of DATE field.
	UHCI_DATE_DATE_Msk = 0xffffffff
)

// Constants for USB_DEVICE: Full-speed USB Serial/JTAG Controller
const (
	// EP1: FIFO access for the CDC-ACM data IN and OUT endpoints.
	// Position of USB_SERIAL_JTAG_RDWR_BYTE field.
	USB_DEVICE_EP1_USB_SERIAL_JTAG_RDWR_BYTE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RDWR_BYTE field.
	USB_DEVICE_EP1_USB_SERIAL_JTAG_RDWR_BYTE_Msk = 0xff

	// EP1_CONF: Configuration and control registers for the CDC-ACM FIFOs.
	// Position of USB_SERIAL_JTAG_WR_DONE field.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_WR_DONE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_WR_DONE field.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_WR_DONE_Msk = 0x1
	// Bit USB_SERIAL_JTAG_WR_DONE.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_WR_DONE = 0x1
	// Position of USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE field.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE field.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_Msk = 0x2
	// Bit USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE = 0x2
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL field.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL field.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_Msk = 0x4
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL.
	USB_DEVICE_EP1_CONF_USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL = 0x4

	// INT_RAW: Interrupt raw status register.
	// Position of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_Msk = 0x1
	// Bit USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW = 0x1
	// Position of USB_SERIAL_JTAG_SOF_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SOF_INT_RAW_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_SOF_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SOF_INT_RAW_Msk = 0x2
	// Bit USB_SERIAL_JTAG_SOF_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SOF_INT_RAW = 0x2
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_Msk = 0x4
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW = 0x4
	// Position of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_Msk = 0x8
	// Bit USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW = 0x8
	// Position of USB_SERIAL_JTAG_PID_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_PID_ERR_INT_RAW_Pos = 0x4
	// Bit mask of USB_SERIAL_JTAG_PID_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_PID_ERR_INT_RAW_Msk = 0x10
	// Bit USB_SERIAL_JTAG_PID_ERR_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_PID_ERR_INT_RAW = 0x10
	// Position of USB_SERIAL_JTAG_CRC5_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_Pos = 0x5
	// Bit mask of USB_SERIAL_JTAG_CRC5_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_Msk = 0x20
	// Bit USB_SERIAL_JTAG_CRC5_ERR_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_CRC5_ERR_INT_RAW = 0x20
	// Position of USB_SERIAL_JTAG_CRC16_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_Pos = 0x6
	// Bit mask of USB_SERIAL_JTAG_CRC16_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_Msk = 0x40
	// Bit USB_SERIAL_JTAG_CRC16_ERR_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_CRC16_ERR_INT_RAW = 0x40
	// Position of USB_SERIAL_JTAG_STUFF_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_Pos = 0x7
	// Bit mask of USB_SERIAL_JTAG_STUFF_ERR_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_Msk = 0x80
	// Bit USB_SERIAL_JTAG_STUFF_ERR_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_STUFF_ERR_INT_RAW = 0x80
	// Position of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_Msk = 0x100
	// Bit USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW = 0x100
	// Position of USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_Msk = 0x200
	// Bit USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW = 0x200
	// Position of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Pos = 0xa
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_Msk = 0x400
	// Bit USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW = 0x400
	// Position of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Pos = 0xb
	// Bit mask of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_Msk = 0x800
	// Bit USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW = 0x800
	// Position of USB_SERIAL_JTAG_RTS_CHG_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_RTS_CHG_INT_RAW_Pos = 0xc
	// Bit mask of USB_SERIAL_JTAG_RTS_CHG_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_RTS_CHG_INT_RAW_Msk = 0x1000
	// Bit USB_SERIAL_JTAG_RTS_CHG_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_RTS_CHG_INT_RAW = 0x1000
	// Position of USB_SERIAL_JTAG_DTR_CHG_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_DTR_CHG_INT_RAW_Pos = 0xd
	// Bit mask of USB_SERIAL_JTAG_DTR_CHG_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_DTR_CHG_INT_RAW_Msk = 0x2000
	// Bit USB_SERIAL_JTAG_DTR_CHG_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_DTR_CHG_INT_RAW = 0x2000
	// Position of USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_Pos = 0xe
	// Bit mask of USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_Msk = 0x4000
	// Bit USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW = 0x4000
	// Position of USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_Pos = 0xf
	// Bit mask of USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW field.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_Msk = 0x8000
	// Bit USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW.
	USB_DEVICE_INT_RAW_USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW = 0x8000

	// INT_ST: Interrupt status register.
	// Position of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_Msk = 0x1
	// Bit USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST = 0x1
	// Position of USB_SERIAL_JTAG_SOF_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SOF_INT_ST_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_SOF_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SOF_INT_ST_Msk = 0x2
	// Bit USB_SERIAL_JTAG_SOF_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SOF_INT_ST = 0x2
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_Msk = 0x4
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST = 0x4
	// Position of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_Msk = 0x8
	// Bit USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST = 0x8
	// Position of USB_SERIAL_JTAG_PID_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_PID_ERR_INT_ST_Pos = 0x4
	// Bit mask of USB_SERIAL_JTAG_PID_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_PID_ERR_INT_ST_Msk = 0x10
	// Bit USB_SERIAL_JTAG_PID_ERR_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_PID_ERR_INT_ST = 0x10
	// Position of USB_SERIAL_JTAG_CRC5_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_CRC5_ERR_INT_ST_Pos = 0x5
	// Bit mask of USB_SERIAL_JTAG_CRC5_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_CRC5_ERR_INT_ST_Msk = 0x20
	// Bit USB_SERIAL_JTAG_CRC5_ERR_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_CRC5_ERR_INT_ST = 0x20
	// Position of USB_SERIAL_JTAG_CRC16_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_CRC16_ERR_INT_ST_Pos = 0x6
	// Bit mask of USB_SERIAL_JTAG_CRC16_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_CRC16_ERR_INT_ST_Msk = 0x40
	// Bit USB_SERIAL_JTAG_CRC16_ERR_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_CRC16_ERR_INT_ST = 0x40
	// Position of USB_SERIAL_JTAG_STUFF_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_STUFF_ERR_INT_ST_Pos = 0x7
	// Bit mask of USB_SERIAL_JTAG_STUFF_ERR_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_STUFF_ERR_INT_ST_Msk = 0x80
	// Bit USB_SERIAL_JTAG_STUFF_ERR_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_STUFF_ERR_INT_ST = 0x80
	// Position of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_Msk = 0x100
	// Bit USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST = 0x100
	// Position of USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_Msk = 0x200
	// Bit USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST = 0x200
	// Position of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_Pos = 0xa
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_Msk = 0x400
	// Bit USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST = 0x400
	// Position of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_Pos = 0xb
	// Bit mask of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_Msk = 0x800
	// Bit USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST = 0x800
	// Position of USB_SERIAL_JTAG_RTS_CHG_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_RTS_CHG_INT_ST_Pos = 0xc
	// Bit mask of USB_SERIAL_JTAG_RTS_CHG_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_RTS_CHG_INT_ST_Msk = 0x1000
	// Bit USB_SERIAL_JTAG_RTS_CHG_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_RTS_CHG_INT_ST = 0x1000
	// Position of USB_SERIAL_JTAG_DTR_CHG_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_DTR_CHG_INT_ST_Pos = 0xd
	// Bit mask of USB_SERIAL_JTAG_DTR_CHG_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_DTR_CHG_INT_ST_Msk = 0x2000
	// Bit USB_SERIAL_JTAG_DTR_CHG_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_DTR_CHG_INT_ST = 0x2000
	// Position of USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_Pos = 0xe
	// Bit mask of USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_Msk = 0x4000
	// Bit USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST = 0x4000
	// Position of USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_Pos = 0xf
	// Bit mask of USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST field.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_Msk = 0x8000
	// Bit USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST.
	USB_DEVICE_INT_ST_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST = 0x8000

	// INT_ENA: Interrupt enable status register.
	// Position of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_Msk = 0x1
	// Bit USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA = 0x1
	// Position of USB_SERIAL_JTAG_SOF_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SOF_INT_ENA_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_SOF_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SOF_INT_ENA_Msk = 0x2
	// Bit USB_SERIAL_JTAG_SOF_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SOF_INT_ENA = 0x2
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_Msk = 0x4
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA = 0x4
	// Position of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_Msk = 0x8
	// Bit USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA = 0x8
	// Position of USB_SERIAL_JTAG_PID_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_PID_ERR_INT_ENA_Pos = 0x4
	// Bit mask of USB_SERIAL_JTAG_PID_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_PID_ERR_INT_ENA_Msk = 0x10
	// Bit USB_SERIAL_JTAG_PID_ERR_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_PID_ERR_INT_ENA = 0x10
	// Position of USB_SERIAL_JTAG_CRC5_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_Pos = 0x5
	// Bit mask of USB_SERIAL_JTAG_CRC5_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_Msk = 0x20
	// Bit USB_SERIAL_JTAG_CRC5_ERR_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_CRC5_ERR_INT_ENA = 0x20
	// Position of USB_SERIAL_JTAG_CRC16_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_Pos = 0x6
	// Bit mask of USB_SERIAL_JTAG_CRC16_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_Msk = 0x40
	// Bit USB_SERIAL_JTAG_CRC16_ERR_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_CRC16_ERR_INT_ENA = 0x40
	// Position of USB_SERIAL_JTAG_STUFF_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_Pos = 0x7
	// Bit mask of USB_SERIAL_JTAG_STUFF_ERR_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_Msk = 0x80
	// Bit USB_SERIAL_JTAG_STUFF_ERR_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_STUFF_ERR_INT_ENA = 0x80
	// Position of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_Msk = 0x100
	// Bit USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA = 0x100
	// Position of USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_Msk = 0x200
	// Bit USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA = 0x200
	// Position of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Pos = 0xa
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_Msk = 0x400
	// Bit USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA = 0x400
	// Position of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Pos = 0xb
	// Bit mask of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_Msk = 0x800
	// Bit USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA = 0x800
	// Position of USB_SERIAL_JTAG_RTS_CHG_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_RTS_CHG_INT_ENA_Pos = 0xc
	// Bit mask of USB_SERIAL_JTAG_RTS_CHG_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_RTS_CHG_INT_ENA_Msk = 0x1000
	// Bit USB_SERIAL_JTAG_RTS_CHG_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_RTS_CHG_INT_ENA = 0x1000
	// Position of USB_SERIAL_JTAG_DTR_CHG_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_DTR_CHG_INT_ENA_Pos = 0xd
	// Bit mask of USB_SERIAL_JTAG_DTR_CHG_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_DTR_CHG_INT_ENA_Msk = 0x2000
	// Bit USB_SERIAL_JTAG_DTR_CHG_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_DTR_CHG_INT_ENA = 0x2000
	// Position of USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_Pos = 0xe
	// Bit mask of USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_Msk = 0x4000
	// Bit USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA = 0x4000
	// Position of USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_Pos = 0xf
	// Bit mask of USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA field.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_Msk = 0x8000
	// Bit USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA.
	USB_DEVICE_INT_ENA_USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA = 0x8000

	// INT_CLR: Interrupt clear status register.
	// Position of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_Msk = 0x1
	// Bit USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR = 0x1
	// Position of USB_SERIAL_JTAG_SOF_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SOF_INT_CLR_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_SOF_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SOF_INT_CLR_Msk = 0x2
	// Bit USB_SERIAL_JTAG_SOF_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SOF_INT_CLR = 0x2
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_Msk = 0x4
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR = 0x4
	// Position of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_Msk = 0x8
	// Bit USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR = 0x8
	// Position of USB_SERIAL_JTAG_PID_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_PID_ERR_INT_CLR_Pos = 0x4
	// Bit mask of USB_SERIAL_JTAG_PID_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_PID_ERR_INT_CLR_Msk = 0x10
	// Bit USB_SERIAL_JTAG_PID_ERR_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_PID_ERR_INT_CLR = 0x10
	// Position of USB_SERIAL_JTAG_CRC5_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_Pos = 0x5
	// Bit mask of USB_SERIAL_JTAG_CRC5_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_Msk = 0x20
	// Bit USB_SERIAL_JTAG_CRC5_ERR_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_CRC5_ERR_INT_CLR = 0x20
	// Position of USB_SERIAL_JTAG_CRC16_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_Pos = 0x6
	// Bit mask of USB_SERIAL_JTAG_CRC16_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_Msk = 0x40
	// Bit USB_SERIAL_JTAG_CRC16_ERR_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_CRC16_ERR_INT_CLR = 0x40
	// Position of USB_SERIAL_JTAG_STUFF_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_Pos = 0x7
	// Bit mask of USB_SERIAL_JTAG_STUFF_ERR_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_Msk = 0x80
	// Bit USB_SERIAL_JTAG_STUFF_ERR_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_STUFF_ERR_INT_CLR = 0x80
	// Position of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_Msk = 0x100
	// Bit USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR = 0x100
	// Position of USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_Msk = 0x200
	// Bit USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR = 0x200
	// Position of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Pos = 0xa
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_Msk = 0x400
	// Bit USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR = 0x400
	// Position of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Pos = 0xb
	// Bit mask of USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_Msk = 0x800
	// Bit USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR = 0x800
	// Position of USB_SERIAL_JTAG_RTS_CHG_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_RTS_CHG_INT_CLR_Pos = 0xc
	// Bit mask of USB_SERIAL_JTAG_RTS_CHG_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_RTS_CHG_INT_CLR_Msk = 0x1000
	// Bit USB_SERIAL_JTAG_RTS_CHG_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_RTS_CHG_INT_CLR = 0x1000
	// Position of USB_SERIAL_JTAG_DTR_CHG_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_DTR_CHG_INT_CLR_Pos = 0xd
	// Bit mask of USB_SERIAL_JTAG_DTR_CHG_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_DTR_CHG_INT_CLR_Msk = 0x2000
	// Bit USB_SERIAL_JTAG_DTR_CHG_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_DTR_CHG_INT_CLR = 0x2000
	// Position of USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_Pos = 0xe
	// Bit mask of USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_Msk = 0x4000
	// Bit USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR = 0x4000
	// Position of USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_Pos = 0xf
	// Bit mask of USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR field.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_Msk = 0x8000
	// Bit USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR.
	USB_DEVICE_INT_CLR_USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR = 0x8000

	// CONF0: PHY hardware configuration.
	// Position of USB_SERIAL_JTAG_PHY_SEL field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PHY_SEL_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_PHY_SEL field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PHY_SEL_Msk = 0x1
	// Bit USB_SERIAL_JTAG_PHY_SEL.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PHY_SEL = 0x1
	// Position of USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_Msk = 0x2
	// Bit USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE = 0x2
	// Position of USB_SERIAL_JTAG_EXCHG_PINS field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_EXCHG_PINS_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_EXCHG_PINS field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_EXCHG_PINS_Msk = 0x4
	// Bit USB_SERIAL_JTAG_EXCHG_PINS.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_EXCHG_PINS = 0x4
	// Position of USB_SERIAL_JTAG_VREFH field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_VREFH_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_VREFH field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_VREFH_Msk = 0x18
	// Position of USB_SERIAL_JTAG_VREFL field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_VREFL_Pos = 0x5
	// Bit mask of USB_SERIAL_JTAG_VREFL field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_VREFL_Msk = 0x60
	// Position of USB_SERIAL_JTAG_VREF_OVERRIDE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_VREF_OVERRIDE_Pos = 0x7
	// Bit mask of USB_SERIAL_JTAG_VREF_OVERRIDE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_VREF_OVERRIDE_Msk = 0x80
	// Bit USB_SERIAL_JTAG_VREF_OVERRIDE.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_VREF_OVERRIDE = 0x80
	// Position of USB_SERIAL_JTAG_PAD_PULL_OVERRIDE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_PAD_PULL_OVERRIDE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_Msk = 0x100
	// Bit USB_SERIAL_JTAG_PAD_PULL_OVERRIDE.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PAD_PULL_OVERRIDE = 0x100
	// Position of USB_SERIAL_JTAG_DP_PULLUP field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DP_PULLUP_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_DP_PULLUP field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DP_PULLUP_Msk = 0x200
	// Bit USB_SERIAL_JTAG_DP_PULLUP.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DP_PULLUP = 0x200
	// Position of USB_SERIAL_JTAG_DP_PULLDOWN field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DP_PULLDOWN_Pos = 0xa
	// Bit mask of USB_SERIAL_JTAG_DP_PULLDOWN field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DP_PULLDOWN_Msk = 0x400
	// Bit USB_SERIAL_JTAG_DP_PULLDOWN.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DP_PULLDOWN = 0x400
	// Position of USB_SERIAL_JTAG_DM_PULLUP field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DM_PULLUP_Pos = 0xb
	// Bit mask of USB_SERIAL_JTAG_DM_PULLUP field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DM_PULLUP_Msk = 0x800
	// Bit USB_SERIAL_JTAG_DM_PULLUP.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DM_PULLUP = 0x800
	// Position of USB_SERIAL_JTAG_DM_PULLDOWN field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DM_PULLDOWN_Pos = 0xc
	// Bit mask of USB_SERIAL_JTAG_DM_PULLDOWN field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DM_PULLDOWN_Msk = 0x1000
	// Bit USB_SERIAL_JTAG_DM_PULLDOWN.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_DM_PULLDOWN = 0x1000
	// Position of USB_SERIAL_JTAG_PULLUP_VALUE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PULLUP_VALUE_Pos = 0xd
	// Bit mask of USB_SERIAL_JTAG_PULLUP_VALUE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PULLUP_VALUE_Msk = 0x2000
	// Bit USB_SERIAL_JTAG_PULLUP_VALUE.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_PULLUP_VALUE = 0x2000
	// Position of USB_SERIAL_JTAG_USB_PAD_ENABLE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_USB_PAD_ENABLE_Pos = 0xe
	// Bit mask of USB_SERIAL_JTAG_USB_PAD_ENABLE field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_USB_PAD_ENABLE_Msk = 0x4000
	// Bit USB_SERIAL_JTAG_USB_PAD_ENABLE.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_USB_PAD_ENABLE = 0x4000
	// Position of USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_Pos = 0xf
	// Bit mask of USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN field.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_Msk = 0x8000
	// Bit USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN.
	USB_DEVICE_CONF0_USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN = 0x8000

	// TEST: Registers used for debugging the PHY.
	// Position of USB_SERIAL_JTAG_TEST_ENABLE field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_ENABLE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_TEST_ENABLE field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_ENABLE_Msk = 0x1
	// Bit USB_SERIAL_JTAG_TEST_ENABLE.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_ENABLE = 0x1
	// Position of USB_SERIAL_JTAG_TEST_USB_OE field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_USB_OE_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_TEST_USB_OE field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_USB_OE_Msk = 0x2
	// Bit USB_SERIAL_JTAG_TEST_USB_OE.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_USB_OE = 0x2
	// Position of USB_SERIAL_JTAG_TEST_TX_DP field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_TX_DP_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_TEST_TX_DP field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_TX_DP_Msk = 0x4
	// Bit USB_SERIAL_JTAG_TEST_TX_DP.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_TX_DP = 0x4
	// Position of USB_SERIAL_JTAG_TEST_TX_DM field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_TX_DM_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_TEST_TX_DM field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_TX_DM_Msk = 0x8
	// Bit USB_SERIAL_JTAG_TEST_TX_DM.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_TX_DM = 0x8
	// Position of USB_SERIAL_JTAG_TEST_RX_RCV field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_RCV_Pos = 0x4
	// Bit mask of USB_SERIAL_JTAG_TEST_RX_RCV field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_RCV_Msk = 0x10
	// Bit USB_SERIAL_JTAG_TEST_RX_RCV.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_RCV = 0x10
	// Position of USB_SERIAL_JTAG_TEST_RX_DP field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_DP_Pos = 0x5
	// Bit mask of USB_SERIAL_JTAG_TEST_RX_DP field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_DP_Msk = 0x20
	// Bit USB_SERIAL_JTAG_TEST_RX_DP.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_DP = 0x20
	// Position of USB_SERIAL_JTAG_TEST_RX_DM field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_DM_Pos = 0x6
	// Bit mask of USB_SERIAL_JTAG_TEST_RX_DM field.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_DM_Msk = 0x40
	// Bit USB_SERIAL_JTAG_TEST_RX_DM.
	USB_DEVICE_TEST_USB_SERIAL_JTAG_TEST_RX_DM = 0x40

	// JFIFO_ST: JTAG FIFO status and control registers.
	// Position of USB_SERIAL_JTAG_IN_FIFO_CNT field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_CNT_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_IN_FIFO_CNT field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_CNT_Msk = 0x3
	// Position of USB_SERIAL_JTAG_IN_FIFO_EMPTY field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_EMPTY_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_IN_FIFO_EMPTY field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_EMPTY_Msk = 0x4
	// Bit USB_SERIAL_JTAG_IN_FIFO_EMPTY.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_EMPTY = 0x4
	// Position of USB_SERIAL_JTAG_IN_FIFO_FULL field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_FULL_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_IN_FIFO_FULL field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_FULL_Msk = 0x8
	// Bit USB_SERIAL_JTAG_IN_FIFO_FULL.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_FULL = 0x8
	// Position of USB_SERIAL_JTAG_OUT_FIFO_CNT field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_CNT_Pos = 0x4
	// Bit mask of USB_SERIAL_JTAG_OUT_FIFO_CNT field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_CNT_Msk = 0x30
	// Position of USB_SERIAL_JTAG_OUT_FIFO_EMPTY field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_EMPTY_Pos = 0x6
	// Bit mask of USB_SERIAL_JTAG_OUT_FIFO_EMPTY field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_EMPTY_Msk = 0x40
	// Bit USB_SERIAL_JTAG_OUT_FIFO_EMPTY.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_EMPTY = 0x40
	// Position of USB_SERIAL_JTAG_OUT_FIFO_FULL field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_FULL_Pos = 0x7
	// Bit mask of USB_SERIAL_JTAG_OUT_FIFO_FULL field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_FULL_Msk = 0x80
	// Bit USB_SERIAL_JTAG_OUT_FIFO_FULL.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_FULL = 0x80
	// Position of USB_SERIAL_JTAG_IN_FIFO_RESET field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_RESET_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_IN_FIFO_RESET field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_RESET_Msk = 0x100
	// Bit USB_SERIAL_JTAG_IN_FIFO_RESET.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_IN_FIFO_RESET = 0x100
	// Position of USB_SERIAL_JTAG_OUT_FIFO_RESET field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_RESET_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_OUT_FIFO_RESET field.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_RESET_Msk = 0x200
	// Bit USB_SERIAL_JTAG_OUT_FIFO_RESET.
	USB_DEVICE_JFIFO_ST_USB_SERIAL_JTAG_OUT_FIFO_RESET = 0x200

	// FRAM_NUM: Last received SOF frame index register.
	// Position of USB_SERIAL_JTAG_SOF_FRAME_INDEX field.
	USB_DEVICE_FRAM_NUM_USB_SERIAL_JTAG_SOF_FRAME_INDEX_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_SOF_FRAME_INDEX field.
	USB_DEVICE_FRAM_NUM_USB_SERIAL_JTAG_SOF_FRAME_INDEX_Msk = 0x7ff

	// IN_EP0_ST: Control IN endpoint status information.
	// Position of USB_SERIAL_JTAG_IN_EP0_STATE field.
	USB_DEVICE_IN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_STATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_IN_EP0_STATE field.
	USB_DEVICE_IN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_STATE_Msk = 0x3
	// Position of USB_SERIAL_JTAG_IN_EP0_WR_ADDR field.
	USB_DEVICE_IN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_WR_ADDR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_IN_EP0_WR_ADDR field.
	USB_DEVICE_IN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_WR_ADDR_Msk = 0x1fc
	// Position of USB_SERIAL_JTAG_IN_EP0_RD_ADDR field.
	USB_DEVICE_IN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_RD_ADDR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_IN_EP0_RD_ADDR field.
	USB_DEVICE_IN_EP0_ST_USB_SERIAL_JTAG_IN_EP0_RD_ADDR_Msk = 0xfe00

	// IN_EP1_ST: CDC-ACM IN endpoint status information.
	// Position of USB_SERIAL_JTAG_IN_EP1_STATE field.
	USB_DEVICE_IN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_STATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_IN_EP1_STATE field.
	USB_DEVICE_IN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_STATE_Msk = 0x3
	// Position of USB_SERIAL_JTAG_IN_EP1_WR_ADDR field.
	USB_DEVICE_IN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_WR_ADDR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_IN_EP1_WR_ADDR field.
	USB_DEVICE_IN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_WR_ADDR_Msk = 0x1fc
	// Position of USB_SERIAL_JTAG_IN_EP1_RD_ADDR field.
	USB_DEVICE_IN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_RD_ADDR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_IN_EP1_RD_ADDR field.
	USB_DEVICE_IN_EP1_ST_USB_SERIAL_JTAG_IN_EP1_RD_ADDR_Msk = 0xfe00

	// IN_EP2_ST: CDC-ACM interrupt IN endpoint status information.
	// Position of USB_SERIAL_JTAG_IN_EP2_STATE field.
	USB_DEVICE_IN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_STATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_IN_EP2_STATE field.
	USB_DEVICE_IN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_STATE_Msk = 0x3
	// Position of USB_SERIAL_JTAG_IN_EP2_WR_ADDR field.
	USB_DEVICE_IN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_WR_ADDR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_IN_EP2_WR_ADDR field.
	USB_DEVICE_IN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_WR_ADDR_Msk = 0x1fc
	// Position of USB_SERIAL_JTAG_IN_EP2_RD_ADDR field.
	USB_DEVICE_IN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_RD_ADDR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_IN_EP2_RD_ADDR field.
	USB_DEVICE_IN_EP2_ST_USB_SERIAL_JTAG_IN_EP2_RD_ADDR_Msk = 0xfe00

	// IN_EP3_ST: JTAG IN endpoint status information.
	// Position of USB_SERIAL_JTAG_IN_EP3_STATE field.
	USB_DEVICE_IN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_STATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_IN_EP3_STATE field.
	USB_DEVICE_IN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_STATE_Msk = 0x3
	// Position of USB_SERIAL_JTAG_IN_EP3_WR_ADDR field.
	USB_DEVICE_IN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_WR_ADDR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_IN_EP3_WR_ADDR field.
	USB_DEVICE_IN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_WR_ADDR_Msk = 0x1fc
	// Position of USB_SERIAL_JTAG_IN_EP3_RD_ADDR field.
	USB_DEVICE_IN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_RD_ADDR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_IN_EP3_RD_ADDR field.
	USB_DEVICE_IN_EP3_ST_USB_SERIAL_JTAG_IN_EP3_RD_ADDR_Msk = 0xfe00

	// OUT_EP0_ST: Control OUT endpoint status information.
	// Position of USB_SERIAL_JTAG_OUT_EP0_STATE field.
	USB_DEVICE_OUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_STATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_OUT_EP0_STATE field.
	USB_DEVICE_OUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_STATE_Msk = 0x3
	// Position of USB_SERIAL_JTAG_OUT_EP0_WR_ADDR field.
	USB_DEVICE_OUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_OUT_EP0_WR_ADDR field.
	USB_DEVICE_OUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_Msk = 0x1fc
	// Position of USB_SERIAL_JTAG_OUT_EP0_RD_ADDR field.
	USB_DEVICE_OUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_OUT_EP0_RD_ADDR field.
	USB_DEVICE_OUT_EP0_ST_USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_Msk = 0xfe00

	// OUT_EP1_ST: CDC-ACM OUT endpoint status information.
	// Position of USB_SERIAL_JTAG_OUT_EP1_STATE field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_STATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_STATE field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_STATE_Msk = 0x3
	// Position of USB_SERIAL_JTAG_OUT_EP1_WR_ADDR field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_WR_ADDR field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_Msk = 0x1fc
	// Position of USB_SERIAL_JTAG_OUT_EP1_RD_ADDR field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_RD_ADDR field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_Msk = 0xfe00
	// Position of USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_Pos = 0x10
	// Bit mask of USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT field.
	USB_DEVICE_OUT_EP1_ST_USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_Msk = 0x7f0000

	// OUT_EP2_ST: JTAG OUT endpoint status information.
	// Position of USB_SERIAL_JTAG_OUT_EP2_STATE field.
	USB_DEVICE_OUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_STATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_OUT_EP2_STATE field.
	USB_DEVICE_OUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_STATE_Msk = 0x3
	// Position of USB_SERIAL_JTAG_OUT_EP2_WR_ADDR field.
	USB_DEVICE_OUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_OUT_EP2_WR_ADDR field.
	USB_DEVICE_OUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_Msk = 0x1fc
	// Position of USB_SERIAL_JTAG_OUT_EP2_RD_ADDR field.
	USB_DEVICE_OUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_Pos = 0x9
	// Bit mask of USB_SERIAL_JTAG_OUT_EP2_RD_ADDR field.
	USB_DEVICE_OUT_EP2_ST_USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_Msk = 0xfe00

	// MISC_CONF: Clock enable control
	// Position of USB_SERIAL_JTAG_CLK_EN field.
	USB_DEVICE_MISC_CONF_USB_SERIAL_JTAG_CLK_EN_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_CLK_EN field.
	USB_DEVICE_MISC_CONF_USB_SERIAL_JTAG_CLK_EN_Msk = 0x1
	// Bit USB_SERIAL_JTAG_CLK_EN.
	USB_DEVICE_MISC_CONF_USB_SERIAL_JTAG_CLK_EN = 0x1

	// MEM_CONF: Memory power control
	// Position of USB_SERIAL_JTAG_USB_MEM_PD field.
	USB_DEVICE_MEM_CONF_USB_SERIAL_JTAG_USB_MEM_PD_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_USB_MEM_PD field.
	USB_DEVICE_MEM_CONF_USB_SERIAL_JTAG_USB_MEM_PD_Msk = 0x1
	// Bit USB_SERIAL_JTAG_USB_MEM_PD.
	USB_DEVICE_MEM_CONF_USB_SERIAL_JTAG_USB_MEM_PD = 0x1
	// Position of USB_SERIAL_JTAG_USB_MEM_CLK_EN field.
	USB_DEVICE_MEM_CONF_USB_SERIAL_JTAG_USB_MEM_CLK_EN_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_USB_MEM_CLK_EN field.
	USB_DEVICE_MEM_CONF_USB_SERIAL_JTAG_USB_MEM_CLK_EN_Msk = 0x2
	// Bit USB_SERIAL_JTAG_USB_MEM_CLK_EN.
	USB_DEVICE_MEM_CONF_USB_SERIAL_JTAG_USB_MEM_CLK_EN = 0x2

	// CHIP_RST: CDC-ACM chip reset control.
	// Position of USB_SERIAL_JTAG_RTS field.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_RTS_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RTS field.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_RTS_Msk = 0x1
	// Bit USB_SERIAL_JTAG_RTS.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_RTS = 0x1
	// Position of USB_SERIAL_JTAG_DTR field.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_DTR_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_DTR field.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_DTR_Msk = 0x2
	// Bit USB_SERIAL_JTAG_DTR.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_DTR = 0x2
	// Position of USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS field.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS field.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_Msk = 0x4
	// Bit USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS.
	USB_DEVICE_CHIP_RST_USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS = 0x4

	// SET_LINE_CODE_W0: W0 of SET_LINE_CODING command.
	// Position of USB_SERIAL_JTAG_DW_DTE_RATE field.
	USB_DEVICE_SET_LINE_CODE_W0_USB_SERIAL_JTAG_DW_DTE_RATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_DW_DTE_RATE field.
	USB_DEVICE_SET_LINE_CODE_W0_USB_SERIAL_JTAG_DW_DTE_RATE_Msk = 0xffffffff

	// SET_LINE_CODE_W1: W1 of SET_LINE_CODING command.
	// Position of USB_SERIAL_JTAG_BCHAR_FORMAT field.
	USB_DEVICE_SET_LINE_CODE_W1_USB_SERIAL_JTAG_BCHAR_FORMAT_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_BCHAR_FORMAT field.
	USB_DEVICE_SET_LINE_CODE_W1_USB_SERIAL_JTAG_BCHAR_FORMAT_Msk = 0xff
	// Position of USB_SERIAL_JTAG_BPARITY_TYPE field.
	USB_DEVICE_SET_LINE_CODE_W1_USB_SERIAL_JTAG_BPARITY_TYPE_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_BPARITY_TYPE field.
	USB_DEVICE_SET_LINE_CODE_W1_USB_SERIAL_JTAG_BPARITY_TYPE_Msk = 0xff00
	// Position of USB_SERIAL_JTAG_BDATA_BITS field.
	USB_DEVICE_SET_LINE_CODE_W1_USB_SERIAL_JTAG_BDATA_BITS_Pos = 0x10
	// Bit mask of USB_SERIAL_JTAG_BDATA_BITS field.
	USB_DEVICE_SET_LINE_CODE_W1_USB_SERIAL_JTAG_BDATA_BITS_Msk = 0xff0000

	// GET_LINE_CODE_W0: W0 of GET_LINE_CODING command.
	// Position of USB_SERIAL_JTAG_GET_DW_DTE_RATE field.
	USB_DEVICE_GET_LINE_CODE_W0_USB_SERIAL_JTAG_GET_DW_DTE_RATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_GET_DW_DTE_RATE field.
	USB_DEVICE_GET_LINE_CODE_W0_USB_SERIAL_JTAG_GET_DW_DTE_RATE_Msk = 0xffffffff

	// GET_LINE_CODE_W1: W1 of GET_LINE_CODING command.
	// Position of USB_SERIAL_JTAG_GET_BDATA_BITS field.
	USB_DEVICE_GET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BDATA_BITS_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_GET_BDATA_BITS field.
	USB_DEVICE_GET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BDATA_BITS_Msk = 0xff
	// Position of USB_SERIAL_JTAG_GET_BPARITY_TYPE field.
	USB_DEVICE_GET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BPARITY_TYPE_Pos = 0x8
	// Bit mask of USB_SERIAL_JTAG_GET_BPARITY_TYPE field.
	USB_DEVICE_GET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BPARITY_TYPE_Msk = 0xff00
	// Position of USB_SERIAL_JTAG_GET_BCHAR_FORMAT field.
	USB_DEVICE_GET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BCHAR_FORMAT_Pos = 0x10
	// Bit mask of USB_SERIAL_JTAG_GET_BCHAR_FORMAT field.
	USB_DEVICE_GET_LINE_CODE_W1_USB_SERIAL_JTAG_GET_BCHAR_FORMAT_Msk = 0xff0000

	// CONFIG_UPDATE: Configuration registers' value update
	// Position of USB_SERIAL_JTAG_CONFIG_UPDATE field.
	USB_DEVICE_CONFIG_UPDATE_USB_SERIAL_JTAG_CONFIG_UPDATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_CONFIG_UPDATE field.
	USB_DEVICE_CONFIG_UPDATE_USB_SERIAL_JTAG_CONFIG_UPDATE_Msk = 0x1
	// Bit USB_SERIAL_JTAG_CONFIG_UPDATE.
	USB_DEVICE_CONFIG_UPDATE_USB_SERIAL_JTAG_CONFIG_UPDATE = 0x1

	// SER_AFIFO_CONFIG: Serial AFIFO configure register
	// Position of USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_Msk = 0x1
	// Bit USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR = 0x1
	// Position of USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_Msk = 0x2
	// Bit USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD = 0x2
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_Pos = 0x2
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_Msk = 0x4
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR = 0x4
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_Pos = 0x3
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_Msk = 0x8
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD = 0x8
	// Position of USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_Pos = 0x4
	// Bit mask of USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_Msk = 0x10
	// Bit USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY = 0x10
	// Position of USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_Pos = 0x5
	// Bit mask of USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL field.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_Msk = 0x20
	// Bit USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL.
	USB_DEVICE_SER_AFIFO_CONFIG_USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL = 0x20

	// BUS_RESET_ST: USB Bus reset status register
	// Position of USB_SERIAL_JTAG_USB_BUS_RESET_ST field.
	USB_DEVICE_BUS_RESET_ST_USB_SERIAL_JTAG_USB_BUS_RESET_ST_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_USB_BUS_RESET_ST field.
	USB_DEVICE_BUS_RESET_ST_USB_SERIAL_JTAG_USB_BUS_RESET_ST_Msk = 0x1
	// Bit USB_SERIAL_JTAG_USB_BUS_RESET_ST.
	USB_DEVICE_BUS_RESET_ST_USB_SERIAL_JTAG_USB_BUS_RESET_ST = 0x1

	// ECO_LOW_48: Reserved.
	// Position of USB_SERIAL_JTAG_RND_ECO_LOW_48 field.
	USB_DEVICE_ECO_LOW_48_USB_SERIAL_JTAG_RND_ECO_LOW_48_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RND_ECO_LOW_48 field.
	USB_DEVICE_ECO_LOW_48_USB_SERIAL_JTAG_RND_ECO_LOW_48_Msk = 0xffffffff

	// ECO_HIGH_48: Reserved.
	// Position of USB_SERIAL_JTAG_RND_ECO_HIGH_48 field.
	USB_DEVICE_ECO_HIGH_48_USB_SERIAL_JTAG_RND_ECO_HIGH_48_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RND_ECO_HIGH_48 field.
	USB_DEVICE_ECO_HIGH_48_USB_SERIAL_JTAG_RND_ECO_HIGH_48_Msk = 0xffffffff

	// ECO_CELL_CTRL_48: Reserved.
	// Position of USB_SERIAL_JTAG_RDN_RESULT_48 field.
	USB_DEVICE_ECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_RESULT_48_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RDN_RESULT_48 field.
	USB_DEVICE_ECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_RESULT_48_Msk = 0x1
	// Bit USB_SERIAL_JTAG_RDN_RESULT_48.
	USB_DEVICE_ECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_RESULT_48 = 0x1
	// Position of USB_SERIAL_JTAG_RDN_ENA_48 field.
	USB_DEVICE_ECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_ENA_48_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_RDN_ENA_48 field.
	USB_DEVICE_ECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_ENA_48_Msk = 0x2
	// Bit USB_SERIAL_JTAG_RDN_ENA_48.
	USB_DEVICE_ECO_CELL_CTRL_48_USB_SERIAL_JTAG_RDN_ENA_48 = 0x2

	// ECO_LOW_APB: Reserved.
	// Position of USB_SERIAL_JTAG_RND_ECO_LOW_APB field.
	USB_DEVICE_ECO_LOW_APB_USB_SERIAL_JTAG_RND_ECO_LOW_APB_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RND_ECO_LOW_APB field.
	USB_DEVICE_ECO_LOW_APB_USB_SERIAL_JTAG_RND_ECO_LOW_APB_Msk = 0xffffffff

	// ECO_HIGH_APB: Reserved.
	// Position of USB_SERIAL_JTAG_RND_ECO_HIGH_APB field.
	USB_DEVICE_ECO_HIGH_APB_USB_SERIAL_JTAG_RND_ECO_HIGH_APB_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RND_ECO_HIGH_APB field.
	USB_DEVICE_ECO_HIGH_APB_USB_SERIAL_JTAG_RND_ECO_HIGH_APB_Msk = 0xffffffff

	// ECO_CELL_CTRL_APB: Reserved.
	// Position of USB_SERIAL_JTAG_RDN_RESULT_APB field.
	USB_DEVICE_ECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_RESULT_APB_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_RDN_RESULT_APB field.
	USB_DEVICE_ECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_RESULT_APB_Msk = 0x1
	// Bit USB_SERIAL_JTAG_RDN_RESULT_APB.
	USB_DEVICE_ECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_RESULT_APB = 0x1
	// Position of USB_SERIAL_JTAG_RDN_ENA_APB field.
	USB_DEVICE_ECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_ENA_APB_Pos = 0x1
	// Bit mask of USB_SERIAL_JTAG_RDN_ENA_APB field.
	USB_DEVICE_ECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_ENA_APB_Msk = 0x2
	// Bit USB_SERIAL_JTAG_RDN_ENA_APB.
	USB_DEVICE_ECO_CELL_CTRL_APB_USB_SERIAL_JTAG_RDN_ENA_APB = 0x2

	// SRAM_CTRL: PPA SRAM Control Register
	// Position of USB_SERIAL_JTAG_MEM_AUX_CTRL field.
	USB_DEVICE_SRAM_CTRL_USB_SERIAL_JTAG_MEM_AUX_CTRL_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_MEM_AUX_CTRL field.
	USB_DEVICE_SRAM_CTRL_USB_SERIAL_JTAG_MEM_AUX_CTRL_Msk = 0x3fff

	// DATE: Date register
	// Position of USB_SERIAL_JTAG_DATE field.
	USB_DEVICE_DATE_USB_SERIAL_JTAG_DATE_Pos = 0x0
	// Bit mask of USB_SERIAL_JTAG_DATE field.
	USB_DEVICE_DATE_USB_SERIAL_JTAG_DATE_Msk = 0xffffffff
)

// Constants for USB_WRAP: USB_WRAP Peripheral
const (
	// OTG_CONF: USB wrapper configuration registers.
	// Position of SRP_SESSEND_OVERRIDE field.
	USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE_Pos = 0x0
	// Bit mask of SRP_SESSEND_OVERRIDE field.
	USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE_Msk = 0x1
	// Bit SRP_SESSEND_OVERRIDE.
	USB_WRAP_OTG_CONF_SRP_SESSEND_OVERRIDE = 0x1
	// Position of SRP_SESSEND_VALUE field.
	USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE_Pos = 0x1
	// Bit mask of SRP_SESSEND_VALUE field.
	USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE_Msk = 0x2
	// Bit SRP_SESSEND_VALUE.
	USB_WRAP_OTG_CONF_SRP_SESSEND_VALUE = 0x2
	// Position of PHY_SEL field.
	USB_WRAP_OTG_CONF_PHY_SEL_Pos = 0x2
	// Bit mask of PHY_SEL field.
	USB_WRAP_OTG_CONF_PHY_SEL_Msk = 0x4
	// Bit PHY_SEL.
	USB_WRAP_OTG_CONF_PHY_SEL = 0x4
	// Position of DFIFO_FORCE_PD field.
	USB_WRAP_OTG_CONF_DFIFO_FORCE_PD_Pos = 0x3
	// Bit mask of DFIFO_FORCE_PD field.
	USB_WRAP_OTG_CONF_DFIFO_FORCE_PD_Msk = 0x8
	// Bit DFIFO_FORCE_PD.
	USB_WRAP_OTG_CONF_DFIFO_FORCE_PD = 0x8
	// Position of DBNCE_FLTR_BYPASS field.
	USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS_Pos = 0x4
	// Bit mask of DBNCE_FLTR_BYPASS field.
	USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS_Msk = 0x10
	// Bit DBNCE_FLTR_BYPASS.
	USB_WRAP_OTG_CONF_DBNCE_FLTR_BYPASS = 0x10
	// Position of EXCHG_PINS_OVERRIDE field.
	USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE_Pos = 0x5
	// Bit mask of EXCHG_PINS_OVERRIDE field.
	USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE_Msk = 0x20
	// Bit EXCHG_PINS_OVERRIDE.
	USB_WRAP_OTG_CONF_EXCHG_PINS_OVERRIDE = 0x20
	// Position of EXCHG_PINS field.
	USB_WRAP_OTG_CONF_EXCHG_PINS_Pos = 0x6
	// Bit mask of EXCHG_PINS field.
	USB_WRAP_OTG_CONF_EXCHG_PINS_Msk = 0x40
	// Bit EXCHG_PINS.
	USB_WRAP_OTG_CONF_EXCHG_PINS = 0x40
	// Position of VREFH field.
	USB_WRAP_OTG_CONF_VREFH_Pos = 0x7
	// Bit mask of VREFH field.
	USB_WRAP_OTG_CONF_VREFH_Msk = 0x180
	// Position of VREFL field.
	USB_WRAP_OTG_CONF_VREFL_Pos = 0x9
	// Bit mask of VREFL field.
	USB_WRAP_OTG_CONF_VREFL_Msk = 0x600
	// Position of VREF_OVERRIDE field.
	USB_WRAP_OTG_CONF_VREF_OVERRIDE_Pos = 0xb
	// Bit mask of VREF_OVERRIDE field.
	USB_WRAP_OTG_CONF_VREF_OVERRIDE_Msk = 0x800
	// Bit VREF_OVERRIDE.
	USB_WRAP_OTG_CONF_VREF_OVERRIDE = 0x800
	// Position of PAD_PULL_OVERRIDE field.
	USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE_Pos = 0xc
	// Bit mask of PAD_PULL_OVERRIDE field.
	USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE_Msk = 0x1000
	// Bit PAD_PULL_OVERRIDE.
	USB_WRAP_OTG_CONF_PAD_PULL_OVERRIDE = 0x1000
	// Position of DP_PULLUP field.
	USB_WRAP_OTG_CONF_DP_PULLUP_Pos = 0xd
	// Bit mask of DP_PULLUP field.
	USB_WRAP_OTG_CONF_DP_PULLUP_Msk = 0x2000
	// Bit DP_PULLUP.
	USB_WRAP_OTG_CONF_DP_PULLUP = 0x2000
	// Position of DP_PULLDOWN field.
	USB_WRAP_OTG_CONF_DP_PULLDOWN_Pos = 0xe
	// Bit mask of DP_PULLDOWN field.
	USB_WRAP_OTG_CONF_DP_PULLDOWN_Msk = 0x4000
	// Bit DP_PULLDOWN.
	USB_WRAP_OTG_CONF_DP_PULLDOWN = 0x4000
	// Position of DM_PULLUP field.
	USB_WRAP_OTG_CONF_DM_PULLUP_Pos = 0xf
	// Bit mask of DM_PULLUP field.
	USB_WRAP_OTG_CONF_DM_PULLUP_Msk = 0x8000
	// Bit DM_PULLUP.
	USB_WRAP_OTG_CONF_DM_PULLUP = 0x8000
	// Position of DM_PULLDOWN field.
	USB_WRAP_OTG_CONF_DM_PULLDOWN_Pos = 0x10
	// Bit mask of DM_PULLDOWN field.
	USB_WRAP_OTG_CONF_DM_PULLDOWN_Msk = 0x10000
	// Bit DM_PULLDOWN.
	USB_WRAP_OTG_CONF_DM_PULLDOWN = 0x10000
	// Position of PULLUP_VALUE field.
	USB_WRAP_OTG_CONF_PULLUP_VALUE_Pos = 0x11
	// Bit mask of PULLUP_VALUE field.
	USB_WRAP_OTG_CONF_PULLUP_VALUE_Msk = 0x20000
	// Bit PULLUP_VALUE.
	USB_WRAP_OTG_CONF_PULLUP_VALUE = 0x20000
	// Position of USB_PAD_ENABLE field.
	USB_WRAP_OTG_CONF_USB_PAD_ENABLE_Pos = 0x12
	// Bit mask of USB_PAD_ENABLE field.
	USB_WRAP_OTG_CONF_USB_PAD_ENABLE_Msk = 0x40000
	// Bit USB_PAD_ENABLE.
	USB_WRAP_OTG_CONF_USB_PAD_ENABLE = 0x40000
	// Position of AHB_CLK_FORCE_ON field.
	USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON_Pos = 0x13
	// Bit mask of AHB_CLK_FORCE_ON field.
	USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON_Msk = 0x80000
	// Bit AHB_CLK_FORCE_ON.
	USB_WRAP_OTG_CONF_AHB_CLK_FORCE_ON = 0x80000
	// Position of PHY_CLK_FORCE_ON field.
	USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON_Pos = 0x14
	// Bit mask of PHY_CLK_FORCE_ON field.
	USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON_Msk = 0x100000
	// Bit PHY_CLK_FORCE_ON.
	USB_WRAP_OTG_CONF_PHY_CLK_FORCE_ON = 0x100000
	// Position of PHY_TX_EDGE_SEL field.
	USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL_Pos = 0x15
	// Bit mask of PHY_TX_EDGE_SEL field.
	USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL_Msk = 0x200000
	// Bit PHY_TX_EDGE_SEL.
	USB_WRAP_OTG_CONF_PHY_TX_EDGE_SEL = 0x200000
	// Position of DFIFO_FORCE_PU field.
	USB_WRAP_OTG_CONF_DFIFO_FORCE_PU_Pos = 0x16
	// Bit mask of DFIFO_FORCE_PU field.
	USB_WRAP_OTG_CONF_DFIFO_FORCE_PU_Msk = 0x400000
	// Bit DFIFO_FORCE_PU.
	USB_WRAP_OTG_CONF_DFIFO_FORCE_PU = 0x400000
	// Position of CLK_EN field.
	USB_WRAP_OTG_CONF_CLK_EN_Pos = 0x1f
	// Bit mask of CLK_EN field.
	USB_WRAP_OTG_CONF_CLK_EN_Msk = 0x80000000
	// Bit CLK_EN.
	USB_WRAP_OTG_CONF_CLK_EN = 0x80000000

	// TEST_CONF: USB wrapper test configuration registers.
	// Position of TEST_ENABLE field.
	USB_WRAP_TEST_CONF_TEST_ENABLE_Pos = 0x0
	// Bit mask of TEST_ENABLE field.
	USB_WRAP_TEST_CONF_TEST_ENABLE_Msk = 0x1
	// Bit TEST_ENABLE.
	USB_WRAP_TEST_CONF_TEST_ENABLE = 0x1
	// Position of TEST_USB_OE field.
	USB_WRAP_TEST_CONF_TEST_USB_OE_Pos = 0x1
	// Bit mask of TEST_USB_OE field.
	USB_WRAP_TEST_CONF_TEST_USB_OE_Msk = 0x2
	// Bit TEST_USB_OE.
	USB_WRAP_TEST_CONF_TEST_USB_OE = 0x2
	// Position of TEST_TX_DP field.
	USB_WRAP_TEST_CONF_TEST_TX_DP_Pos = 0x2
	// Bit mask of TEST_TX_DP field.
	USB_WRAP_TEST_CONF_TEST_TX_DP_Msk = 0x4
	// Bit TEST_TX_DP.
	USB_WRAP_TEST_CONF_TEST_TX_DP = 0x4
	// Position of TEST_TX_DM field.
	USB_WRAP_TEST_CONF_TEST_TX_DM_Pos = 0x3
	// Bit mask of TEST_TX_DM field.
	USB_WRAP_TEST_CONF_TEST_TX_DM_Msk = 0x8
	// Bit TEST_TX_DM.
	USB_WRAP_TEST_CONF_TEST_TX_DM = 0x8
	// Position of TEST_RX_RCV field.
	USB_WRAP_TEST_CONF_TEST_RX_RCV_Pos = 0x4
	// Bit mask of TEST_RX_RCV field.
	USB_WRAP_TEST_CONF_TEST_RX_RCV_Msk = 0x10
	// Bit TEST_RX_RCV.
	USB_WRAP_TEST_CONF_TEST_RX_RCV = 0x10
	// Position of TEST_RX_DP field.
	USB_WRAP_TEST_CONF_TEST_RX_DP_Pos = 0x5
	// Bit mask of TEST_RX_DP field.
	USB_WRAP_TEST_CONF_TEST_RX_DP_Msk = 0x20
	// Bit TEST_RX_DP.
	USB_WRAP_TEST_CONF_TEST_RX_DP = 0x20
	// Position of TEST_RX_DM field.
	USB_WRAP_TEST_CONF_TEST_RX_DM_Pos = 0x6
	// Bit mask of TEST_RX_DM field.
	USB_WRAP_TEST_CONF_TEST_RX_DM_Msk = 0x40
	// Bit TEST_RX_DM.
	USB_WRAP_TEST_CONF_TEST_RX_DM = 0x40

	// DATE: Date register.
	// Position of USB_WRAP_DATE field.
	USB_WRAP_DATE_USB_WRAP_DATE_Pos = 0x0
	// Bit mask of USB_WRAP_DATE field.
	USB_WRAP_DATE_USB_WRAP_DATE_Msk = 0xffffffff
)
